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arch: xtensa: Remove ISYNC from xtensa_compareset()

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Summary:
- According to the Xtensa ISA document, this ISYNC instruction
  between WSR SCOMPARE1 and S32C1I is unnecessary

Impact:
- SMP only

Testing:
- Tested with esp32-devkitc:wapi_smp

Signed-off-by: Masayuki Ishikawa <Masayuki.Ishikawa@jp.sony.com>
This commit is contained in:
Masayuki Ishikawa 2021-06-17 13:31:05 +09:00 committed by Xiang Xiao
parent 2d016f8d21
commit 83ac6cd399
1 changed files with 0 additions and 1 deletions
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arch/xtensa/src/common/xtensa_testset.c
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@ -57,7 +57,6 @@ static inline uint32_t xtensa_compareset(FAR volatile uint32_t *addr,
__asm__ __volatile__ __asm__ __volatile__
( (
"WSR %2, SCOMPARE1\n" /* Initialize SCOMPARE1 */ "WSR %2, SCOMPARE1\n" /* Initialize SCOMPARE1 */
"ISYNC\n" /* Wait sync */
"S32C1I %0, %1, 0\n" /* Store id into the lock, if the lock is the "S32C1I %0, %1, 0\n" /* Store id into the lock, if the lock is the
* same as comparel. Otherwise, no write-access */ * same as comparel. Otherwise, no write-access */
: "=r"(set) : "r"(addr), "r"(compare), "0"(set) : "=r"(set) : "r"(addr), "r"(compare), "0"(set)