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Squashed commit of the following:

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libc/semaphore:  Add nxsem_getvalue() which is identical to sem_getvalue() except that it never modifies the errno variable.  Changed all references to sem_getvalue in the OS to nxsem_getvalue().

    sched/semaphore:  Rename all internal private functions from sem_xyz to nxsem_xyz.  The sem_ prefix is (will be) reserved only for the application semaphore interfaces.

    libc/semaphore:  Add nxsem_init() which is identical to sem_init() except that it never modifies the errno variable.  Changed all references to sem_init in the OS to nxsem_init().

    sched/semaphore:  Rename sem_tickwait() to nxsem_tickwait() so that it is clear this is an internal OS function.

    sched/semaphoate:  Rename sem_reset() to nxsem_reset() so that it is clear this is an internal OS function.
This commit is contained in:
Gregory Nutt 2017-10-03 12:51:15 -06:00
parent 2997a49e51
commit 83cdb0c552
328 changed files with 895 additions and 792 deletions
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4
arch/arm/src/efm32/efm32_dma.c
View File

@ -274,8 +274,8 @@ void weak_function up_dmainitialize(void)
/* Initialize the channel list */
sem_init(&g_dmac.exclsem, 0, 1);
sem_init(&g_dmac.chansem, 0, EFM32_DMA_NCHANNELS);
nxsem_init(&g_dmac.exclsem, 0, 1);
nxsem_init(&g_dmac.chansem, 0, EFM32_DMA_NCHANNELS);
for (i = 0; i < EFM32_DMA_NCHANNELS; i++)
{

4
arch/arm/src/efm32/efm32_i2c.c
View File

@ -673,14 +673,14 @@ static inline void efm32_i2c_sem_post(FAR struct efm32_i2c_priv_s *priv)
static inline void efm32_i2c_sem_init(FAR struct efm32_i2c_priv_s *priv)
{
sem_init(&priv->sem_excl, 0, 1);
nxsem_init(&priv->sem_excl, 0, 1);
#ifndef CONFIG_I2C_POLLED
/* This semaphore is used for signaling and, hence, should not have
* priority inheritance enabled.
*/
sem_init(&priv->sem_isr, 0, 0);
nxsem_init(&priv->sem_isr, 0, 0);
sem_setprotocol(&priv->sem_isr, SEM_PRIO_NONE);
#endif
}

6
arch/arm/src/efm32/efm32_spi.c
View File

@ -1605,7 +1605,7 @@ static int spi_portinitialize(struct efm32_spidev_s *priv)
/* Initialize the SPI semaphore that enforces mutually exclusive access */
sem_init(&priv->exclsem, 0, 1);
nxsem_init(&priv->exclsem, 0, 1);
#ifdef CONFIG_EFM32_SPI_DMA
/* Allocate two DMA channels... one for the RX and one for the TX side of
@ -1639,8 +1639,8 @@ static int spi_portinitialize(struct efm32_spidev_s *priv)
/* Initialized semaphores used to wait for DMA completion */
(void)sem_init(&priv->rxdmasem, 0, 0);
(void)sem_init(&priv->txdmasem, 0, 0);
(void)nxsem_init(&priv->rxdmasem, 0, 0);
(void)nxsem_init(&priv->txdmasem, 0, 0);
/* These semaphores are used for signaling and, hence, should not have
* priority inheritance enabled.

6
arch/arm/src/efm32/efm32_usbhost.c
View File

@ -5155,8 +5155,8 @@ static inline void efm32_sw_initialize(FAR struct efm32_usbhost_s *priv)
/* Initialize semaphores */
sem_init(&priv->pscsem, 0, 0);
sem_init(&priv->exclsem, 0, 1);
nxsem_init(&priv->pscsem, 0, 0);
nxsem_init(&priv->exclsem, 0, 1);
/* The pscsem semaphore is used for signaling and, hence, should not have
* priority inheritance enabled.
@ -5186,7 +5186,7 @@ static inline void efm32_sw_initialize(FAR struct efm32_usbhost_s *priv)
* have priority inheritance enabled.
*/
sem_init(&chan->waitsem, 0, 0);
nxsem_init(&chan->waitsem, 0, 0);
sem_setprotocol(&chan->waitsem, SEM_PRIO_NONE);
}
}

4
arch/arm/src/imx1/imx_spi.c
View File

@ -1122,10 +1122,10 @@ FAR struct spi_dev_s *imx_spibus_initialize(int port)
* signaling and, hence, should not have priority inheritance enabled.
*/
sem_init(&priv->waitsem, 0, 0);
nxsem_init(&priv->waitsem, 0, 0);
sem_setprotocol(&priv->waitsem, SEM_PRIO_NONE);
#endif
sem_init(&priv->exclsem, 0, 1);
nxsem_init(&priv->exclsem, 0, 1);
/* Initialize control register: min frequency, ignore ready, master mode, mode=0, 8-bit */

4
arch/arm/src/imx6/imx_ecspi.c
View File

@ -1308,10 +1308,10 @@ FAR struct spi_dev_s *imx_spibus_initialize(int port)
* signaling and, hence, should not have priority inheritance enabled.
*/
sem_init(&priv->waitsem, 0, 0);
nxsem_init(&priv->waitsem, 0, 0);
sem_setprotocol(&priv->waitsem, SEM_PRIO_NONE);
#endif
sem_init(&priv->exclsem, 0, 1);
nxsem_init(&priv->exclsem, 0, 1);
/* Initialize control register: min frequency, ignore ready, master mode, mode=0, 8-bit */

4
arch/arm/src/kinetis/kinetis_i2c.c
View File

@ -316,13 +316,13 @@ static void kinetis_i2c_putreg(struct kinetis_i2cdev_s *priv, uint8_t value,
static inline void kinetis_i2c_sem_init(FAR struct kinetis_i2cdev_s *priv)
{
sem_init(&priv->mutex, 0, 1);
nxsem_init(&priv->mutex, 0, 1);
/* This semaphore is used for signaling and, hence, should not have
* priority inheritance enabled.
*/
sem_init(&priv->wait, 0, 0);
nxsem_init(&priv->wait, 0, 0);
sem_setprotocol(&priv->wait, SEM_PRIO_NONE);
}

2
arch/arm/src/kinetis/kinetis_sdhc.c
View File

@ -2807,7 +2807,7 @@ FAR struct sdio_dev_s *sdhc_initialize(int slotno)
/* Initialize the SDHC slot structure data structure */
/* Initialize semaphores */
sem_init(&priv->waitsem, 0, 0);
nxsem_init(&priv->waitsem, 0, 0);
/* The waitsem semaphore is used for signaling and, hence, should not have
* priority inheritance enabled.

2
arch/arm/src/kinetis/kinetis_spi.c
View File

@ -1234,7 +1234,7 @@ FAR struct spi_dev_s *kinetis_spibus_initialize(int port)
/* Initialize the SPI semaphore that enforces mutually exclusive access */
sem_init(&priv->exclsem, 0, 1);
nxsem_init(&priv->exclsem, 0, 1);
return &priv->spidev;
}

2
arch/arm/src/kl/kl_spi.c
View File

@ -689,7 +689,7 @@ FAR struct spi_dev_s *kl_spibus_initialize(int port)
/* Initialize the SPI semaphore that enforces mutually exclusive access */
sem_init(&priv->exclsem, 0, 1);
nxsem_init(&priv->exclsem, 0, 1);
return &priv->spidev;
}

4
arch/arm/src/lc823450/lc823450_adc.c
View File

@ -535,9 +535,9 @@ FAR struct adc_dev_s *lc823450_adcinitialize(void)
inst->nchannels = CONFIG_ADC_NCHANNELS;
inst->chanlist = lc823450_chanlist;
sem_init(&inst->sem_excl, 0, 1);
nxsem_init(&inst->sem_excl, 0, 1);
#ifndef CONFIG_ADC_POLLED
sem_init(&inst->sem_isr, 0, 0);
nxsem_init(&inst->sem_isr, 0, 0);
#endif
lc823450_adc_sem_wait(inst);

2
arch/arm/src/lc823450/lc823450_dma.c
View File

@ -344,7 +344,7 @@ void up_dmainitialize(void)
sq_init(&g_dma.phydmach[i].req_q);
}
sem_init(&g_dma.exclsem, 0, 1);
nxsem_init(&g_dma.exclsem, 0, 1);
if (irq_attach(LC823450_IRQ_DMAC, dma_interrupt, NULL) != 0)
{

4
arch/arm/src/lc823450/lc823450_i2c.c
View File

@ -1114,9 +1114,9 @@ FAR struct i2c_master_s *lc823450_i2cbus_initialize(int port)
if ((volatile int)priv->refs++ == 0)
{
sem_init(&priv->sem_excl, 0, 1);
nxsem_init(&priv->sem_excl, 0, 1);
#ifndef CONFIG_I2C_POLLED
sem_init(&priv->sem_isr, 0, 0);
nxsem_init(&priv->sem_isr, 0, 0);
#endif
(void)lc823450_i2c_init(priv, port);
}

2
arch/arm/src/lc823450/lc823450_mtd.c
View File

@ -516,7 +516,7 @@ static FAR struct mtd_dev_s *lc823450_mtd_allocdev(uint32_t channel)
return NULL;
}
sem_init(&priv->sem, 0, 1);
nxsem_init(&priv->sem, 0, 1);
priv->mtd.erase = lc823450_erase;
priv->mtd.bread = lc823450_bread;

2
arch/arm/src/lc823450/lc823450_sdc.c
View File

@ -644,7 +644,7 @@ int lc823450_sdc_locked(void)
for (i = 0; i < 2; i++)
{
(void)sem_getvalue(&_sdc_sem[i], &val);
(void)nxsem_getvalue(&_sdc_sem[i], &val);
if (1 != val)
{
ret = 1;

4
arch/arm/src/lc823450/lc823450_sddrv_dep.c
View File

@ -289,9 +289,9 @@ SINT_T sddep_os_init(struct SdDrCfg_s *cfg)
#ifdef CONFIG_LC823450_SDC_DMA
_hrdma[ch] = lc823450_dmachannel(DMA_CHANNEL_VIRTUAL);
sem_init(&_sem_rwait[ch], 0, 0);
nxsem_init(&_sem_rwait[ch], 0, 0);
_hwdma[ch] = lc823450_dmachannel(DMA_CHANNEL_VIRTUAL);
sem_init(&_sem_wwait[ch], 0, 0);
nxsem_init(&_sem_wwait[ch], 0, 0);
#endif /* CONFIG_LC823450_SDC_DMA */
return 0;
}

4
arch/arm/src/lc823450/lc823450_serial.c
View File

@ -1317,12 +1317,12 @@ void up_serialinit(void)
#ifdef TTYS1_DEV
(void)uart_register("/dev/ttyS1", &TTYS1_DEV);
#ifdef CONFIG_HSUART
sem_init(&g_uart1priv.txdma_wait, 0, 1);
nxsem_init(&g_uart1priv.txdma_wait, 0, 1);
g_uart1priv.htxdma = lc823450_dmachannel(DMA_CHANNEL_UART1TX);
lc823450_dmarequest(g_uart1priv.htxdma, DMA_REQUEST_UART1TX);
sem_init(&g_uart1priv.rxdma_wait, 0, 0);
nxsem_init(&g_uart1priv.rxdma_wait, 0, 0);
g_uart1priv.hrxdma = lc823450_dmachannel(DMA_CHANNEL_UART1RX);
lc823450_dmarequest(g_uart1priv.hrxdma, DMA_REQUEST_UART1RX);

4
arch/arm/src/lc823450/lc823450_spi.c
View File

@ -537,7 +537,7 @@ FAR struct spi_dev_s *lc823450_spibus_initialize(int port)
modifyreg32(MRSTCNTAPB, 0, MRSTCNTAPB_PORT5_RSTB);
#ifndef CONFIG_SPI_OWNBUS
sem_init(&priv->exclsem, 0, 1);
nxsem_init(&priv->exclsem, 0, 1);
#endif
/* Initialize SPI mode. It must be done before starting SPI transfer */
@ -556,7 +556,7 @@ FAR struct spi_dev_s *lc823450_spibus_initialize(int port)
lc823450_spiinitialize();
#ifdef CONFIG_LC823450_SPI_DMA
sem_init(&priv->dma_wait, 0, 0);
nxsem_init(&priv->dma_wait, 0, 0);
priv->hdma = lc823450_dmachannel(DMA_CHANNEL_SIOTX);
lc823450_dmarequest(priv->hdma, DMA_REQUEST_SIOTX);

2
arch/arm/src/lc823450/lc823450_timerisr.c
View File

@ -387,7 +387,7 @@ int up_hrttimer_usleep(unsigned int usec)
{
struct hrt_s hrt;
sem_init(&hrt.sem, 0, 0);
nxsem_init(&hrt.sem, 0, 0);
hrt.usec = usec;
hrt_usleep_add(&hrt);

6
arch/arm/src/lc823450/lc823450_usbdev.c
View File

@ -1430,7 +1430,7 @@ void up_usbinitialize(void)
return;
}
sem_init(&dma_wait, 0, 0);
nxsem_init(&dma_wait, 0, 0);
hdma = lc823450_dmachannel(DMA_CHANNEL_USBDEV);
lc823450_dmarequest(hdma, DMA_REQUEST_USBDEV);
@ -1697,7 +1697,7 @@ void usbdev_msc_read_enter()
privep->epcmd &= ~USB_EPCMD_EMPTY_EN;
epcmd_write(CONFIG_USBMSC_EPBULKIN, (privep->epcmd));
lc823450_dmareauest_dir(hdma, DMA_REQUEST_USBDEV, 1);
sem_init(&dma_wait, 0, 0);
nxsem_init(&dma_wait, 0, 0);
}
/****************************************************************************
@ -1800,7 +1800,7 @@ void usbdev_msc_write_enter0(void)
privep->epcmd &= ~USB_EPCMD_READY_EN;
epcmd_write(CONFIG_USBMSC_EPBULKOUT, (privep->epcmd));
lc823450_dmareauest_dir(hdma, DMA_REQUEST_USBDEV, 0);
sem_init(&dma_wait, 0, 0);
nxsem_init(&dma_wait, 0, 0);
}
/****************************************************************************

4
arch/arm/src/lpc11xx/lpc11_i2c.c
View File

@ -564,8 +564,8 @@ struct i2c_master_s *lpc11_i2cbus_initialize(int port)
/* Initialize semaphores */
sem_init(&priv->mutex, 0, 1);
sem_init(&priv->wait, 0, 0);
nxsem_init(&priv->mutex, 0, 1);
nxsem_init(&priv->wait, 0, 0);
/* The wait semaphore is used for signaling and, hence, should not have
* priority inheritance enabled.

2
arch/arm/src/lpc11xx/lpc11_spi.c
View File

@ -579,7 +579,7 @@ FAR struct spi_dev_s *lpc11_spibus_initialize(int port)
/* Initialize the SPI semaphore that enforces mutually exclusive access */
sem_init(&priv->exclsem, 0, 1);
nxsem_init(&priv->exclsem, 0, 1);
return &priv->spidev;
}

2
arch/arm/src/lpc11xx/lpc11_ssp.c
View File

@ -993,7 +993,7 @@ FAR struct spi_dev_s *lpc11_sspbus_initialize(int port)
/* Initialize the SPI semaphore that enforces mutually exclusive access */
sem_init(&priv->exclsem, 0, 1);
nxsem_init(&priv->exclsem, 0, 1);
/* Enable the SPI */

2
arch/arm/src/lpc17xx/lpc17_gpdma.c
View File

@ -305,7 +305,7 @@ void weak_function up_dmainitialize(void)
/* Initialize the DMA state structure */
sem_init(&g_gpdma.exclsem, 0, 1);
nxsem_init(&g_gpdma.exclsem, 0, 1);
for (i = 0; i < LPC17_NDMACH; i++)
{

4
arch/arm/src/lpc17xx/lpc17_i2c.c
View File

@ -569,8 +569,8 @@ struct i2c_master_s *lpc17_i2cbus_initialize(int port)
/* Initialize semaphores */
sem_init(&priv->mutex, 0, 1);
sem_init(&priv->wait, 0, 0);
nxsem_init(&priv->mutex, 0, 1);
nxsem_init(&priv->wait, 0, 0);
/* The wait semaphore is used for signaling and, hence, should not have
* priority inheritance enabled.

2
arch/arm/src/lpc17xx/lpc17_sdcard.c
View File

@ -2718,7 +2718,7 @@ FAR struct sdio_dev_s *sdio_initialize(int slotno)
/* Initialize the SD card slot structure */
/* Initialize semaphores */
sem_init(&priv->waitsem, 0, 0);
nxsem_init(&priv->waitsem, 0, 0);
/* The waitsem semaphore is used for signaling and, hence, should not have
* priority inheritance enabled.

2
arch/arm/src/lpc17xx/lpc17_spi.c
View File

@ -570,7 +570,7 @@ FAR struct spi_dev_s *lpc17_spibus_initialize(int port)
/* Initialize the SPI semaphore that enforces mutually exclusive access */
sem_init(&priv->exclsem, 0, 1);
nxsem_init(&priv->exclsem, 0, 1);
return &priv->spidev;
}

2
arch/arm/src/lpc17xx/lpc17_ssp.c
View File

@ -982,7 +982,7 @@ FAR struct spi_dev_s *lpc17_sspbus_initialize(int port)
/* Initialize the SPI semaphore that enforces mutually exclusive access */
sem_init(&priv->exclsem, 0, 1);
nxsem_init(&priv->exclsem, 0, 1);
/* Enable the SPI */

8
arch/arm/src/lpc17xx/lpc17_usbhost.c
View File

@ -2267,7 +2267,7 @@ static int lpc17_epalloc(struct usbhost_driver_s *drvr,
* should not have priority inheritance enabled.
*/
sem_init(&ed->wdhsem, 0, 0);
nxsem_init(&ed->wdhsem, 0, 0);
sem_setprotocol(&ed->wdhsem, SEM_PRIO_NONE);
/* Link the common tail TD to the ED's TD list */
@ -3641,8 +3641,8 @@ struct usbhost_connection_s *lpc17_usbhost_initialize(int controller)
/* Initialize semaphores */
sem_init(&priv->pscsem, 0, 0);
sem_init(&priv->exclsem, 0, 1);
nxsem_init(&priv->pscsem, 0, 0);
nxsem_init(&priv->exclsem, 0, 1);
/* The pscsem semaphore is used for signaling and, hence, should not have
* priority inheritance enabled.
@ -3735,7 +3735,7 @@ struct usbhost_connection_s *lpc17_usbhost_initialize(int controller)
* not have priority inheritance enabled.
*/
sem_init(&EDCTRL->wdhsem, 0, 0);
nxsem_init(&EDCTRL->wdhsem, 0, 0);
sem_setprotocol(&EDCTRL->wdhsem, SEM_PRIO_NONE);
/* Initialize user-configurable EDs */

4
arch/arm/src/lpc2378/lpc23xx_i2c.c
View File

@ -580,8 +580,8 @@ struct i2c_master_s *lpc2378_i2cbus_initialize(int port)
/* Initialize semaphores */
sem_init(&priv->mutex, 0, 1);
sem_init(&priv->wait, 0, 0);
nxsem_init(&priv->mutex, 0, 1);
nxsem_init(&priv->wait, 0, 0);
/* The wait semaphore is used for signaling and, hence, should not have
* priority inheritance enabled.

2
arch/arm/src/lpc2378/lpc23xx_spi.c
View File

@ -582,7 +582,7 @@ FAR struct spi_dev_s *lpc23_spibus_initialize(int port)
/* Initialize the SPI semaphore that enforces mutually exclusive access */
sem_init(&priv->exclsem, 0, 1);
nxsem_init(&priv->exclsem, 0, 1);
return &priv->spidev;
}

10
arch/arm/src/lpc31xx/lpc31_ehci.c
View File

@ -3937,7 +3937,7 @@ static int lpc31_epalloc(FAR struct usbhost_driver_s *drvr,
* priority inheritance enabled.
*/
sem_init(&epinfo->iocsem, 0, 0);
nxsem_init(&epinfo->iocsem, 0, 0);
sem_setprotocol(&epinfo->iocsem, SEM_PRIO_NONE);
/* Success.. return an opaque reference to the endpoint information structure
@ -4920,8 +4920,8 @@ FAR struct usbhost_connection_s *lpc31_ehci_initialize(int controller)
/* Initialize the EHCI state data structure */
sem_init(&g_ehci.exclsem, 0, 1);
sem_init(&g_ehci.pscsem, 0, 0);
nxsem_init(&g_ehci.exclsem, 0, 1);
nxsem_init(&g_ehci.pscsem, 0, 0);
/* The pscsem semaphore is used for signaling and, hence, should not have
* priority inheritance enabled.
@ -4931,7 +4931,7 @@ FAR struct usbhost_connection_s *lpc31_ehci_initialize(int controller)
/* Initialize EP0 */
sem_init(&g_ehci.ep0.iocsem, 0, 1);
nxsem_init(&g_ehci.ep0.iocsem, 0, 1);
/* Initialize the root hub port structures */
@ -4970,7 +4970,7 @@ FAR struct usbhost_connection_s *lpc31_ehci_initialize(int controller)
* should not have priority inheritance enabled.
*/
sem_init(&rhport->ep0.iocsem, 0, 0);
nxsem_init(&rhport->ep0.iocsem, 0, 0);
sem_setprotocol(&rhport->iocsem, SEM_PRIO_NONE);
/* Initialize the public port representation */

4
arch/arm/src/lpc31xx/lpc31_i2c.c
View File

@ -551,8 +551,8 @@ struct i2c_master_s *lpc31_i2cbus_initialize(int port)
/* Initialize semaphores */
sem_init(&priv->mutex, 0, 1);
sem_init(&priv->wait, 0, 0);
nxsem_init(&priv->mutex, 0, 1);
nxsem_init(&priv->wait, 0, 0);
/* The wait semaphore is used for signaling and, hence, should not have
* priority inheritance enabled.

2
arch/arm/src/lpc31xx/lpc31_spi.c
View File

@ -941,7 +941,7 @@ FAR struct spi_dev_s *lpc31_spibus_initialize(int port)
/* Initialize the SPI semaphore that enforces mutually exclusive access */
sem_init(&priv->exclsem, 0, 1);
nxsem_init(&priv->exclsem, 0, 1);
/* Reset the SPI block */

10
arch/arm/src/lpc43xx/lpc43_ehci.c
View File

@ -3774,7 +3774,7 @@ static int lpc43_epalloc(FAR struct usbhost_driver_s *drvr,
* should not have priority inheritance enabled.
*/
sem_init(&epinfo->iocsem, 0, 0);
nxsem_init(&epinfo->iocsem, 0, 0);
sem_setprotocol(&epinfo->iocsem, SEM_PRIO_NONE);
/* Success.. return an opaque reference to the endpoint information structure
@ -4751,8 +4751,8 @@ FAR struct usbhost_connection_s *lpc43_ehci_initialize(int controller)
/* Initialize the EHCI state data structure */
sem_init(&g_ehci.exclsem, 0, 1);
sem_init(&g_ehci.pscsem, 0, 0);
nxsem_init(&g_ehci.exclsem, 0, 1);
nxsem_init(&g_ehci.pscsem, 0, 0);
/* The pscsem semaphore is used for signaling and, hence, should not have
* priority inheritance enabled.
@ -4762,7 +4762,7 @@ FAR struct usbhost_connection_s *lpc43_ehci_initialize(int controller)
/* Initialize EP0 */
sem_init(&g_ehci.ep0.iocsem, 0, 1);
nxsem_init(&g_ehci.ep0.iocsem, 0, 1);
/* Initialize the root hub port structures */
@ -4801,7 +4801,7 @@ FAR struct usbhost_connection_s *lpc43_ehci_initialize(int controller)
* not have priority inheritance enabled.
*/
sem_init(&rhport->ep0.iocsem, 0, 0);
nxsem_init(&rhport->ep0.iocsem, 0, 0);
sem_setprotocol(&rhport->ep0.iocsem, SEM_PRIO_NONE);
/* Initialize the public port representation */

2
arch/arm/src/lpc43xx/lpc43_gpdma.c
View File

@ -305,7 +305,7 @@ void weak_function up_dmainitialize(void)
/* Initialize the DMA state structure */
sem_init(&g_gpdma.exclsem, 0, 1);
nxsem_init(&g_gpdma.exclsem, 0, 1);
for (i = 0; i < LPC43_NDMACH; i++)
{

4
arch/arm/src/lpc43xx/lpc43_i2c.c
View File

@ -526,8 +526,8 @@ struct i2c_master_s *lpc43_i2cbus_initialize(int port)
/* Initialize semaphores */
sem_init(&priv->mutex, 0, 1);
sem_init(&priv->wait, 0, 0);
nxsem_init(&priv->mutex, 0, 1);
nxsem_init(&priv->wait, 0, 0);
/* The wait semaphore is used for signaling and, hence, should not have
* priority inheritance enabled.

2
arch/arm/src/lpc43xx/lpc43_spi.c
View File

@ -540,7 +540,7 @@ static FAR struct spi_dev_s *lpc43_spiport_initialize(int port)
/* Initialize the SPI semaphore that enforces mutually exclusive access */
sem_init(&priv->exclsem, 0, 1);
nxsem_init(&priv->exclsem, 0, 1);
return &priv->spidev;
}
#endif /* CONFIG_LPC43_SPI */

2
arch/arm/src/lpc43xx/lpc43_ssp.c
View File

@ -827,7 +827,7 @@ FAR struct spi_dev_s *lpc43_sspbus_initialize(int port)
/* Initialize the SPI semaphore that enforces mutually exclusive access */
sem_init(&priv->exclsem, 0, 1);
nxsem_init(&priv->exclsem, 0, 1);
/* Enable the SPI */

2
arch/arm/src/sam34/sam4cm_tc.c
View File

@ -748,7 +748,7 @@ static inline struct sam_chan_s *sam_tc_initialize(int channel)
tmrerr("ERROR: Initializing TC%d\n", chconfig->chan);
memset(chan, 0, sizeof(struct sam_chan_s));
sem_init(&chan->exclsem, 0, 1);
nxsem_init(&chan->exclsem, 0, 1);
chan->base = chconfig->base;
chan->pid = chconfig->pid;
chan->irq = chconfig->irq;

2
arch/arm/src/sam34/sam_aes.c
View File

@ -225,7 +225,7 @@ int aes_cypher(void *out, const void *in, uint32_t size, const void *iv,
int up_aesinitialize()
{
sem_init(&lock, 0, 1);
nxsem_init(&lock, 0, 1);
sam_aes_enableclk();
putreg32(AES_CR_SWRST, SAM_AES_CR);
return OK;

4
arch/arm/src/sam34/sam_dmac.c
View File

@ -1382,8 +1382,8 @@ void weak_function up_dmainitialize(void)
/* Initialize semaphores */
sem_init(&g_chsem, 0, 1);
sem_init(&g_dsem, 0, CONFIG_SAM34_NLLDESC);
nxsem_init(&g_chsem, 0, 1);
nxsem_init(&g_dsem, 0, CONFIG_SAM34_NLLDESC);
}
/****************************************************************************

2
arch/arm/src/sam34/sam_hsmci.c
View File

@ -2681,7 +2681,7 @@ FAR struct sdio_dev_s *sdio_initialize(int slotno)
/* Initialize the HSMCI slot structure */
/* Initialize semaphores */
sem_init(&priv->waitsem, 0, 0);
nxsem_init(&priv->waitsem, 0, 0);
/* The waitsem semaphore is used for signaling and, hence, should not have
* priority inheritance enabled.

4
arch/arm/src/sam34/sam_spi.c
View File

@ -1878,7 +1878,7 @@ struct spi_dev_s *sam_spibus_initialize(int port)
* access to the SPI registers.
*/
sem_init(&spi->spisem, 0, 1);
nxsem_init(&spi->spisem, 0, 1);
spi->initialized = true;
#ifdef CONFIG_SAM34_SPI_DMA
@ -1887,7 +1887,7 @@ struct spi_dev_s *sam_spibus_initialize(int port)
* signaling and, hence, should not have priority inheritance enabled.
*/
sem_init(&spics->dmawait, 0, 0);
nxsem_init(&spics->dmawait, 0, 0);
sem_setprotocol(&spics->dmawait, SEM_PRIO_NONE);
/* Create a watchdog time to catch DMA timeouts */

4
arch/arm/src/sam34/sam_twi.c
View File

@ -967,8 +967,8 @@ struct i2c_master_s *sam_i2cbus_initialize(int bus)
/* Initialize semaphores */
sem_init(&priv->exclsem, 0, 1);
sem_init(&priv->waitsem, 0, 0);
nxsem_init(&priv->exclsem, 0, 1);
nxsem_init(&priv->waitsem, 0, 0);
/* The waitsem semaphore is used for signaling and, hence, should not have
* priority inheritance enabled.

2
arch/arm/src/sama5/sam_adc.c
View File

@ -2025,7 +2025,7 @@ struct adc_dev_s *sam_adc_initialize(void)
/* Initialize the private ADC device data structure */
sem_init(&priv->exclsem, 0, 1);
nxsem_init(&priv->exclsem, 0, 1);
priv->cb = NULL;
priv->dev = &g_adcdev;

2
arch/arm/src/sama5/sam_can.c
View File

@ -1947,7 +1947,7 @@ FAR struct can_dev_s *sam_caninitialize(int port)
priv->freemb = CAN_ALL_MAILBOXES;
priv->initialized = true;
sem_init(&priv->exclsem, 0, 1);
nxsem_init(&priv->exclsem, 0, 1);
dev->cd_ops = &g_canops;
dev->cd_priv = (FAR void *)priv;

4
arch/arm/src/sama5/sam_dmac.c
View File

@ -1879,8 +1879,8 @@ void sam_dmainitialize(struct sam_dmac_s *dmac)
/* Initialize semaphores */
sem_init(&dmac->chsem, 0, 1);
sem_init(&dmac->dsem, 0, SAM_NDMACHAN);
nxsem_init(&dmac->chsem, 0, 1);
nxsem_init(&dmac->dsem, 0, SAM_NDMACHAN);
}
/****************************************************************************

10
arch/arm/src/sama5/sam_ehci.c
View File

@ -3758,7 +3758,7 @@ static int sam_epalloc(FAR struct usbhost_driver_s *drvr,
* should not have priority inheritance enabled.
*/
sem_init(&epinfo->iocsem, 0, 0);
nxsem_init(&epinfo->iocsem, 0, 0);
sem_setprotocol(&epinfo->iocsem, SEM_PRIO_NONE);
/* Success.. return an opaque reference to the endpoint information structure
@ -4791,8 +4791,8 @@ FAR struct usbhost_connection_s *sam_ehci_initialize(int controller)
/* Initialize the EHCI state data structure */
sem_init(&g_ehci.exclsem, 0, 1);
sem_init(&g_ehci.pscsem, 0, 0);
nxsem_init(&g_ehci.exclsem, 0, 1);
nxsem_init(&g_ehci.pscsem, 0, 0);
/* The pscsem semaphore is used for signaling and, hence, should not have
* priority inheritance enabled.
@ -4802,7 +4802,7 @@ FAR struct usbhost_connection_s *sam_ehci_initialize(int controller)
/* Initialize EP0 */
sem_init(&g_ehci.ep0.iocsem, 0, 1);
nxsem_init(&g_ehci.ep0.iocsem, 0, 1);
/* Initialize the root hub port structures */
@ -4841,7 +4841,7 @@ FAR struct usbhost_connection_s *sam_ehci_initialize(int controller)
* should not have priority inheritance enabled.
*/
sem_init(&rhport->ep0.iocsem, 0, 0);
nxsem_init(&rhport->ep0.iocsem, 0, 0);
sem_setprotocol(&rhport->ep0.iocsem, SEM_PRIO_NONE);
/* Initialize the public port representation */

2
arch/arm/src/sama5/sam_hsmci.c
View File

@ -3298,7 +3298,7 @@ FAR struct sdio_dev_s *sdio_initialize(int slotno)
/* Initialize the HSMCI slot structure */
/* Initialize semaphores */
sem_init(&priv->waitsem, 0, 0);
nxsem_init(&priv->waitsem, 0, 0);
/* The waitsem semaphore is used for signaling and, hence, should not have
* priority inheritance enabled.

6
arch/arm/src/sama5/sam_nand.c
View File

@ -2949,7 +2949,7 @@ struct mtd_dev_s *sam_nand_initialize(int cs)
* priority inheritance enabled.
*/
sem_init(&priv->waitsem, 0, 0);
nxsem_init(&priv->waitsem, 0, 0);
sem_setprotocol(&priv->waitsem, SEM_PRIO_NONE);
#endif
@ -2960,7 +2960,7 @@ struct mtd_dev_s *sam_nand_initialize(int cs)
/* Initialize the global nand state structure */
#if NAND_NBANKS > 1
sem_init(&g_nand.exclsem, 0, 1);
nxsem_init(&g_nand.exclsem, 0, 1);
#endif
#ifdef CONFIG_SAMA5_NAND_HSMCINTERRUPTS
@ -2968,7 +2968,7 @@ struct mtd_dev_s *sam_nand_initialize(int cs)
* have priority inheritance enabled.
*/
sem_init(&g_nand.waitsem, 0, 0);
nxsem_init(&g_nand.waitsem, 0, 0);
sem_setprotocol(&g_nand.waitsem, SEM_PRIO_NONE);
#endif

6
arch/arm/src/sama5/sam_ohci.c
View File

@ -2663,7 +2663,7 @@ static int sam_epalloc(struct usbhost_driver_s *drvr,
/* Initialize the endpoint container */
sem_init(&eplist->wdhsem, 0, 0);
nxsem_init(&eplist->wdhsem, 0, 0);
/* The wdhsem semaphore is used for signaling and, hence, should not have
* priority inheritance enabled.
@ -3907,8 +3907,8 @@ struct usbhost_connection_s *sam_ohci_initialize(int controller)
/* Initialize the state data structure */
sem_init(&g_ohci.pscsem, 0, 0);
sem_init(&g_ohci.exclsem, 0, 1);
nxsem_init(&g_ohci.pscsem, 0, 0);
nxsem_init(&g_ohci.exclsem, 0, 1);
/* The pscsem semaphore is used for signaling and, hence, should not have
* priority inheritance enabled.

2
arch/arm/src/sama5/sam_pmecc.c
View File

@ -988,7 +988,7 @@ static int pmecc_pagelayout(uint16_t datasize, uint16_t eccsize)
#if NAND_NPMECC_BANKS > 1
void pmecc_initialize(void)
{
sem_init(&g_pmecc.exclsem, 0, 1);
nxsem_init(&g_pmecc.exclsem, 0, 1);
}
#endif

4
arch/arm/src/sama5/sam_spi.c
View File

@ -1806,7 +1806,7 @@ struct spi_dev_s *sam_spibus_initialize(int port)
* access to the SPI registers.
*/
sem_init(&spi->spisem, 0, 1);
nxsem_init(&spi->spisem, 0, 1);
spi->initialized = true;
#ifdef CONFIG_SAMA5_SPI_DMA
@ -1815,7 +1815,7 @@ struct spi_dev_s *sam_spibus_initialize(int port)
* signaling and, hence, should not have priority inheritance enabled.
*/
sem_init(&spics->dmawait, 0, 0);
nxsem_init(&spics->dmawait, 0, 0);
sem_setprotocol(&spics->dmawait, SEM_PRIO_NONE);
/* Create a watchdog time to catch DMA timeouts */

4
arch/arm/src/sama5/sam_ssc.c
View File

@ -1037,7 +1037,7 @@ static void ssc_buf_initialize(struct sam_ssc_s *priv)
int i;
priv->freelist = NULL;
sem_init(&priv->bufsem, 0, CONFIG_SAMA5_SSC_MAXINFLIGHT);
nxsem_init(&priv->bufsem, 0, CONFIG_SAMA5_SSC_MAXINFLIGHT);
for (i = 0; i < CONFIG_SAMA5_SSC_MAXINFLIGHT; i++)
{
@ -3430,7 +3430,7 @@ struct i2s_dev_s *sam_ssc_initialize(int port)
/* Initialize the common parts for the SSC device structure */
sem_init(&priv->exclsem, 0, 1);
nxsem_init(&priv->exclsem, 0, 1);
priv->dev.ops = &g_sscops;
priv->sscno = port;

2
arch/arm/src/sama5/sam_tc.c
View File

@ -971,7 +971,7 @@ static inline struct sam_chan_s *sam_tc_initialize(int channel)
/* Initialize the timer counter data structure. */
memset(tc, 0, sizeof(struct sam_tc_s));
sem_init(&tc->exclsem, 0, 1);
nxsem_init(&tc->exclsem, 0, 1);
tc->base = tcconfig->base;
tc->tc = channel < 3 ? 0 : 1;
tc->pid = tcconfig->pid;

4
arch/arm/src/sama5/sam_trng.c
View File

@ -356,8 +356,8 @@ static int sam_rng_initialize(void)
/* Initialize semphores */
sem_init(&g_trngdev.exclsem, 0, 1);
sem_init(&g_trngdev.waitsem, 0, 0);
nxsem_init(&g_trngdev.exclsem, 0, 1);
nxsem_init(&g_trngdev.waitsem, 0, 0);
/* The waitsem semaphore is used for signaling and, hence, should not have
* priority inheritance enabled.

2
arch/arm/src/sama5/sam_tsd.c
View File

@ -1674,7 +1674,7 @@ int sam_tsd_register(struct sam_adc_s *adc, int minor)
* signaling and, hence, should not have priority inheritance enabled.
*/
sem_init(&priv->waitsem, 0, 0);
nxsem_init(&priv->waitsem, 0, 0);
sem_setprotocol(&priv->waitsem, SEM_PRIO_NONE);
/* Register the device as an input device */

4
arch/arm/src/sama5/sam_twi.c
View File

@ -1268,8 +1268,8 @@ struct i2c_master_s *sam_i2cbus_initialize(int bus)
/* Initialize semaphores */
(void)sem_init(&priv->exclsem, 0, 1);
(void)sem_init(&priv->waitsem, 0, 0);
(void)nxsem_init(&priv->exclsem, 0, 1);
(void)nxsem_init(&priv->waitsem, 0, 0);
/* The waitsem semaphore is used for signaling and, hence, should not have
* priority inheritance enabled.

4
arch/arm/src/sama5/sam_xdmac.c
View File

@ -1906,8 +1906,8 @@ void sam_dmainitialize(struct sam_xdmac_s *xdmac)
/* Initialize semaphores */
sem_init(&xdmac->chsem, 0, 1);
sem_init(&xdmac->dsem, 0, SAM_NDMACHAN);
nxsem_init(&xdmac->chsem, 0, 1);
nxsem_init(&xdmac->dsem, 0, SAM_NDMACHAN);
}
/****************************************************************************

4
arch/arm/src/samdl/sam_dmac.c
View File

@ -774,9 +774,9 @@ void weak_function up_dmainitialize(void)
/* Initialize global semaphores */
sem_init(&g_chsem, 0, 1);
nxsem_init(&g_chsem, 0, 1);
#if CONFIG_SAMDL_DMAC_NDESC > 0
sem_init(&g_dsem, 0, CONFIG_SAMDL_DMAC_NDESC);
nxsem_init(&g_dsem, 0, CONFIG_SAMDL_DMAC_NDESC);
#endif
/* Initialized the DMA channel table */

4
arch/arm/src/samdl/sam_i2c_master.c
View File

@ -1344,8 +1344,8 @@ struct i2c_master_s *sam_i2c_master_initialize(int bus)
priv->dev.ops = &g_i2cops;
priv->flags = 0;
(void)sem_init(&priv->exclsem, 0, 1);
(void)sem_init(&priv->waitsem, 0, 0);
(void)nxsem_init(&priv->exclsem, 0, 1);
(void)nxsem_init(&priv->waitsem, 0, 0);
/* Perform repeatable I2C hardware initialization */

2
arch/arm/src/samv7/sam_hsmci.c
View File

@ -3330,7 +3330,7 @@ FAR struct sdio_dev_s *sdio_initialize(int slotno)
/* Initialize the HSMCI slot structure */
/* Initialize semaphores */
sem_init(&priv->waitsem, 0, 0);
nxsem_init(&priv->waitsem, 0, 0);
/* The waitsem semaphore is used for signaling and, hence, should not have
* priority inheritance enabled.

18
arch/arm/src/samv7/sam_mcan.c
View File

@ -1441,7 +1441,7 @@ static void mcan_buffer_reserve(FAR struct sam_mcan_s *priv)
flags = enter_critical_section();
txfqs1 = mcan_getreg(priv, SAM_MCAN_TXFQS_OFFSET);
(void)sem_getvalue(&priv->txfsem, &sval);
(void)nxsem_getvalue(&priv->txfsem, &sval);
txfqs2 = mcan_getreg(priv, SAM_MCAN_TXFQS_OFFSET);
/* If the semaphore count and the TXFQS samples are in
@ -1477,7 +1477,7 @@ static void mcan_buffer_reserve(FAR struct sam_mcan_s *priv)
if (sval > 0)
{
canerr("ERROR: TX FIFOQ full but txfsem is %d\n", sval);
sem_reset(&priv->txfsem, 0);
nxsem_reset(&priv->txfsem, 0);
}
}
@ -1542,7 +1542,7 @@ static void mcan_buffer_reserve(FAR struct sam_mcan_s *priv)
/* Reset the semaphore count to the Tx FIFO free level. */
sem_reset(&priv->txfsem, tffl);
nxsem_reset(&priv->txfsem, tffl);
}
#endif
@ -1587,7 +1587,7 @@ static void mcan_buffer_release(FAR struct sam_mcan_s *priv)
* many times.
*/
(void)sem_getvalue(&priv->txfsem, &sval);
(void)nxsem_getvalue(&priv->txfsem, &sval);
if (sval < priv->config->ntxfifoq)
{
sem_post(&priv->txfsem);
@ -2270,7 +2270,7 @@ static void mcan_reset(FAR struct can_dev_s *dev)
*/
sem_destroy(&priv->txfsem);
sem_init(&priv->txfsem, 0, config->ntxfifoq);
nxsem_init(&priv->txfsem, 0, config->ntxfifoq);
/* Disable peripheral clocking to the MCAN controller */
@ -2949,7 +2949,7 @@ static bool mcan_txready(FAR struct can_dev_s *dev)
* the TX FIFO/queue. Make sure that they are consistent.
*/
(void)sem_getvalue(&priv->txfsem, &sval);
(void)nxsem_getvalue(&priv->txfsem, &sval);
DEBUGASSERT(((notfull && sval > 0) || (!notfull && sval <= 0)) &&
(sval <= priv->config->ntxfifoq));
#endif
@ -3016,7 +3016,7 @@ static bool mcan_txempty(FAR struct can_dev_s *dev)
* elements, then there is no transfer in progress.
*/
(void)sem_getvalue(&priv->txfsem, &sval);
(void)nxsem_getvalue(&priv->txfsem, &sval);
DEBUGASSERT(sval > 0 && sval <= priv->config->ntxfifoq);
empty = (sval == priv->config->ntxfifoq);
@ -4014,8 +4014,8 @@ FAR struct can_dev_s *sam_mcan_initialize(int port)
/* Initialize semaphores */
sem_init(&priv->locksem, 0, 1);
sem_init(&priv->txfsem, 0, config->ntxfifoq);
nxsem_init(&priv->locksem, 0, 1);
nxsem_init(&priv->txfsem, 0, config->ntxfifoq);
dev->cd_ops = &g_mcanops;
dev->cd_priv = (FAR void *)priv;

2
arch/arm/src/samv7/sam_progmem.c
View File

@ -363,7 +363,7 @@ void sam_progmem_initialize(void)
* page buffer.
*/
sem_init(&g_page_sem, 0, 1);
nxsem_init(&g_page_sem, 0, 1);
}
/****************************************************************************

4
arch/arm/src/samv7/sam_qspi.c
View File

@ -1775,7 +1775,7 @@ struct qspi_dev_s *sam_qspi_initialize(int intf)
* access to the QSPI registers.
*/
sem_init(&priv->exclsem, 0, 1);
nxsem_init(&priv->exclsem, 0, 1);
#ifdef CONFIG_SAMV7_QSPI_DMA
/* Pre-allocate DMA channels. */
@ -1795,7 +1795,7 @@ struct qspi_dev_s *sam_qspi_initialize(int intf)
* signaling and, hence, should not have priority inheritance enabled.
*/
sem_init(&priv->dmawait, 0, 0);
nxsem_init(&priv->dmawait, 0, 0);
sem_setprotocol(&priv->dmawait, SEM_PRIO_NONE);
/* Create a watchdog time to catch DMA timeouts */

4
arch/arm/src/samv7/sam_spi.c
View File

@ -2162,7 +2162,7 @@ FAR struct spi_dev_s *sam_spibus_initialize(int port)
* access to the SPI registers.
*/
sem_init(&spi->spisem, 0, 1);
nxsem_init(&spi->spisem, 0, 1);
spi->escape_lastxfer = false;
spi->initialized = true;
@ -2172,7 +2172,7 @@ FAR struct spi_dev_s *sam_spibus_initialize(int port)
* signaling and, hence, should not have priority inheritance enabled.
*/
sem_init(&spics->dmawait, 0, 0);
nxsem_init(&spics->dmawait, 0, 0);
sem_setprotocol(&spics->dmawait, SEM_PRIO_NONE);
/* Create a watchdog time to catch DMA timeouts */

2
arch/arm/src/samv7/sam_spi_slave.c
View File

@ -1198,7 +1198,7 @@ struct spi_sctrlr_s *sam_spi_slave_initialize(int port)
* access to the SPI registers.
*/
sem_init(&priv->spisem, 0, 1);
nxsem_init(&priv->spisem, 0, 1);
priv->nss = true;
priv->initialized = true;

4
arch/arm/src/samv7/sam_ssc.c
View File

@ -1011,7 +1011,7 @@ static void ssc_buf_initialize(struct sam_ssc_s *priv)
int i;
priv->freelist = NULL;
sem_init(&priv->bufsem, 0, CONFIG_SAMV7_SSC_MAXINFLIGHT);
nxsem_init(&priv->bufsem, 0, CONFIG_SAMV7_SSC_MAXINFLIGHT);
for (i = 0; i < CONFIG_SAMV7_SSC_MAXINFLIGHT; i++)
{
@ -3406,7 +3406,7 @@ struct i2s_dev_s *sam_ssc_initialize(int port)
/* Initialize the common parts for the SSC device structure */
sem_init(&priv->exclsem, 0, 1);
nxsem_init(&priv->exclsem, 0, 1);
priv->dev.ops = &g_sscops;
priv->sscno = port;

2
arch/arm/src/samv7/sam_tc.c
View File

@ -1187,7 +1187,7 @@ static inline struct sam_chan_s *sam_tc_initialize(int channel)
/* Initialize the timer counter data structure. */
memset(tc, 0, sizeof(struct sam_tc_s));
sem_init(&tc->exclsem, 0, 1);
nxsem_init(&tc->exclsem, 0, 1);
tc->base = tcconfig->base;
tc->tc = tcconfig->tc;

4
arch/arm/src/samv7/sam_trng.c
View File

@ -357,8 +357,8 @@ static int sam_rng_initialize(void)
/* Initialize semaphores */
sem_init(&g_trngdev.exclsem, 0, 1);
sem_init(&g_trngdev.waitsem, 0, 0);
nxsem_init(&g_trngdev.exclsem, 0, 1);
nxsem_init(&g_trngdev.waitsem, 0, 0);
/* The waitsem semaphore is used for signaling and, hence, should not have
* priority inheritance enabled.

4
arch/arm/src/samv7/sam_twihs.c
View File

@ -1433,8 +1433,8 @@ struct i2c_master_s *sam_i2cbus_initialize(int bus)
/* Initialize semaphores */
(void)sem_init(&priv->exclsem, 0, 1);
(void)sem_init(&priv->waitsem, 0, 0);
(void)nxsem_init(&priv->exclsem, 0, 1);
(void)nxsem_init(&priv->waitsem, 0, 0);
/* The waitsem semaphore is used for signaling and, hence, should not
* have priority inheritance enabled.

4
arch/arm/src/samv7/sam_xdmac.c
View File

@ -1586,8 +1586,8 @@ void sam_dmainitialize(struct sam_xdmac_s *xdmac)
/* Initialize semaphores */
sem_init(&xdmac->chsem, 0, 1);
sem_init(&xdmac->dsem, 0, SAMV7_NDMACHAN);
nxsem_init(&xdmac->chsem, 0, 1);
nxsem_init(&xdmac->dsem, 0, SAMV7_NDMACHAN);
}
/****************************************************************************

4
arch/arm/src/stm32/stm32_1wire.c
View File

@ -708,8 +708,8 @@ static int stm32_1wire_deinit(FAR struct stm32_1wire_priv_s *priv)
static inline void stm32_1wire_sem_init(FAR struct stm32_1wire_priv_s *priv)
{
sem_init(&priv->sem_excl, 0, 1);
sem_init(&priv->sem_isr, 0, 0);
nxsem_init(&priv->sem_excl, 0, 1);
nxsem_init(&priv->sem_isr, 0, 0);
/* The sem_isr semaphore is used for signaling and, hence, should not have
* priority inheritance enabled.

2
arch/arm/src/stm32/stm32_aes.c
View File

@ -293,7 +293,7 @@ int up_aesinitialize(void)
{
uint32_t regval;
sem_init(&aes_lock, 0, 1);
nxsem_init(&aes_lock, 0, 1);
regval = getreg32(STM32_RCC_AHBENR);
regval |= RCC_AHBENR_AESEN;

2
arch/arm/src/stm32/stm32_bbsram.c
View File

@ -698,7 +698,7 @@ static int stm32_bbsram_probe(int *ent, struct stm32_bbsram_s pdev[])
pdev[i].bbf = pf;
pf = (struct bbsramfh_s *)((uint8_t *)pf + alloc);
sem_init(&g_bbsram[i].exclsem, 0, 1);
nxsem_init(&g_bbsram[i].exclsem, 0, 1);
}
avail -= alloc;

4
arch/arm/src/stm32/stm32_dma2d.c
View File

@ -2160,14 +2160,14 @@ int up_dma2dinitialize(void)
* to the driver
*/
sem_init(&g_lock, 0, 1);
nxsem_init(&g_lock, 0, 1);
/* Initialize the semaphore for interrupt handling. This waitsem
* semaphore is used for signaling and, hence, should not have
* priority inheritance enabled.
*/
sem_init(g_interrupt.sem, 0, 0);
nxsem_init(g_interrupt.sem, 0, 0);
sem_setprotocol(g_interrupt.sem, SEM_PRIO_NONE);
#ifdef CONFIG_STM32_DMA2D_L8

2
arch/arm/src/stm32/stm32_hrtim.c
View File

@ -4802,7 +4802,7 @@ int hrtim_register(FAR const char *path, FAR struct hrtim_dev_s *dev)
/* Initialize semaphores */
sem_init(&dev->hd_closesem, 0, 1);
nxsem_init(&dev->hd_closesem, 0, 1);
/* Register the HRTIM character driver */

4
arch/arm/src/stm32/stm32_i2c.c
View File

@ -772,14 +772,14 @@ static inline void stm32_i2c_sem_post(struct stm32_i2c_priv_s *priv)
static inline void stm32_i2c_sem_init(FAR struct stm32_i2c_priv_s *priv)
{
sem_init(&priv->sem_excl, 0, 1);
nxsem_init(&priv->sem_excl, 0, 1);
#ifndef CONFIG_I2C_POLLED
/* This semaphore is used for signaling and, hence, should not have
* priority inheritance enabled.
*/
sem_init(&priv->sem_isr, 0, 0);
nxsem_init(&priv->sem_isr, 0, 0);
sem_setprotocol(&priv->sem_isr, SEM_PRIO_NONE);
#endif
}

4
arch/arm/src/stm32/stm32_i2c_alt.c
View File

@ -780,14 +780,14 @@ static inline void stm32_i2c_sem_post(FAR struct stm32_i2c_priv_s *priv)
static inline void stm32_i2c_sem_init(FAR struct stm32_i2c_priv_s *priv)
{
sem_init(&priv->sem_excl, 0, 1);
nxsem_init(&priv->sem_excl, 0, 1);
#ifndef CONFIG_I2C_POLLED
/* This semaphore is used for signaling and, hence, should not have
* priority inheritance enabled.
*/
sem_init(&priv->sem_isr, 0, 0);
nxsem_init(&priv->sem_isr, 0, 0);
sem_setprotocol(&priv->sem_isr, SEM_PRIO_NONE);
#endif
}

4
arch/arm/src/stm32/stm32_i2s.c
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@ -773,7 +773,7 @@ static void i2s_buf_initialize(struct stm32_i2s_s *priv)
int i;
priv->freelist = NULL;
sem_init(&priv->bufsem, 0, CONFIG_STM32_I2S_MAXINFLIGHT);
nxsem_init(&priv->bufsem, 0, CONFIG_STM32_I2S_MAXINFLIGHT);
for (i = 0; i < CONFIG_STM32_I2S_MAXINFLIGHT; i++)
{
@ -2598,7 +2598,7 @@ FAR struct i2s_dev_s *stm32_i2sdev_initialize(int port)
/* Initialize the common parts for the I2S device structure */
sem_init(&priv->exclsem, 0, 1);
nxsem_init(&priv->exclsem, 0, 1);
priv->dev.ops = &g_i2sops;
priv->i2sno = port;

4
arch/arm/src/stm32/stm32_ltdc.c
View File

@ -1286,14 +1286,14 @@ static void stm32_global_configure(void)
{
/* Initialize the LTDC semaphore that enforces mutually exclusive access */
sem_init(&g_lock, 0, 1);
nxsem_init(&g_lock, 0, 1);
/* Initialize the semaphore for interrupt handling. This waitsem
* semaphore is used for signaling and, hence, should not have priority
* inheritance enabled.
*/
sem_init(g_interrupt.sem, 0, 0);
nxsem_init(g_interrupt.sem, 0, 0);
sem_setprotocol(g_interrupt.sem, SEM_PRIO_NONE);
/* Attach LTDC interrupt vector */

6
arch/arm/src/stm32/stm32_otgfshost.c
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@ -5186,8 +5186,8 @@ static inline void stm32_sw_initialize(FAR struct stm32_usbhost_s *priv)
/* Initialize semaphores */
sem_init(&priv->pscsem, 0, 0);
sem_init(&priv->exclsem, 0, 1);
nxsem_init(&priv->pscsem, 0, 0);
nxsem_init(&priv->exclsem, 0, 1);
/* The pscsem semaphore is used for signaling and, hence, should not have
* priority inheritance enabled.
@ -5217,7 +5217,7 @@ static inline void stm32_sw_initialize(FAR struct stm32_usbhost_s *priv)
* have priority inheritance enabled.
*/
sem_init(&chan->waitsem, 0, 0);
nxsem_init(&chan->waitsem, 0, 0);
sem_setprotocol(&chan->waitsem, SEM_PRIO_NONE);
}
}

6
arch/arm/src/stm32/stm32_otghshost.c
View File

@ -5189,8 +5189,8 @@ static inline void stm32_sw_initialize(FAR struct stm32_usbhost_s *priv)
/* Initialize semaphores */
sem_init(&priv->pscsem, 0, 0);
sem_init(&priv->exclsem, 0, 1);
nxsem_init(&priv->pscsem, 0, 0);
nxsem_init(&priv->exclsem, 0, 1);
/* The pscsem semaphore is used for signaling and, hence, should not have
* priority inheritance enabled.
@ -5220,7 +5220,7 @@ static inline void stm32_sw_initialize(FAR struct stm32_usbhost_s *priv)
* have priority inheritance enabled.
*/
sem_init(&chan->waitsem, 0, 0);
nxsem_init(&chan->waitsem, 0, 0);
sem_setprotocol(&chan->waitsem, SEM_PRIO_NONE);
}
}

4
arch/arm/src/stm32/stm32_rng.c
View File

@ -119,7 +119,7 @@ static int stm32_rng_initialize(void)
memset(&g_rngdev, 0, sizeof(struct rng_dev_s));
sem_init(&g_rngdev.rd_devsem, 0, 1);
nxsem_init(&g_rngdev.rd_devsem, 0, 1);
if (irq_attach(STM32_IRQ_RNG, stm32_interrupt, NULL))
{
@ -262,7 +262,7 @@ static ssize_t stm32_read(struct file *filep, char *buffer, size_t buflen)
* enabled.
*/
sem_init(&g_rngdev.rd_readsem, 0, 0);
nxsem_init(&g_rngdev.rd_readsem, 0, 0);
sem_setprotocol(&g_rngdev.rd_readsem, SEM_PRIO_NONE);
g_rngdev.rd_buflen = buflen;

2
arch/arm/src/stm32/stm32_sdio.c
View File

@ -2963,7 +2963,7 @@ FAR struct sdio_dev_s *sdio_initialize(int slotno)
/* Initialize the SDIO slot structure */
/* Initialize semaphores */
sem_init(&priv->waitsem, 0, 0);
nxsem_init(&priv->waitsem, 0, 0);
/* The waitsem semaphore is used for signaling and, hence, should not have
* priority inheritance enabled.

6
arch/arm/src/stm32/stm32_spi.c
View File

@ -1722,7 +1722,7 @@ static void spi_bus_initialize(FAR struct stm32_spidev_s *priv)
/* Initialize the SPI semaphore that enforces mutually exclusive access */
sem_init(&priv->exclsem, 0, 1);
nxsem_init(&priv->exclsem, 0, 1);
#ifdef CONFIG_STM32_SPI_DMA
/* Initialize the SPI semaphores that is used to wait for DMA completion.
@ -1730,8 +1730,8 @@ static void spi_bus_initialize(FAR struct stm32_spidev_s *priv)
* priority inheritance enabled.
*/
sem_init(&priv->rxsem, 0, 0);
sem_init(&priv->txsem, 0, 0);
nxsem_init(&priv->rxsem, 0, 0);
nxsem_init(&priv->txsem, 0, 0);
sem_setprotocol(&priv->rxsem, SEM_PRIO_NONE);
sem_setprotocol(&priv->txsem, SEM_PRIO_NONE);

2
arch/arm/src/stm32/stm32f10xxx_dma.c
View File

@ -348,7 +348,7 @@ void weak_function up_dmainitialize(void)
for (chndx = 0; chndx < DMA_NCHANNELS; chndx++)
{
dmach = &g_dma[chndx];
sem_init(&dmach->sem, 0, 1);
nxsem_init(&dmach->sem, 0, 1);
/* Attach DMA interrupt vectors */

2
arch/arm/src/stm32/stm32f20xxx_dma.c
View File

@ -478,7 +478,7 @@ void weak_function up_dmainitialize(void)
for (stream = 0; stream < DMA_NSTREAMS; stream++)
{
dmast = &g_dma[stream];
sem_init(&dmast->sem, 0, 1);
nxsem_init(&dmast->sem, 0, 1);
/* Attach DMA interrupt vectors */

4
arch/arm/src/stm32/stm32f30xxx_i2c.c
View File

@ -888,14 +888,14 @@ static inline void stm32_i2c_sem_post(FAR struct stm32_i2c_priv_s *priv)
static inline void stm32_i2c_sem_init(FAR struct stm32_i2c_priv_s *priv)
{
sem_init(&priv->sem_excl, 0, 1);
nxsem_init(&priv->sem_excl, 0, 1);
#ifndef CONFIG_I2C_POLLED
/* This semaphore is used for signaling and, hence, should not have
* priority inheritance enabled.
*/
sem_init(&priv->sem_isr, 0, 0);
nxsem_init(&priv->sem_isr, 0, 0);
sem_setprotocol(&priv->sem_isr, SEM_PRIO_NONE);
#endif
}

2
arch/arm/src/stm32/stm32f33xxx_dma.c
View File

@ -296,7 +296,7 @@ void weak_function up_dmainitialize(void)
for (chndx = 0; chndx < DMA_NCHANNELS; chndx++)
{
dmach = &g_dma[chndx];
sem_init(&dmach->sem, 0, 1);
nxsem_init(&dmach->sem, 0, 1);
/* Attach DMA interrupt vectors */

2
arch/arm/src/stm32/stm32f40xxx_dma.c
View File

@ -477,7 +477,7 @@ void weak_function up_dmainitialize(void)
for (stream = 0; stream < DMA_NSTREAMS; stream++)
{
dmast = &g_dma[stream];
sem_init(&dmast->sem, 0, 1);
nxsem_init(&dmast->sem, 0, 1);
/* Attach DMA interrupt vectors */

4
arch/arm/src/stm32/stm32f40xxx_i2c.c
View File

@ -829,14 +829,14 @@ static inline void stm32_i2c_sem_post(struct stm32_i2c_priv_s *priv)
static inline void stm32_i2c_sem_init(FAR struct stm32_i2c_priv_s *priv)
{
sem_init(&priv->sem_excl, 0, 1);
nxsem_init(&priv->sem_excl, 0, 1);
#ifndef CONFIG_I2C_POLLED
/* This semaphore is used for signaling and, hence, should not have
* priority inheritance enabled.
*/
sem_init(&priv->sem_isr, 0, 0);
nxsem_init(&priv->sem_isr, 0, 0);
sem_setprotocol(&priv->sem_isr, SEM_PRIO_NONE);
#endif
}

4
arch/arm/src/stm32f0/stm32f0_i2c.c
View File

@ -829,14 +829,14 @@ static inline void stm32f0_i2c_sem_post(FAR struct stm32f0_i2c_priv_s *priv)
static inline void stm32f0_i2c_sem_init(FAR struct stm32f0_i2c_priv_s *priv)
{
sem_init(&priv->sem_excl, 0, 1);
nxsem_init(&priv->sem_excl, 0, 1);
#ifndef CONFIG_I2C_POLLED
/* This semaphore is used for signaling and, hence, should not have
* priority inheritance enabled.
*/
sem_init(&priv->sem_isr, 0, 0);
nxsem_init(&priv->sem_isr, 0, 0);
sem_setprotocol(&priv->sem_isr, SEM_PRIO_NONE);
#endif
}

2
arch/arm/src/stm32f7/stm32_bbsram.c
View File

@ -699,7 +699,7 @@ static int stm32_bbsram_probe(int *ent, struct stm32_bbsram_s pdev[])
pdev[i].bbf = pf;
pf = (struct bbsramfh_s *)((uint8_t *)pf + alloc);
sem_init(&g_bbsram[i].exclsem, 0, 1);
nxsem_init(&g_bbsram[i].exclsem, 0, 1);
}
avail -= alloc;

2
arch/arm/src/stm32f7/stm32_dma.c
View File

@ -478,7 +478,7 @@ void weak_function up_dmainitialize(void)
for (stream = 0; stream < DMA_NSTREAMS; stream++)
{
dmast = &g_dma[stream];
sem_init(&dmast->sem, 0, 1);
nxsem_init(&dmast->sem, 0, 1);
/* Attach DMA interrupt vectors */

4
arch/arm/src/stm32f7/stm32_dma2d.c
View File

@ -2152,14 +2152,14 @@ int up_dma2dinitialize(void)
* to the driver
*/
sem_init(&g_lock, 0, 1);
nxsem_init(&g_lock, 0, 1);
/* Initialize the semaphore for interrupt handling. This waitsem
* semaphore is used for signaling and, hence, should not have
* priority inheritance enabled.
*/
sem_init(g_interrupt.sem, 0, 0);
nxsem_init(g_interrupt.sem, 0, 0);
sem_setprotocol(g_interrupt.sem, SEM_PRIO_NONE);
#ifdef CONFIG_STM32F7_DMA2D_L8

4
arch/arm/src/stm32f7/stm32_i2c.c
View File

@ -1074,14 +1074,14 @@ static inline void stm32_i2c_sem_post(FAR struct i2c_master_s *dev)
static inline void stm32_i2c_sem_init(FAR struct i2c_master_s *dev)
{
sem_init(&((struct stm32_i2c_inst_s *)dev)->priv->sem_excl, 0, 1);
nxsem_init(&((struct stm32_i2c_inst_s *)dev)->priv->sem_excl, 0, 1);
#ifndef CONFIG_I2C_POLLED
/* This semaphore is used for signaling and, hence, should not have
* priority inheritance enabled.
*/
sem_init(&((struct stm32_i2c_inst_s *)dev)->priv->sem_isr, 0, 0);
nxsem_init(&((struct stm32_i2c_inst_s *)dev)->priv->sem_isr, 0, 0);
sem_setprotocol(&((struct stm32_i2c_inst_s *)dev)->priv->sem_isr, SEM_PRIO_NONE);
#endif
}

4
arch/arm/src/stm32f7/stm32_ltdc.c
View File

@ -1285,14 +1285,14 @@ static void stm32_global_configure(void)
{
/* Initialize the LTDC semaphore that enforces mutually exclusive access */
sem_init(&g_lock, 0, 1);
nxsem_init(&g_lock, 0, 1);
/* Initialize the semaphore for interrupt handling. This waitsem
* semaphore is used for signaling and, hence, should not have priority
* inheritance enabled.
*/
sem_init(g_interrupt.sem, 0, 0);
nxsem_init(g_interrupt.sem, 0, 0);
sem_setprotocol(g_interrupt.sem, SEM_PRIO_NONE);
/* Attach LTDC interrupt vector */

6
arch/arm/src/stm32f7/stm32_otghost.c
View File

@ -5183,8 +5183,8 @@ static inline void stm32_sw_initialize(FAR struct stm32_usbhost_s *priv)
/* Initialize semaphores */
sem_init(&priv->pscsem, 0, 0);
sem_init(&priv->exclsem, 0, 1);
nxsem_init(&priv->pscsem, 0, 0);
nxsem_init(&priv->exclsem, 0, 1);
/* The pscsem semaphore is used for signaling and, hence, should not have
* priority inheritance enabled.
@ -5214,7 +5214,7 @@ static inline void stm32_sw_initialize(FAR struct stm32_usbhost_s *priv)
* have priority inheritance enabled.
*/
sem_init(&chan->waitsem, 0, 0);
nxsem_init(&chan->waitsem, 0, 0);
sem_setprotocol(&chan->waitsem, SEM_PRIO_NONE);
}
}

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