STM32 F3 I2C driver from John Wharington
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4bdcceb3b3
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@ -95,8 +95,7 @@ CHIP_ASRCS =
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CHIP_CSRCS = stm32_allocateheap.c stm32_start.c stm32_rcc.c stm32_lse.c
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CHIP_CSRCS = stm32_allocateheap.c stm32_start.c stm32_rcc.c stm32_lse.c
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CHIP_CSRCS += stm32_lsi.c stm32_gpio.c stm32_exti_gpio.c stm32_flash.c stm32_irq.c
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CHIP_CSRCS += stm32_lsi.c stm32_gpio.c stm32_exti_gpio.c stm32_flash.c stm32_irq.c
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CHIP_CSRCS += stm32_timerisr.c stm32_dma.c stm32_lowputc.c stm32_serial.c
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CHIP_CSRCS += stm32_timerisr.c stm32_dma.c stm32_lowputc.c stm32_serial.c
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CHIP_CSRCS += stm32_spi.c stm32_sdio.c stm32_tim.c stm32_i2c.c stm32_waste.c
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CHIP_CSRCS += stm32_spi.c stm32_sdio.c stm32_tim.c stm32_waste.c stm32_ccm.c
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CHIP_CSRCS += stm32_ccm.c
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ifeq ($(CONFIG_ARMV7M_CMNVECTOR),y)
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ifeq ($(CONFIG_ARMV7M_CMNVECTOR),y)
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CHIP_ASRCS += stm32_vectors.S
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CHIP_ASRCS += stm32_vectors.S
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@ -106,6 +105,12 @@ ifeq ($(CONFIG_NUTTX_KERNEL),y)
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CHIP_CSRCS += stm32_userspace.c stm32_mpuinit.c
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CHIP_CSRCS += stm32_userspace.c stm32_mpuinit.c
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endif
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endif
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ifeq ($(CONFIG_STM32_STM32F30XX),y)
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CHIP_CSRCS += stm32f30xx_i2c.c
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else
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CHIP_CSRCS += stm32_i2c.c
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endif
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ifeq ($(CONFIG_USBDEV),y)
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ifeq ($(CONFIG_USBDEV),y)
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ifeq ($(CONFIG_STM32_USB),y)
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ifeq ($(CONFIG_STM32_USB),y)
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CHIP_CSRCS += stm32_usbdev.c
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CHIP_CSRCS += stm32_usbdev.c
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@ -1,7 +1,7 @@
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/************************************************************************************
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/************************************************************************************
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* arch/arm/src/stm32/chip/stm32f30xxx_i2c.h
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* arch/arm/src/stm32/chip/stm32f30xxx_i2c.h
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*
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*
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* Copyright (C) 2009, 2011 Gregory Nutt. All rights reserved.
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* Copyright (C) 2009, 2011, 2013 Gregory Nutt. All rights reserved.
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* Author: Gregory Nutt <gnutt@nuttx.org>
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* Author: Gregory Nutt <gnutt@nuttx.org>
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*
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*
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* Redistribution and use in source and binary forms, with or without
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* Redistribution and use in source and binary forms, with or without
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@ -151,6 +151,7 @@
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#define I2C_OAR1_OA1_7_SHIFT (1) /* Bits 1-7: 7-bit interface address */
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#define I2C_OAR1_OA1_7_SHIFT (1) /* Bits 1-7: 7-bit interface address */
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#define I2C_OAR1_OA1_7_MASK (0x7f << I2C_OAR1_OA1_7_SHIFT)
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#define I2C_OAR1_OA1_7_MASK (0x7f << I2C_OAR1_OA1_7_SHIFT)
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#define I2C_OAR1_OA1MODE (1 << 10) /* Bit 10: Own Address 1 10-bit mode */
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#define I2C_OAR1_OA1MODE (1 << 10) /* Bit 10: Own Address 1 10-bit mode */
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#define I2C_OAR1_ONE (1 << 14) /* Bit 14: always keep on in software */
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#define I2C_OAR1_OA1EN (1 << 15) /* Bit 15: Own Address 1 enable */
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#define I2C_OAR1_OA1EN (1 << 15) /* Bit 15: Own Address 1 enable */
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/* Own address register 2 */
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/* Own address register 2 */
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@ -174,16 +175,20 @@
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#define I2C_TIMINGR_SCLL_SHIFT (0) /* Bits 0-7: SCL low period (master) */
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#define I2C_TIMINGR_SCLL_SHIFT (0) /* Bits 0-7: SCL low period (master) */
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#define I2C_TIMINGR_SCLL_MASK (0xff << I2C_TIMINGR_SCLL_SHIFT)
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#define I2C_TIMINGR_SCLL_MASK (0xff << I2C_TIMINGR_SCLL_SHIFT)
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# define I2C_TIMINGR_SCLL(n) (((n)-1) << I2C_TIMINGR_SCLL_SHIFT) /* tSCLL = n x tPRESC */
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# define I2C_TIMINGR_SCLL(n) (((n)-1) << I2C_TIMINGR_SCLL_SHIFT) /* tSCLL = n x tPRESC */
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#define I2C_TIMINGR_SCLH_SHIFT (0) /* Bits 8-15: SCL high period (master) */
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#define I2C_TIMINGR_SCLH_SHIFT (8) /* Bits 8-15: SCL high period (master) */
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#define I2C_TIMINGR_SCLH_MASK (0xff << I2C_TIMINGR_SCLH_SHIFT)
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#define I2C_TIMINGR_SCLH_MASK (0xff << I2C_TIMINGR_SCLH_SHIFT)
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# define I2C_TIMINGR_SCLH(n) (((n)-1) << I2C_TIMINGR_SCLH_SHIFT) /* tSCLH = n x tPRESC */
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# define I2C_TIMINGR_SCLH(n) (((n)-1) << I2C_TIMINGR_SCLH_SHIFT) /* tSCLH = n x tPRESC */
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#define I2C_TIMINGR_SDADEL_SHIFT (0) /* Bits 16-19: Data hold time */
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#define I2C_TIMINGR_SDADEL_SHIFT (16) /* Bits 16-19: Data hold time */
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#define I2C_TIMINGR_SDADEL_MASK (15 << I2C_TIMINGR_SDADEL_SHIFT)
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#define I2C_TIMINGR_SDADEL_MASK (15 << I2C_TIMINGR_SDADEL_SHIFT)
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# define I2C_TIMINGR_SDADEL(n) ((n) << I2C_TIMINGR_SDADEL_SHIFT) /* tSDADEL= n x tPRESC */
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# define I2C_TIMINGR_SDADEL(n) ((n) << I2C_TIMINGR_SDADEL_SHIFT) /* tSDADEL= n x tPRESC */
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#define I2C_TIMINGR_SCLDEL_SHIFT (0) /* Bits 20-23: Data setup time */
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#define I2C_TIMINGR_SCLDEL_SHIFT (20) /* Bits 20-23: Data setup time */
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#define I2C_TIMINGR_SCLDEL_MASK (15 << I2C_TIMINGR_SCLDEL_SHIFT)
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#define I2C_TIMINGR_SCLDEL_MASK (15 << I2C_TIMINGR_SCLDEL_SHIFT)
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# define I2C_TIMINGR_SCLDEL(n) (((n)-1) << I2C_TIMINGR_SCLDEL_SHIFT) /* tSCLDEL = n x tPRESC */
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# define I2C_TIMINGR_SCLDEL(n) (((n)-1) << I2C_TIMINGR_SCLDEL_SHIFT) /* tSCLDEL = n x tPRESC */
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#define I2C_TIMINGR_PRESC_SHIFT (0) /* Bits 28-31: Timing prescaler */
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#define I2C_TIMINGR_PRESC_SHIFT (28) /* Bits 28-31: Timing prescaler */
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#define I2C_TIMINGR_PRESC_MASK (15 << I2C_TIMINGR_PRESC_SHIFT)
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#define I2C_TIMINGR_PRESC_MASK (15 << I2C_TIMINGR_PRESC_SHIFT)
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# define I2C_TIMINGR_PRESC(n) (((n)-1) << I2C_TIMINGR_PRESC_SHIFT) /* tPRESC = n x tI2CCLK */
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# define I2C_TIMINGR_PRESC(n) (((n)-1) << I2C_TIMINGR_PRESC_SHIFT) /* tPRESC = n x tI2CCLK */
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@ -224,6 +229,11 @@
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#define I2C_ISR_ADDCODE_SHIFT (17) /* Bits 17-23: Address match code (slave) */
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#define I2C_ISR_ADDCODE_SHIFT (17) /* Bits 17-23: Address match code (slave) */
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#define I2C_ISR_ADDCODE_MASK (0x7f << I2C_ISR_ADDCODE_SHIFT)
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#define I2C_ISR_ADDCODE_MASK (0x7f << I2C_ISR_ADDCODE_SHIFT)
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#define I2C_ISR_ERRORMASK (I2C_INT_BERR | I2C_INT_ARLO | I2C_INT_OVR | I2C_INT_PECERR | I2C_INT_TIMEOUT)
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#define I2C_ICR_CLEARMASK (I2C_INT_ADDR | I2C_INT_NACK | I2C_INT_STOP | I2C_INT_BERR | I2C_INT_ARLO \
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| I2C_INT_OVR | I2C_INT_PECERR | I2C_INT_TIMEOUT | I2C_INT_ALERT)
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/* Packet error checking register */
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/* Packet error checking register */
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#define I2C_PECR_MASK (0xff)
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#define I2C_PECR_MASK (0xff)
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@ -96,7 +96,6 @@
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/* At least one I2C peripheral must be enabled */
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/* At least one I2C peripheral must be enabled */
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#if defined(CONFIG_STM32_I2C1) || defined(CONFIG_STM32_I2C2) || defined(CONFIG_STM32_I2C3)
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#if defined(CONFIG_STM32_I2C1) || defined(CONFIG_STM32_I2C2) || defined(CONFIG_STM32_I2C3)
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/* This implementation is for the STM32 F1, F2, and F4 only */
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/* This implementation is for the STM32 F1, F2, and F4 only */
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#if defined(CONFIG_STM32_STM32F10XX) || defined(CONFIG_STM32_STM32F20XX) || \
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#if defined(CONFIG_STM32_STM32F10XX) || defined(CONFIG_STM32_STM32F20XX) || \
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@ -469,7 +468,7 @@ struct i2c_ops_s stm32_i2c_ops =
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* Name: stm32_i2c_getreg
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* Name: stm32_i2c_getreg
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*
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*
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* Description:
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* Description:
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* Get register value by offset
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* Get a 16-bit register value by offset
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*
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*
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************************************************************************************/
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************************************************************************************/
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@ -483,7 +482,7 @@ static inline uint16_t stm32_i2c_getreg(FAR struct stm32_i2c_priv_s *priv,
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* Name: stm32_i2c_putreg
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* Name: stm32_i2c_putreg
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*
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*
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* Description:
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* Description:
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* Put register value by offset
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* Put a 16-bit register value by offset
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*
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*
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************************************************************************************/
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************************************************************************************/
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@ -497,7 +496,7 @@ static inline void stm32_i2c_putreg(FAR struct stm32_i2c_priv_s *priv, uint8_t o
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* Name: stm32_i2c_modifyreg
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* Name: stm32_i2c_modifyreg
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*
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*
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* Description:
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* Description:
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* Modify register value by offset
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* Modify a 16-bit register value by offset
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*
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*
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************************************************************************************/
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************************************************************************************/
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@ -509,10 +508,10 @@ static inline void stm32_i2c_modifyreg(FAR struct stm32_i2c_priv_s *priv,
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}
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}
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/************************************************************************************
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/************************************************************************************
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* Name:
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* Name: stm32_i2c_sem_wait
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*
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*
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* Description:
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* Description:
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*
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* Take the exclusive access, waiting as necessary
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*
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*
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************************************************************************************/
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************************************************************************************/
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@ -1356,7 +1355,7 @@ static int stm32_i2c_isr(struct stm32_i2c_priv_s *priv)
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* since ACK is not returned. We should ignore this error.
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* since ACK is not returned. We should ignore this error.
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*/
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*/
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if ((status & I2C_SR1_ERRORMASK) != 0)
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if ((status & I2C_ISR_ERRORMASK) != 0)
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{
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{
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stm32_i2c_traceevent(priv, I2CEVENT_ERROR, 0);
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stm32_i2c_traceevent(priv, I2CEVENT_ERROR, 0);
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2207
arch/arm/src/stm32/stm32f30xxx_i2c.c
Normal file
2207
arch/arm/src/stm32/stm32f30xxx_i2c.c
Normal file
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