STM32 F3 I2C driver from John Wharington

arch/arm/src/stm32/Make.defs

@@ -95,8 +95,7 @@ CHIP_ASRCS  =
 CHIP_CSRCS  = stm32_allocateheap.c stm32_start.c stm32_rcc.c stm32_lse.c
 CHIP_CSRCS += stm32_lsi.c stm32_gpio.c stm32_exti_gpio.c stm32_flash.c stm32_irq.c
 CHIP_CSRCS += stm32_timerisr.c stm32_dma.c stm32_lowputc.c stm32_serial.c
-CHIP_CSRCS += stm32_spi.c stm32_sdio.c stm32_tim.c stm32_i2c.c stm32_waste.c
-CHIP_CSRCS += stm32_ccm.c
+CHIP_CSRCS += stm32_spi.c stm32_sdio.c stm32_tim.c stm32_waste.c stm32_ccm.c
 
 ifeq ($(CONFIG_ARMV7M_CMNVECTOR),y)
 CHIP_ASRCS += stm32_vectors.S
@@ -106,6 +105,12 @@ ifeq ($(CONFIG_NUTTX_KERNEL),y)
 CHIP_CSRCS += stm32_userspace.c stm32_mpuinit.c
 endif
 
+ifeq ($(CONFIG_STM32_STM32F30XX),y)
+CHIP_CSRCS += stm32f30xx_i2c.c
+else
+CHIP_CSRCS += stm32_i2c.c
+endif
+
 ifeq ($(CONFIG_USBDEV),y)
 ifeq ($(CONFIG_STM32_USB),y)
 CHIP_CSRCS += stm32_usbdev.c

arch/arm/src/stm32/chip/stm32f30xxx_i2c.h

@@ -1,7 +1,7 @@
 /************************************************************************************
  * arch/arm/src/stm32/chip/stm32f30xxx_i2c.h
  *
- *   Copyright (C) 2009, 2011 Gregory Nutt. All rights reserved.
+ *   Copyright (C) 2009, 2011, 2013 Gregory Nutt. All rights reserved.
  *   Author: Gregory Nutt <gnutt@nuttx.org>
  *
  * Redistribution and use in source and binary forms, with or without
@@ -151,6 +151,7 @@
 #define I2C_OAR1_OA1_7_SHIFT      (1)       /* Bits 1-7: 7-bit interface address */
 #define I2C_OAR1_OA1_7_MASK       (0x7f << I2C_OAR1_OA1_7_SHIFT)
 #define I2C_OAR1_OA1MODE          (1 << 10) /* Bit 10: Own Address 1 10-bit mode */
+#define I2C_OAR1_ONE              (1 << 14) /* Bit 14: always keep on in software */
 #define I2C_OAR1_OA1EN            (1 << 15) /* Bit 15: Own Address 1 enable */
 
 /* Own address register 2 */
@@ -174,16 +175,20 @@
 #define I2C_TIMINGR_SCLL_SHIFT    (0)        /* Bits 0-7: SCL low period (master) */
 #define I2C_TIMINGR_SCLL_MASK     (0xff << I2C_TIMINGR_SCLL_SHIFT)
 #  define I2C_TIMINGR_SCLL(n)     (((n)-1) << I2C_TIMINGR_SCLL_SHIFT) /* tSCLL = n x tPRESC */
-#define I2C_TIMINGR_SCLH_SHIFT    (0)        /* Bits 8-15: SCL high period (master) */
+
+#define I2C_TIMINGR_SCLH_SHIFT    (8)        /* Bits 8-15: SCL high period (master) */
 #define I2C_TIMINGR_SCLH_MASK     (0xff << I2C_TIMINGR_SCLH_SHIFT)
 #  define I2C_TIMINGR_SCLH(n)     (((n)-1) << I2C_TIMINGR_SCLH_SHIFT) /* tSCLH = n x tPRESC */
-#define I2C_TIMINGR_SDADEL_SHIFT  (0)        /* Bits 16-19: Data hold time */
+
+#define I2C_TIMINGR_SDADEL_SHIFT  (16)        /* Bits 16-19: Data hold time */
 #define I2C_TIMINGR_SDADEL_MASK   (15 << I2C_TIMINGR_SDADEL_SHIFT)
 #  define I2C_TIMINGR_SDADEL(n)   ((n) << I2C_TIMINGR_SDADEL_SHIFT) /* tSDADEL= n x tPRESC */
-#define I2C_TIMINGR_SCLDEL_SHIFT  (0)        /* Bits 20-23: Data setup time */
+
+#define I2C_TIMINGR_SCLDEL_SHIFT  (20)        /* Bits 20-23: Data setup time */
 #define I2C_TIMINGR_SCLDEL_MASK   (15 << I2C_TIMINGR_SCLDEL_SHIFT)
 #  define I2C_TIMINGR_SCLDEL(n)   (((n)-1) << I2C_TIMINGR_SCLDEL_SHIFT) /* tSCLDEL = n x tPRESC */
-#define I2C_TIMINGR_PRESC_SHIFT   (0)        /* Bits 28-31: Timing prescaler */
+
+#define I2C_TIMINGR_PRESC_SHIFT   (28)        /* Bits 28-31: Timing prescaler */
 #define I2C_TIMINGR_PRESC_MASK    (15 << I2C_TIMINGR_PRESC_SHIFT)
 #  define I2C_TIMINGR_PRESC(n)    (((n)-1) << I2C_TIMINGR_PRESC_SHIFT) /* tPRESC = n x tI2CCLK */
 
@@ -224,6 +229,11 @@
 #define I2C_ISR_ADDCODE_SHIFT     (17)      /* Bits 17-23: Address match code (slave) */
 #define I2C_ISR_ADDCODE_MASK      (0x7f << I2C_ISR_ADDCODE_SHIFT)
 
+#define I2C_ISR_ERRORMASK (I2C_INT_BERR | I2C_INT_ARLO | I2C_INT_OVR | I2C_INT_PECERR | I2C_INT_TIMEOUT)
+
+#define I2C_ICR_CLEARMASK (I2C_INT_ADDR | I2C_INT_NACK | I2C_INT_STOP | I2C_INT_BERR | I2C_INT_ARLO \
+                           | I2C_INT_OVR | I2C_INT_PECERR | I2C_INT_TIMEOUT | I2C_INT_ALERT)
+
 /* Packet error checking register */
 
 #define I2C_PECR_MASK             (0xff)

arch/arm/src/stm32/stm32_i2c.c

@@ -96,7 +96,6 @@
 /* At least one I2C peripheral must be enabled */
 
 #if defined(CONFIG_STM32_I2C1) || defined(CONFIG_STM32_I2C2) || defined(CONFIG_STM32_I2C3)
-
 /* This implementation is for the STM32 F1, F2, and F4 only */
 
 #if defined(CONFIG_STM32_STM32F10XX) || defined(CONFIG_STM32_STM32F20XX) || \
@@ -469,7 +468,7 @@ struct i2c_ops_s stm32_i2c_ops =
  * Name: stm32_i2c_getreg
  *
  * Description:
- *   Get register value by offset
+ *   Get a 16-bit register value by offset
  *
  ************************************************************************************/
 
@@ -483,7 +482,7 @@ static inline uint16_t stm32_i2c_getreg(FAR struct stm32_i2c_priv_s *priv,
  * Name: stm32_i2c_putreg
  *
  * Description:
- *  Put register value by offset
+ *  Put a 16-bit register value by offset
  *
  ************************************************************************************/
 
@@ -497,7 +496,7 @@ static inline void stm32_i2c_putreg(FAR struct stm32_i2c_priv_s *priv, uint8_t o
  * Name: stm32_i2c_modifyreg
  *
  * Description:
- *   Modify register value by offset
+ *   Modify a 16-bit register value by offset
  *
  ************************************************************************************/
 
@@ -509,10 +508,10 @@ static inline void stm32_i2c_modifyreg(FAR struct stm32_i2c_priv_s *priv,
 }
 
 /************************************************************************************
- * Name:
+ * Name: stm32_i2c_sem_wait
  *
  * Description:
- *
+ *   Take the exclusive access, waiting as necessary
  *
  ************************************************************************************/
 
@@ -1356,7 +1355,7 @@ static int stm32_i2c_isr(struct stm32_i2c_priv_s *priv)
    * since ACK is not returned. We should ignore this error.
    */
 
-    if ((status & I2C_SR1_ERRORMASK) != 0)
+  if ((status & I2C_ISR_ERRORMASK) != 0)
     {
       stm32_i2c_traceevent(priv, I2CEVENT_ERROR, 0);