SAMV7: Add SMC register definition header file; SAMV71-Xult: Add an LCD driver. The initial commit is simply the SAVM4E-EK ILI9375 driver will bogus name changes to ILI9488.
This commit is contained in:
Gregory Nutt
parent
69d2d77424
commit
841854956a
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arch/arm/src/samv7/chip/sam_smc.h
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arch/arm/src/samv7/chip/sam_smc.h
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/****************************************************************************************
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* arch/arm/src/ssamv7/chip/sam_smc.h
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* Static Memory Controller (SMC) definitions for the SAMV71
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*
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* Copyright (C) 2015 Gregory Nutt. All rights reserved.
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* Author: Gregory Nutt <gnutt@nuttx.org>
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in
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* the documentation and/or other materials provided with the
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* distribution.
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* 3. Neither the name NuttX nor the names of its contributors may be
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* used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
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* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
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* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
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* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
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* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
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* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
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* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*
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****************************************************************************************/
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#ifndef __ARCH_ARM_SRC_SAMV7_CHIP_SAM_SMC_H
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#define __ARCH_ARM_SRC_SAMV7_CHIP_SAM_SMC_H
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/****************************************************************************************
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* Included Files
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****************************************************************************************/
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#include <nuttx/config.h>
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#include <arch/samv7/chip.h>
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#include "chip/sam_memorymap.h"
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/****************************************************************************************
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* Pre-processor Definitions
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****************************************************************************************/
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/* SMC register offsets *****************************************************************/
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#define SAM_SMCCS_OFFSET(n) ((n) << 4)
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# define SAM_SMCCS0_OFFSET 0x0000 /* SMC CS0 offset */
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# define SAM_SMCCS1_OFFSET 0x0010 /* SMC CS1 offset */
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# define SAM_SMCCS2_OFFSET 0x0020 /* SMC CS2 offset */
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# define SAM_SMCCS3_OFFSET 0x0030 /* SMC CS3 offset */
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#define SAM_SMCCS_SETUP_OFFSET 0x0000 /* SMC Setup Register */
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#define SAM_SMCCS_PULSE_OFFSET 0x0004 /* SMC Pulse Register */
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#define SAM_SMCCS_CYCLE_OFFSET 0x0008 /* SMC Cycle Register */
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#define SAM_SMCCS_MODE_OFFSET 0x000c /* SMC Mode Register */
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#define SAM_SMC_OCMS_OFFSET 0x0080 /* SMC OCMS Mode Register */
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#define SAM_SMC_KEY1_OFFSET 0x0084 /* SMC KEY1 Register */
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#define SAM_SMC_KEY2_OFFSET 0x0088 /* SMC KEY2 Register */
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#define SAM_SMC_WPCR_OFFSET 0x00e4 /* Write Protection Control Register */
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#define SAM_SMC_WPSR_OFFSET 0x00e8 /* Write Protection Status Register */
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/* SMC register addresses ***************************************************************/
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#define SAM_SMCCS_BASE(n) (SAM_SMC_BASE+SAM_SMCCS_OFFSET(n))
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# define SAM_SMC_CS0_BASE (SAM_SMC_BASE+SAM_SMCCS0_OFFSET)
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# define SAM_SMC_CS1_BASE (SAM_SMC_BASE+SAM_SMCCS1_OFFSET)
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# define SAM_SMC_CS2_BASE (SAM_SMC_BASE+SAM_SMCCS2_OFFSET)
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# define SAM_SMC_CS3_BASE (SAM_SMC_BASE+SAM_SMCCS3_OFFSET)
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#define SAM_SMCCS_SETUP(n) (SAM_SMCCS_BASE(n)+SAM_SMCCS_SETUP_OFFSET)
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#define SAM_SMCCS_PULSE(n) (SAM_SMCCS_BASE(n)+SAM_SMCCS_PULSE_OFFSET)
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#define SAM_SMCCS_CYCLE(n) (SAM_SMCCS_BASE(n)+SAM_SMCCS_CYCLE_OFFSET)
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#define SAM_SMCCS_MODE(n) (SAM_SMCCS_BASE(n)+SAM_SMCCS_MODE_OFFSET)
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#define SAM_SMCCS0_SETUP (SAM_SMC_CS0_BASE+SAM_SMCCS_SETUP_OFFSET)
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#define SAM_SMCCS0_PULSE (SAM_SMC_CS0_BASE+SAM_SMCCS_PULSE_OFFSET)
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#define SAM_SMCCS0_CYCLE (SAM_SMC_CS0_BASE+SAM_SMCCS_CYCLE_OFFSET)
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#define SAM_SMCCS0_MODE (SAM_SMC_CS0_BASE+SAM_SMCCS_MODE_OFFSET)
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#define SAM_SMCCS1_SETUP (SAM_SMC_CS1_BASE+SAM_SMCCS_SETUP_OFFSET)
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#define SAM_SMCCS1_PULSE (SAM_SMC_CS1_BASE+SAM_SMCCS_PULSE_OFFSET)
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#define SAM_SMCCS1_CYCLE (SAM_SMC_CS1_BASE+SAM_SMCCS_CYCLE_OFFSET)
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#define SAM_SMCCS1_MODE (SAM_SMC_CS1_BASE+SAM_SMCCS_MODE_OFFSET)
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#define SAM_SMCCS2_SETUP (SAM_SMC_CS2_BASE+SAM_SMCCS_SETUP_OFFSET)
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#define SAM_SMCCS2_PULSE (SAM_SMC_CS2_BASE+SAM_SMCCS_PULSE_OFFSET)
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#define SAM_SMCCS2_CYCLE (SAM_SMC_CS2_BASE+SAM_SMCCS_CYCLE_OFFSET)
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#define SAM_SMCCS2_MODE (SAM_SMC_CS2_BASE+SAM_SMCCS_MODE_OFFSET)
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#define SAM_SMCCS3_SETUP (SAM_SMC_CS3_BASE+SAM_SMCCS_SETUP_OFFSET)
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#define SAM_SMCCS3_PULSE (SAM_SMC_CS3_BASE+SAM_SMCCS_PULSE_OFFSET)
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#define SAM_SMCCS3_CYCLE (SAM_SMC_CS3_BASE+SAM_SMCCS_CYCLE_OFFSET)
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#define SAM_SMCCS3_MODE (SAM_SMC_CS3_BASE+SAM_SMCCS_MODE_OFFSET)
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#define SAM_SMC_OCMS (SAM_SMC_BASE+SAM_SMC_OCMS_OFFSET)
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#define SAM_SMC_KEY1 (SAM_SMC_BASE+SAM_SMC_KEY1_OFFSET)
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#define SAM_SMC_KEY2 (SAM_SMC_BASE+SAM_SMC_KEY2_OFFSET)
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#define SAM_SMC_WPCR (SAM_SMC_BASE+SAM_SMC_WPCR_OFFSET)
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#define SAM_SMC_WPSR (SAM_SMC_BASE+SAM_SMC_WPSR_OFFSET)
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/* SMC register bit definitions *********************************************************/
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/* SMC Setup Register */
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#define SMCCS_SETUP_NWESETUP_SHIFT (0) /* Bits 0-5: NWE Setup length */
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#define SMCCS_SETUP_NWESETUP_MASK (63 << SMCCS_SETUP_NWESETUP_SHIFT)
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# define SMCCS_SETUP_NWESETUP(n) ((n) << SMCCS_SETUP_NWESETUP_SHIFT)
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#define SMCCS_SETUP_NCSWRSETUP_SHIFT (8) /* Bits 8-13: NCS Setup length in Write access */
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#define SMCCS_SETUP_NCSWRSETUP_MASK (63 << SMCCS_SETUP_NCSWRSETUP_SHIFT)
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# define SMCCS_SETUP_NCSWRSETUP(n) ((n) << SMCCS_SETUP_NCSWRSETUP_SHIFT)
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#define SMCCS_SETUP_NRDSETUP_SHIFT (16) /* Bits 16-21: NRD Setup length */
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#define SMCCS_SETUP_NRDSETUP_MASK (63 << SMCCS_SETUP_NRDSETUP_SHIFT)
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# define SMCCS_SETUP_NRDSETUP(n) ((n) << SMCCS_SETUP_NRDSETUP_SHIFT)
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#define SMCCS_SETUP_NCSRDSETUP_SHIFT (24) /* Bits 24-29: NCS Setup length in Read access */
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#define SMCCS_SETUP_NCSRDSETUP_MASK (63 << SMCCS_SETUP_NCSRDSETUP_SHIFT)
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# define SMCCS_SETUP_NCSRDSETUP(n) ((n) << SMCCS_SETUP_NCSRDSETUP_SHIFT)
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/* SMC Pulse Register */
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#define SMCCS_PULSE_NWEPULSE_SHIFT (0) /* Bits 0-6: NWE Pulse Length */
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#define SMCCS_PULSE_NWEPULSE_MASK (127 << SMCCS_PULSE_NWEPULSE_SHIFT)
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# define SMCCS_PULSE_NWEPULSE(n) ((n) << SMCCS_PULSE_NWEPULSE_SHIFT)
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#define SMCCS_PULSE_NCSWRPULSE_SHIFT (8) /* Bits 8-14: NCS Pulse Length in WRITE Access */
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#define SMCCS_PULSE_NCSWRPULSE_MASK (127 << SMCCS_PULSE_NCSWRPULSE_SHIFT)
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# define SMCCS_PULSE_NCSWRPULSE(n) ((n) << SMCCS_PULSE_NCSWRPULSE_SHIFT)
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#define SMCCS_PULSE_NRDPULSE_SHIFT (16) /* Bits 16-22: NRD Pulse Length */
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#define SMCCS_PULSE_NRDPULSE_MASK (127 << SMCCS_PULSE_NRDPULSE_SHIFT)
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# define SMCCS_PULSE_NRDPULSE(n) ((n) << SMCCS_PULSE_NRDPULSE_SHIFT)
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#define SMCCS_PULSE_NCSRDPULSE_SHIFT (24) /* Bits 24-30: NCS Pulse Length in READ Access */
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#define SMCCS_PULSE_NCSRDPULSE_MASK (127 << SMCCS_PULSE_NCSRDPULSE_SHIFT)
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# define SMCCS_PULSE_NCSRDPULSE(n) ((n) << SMCCS_PULSE_NCSRDPULSE_SHIFT)
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/* SMC Cycle Register */
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#define SMCCS_CYCLE_NWECYCLE_SHIFT (0) /* Bits 0-8: Total Write Cycle Length */
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#define SMCCS_CYCLE_NWECYCLE_MASK (0x1ff << SMCCS_CYCLE_NWECYCLE_SHIFT)
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# define SMCCS_CYCLE_NWECYCLE(n) ((n) << SMCCS_CYCLE_NWECYCLE_SHIFT)
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#define SMCCS_CYCLE_NRDCYCLE_SHIFT (16) /* Bits 16-24: Total Read Cycle Length */
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#define SMCCS_CYCLE_NRDCYCLE_MASK (0x1ff << SMCCS_CYCLE_NRDCYCLE_SHIFT)
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# define SMCCS_CYCLE_NRDCYCLE(n) ((n) << SMCCS_CYCLE_NRDCYCLE_SHIFT)
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/* SMC Mode Register */
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#define SMCCS_MODE_READMODE (1 << 0) /* Bit 0: Read mode */
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#define SMCCS_MODE_WRITEMODE (1 << 1) /* Bit 1: Write mode */
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#define SMCCS_MODE_EXNWMODE_SHIFT (4) /* Bits 4-5: NWAIT Mode */
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#define SMCCS_MODE_EXNWMODE_MASK (3 << SMCCS_MODE_EXNWMODE_SHIFT)
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# define SMCCS_EXNWMODE_DISABLED (0 << SMCCS_MODE_EXNWMODE_SHIFT)
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# define SMCCS_EXNWMODE_FROZEN (2 << SMCCS_MODE_EXNWMODE_SHIFT)
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# define SMCCS_EXNWMODE_READY (3 << SMCCS_MODE_EXNWMODE_SHIFT)
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#define SMCCS_MODE_BAT (1 << 8) /* Bit 8: Byte Access Type */
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#define SMCCS_MODE_DBW_MASK (1 << 12) /* Bit 12: Data Bus Width */
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# define SMCCS_MODE_DBW_8BIT (0 << 12) /* 0=8-bit data bus */
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# define SMCCS_MODE_DBW_16BIT (1 << 12) /* 1=16-bit data bus */
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#define SMCCS_MODE_TDFCYCLES_SHIFT (16) /* Bits 16-19: Data Float Time */
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#define SMCCS_MODE_TDFCYCLES_MASK (15 << SMCCS_MODE_TDFCYCLES_SHIFT)
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# define SMCCS_MODE_TDFCYCLES(n) ((uint32_t)(n) << SMCCS_MODE_TDFCYCLES_SHIFT)
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#define SMCCS_MODE_TDFMODE (1 << 20) /* Bit 20: TDF Optimization */
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#define SMCCS_MODE_PMEN (1 << 24) /* Bit 24: Page Mode Enabled */
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#define SMCCS_MODE_PS_SHIFT (28) /* Bits 28-29: Page Size */
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#define SMCCS_MODE_PS_MASK (3 << SMCCS_MODE_PS_SHIFT)
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# define SMCCS_MODE_PS_SIZE_4BYTES (0 << SMCCS_MODE_PS_SHIFT) /* 4 bytes */
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# define SMCCS_MODE_PS_SIZE_8BYTES (1 << SMCCS_MODE_PS_SHIFT) /* 8 bytes */
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# define SMCCS_MODE_PS_SIZE_16BYTES (2 << SMCCS_MODE_PS_SHIFT) /* 16 bytes */
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# define SMCCS_MODE_PS_SIZE_32BYTES (3 << SMCCS_MODE_PS_SHIFT) /* 32 bytes */
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/* SMC OCMS Mode Register */
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#define SMC_OCMS_SMSE (1 << 0) /* Bit 0: Static Memory Controller Scrambling Enable */
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#define SMC_OCMS_CSSE(n) (1 << ((n)+16)) /* Chip Select (n=0-3) Scrambling Enable */
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# define SMC_OCMS_CS0SE (1 << 16) /* Bit 16: Chip Select 0 Scrambling Enable */
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# define SMC_OCMS_CS1SE (1 << 17) /* Bit 17: Chip Select 1 Scrambling Enable */
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# define SMC_OCMS_CS2SE (1 << 18) /* Bit 18: Chip Select 2 Scrambling Enable */
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# define SMC_OCMS_CS3SE (1 << 19) /* Bit 19: Chip Select 3 Scrambling Enable */
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/* SMC KEY1/2 Registers (32-bit data) */
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/* SMC Write Protect Mode Register */
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#define SMC_WPCR_WPPEN (1 << 0) /* Bit 0: Write Protection Enable */
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#define SMC_WPCR_WPKEY_SHIFT (8) /* Bits 8-31: Write Protection KEY password */
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#define SMC_WPCR_WPKEY_MASK (0x00ffffff << SMC_WPCR_WPKEY_SHIFT)
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# define SMC_WPCR_WPKEY (0x00534d43 << SMC_WPCR_WPKEY_SHIFT)
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/* SMC Write Protection Status */
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#define SMC_WPSR_WPVS (1 << 0) /* Bit 0: Write Protect Violation Source */
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#define SMC_WPSR_WPVSRC_SHIFT (8) /* Bits 8-23: Write Protection Violation Source */
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#define SMC_WPSR_WPVSRC_MASK (0xffff << SMC_WPSR_WPVSRC_SHIFT)
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/****************************************************************************************
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* Public Types
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****************************************************************************************/
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/****************************************************************************************
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* Public Data
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****************************************************************************************/
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/****************************************************************************************
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* Public Functions
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****************************************************************************************/
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#endif /* __ARCH_ARM_SRC_SAMV7_CHIP_SAM_SMC_H */
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