Add STM32 F3 USART definitions
git-svn-id: svn://svn.code.sf.net/p/nuttx/code/trunk@5626 42af7a65-404d-4744-a932-0658087f49c3
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217
arch/arm/src/stm32/chip/stm32f10xxx_uart.h
Normal file
217
arch/arm/src/stm32/chip/stm32f10xxx_uart.h
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@ -0,0 +1,217 @@
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/************************************************************************************
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* arch/arm/src/stm32/chip/stm32f10xxx_uart.h
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*
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* Copyright (C) 2009, 2011-2013 Gregory Nutt. All rights reserved.
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* Author: Gregory Nutt <gnutt@nuttx.org>
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
*
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||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in
|
||||
* the documentation and/or other materials provided with the
|
||||
* distribution.
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* 3. Neither the name NuttX nor the names of its contributors may be
|
||||
* used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
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||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
|
||||
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
|
||||
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
|
||||
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
|
||||
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
|
||||
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
|
||||
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*
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************************************************************************************/
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#ifndef __ARCH_ARM_STC_STM32_CHIP_STM32F10XXX_UART_H
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#define __ARCH_ARM_STC_STM32_CHIP_STM32F10XXX_UART_H
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/************************************************************************************
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* Included Files
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************************************************************************************/
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#include <nuttx/config.h>
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#include "chip.h"
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/************************************************************************************
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* Pre-processor Definitions
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************************************************************************************/
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/* Register Offsets *****************************************************************/
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#define STM32_USART_SR_OFFSET 0x0000 /* Status register (32-bits) */
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#define STM32_USART_DR_OFFSET 0x0004 /* Data register (32-bits) */
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#define STM32_USART_BRR_OFFSET 0x0008 /* Baud Rate Register (32-bits) */
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#define STM32_USART_CR1_OFFSET 0x000c /* Control register 1 (32-bits) */
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#define STM32_USART_CR2_OFFSET 0x0010 /* Control register 2 (32-bits) */
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#define STM32_USART_CR3_OFFSET 0x0014 /* Control register 3 (32-bits) */
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#define STM32_USART_GTPR_OFFSET 0x0018 /* Guard time and prescaler register (32-bits) */
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/* Register Addresses ***************************************************************/
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#if STM32_NUSART > 0
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# define STM32_USART1_SR (STM32_USART1_BASE+STM32_USART_SR_OFFSET)
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# define STM32_USART1_DR (STM32_USART1_BASE+STM32_USART_DR_OFFSET)
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# define STM32_USART1_BRR (STM32_USART1_BASE+STM32_USART_BRR_OFFSET)
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# define STM32_USART1_CR1 (STM32_USART1_BASE+STM32_USART_CR1_OFFSET)
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# define STM32_USART1_CR2 (STM32_USART1_BASE+STM32_USART_CR2_OFFSET)
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# define STM32_USART1_CR3 (STM32_USART1_BASE+STM32_USART_CR3_OFFSET)
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# define STM32_USART1_GTPR (STM32_USART1_BASE+STM32_USART_GTPR_OFFSET)
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#endif
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#if STM32_NUSART > 1
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# define STM32_USART2_SR (STM32_USART2_BASE+STM32_USART_SR_OFFSET)
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# define STM32_USART2_DR (STM32_USART2_BASE+STM32_USART_DR_OFFSET)
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# define STM32_USART2_BRR (STM32_USART2_BASE+STM32_USART_BRR_OFFSET)
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# define STM32_USART2_CR1 (STM32_USART2_BASE+STM32_USART_CR1_OFFSET)
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# define STM32_USART2_CR2 (STM32_USART2_BASE+STM32_USART_CR2_OFFSET)
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# define STM32_USART2_CR3 (STM32_USART2_BASE+STM32_USART_CR3_OFFSET)
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# define STM32_USART2_GTPR (STM32_USART2_BASE+STM32_USART_GTPR_OFFSET)
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#endif
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#if STM32_NUSART > 2
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# define STM32_USART3_SR (STM32_USART3_BASE+STM32_USART_SR_OFFSET)
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# define STM32_USART3_DR (STM32_USART3_BASE+STM32_USART_DR_OFFSET)
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# define STM32_USART3_BRR (STM32_USART3_BASE+STM32_USART_BRR_OFFSET)
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# define STM32_USART3_CR1 (STM32_USART3_BASE+STM32_USART_CR1_OFFSET)
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# define STM32_USART3_CR2 (STM32_USART3_BASE+STM32_USART_CR2_OFFSET)
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# define STM32_USART3_CR3 (STM32_USART3_BASE+STM32_USART_CR3_OFFSET)
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# define STM32_USART3_GTPR (STM32_USART3_BASE+STM32_USART_GTPR_OFFSET)
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#endif
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#if STM32_NUSART > 3
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# define STM32_UART4_SR (STM32_UART4_BASE+STM32_USART_SR_OFFSET)
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# define STM32_UART4_DR (STM32_UART4_BASE+STM32_USART_DR_OFFSET)
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# define STM32_UART4_BRR (STM32_UART4_BASE+STM32_USART_BRR_OFFSET)
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# define STM32_UART4_CR1 (STM32_UART4_BASE+STM32_USART_CR1_OFFSET)
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# define STM32_UART4_CR2 (STM32_UART4_BASE+STM32_USART_CR2_OFFSET)
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# define STM32_UART4_CR3 (STM32_UART4_BASE+STM32_USART_CR3_OFFSET)
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#endif
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#if STM32_NUSART > 4
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# define STM32_UART5_SR (STM32_UART5_BASE+STM32_USART_SR_OFFSET)
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# define STM32_UART5_DR (STM32_UART5_BASE+STM32_USART_DR_OFFSET)
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# define STM32_UART5_BRR (STM32_UART5_BASE+STM32_USART_BRR_OFFSET)
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# define STM32_UART5_CR1 (STM32_UART5_BASE+STM32_USART_CR1_OFFSET)
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# define STM32_UART5_CR2 (STM32_UART5_BASE+STM32_USART_CR2_OFFSET)
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# define STM32_UART5_CR3 (STM32_UART5_BASE+STM32_USART_CR3_OFFSET)
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#endif
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/* Register Bitfield Definitions ****************************************************/
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/* Status register */
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#define USART_SR_PE (1 << 0) /* Bit 0: Parity Error */
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#define USART_SR_FE (1 << 1) /* Bit 1: Framing Error */
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#define USART_SR_NE (1 << 2) /* Bit 2: Noise Error Flag */
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#define USART_SR_ORE (1 << 3) /* Bit 3: OverRun Error */
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#define USART_SR_IDLE (1 << 4) /* Bit 4: IDLE line detected */
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#define USART_SR_RXNE (1 << 5) /* Bit 5: Read Data Register Not Empty */
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#define USART_SR_TC (1 << 6) /* Bit 6: Transmission Complete */
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#define USART_SR_TXE (1 << 7) /* Bit 7: Transmit Data Register Empty */
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#define USART_SR_LBD (1 << 8) /* Bit 8: LIN Break Detection Flag */
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#define USART_SR_CTS (1 << 9) /* Bit 9: CTS Flag */
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#define USART_SR_ALLBITS (0x03ff)
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#define USART_SR_CLRBITS (USART_SR_CTS|USART_SR_LBD) /* Cleared by SW write to SR */
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/* Data register */
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#define USART_DR_SHIFT (0) /* Bits 8:0: Data value */
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#define USART_DR_MASK (0xff << USART_DR_SHIFT)
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/* Baud Rate Register */
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#define USART_BRR_FRAC_SHIFT (0) /* Bits 3-0: fraction of USARTDIV */
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#define USART_BRR_FRAC_MASK (0x0f << USART_BRR_FRAC_SHIFT)
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#define USART_BRR_MANT_SHIFT (4) /* Bits 15-4: mantissa of USARTDIV */
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#define USART_BRR_MANT_MASK (0x0fff << USART_BRR_MANT_SHIFT)
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/* Control register 1 */
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#define USART_CR1_SBK (1 << 0) /* Bit 0: Send Break */
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#define USART_CR1_RWU (1 << 1) /* Bit 1: Receiver wakeup */
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#define USART_CR1_RE (1 << 2) /* Bit 2: Receiver Enable */
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#define USART_CR1_TE (1 << 3) /* Bit 3: Transmitter Enable */
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#define USART_CR1_IDLEIE (1 << 4) /* Bit 4: IDLE Interrupt Enable */
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#define USART_CR1_RXNEIE (1 << 5) /* Bit 5: RXNE Interrupt Enable */
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#define USART_CR1_TCIE (1 << 6) /* Bit 6: Transmission Complete Interrupt Enable */
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#define USART_CR1_TXEIE (1 << 7) /* Bit 7: TXE Interrupt Enable */
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#define USART_CR1_PEIE (1 << 8) /* Bit 8: PE Interrupt Enable */
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#define USART_CR1_PS (1 << 9) /* Bit 9: Parity Selection */
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#define USART_CR1_PCE (1 << 10) /* Bit 10: Parity Control Enable */
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#define USART_CR1_WAKE (1 << 11) /* Bit 11: Wakeup method */
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#define USART_CR1_M (1 << 12) /* Bit 12: word length */
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#define USART_CR1_UE (1 << 13) /* Bit 13: USART Enable */
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#define USART_CR1_ALLINTS (USART_CR1_IDLEIE|USART_CR1_RXNEIE|USART_CR1_TCIE|USART_CR1_PEIE)
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/* Control register 2 */
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#define USART_CR2_ADD_SHIFT (0) /* Bits 3-0: Address of the USART node */
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#define USART_CR2_ADD_MASK (0x0f << USART_CR2_ADD_SHIFT)
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#define USART_CR2_LBDL (1 << 5) /* Bit 5: LIN Break Detection Length */
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#define USART_CR2_LBDIE (1 << 6) /* Bit 6: LIN Break Detection Interrupt Enable */
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#define USART_CR2_LBCL (1 << 8) /* Bit 8: Last Bit Clock pulse */
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#define USART_CR2_CPHA (1 << 9) /* Bit 9: Clock Phase */
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#define USART_CR2_CPOL (1 << 10) /* Bit 10: Clock Polarity */
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#define USART_CR2_CLKEN (1 << 11) /* Bit 11: Clock Enable */
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#define USART_CR2_STOP_SHIFT (12) /* Bits 13-12: STOP bits */
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#define USART_CR2_STOP_MASK (3 << USART_CR2_STOP_SHIFT)
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# define USART_CR2_STOP1 (0 << USART_CR2_STOP_SHIFT) /* 00: 1 Stop bit */
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# define USART_CR2_STOP0p5 (1 << USART_CR2_STOP_SHIFT) /* 01: 0.5 Stop bit */
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# define USART_CR2_STOP2 (2 << USART_CR2_STOP_SHIFT) /* 10: 2 Stop bits */
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# define USART_CR2_STOP1p5 (3 << USART_CR2_STOP_SHIFT) /* 11: 1.5 Stop bit */
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#define USART_CR2_LINEN (1 << 14) /* Bit 14: LIN mode enable */
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/* Control register 3 */
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#define USART_CR3_EIE (1 << 0) /* Bit 0: Error Interrupt Enable */
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#define USART_CR3_IREN (1 << 1) /* Bit 1: IrDA mode Enable */
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#define USART_CR3_IRLP (1 << 2) /* Bit 2: IrDA Low-Power */
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#define USART_CR3_HDSEL (1 << 3) /* Bit 3: Half-Duplex Selection */
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#define USART_CR3_NACK (1 << 4) /* Bit 4: Smartcard NACK enable */
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#define USART_CR3_SCEN (1 << 5) /* Bit 5: Smartcard mode enable */
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#define USART_CR3_DMAR (1 << 6) /* Bit 6: DMA Enable Receiver */
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#define USART_CR3_DMAT (1 << 7) /* Bit 7: DMA Enable Transmitter */
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#define USART_CR3_RTSE (1 << 8) /* Bit 8: RTS Enable */
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#define USART_CR3_CTSE (1 << 9) /* Bit 9: CTS Enable */
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#define USART_CR3_CTSIE (1 << 10) /* Bit 10: CTS Interrupt Enable */
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/* Guard time and prescaler register */
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#define USART_GTPR_PSC_SHIFT (0) /* Bits 0-7: Prescaler value */
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#define USART_GTPR_PSC_MASK (0xff << USART_GTPR_PSC_SHIFT)
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#define USART_GTPR_GT_SHIFT (8) /* Bits 8-15: Guard time value */
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#define USART_GTPR_GT_MASK (0xff << USART_GTPR_GT_SHIFT)
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/* Compatibility definitions ********************************************************/
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/* F3 Transmit/Read registers */
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#define STM32_USART_RDR_OFFSET STM32_USART_DR_OFFSET /* Receive data register */
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#define STM32_USART_TDR_OFFSET STM32_USART_DR_OFFSET /* Transmit data register */
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/************************************************************************************
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* Public Types
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************************************************************************************/
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/************************************************************************************
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* Public Data
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************************************************************************************/
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/************************************************************************************
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* Public Functions
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************************************************************************************/
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#endif /* __ARCH_ARM_STC_STM32_CHIP_STM32F10XXX_UART_H */
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@ -1,7 +1,7 @@
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/************************************************************************************
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* arch/arm/src/stm32/chip/stm32_uart.h
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* arch/arm/src/stm32/chip/stm32f20xxx_uart.h
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*
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* Copyright (C) 2009, 2011-2012 Gregory Nutt. All rights reserved.
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* Copyright (C) 2009, 2011-2013 Gregory Nutt. All rights reserved.
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* Author: Gregory Nutt <gnutt@nuttx.org>
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*
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* Redistribution and use in source and binary forms, with or without
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@ -33,8 +33,8 @@
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*
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************************************************************************************/
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#ifndef __ARCH_ARM_STC_STM32_CHIP_STM32_UART_H
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#define __ARCH_ARM_STC_STM32_CHIP_STM32_UART_H
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#ifndef __ARCH_ARM_STC_STM32_CHIP_STM32F20XXX_UART_H
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#define __ARCH_ARM_STC_STM32_CHIP_STM32F20XXX_UART_H
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/************************************************************************************
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* Included Files
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@ -164,10 +164,7 @@
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#define USART_CR1_WAKE (1 << 11) /* Bit 11: Wakeup method */
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#define USART_CR1_M (1 << 12) /* Bit 12: word length */
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#define USART_CR1_UE (1 << 13) /* Bit 13: USART Enable */
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#if defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F40XX)
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# define USART_CR1_OVER8 (1 << 15) /* Bit 15: Oversampling mode */
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#endif
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#define USART_CR1_OVER8 (1 << 15) /* Bit 15: Oversampling mode */
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#define USART_CR1_ALLINTS (USART_CR1_IDLEIE|USART_CR1_RXNEIE|USART_CR1_TCIE|USART_CR1_PEIE)
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@ -202,10 +199,7 @@
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#define USART_CR3_RTSE (1 << 8) /* Bit 8: RTS Enable */
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#define USART_CR3_CTSE (1 << 9) /* Bit 9: CTS Enable */
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#define USART_CR3_CTSIE (1 << 10) /* Bit 10: CTS Interrupt Enable */
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#if defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F40XX)
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# define USART_CR1_ONEBIT (1 << 11) /* Bit 11: One sample bit method enable */
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#endif
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#define USART_CR1_ONEBIT (1 << 11) /* Bit 11: One sample bit method enable */
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/* Guard time and prescaler register */
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@ -214,6 +208,12 @@
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#define USART_GTPR_GT_SHIFT (8) /* Bits 8-15: Guard time value */
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#define USART_GTPR_GT_MASK (0xff << USART_GTPR_GT_SHIFT)
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/* Compatibility definitions ********************************************************/
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/* F3 Transmit/Read registers */
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#define STM32_USART_RDR_OFFSET STM32_USART_DR_OFFSET /* Receive data register */
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#define STM32_USART_TDR_OFFSET STM32_USART_DR_OFFSET /* Transmit data register */
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/************************************************************************************
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* Public Types
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************************************************************************************/
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@ -226,4 +226,4 @@
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* Public Functions
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************************************************************************************/
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#endif /* __ARCH_ARM_STC_STM32_CHIP_STM32_UART_H */
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#endif /* __ARCH_ARM_STC_STM32_CHIP_STM32F20XXX_UART_H */
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334
arch/arm/src/stm32/chip/stm32f30xxx_uart.h
Normal file
334
arch/arm/src/stm32/chip/stm32f30xxx_uart.h
Normal file
@ -0,0 +1,334 @@
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/************************************************************************************
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* arch/arm/src/stm32/chip/stm32f30xxx_uart.h
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*
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* Copyright (C) 2013 Gregory Nutt. All rights reserved.
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* Author: Gregory Nutt <gnutt@nuttx.org>
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*
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* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in
|
||||
* the documentation and/or other materials provided with the
|
||||
* distribution.
|
||||
* 3. Neither the name NuttX nor the names of its contributors may be
|
||||
* used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
|
||||
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
|
||||
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
|
||||
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
|
||||
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
|
||||
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
|
||||
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH DAMAGE.
|
||||
*
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************************************************************************************/
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#ifndef __ARCH_ARM_STC_STM32_CHIP_STM32F30XXX_UART_H
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#define __ARCH_ARM_STC_STM32_CHIP_STM32F30XXX_UART_H
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/************************************************************************************
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* Included Files
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************************************************************************************/
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#include <nuttx/config.h>
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#include "chip.h"
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/************************************************************************************
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* Pre-processor Definitions
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************************************************************************************/
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/* Register Offsets *****************************************************************/
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#define STM32_USART_CR1_OFFSET 0x0000 /* Control register 1 */
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#define STM32_USART_CR2_OFFSET 0x0004 /* Control register 2 */
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#define STM32_USART_CR3_OFFSET 0x0008 /* Control register 3 */
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#define STM32_USART_BRR_OFFSET 0x000c /* Baud Rate Register (32-bits) */
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#define STM32_USART_GTPR_OFFSET 0x0010 /* Guard time and prescaler register */
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#define STM32_USART_RTOR_OFFSET 0x0014 /* Receiver timeout register */
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#define STM32_USART_RQR_OFFSET 0x0018 /* Request register */
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#define STM32_USART_ISR_OFFSET 0x001c /* Interrupt & status register */
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#define STM32_USART_ICR_OFFSET 0x0020 /* Interrupt flag clear register */
|
||||
#define STM32_USART_RDR_OFFSET 0x0024 /* Receive data register */
|
||||
#define STM32_USART_TDR_OFFSET 0x0028 /* Transmit data register */
|
||||
|
||||
/* Register Addresses ***************************************************************/
|
||||
|
||||
#if STM32_NUSART > 0
|
||||
# define STM32_USART1_CR1 (STM32_USART1_BASE+STM32_USART_CR1_OFFSET)
|
||||
# define STM32_USART1_CR2 (STM32_USART1_BASE+STM32_USART_CR2_OFFSET)
|
||||
# define STM32_USART1_CR3 (STM32_USART1_BASE+STM32_USART_CR3_OFFSET)
|
||||
# define STM32_USART1_BRR (STM32_USART1_BASE+STM32_USART_BRR_OFFSET)
|
||||
# define STM32_USART1_GTPR (STM32_USART1_BASE+STM32_USART_GTPR_OFFSET)
|
||||
# define STM32_USART1_RTOR (STM32_USART1_BASE+STM32_USART_RTOR_OFFSET)
|
||||
# define STM32_USART1_RQR (STM32_USART1_BASE+STM32_USART_RQR_OFFSET)
|
||||
# define STM32_USART1_GTPR (STM32_USART1_BASE+STM32_USART_GTPR_OFFSET)
|
||||
# define STM32_USART1_ISR (STM32_USART1_BASE+STM32_USART_ISR_OFFSET)
|
||||
# define STM32_USART1_ICR (STM32_USART1_BASE+STM32_USART_ICR_OFFSET)
|
||||
# define STM32_USART1_RDR (STM32_USART1_BASE+STM32_USART_RDR_OFFSET)
|
||||
# define STM32_USART1_TDR (STM32_USART1_BASE+STM32_USART_TDR_OFFSET)
|
||||
#endif
|
||||
|
||||
#if STM32_NUSART > 1
|
||||
# define STM32_USART2_CR1 (STM32_USART2_BASE+STM32_USART_CR1_OFFSET)
|
||||
# define STM32_USART2_CR2 (STM32_USART2_BASE+STM32_USART_CR2_OFFSET)
|
||||
# define STM32_USART2_CR3 (STM32_USART2_BASE+STM32_USART_CR3_OFFSET)
|
||||
# define STM32_USART2_BRR (STM32_USART2_BASE+STM32_USART_BRR_OFFSET)
|
||||
# define STM32_USART2_GTPR (STM32_USART2_BASE+STM32_USART_GTPR_OFFSET)
|
||||
# define STM32_USART2_RTOR (STM32_USART2_BASE+STM32_USART_RTOR_OFFSET)
|
||||
# define STM32_USART2_RQR (STM32_USART2_BASE+STM32_USART_RQR_OFFSET)
|
||||
# define STM32_USART2_GTPR (STM32_USART2_BASE+STM32_USART_GTPR_OFFSET)
|
||||
# define STM32_USART2_ISR (STM32_USART2_BASE+STM32_USART_ISR_OFFSET)
|
||||
# define STM32_USART2_ICR (STM32_USART2_BASE+STM32_USART_ICR_OFFSET)
|
||||
# define STM32_USART2_RDR (STM32_USART2_BASE+STM32_USART_RDR_OFFSET)
|
||||
# define STM32_USART2_TDR (STM32_USART2_BASE+STM32_USART_TDR_OFFSET)
|
||||
#endif
|
||||
|
||||
#if STM32_NUSART > 2
|
||||
# define STM32_USART3_CR1 (STM32_USART3_BASE+STM32_USART_CR1_OFFSET)
|
||||
# define STM32_USART3_CR2 (STM32_USART3_BASE+STM32_USART_CR2_OFFSET)
|
||||
# define STM32_USART3_CR3 (STM32_USART3_BASE+STM32_USART_CR3_OFFSET)
|
||||
# define STM32_USART3_BRR (STM32_USART3_BASE+STM32_USART_BRR_OFFSET)
|
||||
# define STM32_USART3_GTPR (STM32_USART3_BASE+STM32_USART_GTPR_OFFSET)
|
||||
# define STM32_USART3_RTOR (STM32_USART3_BASE+STM32_USART_RTOR_OFFSET)
|
||||
# define STM32_USART3_RQR (STM32_USART3_BASE+STM32_USART_RQR_OFFSET)
|
||||
# define STM32_USART3_GTPR (STM32_USART3_BASE+STM32_USART_GTPR_OFFSET)
|
||||
# define STM32_USART3_ISR (STM32_USART3_BASE+STM32_USART_ISR_OFFSET)
|
||||
# define STM32_USART3_ICR (STM32_USART3_BASE+STM32_USART_ICR_OFFSET)
|
||||
# define STM32_USART3_RDR (STM32_USART3_BASE+STM32_USART_RDR_OFFSET)
|
||||
# define STM32_USART3_TDR (STM32_USART3_BASE+STM32_USART_TDR_OFFSET)
|
||||
#endif
|
||||
|
||||
#if STM32_NUSART > 3
|
||||
# define STM32_UART4_CR1 (STM32_UART4_BASE+STM32_USART_CR1_OFFSET)
|
||||
# define STM32_UART4_CR2 (STM32_UART4_BASE+STM32_USART_CR2_OFFSET)
|
||||
# define STM32_UART4_CR3 (STM32_UART4_BASE+STM32_USART_CR3_OFFSET)
|
||||
# define STM32_UART4_BRR (STM32_UART4_BASE+STM32_USART_BRR_OFFSET)
|
||||
# define STM32_UART4_GTPR (STM32_UART4_BASE+STM32_USART_GTPR_OFFSET)
|
||||
# define STM32_UART4_RTOR (STM32_UART4_BASE+STM32_USART_RTOR_OFFSET)
|
||||
# define STM32_UART4_RQR (STM32_UART4_BASE+STM32_USART_RQR_OFFSET)
|
||||
# define STM32_UART4_GTPR (STM32_UART4_BASE+STM32_USART_GTPR_OFFSET)
|
||||
# define STM32_UART4_ISR (STM32_UART4_BASE+STM32_USART_ISR_OFFSET)
|
||||
# define STM32_UART4_ICR (STM32_UART4_BASE+STM32_USART_ICR_OFFSET)
|
||||
# define STM32_UART4_RDR (STM32_UART4_BASE+STM32_USART_RDR_OFFSET)
|
||||
# define STM32_UART4_TDR (STM32_UART4_BASE+STM32_USART_TDR_OFFSET)
|
||||
#endif
|
||||
|
||||
#if STM32_NUSART > 4
|
||||
# define STM32_UART5_CR1 (STM32_UART5_BASE+STM32_USART_CR1_OFFSET)
|
||||
# define STM32_UART5_CR2 (STM32_UART5_BASE+STM32_USART_CR2_OFFSET)
|
||||
# define STM32_UART5_CR3 (STM32_UART5_BASE+STM32_USART_CR3_OFFSET)
|
||||
# define STM32_UART5_BRR (STM32_UART5_BASE+STM32_USART_BRR_OFFSET)
|
||||
# define STM32_UART5_GTPR (STM32_UART5_BASE+STM32_USART_GTPR_OFFSET)
|
||||
# define STM32_UART5_RTOR (STM32_UART5_BASE+STM32_USART_RTOR_OFFSET)
|
||||
# define STM32_UART5_RQR (STM32_UART5_BASE+STM32_USART_RQR_OFFSET)
|
||||
# define STM32_UART5_GTPR (STM32_UART5_BASE+STM32_USART_GTPR_OFFSET)
|
||||
# define STM32_UART5_ISR (STM32_UART5_BASE+STM32_USART_ISR_OFFSET)
|
||||
# define STM32_UART5_ICR (STM32_UART5_BASE+STM32_USART_ICR_OFFSET)
|
||||
# define STM32_UART5_RDR (STM32_UART5_BASE+STM32_USART_RDR_OFFSET)
|
||||
# define STM32_UART5_TDR (STM32_UART5_BASE+STM32_USART_TDR_OFFSET)
|
||||
#endif
|
||||
|
||||
/* Register Bitfield Definitions ****************************************************/
|
||||
|
||||
/* Control register 1 */
|
||||
|
||||
#define USART_CR1_UE (1 << 0) /* Bit 0: USART enable */
|
||||
#define USART_CR1_UESM (1 << 1) /* Bit 1: USART enable in Stop mode */
|
||||
#define USART_CR1_RE (1 << 2) /* Bit 2: Receiver Enable */
|
||||
#define USART_CR1_TE (1 << 3) /* Bit 3: Transmitter Enable */
|
||||
#define USART_CR1_IDLEIE (1 << 4) /* Bit 4: IDLE Interrupt Enable */
|
||||
#define USART_CR1_RXNEIE (1 << 5) /* Bit 5: RXNE Interrupt Enable */
|
||||
#define USART_CR1_TCIE (1 << 6) /* Bit 6: Transmission Complete Interrupt Enable */
|
||||
#define USART_CR1_TXEIE (1 << 7) /* Bit 7: TXE Interrupt Enable */
|
||||
#define USART_CR1_PEIE (1 << 8) /* Bit 8: PE Interrupt Enable */
|
||||
|
||||
#define USART_CR1_PS (1 << 9) /* Bit 9: Parity Selection */
|
||||
#define USART_CR1_PCE (1 << 10) /* Bit 10: Parity Control Enable */
|
||||
#define USART_CR1_WAKE (1 << 11) /* Bit 11: Receiver wakeup method */
|
||||
#define USART_CR1_M (1 << 12) /* Bit 12: Word length */
|
||||
#define USART_CR1_MME (1 << 13) /* Bit 13: Mute mode enable */
|
||||
#define USART_CR1_CMIE (1 << 14) /* Bit 14: Character match interrupt enable */
|
||||
#define USART_CR1_OVER8 (1 << 15) /* Bit 15: Oversampling mode */
|
||||
#define USART_CR1_DEDT_SHIFT (16) /* Bits 16-20: Driver Enable deassertion time */
|
||||
#define USART_CR1_DEDT_MASK (31 << USART_CR1_DEDT_SHIFT)
|
||||
#define USART_CR1_DEAT_SHIFT (21) /* Bits 21-25: Driver Enable assertion time */
|
||||
#define USART_CR1_DEAT_MASK (31 << USART_CR1_DEAT_SHIFT)
|
||||
#define USART_CR1_RTOIE (1 << 26) /* Bit 26: Receiver timeout interrupt enable */
|
||||
#define USART_CR1_EOBIE (1 << 27) /* Bit 27: End of Block interrupt enable */
|
||||
|
||||
#define USART_CR1_ALLINTS (USART_CR1_IDLEIE|USART_CR1_RXNEIE|USART_CR1_TCIE|USART_CR1_TXEIE|USART_CR1_PEIE|USART_CR1_CMIE|USART_CR1_RTOIE|USART_CR1_EOBIE)
|
||||
|
||||
/* Control register 2 */
|
||||
|
||||
#define USART_CR2_ADDM7 (1 << 4) /* Bit 4: :7-/4-bit Address Detection */
|
||||
#define USART_CR2_LBDL (1 << 5) /* Bit 5: LIN Break Detection Length */
|
||||
#define USART_CR2_LBDIE (1 << 6) /* Bit 6: LIN Break Detection Interrupt Enable */
|
||||
#define USART_CR2_LBCL (1 << 8) /* Bit 8: Last Bit Clock pulse */
|
||||
#define USART_CR2_CPHA (1 << 9) /* Bit 9: Clock Phase */
|
||||
#define USART_CR2_CPOL (1 << 10) /* Bit 10: Clock Polarity */
|
||||
#define USART_CR2_CLKEN (1 << 11) /* Bit 11: Clock Enable */
|
||||
#define USART_CR2_STOP_SHIFT (12) /* Bits 13-12: STOP bits */
|
||||
#define USART_CR2_STOP_MASK (3 << USART_CR2_STOP_SHIFT)
|
||||
# define USART_CR2_STOP1 (0 << USART_CR2_STOP_SHIFT) /* 00: 1 Stop bit */
|
||||
# define USART_CR2_STOP2 (2 << USART_CR2_STOP_SHIFT) /* 10: 2 Stop bits */
|
||||
# define USART_CR2_STOP1p5 (3 << USART_CR2_STOP_SHIFT) /* 11: 1.5 Stop bit */
|
||||
#define USART_CR2_LINEN (1 << 14) /* Bit 14: LIN mode enable */
|
||||
#define USART_CR2_RXINV (1 << 16) /* Bit 16: RX pin active level inversion */
|
||||
#define USART_CR2_TXINV (1 << 17) /* Bit 17: TX pin active level inversion */
|
||||
#define USART_CR2_DATAINV (1 << 18) /* Bit 18: Binary data inversion */
|
||||
#define USART_CR2_MSBFIRST (1 << 19) /* Bit 19: Most significant bit first */
|
||||
#define USART_CR2_ABREN (1 << 20) /* Bit 20: Auto baud rate enable */
|
||||
#define USART_CR2_ABRMOD_SHIFT (21) /* Bits 21-22: Auto baud rate mode */
|
||||
#define USART_CR2_ABRMOD_MASK (3 << USART_CR2_ABRMOD_SHIFT)
|
||||
# define USART_CR2_ABRMOD_START (0 << USART_CR2_ABRMOD_SHIFT) /* Start bit */
|
||||
# define USART_CR2_ABRMOD_FALL (1 << USART_CR2_ABRMOD_SHIFT) /* Falling edge measurement */
|
||||
# define USART_CR2_ABRMOD_7F (2 << USART_CR2_ABRMOD_SHIFT) /* 0x7F frame detection */
|
||||
# define USART_CR2_ABRMOD_55 (3 << USART_CR2_ABRMOD_SHIFT) /* 0x55 frame detection */
|
||||
#define USART_CR2_RTOEN (1 << 23) /* Bit 23: Receiver timeout enable */
|
||||
#define USART_CR2_ADD4L_SHIFT (24) /* Bits 24-17: Address[3:0]:of the USART node */
|
||||
#define USART_CR2_ADD4L_MASK (15 << USART_CR2_ADD4_SHIFT)
|
||||
#define USART_CR2_ADD4H_SHIFT (28) /* Bits 28-31: Address[4:0] of the USART node */
|
||||
#define USART_CR2_ADD4H_MASK (15 << USART_CR2_ADD4_SHIFT)
|
||||
#define USART_CR2_ADD8_SHIFT (24) /* Bits 24-31: Address[7:0] of the USART node */
|
||||
#define USART_CR2_ADD8_MASK (255 << USART_CR2_ADD8_SHIFT)
|
||||
|
||||
/* Control register 3 */
|
||||
|
||||
#define USART_CR3_EIE (1 << 0) /* Bit 0: Error Interrupt Enable */
|
||||
#define USART_CR3_IREN (1 << 1) /* Bit 1: IrDA mode Enable */
|
||||
#define USART_CR3_IRLP (1 << 2) /* Bit 2: IrDA Low-Power */
|
||||
#define USART_CR3_HDSEL (1 << 3) /* Bit 3: Half-Duplex Selection */
|
||||
#define USART_CR3_NACK (1 << 4) /* Bit 4: Smartcard NACK enable */
|
||||
#define USART_CR3_SCEN (1 << 5) /* Bit 5: Smartcard mode enable */
|
||||
#define USART_CR3_DMAR (1 << 6) /* Bit 6: DMA Enable Receiver */
|
||||
#define USART_CR3_DMAT (1 << 7) /* Bit 7: DMA Enable Transmitter */
|
||||
#define USART_CR3_RTSE (1 << 8) /* Bit 8: RTS Enable */
|
||||
#define USART_CR3_CTSE (1 << 9) /* Bit 9: CTS Enable */
|
||||
#define USART_CR3_CTSIE (1 << 10) /* Bit 10: CTS Interrupt Enable */
|
||||
#define USART_CR1_ONEBIT (1 << 11) /* Bit 11: One sample bit method enable */
|
||||
#define USART_CR1_OVRDIS (1 << 12) /* Bit 12: Overrun Disable */
|
||||
#define USART_CR1_DDRE (1 << 13) /* Bit 13: DMA Disable on Reception Error */
|
||||
#define USART_CR1_DEM (1 << 14) /* Bit 14: Driver enable mode */
|
||||
#define USART_CR1_DEP (1 << 15) /* Bit 15: Driver enable polarity selection */
|
||||
#define USART_CR1_SCARCNT_SHIFT (17) /* Bit 17-19: Smartcard auto-retry count */
|
||||
#define USART_CR1_SCARCNT_MASK (7 << USART_CR1_SCARCNT_SHIFT)
|
||||
#define USART_CR1_WUS_SHIFT (20) /* Bit 20-21: Wakeup from Stop mode interrupt */
|
||||
#define USART_CR1_WUS_MASK (3 << USART_CR1_WUS_SHIFT)
|
||||
# define USART_CR1_WUS_ADDRMAT (0 << USART_CR1_WUS_SHIFT) /* Active on address match */
|
||||
# define USART_CR1_WUS_STARTBIT (2 << USART_CR1_WUS_SHIFT) /* Active on Start bit */
|
||||
# define USART_CR1_WUS_RXNE (3 << USART_CR1_WUS_SHIFT) /* Active on RXNE */
|
||||
#define USART_CR1_WUFIE (1 << 22) /* Bit 22: Wakeup from Stop mode interrupt enable */
|
||||
|
||||
/* Baud Rate Register */
|
||||
|
||||
#define USART_BRR_SHIFT (0) /* Bits 0-15: USARTDIV[15:0] OVER8=0*/
|
||||
#define USART_BRR_MASK (0xffff << USART_BRR_SHIFT)
|
||||
#define USART_BRR_0_3_SHIFT (0) /* Bits 0-2: USARTDIV[3:0] OVER8=1 */
|
||||
#define USART_BRR_0_3_MASK (0x0fff << USART_BRR_0_3_SHIFT)
|
||||
#define USART_BRR_4_7_SHIFT (0) /* Bits 4-15: USARTDIV[15:4] OVER8=1*/
|
||||
#define USART_BRR_4_7_MASK (0xffff << USART_BRR_4_7_SHIFT)
|
||||
|
||||
/* Guard time and prescaler register */
|
||||
|
||||
#define USART_GTPR_PSC_SHIFT (0) /* Bits 0-7: Prescaler value */
|
||||
#define USART_GTPR_PSC_MASK (0xff << USART_GTPR_PSC_SHIFT)
|
||||
#define USART_GTPR_GT_SHIFT (8) /* Bits 8-15: Guard time value */
|
||||
#define USART_GTPR_GT_MASK (0xff << USART_GTPR_GT_SHIFT)
|
||||
|
||||
/* Receiver timeout register */
|
||||
|
||||
#define USART_RTOR_RTO_SHIFT (0) /* Bits 0-23: Receiver timeout value */
|
||||
#define USART_RTOR_RTO_MASK (0xffffff << USART_RTOR_RTO_SHIFT)
|
||||
#define USART_RTOR_BLEN_SHIFT (24) /* Bits 24-31: Block Length */
|
||||
#define USART_RTOR_BLEN_MASK (0xff << USART_RTOR_BLEN_SHIFT)
|
||||
|
||||
/* Request register */
|
||||
|
||||
#define USART_RQR_ABRRQ (1 << 0) /* Bit 0: Auto baud rate request */
|
||||
#define USART_RQR_SBKRQ (1 << 1) /* Bit 1: Send break request */
|
||||
#define USART_RQR_MMRQ (1 << 2) /* Bit 2: Mute mode request */
|
||||
#define USART_RQR_RXFRQ (1 << 3) /* Bit 3: Receive data flush request */
|
||||
#define USART_RQR_TXFRQ (1 << 4) /* Bit 4: Transmit data flush request */
|
||||
|
||||
/* Interrupt & status register */
|
||||
|
||||
#define USART_ISR_PE (1 << 0) /* Bit 0: Parity error */
|
||||
#define USART_ISR_FE (1 << 1) /* Bit 1: Framing error */
|
||||
#define USART_ISR_NF (1 << 2) /* Bit 2: Noise detected flag */
|
||||
#define USART_ISR_ORE (1 << 3) /* Bit 3: Overrun error */
|
||||
#define USART_ISR_IDLE (1 << 4) /* Bit 4: Idle line detected */
|
||||
#define USART_ISR_RXNE (1 << 5) /* Bit 5: Read data register not empty */
|
||||
#define USART_ISR_TC (1 << 6) /* Bit 6: Transmission complete */
|
||||
#define USART_ISR_TXE (1 << 7) /* Bit 7: Transmit data register empty */
|
||||
#define USART_ISR_LBDF (1 << 8) /* Bit 8: LIN break detection flag */
|
||||
#define USART_ISR_CTSIF (1 << 9) /* Bit 9: CTS interrupt flag */
|
||||
#define USART_ISR_CTS (1 << 10) /* Bit 10: CTS flag */
|
||||
#define USART_ISR_RTOF (1 << 11) /* Bit 11: Receiver timeout */
|
||||
#define USART_ISR_EOBF (1 << 12) /* Bit 12: End of block flag */
|
||||
#define USART_ISR_ABRE (1 << 14) /* Bit 14: Auto baud rate error */
|
||||
#define USART_ISR_ABRF (1 << 15) /* Bit 15: Auto baud rate flag */
|
||||
#define USART_ISR_BUSY (1 << 16) /* Bit 16: Busy flag */
|
||||
#define USART_ISR_CMF (1 << 17) /* Bit 17: Character match flag */
|
||||
#define USART_ISR_SBKF (1 << 18) /* Bit 18: Send break flag */
|
||||
#define USART_ISR_ISRRWU (1 << 19) /* Bit 19: Receiver wakeup from Mute mode */
|
||||
#define USART_ISR_WUF (1 << 20) /* Bit 20: Wakeup from Stop mode flag */
|
||||
#define USART_ISR_TEACK (1 << 21) /* Bit 21: Transmit enable acknowledge flag */
|
||||
#define USART_ISR_REACK (1 << 22) /* Bit 22: Receive enable acknowledge flag */
|
||||
|
||||
#define USART_ISR_ALLBITS (0x007fdfff)
|
||||
|
||||
/* Interrupt flag clear register */
|
||||
#define USART_ICR_
|
||||
/* Receive data register */
|
||||
#define USART_RDR_
|
||||
/* Transmit data register */
|
||||
#define USART_TDR_
|
||||
|
||||
|
||||
/* Data register */
|
||||
|
||||
#define USART_DR_SHIFT (0) /* Bits 8:0: Data value */
|
||||
#define USART_DR_MASK (0xff << USART_DR_SHIFT)
|
||||
|
||||
/* Compatibility definitions ********************************************************/
|
||||
/* F1/F2/F4 Status register */
|
||||
|
||||
#define STM32_USART_SR_OFFSET STM32_USART_ISR_OFFSET
|
||||
|
||||
#define USART_SR_PE USART_ISR_PE /* Parity Error */
|
||||
#define USART_SR_FE USART_ISR_FE /* Framing error */
|
||||
#define USART_SR_NE USART_ISR_NF /* Noise detected flag */
|
||||
#define USART_SR_ORE USART_ISR_ORE /* Overrun error */
|
||||
#define USART_SR_IDLE USART_ISR_IDLE /* IDLE line detected */
|
||||
#define USART_SR_RXNE USART_ISR_RXNE /* Read Data Register Not Empty */
|
||||
#define USART_SR_TC USART_ISR_TC /* Transmission Complete */
|
||||
#define USART_SR_TXE USART_ISR_TXE /* Transmit Data Register Empty */
|
||||
#define USART_SR_LBD USART_ISR_LBDF /* LIN Break Detection Flag */
|
||||
#define USART_SR_CTS USART_ISR_CTS /* Bit 9: CTS Flag */
|
||||
|
||||
#define USART_SR_ALLBITS USART_ISR_ALLBITS
|
||||
|
||||
/************************************************************************************
|
||||
* Public Types
|
||||
************************************************************************************/
|
||||
|
||||
/************************************************************************************
|
||||
* Public Data
|
||||
************************************************************************************/
|
||||
|
||||
/************************************************************************************
|
||||
* Public Functions
|
||||
************************************************************************************/
|
||||
|
||||
#endif /* __ARCH_ARM_STC_STM32_CHIP_STM32F30XXX_UART_H */
|
||||
229
arch/arm/src/stm32/chip/stm32f40xxx_uart.h
Normal file
229
arch/arm/src/stm32/chip/stm32f40xxx_uart.h
Normal file
@ -0,0 +1,229 @@
|
||||
/************************************************************************************
|
||||
* arch/arm/src/stm32/chip/stm32f40xxx_uart.h
|
||||
*
|
||||
* Copyright (C) 2009, 2011-2014 Gregory Nutt. All rights reserved.
|
||||
* Author: Gregory Nutt <gnutt@nuttx.org>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in
|
||||
* the documentation and/or other materials provided with the
|
||||
* distribution.
|
||||
* 3. Neither the name NuttX nor the names of its contributors may be
|
||||
* used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
|
||||
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
|
||||
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
|
||||
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
|
||||
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
|
||||
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
|
||||
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
************************************************************************************/
|
||||
|
||||
#ifndef __ARCH_ARM_STC_STM32_CHIP_STM32F40XXX_UART_H
|
||||
#define __ARCH_ARM_STC_STM32_CHIP_STM32F40XXX_UART_H
|
||||
|
||||
/************************************************************************************
|
||||
* Included Files
|
||||
************************************************************************************/
|
||||
|
||||
#include <nuttx/config.h>
|
||||
|
||||
#include "chip.h"
|
||||
|
||||
/************************************************************************************
|
||||
* Pre-processor Definitions
|
||||
************************************************************************************/
|
||||
|
||||
/* Register Offsets *****************************************************************/
|
||||
|
||||
#define STM32_USART_SR_OFFSET 0x0000 /* Status register (32-bits) */
|
||||
#define STM32_USART_DR_OFFSET 0x0004 /* Data register (32-bits) */
|
||||
#define STM32_USART_BRR_OFFSET 0x0008 /* Baud Rate Register (32-bits) */
|
||||
#define STM32_USART_CR1_OFFSET 0x000c /* Control register 1 (32-bits) */
|
||||
#define STM32_USART_CR2_OFFSET 0x0010 /* Control register 2 (32-bits) */
|
||||
#define STM32_USART_CR3_OFFSET 0x0014 /* Control register 3 (32-bits) */
|
||||
#define STM32_USART_GTPR_OFFSET 0x0018 /* Guard time and prescaler register (32-bits) */
|
||||
|
||||
/* Register Addresses ***************************************************************/
|
||||
|
||||
#if STM32_NUSART > 0
|
||||
# define STM32_USART1_SR (STM32_USART1_BASE+STM32_USART_SR_OFFSET)
|
||||
# define STM32_USART1_DR (STM32_USART1_BASE+STM32_USART_DR_OFFSET)
|
||||
# define STM32_USART1_BRR (STM32_USART1_BASE+STM32_USART_BRR_OFFSET)
|
||||
# define STM32_USART1_CR1 (STM32_USART1_BASE+STM32_USART_CR1_OFFSET)
|
||||
# define STM32_USART1_CR2 (STM32_USART1_BASE+STM32_USART_CR2_OFFSET)
|
||||
# define STM32_USART1_CR3 (STM32_USART1_BASE+STM32_USART_CR3_OFFSET)
|
||||
# define STM32_USART1_GTPR (STM32_USART1_BASE+STM32_USART_GTPR_OFFSET)
|
||||
#endif
|
||||
|
||||
#if STM32_NUSART > 1
|
||||
# define STM32_USART2_SR (STM32_USART2_BASE+STM32_USART_SR_OFFSET)
|
||||
# define STM32_USART2_DR (STM32_USART2_BASE+STM32_USART_DR_OFFSET)
|
||||
# define STM32_USART2_BRR (STM32_USART2_BASE+STM32_USART_BRR_OFFSET)
|
||||
# define STM32_USART2_CR1 (STM32_USART2_BASE+STM32_USART_CR1_OFFSET)
|
||||
# define STM32_USART2_CR2 (STM32_USART2_BASE+STM32_USART_CR2_OFFSET)
|
||||
# define STM32_USART2_CR3 (STM32_USART2_BASE+STM32_USART_CR3_OFFSET)
|
||||
# define STM32_USART2_GTPR (STM32_USART2_BASE+STM32_USART_GTPR_OFFSET)
|
||||
#endif
|
||||
|
||||
#if STM32_NUSART > 2
|
||||
# define STM32_USART3_SR (STM32_USART3_BASE+STM32_USART_SR_OFFSET)
|
||||
# define STM32_USART3_DR (STM32_USART3_BASE+STM32_USART_DR_OFFSET)
|
||||
# define STM32_USART3_BRR (STM32_USART3_BASE+STM32_USART_BRR_OFFSET)
|
||||
# define STM32_USART3_CR1 (STM32_USART3_BASE+STM32_USART_CR1_OFFSET)
|
||||
# define STM32_USART3_CR2 (STM32_USART3_BASE+STM32_USART_CR2_OFFSET)
|
||||
# define STM32_USART3_CR3 (STM32_USART3_BASE+STM32_USART_CR3_OFFSET)
|
||||
# define STM32_USART3_GTPR (STM32_USART3_BASE+STM32_USART_GTPR_OFFSET)
|
||||
#endif
|
||||
|
||||
#if STM32_NUSART > 3
|
||||
# define STM32_UART4_SR (STM32_UART4_BASE+STM32_USART_SR_OFFSET)
|
||||
# define STM32_UART4_DR (STM32_UART4_BASE+STM32_USART_DR_OFFSET)
|
||||
# define STM32_UART4_BRR (STM32_UART4_BASE+STM32_USART_BRR_OFFSET)
|
||||
# define STM32_UART4_CR1 (STM32_UART4_BASE+STM32_USART_CR1_OFFSET)
|
||||
# define STM32_UART4_CR2 (STM32_UART4_BASE+STM32_USART_CR2_OFFSET)
|
||||
# define STM32_UART4_CR3 (STM32_UART4_BASE+STM32_USART_CR3_OFFSET)
|
||||
#endif
|
||||
|
||||
#if STM32_NUSART > 4
|
||||
# define STM32_UART5_SR (STM32_UART5_BASE+STM32_USART_SR_OFFSET)
|
||||
# define STM32_UART5_DR (STM32_UART5_BASE+STM32_USART_DR_OFFSET)
|
||||
# define STM32_UART5_BRR (STM32_UART5_BASE+STM32_USART_BRR_OFFSET)
|
||||
# define STM32_UART5_CR1 (STM32_UART5_BASE+STM32_USART_CR1_OFFSET)
|
||||
# define STM32_UART5_CR2 (STM32_UART5_BASE+STM32_USART_CR2_OFFSET)
|
||||
# define STM32_UART5_CR3 (STM32_UART5_BASE+STM32_USART_CR3_OFFSET)
|
||||
#endif
|
||||
|
||||
#if STM32_NUSART > 5
|
||||
# define STM32_USART6_SR (STM32_USART6_BASE+STM32_USART_SR_OFFSET)
|
||||
# define STM32_USART6_DR (STM32_USART6_BASE+STM32_USART_DR_OFFSET)
|
||||
# define STM32_USART6_BRR (STM32_USART6_BASE+STM32_USART_BRR_OFFSET)
|
||||
# define STM32_USART6_CR1 (STM32_USART6_BASE+STM32_USART_CR1_OFFSET)
|
||||
# define STM32_USART6_CR2 (STM32_USART6_BASE+STM32_USART_CR2_OFFSET)
|
||||
# define STM32_USART6_CR3 (STM32_USART6_BASE+STM32_USART_CR3_OFFSET)
|
||||
# define STM32_USART6_GTPR (STM32_USART6_BASE+STM32_USART_GTPR_OFFSET)
|
||||
#endif
|
||||
|
||||
/* Register Bitfield Definitions ****************************************************/
|
||||
|
||||
/* Status register */
|
||||
|
||||
#define USART_SR_PE (1 << 0) /* Bit 0: Parity Error */
|
||||
#define USART_SR_FE (1 << 1) /* Bit 1: Framing Error */
|
||||
#define USART_SR_NE (1 << 2) /* Bit 2: Noise Error Flag */
|
||||
#define USART_SR_ORE (1 << 3) /* Bit 3: OverRun Error */
|
||||
#define USART_SR_IDLE (1 << 4) /* Bit 4: IDLE line detected */
|
||||
#define USART_SR_RXNE (1 << 5) /* Bit 5: Read Data Register Not Empty */
|
||||
#define USART_SR_TC (1 << 6) /* Bit 6: Transmission Complete */
|
||||
#define USART_SR_TXE (1 << 7) /* Bit 7: Transmit Data Register Empty */
|
||||
#define USART_SR_LBD (1 << 8) /* Bit 8: LIN Break Detection Flag */
|
||||
#define USART_SR_CTS (1 << 9) /* Bit 9: CTS Flag */
|
||||
|
||||
#define USART_SR_ALLBITS (0x03ff)
|
||||
#define USART_SR_CLRBITS (USART_SR_CTS|USART_SR_LBD) /* Cleared by SW write to SR */
|
||||
|
||||
/* Data register */
|
||||
|
||||
#define USART_DR_SHIFT (0) /* Bits 8:0: Data value */
|
||||
#define USART_DR_MASK (0xff << USART_DR_SHIFT)
|
||||
|
||||
/* Baud Rate Register */
|
||||
|
||||
#define USART_BRR_FRAC_SHIFT (0) /* Bits 3-0: fraction of USARTDIV */
|
||||
#define USART_BRR_FRAC_MASK (0x0f << USART_BRR_FRAC_SHIFT)
|
||||
#define USART_BRR_MANT_SHIFT (4) /* Bits 15-4: mantissa of USARTDIV */
|
||||
#define USART_BRR_MANT_MASK (0x0fff << USART_BRR_MANT_SHIFT)
|
||||
|
||||
/* Control register 1 */
|
||||
|
||||
#define USART_CR1_SBK (1 << 0) /* Bit 0: Send Break */
|
||||
#define USART_CR1_RWU (1 << 1) /* Bit 1: Receiver wakeup */
|
||||
#define USART_CR1_RE (1 << 2) /* Bit 2: Receiver Enable */
|
||||
#define USART_CR1_TE (1 << 3) /* Bit 3: Transmitter Enable */
|
||||
#define USART_CR1_IDLEIE (1 << 4) /* Bit 4: IDLE Interrupt Enable */
|
||||
#define USART_CR1_RXNEIE (1 << 5) /* Bit 5: RXNE Interrupt Enable */
|
||||
#define USART_CR1_TCIE (1 << 6) /* Bit 6: Transmission Complete Interrupt Enable */
|
||||
#define USART_CR1_TXEIE (1 << 7) /* Bit 7: TXE Interrupt Enable */
|
||||
#define USART_CR1_PEIE (1 << 8) /* Bit 8: PE Interrupt Enable */
|
||||
#define USART_CR1_PS (1 << 9) /* Bit 9: Parity Selection */
|
||||
#define USART_CR1_PCE (1 << 10) /* Bit 10: Parity Control Enable */
|
||||
#define USART_CR1_WAKE (1 << 11) /* Bit 11: Wakeup method */
|
||||
#define USART_CR1_M (1 << 12) /* Bit 12: word length */
|
||||
#define USART_CR1_UE (1 << 13) /* Bit 13: USART Enable */
|
||||
#define USART_CR1_OVER8 (1 << 15) /* Bit 15: Oversampling mode */
|
||||
|
||||
#define USART_CR1_ALLINTS (USART_CR1_IDLEIE|USART_CR1_RXNEIE|USART_CR1_TCIE|USART_CR1_PEIE)
|
||||
|
||||
/* Control register 2 */
|
||||
|
||||
#define USART_CR2_ADD_SHIFT (0) /* Bits 3-0: Address of the USART node */
|
||||
#define USART_CR2_ADD_MASK (0x0f << USART_CR2_ADD_SHIFT)
|
||||
#define USART_CR2_LBDL (1 << 5) /* Bit 5: LIN Break Detection Length */
|
||||
#define USART_CR2_LBDIE (1 << 6) /* Bit 6: LIN Break Detection Interrupt Enable */
|
||||
#define USART_CR2_LBCL (1 << 8) /* Bit 8: Last Bit Clock pulse */
|
||||
#define USART_CR2_CPHA (1 << 9) /* Bit 9: Clock Phase */
|
||||
#define USART_CR2_CPOL (1 << 10) /* Bit 10: Clock Polarity */
|
||||
#define USART_CR2_CLKEN (1 << 11) /* Bit 11: Clock Enable */
|
||||
#define USART_CR2_STOP_SHIFT (12) /* Bits 13-12: STOP bits */
|
||||
#define USART_CR2_STOP_MASK (3 << USART_CR2_STOP_SHIFT)
|
||||
# define USART_CR2_STOP1 (0 << USART_CR2_STOP_SHIFT) /* 00: 1 Stop bit */
|
||||
# define USART_CR2_STOP0p5 (1 << USART_CR2_STOP_SHIFT) /* 01: 0.5 Stop bit */
|
||||
# define USART_CR2_STOP2 (2 << USART_CR2_STOP_SHIFT) /* 10: 2 Stop bits */
|
||||
# define USART_CR2_STOP1p5 (3 << USART_CR2_STOP_SHIFT) /* 11: 1.5 Stop bit */
|
||||
#define USART_CR2_LINEN (1 << 14) /* Bit 14: LIN mode enable */
|
||||
|
||||
/* Control register 3 */
|
||||
|
||||
#define USART_CR3_EIE (1 << 0) /* Bit 0: Error Interrupt Enable */
|
||||
#define USART_CR3_IREN (1 << 1) /* Bit 1: IrDA mode Enable */
|
||||
#define USART_CR3_IRLP (1 << 2) /* Bit 2: IrDA Low-Power */
|
||||
#define USART_CR3_HDSEL (1 << 3) /* Bit 3: Half-Duplex Selection */
|
||||
#define USART_CR3_NACK (1 << 4) /* Bit 4: Smartcard NACK enable */
|
||||
#define USART_CR3_SCEN (1 << 5) /* Bit 5: Smartcard mode enable */
|
||||
#define USART_CR3_DMAR (1 << 6) /* Bit 6: DMA Enable Receiver */
|
||||
#define USART_CR3_DMAT (1 << 7) /* Bit 7: DMA Enable Transmitter */
|
||||
#define USART_CR3_RTSE (1 << 8) /* Bit 8: RTS Enable */
|
||||
#define USART_CR3_CTSE (1 << 9) /* Bit 9: CTS Enable */
|
||||
#define USART_CR3_CTSIE (1 << 10) /* Bit 10: CTS Interrupt Enable */
|
||||
#define USART_CR1_ONEBIT (1 << 11) /* Bit 11: One sample bit method enable */
|
||||
|
||||
/* Guard time and prescaler register */
|
||||
|
||||
#define USART_GTPR_PSC_SHIFT (0) /* Bits 0-7: Prescaler value */
|
||||
#define USART_GTPR_PSC_MASK (0xff << USART_GTPR_PSC_SHIFT)
|
||||
#define USART_GTPR_GT_SHIFT (8) /* Bits 8-15: Guard time value */
|
||||
#define USART_GTPR_GT_MASK (0xff << USART_GTPR_GT_SHIFT)
|
||||
|
||||
/* Compatibility definitions ********************************************************/
|
||||
/* F3 Transmit/Read registers */
|
||||
|
||||
#define STM32_USART_RDR_OFFSET STM32_USART_DR_OFFSET /* Receive data register */
|
||||
#define STM32_USART_TDR_OFFSET STM32_USART_DR_OFFSET /* Transmit data register */
|
||||
|
||||
/************************************************************************************
|
||||
* Public Types
|
||||
************************************************************************************/
|
||||
|
||||
/************************************************************************************
|
||||
* Public Data
|
||||
************************************************************************************/
|
||||
|
||||
/************************************************************************************
|
||||
* Public Functions
|
||||
************************************************************************************/
|
||||
|
||||
#endif /* __ARCH_ARM_STC_STM32_CHIP_STM32F40XXX_UART_H */
|
||||
@ -197,48 +197,89 @@
|
||||
#define USART_CR3_CLRBITS (USART_CR3_CTSIE|USART_CR3_CTSE|USART_CR3_RTSE|USART_CR3_EIE)
|
||||
#define USART_CR3_SETBITS 0
|
||||
|
||||
/* Calculate USART BAUD rate divider
|
||||
*
|
||||
* The baud rate for the receiver and transmitter (Rx and Tx) are both set to
|
||||
* the same value as programmed in the Mantissa and Fraction values of USARTDIV.
|
||||
*
|
||||
* baud = fCK / (16 * usartdiv)
|
||||
* usartdiv = fCK / (16 * baud)
|
||||
*
|
||||
* Where fCK is the input clock to the peripheral (PCLK1 for USART2, 3, 4, 5
|
||||
* or PCLK2 for USART1). Example, fCK=72MHz baud=115200, usartdiv=39.0625=39 1/16th;
|
||||
*
|
||||
* First calculate:
|
||||
*
|
||||
* usartdiv32 = 32 * usartdiv = fCK / (baud/2)
|
||||
*
|
||||
* (NOTE: all standard baud values are even so dividing by two does not
|
||||
* lose precision). Eg. (same fCK and buad), usartdiv32 = 1250
|
||||
*/
|
||||
/* Only the STM32 F3 supports oversampling by 8 */
|
||||
|
||||
#define STM32_USARTDIV32 (STM32_APBCLOCK / (STM32_CONSOLE_BAUD >> 1))
|
||||
#undef USE_OVER8
|
||||
|
||||
/* The mantissa is then usartdiv32 / 32:
|
||||
*
|
||||
* mantissa = usartdiv32 / 32/
|
||||
*
|
||||
* Eg. usartdiv32=1250, mantissa = 39
|
||||
*/
|
||||
/* Calculate USART BAUD rate divider */
|
||||
|
||||
#define STM32_MANTISSA (STM32_USARTDIV32 >> 5)
|
||||
#ifdef CONFIG_STM32_STM32F30XX
|
||||
|
||||
/* And the fraction:
|
||||
*
|
||||
* fraction = (usartdiv32 - mantissa*32 + 1) / 2
|
||||
*
|
||||
* Eg., (1,250 - 39*32 + 1)/2 = 1 (or 0.0625)
|
||||
*/
|
||||
/* Baud rate for standard USART (SPI mode included):
|
||||
*
|
||||
* In case of oversampling by 16, the equation is:
|
||||
* baud = fCK / UARTDIV
|
||||
* UARTDIV = fCK / baud
|
||||
*
|
||||
* In case of oversampling by 8, the equation is:
|
||||
*
|
||||
* baud = 2 * fCK / UARTDIV
|
||||
* UARTDIV = 2 * fCK / baud
|
||||
*/
|
||||
|
||||
#define STM32_FRACTION ((STM32_USARTDIV32 - (STM32_MANTISSA << 5) + 1) >> 1)
|
||||
# define STM32_USARTDIV8 \
|
||||
(((STM32_APBCLOCK << 1) + (STM32_CONSOLE_BAUD >> 1)) / STM32_CONSOLE_BAUD)
|
||||
# define STM32_USARTDIV16 \
|
||||
((STM32_APBCLOCK + (STM32_CONSOLE_BAUD >> 1)) / STM32_CONSOLE_BAUD)
|
||||
|
||||
/* Use oversamply by 8 only if the divisor is small */
|
||||
|
||||
# if STM32_USARTDIV8 > 100
|
||||
# define STM32_BRR_VALUE STM32_USARTDIV16
|
||||
# else
|
||||
# define USE_OVER8 1
|
||||
# define STM32_BRR_VALUE \
|
||||
((STM32_USARTDIV8 && 0xfff0) | ((STM32_USARTDIV8 & 0x000f) >> 1)
|
||||
# endif
|
||||
|
||||
#else
|
||||
|
||||
/* The baud rate for the receiver and transmitter (Rx and Tx) are both set
|
||||
* to the same value as programmed in the Mantissa and Fraction values of
|
||||
* USARTDIV.
|
||||
*
|
||||
* baud = fCK / (16 * usartdiv)
|
||||
* usartdiv = fCK / (16 * baud)
|
||||
*
|
||||
* Where fCK is the input clock to the peripheral (PCLK1 for USART2, 3, 4,
|
||||
* 5 or PCLK2 for USART1). Example, fCK=72MHz baud=115200,
|
||||
* usartdiv=39.0625=39 1/16th;
|
||||
*
|
||||
* First calculate:
|
||||
*
|
||||
* usartdiv32 = 32 * usartdiv = fCK / (baud/2)
|
||||
*
|
||||
* (NOTE: all standard baud values are even so dividing by two does not
|
||||
* lose precision). Eg. (same fCK and buad), usartdiv32 = 1250
|
||||
*/
|
||||
|
||||
# define STM32_USARTDIV32 (STM32_APBCLOCK / (STM32_CONSOLE_BAUD >> 1))
|
||||
|
||||
/* The mantissa is then usartdiv32 / 32:
|
||||
*
|
||||
* mantissa = usartdiv32 / 32/
|
||||
*
|
||||
* Eg. usartdiv32=1250, mantissa = 39
|
||||
*/
|
||||
|
||||
# define STM32_MANTISSA (STM32_USARTDIV32 >> 5)
|
||||
|
||||
/* And the fraction:
|
||||
*
|
||||
* fraction = (usartdiv32 - mantissa*32 + 1) / 2
|
||||
*
|
||||
* Eg., (1,250 - 39*32 + 1)/2 = 1 (or 0.0625)
|
||||
*/
|
||||
|
||||
# define STM32_FRACTION \
|
||||
((STM32_USARTDIV32 - (STM32_MANTISSA << 5) + 1) >> 1)
|
||||
|
||||
/* And, finally, the BRR value is: */
|
||||
|
||||
#define STM32_BRR_VALUE ((STM32_MANTISSA << USART_BRR_MANT_SHIFT) | (STM32_FRACTION << USART_BRR_FRAC_SHIFT))
|
||||
# define STM32_BRR_VALUE \
|
||||
((STM32_MANTISSA << USART_BRR_MANT_SHIFT) | \
|
||||
(STM32_FRACTION << USART_BRR_FRAC_SHIFT))
|
||||
#endif
|
||||
|
||||
/**************************************************************************
|
||||
* Private Types
|
||||
@ -284,7 +325,7 @@ void up_lowputc(char ch)
|
||||
|
||||
/* Then send the character */
|
||||
|
||||
putreg32((uint32_t)ch, STM32_CONSOLE_BASE + STM32_USART_DR_OFFSET);
|
||||
putreg32((uint32_t)ch, STM32_CONSOLE_BASE + STM32_USART_TDR_OFFSET);
|
||||
|
||||
#if STM32_CONSOLE_RS485_DIR
|
||||
while ((getreg32(STM32_CONSOLE_BASE + STM32_USART_SR_OFFSET) & USART_SR_TC) == 0);
|
||||
@ -305,6 +346,7 @@ void up_lowputc(char ch)
|
||||
**************************************************************************/
|
||||
|
||||
#if defined(CONFIG_STM32_STM32F10XX)
|
||||
|
||||
void stm32_lowsetup(void)
|
||||
{
|
||||
#if defined(HAVE_UART)
|
||||
@ -423,6 +465,14 @@ void stm32_lowsetup(void)
|
||||
|
||||
putreg32(STM32_BRR_VALUE, STM32_CONSOLE_BASE + STM32_USART_BRR_OFFSET);
|
||||
|
||||
/* Select oversampling by 8 */
|
||||
|
||||
#ifdef USE_OVER8
|
||||
cr = getreg32(STM32_CONSOLE_BASE + STM32_USART_CR1_OFFSET);
|
||||
cr |= USART_CR1_OVER8;
|
||||
putreg32(cr, STM32_CONSOLE_BASE + STM32_USART_CR1_OFFSET);
|
||||
#endif
|
||||
|
||||
/* Enable Rx, Tx, and the USART */
|
||||
|
||||
cr = getreg32(STM32_CONSOLE_BASE + STM32_USART_CR1_OFFSET);
|
||||
@ -431,7 +481,9 @@ void stm32_lowsetup(void)
|
||||
#endif
|
||||
#endif /* HAVE_UART */
|
||||
}
|
||||
|
||||
#elif defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F30XX) || defined(CONFIG_STM32_STM32F40XX)
|
||||
|
||||
void stm32_lowsetup(void)
|
||||
{
|
||||
#if defined(HAVE_UART)
|
||||
@ -492,6 +544,7 @@ void stm32_lowsetup(void)
|
||||
#endif
|
||||
#endif /* HAVE_UART */
|
||||
}
|
||||
|
||||
#else
|
||||
# error "Unsupported STM32 chip"
|
||||
#endif
|
||||
|
||||
@ -43,7 +43,18 @@
|
||||
#include <nuttx/config.h>
|
||||
|
||||
#include "chip.h"
|
||||
#include "chip/stm32_uart.h"
|
||||
|
||||
#if defined(CONFIG_STM32_STM32F10XX)
|
||||
# include "chip/stm32f10xxx_uart.h"
|
||||
#elif defined(CONFIG_STM32_STM32F20XX)
|
||||
# include "chip/stm32f20xxx_uart.h"
|
||||
#elif defined(CONFIG_STM32_STM32F30XX)
|
||||
# include "chip/stm32f30xxx_uart.h"
|
||||
#elif defined(CONFIG_STM32_STM32F40XX)
|
||||
# include "chip/stm32f40xxx_uart.h"
|
||||
#else
|
||||
# error "Unsupported STM32 memory map"
|
||||
#endif
|
||||
|
||||
/************************************************************************************
|
||||
* Pre-processor Definitions
|
||||
|
||||
@ -122,7 +122,8 @@ static inline void rcc_enableahb(void)
|
||||
|
||||
regval = RCC_AHBENR_FLITFEN | RCC_AHBENR_SRAMEN;
|
||||
|
||||
/* Enable GPIOA, GPIOB, ... and AFIO clocks */
|
||||
/* Enable GPIO PORTA, PORTB, ... PORTF */
|
||||
|
||||
regval |= (RCC_AHBENR_IOPAEN | RCC_AHBENR_IOPBEN | RCC_AHBENR_IOPCEN |
|
||||
RCC_AHBENR_IOPDEN | RCC_AHBENR_IOPEEN | RCC_AHBENR_IOPFEN);
|
||||
|
||||
|
||||
Loading…
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Reference in New Issue
Block a user