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Tiva Ethernet: Add DMA descriptor definitions

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This commit is contained in:
Gregory Nutt 2014-12-31 07:32:11 -06:00
parent a1bff3f9eb
commit 84485b2601
1 changed files with 186 additions and 2 deletions
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188
arch/arm/src/tiva/chip/tm4c_ethernet.h
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@ -781,8 +781,8 @@
#define EMAC_MFBOC_MISFRMCNT_SHIFT (0) /* Bits 0-15: Missed Frame Counter */
#define EMAC_MFBOC_MISFRMCNT_MASK (0xffff << EMAC_MFBOC_MISFRMCNT_SHIFT)
#define EMAC_MFBOC_MISCNTOVF (1 << 16) /* Bit 16: Overflow bit for Missed Frame Counter */
#define EMAC_MFBOC_OVFFRMCNT_MASK (17) /* Bits 17-27: Overflow Frame Counter */
#define EMAC_MFBOC_OVFFRMCNT_MASK (0x7ff << EMAC_MFBOC_OVFFRMCNT_MASK)
#define EMAC_MFBOC_OVFFRMCNT_SHIFT (17) /* Bits 17-27: Overflow Frame Counter */
#define EMAC_MFBOC_OVFFRMCNT_MASK (0x7ff << EMAC_MFBOC_OVFFRMCNT_SHIFT)
#define EMAC_MFBOC_OVFCNTOVF (1 << 28) /* Bit 28: Overflow Bit for FIFO Overflow Counter */
/* Ethernet MAC Receive Interrupt Watchdog Timer */
@ -1198,10 +1198,193 @@
# define EPHY_LEDCFG_LED2_FD (7 << EPHY_LEDCFG_LED2_SHIFT) /* Full Duplex */
# define EPHY_LEDCFG_LED2_LINKTXRX (8 << EPHY_LEDCFG_LED2_SHIFT) /* Link OK/Blink on TX/RX Activity */
/* DMA Descriptors **********************************************************************************/
/* TDES0: Transmit descriptor Word0 */
#define EMAC_TDES0_DB (1 << 0) /* Bit 0: Deferred bit */
#define EMAC_TDES0_UF (1 << 1) /* Bit 1: Underflow error */
#define EMAC_TDES0_ED (1 << 2) /* Bit 2: Excessive deferral */
#define EMAC_TDES0_CC_SHIFT (3) /* Bits 3-6: Collision count */
#define EMAC_TDES0_CC_MASK (15 << EMAC_TDES0_CC_SHIFT)
#define EMAC_TDES0_VF (1 << 7) /* Bit 7: VLAN frame */
#define EMAC_TDES0_EC (1 << 8) /* Bit 8: Excessive collision */
#define EMAC_TDES0_LCO (1 << 9) /* Bit 9: Late collision */
#define EMAC_TDES0_NC (1 << 10) /* Bit 10: No carrier */
#define EMAC_TDES0_LCA (1 << 11) /* Bit 11: Loss of carrier */
#define EMAC_TDES0_IPE (1 << 12) /* Bit 12: IP payload error */
#define EMAC_TDES0_FF (1 << 13) /* Bit 13: Frame flushed */
#define EMAC_TDES0_JT (1 << 14) /* Bit 14: Jabber timeout */
#define EMAC_TDES0_ES (1 << 15) /* Bit 15: Error summary */
#define EMAC_TDES0_IHE (1 << 16) /* Bit 16: IP header error */
#define EMAC_TDES0_TTSS (1 << 17) /* Bit 17: Transmit time stamp status */
#define EMAC_TDES0_VLIC_SHIFT (18) /* Bits 18-19: VLAN Insertion Control */
#define EMAC_TDES0_VLIC_MASK (3 << EMAC_TDES0_VLIC_SHIFT)
# define EMAC_TDES0_VLIC_NOACTION (0 << EMAC_TDES0_VLIC_SHIFT) /* Do not add a VLAN tag */
# define EMAC_TDES0_VLIC_REMOVE (1 << EMAC_TDES0_VLIC_SHIFT) /* Remove the VLAN tag before sending */
# define EMAC_TDES0_VLIC_INSERT (2 << EMAC_TDES0_VLIC_SHIFT) /* Insert a VLAN tag (EMACVLNINCREP) */
# define EMAC_TDES0_VLIC_REPLACE (3 << EMAC_TDES0_VLIC_SHIFT) /* Replace the VLAN tag i(EMACVLNINCREP) */
#define EMAC_TDES0_TCH (1 << 20) /* Bit 20: Second address chained */
#define EMAC_TDES0_TER (1 << 21) /* Bit 21: Transmit end of ring */
#define EMAC_TDES0_CIC_SHIFT (22) /* Bits 22-23: Checksum insertion control */
#define EMAC_TDES0_CIC_MASK (3 << EMAC_TDES0_CIC_SHIFT)
# define EMAC_TDES0_CIC_DISABLED (0 << EMAC_TDES0_CIC_SHIFT) /* Checksum disabled */
# define EMAC_TDES0_CIC_IH (1 << EMAC_TDES0_CIC_SHIFT) /* Insert IPv4 header checksum */
# define EMAC_TDES0_CIC_IHPL (2 << EMAC_TDES0_CIC_SHIFT) /* Insert TCP/UDP/ICMP checksum */
# define EMAC_TDES0_CIC_ALL (3 << EMAC_TDES0_CIC_SHIFT) /* TCP/UDP/ICMP checksum fully calculated */
#define EMAC_TDES0_CRCR (1 << 24) /* Bit 24: CRC Replacement Control */
#define EMAC_TDES0_TTSE (1 << 25) /* Bit 25: Transmit time stamp enable */
#define EMAC_TDES0_DP (1 << 26) /* Bit 26: Disable pad */
#define EMAC_TDES0_DC (1 << 27) /* Bit 27: Disable CRC */
#define EMAC_TDES0_FS (1 << 28) /* Bit 28: First segment */
#define EMAC_TDES0_LS (1 << 29) /* Bit 29: Last segment */
#define EMAC_TDES0_IC (1 << 30) /* Bit 30: Interrupt on completion */
#define EMAC_TDES0_OWN (1 << 31) /* Bit 31: Own bit */
/* TDES1: Transmit descriptor Word1 */
#define EMAC_TDES1_TBS1_SHIFT (0) /* Bits 0-12: Transmit buffer 1 size */
#define EMAC_TDES1_TBS1_MASK (0x1fff << EMAC_TDES1_TBS1_SHIFT)
# define EMAC_TDES1_TBS1(n) ((uint32_t)(n) << EMAC_TDES1_TBS1_SHIFT)
#define EMAC_TDES1_TBS2_SHIFT (16) /* Bits 16-28: Transmit buffer 2 size */
#define EMAC_TDES1_TBS2_MASK (0x1fff << EMAC_TDES1_TBS2_SHIFT)
# define EMAC_TDES1_TBS2(n) ((uint32_t)(n) << EMAC_TDES1_TBS2_SHIFT)
#define EMAC_TDES1_CTRL_SHIFT (29) /* Bits 29-31:SA Insertion Control */
#define EMAC_TDES1_CTRL_MASK (7 << EMAC_TDES1_CTRL_SHIFT)
# define EMAC_TDES1_CTRL_NOACTION (0 << EMAC_TDES1_CTRL_SHIFT) /* Do not include the source address */
# define EMAC_TDES1_CTRL_INSERT (1 << EMAC_TDES1_CTRL_SHIFT) /* Insert the source address */
# define EMAC_TDES1_CTRL_REPLACE (2 << EMAC_TDES1_CTRL_SHIFT) /* Replace the source address */
/* TDES2: Transmit descriptor Word2 (32-bit address) */
/* TDES3: Transmit descriptor Word3 (32-bit address) */
/* TDES6: Transmit descriptor Word6 (32-bit time stamp) */
/* TDES7: Transmit descriptor Word7 (32-bit time stamp) */
/* RDES0: Receive descriptor Word0 */
#define EMAC_RDES0_ESA (1 << 0) /* Bit 0: Extended status available */
#define EMAC_RDES0_CE (1 << 1) /* Bit 1: CRC error */
#define EMAC_RDES0_DBE (1 << 2) /* Bit 2: Dribble bit error */
#define EMAC_RDES0_RE (1 << 3) /* Bit 3: Receive error */
#define EMAC_RDES0_RWT (1 << 4) /* Bit 4: Receive watchdog timeout */
#define EMAC_RDES0_FT (1 << 5) /* Bit 5: Frame type */
#define EMAC_RDES0_LCO (1 << 6) /* Bit 6: Late collision */
#define EMAC_RDES0_TSV (1 << 7) /* Bit 7: Time stamp available */
#define EMAC_RDES0_GIANT (1 << 7) /* Bit 7: Giant frame */
#define EMAC_RDES0_LS (1 << 8) /* Bit 8: Last descriptor */
#define EMAC_RDES0_FS (1 << 9) /* Bit 9: First descriptor */
#define EMAC_RDES0_VLAN (1 << 10) /* Bit 10: VLAN tag */
#define EMAC_RDES0_OE (1 << 11) /* Bit 11: Overflow error */
#define EMAC_RDES0_LE (1 << 12) /* Bit 12: Length error */
#define EMAC_RDES0_SAF (1 << 13) /* Bit 13: Source address filter fail */
#define EMAC_RDES0_DE (1 << 14) /* Bit 14: Descriptor error */
#define EMAC_RDES0_ES (1 << 15) /* Bit 15: Error summary */
#define EMAC_RDES0_FL_SHIFT (16) /* Bits 16-29: Frame length */
#define EMAC_RDES0_FL_MASK (0x3fff << EMAC_RDES0_FL_SHIFT)
#define EMAC_RDES0_AFM (1 << 30) /* Bit 30: Destination address filter fail */
#define EMAC_RDES0_OWN (1 << 31) /* Bit 31: Own bit */
/* RDES1: Receive descriptor Word1 */
#define EMAC_RDES1_RBS1_SHIFT (0) /* Bits 0-12: Receive buffer 1 size */
#define EMAC_RDES1_RBS1_MASK (0x1fff << EMAC_RDES1_RBS1_SHIFT)
/* Bit 13: Reserved */
#define EMAC_RDES1_RCH (1 << 14) /* Bit 14: Second address chained */
#define EMAC_RDES1_RER (1 << 15) /* Bit 15: Receive end of ring */
#define EMAC_RDES1_RBS2_SHIFT (16) /* Bits 16-28: Receive buffer 2 size */
#define EMAC_RDES1_RBS2_MASK (0x1fff << EMAC_RDES1_RBS2_SHIFT)
#define EMAC_RDES1_DIC (1 << 31) /* Bit 31: Disable interrupt on completion */
/* RDES2: Receive descriptor Word2 (32-bit address) */
/* RDES3: Receive descriptor Word3 (32-bit address) */
/* RDES4: Receive descriptor Word4 */
#define EMAC_RDES4_IPPT_SHIFT (0) /* Bits 0-2: IP payload type */
#define EMAC_RDES4_IPPT_MASK (7 << EMAC_RDES4_IPPT_SHIFT)
# define EMAC_RDES4_IPPT_UNKNOWN (0 << EMAC_RDES4_IPPT_SHIFT) /* Unknown */
# define EMAC_RDES4_IPPT_UDP (1 << EMAC_RDES4_IPPT_SHIFT) /* UDP payload in IP datagram */
# define EMAC_RDES4_IPPT_TCP (2 << EMAC_RDES4_IPPT_SHIFT) /* TCP payload in IP datagram */
# define EMAC_RDES4_IPPT_ICMP (3 << EMAC_RDES4_IPPT_SHIFT) /* ICMP payload in IP datagram */
#define EMAC_RDES4_IPHE (1 << 3) /* Bit 3: IP header error */
#define EMAC_RDES4_IPPE (1 << 4) /* Bit 4: IP payload error */
#define EMAC_RDES4_IPCB (1 << 5) /* Bit 5: IP checksum bypassed */
#define EMAC_RDES4_IPV4PR (1 << 6) /* Bit 6: IPv4 packet received */
#define EMAC_RDES4_IPV6PR (1 << 7) /* Bit 7: IPv6 packet received */
#define EMAC_RDES4_PMT_SHIFT (8) /* Bits 8-11: PTP message type */
#define EMAC_RDES4_PMT_MASK (15 << EMAC_RDES4_PMT_SHIFT)
# define EMAC_RDES4_PMT_NONE (0 << EMAC_RDES4_PMT_SHIFT) /* No PTP message received */
# define EMAC_RDES4_PMT_SYNC (1 << EMAC_RDES4_PMT_SHIFT) /* SYNC (all clock types) */
# define EMAC_RDES4_PMT_FOLLOWUP (2 << EMAC_RDES4_PMT_SHIFT) /* Follow_Up (all clock types) */
# define EMAC_RDES4_PMT_DELAYREQ (3 << EMAC_RDES4_PMT_SHIFT) /* Delay_Req (all clock types) */
# define EMAC_RDES4_PMT_DELAYRESP (4 << EMAC_RDES4_PMT_SHIFT) /* Delay_Resp (all clock types) */
# define EMAC_RDES4_PMT_PDELREQAM (5 << EMAC_RDES4_PMT_SHIFT) /* Pdelay_Req (in peer-to-peer
* transparent clock) or Announce (in
* ordinary or boundary clock) */
# define EMAC_RDES4_PMT_PDELREQMM (6 << EMAC_RDES4_PMT_SHIFT) /* Pdelay_Resp (in peer-to-peer
* transparent clock) or Management (in
* ordinary or boundary clock) */
# define EMAC_RDES4_PMT_PDELREQFUS (7 << EMAC_RDES4_PMT_SHIFT) /* Pdelay_Resp_Follow_Up (in
* peer-to-peer transparent clock) or
* Signaling (for ordinary or boundary
* clock) */
# define EMAC_RDES4_PMT_ANNOUNCE (8 << EMAC_RDES4_PMT_SHIFT) /* Announce */
# define EMAC_RDES4_PMT_MANAGEMENT (9 << EMAC_RDES4_PMT_SHIFT) /* Management */
# define EMAC_RDES4_PMT_SIGNALING (10 << EMAC_RDES4_PMT_SHIFT) /* Signaling */
# define EMAC_RDES4_PMT_PTP (15 << EMAC_RDES4_PMT_SHIFT) /* PTP packet w/ Reserved message type */
#define EMAC_RDES4_PFT (1 << 12) /* Bit 12: PTP frame type */
#define EMAC_RDES4_PV (1 << 13) /* Bit 13: PTP version */
#define EMAC_RDES4_TSD (1 << 14) /* Bit 14: Time stampe dropped */
/* RDES5: Receive descriptor Word5 - Reserved */
/* RDES6: Receive descriptor Word6 (32-bit time stamp) */
/* RDES7: Receive descriptor Word7 (32-bit time stamp) */
/************************************************************************************
* Public Types
************************************************************************************/
#ifndef __ASSEMBLY__
/* Ethernet TX DMA Descriptor */
struct emac_txdesc_s
{
/* Normal DMA descriptor words */
volatile uint32_t tdes0; /* Status */
volatile uint32_t tdes1; /* Control and buffer1/2 lengths */
volatile uint32_t tdes2; /* Buffer1 address pointer */
volatile uint32_t tdes3; /* Buffer2 or next descriptor address pointer */
/* Enhanced DMA descriptor words with time stamp */
#ifdef CONFIG_TIVA_EMAC_ENHANCEDDESC
volatile uint32_t tdes4; /* Reserved */
volatile uint32_t tdes5; /* Reserved */
volatile uint32_t tdes6; /* Time Stamp Low value for transmit and receive */
volatile uint32_t tdes7; /* Time Stamp High value for transmit and receive */
#endif
};
/* Ethernet RX DMA Descriptor */
struct emac_rxdesc_s
{
volatile uint32_t rdes0; /* Status */
volatile uint32_t rdes1; /* Control and buffer1/2 lengths */
volatile uint32_t rdes2; /* Buffer1 address pointer */
volatile uint32_t rdes3; /* Buffer2 or next descriptor address pointer */
/* Enhanced DMA descriptor words with time stamp and PTP support */
#ifdef CONFIG_TIVA_EMAC_ENHANCEDDESC
volatile uint32_t rdes4; /* Extended status for PTP receive descriptor */
volatile uint32_t rdes5; /* Reserved */
volatile uint32_t rdes6; /* Time Stamp Low value for transmit and receive */
volatile uint32_t rdes7; /* Time Stamp High value for transmit and receive */
#endif
};
/************************************************************************************
* Public Data
************************************************************************************/
@ -1210,4 +1393,5 @@
* Public Function Prototypes
************************************************************************************/
#endif /* __ASSEMBLY__ */
#endif /* __ARCH_ARM_SRC_TIVA_CHIP_TM4C_ETHERNET_H */