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risc-v/bl808: Add GPADC character driver

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This commit implements a character driver for the general purpose ADC of the BL808, based on the hardware scanning functionality. The driver supports setting different conversion resolutions and the order of channels to be scanned via menuconfig.
This commit is contained in:
Henry Rovner 2024-06-29 16:30:20 -07:00 committed by Xiang Xiao
parent 0c63840b18
commit 8493273c2c
9 changed files with 818 additions and 1 deletions
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1
arch/risc-v/include/bl808/irq.h
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@ -57,6 +57,7 @@
/* M0 IRQs ******************************************************************/
#define BL808_IRQ_GPADC (RISCV_IRQ_SEXT + BL808_IRQ_NUM_BASE + BL808_M0_IRQ_OFFSET + 25)
#define BL808_IRQ_UART0 (RISCV_IRQ_SEXT + BL808_IRQ_NUM_BASE + BL808_M0_IRQ_OFFSET + 28)
#define BL808_IRQ_UART1 (RISCV_IRQ_SEXT + BL808_IRQ_NUM_BASE + BL808_M0_IRQ_OFFSET + 29)
#define BL808_IRQ_UART2 (RISCV_IRQ_SEXT + BL808_IRQ_NUM_BASE + BL808_M0_IRQ_OFFSET + 30)

99
arch/risc-v/src/bl808/Kconfig
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@ -7,6 +7,105 @@ comment "BL808 Configuration Options"
menu "BL808 Peripheral Support"
config BL808_GPADC
bool "GPADC"
default n
menu "BL808 GPADC Options"
depends on BL808_GPADC
choice BL808_GPADC_RES
prompt "GPADC Resolution"
default BL808_GPADC_RES_12
depends on BL808_GPADC
config BL808_GPADC_RES_12
bool "12 bits"
config BL808_GPADC_RES_14
bool "14 bits"
config BL808_GPADC_RES_16
bool "16 bits"
endchoice
config BL808_GPADC_NCHANNELS
int "Number of channels"
default 12
range 1 12
comment "Channel scanning order - set the channel number for each scanning position"
comment "Only positions smaller than the number of channels will be used."
comment "Channel codes:"
comment "0-11: External channels"
comment "12 or 13: DAC output A or B"
comment "16: VREF"
comment "18: VBAT\/2"
comment "23: GND"
config BL808_GPADC_SCAN_ORD0
int "Position 0"
default 0
range 0 23
config BL808_GPADC_SCAN_ORD1
int "Position 1"
default 1
range 0 23
config BL808_GPADC_SCAN_ORD2
int "Position 2"
default 2
range 0 23
config BL808_GPADC_SCAN_ORD3
int "Position 3"
default 3
range 0 23
config BL808_GPADC_SCAN_ORD4
int "Position 4"
default 4
range 0 23
config BL808_GPADC_SCAN_ORD5
int "Position 5"
default 5
range 0 23
config BL808_GPADC_SCAN_ORD6
int "Position 6"
default 6
range 0 23
config BL808_GPADC_SCAN_ORD7
int "Position 7"
default 7
range 0 23
config BL808_GPADC_SCAN_ORD8
int "Position 8"
default 8
range 0 23
config BL808_GPADC_SCAN_ORD9
int "Position 9"
default 9
range 0 23
config BL808_GPADC_SCAN_ORD10
int "Position 10"
default 10
range 0 23
config BL808_GPADC_SCAN_ORD11
int "Position 11"
default 11
range 0 23
endmenu
config BL808_UART0
bool "UART 0"
default n

1
arch/risc-v/src/bl808/Make.defs
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@ -28,3 +28,4 @@ HEAD_ASRC = bl808_head.S
CHIP_CSRCS = bl808_start.c bl808_irq_dispatch.c bl808_irq.c
CHIP_CSRCS += bl808_timerisr.c bl808_allocateheap.c
CHIP_CSRCS += bl808_gpio.c bl808_mm_init.c bl808_pgalloc.c bl808_serial.c
CHIP_CSRCS += bl808_gpadc.c

477
arch/risc-v/src/bl808/bl808_gpadc.c Normal file
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@ -0,0 +1,477 @@
/****************************************************************************
* arch/risc-v/src/bl808/bl808_gpadc.c
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include <nuttx/arch.h>
#include <sys/types.h>
#include <stdint.h>
#include <stdbool.h>
#include <stdio.h>
#include <unistd.h>
#include <string.h>
#include <errno.h>
#include <debug.h>
#include <nuttx/irq.h>
#include <nuttx/fs/ioctl.h>
#include <nuttx/analog/adc.h>
#include <nuttx/analog/ioctl.h>
#include "hardware/bl808_gpadc.h"
#include "riscv_internal.h"
#include "chip.h"
#include "bl808_gpadc.h"
#ifdef CONFIG_BL808_GPADC
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
#define BL808_GPADC_TOTAL_NCHANNELS 18
#define BL808_GPADC_SCAN_MAX_CHANNELS 12
/****************************************************************************
* Private Types
****************************************************************************/
enum bl808_gpadc_channel_e
{
GPADC_CH0,
GPADC_CH1,
GPADC_CH2,
GPADC_CH3,
GPADC_CH4,
GPADC_CH5,
GPADC_CH6,
GPADC_CH7,
GPADC_CH8,
GPADC_CH9,
GPADC_CH10,
GPADC_CH11,
GPADC_CH_DAC_OUTA,
GPADC_CH_DAC_OUTB,
GPADC_CH_TSEN,
GPADC_CH_VREF = 16,
GPADC_CH_HALF_VBAT = 18,
GPADC_CH_GND = 23
};
/* Values for resolution enum correspond to the register values
* for each option.
*/
enum bl808_gpadc_resolution_e
{
GPADC_12_BIT = 0,
GPADC_14_BIT = 1,
GPADC_16_BIT = 3
};
struct bl808_gpadc_s
{
const struct adc_callback_s *callback;
enum bl808_gpadc_channel_e enabled_channels[BL808_GPADC_SCAN_MAX_CHANNELS];
uint8_t nchannels;
enum bl808_gpadc_resolution_e resolution;
};
/****************************************************************************
* Private Function Prototypes
****************************************************************************/
uint8_t bl808_gpadc_get_count(void);
/* Character driver methods */
static int bl808_gpadc_bind(struct adc_dev_s *dev,
const struct adc_callback_s *callback);
static void bl808_gpadc_reset(struct adc_dev_s *dev);
static int bl808_gpadc_setup(struct adc_dev_s *dev);
static void bl808_gpadc_shutdown(struct adc_dev_s *dev);
static void bl808_gpadc_rxint(struct adc_dev_s *dev,
bool enable);
static int bl808_gpadc_ioctl(struct adc_dev_s *dev,
int cmd, unsigned long arg);
/****************************************************************************
* Private Data
****************************************************************************/
static struct bl808_gpadc_s gpadc_priv =
{
.callback = NULL,
.enabled_channels =
{
CONFIG_BL808_GPADC_SCAN_ORD0,
CONFIG_BL808_GPADC_SCAN_ORD1,
CONFIG_BL808_GPADC_SCAN_ORD2,
CONFIG_BL808_GPADC_SCAN_ORD3,
CONFIG_BL808_GPADC_SCAN_ORD4,
CONFIG_BL808_GPADC_SCAN_ORD5,
CONFIG_BL808_GPADC_SCAN_ORD6,
CONFIG_BL808_GPADC_SCAN_ORD7,
CONFIG_BL808_GPADC_SCAN_ORD8,
CONFIG_BL808_GPADC_SCAN_ORD9,
CONFIG_BL808_GPADC_SCAN_ORD10,
CONFIG_BL808_GPADC_SCAN_ORD11
},
.nchannels = CONFIG_BL808_GPADC_NCHANNELS,
#ifdef CONFIG_BL808_GPADC_RES_12
.resolution = GPADC_12_BIT,
#elif defined(CONFIG_BL808_GPADC_RES_14)
.resolution = GPADC_14_BIT,
#elif defined(CONFIG_BL808_GPADC_RES_16)
.resolution = GPADC_16_BIT,
#endif
};
static struct adc_ops_s gpadc_ops =
{
.ao_bind = bl808_gpadc_bind,
.ao_reset = bl808_gpadc_reset,
.ao_setup = bl808_gpadc_setup,
.ao_shutdown = bl808_gpadc_shutdown,
.ao_rxint = bl808_gpadc_rxint,
.ao_ioctl = bl808_gpadc_ioctl
};
/****************************************************************************
* Private Functions
****************************************************************************/
/****************************************************************************
* Name: bl808_gpadc_get_count
*
* Description:
* Gets the number of items available in the GPADC FIFO.
*
****************************************************************************/
uint8_t bl808_gpadc_get_count()
{
uint32_t status = getreg32(BL808_GPADC_CONFIG);
uint8_t count = (status & GPADC_FIFO_DATA_COUNT_MASK)
>> GPADC_FIFO_DATA_COUNT_SHIFT;
return count;
}
/****************************************************************************
* Name: gpadc_interrupt
*
* Description:
* GPADC interrupt handler. Passes ADC readings to upper half driver,
* then clears the FIFO.
*
****************************************************************************/
static int __gpadc_interrupt(int irq, void *context, void *arg)
{
struct adc_dev_s *dev = (struct adc_dev_s *)arg;
struct bl808_gpadc_s *priv = dev->ad_priv;
uint32_t status = getreg32(BL808_GPADC_CONFIG);
if (status & GPADC_RDY)
{
if ((priv->callback != NULL)
&& (priv->callback->au_receive != NULL))
{
uint8_t count = bl808_gpadc_get_count();
while (count != 0)
{
uint32_t result = getreg32(BL808_GPADC_DMA_RDATA);
uint32_t channel = (result & GPADC_RESULT_POS_CHN_MASK)
>> GPADC_RESULT_POS_CHN_SHIFT;
uint32_t adc_val = result & GPADC_RESULT_RAW_VAL_MASK;
int receive_ret =
priv->callback->au_receive(dev, channel, adc_val);
if (receive_ret)
{
aerr("ADC driver upper half receive error");
return -EIO;
}
count = bl808_gpadc_get_count();
}
modifyreg32(BL808_GPADC_CONFIG, 0,
GPADC_FIFO_CLR);
modifyreg32(BL808_GPADC_CONFIG, 0,
GPADC_RDY_CLR);
modifyreg32(BL808_GPADC_CONFIG,
GPADC_RDY_CLR, 0);
return OK;
}
}
/* If we get here, there was an error */
return -EIO;
}
/****************************************************************************
* Name: bl808_gpadc_bind
*
* Description:
* Called when the driver is registered. Binds upper half callbacks
* to the private data structure.
*
****************************************************************************/
static int bl808_gpadc_bind(struct adc_dev_s *dev,
const struct adc_callback_s *callback)
{
((struct bl808_gpadc_s *)(dev->ad_priv))->callback = callback;
return OK;
}
/****************************************************************************
* Name: bl808_gpadc_reset
*
* Description:
* Called as part of the device registration process. Resets the
* GPADC hardware block.
*
****************************************************************************/
static void bl808_gpadc_reset(struct adc_dev_s *dev)
{
modifyreg32(BL808_GPADC_CMD, 0, GPADC_SOFT_RST);
modifyreg32(BL808_GPADC_CMD, GPADC_SOFT_RST, 0);
}
/****************************************************************************
* Name: bl808_gpadc_setup
*
* Description:
* Called when the driver is first opened. Sets registers to allow
* scanning functionality, and sets the scan order registers.
*
****************************************************************************/
static int bl808_gpadc_setup(struct adc_dev_s *dev)
{
struct bl808_gpadc_s *priv = dev->ad_priv;
/* This setup process is mostly taken from bouffalo_sdk */
modifyreg32(BL808_GPADC_CMD, GPADC_GLOBAL_EN, 0);
/* Soft reset */
modifyreg32(BL808_GPADC_CMD, 0, GPADC_SOFT_RST);
modifyreg32(BL808_GPADC_CMD, GPADC_SOFT_RST, 0);
modifyreg32(BL808_GPADC_CONFIG1, GPADC_CONT_CONV_EN,
(2 << GPADC_V18_SEL_SHIFT)
| (1 << GPADC_V11_SEL_SHIFT)
| GPADC_SCAN_EN
| GPADC_CLK_ANA_INV
| (priv->resolution << GPADC_RES_SEL_SHIFT));
modifyreg32(BL808_GPADC_CONFIG2, 0,
(2 << GPADC_DLY_SEL_SHIFT)
| GPADC_VBAT_EN
| GPADC_TS_EN);
/* Use GND as negative channel for now */
modifyreg32(BL808_GPADC_CMD, 0, GPADC_NEG_GND);
/* Clear all interrupts and masked unused ones */
modifyreg32(BL808_GPADC_CONFIG, 0,
GPADC_RDY_CLR
| GPADC_FIFO_OVERRUN_CLR
| GPADC_FIFO_UNDERRUN_CLR
| GPADC_FIFO_OVERRUN_MASK
| GPADC_FIFO_UNDERRUN_MASK);
modifyreg32(BL808_GPADC_ISR, 0,
GPADC_NEG_SATUR_CLR
| GPADC_POS_SATUR_CLR
| GPADC_NEG_SATUR_MASK
| GPADC_POS_SATUR_MASK);
modifyreg32(BL808_GPADC_CONFIG,
GPADC_RDY_CLR, 0);
/* Set scan channels */
modifyreg32(BL808_GPADC_SCAN_POS1,
0xffffffff, 0);
modifyreg32(BL808_GPADC_SCAN_POS2,
0xffffffff, 0);
for (int channel_idx = 0;
channel_idx < priv->nchannels;
channel_idx++)
{
if (channel_idx < 6)
{
modifyreg32(BL808_GPADC_SCAN_POS1, 0,
(priv->enabled_channels[channel_idx]
<< GPADC_SCAN_SHIFT(channel_idx)));
}
else
{
modifyreg32(BL808_GPADC_SCAN_POS2, 0,
(priv->enabled_channels[channel_idx]
<< GPADC_SCAN_SHIFT(channel_idx)));
}
}
modifyreg32(BL808_GPADC_CONFIG1, 0,
((priv->nchannels - 1) << GPADC_SCAN_LENGTH_SHIFT));
modifyreg32(BL808_GPADC_CONFIG, 0,
GPADC_FIFO_CLR);
modifyreg32(BL808_GPADC_CMD, 0, GPADC_GLOBAL_EN);
return OK;
}
/****************************************************************************
* Name: bl808_gpadc_shutdown
*
* Description:
* Disables the GPADC hardware block.
*
****************************************************************************/
static void bl808_gpadc_shutdown(struct adc_dev_s *dev)
{
modifyreg32(BL808_GPADC_CMD, GPADC_GLOBAL_EN, 0);
}
/****************************************************************************
* Name: bl808_gpadc_rxint
*
* Description:
* Enables or disables the conversion finished interrupt.
*
****************************************************************************/
static void bl808_gpadc_rxint(struct adc_dev_s *dev,
bool enable)
{
if (enable)
{
irq_attach(BL808_IRQ_GPADC, __gpadc_interrupt, (void *)dev);
up_enable_irq(BL808_IRQ_GPADC);
modifyreg32(BL808_GPADC_CMD, 0, GPADC_CONV_START);
}
else
{
up_disable_irq(BL808_IRQ_GPADC);
irq_detach(BL808_IRQ_GPADC);
modifyreg32(BL808_GPADC_CMD, GPADC_CONV_START, 0);
}
}
/****************************************************************************
* Name: bl808_gpadc_ioctl
*
* Description:
* All ioctl calls will be routed through this method.
*
****************************************************************************/
static int bl808_gpadc_ioctl(struct adc_dev_s *dev,
int cmd, unsigned long arg)
{
int ret;
struct bl808_gpadc_s *priv = (struct bl808_gpadc_s *)dev->ad_priv;
switch (cmd)
{
case ANIOC_TRIGGER:
{
modifyreg32(BL808_GPADC_CMD, 0, GPADC_CONV_START);
ret = OK;
break;
}
case ANIOC_GET_NCHANNELS:
{
ret = priv->nchannels;
break;
}
case ANIOC_RESET_FIFO:
{
modifyreg32(BL808_GPADC_CONFIG, 0,
GPADC_FIFO_CLR);
ret = OK;
break;
}
case ANIOC_SAMPLES_ON_READ:
{
ret = bl808_gpadc_get_count();
break;
}
default:
{
/* Other commands not implemented */
ret = -ENOTTY;
break;
}
}
return ret;
}
/****************************************************************************
* Public Functions
****************************************************************************/
int bl808_gpadc_init(void)
{
struct adc_dev_s *dev = kmm_zalloc(sizeof(struct adc_dev_s));
dev->ad_ops = &gpadc_ops;
dev->ad_priv = &gpadc_priv;
int ret = adc_register("/dev/gpadc", dev);
return ret;
}
#endif /* CONFIG_BL808_GPADC */

33
arch/risc-v/src/bl808/bl808_gpadc.h Normal file
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@ -0,0 +1,33 @@
/****************************************************************************
* arch/risc-v/src/bl808/bl808_gpadc.h
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
#ifndef __ARCH_RISC_V_SRC_BL808_BL808_GPADC_H
#define __ARCH_RISC_V_SRC_BL808_BL808_GPADC_H
#ifdef CONFIG_BL808_GPADC
/****************************************************************************
* Public Functions Prototypes
****************************************************************************/
int bl808_gpadc_init(void);
#endif /* CONFIG_BL808_GPADC */
#endif /* __ARCH_RISC_V_SRC_BL808_BL808_GPADC_H */

1
arch/risc-v/src/bl808/bl808_start.c
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@ -37,6 +37,7 @@
#include "bl808_mm_init.h"
#include "bl808_memorymap.h"
#include "bl808_serial.h"
#include "bl808_gpadc.h"
/****************************************************************************
* Pre-processor Definitions

197
arch/risc-v/src/bl808/hardware/bl808_gpadc.h Normal file
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@ -0,0 +1,197 @@
/****************************************************************************
* arch/risc-v/src/bl808/hardware/bl808_gpadc.h
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
#ifndef __ARCH_RISCV_SRC_BL808_HARDWARE_BL808_GPADC_H
#define __ARCH_RISCV_SRC_BL808_HARDWARE_BL808_GPADC_H
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include "bl808_memorymap.h"
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/* Register offsets *********************************************************/
/* gpadc base */
#define BL808_GPADC_CONFIG_OFFSET (0x0)
#define BL808_GPADC_DMA_RDATA_OFFSET (0x4)
#define BL808_GPADC_PIR_TRAIN_OFFSET (0x20
/* aon base */
#define BL808_GPADC_CMD_OFFSET (0x90C)
#define BL808_GPADC_CONFIG1_OFFSET (0x910)
#define BL808_GPADC_CONFIG2_OFFSET (0x914)
#define BL808_GPADC_SCAN_POS1_OFFSET (0x918)
#define BL808_GPADC_SCAN_POS2_OFFSET (0x91C)
#define BL808_GPADC_SCAN_NEG1_OFFSET (0x920)
#define BL808_GPADC_SCAN_NEG2_OFFSET (0x924)
#define BL808_GPADC_STATUS_OFFSET (0x928)
#define BL808_GPADC_ISR_OFFSET (0x92C)
#define BL808_GPADC_RESULT_OFFSET (0x930)
#define BL808_GPADC_RAW_RESULT_OFFSET (0x934)
#define BL808_GPADC_DEFINE_OFFSET (0x938)
/* Register definitions *****************************************************/
#define BL808_GPADC_CONFIG (BL808_GPADC_BASE + BL808_GPADC_CONFIG_OFFSET)
#define BL808_GPADC_DMA_RDATA (BL808_GPADC_BASE + BL808_GPADC_DMA_RDATA_OFFSET)
#define BL808_GPADC_PIR_TRAIN (BL808_GPADC_BASE + BL808_GPADC_PIR_TRAIN_OFFSET)
#define BL808_GPADC_CMD (BL808_AON_BASE + BL808_GPADC_CMD_OFFSET)
#define BL808_GPADC_CONFIG1 (BL808_AON_BASE + BL808_GPADC_CONFIG1_OFFSET)
#define BL808_GPADC_CONFIG2 (BL808_AON_BASE + BL808_GPADC_CONFIG2_OFFSET)
#define BL808_GPADC_SCAN_POS1 (BL808_AON_BASE + BL808_GPADC_SCAN_POS1_OFFSET)
#define BL808_GPADC_SCAN_POS2 (BL808_AON_BASE + BL808_GPADC_SCAN_POS2_OFFSET)
#define BL808_GPADC_SCAN_NEG1 (BL808_AON_BASE + BL808_GPADC_SCAN_NEG1_OFFSET)
#define BL808_GPADC_SCAN_NEG2 (BL808_AON_BASE + BL808_GPADC_SCAN_NEG2_OFFSET)
#define BL808_GPADC_STATUS (BL808_AON_BASE + BL808_GPADC_STATUS_OFFSET)
#define BL808_GPADC_ISR (BL808_AON_BASE + BL808_GPADC_ISR_OFFSET)
#define BL808_GPADC_RESULT (BL808_AON_BASE + BL808_GPADC_RESULT_OFFSET)
#define BL808_GPADC_RAW_RESULT (BL808_AON_BASE + BL808_GPADC_RAW_RESULT_OFFSET)
#define BL808_GPADC_DEFINE (BL808_AON_BASE + BL808_GPADC_DEFINE_OFFSET)
/* Register bit definitions *************************************************/
/* GPADC_DMA_RDATA */
#define GPADC_DMA_RDATA_SHIFT (0U)
#define GPADC_DMA_RDATA_MASK (0x3ffffff << GPADC_DMA_RDATA_SHIFT)
#define GPADC_RESULT_RAW_VAL_SHIFT (0U)
#define GPADC_RESULT_RAW_VAL_MASK (0xffff << GPADC_RESULT_RAW_VAL_SHIFT)
#define GPADC_RESULT_POS_CHN_SHIFT (21U)
#define GPADC_RESULT_POS_CHN_MASK (0x1f << GPADC_RESULT_POS_CHN_SHIFT)
/* GPADC_CONFIG */
#define GPADC_DMA_EN (1 << 0U)
#define GPADC_FIFO_CLR (1 << 1U)
#define GPADC_FIFO_NE (1 << 2U)
#define GPADC_FIFO_FULL (1 << 3U)
#define GPADC_RDY (1 << 4U)
#define GPADC_FIFO_OVERRUN (1 << 5U)
#define GPADC_FIFO_UNDERRUN (1 << 6U)
#define GPADC_RDY_CLR (1 << 8U)
#define GPADC_FIFO_OVERRUN_CLR (1 << 9U)
#define GPADC_FIFO_UNDERRUN_CLR (1 << 10U)
#define GPADC_RDY_MASK (1 << 12U)
#define GPADC_FIFO_OVERRUN_MASK (1 << 13U)
#define GPADC_FIFO_UNDERRUN_MASK (1 << 14U)
#define GPADC_FIFO_DATA_COUNT_SHIFT (16U)
#define GPADC_FIFO_DATA_COUNT_MASK (0x3f << GPADC_FIFO_DATA_COUNT_SHIFT)
#define GPADC_FIFO_THL_SHIFT (22U)
#define GPADC_FIFO_THL_MASK (0x3 << GPADC_FIFO_THL_SHIFT)
/* GPADC_CMD */
#define GPADC_GLOBAL_EN (1 << 0U)
#define GPADC_CONV_START (1 << 1U)
#define GPADC_SOFT_RST (1 << 2U)
#define GPADC_NEG_SEL_SHIFT (3U)
#define GPADC_NEG_SEL_MASK (0x1f << GPADC_NEG_SEL_SHIFT)
#define GPADC_POS_SEL_SHIFT (8U)
#define GPADC_POS_SEL_MASK (0x1f << GPADC_POS_SEL_SHIFT)
#define GPADC_NEG_GND (1 << 13U)
#define GPADC_MICBIAS_EN (1 << 14U)
#define GPADC_MICPGA_EN (1 << 15U)
#define GPADC_BYP_MICBOOST (1 << 16U)
#define GPADC_RCAL_EN (1 << 17U)
#define GPADC_DWA_EN (1 << 18U)
#define GPADC_MIC2_DIFF (1 << 19U)
#define GPADC_MIC1_DIFF (1 << 20U)
#define GPADC_MIC_PGA2_GAIN_SHIFT (21U)
#define GPADC_MIC_PGA2_GAIN_MASK (0x3 << GPADC_MIC_PGA2_GAIN_SHIFT)
#define GPADC_MICBOOST_32DB_EN (1 << 23U)
#define GPADC_CHIP_SEN_PU (1 << 27U)
#define GPADC_SEN_SEL_SHIFT (28U)
#define GPADC_SEN_SEL_MASK (0x7 << GPADC_SEN_SEL_SHIFT)
#define GPADC_SEN_TEST_EN (1 << 31U)
/* GPADC_CONFIG1 */
#define GPADC_CAL_OS_EN (1 << 0U)
#define GPADC_CONT_CONV_EN (1 << 1U)
#define GPADC_RES_SEL_SHIFT (2U)
#define GPADC_RES_SEL_MASK (0x7 << GPADC_RES_SEL_SHIFT)
#define GPADC_VCM_SEL_EN (1 << 8U)
#define GPADC_VCM_HYST_SEL (1 << 9U)
#define GPADC_LOWV_DET_EN (1 << 10U)
#define GPADC_PWM_TRG_EN (1 << 11U)
#define GPADC_CLK_ANA_DLY_SHIFT (12U)
#define GPADC_CLK_ANA_DLY_MASK (0xf << GPADC_CLK_ANA_DLY_SHIFT)
#define GPADC_CLK_ANA_DLY_EN (1 << 16U)
#define GPADC_CLK_ANA_INV (1 << 17U)
#define GPADC_CLK_DIV_RATIO_SHIFT (18U)
#define GPADC_CLK_DIV_RATIO_MASK (0x7 << GPADC_CLK_DIV_RATIO_SHIFT)
#define GPADC_SCAN_LENGTH_SHIFT (21U)
#define GPADC_SCAN_LENGTH_MASK (0xf << GPADC_SCAN_LENGTH_SHIFT)
#define GPADC_SCAN_EN (1 << 25U)
#define GPADC_DITHER_EN (1 << 26U)
#define GPADC_V11_SEL_SHIFT (27U)
#define GPADC_V11_SEL_MASK (0x3 << GPADC_V11_SEL_SHIFT)
#define GPADC_V18_SEL_SHIFT (29U)
#define GPADC_V18_SEL_MASK (0x3 << GPADC_V18_SEL_SHIFT)
/* GPADC_CONFIG2 */
#define GPADC_DIFF_MODE (1 << 2U)
#define GPADC_VREF_SEL (1 << 3U)
#define GPADC_VBAT_EN (1 << 4U)
#define GPADC_TSEXT_SEL (1 << 5U)
#define GPADC_TS_EN (1 << 6U)
#define GPADC_PGA_VCM_SHIFT (7U)
#define GPADC_PGA_VCM_MASK (0x3 << GPADC_PGA_VCM_SHIFT)
#define GPADC_PGA_OS_CAL_SHIFT (9U)
#define GPADC_PGA_OS_CAL_MASK (0xf << GPADC_PGA_OS_CAL_SHIFT)
#define GPADC_PGA_EN (1 << 13U)
#define GPADC_PGA_VCMI_EN (1 << 14U)
#define GPADC_CHOP_MODE_SHIFT (15U)
#define GPADC_CHOP_MODE_MASK (0x3 << GPADC_CHOP_MODE_SHIFT)
#define GPADC_BIAS_SEL (1 << 17U)
#define GPADC_TEST_EN (1 << 18U)
#define GPADC_TEST_SEL_SHIFT (19U)
#define GPADC_TEST_SEL_MASK (0x7 << GPADC_TEST_SEL_SHIFT)
#define GPADC_PGA2_GAIN_SHIFT (22U)
#define GPADC_PGA2_GAIN_MASK (0x7 << GPADC_PGA2_GAIN_SHIFT)
#define GPADC_PGA1_GAIN_SHIFT (25U)
#define GPADC_PGA1_GAIN_MASK (0x7 << GPADC_PGA1_GAIN_SHIFT)
#define GPADC_DLY_SEL_SHIFT (28U)
#define GPADC_DLY_SEL_MASK (0x7 << GPADC_DLY_SEL_SHIFT)
#define GPADC_TSVBE_LOW (1 << 31U)
/* GPADC_SCAN_n */
#define GPADC_SCAN_SHIFT(n) (5 * (n % 6))
#define GPADC_SCAN_MASK(n) (0x1f << GPADC_SCAN_POS_SHIFT(n))
/* GPADC_ISR */
#define GPADC_NEG_SATUR (1 << 0U)
#define GPADC_POS_SATUR (1 << 1U)
#define GPADC_NEG_SATUR_CLR (1 << 4U)
#define GPADC_POS_SATUR_CLR (1 << 5U)
#define GPADC_NEG_SATUR_MASK (1 << 8U)
#define GPADC_POS_SATUR_MASK (1 << 9U)
#endif /* __ARCH_RISCV_SRC_BL808_HARDWARE_BL808_GPADC_H */

3
arch/risc-v/src/bl808/hardware/bl808_memorymap.h
View File

@ -29,11 +29,12 @@
#define BL808_GLB_BASE 0x20000000ul
#define BL808_M0IC_BASE 0x20000050ul
#define BL808_GPIO_BASE 0x200008c4ul
#define BL808_GPADC_BASE 0x20002000ul
#define BL808_UART0_BASE 0x2000a000ul
#define BL808_UART1_BASE 0x2000a100ul
#define BL808_UART2_BASE 0x2000aa00ul
#define BL808_AON_BASE 0x2000f000ul
#define BL808_UART3_BASE 0x30002000ul
#define BL808_PLIC_BASE 0xe0000000ul

7
boards/risc-v/bl808/ox64/src/bl808_appinit.c
View File

@ -38,6 +38,7 @@
#ifdef CONFIG_USERLED
#include <nuttx/leds/userled.h>
#endif
#include "bl808_gpadc.h"
/****************************************************************************
* Pre-processor Definitions
@ -163,6 +164,12 @@ void board_late_initialize(void)
/* Perform board-specific initialization */
#ifdef CONFIG_BL808_GPADC
bl808_gpadc_init();
#endif
#ifdef CONFIG_NSH_ARCHINIT
mount(NULL, "/proc", "procfs", 0, NULL);