STM32 F33 ADC: Correct bad definitions of base addresses; Fix naming collision by changing colliding STM32_ADC12_BASE to STM32_ADC12_CMN_BASE
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@ -49,13 +49,13 @@
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* Pre-processor Definitions
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* Pre-processor Definitions
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****************************************************************************************************/
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****************************************************************************************************/
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#define STM32_ADC1_BASE_OFFSET 0x0000
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#define STM32_ADC1_OFFSET 0x0000
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#define STM32_ADC2_BASE_OFFSET 0x0100
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#define STM32_ADC2_OFFSET 0x0100
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#define STM32_ADC12_BASE_OFFSET 0x0300
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#define STM32_ADC12_CMN_OFFSET 0x0300
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#define STM32_ADC1_BASE (STM32_ADC1_BASE_OFFSET+STM32_ADC12_BASE) /* ADC1 Master ADC */
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#define STM32_ADC1_BASE (STM32_ADC1_OFFSET+STM32_ADC12_BASE) /* ADC1 Master ADC */
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#define STM32_ADC2_BASE (STM32_ADC1_BASE_OFFSET+STM32_ADC12_BASE) /* ADC2 Slave ADC */
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#define STM32_ADC2_BASE (STM32_ADC2_OFFSET+STM32_ADC12_BASE) /* ADC2 Slave ADC */
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#define STM32_ADC12_BASE (STM32_ADC1_BASE_OFFSET+STM32_ADC12_BASE) /* ADC1, ADC2 common */
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#define STM32_ADC12_CMN_BASE (STM32_ADC12_CMN_OFFSET+STM32_ADC12_BASE) /* ADC1, ADC2 common */
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/* Register Offsets *********************************************************************************/
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/* Register Offsets *********************************************************************************/
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