arch/risc-v: Remove dupped irq code from fe310
Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
This commit is contained in:
Huang Qi
Xiang Xiao
parent
e81439a367
commit
8532feda78
@ -33,66 +33,43 @@
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/* Map RISC-V exception code to NuttX IRQ */
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/* IRQ 0-15 : (exception:interrupt=0) */
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#define FE310_IRQ_IAMISALIGNED (0) /* Instruction Address Misaligned */
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#define FE310_IRQ_IAFAULT (1) /* Instruction Address Fault */
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#define FE310_IRQ_IINSTRUCTION (2) /* Illegal Instruction */
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#define FE310_IRQ_BPOINT (3) /* Break Point */
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#define FE310_IRQ_LAMISALIGNED (4) /* Load Address Misaligned */
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#define FE310_IRQ_LAFAULT (5) /* Load Access Fault */
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#define FE310_IRQ_SAMISALIGNED (6) /* Store/AMO Address Misaligned */
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#define FE310_IRQ_SAFAULT (7) /* Store/AMO Access Fault */
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#define FE310_IRQ_ECALLU (8) /* Environment Call from U-mode */
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/* 9-10: Reserved */
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#define FE310_IRQ_ECALLM (11) /* Environment Call from M-mode */
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/* 12-15: Reserved */
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/* IRQ 16- : (async event:interrupt=1) */
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#define FE310_IRQ_ASYNC (16)
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#define FE310_IRQ_MSOFT (FE310_IRQ_ASYNC + 3) /* Machine Software Int */
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#define FE310_IRQ_MTIMER (FE310_IRQ_ASYNC + 7) /* Machine Timer Int */
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#define FE310_IRQ_MEXT (FE310_IRQ_ASYNC + 11) /* Machine External Int */
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/* Machine Global External Interrupt */
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#define FE310_IRQ_UART0 (FE310_IRQ_MEXT + 3)
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#define FE310_IRQ_UART1 (FE310_IRQ_MEXT + 4)
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#define FE310_IRQ_UART0 (RISCV_IRQ_MEXT + 3)
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#define FE310_IRQ_UART1 (RISCV_IRQ_MEXT + 4)
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#define FE310_IRQ_GPIO0 (FE310_IRQ_MEXT + 8)
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#define FE310_IRQ_GPIO1 (FE310_IRQ_MEXT + 9)
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#define FE310_IRQ_GPIO2 (FE310_IRQ_MEXT + 10)
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#define FE310_IRQ_GPIO3 (FE310_IRQ_MEXT + 11)
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#define FE310_IRQ_GPIO4 (FE310_IRQ_MEXT + 12)
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#define FE310_IRQ_GPIO5 (FE310_IRQ_MEXT + 13)
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#define FE310_IRQ_GPIO6 (FE310_IRQ_MEXT + 14)
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#define FE310_IRQ_GPIO7 (FE310_IRQ_MEXT + 15)
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#define FE310_IRQ_GPIO8 (FE310_IRQ_MEXT + 16)
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#define FE310_IRQ_GPIO9 (FE310_IRQ_MEXT + 17)
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#define FE310_IRQ_GPIO10 (FE310_IRQ_MEXT + 18)
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#define FE310_IRQ_GPIO11 (FE310_IRQ_MEXT + 19)
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#define FE310_IRQ_GPIO12 (FE310_IRQ_MEXT + 20)
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#define FE310_IRQ_GPIO13 (FE310_IRQ_MEXT + 21)
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#define FE310_IRQ_GPIO14 (FE310_IRQ_MEXT + 22)
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#define FE310_IRQ_GPIO15 (FE310_IRQ_MEXT + 23)
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#define FE310_IRQ_GPIO16 (FE310_IRQ_MEXT + 24)
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#define FE310_IRQ_GPIO17 (FE310_IRQ_MEXT + 25)
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#define FE310_IRQ_GPIO18 (FE310_IRQ_MEXT + 26)
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#define FE310_IRQ_GPIO19 (FE310_IRQ_MEXT + 27)
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#define FE310_IRQ_GPIO20 (FE310_IRQ_MEXT + 28)
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#define FE310_IRQ_GPIO21 (FE310_IRQ_MEXT + 29)
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#define FE310_IRQ_GPIO22 (FE310_IRQ_MEXT + 30)
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#define FE310_IRQ_GPIO23 (FE310_IRQ_MEXT + 31)
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#define FE310_IRQ_GPIO24 (FE310_IRQ_MEXT + 32)
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#define FE310_IRQ_GPIO25 (FE310_IRQ_MEXT + 33)
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#define FE310_IRQ_GPIO26 (FE310_IRQ_MEXT + 34)
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#define FE310_IRQ_GPIO27 (FE310_IRQ_MEXT + 35)
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#define FE310_IRQ_GPIO28 (FE310_IRQ_MEXT + 36)
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#define FE310_IRQ_GPIO29 (FE310_IRQ_MEXT + 37)
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#define FE310_IRQ_GPIO30 (FE310_IRQ_MEXT + 38)
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#define FE310_IRQ_GPIO31 (FE310_IRQ_MEXT + 39)
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#define FE310_IRQ_GPIO0 (RISCV_IRQ_MEXT + 8)
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#define FE310_IRQ_GPIO1 (RISCV_IRQ_MEXT + 9)
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#define FE310_IRQ_GPIO2 (RISCV_IRQ_MEXT + 10)
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#define FE310_IRQ_GPIO3 (RISCV_IRQ_MEXT + 11)
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#define FE310_IRQ_GPIO4 (RISCV_IRQ_MEXT + 12)
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#define FE310_IRQ_GPIO5 (RISCV_IRQ_MEXT + 13)
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#define FE310_IRQ_GPIO6 (RISCV_IRQ_MEXT + 14)
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#define FE310_IRQ_GPIO7 (RISCV_IRQ_MEXT + 15)
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#define FE310_IRQ_GPIO8 (RISCV_IRQ_MEXT + 16)
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#define FE310_IRQ_GPIO9 (RISCV_IRQ_MEXT + 17)
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#define FE310_IRQ_GPIO10 (RISCV_IRQ_MEXT + 18)
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#define FE310_IRQ_GPIO11 (RISCV_IRQ_MEXT + 19)
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#define FE310_IRQ_GPIO12 (RISCV_IRQ_MEXT + 20)
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#define FE310_IRQ_GPIO13 (RISCV_IRQ_MEXT + 21)
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#define FE310_IRQ_GPIO14 (RISCV_IRQ_MEXT + 22)
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#define FE310_IRQ_GPIO15 (RISCV_IRQ_MEXT + 23)
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#define FE310_IRQ_GPIO16 (RISCV_IRQ_MEXT + 24)
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#define FE310_IRQ_GPIO17 (RISCV_IRQ_MEXT + 25)
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#define FE310_IRQ_GPIO18 (RISCV_IRQ_MEXT + 26)
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#define FE310_IRQ_GPIO19 (RISCV_IRQ_MEXT + 27)
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#define FE310_IRQ_GPIO20 (RISCV_IRQ_MEXT + 28)
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#define FE310_IRQ_GPIO21 (RISCV_IRQ_MEXT + 29)
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#define FE310_IRQ_GPIO22 (RISCV_IRQ_MEXT + 30)
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#define FE310_IRQ_GPIO23 (RISCV_IRQ_MEXT + 31)
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#define FE310_IRQ_GPIO24 (RISCV_IRQ_MEXT + 32)
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#define FE310_IRQ_GPIO25 (RISCV_IRQ_MEXT + 33)
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#define FE310_IRQ_GPIO26 (RISCV_IRQ_MEXT + 34)
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#define FE310_IRQ_GPIO27 (RISCV_IRQ_MEXT + 35)
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#define FE310_IRQ_GPIO28 (RISCV_IRQ_MEXT + 36)
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#define FE310_IRQ_GPIO29 (RISCV_IRQ_MEXT + 37)
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#define FE310_IRQ_GPIO30 (RISCV_IRQ_MEXT + 38)
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#define FE310_IRQ_GPIO31 (RISCV_IRQ_MEXT + 39)
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/* Total number of IRQs */
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@ -84,7 +84,7 @@ void up_irqinitialize(void)
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/* Attach the ecall interrupt handler */
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irq_attach(FE310_IRQ_ECALLM, riscv_swint, NULL);
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irq_attach(RISCV_IRQ_ECALLM, riscv_swint, NULL);
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#ifndef CONFIG_SUPPRESS_INTERRUPTS
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@ -107,15 +107,15 @@ void up_disable_irq(int irq)
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int extirq;
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uint32_t oldstat;
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if (irq == FE310_IRQ_MTIMER)
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if (irq == RISCV_IRQ_MTIMER)
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{
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/* Read mstatus & clear machine timer interrupt enable in mie */
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asm volatile ("csrrc %0, mie, %1": "=r" (oldstat) : "r"(MIE_MTIE));
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}
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else if (irq > FE310_IRQ_MEXT)
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else if (irq > RISCV_IRQ_MEXT)
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{
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extirq = irq - FE310_IRQ_MEXT;
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extirq = irq - RISCV_IRQ_MEXT;
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/* Clear enable bit for the irq */
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@ -144,15 +144,15 @@ void up_enable_irq(int irq)
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int extirq;
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uint32_t oldstat;
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if (irq == FE310_IRQ_MTIMER)
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if (irq == RISCV_IRQ_MTIMER)
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{
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/* Read mstatus & set machine timer interrupt enable in mie */
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asm volatile ("csrrs %0, mie, %1": "=r" (oldstat) : "r"(MIE_MTIE));
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}
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else if (irq > FE310_IRQ_MEXT)
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else if (irq > RISCV_IRQ_MEXT)
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{
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extirq = irq - FE310_IRQ_MEXT;
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extirq = irq - RISCV_IRQ_MEXT;
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/* Set enable bit for the irq */
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@ -59,7 +59,7 @@ void *riscv_dispatch_irq(uintptr_t vector, uintptr_t *regs)
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/* Firstly, check if the irq is machine external interrupt */
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if (FE310_IRQ_MEXT == irq)
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if (RISCV_IRQ_MEXT == irq)
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{
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uint32_t val = getreg32(FE310_PLIC_CLAIM);
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@ -70,7 +70,7 @@ void *riscv_dispatch_irq(uintptr_t vector, uintptr_t *regs)
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/* NOTE: In case of ecall, we need to adjust mepc in the context */
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if (FE310_IRQ_ECALLM == irq)
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if (RISCV_IRQ_ECALLM == irq)
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{
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*mepc += 4;
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}
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@ -95,7 +95,7 @@ void *riscv_dispatch_irq(uintptr_t vector, uintptr_t *regs)
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irq_dispatch(irq, regs);
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if (FE310_IRQ_MEXT <= irq)
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if (RISCV_IRQ_MEXT <= irq)
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{
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/* If the irq is from GPIO, clear pending bit in the GPIO */
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@ -106,7 +106,7 @@ void *riscv_dispatch_irq(uintptr_t vector, uintptr_t *regs)
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/* Then write PLIC_CLAIM to clear pending in PLIC */
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putreg32(irq - FE310_IRQ_MEXT, FE310_PLIC_CLAIM);
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putreg32(irq - RISCV_IRQ_MEXT, FE310_PLIC_CLAIM);
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}
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#endif
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@ -118,7 +118,7 @@ void up_timer_initialize(void)
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{
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/* Attach timer interrupt handler */
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irq_attach(FE310_IRQ_MTIMER, fe310_timerisr, NULL);
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irq_attach(RISCV_IRQ_MTIMER, fe310_timerisr, NULL);
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/* Reload CLINT mtimecmp */
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@ -126,5 +126,5 @@ void up_timer_initialize(void)
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/* And enable the timer interrupt */
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up_enable_irq(FE310_IRQ_MTIMER);
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up_enable_irq(RISCV_IRQ_MTIMER);
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}
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