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git-svn-id: svn://svn.code.sf.net/p/nuttx/code/trunk@2865 42af7a65-404d-4744-a932-0658087f49c3
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@ -164,26 +164,30 @@ __start:
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teq r0, r2
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bne .Lpgtableclear
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/* Create identity mapping for first MB section to support this startup
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* logic executing out of the physical address space. This identity
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* mapping will be removed by .Lvstart (see below).
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/* Create identity mapping for first MB of the .text section to support
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* this startup logic executing out of the physical address space. This
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* identity mapping will be removed by .Lvstart (see below).
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*/
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#warning "We need to do things differently here if the .text region is smaller or if CONFIG_PAGING"
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mksection r0, r4 /* r0=phys. base section */
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ldr r1, .LCmmuflags /* FLGS=MMU_MEMFLAGS */
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add r3, r1, r0 /* r3=flags + base */
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str r3, [r4, r0, lsr #18] /* identity mapping */
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/* Create a "normal" single section mapping for the first
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* MB of memory. Now, we have the first 1MB mapping to
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* both phyical and virtual addresses. The reset of the
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* SDRAM mapping will be completed in .Lvstart once we have
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* moved the physical mapping out of the way.
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/* Create a virtual single section mapping for the first MB of the .text
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* address space. Now, we have the first 1MB mapping to both phyical and
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* virtual addresses. The rest of the .text mapping will be completed in
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* .Lvstart once we have moved the physical mapping out of the way.
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*/
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ldr r2, .LCvpgtable /* r2=virt. page table */
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mksection r0, r2 /* r0=virt. base section */
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str r3, [r4, r0, lsr #18] /* identity mapping */
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/* NOTE: No .data/.bss access should be attempted. This temporary mapping
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* can only be assumed to cover the initial .text region.
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*/
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#endif /* CONFIG_ARCH_ROMPGTABLE */
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/* The following logic will set up the ARM920/ARM926 for normal operation */
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@ -316,7 +320,10 @@ __start:
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.type .Lvstart, %function
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.Lvstart:
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/* Remove the temporary null mapping */
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/* Remove the temporary mapping. The following assumes that the
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* total RAM size is > 1Mb and extends that initial mapping to
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* cover additinal RAM sections.
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*/
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#ifndef CONFIG_ARCH_ROMPGTABLE
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ldr r4, .LCvpgtable /* r4=virtual page table */
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@ -328,7 +335,7 @@ __start:
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/* Now setup the pagetables for our normal SDRAM mappings mapped region.
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* We round NUTTX_START_VADDR down to the nearest megabyte boundary.
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*/
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#warning "We need to do things differently here if the .text region is smaller or if CONFIG_PAGING"
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ldr r1, .LCmmuflags /* FLGS=MMU_MEMFLAGS */
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add r3, r3, r1 /* r3=flags + base */
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@ -347,6 +354,19 @@ __start:
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add r3, r3, #SECTION_SIZE
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str r3, [r0], #4
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.endr
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/* If we are executing from RAM with a fixed page configuration, then
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* we can assume that the above contiguous mapping included all of the
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* .text, .data, .bss, heap, etc. But if we are executing from FLASH,
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* then the RAM area is probably in a separate physical address region
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* and will require a separate mapping. Or, if we are supporting on-demand
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* paging of the .text region, then the RAM-based .data/.bss/heap section
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* will still probably be located in a separate (virtual) address region.
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*/
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#if defined(CONFIG_BOOT_RUNFROMFLASH) || defined(CONFIG_PAGING)
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# error "Logic not implemented"
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#endif
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#endif /* CONFIG_ARCH_ROMPGTABLE */
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/* Zero BSS and set up the stack pointer */
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@ -363,6 +383,19 @@ __start:
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strcc fp, [r0],#4
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bcc .Lbssinit
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/* If the .data section is in a separate, unitialized address space,
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* then we will also need to copy the initial values of of the .data
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* section from the .text region into that .data region. This would
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* be the case if we are executing from FLASH and the .data section
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* lies in a different physical address region OR if we are support
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* on-demand paging and the .data section lies in a different virtual
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* address region.
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*/
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#if defined(CONFIG_BOOT_RUNFROMFLASH) || defined(CONFIG_PAGING)
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# error "Logic not implemented"
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#endif
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/* Perform early C-level, platform-specific initialization */
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bl up_boot
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@ -269,7 +269,7 @@ static void up_copyvectorblock(void)
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void up_boot(void)
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{
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/* __start provided the basic MMU mappings for SDRAM. Now provide mappings for all
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/* __start provided the basic MMU mappings for SRAM. Now provide mappings for all
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* IO regions (Including the vector region).
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*/
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