SAMA5D3x-EK: At support for the AT25 serial FLASH

configs/sam3u-ek/src/up_spi.c

@@ -89,7 +89,7 @@
  * Name: sam_spiinitialize
  *
  * Description:
- *   Called to configure SPI chip select GPIO pins for the SAM3U10E-EVAL board.
+ *   Called to configure SPI chip select GPIO pins for the SAM3U-EK board.
  *
  ************************************************************************************/
 

configs/sama5d3x-ek/README.txt

@@ -62,7 +62,6 @@ README
 Contents
 ========
 
-  - PIO Muliplexing
   - Development Environment
   - GNU Toolchain Options
   - IDEs
@@ -74,14 +73,10 @@ Contents
   - Creating and Using NORBOOT
   - Buttons and LEDs
   - Serial Consoles
+  - Serial FLASH
   - SAMA5D3x-EK Configuration Options
   - Configurations
 
-PIO Muliplexing
-===============
-
-  To be provided
-
 Development Environment
 =======================
 
@@ -513,6 +508,25 @@ Serial Consoles
     - Jumper JP16 not fitted: CDC is enabled
     - Jumper JP16 fitted : CDC is disabled"
 
+Serial FLASH
+============
+
+  Both the Ronetix and Embest versions of the SAMAD3x CPU modules include an
+  Atmel AT25DF321A, 32-megabit, 2.7-volt SPI serial flash.  The SPI
+  connection is as follows:
+
+    AT25DF321A      SAMA5
+    --------------- -----------------------------------------------
+    SI              PD11 SPI0_MOSI
+    SO              PD10 SPI0_MIS0
+    SCK             PD12 SPI0_SPCK
+    /CS             PD13 via NL17SZ126 if JP1 is closed (See below)
+
+  JP1 and JP2 seem to related to /CS on the Ronetix board, but the usage is
+  less clear.  For the Embest module, JP1 must be closed to connect /CS to
+  PD13; on the Ronetix schematic, JP11 seems only to bypass a resistor (may
+  not be populated?).  I think closing JP1 is correct in either case.
+
 SAMA5D3x-EK Configuration Options
 =================================
 
@@ -915,6 +929,24 @@ Configurations
         If the CPU speed changes, then so must the NOR and SDRAM
         initialization!
 
+    7. The Embest or Ronetix CPU module includes an Atmel AT25DF321A,
+       32-megabit, 2.7-volt SPI serial flash.  Support for that serial
+       FLASH can be enabled by modifying the NuttX configuration as
+       follows:
+
+       System Type -> SAMA5 Peripheral Support
+         CONFIG_SAMA5_SPI0=y                   : Enable SPI0
+
+       Device Drivers -> Memory Technology Device (MTD) Support
+         CONFIG_SPI=y                          : Enable SPI support
+         CONFIG_SPI_EXCHANGE=y                 : Support the exchange method
+
+       Device Drivers -> SPI Driver Support
+         CONFIG_MTD=y                          : Enable MTD support
+         CONFIG_MTD_AT25=y                     : Enable the AT25 driver
+         CONFIG_AT25_SPIMODE=0                 : Use SPI mode 0
+         CONFIG_AT25_SPIFREQUENCY=20000000     : Use SPI frequency 20MHz
+
       2013-7-31:  I have been unable to execute this configuration from NOR
         FLASH by closing the BMS jumper (J9).  As far as I can tell, this
         jumper does nothing on my board???  I have been using the norboot

configs/sama5d3x-ek/src/Makefile

@@ -46,6 +46,14 @@ ifeq ($(CONFIG_HAVE_CXX),y)
 CSRCS += sam_cxxinitialize.c
 endif
 
+ifeq ($(CONFIG_SAMA5_SPI0),y)
+CSRCS += sam_spi.c
+else
+ifeq ($(CONFIG_SAMA5_SPI1),y)
+CSRCS += sam_spi.c
+endif
+endif
+
 ifeq ($(CONFIG_SAMA5_DDRCS),y)
 CSRCS += sam_sdram.c
 endif

configs/sama5d3x-ek/src/sam_boot.c

@@ -67,6 +67,17 @@
 
 void sam_boardinitialize(void)
 {
+  /* Configure SPI chip selects if 1) SPI is enable, and 2) the weak function
+   * sam_spiinitialize() has been brought into the link.
+   */
+
+#if defined(CONFIG_SAMA5_SPI0) || defined(CONFIG_SAMA5_SPI1)
+  if (sam_spiinitialize)
+    {
+      sam_spiinitialize();
+    }
+#endif
+
 #if defined(CONFIG_SAMA5_DDRCS) && !defined(CONFIG_SAMA5_BOOT_SDRAM)
 
   /* Configure SDRAM if (1) SDRAM has been enalbled in the NuttX configuration and

configs/sama5d3x-ek/src/sam_spi.c

@@ -0,0 +1,216 @@
+/************************************************************************************
+ * configs/sama5d3x-ek/src/up_spi.c
+ *
+ *   Copyright (C) 2013 Gregory Nutt. All rights reserved.
+ *   Author: Gregory Nutt <gnutt@nuttx.org>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ************************************************************************************/
+
+/************************************************************************************
+ * Included Files
+ ************************************************************************************/
+
+#include <nuttx/config.h>
+
+#include <stdint.h>
+#include <stdbool.h>
+#include <debug.h>
+#include <errno.h>
+
+#include <nuttx/spi/spi.h>
+#include <arch/board/board.h>
+
+#include "up_arch.h"
+#include "chip.h"
+#include "sam_gpio.h"
+#include "sam_spi.h"
+#include "sama5d3x-ek.h"
+
+#if defined(CONFIG_SAMA5_SPI0) || defined(CONFIG_SAMA5_SPI1)
+
+/************************************************************************************
+ * Definitions
+ ************************************************************************************/
+
+/* Enables debug output from this file (needs CONFIG_DEBUG too) */
+
+#undef SPI_DEBUG   /* Define to enable debug */
+#undef SPI_VERBOSE /* Define to enable verbose debug */
+
+#ifdef SPI_DEBUG
+#  define spidbg  lldbg
+#  ifdef SPI_VERBOSE
+#    define spivdbg lldbg
+#  else
+#    define spivdbg(x...)
+#  endif
+#else
+#  undef SPI_VERBOSE
+#  define spidbg(x...)
+#  define spivdbg(x...)
+#endif
+
+/************************************************************************************
+ * Private Functions
+ ************************************************************************************/
+
+/************************************************************************************
+ * Public Functions
+ ************************************************************************************/
+
+/************************************************************************************
+ * Name: sam_spiinitialize
+ *
+ * Description:
+ *   Called to configure SPI chip select GPIO pins for the SAMA5D3x-EK board.
+ *
+ ************************************************************************************/
+
+void weak_function sam_spiinitialize(void)
+{
+#ifdef CONFIG_SAMA5_SPI0
+#ifdef CONFIG_MTD_AT25
+  /* The AT25 serial FLASH connects using NPCS0 */
+
+   sam_configgpio(GPIO_AT25_NPCS0);
+#endif
+#endif
+
+#ifdef CONFIG_SAMA5_SPI1
+#endif
+}
+
+/****************************************************************************
+ * Name:  sam_spi[0|1]select, sam_spi[0|1]status, and sam_spi[0|1]cmddata
+ *
+ * Description:
+ *   These external functions must be provided by board-specific logic.  They
+ *   include:
+ *
+ *   o sam_spi[0|1]select is a functions tomanage the board-specific chip selects
+ *   o sam_spi[0|1]status and sam_spi[0|1]cmddata:  Implementations of the status
+ *     and cmddata methods of the SPI interface defined by struct spi_ops_
+ *     (see include/nuttx/spi/spi.h). All other methods including
+ *     up_spiinitialize()) are provided by common SAM3/4 logic.
+ *
+ *  To use this common SPI logic on your board:
+ *
+ *   1. Provide logic in sam_boardinitialize() to configure SPI chip select
+ *      pins.
+ *   2. Provide sam_spi[0|1]select() and sam_spi[0|1]status() functions in your board-
+ *      specific logic.  These functions will perform chip selection and
+ *      status operations using GPIOs in the way your board is configured.
+ *   2. If CONFIG_SPI_CMDDATA is defined in the NuttX configuration, provide
+ *      sam_spi[0|1]cmddata() functions in your board-specific logic.  This
+ *      function will perform cmd/data selection operations using GPIOs in
+ *      the way your board is configured.
+ *   3. Add a call to up_spiinitialize() in your low level application
+ *      initialization logic
+ *   4. The handle returned by up_spiinitialize() may then be used to bind the
+ *      SPI driver to higher level logic (e.g., calling
+ *      mmcsd_spislotinitialize(), for example, will bind the SPI driver to
+ *      the SPI MMC/SD driver).
+ *
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name: sam_spi[0|1]select
+ *
+ * Description:
+ *   PIO chip select pins may be programmed by the board specific logic in
+ *   one of two different ways.  First, the pins may be programmed as SPI
+ *   peripherals.  In that case, the pins are completely controlled by the
+ *   SPI driver.  This method still needs to be provided, but it may be only
+ *   a stub.
+ *
+ *   An alternative way to program the PIO chip select pins is as a normal
+ *   GPIO output.  In that case, the automatic control of the CS pins is
+ *   bypassed and this function must provide control of the chip select.
+ *   NOTE:  In this case, the GPIO output pin does *not* have to be the
+ *   same as the NPCS pin normal associated with the chip select number.
+ *
+ * Input Parameters:
+ *   devid - Identifies the (logical) device
+ *   selected - TRUE:Select the device, FALSE:De-select the device
+ *
+ * Returned Values:
+ *   None
+ *
+ ****************************************************************************/
+
+#ifdef CONFIG_SAMA5_SPI0
+void sam_spi0select(enum spi_dev_e devid, bool selected)
+{
+#ifdef CONFIG_MTD_AT25
+  /* The AT25 serial FLASH connects using NPCS0 */
+
+  if (devid == SPIDEV_FLASH)
+    {
+      sam_gpiowrite(GPIO_AT25_NPCS0, !selected);
+    }
+#endif
+}
+#endif
+
+#ifdef CONFIG_SAMA5_SPI1
+void sam_spi1select(enum spi_dev_e devid, bool selected)
+{
+}
+#endif
+
+/****************************************************************************
+ * Name: sam_spi[0|1]status
+ *
+ * Description:
+ *   Return status information associated with the SPI device.
+ *
+ * Input Parameters:
+ *   devid - Identifies the (logical) device
+ *
+ * Returned Values:
+ *   Bit-encoded SPI status (see include/nuttx/spi/spi.h.
+ *
+ ****************************************************************************/
+
+#ifdef CONFIG_SAMA5_SPI0
+uint8_t sam_spi0status(FAR struct spi_dev_s *dev, enum spi_dev_e devid)
+{
+  return 0;
+}
+#endif
+
+#ifdef CONFIG_SAMA5_SPI0
+uint8_t sam_spi1status(FAR struct spi_dev_s *dev, enum spi_dev_e devid)
+{
+  return 0;
+}
+#endif
+
+#endif /* CONFIG_SAMA5_SPI0 || CONFIG_SAMA5_SPI1 */

configs/sama5d3x-ek/src/sama5d3x-ek.h

@@ -94,6 +94,28 @@
                       GPIO_INT_BOTHEDGES | GPIO_PORT_PIOE | GPIO_PIN27)
 #define IRQ_USER1    SAM_IRQ_PE27
 
+/* SPI Chip Selects *****************************************************************/
+/* Both the Ronetix and Embest versions of the SAMAD3x CPU modules include an
+ * Atmel AT25DF321A, 32-megabit, 2.7-volt SPI serial flash.  The SPI
+ * connection is as follows:
+ *
+ *   AT25DF321A      SAMA5
+ *   --------------- -----------------------------------------------
+ *   SI              PD11 SPI0_MOSI
+ *   SO              PD10 SPI0_MIS0
+ *   SCK             PD12 SPI0_SPCK
+ *   /CS             PD13 via NL17SZ126 if JP1 is closed (See below)
+ *
+ * JP1 and JP2 seem to related to /CS on the Ronetix board, but the usage is
+ * less clear.  For the Embest module, JP1 must be closed to connect /CS to
+ * PD13; on the Ronetix schematic, JP11 seems only to bypass a resistor (may
+ * not be populated?).  I think closing JP1 is correct in either case.
+ */
+
+#define GPIO_AT25_NPCS0 (GPIO_OUTPUT | GPIO_CFG_PULLUP | GPIO_OUTPUT_SET | \
+                         GPIO_PORT_PIOD | GPIO_PIN13)
+#define AT25_CSNUM      0
+
 /************************************************************************************
  * Public Types
  ************************************************************************************/
@@ -108,6 +130,18 @@
  * Public Functions
  ************************************************************************************/
 
+/************************************************************************************
+ * Name: sam_spiinitialize
+ *
+ * Description:
+ *   Called to configure SPI chip select PIO pins for the SAMA4D3x-EK board.
+ *
+ ************************************************************************************/
+
+#if defined(CONFIG_SAMA5_SPI0) || defined(CONFIG_SAMA5_SPI1)
+void weak_function sam_spiinitialize(void);
+#endif
+
 /************************************************************************************
  * Name: board_sdram_config
  *