arch/arm/src/max326xx/chip: Add I2C register definition header file.
This commit is contained in:
Gregory Nutt
parent
6673ae3e9c
commit
854f171c66
@ -201,6 +201,10 @@ config MAX326XX_HAVE_SPIM
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bool
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default n
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config MAX326XX_HAVE_UART
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bool
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default n
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# Peripheral Driver Selections
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config MAX326XX_WDOG
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@ -348,16 +352,19 @@ config MAX326XX_I2CS1
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config MAX326XX_UART0
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bool "UART 0"
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default n
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select MAX326XX_HAVE_UART
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select UART0_SERIALDRIVER
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config MAX326XX_UART1
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bool "UART 1"
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default n
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select MAX326XX_HAVE_UART
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select UART1_SERIALDRIVER
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config MAX326XX_UART2
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bool "UART 2"
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default n
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select MAX326XX_HAVE_UART
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select UART2_SERIALDRIVER
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depends on MAX326XX_HAVE_UART2
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@ -33,6 +33,8 @@
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#
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############################################################################
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# Common ARMv7-M Source Files
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HEAD_ASRC =
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CMN_ASRCS = up_saveusercontext.S up_fullcontextrestore.S up_switchcontext.S
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@ -75,9 +77,21 @@ CMN_ASRCS += up_fpu.S
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CMN_CSRCS += up_copyarmstate.c
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endif
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# Common MAX326XX Source Files
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CHIP_ASRCS =
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CHIP_CSRCS = max326_start.c max326_clockconfig.c max326_irq.c max326_clrpend.c
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CHIP_CSRCS += max326_allocateheap.c max326_lowputc.c max326_gpio.c
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CHIP_CSRCS += max326_allocateheap.c
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# Source Files for the MAX32620 and MAX32630
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# Source Files for the MAX32660
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ifeq ($(CONFIG_ARCH_FAMILY_MAX32660),y)
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CHIP_CSRCS += max32660_lowputc.c max32660_gpio.c
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endif
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# Configuration-Dependent Source Files
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ifneq ($(CONFIG_SCHED_TICKLESS),y)
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CHIP_CSRCS += max326_timerisr.c
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@ -90,7 +104,9 @@ CHIP_CSRCS += max326_userspace.c max326_mpuinit.c
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endif
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ifeq ($(CONFIG_MAX326_DMA),y)
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CHIP_CSRCS += max326_dma.c
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ifeq ($(CONFIG_ARCH_FAMILY_MAX32660),y)
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CHIP_CSRCS += max32660_dma.c
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endif
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endif
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ifneq ($(CONFIG_ARCH_IDLE_CUSTOM),y)
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@ -98,32 +114,42 @@ CHIP_CSRCS += max326_idle.c
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endif
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ifeq ($(CONFIG_MAX326_GPIOIRQ),y)
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CHIP_CSRCS += max326_gpioirq.c
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ifeq ($(CONFIG_ARCH_FAMILY_MAX32660),y)
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CHIP_CSRCS += max32660_gpioirq.c
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endif
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endif
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ifeq ($(CONFIG_RTC),y)
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CHIP_CSRCS += max326_rtc.c
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ifeq ($(CONFIG_ARCH_FAMILY_MAX32660),y)
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CHIP_CSRCS += max32660_rtc.c
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endif
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ifeq ($(CONFIG_RTC_DRIVER),y)
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CHIP_CSRCS += max326_rtc_lowerhalf.c
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endif
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endif
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ifeq ($(CONFIG_MAX326_WDT),y)
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CHIP_CSRCS += max326_wdt.c
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ifeq ($(CONFIG_ARCH_FAMILY_MAX32660),y)
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CHIP_CSRCS += max32660_wdt.c
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endif
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endif
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ifeq ($(CONFIG_MAX326_RNG),y)
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CHIP_CSRCS += max326_rng.c
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endif
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ifeq ($(CONFIG_MAX326_HAVE_USART),y)
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CHIP_CSRCS += max326_serial.c
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ifeq ($(CONFIG_MAX326XX_HAVE_UART),y)
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ifeq ($(CONFIG_ARCH_FAMILY_MAX32660),y)
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CHIP_CSRCS += max32660_serial.c
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endif
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endif
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ifeq ($(CONFIG_MAX326XX_HAVE_I2CM),y)
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CHIP_CSRCS += max326_i2c_master.c
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ifeq ($(CONFIG_ARCH_FAMILY_MAX32660),y)
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CHIP_CSRCS += max32660_i2cm.c
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endif
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endif
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ifeq ($(CONFIG_MAX326XX_HAVE_SPIM),y)
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CHIP_CSRCS += max326_spi_master.c
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CHIP_CSRCS += max326_spim.c
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endif
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301
arch/arm/src/max326xx/chip/max32660_i2c.h
Normal file
301
arch/arm/src/max326xx/chip/max32660_i2c.h
Normal file
@ -0,0 +1,301 @@
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/************************************************************************************
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* arch/arm/src/max326xx/chip/max326_i2c.h
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*
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* Copyright (C) 2018 Gregory Nutt. All rights reserved.
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* Author: Gregory Nutt <gnutt@nuttx.org>
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in
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* the documentation and/or other materials provided with the
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* distribution.
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* 3. Neither the name NuttX nor the names of its contributors may be
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* used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
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* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
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* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
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* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
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* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
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* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
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* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*
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************************************************************************************/
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#ifndef __ARCH_ARM_SRC_MAX326XX_CHIP_MAX326_I2C_H
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#define __ARCH_ARM_SRC_MAX326XX_CHIP_MAX326_I2C_H
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/************************************************************************************
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* Included Files
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************************************************************************************/
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#include <nuttx/config.h>
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#include "chip/max326_memorymap.h"
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/************************************************************************************
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* Pre-processor Definitions
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************************************************************************************/
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/* Register Offsets *****************************************************************/
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#define MAX326_I2C_CTRL0_OFFSET 0x0000 /* I2C Control 0 Register */
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#define MAX326_I2C_STATUS_OFFSET 0x0004 /* I2C Status Register */
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#define MAX326_I2C_INTFL0_OFFSET 0x0008 /* I2C Interrupt Flags 0 Register */
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#define MAX326_I2C_INTEN0_OFFSET 0x000c /* I2C Interrupt Enable 0 Register */
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#define MAX326_I2C_INTFL1_OFFSET 0x0010 /* I2C Interrupts Flags 1 Register */
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#define MAX326_I2C_INTEN1_OFFSET 0x0014 /* I2C Interrupts Enable 1 Register */
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#define MAX326_I2C_FIFOLEN_OFFSET 0x0018 /* I2C FIFO Length Register */
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#define MAX326_I2C_RXCTRL0_OFFSET 0x001c /* I2C Receive Control 0 Register */
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#define MAX326_I2C_RXCTRL1_OFFSET 0x0020 /* I2C Receive Control 1 Register 1 */
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#define MAX326_I2C_TXCTRL0_OFFSET 0x0024 /* I2C Transmit Control 0 Register 0 */
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#define MAX326_I2C_TXCTRL1_OFFSET 0x0028 /* I2C Transmit Control 1 Register 1 */
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#define MAX326_I2C_FIFO_OFFSET 0x002c /* I2C Transmit and Receive FIFO Register */
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#define MAX326_I2C_MSTRMODE_OFFSET 0x0030 /* I2C Master Mode Register */
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#define MAX326_I2C_CLKLO_OFFSET 0x0034 /* I2C Clock Low Time Register */
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#define MAX326_I2C_CLKHI_OFFSET 0x0038 /* I2C Clock High Time Register */
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#define MAX326_I2C_HSCLK_OFFSET 0x003c /* I2C Hs-Mode Clock Control Register */
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#define MAX326_I2C_TIMEOUT_OFFSET 0x0040 /* I2C Timeout Register */
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#define MAX326_I2C_SLADDR_OFFSET 0x0044 /* I2C Slave Address Register */
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#define MAX326_I2C_DMA_OFFSET 0x0048 /* I2C DMA Enable Register */
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/* Register Addresses ***************************************************************/
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#define MAX326_I2C0_CTRL0 (MAX326_I2C0_BASE + MAX326_I2C_CTRL0_OFFSET)
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#define MAX326_I2C0_STATUS (MAX326_I2C0_BASE + MAX326_I2C_STATUS_OFFSET)
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#define MAX326_I2C0_INTFL0 (MAX326_I2C0_BASE + MAX326_I2C_INTFL0_OFFSET)
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#define MAX326_I2C0_INTEN0 (MAX326_I2C0_BASE + MAX326_I2C_INTEN0_OFFSET)
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#define MAX326_I2C0_INTFL1 (MAX326_I2C0_BASE + MAX326_I2C_INTFL1_OFFSET)
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#define MAX326_I2C0_INTEN1 (MAX326_I2C0_BASE + MAX326_I2C_INTEN1_OFFSET)
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#define MAX326_I2C0_FIFOLEN (MAX326_I2C0_BASE + MAX326_I2C_FIFOLEN_OFFSET)
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#define MAX326_I2C0_RXCTRL0 (MAX326_I2C0_BASE + MAX326_I2C_RXCTRL0_OFFSET)
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#define MAX326_I2C0_RXCTRL1 (MAX326_I2C0_BASE + MAX326_I2C_RXCTRL1_OFFSET)
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#define MAX326_I2C0_TXCTRL0 (MAX326_I2C0_BASE + MAX326_I2C_TXCTRL0_OFFSET)
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#define MAX326_I2C0_TXCTRL1 (MAX326_I2C0_BASE + MAX326_I2C_TXCTRL1_OFFSET)
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#define MAX326_I2C0_FIFO (MAX326_I2C0_BASE + MAX326_I2C_FIFO_OFFSET)
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#define MAX326_I2C0_MSTRMODE (MAX326_I2C0_BASE + MAX326_I2C_MSTRMODE_OFFSET)
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#define MAX326_I2C0_CLKLO (MAX326_I2C0_BASE + MAX326_I2C_CLKLO_OFFSET)
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#define MAX326_I2C0_CLKHI (MAX326_I2C0_BASE + MAX326_I2C_CLKHI_OFFSET)
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#define MAX326_I2C0_HSCLK (MAX326_I2C0_BASE + MAX326_I2C_HSCLK_OFFSET)
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#define MAX326_I2C0_TIMEOUT (MAX326_I2C0_BASE + MAX326_I2C_TIMEOUT_OFFSET)
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#define MAX326_I2C0_SLADDR (MAX326_I2C0_BASE + MAX326_I2C_SLADDR_OFFSET)
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#define MAX326_I2C0_DMA (MAX326_I2C0_BASE + MAX326_I2C_DMA_OFFSET)
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#define MAX326_I2C1_CTRL0 (MAX326_I2C1_BASE + MAX326_I2C_CTRL0_OFFSET)
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#define MAX326_I2C1_STATUS (MAX326_I2C1_BASE + MAX326_I2C_STATUS_OFFSET)
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#define MAX326_I2C1_INTFL0 (MAX326_I2C1_BASE + MAX326_I2C_INTFL0_OFFSET)
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#define MAX326_I2C1_INTEN0 (MAX326_I2C1_BASE + MAX326_I2C_INTEN0_OFFSET)
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#define MAX326_I2C1_INTFL1 (MAX326_I2C1_BASE + MAX326_I2C_INTFL1_OFFSET)
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#define MAX326_I2C1_INTEN1 (MAX326_I2C1_BASE + MAX326_I2C_INTEN1_OFFSET)
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#define MAX326_I2C1_FIFOLEN (MAX326_I2C1_BASE + MAX326_I2C_FIFOLEN_OFFSET)
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#define MAX326_I2C1_RXCTRL0 (MAX326_I2C1_BASE + MAX326_I2C_RXCTRL0_OFFSET)
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#define MAX326_I2C1_RXCTRL1 (MAX326_I2C1_BASE + MAX326_I2C_RXCTRL1_OFFSET)
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#define MAX326_I2C1_TXCTRL0 (MAX326_I2C1_BASE + MAX326_I2C_TXCTRL0_OFFSET)
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#define MAX326_I2C1_TXCTRL1 (MAX326_I2C1_BASE + MAX326_I2C_TXCTRL1_OFFSET)
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#define MAX326_I2C1_FIFO (MAX326_I2C1_BASE + MAX326_I2C_FIFO_OFFSET)
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#define MAX326_I2C1_MSTRMODE (MAX326_I2C1_BASE + MAX326_I2C_MSTRMODE_OFFSET)
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#define MAX326_I2C1_CLKLO (MAX326_I2C1_BASE + MAX326_I2C_CLKLO_OFFSET)
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#define MAX326_I2C1_CLKHI (MAX326_I2C1_BASE + MAX326_I2C_CLKHI_OFFSET)
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#define MAX326_I2C1_HSCLK (MAX326_I2C1_BASE + MAX326_I2C_HSCLK_OFFSET)
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#define MAX326_I2C1_TIMEOUT (MAX326_I2C1_BASE + MAX326_I2C_TIMEOUT_OFFSET)
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#define MAX326_I2C1_SLADDR (MAX326_I2C1_BASE + MAX326_I2C_SLADDR_OFFSET)
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#define MAX326_I2C1_DMA (MAX326_I2C1_BASE + MAX326_I2C_DMA_OFFSET)
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/* Register Bit-field Definitions ***************************************************/
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/* I2C Control 0 Register */
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#define I2C_CTRL0_I2CEN (1 << 0) /* Bit 0: I2C Enable */
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#define I2C_CTRL0_MST (1 << 1) /* Bit 1: Master Mode Enable */
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#define I2C_CTRL0_GCEN (1 << 2) /* Bit 2: General Call Address Enable */
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#define I2C_CTRL0_IRXM (1 << 3) /* Bit 3: Interactive Receive Mode (IRXM) */
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#define I2C_CTRL0_ACK (1 << 4) /* Bit 4: Interactive Receive Mode (IRXM)
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* Acknowledge */
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#define I2C_CTRL0_SCLO (1 << 6) /* Bit 6: SCL Pin Control */
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#define I2C_CTRL0_SDAO (1 << 7) /* Bit 7: SDA Pin Control */
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#define I2C_CTRL0_SCL (1 << 8) /* Bit 8: SCL Status */
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#define I2C_CTRL0_SDA (1 << 9) /* Bit 9: SDA Status */
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#define I2C_CTRL0_SWOE (1 << 10) /* Bit 10: Software output Enabled */
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#define I2C_CTRL0_READ (1 << 11) /* Bit 11: Read/Write Bit Status */
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#define I2C_CTRL0_SCLSTRD (1 << 12) /* Bit 12: SCL Clock Stretch Control */
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#define I2C_CTRL0_SCLPPM (1 << 13) /* Bit 13: SCL Push-Pull Mode Enable */
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#define I2C_CTRL0_HSMODE (1 << 15) /* Bit 15: High Speed Mode */
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/* I2C Status Register */
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#define I2C_STATUS_BUSY (1 << 0) /* Bit 0: Bus Busy */
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#define I2C_STATUS_RXE (1 << 1) /* Bit 1: RX FIFO Empty */
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#define I2C_STATUS_RXF (1 << 2) /* Bit 2: RX FIFO Full */
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#define I2C_STATUS_TXE (1 << 3) /* Bit 3: TX FIFO Empty */
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#define I2C_STATUS_TXF (1 << 4) /* Bit 4: TX FIFO Full */
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#define I2C_STATUS_CKMD (1 << 5) /* Bit 5: SCL Drive Status */
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#define I2C_STATUS_STAT_SHIFT (8) /* Bits 8-11: I2C Controller Status */
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#define I2C_STATUS_STAT_MASK (15 << I2C_STATUS_STAT_SHIFT)
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# define I2C_STATUS_STAT_IDLE (0 << I2C_STATUS_STAT_SHIFT) /* Idle */
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# define I2C_STATUS_STAT_MTXADDR (1 << I2C_STATUS_STAT_SHIFT) /* Master Transmit
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* address */
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# define I2C_STATUS_STAT_MRXACK (2 << I2C_STATUS_STAT_SHIFT) /* Master Receive
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* address ACK */
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# define I2C_STATUS_STAT_MTXEXTADDR (3 << I2C_STATUS_STAT_SHIFT) /* Master Transmit
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* extended address */
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# define I2C_STATUS_STAT_MRXEXTACK (4 << I2C_STATUS_STAT_SHIFT) /* Master Receive
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* extended address
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* ACK */
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# define I2C_STATUS_STAT_SRXADDR (5 << I2C_STATUS_STAT_SHIFT) /* Slave Receive
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* address */
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# define I2C_STATUS_STAT_STXRACK (6 << I2C_STATUS_STAT_SHIFT) /* Slave Transmit
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* address ACK */
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# define I2C_STATUS_STAT_SRXEXTADDR (7 << I2C_STATUS_STAT_SHIFT) /* Slave Receive
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* extended address */
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# define I2C_STATUS_STAT_STXEXTACK (8 << I2C_STATUS_STAT_SHIFT) /* Slave transit
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* extended address
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* ACK */
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# define I2C_STATUS_STAT_TXDATA (9 << I2C_STATUS_STAT_SHIFT) /* Transmit data
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* (Master or Slave) */
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# define I2C_STATUS_STAT_RXACK (10 << I2C_STATUS_STAT_SHIFT) /* Receive data ACK
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* (Master or Slave) */
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# define I2C_STATUS_STAT_RXDATA (11 << I2C_STATUS_STAT_SHIFT) /* Receive data
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* (Master or Slave) */
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# define I2C_STATUS_STAT_TXACK (12 << I2C_STATUS_STAT_SHIFT) /* Transmit data ACK
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* (Master or Slave) */
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# define I2C_STATUS_STAT_NACK (13 << I2C_STATUS_STAT_SHIFT) /* NACK stage (Master
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* or Slave) */
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# define I2C_STATUS_STAT_MBUSY (15 << I2C_STATUS_STAT_SHIFT) /* Another master is
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* addressing another
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* slave. */
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/* I2C Interrupt Flags 0 Register and I2C Interrupt Enable 0 Register */
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#define I2C_INT0_DONEI (1 << 0) /* Bit 0: Transfer Complete Interrupt */
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#define I2C_INT0_IRXMI (1 << 1) /* Bit 1: Interactive Receive Mode
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* Interrupt */
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#define I2C_INT0_GCI (1 << 2) /* Bit 2: General Call Address Match
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* Received Interrupt (slave) */
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#define I2C_INT0_AMI (1 << 3) /* Bit 3: Address Match Status Interrupt
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* (slave) */
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#define I2C_INT0_RXTHI (1 << 4) /* Bit 4: RX FIFO Threshold Level Interrupt */
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#define I2C_INT0_TXTHI (1 << 5) /* Bit 5: TX FIFO Threshold Level Interrupt */
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#define I2C_INT0_STOPI (1 << 6) /* Bit 6: Slave Mode: STOP Condition
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* Interrupt (slave) */
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#define I2C_INT0_ADRACKI (1 << 7) /* Bit 7: Address ACK from External Slave
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* Interrupt (master) */
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#define I2C_INT0_ARBERI (1 << 8) /* Bit 8: Arbitration Lost Interrupt
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* (master) */
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#define I2C_INT0_TOERI (1 << 9) /* Bit 9: Timeout Error Interrupt */
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#define I2C_INT0_ADRERI (1 << 10) /* Bit 10: Address NACK from Slave Error
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* (master) */
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#define I2C_INT0_DATERI (1 << 11) /* Bit 11: Data NACK from External Slave
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* Interrupt (master) */
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#define I2C_INT0_DNRERI (1 << 12) /* Bit 12: Slave Mode Do Not Respond
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* Interrupt */
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#define I2C_INT0_STRTERI (1 << 13) /* Bit 13: Out of Sequence START Interrupt */
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#define I2C_INT0_STOPERI (1 << 14) /* Bit 14: Out of Sequence STOP Interrupt */
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#define I2C_INT0_TXLOI (1 << 15) /* Bit 15: TX FIFO Locked Interrupt */
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/* I2C Interrupts Flags 1 Register and I2C Interrupts Enable 1 Register */
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#define I2C_INT1_RXOFI (1 << 0) /* Bit 0: RX FIFO Overflow Interrupt
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* (slave) */
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#define I2C_INT1_TXUFI (1 << 1) /* Bit 1: TX FIFO Underflow Interrupt
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* (slave) */
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/* I2C FIFO Length Register */
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#define I2C_FIFOLEN_RXLEN_SHIFT (0) /* Bits 0-7: RX FIFO Length */
|
||||
#define I2C_FIFOLEN_RXLEN_MASK (0xff << I2C_FIFOLEN_RXLEN_SHIFT)
|
||||
#define I2C_FIFOLEN_TXLEN_SHIFT (8) /* Bits 8-15: TX FIFO Length */
|
||||
#define I2C_FIFOLEN_TXLEN_MASK (0xff << I2C_FIFOLEN_TXLEN_SHIFT)
|
||||
|
||||
/* I2C Receive Control 0 Register */
|
||||
|
||||
#define I2C_RXCTRL0_DNR (1 << 0) /* Bit 0: Do Not Respond (slave) */
|
||||
#define I2C_RXCTRL0_RXFSH (1 << 7) /* Bit 7: Flush RX FIFO */
|
||||
#define I2C_RXCTRL0_RXTH_SHIFT (8) /* Bits 8-11: RX FIFO Threshold Level */
|
||||
#define I2C_RXCTRL0_RXTH_MASK (15 << I2C_RXCTRL0_RXTH_SHIFT)
|
||||
|
||||
/* I2C Receive Control 1 Register 1 */
|
||||
|
||||
#define I2C_RXCTRL1_RXCNT_SHIFT (0) /* Bits 0-7: RX FIFO Transaction Byte Count */
|
||||
#define I2C_RXCTRL1_RXCNT_MASK (0xff << I2C_RXCTRL1_RXCNT_SHIFT)
|
||||
# define I2C_RXCTRL1_RXCNT(n) ((uint16_t)((n) & 0xff) << I2C_RXCTRL1_RXFIFO_SHIFT)
|
||||
#define I2C_RXCTRL1_RXFIFO_SHIFT (8) /* Bits 8-11: RX FIFO Byte Count */
|
||||
#define I2C_RXCTRL1_RXFIFO_MASK (15 << I2C_RXCTRL1_RXFIFO_SHIFT)
|
||||
|
||||
/* I2C Transmit Control 0 Register 0 */
|
||||
|
||||
#define I2C_TXCTRL0_TXPRELD (1 << 0) /* Bit 0: TX FIFO Preload Mode Enable */
|
||||
#define I2C_TXCTRL0_TXFSH (1 << 7) /* Bit 7: Flush TX FIFO */
|
||||
#define I2C_TXCTRL0_TXTH_SHIFT (8) /* Bits 8-11: TX FIFO Threshold Level */
|
||||
#define I2C_TXCTRL0_TXTH_MASK (15 << I2C_TXCTRL0_TXTH_SHIFT)
|
||||
|
||||
/* I2C Transmit Control 1 Register 1 */
|
||||
|
||||
#define I2C_TXCTRL1_TXRDY (1 << 0) /* Bit 0: Transmit FIFO Preload Ready
|
||||
* Status */
|
||||
#define I2C_TXCTRL1_TXLAST (1 << 1) /* Bit 1: Transmit Last (slave) */
|
||||
#define I2C_TXCTRL1_FLSH_GCADDRDIS (1 << 2) /* Bit 2: TX FIFO Auto Flush Disable on
|
||||
* General Call Address Match */
|
||||
#define I2C_TXCTRL1_FLSH_SLADDRDIS (1 << 4) /* Bit 4: TX FIFO Auto Flush Disable for
|
||||
* Slave Address Match */
|
||||
#define I2C_TXCTRL1_FLSH_NACKDIS (1 << 5) /* Bit 5: TX FIFO Auto Flush Disable for
|
||||
* NACK */
|
||||
#define I2C_TXCTRL1_TXFIFO_SHIFT (8) /* Bits 8-11: TX FIFO Byte Count */
|
||||
#define I2C_TXCTRL1_TXFIFO_MASK (15 << I2C_TXCTRL1_TXFIFO_SHIFT)
|
||||
|
||||
/* I2C Transmit and Receive FIFO Register */
|
||||
|
||||
#define I2C_FIFO_MASK (0xff) /* Bits 0-7: I2C FIFO Data */
|
||||
|
||||
/* I2C Master Mode Register */
|
||||
|
||||
#define I2C_MSTRMODE_START (1 << 0) /* Bit 0: Start Master Mode Transfer */
|
||||
#define I2C_MSTRMODE_RESTART (1 << 1) /* Bit 1: Send Repeated START Condition */
|
||||
#define I2C_MSTRMODE_STOP (1 << 2) /* Bit 2: Send STOP Condition */
|
||||
#define I2C_MSTRMODE_SEA (1 << 7) /* Bit 7: Slave Extended Addressing */
|
||||
|
||||
/* I2C Clock Low Time Register */
|
||||
|
||||
#define I2C_CLKLO_MASK (0x1ff) /* Bits 0-8: Clock Low Time */
|
||||
|
||||
/* I2C Clock High Time Register */
|
||||
|
||||
#define I2C_CLKHI_MASK (0x1ff) /* Bits 0-8: Clock High Time */
|
||||
|
||||
/* I2C Hs-Mode Clock Control Register */
|
||||
|
||||
#define I2C_HSCLK_HSCLKLO_SHIFT (0) /* Bits 0-7: Hs-Mode Clock Low Time */
|
||||
#define I2C_HSCLK_HSCLKLO_MASK (0xff << I2C_HSCLK_HSCLKLO_SHIFT)
|
||||
# define I2C_HSCLK_HSCLKLO(n) ((uint32_t)((n) - 1) << I2C_HSCLK_HSCLKLO_SHIFT)
|
||||
#define I2C_HSCLK_HSCLKHI_SHIFT (8) /* Bits 8-15: Hs-Mode Clock High Time */
|
||||
#define I2C_HSCLK_HSCLKHI_MASK (0xff << I2C_HSCLK_HSCLKHI_SHIFT)
|
||||
# define I2C_HSCLK_HSCLKHI(n) ((uint32_t)((n) - 1) << I2C_HSCLK_HSCLKHI_SHIFT)
|
||||
|
||||
/* I2C Timeout Register */
|
||||
|
||||
#define I2C_TIMEOUT_MASK (0xffff) /* Bits 0-15: Bus Error SCL Timeout Period */
|
||||
|
||||
/* I2C Slave Address Register */
|
||||
|
||||
#define I2C_SLADDR_SLA_SHIFT (0) /* Bits 0-9: Slave Mode Slave Address */
|
||||
#define I2C_SLADDR_SLA_MASK (0x3ff << I2C_SLADDR_SLA_SHIFT)
|
||||
# define I2C_SLADDR_SLA(n) ((uint32_t)(n) << I2C_SLADDR_SLA_SHIFT)
|
||||
#define I2C_SLADDR_EA (1 << 15) /* Bit 15: Slave Mode Extended Address
|
||||
* Select */
|
||||
|
||||
/* I2C DMA Enable Register */
|
||||
|
||||
#define I2C_DMA_TXEN (1 << 0) /* Bit 0: TX DMA Channel Enable */
|
||||
#define I2C_DMA_RXEN (1 << 1) /* Bit 1: RX DMA Channel Enable */
|
||||
|
||||
#endif /* __ARCH_ARM_SRC_MAX326XX_CHIP_MAX326_I2C_H */
|
||||
@ -69,19 +69,13 @@
|
||||
#define MAX326_TMR2_BASE 0x40012000 /* TMR2 */
|
||||
#define MAX326_SPIMSS_BASE 0x40019000 /* SPIMSS (I2S) */
|
||||
#define MAX326_I2C0_BASE 0x4001d000 /* I2CM 0 Master/Slave */
|
||||
# define MAX326_I2CM0_BASE 0x4001d000 /* I2CM 0 Master */
|
||||
# define MAX326_I2CS0_BASE 0x4001d000 /* I2CS 0 Slave */
|
||||
#define MAX326_I2C1_BASE 0x4001e000 /* I2CM 1 Master/Slave */
|
||||
# define MAX326_I2CM1_BASE 0x4001e000 /* I2CM 1 Master */
|
||||
# define MAX326_I2CS1_BASE 0x4001e000 /* I2CS 1 Slave */
|
||||
#define MAX326_DMA_BASE 0x40028000 /* Standard DMA */
|
||||
#define MAX326_FLC_BASE 0x40029000 /* FLASH Controller */
|
||||
#define MAX326_ICC_BASE 0x4002a000 /* Internal Cache Controller */
|
||||
#define MAX326_UART0_BASE 0x40042000 /* UART 0 */
|
||||
#define MAX326_UART1_BASE 0x40043000 /* UART 1 */
|
||||
#define MAX326_SPI0_BASE 0x40046000 /* SPIM 0 Master/Slave */
|
||||
# define MAX326_SPIM0_BASE 0x40046000 /* SPIM 0 Master */
|
||||
# define MAX326_SPIS0_BASE 0x40046000 /* SPIS 0 Slave */
|
||||
|
||||
/********************************************************************************************
|
||||
* Public Types
|
||||
|
||||
Loading…
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Reference in New Issue
Block a user