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SAMD/L: Hide differences in the way peripheral clocking is enabled behind macros. Some updates to saml_clockconfig.h + various fixes while working toward SAML21 build

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This commit is contained in:
Gregory Nutt 2015-05-19 11:03:24 -06:00
parent ce5d03c763
commit 857a2d08d9
14 changed files with 957 additions and 185 deletions
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3
arch/arm/src/samdl/chip/saml_mclk.h
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@ -119,7 +119,7 @@
#define MCLK_APBAMASK_PM (1 << 0) /* Bit 0: PM APBA clock enable */ #define MCLK_APBAMASK_PM (1 << 0) /* Bit 0: PM APBA clock enable */
#define MCLK_APBAMASK_MCLK (1 << 1) /* Bit 1: MCLK APBA clock enable */ #define MCLK_APBAMASK_MCLK (1 << 1) /* Bit 1: MCLK APBA clock enable */
#define MCLK_APBAMASK_RSTC (1 << 2) /* Bit 2: RSTC APBA clock enable */ #define MCLK_APBAMASK_RSTC (1 << 2) /* Bit 2: RSTC APBA clock enable */
#define MCLK_APBAMASK_OCCTRL (1 << 3) /* Bit 3: OSCCTRL APBA clock enable */ #define MCLK_APBAMASK_OSCCTRL (1 << 3) /* Bit 3: OSCCTRL APBA clock enable */
#define MCLK_APBAMASK_OSC32KCTRL (1 << 4) /* Bit 4: OSC32KCTRL APBA clock enable */ #define MCLK_APBAMASK_OSC32KCTRL (1 << 4) /* Bit 4: OSC32KCTRL APBA clock enable */
#define MCLK_APBAMASK_SUPC (1 << 5) /* Bit 5: SUPC APBA clock enable */ #define MCLK_APBAMASK_SUPC (1 << 5) /* Bit 5: SUPC APBA clock enable */
#define MCLK_APBAMASK_GCLK (1 << 6) /* Bit 6: GCLK APBA clock enable */ #define MCLK_APBAMASK_GCLK (1 << 6) /* Bit 6: GCLK APBA clock enable */
@ -136,6 +136,7 @@
/* APBC mask */ /* APBC mask */
#define MCLK_APBCMASK_SERCOM(n) (1 << (n)) /* Bit n: SERCOMn APBC clock enable, n=0-4 */
# define MCLK_APBCMASK_SERCOM0 (1 << 0) /* Bit 0: SERCOM0 APBC clock enable */ # define MCLK_APBCMASK_SERCOM0 (1 << 0) /* Bit 0: SERCOM0 APBC clock enable */
# define MCLK_APBCMASK_SERCOM1 (1 << 1) /* Bit 1: SERCOM1 APBC clock enable */ # define MCLK_APBCMASK_SERCOM1 (1 << 1) /* Bit 1: SERCOM1 APBC clock enable */
# define MCLK_APBCMASK_SERCOM2 (1 << 2) /* Bit 2: SERCOM2 APBC clock enable */ # define MCLK_APBCMASK_SERCOM2 (1 << 2) /* Bit 2: SERCOM2 APBC clock enable */

148
arch/arm/src/samdl/chip/saml_osc32kctrl.h
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@ -37,8 +37,8 @@
* *
********************************************************************************************/ ********************************************************************************************/
#ifndef __ARCH_ARM_SRC_SAMDL_CHIP_SAML_OS32KCCTRL_H #ifndef __ARCH_ARM_SRC_SAMDL_CHIP_SAML_OSC32KCTRL_H
#define __ARCH_ARM_SRC_SAMDL_CHIP_SAML_OS32KCCTRL_H #define __ARCH_ARM_SRC_SAMDL_CHIP_SAML_OSC32KCTRL_H
/******************************************************************************************** /********************************************************************************************
* Included Files * Included Files
@ -53,100 +53,100 @@
/******************************************************************************************** /********************************************************************************************
* Pre-processor Definitions * Pre-processor Definitions
********************************************************************************************/ ********************************************************************************************/
/* OS32KCCTRL register offsets **************************************************************/ /* OSC32KCTRL register offsets **************************************************************/
#define SAM_OS32KCCTRL_INTENCLR_OFFSET 0x0000 /* Interrupt enable clear */ #define SAM_OSC32KCTRL_INTENCLR_OFFSET 0x0000 /* Interrupt enable clear */
#define SAM_OS32KCCTRL_INTENSET_OFFSET 0x0004 /* Interrupt enable set */ #define SAM_OSC32KCTRL_INTENSET_OFFSET 0x0004 /* Interrupt enable set */
#define SAM_OS32KCCTRL_INTFLAG_OFFSET 0x0008 /* Interrupt flag status and clear */ #define SAM_OSC32KCTRL_INTFLAG_OFFSET 0x0008 /* Interrupt flag status and clear */
#define SAM_OS32KCCTRL_STATUS_OFFSET 0x000c /* Status */ #define SAM_OSC32KCTRL_STATUS_OFFSET 0x000c /* Status */
#define SAM_OS32KCCTRL_RTCCTRL_OFFSET 0x0010 /* RTC clock selection */ #define SAM_OSC32KCTRL_RTCCTRL_OFFSET 0x0010 /* RTC clock selection */
#define SAM_OS32KCCTRL_XOSC32K_OFFSET 0x0014 /* 32kHz external crystal oscillator control */ #define SAM_OSC32KCTRL_XOSC32K_OFFSET 0x0014 /* 32kHz external crystal oscillator control */
#define SAM_OS32KCCTRL_OSC32K_OFFSET 0x0018 /* 32kHz internal oscillator control */ #define SAM_OSC32KCTRL_OSC32K_OFFSET 0x0018 /* 32kHz internal oscillator control */
#define SAM_OS32KCCTRL_OSCULP32K_OFFSET 0x001c /* 32kHz ultra low power internal oscillator control */ #define SAM_OSC32KCTRL_OSCULP32K_OFFSET 0x001c /* 32kHz ultra low power internal oscillator control */
/* OS32KCCTRL register addresses ************************************************************/ /* OSC32KCTRL register addresses ************************************************************/
#define SAM_OS32KCCTRL_INTENCLR (SAM_OS32KCCTRL_BASE+SAM_OS32KCCTRL_INTENCLR_OFFSET) #define SAM_OSC32KCTRL_INTENCLR (SAM_OSC32KCTRL_BASE+SAM_OSC32KCTRL_INTENCLR_OFFSET)
#define SAM_OS32KCCTRL_INTENSET (SAM_OS32KCCTRL_BASE+SAM_OS32KCCTRL_INTENSET_OFFSET) #define SAM_OSC32KCTRL_INTENSET (SAM_OSC32KCTRL_BASE+SAM_OSC32KCTRL_INTENSET_OFFSET)
#define SAM_OS32KCCTRL_INTFLAG (SAM_OS32KCCTRL_BASE+SAM_OS32KCCTRL_INTFLAG_OFFSET) #define SAM_OSC32KCTRL_INTFLAG (SAM_OSC32KCTRL_BASE+SAM_OSC32KCTRL_INTFLAG_OFFSET)
#define SAM_OS32KCCTRL_STATUS (SAM_OS32KCCTRL_BASE+SAM_OS32KCCTRL_STATUS_OFFSET) #define SAM_OSC32KCTRL_STATUS (SAM_OSC32KCTRL_BASE+SAM_OSC32KCTRL_STATUS_OFFSET)
#define SAM_OS32KCCTRL_RTCCTRL (SAM_OS32KCCTRL_BASE+SAM_OS32KCCTRL_RTCCTRL_OFFSET) #define SAM_OSC32KCTRL_RTCCTRL (SAM_OSC32KCTRL_BASE+SAM_OSC32KCTRL_RTCCTRL_OFFSET)
#define SAM_OS32KCCTRL_XOSC32K (SAM_OS32KCCTRL_BASE+SAM_OS32KCCTRL_XOSC32K_OFFSET) #define SAM_OSC32KCTRL_XOSC32K (SAM_OSC32KCTRL_BASE+SAM_OSC32KCTRL_XOSC32K_OFFSET)
#define SAM_OS32KCCTRL_OSC32K (SAM_OS32KCCTRL_BASE+SAM_OS32KCCTRL_OSC32K_OFFSET) #define SAM_OSC32KCTRL_OSC32K (SAM_OSC32KCTRL_BASE+SAM_OSC32KCTRL_OSC32K_OFFSET)
#define SAM_OS32KCCTRL_OSCULP32K (SAM_OS32KCCTRL_BASE+SAM_OS32KCCTRL_OSCULP32K_OFFSET) #define SAM_OSC32KCTRL_OSCULP32K (SAM_OSC32KCTRL_BASE+SAM_OSC32KCTRL_OSCULP32K_OFFSET)
/* OS32KCCTRL register bit definitions ******************************************************/ /* OSC32KCTRL register bit definitions ******************************************************/
/* Interrupt enable clear, Interrupt enable set, Interrupt flag status and clear, and /* Interrupt enable clear, Interrupt enable set, Interrupt flag status and clear, and
* status registers. * status registers.
*/ */
#define OS32KCCTRL_INT_XOSC32KRDY (1 << 0) /* Bit 0: XOSC32K ready interrupt */ #define OSC32KCTRL_INT_XOSC32KRDY (1 << 0) /* Bit 0: XOSC32K ready interrupt */
#define OS32KCCTRL_INT_OSC32KRDY (1 << 1) /* Bit 1: OSC32K ready interrupt */ #define OSC32KCTRL_INT_OSC32KRDY (1 << 1) /* Bit 1: OSC32K ready interrupt */
#define OS32KCCTRL_INT_ALL (0x00000003) #define OSC32KCTRL_INT_ALL (0x00000003)
/* RTC clock selection */ /* RTC clock selection */
#define OS32KCCTRL_RTCCTRL_RTCSEL_SHIFT (0) /* Bits 0-2: RTC clock source selection */ #define OSC32KCTRL_RTCCTRL_RTCSEL_SHIFT (0) /* Bits 0-2: RTC clock source selection */
#define OS32KCCTRL_RTCCTRL_RTCSEL_MASK (7 << OS32KCCTRL_RTCCTRL_RTCSEL_SHIFT) #define OSC32KCTRL_RTCCTRL_RTCSEL_MASK (7 << OSC32KCTRL_RTCCTRL_RTCSEL_SHIFT)
# define OS32KCCTRL_RTCCTRL_RTCSEL_ULP1K (0 << OS32KCCTRL_RTCCTRL_RTCSEL_SHIFT) /* 1.024KHz from 32HKz internal ULP oscillator */ # define OSC32KCTRL_RTCCTRL_RTCSEL_ULP1K (0 << OSC32KCTRL_RTCCTRL_RTCSEL_SHIFT) /* 1.024KHz from 32HKz internal ULP oscillator */
# define OS32KCCTRL_RTCCTRL_RTCSEL_ULP32K (1 << OS32KCCTRL_RTCCTRL_RTCSEL_SHIFT) /* 32.768KHz from 32KHz internal ULP oscillator */ # define OSC32KCTRL_RTCCTRL_RTCSEL_ULP32K (1 << OSC32KCTRL_RTCCTRL_RTCSEL_SHIFT) /* 32.768KHz from 32KHz internal ULP oscillator */
# define OS32KCCTRL_RTCCTRL_RTCSEL_OSC1K (2 << OS32KCCTRL_RTCCTRL_RTCSEL_SHIFT) /* 1.024KHz for 32KHz internal oscillator */ # define OSC32KCTRL_RTCCTRL_RTCSEL_OSC1K (2 << OSC32KCTRL_RTCCTRL_RTCSEL_SHIFT) /* 1.024KHz for 32KHz internal oscillator */
# define OS32KCCTRL_RTCCTRL_RTCSEL_XOSC1K (3 << OS32KCCTRL_RTCCTRL_RTCSEL_SHIFT) /* 1.024KHz for 32KHz external oscillator */ # define OSC32KCTRL_RTCCTRL_RTCSEL_XOSC1K (3 << OSC32KCTRL_RTCCTRL_RTCSEL_SHIFT) /* 1.024KHz for 32KHz external oscillator */
# define OS32KCCTRL_RTCCTRL_RTCSEL_OSC32K (4 << OS32KCCTRL_RTCCTRL_RTCSEL_SHIFT) /* 32.768KHz from 32KHz external oscillator */ # define OSC32KCTRL_RTCCTRL_RTCSEL_OSC32K (4 << OSC32KCTRL_RTCCTRL_RTCSEL_SHIFT) /* 32.768KHz from 32KHz external oscillator */
# define OS32KCCTRL_RTCCTRL_RTCSEL_XOSC312K (5 << OS32KCCTRL_RTCCTRL_RTCSEL_SHIFT) /* 32.768KHz from 32KHz external crystal oscillator */ # define OSC32KCTRL_RTCCTRL_RTCSEL_XOSC312K (5 << OSC32KCTRL_RTCCTRL_RTCSEL_SHIFT) /* 32.768KHz from 32KHz external crystal oscillator */
/* 32kHz external crystal oscillator control register */ /* 32kHz external crystal oscillator control register */
#define OS32KCCTRL_XOSC32K_ENABLE (1 << 1) /* Bit 1: Oscillator enable */ #define OSC32KCTRL_XOSC32K_ENABLE (1 << 1) /* Bit 1: Oscillator enable */
#define OS32KCCTRL_XOSC32K_XTALEN (1 << 2) /* Bit 2: Crystal oscillator enable */ #define OSC32KCTRL_XOSC32K_XTALEN (1 << 2) /* Bit 2: Crystal oscillator enable */
#define OS32KCCTRL_XOSC32K_EN32K (1 << 3) /* Bit 3: 32kHz Output enable */ #define OSC32KCTRL_XOSC32K_EN32K (1 << 3) /* Bit 3: 32kHz Output enable */
#define OS32KCCTRL_XOSC32K_EN1K (1 << 4) /* Bit 4: 1kHz Output enable */ #define OSC32KCTRL_XOSC32K_EN1K (1 << 4) /* Bit 4: 1kHz Output enable */
#define OS32KCCTRL_XOSC32K_RUNSTDBY (1 << 6) /* Bit 6: Run in standby */ #define OSC32KCTRL_XOSC32K_RUNSTDBY (1 << 6) /* Bit 6: Run in standby */
#define OS32KCCTRL_XOSC32K_ONDEMAND (1 << 7) /* Bit 7: On demand control */ #define OSC32KCTRL_XOSC32K_ONDEMAND (1 << 7) /* Bit 7: On demand control */
#define OS32KCCTRL_XOSC32K_STARTUP_SHIFT (8) /* Bits 8-10: Oscillator start-up time */ #define OSC32KCTRL_XOSC32K_STARTUP_SHIFT (8) /* Bits 8-10: Oscillator start-up time */
#define OS32KCCTRL_XOSC32K_STARTUP_MASK (7 << OS32KCCTRL_XOSC32K_STARTUP_SHIFT) #define OSC32KCTRL_XOSC32K_STARTUP_MASK (7 << OSC32KCTRL_XOSC32K_STARTUP_SHIFT)
# define OS32KCCTRL_XOSC32K_STARTUP(n) ((n) << OS32KCCTRL_XOSC32K_STARTUP_SHIFT) # define OSC32KCTRL_XOSC32K_STARTUP(n) ((n) << OSC32KCTRL_XOSC32K_STARTUP_SHIFT)
# define OS32KCCTRL_XOSC32K_STARTUP_63MS (0 << OS32KCCTRL_XOSC32K_STARTUP_SHIFT) /* 62.592 msec */ # define OSC32KCTRL_XOSC32K_STARTUP_63MS (0 << OSC32KCTRL_XOSC32K_STARTUP_SHIFT) /* 62.592 msec */
# define OS32KCCTRL_XOSC32K_STARTUP_125MS (1 << OS32KCCTRL_XOSC32K_STARTUP_SHIFT) /* 125.092 msec */ # define OSC32KCTRL_XOSC32K_STARTUP_125MS (1 << OSC32KCTRL_XOSC32K_STARTUP_SHIFT) /* 125.092 msec */
# define OS32KCCTRL_XOSC32K_STARTUP_500MS (2 << OS32KCCTRL_XOSC32K_STARTUP_SHIFT) /* 500.092 msec */ # define OSC32KCTRL_XOSC32K_STARTUP_500MS (2 << OSC32KCTRL_XOSC32K_STARTUP_SHIFT) /* 500.092 msec */
# define OS32KCCTRL_XOSC32K_STARTUP_100MS (3 << OS32KCCTRL_XOSC32K_STARTUP_SHIFT) /* 100.0092 msec */ # define OSC32KCTRL_XOSC32K_STARTUP_100MS (3 << OSC32KCTRL_XOSC32K_STARTUP_SHIFT) /* 100.0092 msec */
# define OS32KCCTRL_XOSC32K_STARTUP_200MS (4 << OS32KCCTRL_XOSC32K_STARTUP_SHIFT) /* 200.0092 msec */ # define OSC32KCTRL_XOSC32K_STARTUP_200MS (4 << OSC32KCTRL_XOSC32K_STARTUP_SHIFT) /* 200.0092 msec */
# define OS32KCCTRL_XOSC32K_STARTUP_400MS (5 << OS32KCCTRL_XOSC32K_STARTUP_SHIFT) /* 400.092 msec */ # define OSC32KCTRL_XOSC32K_STARTUP_400MS (5 << OSC32KCTRL_XOSC32K_STARTUP_SHIFT) /* 400.092 msec */
# define OS32KCCTRL_XOSC32K_STARTUP_800MS (6 << OS32KCCTRL_XOSC32K_STARTUP_SHIFT) /* 800.0092 msec */ # define OSC32KCTRL_XOSC32K_STARTUP_800MS (6 << OSC32KCTRL_XOSC32K_STARTUP_SHIFT) /* 800.0092 msec */
#define OS32KCCTRL_XOSC32K_WRTLOCK (1 << 12) /* Bit 12: Write lock */ #define OSC32KCTRL_XOSC32K_WRTLOCK (1 << 12) /* Bit 12: Write lock */
/* 32kHz internal oscillator control register */ /* 32kHz internal oscillator control register */
#define OS32KCCTRL_OSC32K_ENABLE (1 << 1) /* Bit 1: Oscillator enable */ #define OSC32KCTRL_OSC32K_ENABLE (1 << 1) /* Bit 1: Oscillator enable */
#define OS32KCCTRL_OSC32K_EN32K (1 << 2) /* Bit 2: 32kHz Output enable */ #define OSC32KCTRL_OSC32K_EN32K (1 << 2) /* Bit 2: 32kHz Output enable */
#define OS32KCCTRL_OSC32K_EN1K (1 << 3) /* Bit 3: 1kHz Output enable */ #define OSC32KCTRL_OSC32K_EN1K (1 << 3) /* Bit 3: 1kHz Output enable */
#define OS32KCCTRL_OSC32K_RUNSTDBY (1 << 6) /* Bit 6: Run in standby */ #define OSC32KCTRL_OSC32K_RUNSTDBY (1 << 6) /* Bit 6: Run in standby */
#define OS32KCCTRL_OSC32K_ONDEMAND (1 << 7) /* Bit 7: On demand control */ #define OSC32KCTRL_OSC32K_ONDEMAND (1 << 7) /* Bit 7: On demand control */
#define OS32KCCTRL_OSC32K_STARTUP_SHIFT (8) /* Bits 8-10: Oscillator start-up time */ #define OSC32KCTRL_OSC32K_STARTUP_SHIFT (8) /* Bits 8-10: Oscillator start-up time */
#define OS32KCCTRL_OSC32K_STARTUP_MASK (7 << OS32KCCTRL_OSC32K_STARTUP_SHIFT) #define OSC32KCTRL_OSC32K_STARTUP_MASK (7 << OSC32KCTRL_OSC32K_STARTUP_SHIFT)
# define OS32KCCTRL_OSC32K_STARTUP(n) ((n) << OS32KCCTRL_OSC32K_STARTUP_SHIFT) # define OSC32KCTRL_OSC32K_STARTUP(n) ((n) << OSC32KCTRL_OSC32K_STARTUP_SHIFT)
# define OS32KCCTRL_OSC32K_STARTUP_92US (0 << OS32KCCTRL_OSC32K_STARTUP_SHIFT) /* 92µs */ # define OSC32KCTRL_OSC32K_STARTUP_92US (0 << OSC32KCTRL_OSC32K_STARTUP_SHIFT) /* 92µs */
# define OS32KCCTRL_OSC32K_STARTUP_122US (1 << OS32KCCTRL_OSC32K_STARTUP_SHIFT) /* 122µs */ # define OSC32KCTRL_OSC32K_STARTUP_122US (1 << OSC32KCTRL_OSC32K_STARTUP_SHIFT) /* 122µs */
# define OS32KCCTRL_OSC32K_STARTUP_183US (2 << OS32KCCTRL_OSC32K_STARTUP_SHIFT) /* 183µs */ # define OSC32KCTRL_OSC32K_STARTUP_183US (2 << OSC32KCTRL_OSC32K_STARTUP_SHIFT) /* 183µs */
# define OS32KCCTRL_OSC32K_STARTUP_305US (3 << OS32KCCTRL_OSC32K_STARTUP_SHIFT) /* 305µs */ # define OSC32KCTRL_OSC32K_STARTUP_305US (3 << OSC32KCTRL_OSC32K_STARTUP_SHIFT) /* 305µs */
# define OS32KCCTRL_OSC32K_STARTUP_549US (4 << OS32KCCTRL_OSC32K_STARTUP_SHIFT) /* 549µs */ # define OSC32KCTRL_OSC32K_STARTUP_549US (4 << OSC32KCTRL_OSC32K_STARTUP_SHIFT) /* 549µs */
# define OS32KCCTRL_OSC32K_STARTUP_1MS (5 << OS32KCCTRL_OSC32K_STARTUP_SHIFT) /* 1038µs */ # define OSC32KCTRL_OSC32K_STARTUP_1MS (5 << OSC32KCTRL_OSC32K_STARTUP_SHIFT) /* 1038µs */
# define OS32KCCTRL_OSC32K_STARTUP_2MS (6 << OS32KCCTRL_OSC32K_STARTUP_SHIFT) /* 2014µs */ # define OSC32KCTRL_OSC32K_STARTUP_2MS (6 << OSC32KCTRL_OSC32K_STARTUP_SHIFT) /* 2014µs */
# define OS32KCCTRL_OSC32K_STARTUP_4MS (7 << OS32KCCTRL_OSC32K_STARTUP_SHIFT) /* 3967µs */ # define OSC32KCTRL_OSC32K_STARTUP_4MS (7 << OSC32KCTRL_OSC32K_STARTUP_SHIFT) /* 3967µs */
#define OS32KCCTRL_OSC32K_WRTLOCK (1 << 12) /* Bit 12: Write lock */ #define OSC32KCTRL_OSC32K_WRTLOCK (1 << 12) /* Bit 12: Write lock */
#define OS32KCCTRL_OSC32K_CALIB_SHIFT (16) /* Bits 16-22: Oscillator calibration */ #define OSC32KCTRL_OSC32K_CALIB_SHIFT (16) /* Bits 16-22: Oscillator calibration */
#define OS32KCCTRL_OSC32K_CALIB_MASK (0x7f << OS32KCCTRL_OSC32K_CALIB_SHIFT) #define OSC32KCTRL_OSC32K_CALIB_MASK (0x7f << OSC32KCTRL_OSC32K_CALIB_SHIFT)
# define OS32KCCTRL_OSC32K_CALIB(n) ((n) << OS32KCCTRL_OSC32K_CALIB_SHIFT) # define OSC32KCTRL_OSC32K_CALIB(n) ((n) << OSC32KCTRL_OSC32K_CALIB_SHIFT)
/* 32kHz ultra low power internal oscillator control register */ /* 32kHz ultra low power internal oscillator control register */
#define OS32KCCTRL_OSCULP32K_CALIB_SHIFT (8) /* Bits 0-12: Oscillator Calibration */ #define OSC32KCTRL_OSCULP32K_CALIB_SHIFT (8) /* Bits 0-12: Oscillator Calibration */
#define OS32KCCTRL_OSCULP32K_CALIB_MASK (31 << OS32KCCTRL_OSCULP32K_CALIB_SHIFT) #define OSC32KCTRL_OSCULP32K_CALIB_MASK (31 << OSC32KCTRL_OSCULP32K_CALIB_SHIFT)
# define OS32KCCTRL_OSCULP32K_CALIB(n) ((n) << OS32KCCTRL_OSCULP32K_CALIB_SHIFT) # define OSC32KCTRL_OSCULP32K_CALIB(n) ((n) << OSC32KCTRL_OSCULP32K_CALIB_SHIFT)
#define OS32KCCTRL_OSCULP32K_WRTLOCK (1 << 7) /* Bit 7: Write Lock */ #define OSC32KCTRL_OSCULP32K_WRTLOCK (1 << 7) /* Bit 7: Write Lock */
/******************************************************************************************** /********************************************************************************************
* Public Types * Public Types
@ -161,4 +161,4 @@
********************************************************************************************/ ********************************************************************************************/
#endif /* CONFIG_ARCH_FAMILY_SAML21 */ #endif /* CONFIG_ARCH_FAMILY_SAML21 */
#endif /* __ARCH_ARM_SRC_SAMDL_CHIP_SAML_OS32KCCTRL_H */ #endif /* __ARCH_ARM_SRC_SAMDL_CHIP_SAML_OSC32KCTRL_H */

4
arch/arm/src/samdl/chip/saml_supc.h
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@ -100,7 +100,7 @@
#define SUPC_INT_APWSRDY (1 << 9) /* Bit 9: Automatic power switch ready interrupt */ #define SUPC_INT_APWSRDY (1 << 9) /* Bit 9: Automatic power switch ready interrupt */
#define SUPC_INT_VCORERDY (1 << 10) /* Bit 10: VDDCORE voltage ready interrupt */ #define SUPC_INT_VCORERDY (1 << 10) /* Bit 10: VDDCORE voltage ready interrupt */
#define SUPC_INT_ALL (0x00007fff) #define SUPC_INT_ALL (0x0000073f)
/* 3.3V brown-out detector control register */ /* 3.3V brown-out detector control register */
@ -187,7 +187,7 @@
#define SUPC_VREG_RUNDSTDBY (1 << 6) /* Bit 6: Run in standby */ #define SUPC_VREG_RUNDSTDBY (1 << 6) /* Bit 6: Run in standby */
#define SUPC_VREG_LPEFF (1 << 8) /* Bit 8: Low power mode efficiency */ #define SUPC_VREG_LPEFF (1 << 8) /* Bit 8: Low power mode efficiency */
#define SUPC_VREG_VSVSTEP_SHIFT (16) /* Bits 16-19: Voltage scaling step */ #define SUPC_VREG_VSVSTEP_SHIFT (16) /* Bits 16-19: Voltage scaling step */
#define SUPC_VREG_VSVSTEP_SHIFT (15 << SUPC_VREG_VSVSTEP_SHIFT) #define SUPC_VREG_VSVSTEP_MASK (15 << SUPC_VREG_VSVSTEP_SHIFT)
# define SUPC_VREG_VSVSTEP(n) ((uint32_t)(n) << SUPC_VREG_VSVSTEP_SHIFT) # define SUPC_VREG_VSVSTEP(n) ((uint32_t)(n) << SUPC_VREG_VSVSTEP_SHIFT)
#define SUPC_VREG_VSPER_SHIFT (24) /* Bits 24-31: Voltage scaling period */ #define SUPC_VREG_VSPER_SHIFT (24) /* Bits 24-31: Voltage scaling period */
#define SUPC_VREG_VSPER_MASK (0xff << SUPC_VREG_VSPER_SHIFT) #define SUPC_VREG_VSPER_MASK (0xff << SUPC_VREG_VSPER_SHIFT)

2
arch/arm/src/samdl/chip/saml_usart.h
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@ -64,9 +64,7 @@
#define SAM_USART_INTENSET_OFFSET 0x0016 /* Interrupt enable set register */ #define SAM_USART_INTENSET_OFFSET 0x0016 /* Interrupt enable set register */
#define SAM_USART_INTFLAG_OFFSET 0x0018 /* Interrupt flag and status clear register */ #define SAM_USART_INTFLAG_OFFSET 0x0018 /* Interrupt flag and status clear register */
#define SAM_USART_STATUS_OFFSET 0x001a /* Status register */ #define SAM_USART_STATUS_OFFSET 0x001a /* Status register */
#define SAM_USART_SYNCBUSY_OFFSET 0x001c /* Synchronization busy register */ #define SAM_USART_SYNCBUSY_OFFSET 0x001c /* Synchronization busy register */
#define SAM_USART_DATA_OFFSET 0x0018 /* Data register */ #define SAM_USART_DATA_OFFSET 0x0018 /* Data register */
#define SAM_USART_DBGCTRL_OFFSET 0x0030 /* Debug control register */ #define SAM_USART_DBGCTRL_OFFSET 0x0030 /* Debug control register */

16
arch/arm/src/samdl/sam_lowputc.c
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@ -80,22 +80,6 @@
* Private Functions * Private Functions
****************************************************************************/ ****************************************************************************/
/****************************************************************************
* Name: sam_wait_synchronization
*
* Description:
* Wait until the SERCOM USART reports that it is synchronized.
*
****************************************************************************/
#ifdef SAMDL_HAVE_USART
static void
sam_wait_synchronization(const struct sam_usart_config_s * const config)
{
while ((getreg16(config->base + SAM_USART_STATUS_OFFSET) & USART_STATUS_SYNCBUSY) != 0);
}
#endif
/**************************************************************************** /****************************************************************************
* Name: sam_usart_configure * Name: sam_usart_configure
* *

89
arch/arm/src/samdl/sam_periphclks.h Normal file
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@ -0,0 +1,89 @@
/****************************************************************************
* arch/arm/src/samdl/sam_periphclks.h
*
* Copyright (C) 2015 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
****************************************************************************/
#ifndef __ARCH_ARM_SRC_SAMDL_SAM_PERIPHCLKS_H
#define __ARCH_ARM_SRC_SAMDL_SAM_PERIPHCLKS_H
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include "sam_config.h"
#if defined(CONFIG_ARCH_FAMILY_SAMD20)
# include "samd_periphclks.h"
#elif defined(CONFIG_ARCH_FAMILY_SAML21)
# include "saml_periphclks.h"
#endif
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/****************************************************************************
* Public Types
****************************************************************************/
/****************************************************************************
* Inline Functions
****************************************************************************/
#ifndef __ASSEMBLY__
/****************************************************************************
* Public Data
****************************************************************************/
#undef EXTERN
#if defined(__cplusplus)
#define EXTERN extern "C"
extern "C"
{
#else
#define EXTERN extern
#endif
/****************************************************************************
* Public Function Prototypes
****************************************************************************/
#undef EXTERN
#if defined(__cplusplus)
}
#endif
#endif /* __ASSEMBLY__ */
#endif /* __ARCH_ARM_SRC_SAMDL_SAM_PERIPHCLKS_H */

2
arch/arm/src/samdl/sam_sercom.c
View File

@ -1,5 +1,5 @@
/**************************************************************************** /****************************************************************************
* arch/arm/src/samdl/sam_lowputc.c * arch/arm/src/samdl/sam_sercom.c
* *
* Copyright (C) 2014-2015 Gregory Nutt. All rights reserved. * Copyright (C) 2014-2015 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org> * Author: Gregory Nutt <gnutt@nuttx.org>

24
arch/arm/src/samdl/sam_sercom.h
View File

@ -46,7 +46,7 @@
#include "up_arch.h" #include "up_arch.h"
#include "sam_config.h" #include "sam_config.h"
#include "sam_pm.h" #include "sam_periphclks.h"
#if defined(CONFIG_ARCH_FAMILY_SAMD20) #if defined(CONFIG_ARCH_FAMILY_SAMD20)
# include "chip/samd_sercom.h" # include "chip/samd_sercom.h"
@ -87,23 +87,27 @@ extern "C"
* Name: sercom_enable * Name: sercom_enable
* *
* Description: * Description:
* Enable clocking to a SERCOM module in PM * Enable clocking to a SERCOM module
* *
* Assumptions/Limitation: * Assumptions/Limitation:
* This operation is global and non-atomic. The caller should disable * This operation is global and atomic. Interrupts will be masked.
* interrupts prior to calling this function.
* *
****************************************************************************/ ****************************************************************************/
static inline void sercom_enable(int sercom) static inline void sercom_enable(int sercom)
{ {
uint32_t regval; #ifdef SAMDL_HAVE_SERCOM5
/* SERCOM5 is a special case */
/* Enable clocking to the SERCOM module in PM */ if (sercom == 5)
{
regval = getreg32(SAM_PM_APBCMASK); sam_sercom5_enableperiph();
regval |= PM_APBCMASK_SERCOM(sercom); }
putreg32(regval, SAM_PM_APBCMASK); else
#endif
{
sam_sercom_enableperiph(sercom);
}
} }
/**************************************************************************** /****************************************************************************

25
arch/arm/src/samdl/sam_usart.h
View File

@ -100,6 +100,31 @@ struct sam_usart_config_s
uintptr_t base; /* SERCOM base address */ uintptr_t base; /* SERCOM base address */
}; };
/************************************************************************************
* Inline Functions
************************************************************************************/
/************************************************************************************
* Name: sam_wait_synchronization
*
* Description:
* Wait until the SERCOM USART reports that it is synchronized.
*
***********************************************************************************/
#ifdef SAMDL_HAVE_USART
static inline void
sam_wait_synchronization(const struct sam_usart_config_s * const config)
{
#if defined(CONFIG_ARCH_FAMILY_SAMD20)
while ((getreg16(config->base + SAM_USART_STATUS_OFFSET) & USART_STATUS_SYNCBUSY) != 0);
#elif defined(CONFIG_ARCH_FAMILY_SAML21)
# warning Need SAML21 synchronization logic
#else
# error Unrecognized SAMD/L family
#endif
}
#endif
/************************************************************************************ /************************************************************************************
* Public Data * Public Data
************************************************************************************/ ************************************************************************************/

9
arch/arm/src/samdl/samd_clockconfig.c
View File

@ -62,8 +62,11 @@
#include <arch/board/board.h> #include <arch/board/board.h>
#include "samd_periphclks.h"
#include "sam_clockconfig.h" #include "sam_clockconfig.h"
#ifdef CONFIG_ARCH_FAMILY_SAMD20
/**************************************************************************** /****************************************************************************
* Pre-processor Definitions * Pre-processor Definitions
****************************************************************************/ ****************************************************************************/
@ -886,9 +889,7 @@ static inline void sam_config_gclks(void)
/* Turn on the GCLK interface clock */ /* Turn on the GCLK interface clock */
regval = getreg32(SAM_PM_APBAMASK); sam_gclk_enableperiph();
regval |= PM_APBAMASK_GCLK;
putreg32(regval, SAM_PM_APBAMASK);
/* Reset the GCLK module */ /* Reset the GCLK module */
@ -1025,3 +1026,5 @@ void sam_clockconfig(void)
sam_dividers(); sam_dividers();
} }
#endif /* CONFIG_ARCH_FAMILY_SAMD20 */

209
arch/arm/src/samdl/samd_periphclks.h Normal file
View File

@ -0,0 +1,209 @@
/****************************************************************************
* arch/arm/src/samdl/samd_periphclks.h
*
* Copyright (C) 2015 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
****************************************************************************/
#ifndef __ARCH_ARM_SRC_SAMDL_SAMD_PERIPHCLKS_H
#define __ARCH_ARM_SRC_SAMDL_SAMD_PERIPHCLKS_H
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include "chip/samd_pm.h"
#ifdef CONFIG_ARCH_FAMILY_SAMD20
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
#define sam_apba_enableperiph(s) modifyreg32(SAM_PM_APBAMASK,0,s)
#define sam_pac0_enableperiph() sam_apba_enableperiph(PM_APBAMASK_PAC0)
#define sam_pm_enableperiph() sam_apba_enableperiph(PM_APBAMASK_PM)
#define sam_sysctrl_enableperiph() sam_apba_enableperiph(PM_APBAMASK_SYSCTRL)
#define sam_gclk_enableperiph() sam_apba_enableperiph(PM_APBAMASK_GCLK)
#define sam_wdt_enableperiph() sam_apba_enableperiph(PM_APBAMASK_WDT)
#define sam_rtc_enableperiph() sam_apba_enableperiph(PM_APBAMASK_RTC)
#define sam_eic_enableperiph() sam_apba_enableperiph(PM_APBAMASK_EIC)
#define sam_apbb_enableperiph(s) modifyreg32(SAM_PM_APBBMASK,0,s)
#define sam_pac1_enableperiph() sam_apbb_enableperiph(PM_APBBMASK_PAC1)
#define sam_dsu_enableperiph() sam_apbb_enableperiph(PM_APBBMASK_DSU)
#define sam_nvmctrl_enableperiph() sam_apbb_enableperiph(PM_APBBMASK_NVMCTRL)
#define sam_port_enableperiph() sam_apbb_enableperiph(PM_APBBMASK_PORT)
#define sam_apbc_enableperiph(s) modifyreg32(SAM_PM_APBCMASK,0,s)
#define sam_pac2_enableperiph() sam_apbc_enableperiph(PM_APBCMASK_PAC2)
#define sam_devsys_enableperiph() sam_apbc_enableperiph(PM_APBCMASK_EVSYS)
#define sam_sercom_enableperiph(n) sam_apbc_enableperiph(PM_APBCMASK_SERCOM(n))
#define sam_sercom0_enableperiph() sam_apbc_enableperiph(PM_APBCMASK_SERCOM0)
#define sam_sercom1_enableperiph() sam_apbc_enableperiph(PM_APBCMASK_SERCOM1)
#define sam_sercom2_enableperiph() sam_apbc_enableperiph(PM_APBCMASK_SERCOM2)
#define sam_sercom3_enableperiph() sam_apbc_enableperiph(PM_APBCMASK_SERCOM3)
#define sam_sercom4_enableperiph() sam_apbc_enableperiph(PM_APBCMASK_SERCOM4)
#define sam_sercom5_enableperiph() sam_apbc_enableperiph(PM_APBCMASK_SERCOM5)
#define sam_tc0_enableperiph() sam_apbc_enableperiph(PM_APBCMASK_TC0)
#define sam_tc1_enableperiph() sam_apbc_enableperiph(PM_APBCMASK_TC1)
#define sam_tc2_enableperiph() sam_apbc_enableperiph(PM_APBCMASK_TC2)
#define sam_tc3_enableperiph() sam_apbc_enableperiph(PM_APBCMASK_TC3)
#define sam_tc4_enableperiph() sam_apbc_enableperiph(PM_APBCMASK_TC4)
#define sam_tc5_enableperiph() sam_apbc_enableperiph(PM_APBCMASK_TC5)
#define sam_tc6_enableperiph() sam_apbc_enableperiph(PM_APBCMASK_TC6)
#define sam_tc7_enableperiph() sam_apbc_enableperiph(PM_APBCMASK_TC7)
#define sam_adc_enableperiph() sam_apbc_enableperiph(PM_APBCMASK_ADC)
#define sam_ac_enableperiph() sam_apbc_enableperiph(PM_APBCMASK_AC)
#define sam_dac_enableperiph() sam_apbc_enableperiph(PM_APBCMASK_DAC)
#define sam_ptc_enableperiph() sam_apbc_enableperiph(PM_APBCMASK_PTC)
#define sam_apba_disableperiph(s) modifyreg32(SAM_PM_APBAMASK,s,0)
#define sam_pac0_disableperiph() sam_apba_disableperiph(PM_APBAMASK_PAC0)
#define sam_pm_disableperiph() sam_apba_disableperiph(PM_APBAMASK_PM)
#define sam_sysctrl_disableperiph() sam_apba_disableperiph(PM_APBAMASK_SYSCTRL)
#define sam_gclk_disableperiph() sam_apba_disableperiph(PM_APBAMASK_GCLK)
#define sam_wdt_disableperiph() sam_apba_disableperiph(PM_APBAMASK_WDT)
#define sam_rtc_disableperiph() sam_apba_disableperiph(PM_APBAMASK_RTC)
#define sam_eic_disableperiph() sam_apba_disableperiph(PM_APBAMASK_EIC)
#define sam_apbb_disableperiph(s) modifyreg32(SAM_PM_APBBMASK,s,0)
#define sam_pac1_disableperiph() sam_apbb_disableperiph(PM_APBBMASK_PAC1)
#define sam_dsu_disableperiph() sam_apbb_disableperiph(PM_APBBMASK_DSU)
#define sam_nvmctrl_disableperiph() sam_apbb_disableperiph(PM_APBBMASK_NVMCTRL)
#define sam_port_disableperiph() sam_apbb_disableperiph(PM_APBBMASK_PORT)
#define sam_apbc_disableperiph(s) modifyreg32(SAM_PM_APBCMASK,s,0)
#define sam_pac2_disableperiph() sam_apbc_disableperiph(PM_APBCMASK_PAC2)
#define sam_devsys_disableperiph() sam_apbc_disableperiph(PM_APBCMASK_EVSYS)
#define sam_sercom_disableperiph(n) sam_apbc_disableperiph(PM_APBCMASK_SERCOM(n))
#define sam_sercom0_disableperiph() sam_apbc_disableperiph(PM_APBCMASK_SERCOM0)
#define sam_sercom1_disableperiph() sam_apbc_disableperiph(PM_APBCMASK_SERCOM1)
#define sam_sercom2_disableperiph() sam_apbc_disableperiph(PM_APBCMASK_SERCOM2)
#define sam_sercom3_disableperiph() sam_apbc_disableperiph(PM_APBCMASK_SERCOM3)
#define sam_sercom4_disableperiph() sam_apbc_disableperiph(PM_APBCMASK_SERCOM4)
#define sam_sercom5_disableperiph() sam_apbc_disableperiph(PM_APBCMASK_SERCOM5)
#define sam_tc0_disableperiph() sam_apbc_disableperiph(PM_APBCMASK_TC0)
#define sam_tc1_disableperiph() sam_apbc_disableperiph(PM_APBCMASK_TC1)
#define sam_tc2_disableperiph() sam_apbc_disableperiph(PM_APBCMASK_TC2)
#define sam_tc3_disableperiph() sam_apbc_disableperiph(PM_APBCMASK_TC3)
#define sam_tc4_disableperiph() sam_apbc_disableperiph(PM_APBCMASK_TC4)
#define sam_tc5_disableperiph() sam_apbc_disableperiph(PM_APBCMASK_TC5)
#define sam_tc6_disableperiph() sam_apbc_disableperiph(PM_APBCMASK_TC6)
#define sam_tc7_disableperiph() sam_apbc_disableperiph(PM_APBCMASK_TC7)
#define sam_adc_disableperiph() sam_apbc_disableperiph(PM_APBCMASK_ADC)
#define sam_ac_disableperiph() sam_apbc_disableperiph(PM_APBCMASK_AC)
#define sam_dac_disableperiph() sam_apbc_disableperiph(PM_APBCMASK_DAC)
#define sam_ptc_disableperiph() sam_apbc_disableperiph(PM_APBCMASK_PTC)
#define sam_apba_isenabled(s) (getreg32(SAM_PM_APBAMASK) & (s)) != 0)
#define sam_pac0_isenabled() sam_apba_isenabled(PM_APBAMASK_PAC0)
#define sam_pm_isenabled() sam_apba_isenabled(PM_APBAMASK_PM)
#define sam_sysctrl_isenabled() sam_apba_isenabled(PM_APBAMASK_SYSCTRL)
#define sam_gclk_isenabled() sam_apba_isenabled(PM_APBAMASK_GCLK)
#define sam_wdt_isenabled() sam_apba_isenabled(PM_APBAMASK_WDT)
#define sam_rtc_isenabled() sam_apba_isenabled(PM_APBAMASK_RTC)
#define sam_eic_isenabled() sam_apba_isenabled(PM_APBAMASK_EIC)
#define sam_apbb_isenabled(s) (getreg32(SAM_PM_APBBMASK) & (s)) != 0)
#define sam_pac1_isenabled() sam_apbb_isenabled(PM_APBBMASK_PAC1)
#define sam_dsu_isenabled() sam_apbb_isenabled(PM_APBBMASK_DSU)
#define sam_nvmctrl_isenabled() sam_apbb_isenabled(PM_APBBMASK_NVMCTRL)
#define sam_port_isenabled() sam_apbb_isenabled(PM_APBBMASK_PORT)
#define sam_apbc_isenabled(s) (getreg32(SAM_PM_APBCMASK) & (s)) != 0)
#define sam_pac2_isenabled() sam_apbc_isenabled(PM_APBCMASK_PAC2)
#define sam_devsys_isenabled() sam_apbc_isenabled(PM_APBCMASK_EVSYS)
#define sam_sercom_isenabled(n) sam_apbc_isenabled(PM_APBCMASK_SERCOM(n))
#define sam_sercom0_isenabled() sam_apbc_isenabled(PM_APBCMASK_SERCOM0)
#define sam_sercom1_isenabled() sam_apbc_isenabled(PM_APBCMASK_SERCOM1)
#define sam_sercom2_isenabled() sam_apbc_isenabled(PM_APBCMASK_SERCOM2)
#define sam_sercom3_isenabled() sam_apbc_isenabled(PM_APBCMASK_SERCOM3)
#define sam_sercom4_isenabled() sam_apbc_isenabled(PM_APBCMASK_SERCOM4)
#define sam_sercom5_isenabled() sam_apbc_isenabled(PM_APBCMASK_SERCOM5)
#define sam_tc0_isenabled() sam_apbc_isenabled(PM_APBCMASK_TC0)
#define sam_tc1_isenabled() sam_apbc_isenabled(PM_APBCMASK_TC1)
#define sam_tc2_isenabled() sam_apbc_isenabled(PM_APBCMASK_TC2)
#define sam_tc3_isenabled() sam_apbc_isenabled(PM_APBCMASK_TC3)
#define sam_tc4_isenabled() sam_apbc_isenabled(PM_APBCMASK_TC4)
#define sam_tc5_isenabled() sam_apbc_isenabled(PM_APBCMASK_TC5)
#define sam_tc6_isenabled() sam_apbc_isenabled(PM_APBCMASK_TC6)
#define sam_tc7_isenabled() sam_apbc_isenabled(PM_APBCMASK_TC7)
#define sam_adc_isenabled() sam_apbc_isenabled(PM_APBCMASK_ADC)
#define sam_ac_isenabled() sam_apbc_isenabled(PM_APBCMASK_AC)
#define sam_dac_isenabled() sam_apbc_isenabled(PM_APBCMASK_DAC)
#define sam_ptc_isenabled() sam_apbc_isenabled(PM_APBCMASK_PTC)
/****************************************************************************
* Public Types
****************************************************************************/
/****************************************************************************
* Inline Functions
****************************************************************************/
#ifndef __ASSEMBLY__
/****************************************************************************
* Public Data
****************************************************************************/
#undef EXTERN
#if defined(__cplusplus)
#define EXTERN extern "C"
extern "C"
{
#else
#define EXTERN extern
#endif
/****************************************************************************
* Public Function Prototypes
****************************************************************************/
#undef EXTERN
#if defined(__cplusplus)
}
#endif
#endif /* __ASSEMBLY__ */
#endif /* CONFIG_ARCH_FAMILY_SAMD20 */
#endif /* __ARCH_ARM_SRC_SAMDL_SAMD_PERIPHCLKS_H */

291
arch/arm/src/samdl/saml_clockconfig.c
View File

@ -9,6 +9,11 @@
* Datasheet", Atmel-42385C-SAML21_Datasheet_Preliminary-03/20/15 * Datasheet", Atmel-42385C-SAML21_Datasheet_Preliminary-03/20/15
* 2. The SAMD20 samd_clockconfig.c file. See that file for additional * 2. The SAMD20 samd_clockconfig.c file. See that file for additional
* references. * references.
* 3. Atmel sample code for the SAML21. This code has an ASF license
* with is compatible with the NuttX BSD license, but includes the
* provision that this code not be used in non-Atmel products. That
* sample code was used only as a reference so I believe that only the
* NuttX BSD license applies.
* *
* Redistribution and use in source and binary forms, with or without * Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions * modification, are permitted provided that the following conditions
@ -52,14 +57,15 @@
#include "up_arch.h" #include "up_arch.h"
#include "chip/saml_pm.h" #include "chip/saml_pm.h"
#include "chip/saml_supc.h"
#include "chip/saml_oscctrl.h" #include "chip/saml_oscctrl.h"
#include "chip/saml_osc32kctrl.h" #include "chip/saml_osc32kctrl.h"
#include "chip/saml_gclk.h" #include "chip/saml_gclk.h"
#include "chip/saml_nvmctrl.h" #include "chip/saml_nvmctrl.h"
#include "sam_fuses.h"
#include <arch/board/board.h> #include <arch/board/board.h>
#include "saml_periphclks.h"
#include "sam_clockconfig.h" #include "sam_clockconfig.h"
#ifdef CONFIG_ARCH_FAMILY_SAML21 #ifdef CONFIG_ARCH_FAMILY_SAML21
@ -85,6 +91,36 @@ struct sam_gclkconfig_s
}; };
#endif #endif
/****************************************************************************
* Private Function Prototypes
****************************************************************************/
static inline void sam_flash_waitstates(void);
static void sam_performance_level(uint8_t level);
#ifdef BOARD_XOSC_ENABLE
static inline void sam_xosc_config(void);
#endif
#ifdef BOARD_XOSC32K_ENABLE
static inline void sam_xosc32k_config(void);
#endif
#ifdef BOARD_OSC32K_ENABLE
static inline void sam_osc32k_config(void);
#endif
static inline void sam_osc16m_config(void);
#ifdef BOARD_DFLL_ENABLE
static inline void sam_dfll48m_config(void);
#endif
#if defined(BOARD_GCLK_ENABLE) && defined(BOARD_DFLL_ENABLE) && \
!defined(BOARD_DFLL_OPENLOOP)
static inline void sam_dfll_reference(void);
#endif
static void sam_gclck_waitsyncbusy(void);
static void sam_gclk_config(FAR const struct sam_gclkconfig_s *config);
#ifdef BOARD_GCLK_ENABLE
static inline void sam_config_gclks(void);
#endif
static inline void sam_dividers(void);
/**************************************************************************** /****************************************************************************
* Private Data * Private Data
****************************************************************************/ ****************************************************************************/
@ -230,6 +266,22 @@ static const struct sam_gclkconfig_s g_gclkconfig[] =
#define NGCLKS_ENABLED (sizeof(g_gclkconfig) / sizeof(struct sam_gclkconfig_s)) #define NGCLKS_ENABLED (sizeof(g_gclkconfig) / sizeof(struct sam_gclkconfig_s))
#endif #endif
/* These are temporary GLCK0 configuration that may be needed at power up */
static const struct sam_gclkconfig_s g_gclk0_default =
{
.gclk = 0,
.prescaler = 1,
.clksrc = (uint8_t)(GCLK_GENCTRL_SRC_OSC16M >> GCLK_GENCTRL_SRC_SHIFT),
};
static const struct sam_gclkconfig_s g_gclk0_ulp32kconfig =
{
.gclk = 0,
.prescaler = 1,
.clksrc = (uint8_t)(GCLK_GENCTRL_SRC_OSCULP32K >> GCLK_GENCTRL_SRC_SHIFT),
};
/**************************************************************************** /****************************************************************************
* Private Functions * Private Functions
****************************************************************************/ ****************************************************************************/
@ -261,6 +313,43 @@ static inline void sam_flash_waitstates(void)
putreg32(regval, SAM_NVMCTRL_CTRLB); putreg32(regval, SAM_NVMCTRL_CTRLB);
} }
/****************************************************************************
* Name: sam_performance_level
*
* Description:
* "When scaling down the performance level, the bus frequency should be
* first scaled down in order to not exceed the maximum frequency allowed
* for the low performance level.
*
* "When scaling up the performance level (for example from PL0 to PL2),
* the bus frequency can be increased only once the performance level
* transition is completed, check the performance level status.
*
* Input Parameters:
* level - The new performance level
*
* Returned Value:
* None
*
****************************************************************************/
static void sam_performance_level(uint8_t level)
{
/* Check if we are already at this performance level */
if (level != (getreg8(SAM_PM_PLCFG) & PM_PLCFG_PLSEL_MASK))
{
/* Clear performance level status and set the new performance level */
putreg8(PM_INT_PLRDY, SAM_PM_INTFLAG);
putreg8(level, SAM_PM_PLCFG);
/* Wait for the new performance level to be ready */
while ((getreg16(SAM_PM_INTFLAG) & PM_INT_PLRDY) == 0);
}
}
/**************************************************************************** /****************************************************************************
* Name: sam_xosc_config * Name: sam_xosc_config
* *
@ -291,7 +380,11 @@ static inline void sam_xosc_config(void)
/* Configure the XOSC clock */ /* Configure the XOSC clock */
regval = BOARD_XOSC_STARTUPTIME regval = getreg16(SAM_OSCCTRL_XOSCCTRL);
regval &= ~(OSCCTRL_XOSCCTRL_RUNSTDBY | OSCCTRL_XOSCCTRL_ONDEMAND |
OSCCTRL_XOSCCTRL_GAIN_MASK | OSCCTRL_XOSCCTRL_XTALEN |
OSCCTRL_XOSCCTRL_AMPGC | OSCCTRL_XOSCCTRL_STARTUP_MASK);
regval |= BOARD_XOSC_STARTUPTIME
#ifdef BOARD_XOSC_ISCRYSTAL #ifdef BOARD_XOSC_ISCRYSTAL
/* XOSC is a crystal */ /* XOSC is a crystal */
@ -350,13 +443,14 @@ static inline void sam_xosc_config(void)
* *
* BOARD_XOSC32K_ENABLE - Boolean (defined / not defined) * BOARD_XOSC32K_ENABLE - Boolean (defined / not defined)
* BOARD_XOSC32K_FREQUENCY - In Hz * BOARD_XOSC32K_FREQUENCY - In Hz
* BOARD_XOSC32K_STARTUPTIME - See OS32KCCTRL_XOSC32K_STARTUP_* definitions * BOARD_XOSC32K_STARTUPTIME - See OSC32KCTRL_XOSC32K_STARTUP_* definitions
* BOARD_XOSC32K_ISCRYSTAL - Boolean (defined / not defined) * BOARD_XOSC32K_ISCRYSTAL - Boolean (defined / not defined)
* BOARD_XOSC32K_AAMPEN - Boolean (defined / not defined) * BOARD_XOSC32K_AAMPEN - Boolean (defined / not defined)
* BOARD_XOSC32K_EN1KHZ - Boolean (defined / not defined) * BOARD_XOSC32K_EN1KHZ - Boolean (defined / not defined)
* BOARD_XOSC32K_EN32KHZ - Boolean (defined / not defined) * BOARD_XOSC32K_EN32KHZ - Boolean (defined / not defined)
* BOARD_XOSC32K_ONDEMAND - Boolean (defined / not defined) * BOARD_XOSC32K_ONDEMAND - Boolean (defined / not defined)
* BOARD_XOSC32K_RUNINSTANDBY - Boolean (defined / not defined) * BOARD_XOSC32K_RUNINSTANDBY - Boolean (defined / not defined)
* BOARD_XOSC32K_WRITELOCK - Boolean (defined / not defined)
* *
* Input Parameters: * Input Parameters:
* None * None
@ -373,38 +467,54 @@ static inline void sam_xosc32k_config(void)
/* Configure XOSC32K */ /* Configure XOSC32K */
regval = BOARD_XOSC32K_STARTUPTIME regval = getreg16(SAM_OSC32KCTRL_XOSC32K);
regval &= ~(OSC32KCTRL_XOSC32K_XTALEN | OSC32KCTRL_XOSC32K_EN32K |
OSC32KCTRL_XOSC32K_EN1K | OSC32KCTRL_XOSC32K_RUNSTDBY |
OSC32KCTRL_XOSC32K_ONDEMAND | OSC32KCTRL_XOSC32K_STARTUP_MASK |
OSC32KCTRL_XOSC32K_WRTLOCK);
regval |= BOARD_XOSC32K_STARTUPTIME
#ifdef BOARD_XOSC32K_ISCRYSTAL #ifdef BOARD_XOSC32K_ISCRYSTAL
regval |= OS32KCCTRL_XOSC32K_XTALEN; regval |= OSC32KCTRL_XOSC32K_XTALEN;
#endif #endif
#ifdef BOARD_XOSC32K_AAMPEN #ifdef BOARD_XOSC32K_AAMPEN
regval |= OS32KCCTRL_XOSC32K_AAMPEN; regval |= OSC32KCTRL_XOSC32K_AAMPEN;
#endif #endif
#ifdef BOARD_XOSC32K_EN1KHZ #ifdef BOARD_XOSC32K_EN1KHZ
regval |= OS32KCCTRL_XOSC32K_EN1K; regval |= OSC32KCTRL_XOSC32K_EN1K;
#endif #endif
#ifdef BOARD_XOSC32K_EN32KHZ #ifdef BOARD_XOSC32K_EN32KHZ
regval |= OS32KCCTRL_XOSC32K_EN32K; regval |= OSC32KCTRL_XOSC32K_EN32K;
#endif #endif
#ifdef BOARD_XOSC32K_ONDEMAND #ifdef BOARD_XOSC32K_ONDEMAND
regval |= OS32KCCTRL_XOSC32K_ONDEMAND; regval |= OSC32KCTRL_XOSC32K_ONDEMAND;
#endif #endif
#ifdef BOARD_XOSC32K_RUNINSTANDBY #ifdef BOARD_XOSC32K_RUNINSTANDBY
regval |= OS32KCCTRL_XOSC32K_RUNSTDBY; regval |= OSC32KCTRL_XOSC32K_RUNSTDBY;
#endif #endif
putreg16(regval, SAM_OS32KCCTRL_XOSC32K); putreg16(regval, SAM_OSC32KCTRL_XOSC32K);
/* Then enable the XOSC clock */ /* Then enable the XOSC clock */
regval |= OS32KCCTRL_XOSC32K_ENABLE; regval |= OSC32KCTRL_XOSC32K_ENABLE;
putreg16(regval, SAM_OS32KCCTRL_XOSC32K); putreg16(regval, SAM_OSC32KCTRL_XOSC32K);
/* Wait for XOSC32K to be ready */
while ((getreg32(SAM_OSC32CTRL_STATUS) & OSC32KCTRL_INT_XOSC32KRDY) == 0);
#ifdef BOARD_XOSC32K_WRITELOCK
/* Lock this configuration until the next power up */
regval |= OSC32KCTRL_XOSC32K_WRTLOCK;
putreg16(regval, SAM_OSC32KCTRL_XOSC32K);
#endif
} }
#else #else
# define sam_xosc32k_config() # define sam_xosc32k_config()
@ -419,11 +529,12 @@ static inline void sam_xosc32k_config(void)
* *
* BOARD_OSC32K_ENABLE - Boolean (defined / not defined) * BOARD_OSC32K_ENABLE - Boolean (defined / not defined)
* BOARD_OSC32K_FREQUENCY - In Hz * BOARD_OSC32K_FREQUENCY - In Hz
* BOARD_OSC32K_STARTUPTIME - See OS32KCCTRL_OSC32K_STARTUP_* definitions * BOARD_OSC32K_STARTUPTIME - See OSC32KCTRL_OSC32K_STARTUP_* definitions
* BOARD_OSC32K_EN1KHZ - Boolean (defined / not defined) * BOARD_OSC32K_EN1KHZ - Boolean (defined / not defined)
* BOARD_OSC32K_EN32KHZ - Boolean (defined / not defined) * BOARD_OSC32K_EN32KHZ - Boolean (defined / not defined)
* BOARD_OSC32K_ONDEMAND - Boolean (defined / not defined) * BOARD_OSC32K_ONDEMAND - Boolean (defined / not defined)
* BOARD_OSC32K_RUNINSTANDBY - Boolean (defined / not defined) * BOARD_OSC32K_RUNINSTANDBY - Boolean (defined / not defined)
* BOARD_OSC32K_WRITELOCK - Boolean (defined / not defined)
* *
* Input Parameters: * Input Parameters:
* None * None
@ -437,45 +548,65 @@ static inline void sam_xosc32k_config(void)
static inline void sam_osc32k_config(void) static inline void sam_osc32k_config(void)
{ {
uint32_t regval; uint32_t regval;
uint32_t calib;
/* Recover OSC32K calibration data from OTP "fuse" memory */
regval = getreg32(SAM_FUSES_OSC32KCAL_ADDR);
calib = (regval & SAM_FUSES_OSC32KCAL_MASK) >> SAM_FUSES_OSC32KCAL_SHIFT;
regval = calib << OS32KCCTRL_OSC32K_CALIB_SHIFT;
/* Configure OSC32K */ /* Configure OSC32K */
regval = getreg32(SAM_OSC32KCTRL_OSC32K);
regval &= ~(OSC32KCTRL_OSC32K_EN32K | OSC32KCTRL_OSC32K_EN1K |
OSC32KCTRL_OSC32K_RUNSTDBY | OSC32KCTRL_OSC32K_ONDEMAND |
OSC32KCTRL_OSC32K_STARTUP_MASK | OSC32KCTRL_OSC32K_WRTLOCK);
regval |= BOARD_OSC32K_STARTUPTIME; regval |= BOARD_OSC32K_STARTUPTIME;
#ifdef BOARD_OSC32K_EN1KHZ
regval |= OS32KCCTRL_OSC32K_EN1K;
#endif
#ifdef BOARD_OSC32K_EN32KHZ #ifdef BOARD_OSC32K_EN32KHZ
regval |= OS32KCCTRL_OSC32K_EN32K; regval |= OSC32KCTRL_OSC32K_EN32K;
#endif #endif
#ifdef BOARD_OSC32K_ONDEMAND #ifdef BOARD_OSC32K_EN1KHZ
regval |= OS32KCCTRL_OSC32K_ONDEMAND; regval |= OSC32KCTRL_OSC32K_EN1K;
#endif #endif
#ifdef BOARD_OSC32K_RUNINSTANDBY #ifdef BOARD_OSC32K_RUNINSTANDBY
regval |= OS32KCCTRL_OSC32K_RUNSTDBY; regval |= OSC32KCTRL_OSC32K_RUNSTDBY;
#endif #endif
putreg32(regval, SAM_OS32KCCTRL_OSC32K); #ifdef BOARD_OSC32K_ONDEMAND
regval |= OSC32KCTRL_OSC32K_ONDEMAND;
#endif
putreg32(regval, SAM_OSC32KCTRL_OSC32K);
/* Then enable OSC32K */ /* Then enable OSC32K */
regval |= OS32KCCTRL_OSC32K_ENABLE; regval |= OSC32KCTRL_OSC32K_ENABLE;
putreg32(regval, SAM_OS32KCCTRL_OSC32K); putreg32(regval, SAM_OSC32KCTRL_OSC32K);
#ifdef BOARD_XOSC32K_WRITELOCK
/* Lock this configuration until the next power up */
regval |= OSC32KCTRL_OSC32K_WRTLOCK;
putreg16(regval, SAM_OSC32KCTRL_OSC32K);
#endif
} }
#else #else
# define sam_osc32k_config() # define sam_osc32k_config()
#endif #endif
/****************************************************************************
* Name: sam_osculp32k_config
*
* Description:
* Configure OSCULP32K
*
* Input Parameters:
* None
*
* Returned Value:
* None
*
****************************************************************************/
#define sam_osculp32k_config()
/**************************************************************************** /****************************************************************************
* Name: sam_osc16m_config * Name: sam_osc16m_config
* *
@ -483,7 +614,7 @@ static inline void sam_osc32k_config(void)
* Configure OSC16M based on settings in the board.h header file. * Configure OSC16M based on settings in the board.h header file.
* Depends on: * Depends on:
* *
* BOARD_OSC16M_PRESCALER - See OSCCTRL_OSC16MCTRL_PRESC_DIV* definitions * BOARD_OSC16M_FSEL - See OSCCTRL_OSC16MCTRL_FSEL_* definitions
* BOARD_OSC16M_ONDEMAND - Boolean (defined / not defined) * BOARD_OSC16M_ONDEMAND - Boolean (defined / not defined)
* BOARD_OSC16M_RUNINSTANDBY - Boolean (defined / not defined) * BOARD_OSC16M_RUNINSTANDBY - Boolean (defined / not defined)
* *
@ -518,16 +649,25 @@ static inline void sam_osc32k_config(void)
static inline void sam_osc16m_config(void) static inline void sam_osc16m_config(void)
{ {
uint32_t regval; uint32_t regval;
bool enabled;
/* After reset, OSC16M is enabled and serve4s as the default clock source
* at 4MHz. Since this particular logic only runs on reset, there is
* some additional unnecessary logic in the following.
*/
/* Configure OSC16M */ /* Configure OSC16M */
regval = getreg32(SAM_OSCCTRL_OSC16MCTRL); regval = getreg32(SAM_OSCCTRL_OSC16MCTRL);
regval &= ~(OSCCTRL_OSC16MCTRL_PRESC_MASK | OSCCTRL_OSC16MCTRL_ONDEMAND |
OSCCTRL_OSC16MCTRL_RUNSTDBY);
/* Select the prescaler */ /* Is OSC16M already enabled? Is it already running at the requested
* frequency?
*/
regval |= (BOARD_OSC16M_PRESCALER | OSCCTRL_OSC16MCTRL_ENABLE); enabled = ((regval & OSCCTRL_OSC16MCTRL_ENABLE) != 0);
if (enabled && (regval & OSCCTRL_OSC16MCTRL_FSEL_MASK) == BOARD_OSC16M_FSEL)
{
regval &= ~(OSCCTRL_OSC16MCTRL_ONDEMAND | OSCCTRL_OSC16MCTRL_RUNSTDBY);
#ifdef BOARD_OSC16M_ONDEMAND #ifdef BOARD_OSC16M_ONDEMAND
/* Select on-demand oscillator controls */ /* Select on-demand oscillator controls */
@ -541,11 +681,72 @@ static inline void sam_osc16m_config(void)
regval |= OSCCTRL_OSC16MCTRL_RUNSTDBY; regval |= OSCCTRL_OSC16MCTRL_RUNSTDBY;
#endif #endif
/* Set the OSC16M configuration */ /* Save the new OSC16M configuration */
putreg32(regval, SAM_OSCCTRL_OSC16MCTRL); putreg32(regval, SAM_OSCCTRL_OSC16MCTRL);
} }
/* Either the OSC16M is not running (which is not possible in this
* context) or else OSC16M is configured to run at a different frequency.
*/
else
{
/* If it is enabled, then we are probably running on OSC16M now.
* Select OSCULP32K as new clock source for main clock temporarily.
* This depends on the fact the GCLK0 is enabled at reset.
*/
if (enabled)
{
sam_gclk_config(&g_gclk0_ulp32kconfig);
/* Disable OSC16M clock */
regval &= ~OSCCTRL_OSC16MCTRL_ENABLE;
putreg32(regval, SAM_OSCCTRL_OSC16MCTRL);
}
/* Set the new OSC16M configuration */
regval &= ~(OSCCTRL_OSC16MCTRL_FSEL_MASK | OSCCTRL_OSC16MCTRL_RUNSTDBY |
OSCCTRL_OSC16MCTRL_ONDEMAND);
regval |= BOARD_OSC16M_FSEL;
#ifdef BOARD_OSC16M_ONDEMAND
/* Select on-demand oscillator controls */
regval |= OSCCTRL_OSC16MCTRL_ONDEMAND;
#endif
#ifdef BOARD_OSC16M_RUNINSTANDBY
/* The oscillator continues to run in standby sleep mode */
regval |= OSCCTRL_OSC16MCTRL_RUNSTDBY;
#endif
/* Save the new OSC16M configuration */
putreg32(regval, SAM_OSCCTRL_OSC16MCTRL);
/* Enable OSC16M */
regval |= OSCCTRL_OSC16MCTRL_ENABLE;
putreg32(regval, SAM_OSCCTRL_OSC16MCTRL);
/* Wait for OSC16M to be ready */
while ((getreg32(SAM_OSCCTRL_STATUS) & OSCCTRL_INT_OSC16MRDY) == 0);
/* Re-select OSC16M for main clock again */
if (enabled)
{
sam_gclk_config(&g_gclk0_default);
}
}
}
/**************************************************************************** /****************************************************************************
* Name: sam_dfll48m_config * Name: sam_dfll48m_config
* *
@ -745,8 +946,7 @@ static void sam_gclck_waitsyncbusy(void)
* *
****************************************************************************/ ****************************************************************************/
#ifdef BOARD_GCLK_ENABLE static void sam_gclk_config(FAR const struct sam_gclkconfig_s *config)
static inline void sam_gclk_config(FAR const struct sam_gclkconfig_s *config)
{ {
uint32_t genctrl; uint32_t genctrl;
uint32_t gendiv; uint32_t gendiv;
@ -848,7 +1048,6 @@ static inline void sam_gclk_config(FAR const struct sam_gclkconfig_s *config)
sam_gclck_waitsyncbusy(); sam_gclck_waitsyncbusy();
} }
#endif
/**************************************************************************** /****************************************************************************
* Name: sam_config_gclks * Name: sam_config_gclks
@ -881,14 +1080,11 @@ static inline void sam_gclk_config(FAR const struct sam_gclkconfig_s *config)
#ifdef BOARD_GCLK_ENABLE #ifdef BOARD_GCLK_ENABLE
static inline void sam_config_gclks(void) static inline void sam_config_gclks(void)
{ {
uint32_t regval;
int i; int i;
/* Turn on the GCLK interface clock */ /* Turn on the GCLK interface clock */
regval = getreg32(SAM_PM_APBAMASK); sam_gclk_enableperiph();
regval |= PM_APBAMASK_GCLK;
putreg32(regval, SAM_PM_APBAMASK);
/* Reset the GCLK module */ /* Reset the GCLK module */
@ -993,11 +1189,16 @@ void sam_clockconfig(void)
putreg32(OSCCTRL_INT_ALL, SAM_OSCCTRL_INTFLAG); putreg32(OSCCTRL_INT_ALL, SAM_OSCCTRL_INTFLAG);
putreg32(OSC32KCTRL_INT_ALL, SAM_OSC32KCTRL_INTFLAG); putreg32(OSC32KCTRL_INT_ALL, SAM_OSC32KCTRL_INTFLAG);
putreg32(SUPC_INT_ALL, SAM_SUPC_INTFLAG);
/* Set FLASH wait states */ /* Set FLASH wait states */
sam_flash_waitstates(); sam_flash_waitstates();
/* Switch to PL2 to be sure configuration of GCLK0 is safe */
sam_performance_level(PM_PLCFG_PLSEL_PL2);
/* Configure XOSC */ /* Configure XOSC */
sam_xosc_config(); sam_xosc_config();

248
arch/arm/src/samdl/saml_periphclks.h Normal file
View File

@ -0,0 +1,248 @@
/****************************************************************************
* arch/arm/src/samdl/saml_periphclks.h
*
* Copyright (C) 2015 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
****************************************************************************/
#ifndef __ARCH_ARM_SRC_SAMDL_SAML_PERIPHCLKS_H
#define __ARCH_ARM_SRC_SAMDL_SAML_PERIPHCLKS_H
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include "chip/saml_mclk.h"
#ifdef CONFIG_ARCH_FAMILY_SAML21
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
#define sam_apba_enableperiph(s) modifyreg32(SAM_MCLK_APBAMASK,0,s)
#define sam_pm_enableperiph() sam_apba_enableperiph(MCLK_APBAMASK_PM)
#define sam_mclk_enableperiph() sam_apba_enableperiph(MCLK_APBAMASK_MCLK)
#define sam_rstc_enableperiph() sam_apba_enableperiph(MCLK_APBAMASK_RSTC)
#define sam_oscctrl_enableperiph() sam_apba_enableperiph(MCLK_APBAMASK_OSCCTRL)
#define sam_osc32kctrl_enableperiph() sam_apba_enableperiph(MCLK_APBAMASK_OSC32KCTRL)
#define sam_supc_enableperiph() sam_apba_enableperiph(MCLK_APBAMASK_SUPC)
#define sam_gclk_enableperiph() sam_apba_enableperiph(MCLK_APBAMASK_GCLK)
#define sam_wdt_enableperiph() sam_apba_enableperiph(MCLK_APBAMASK_WDT)
#define sam_rtc_enableperiph() sam_apba_enableperiph(MCLK_APBAMASK_RTC)
#define sam_eic_enableperiph() sam_apba_enableperiph(MCLK_APBAMASK_EIC)
#define sam_port_enableperiph() sam_apba_enableperiph(MCLK_APBAMASK_PORT)
#define sam_apbb_enableperiph(s) modifyreg32(SAM_MCLK_APBBMASK,0,s)
#define sam_usb_enableperiph() sam_apbb_enableperiph(MCLK_APBBMASK_USB)
#define sam_dsu_enableperiph() sam_apbb_enableperiph(MCLK_APBBMASK_DSU)
#define sam_nvmctrl_enableperiph() sam_apbb_enableperiph(MCLK_APBBMASK_NVMCTRL)
#define sam_apbc_enableperiph(s) modifyreg32(SAM_MCLK_APBCMASK,0,s)
#define sam_sercom_enableperiph(n) sam_apbc_enableperiph(MCLK_APBCMASK_SERCOM(n))
#define sam_sercom0_enableperiph() sam_apbc_enableperiph(MCLK_APBCMASK_SERCOM0)
#define sam_sercom1_enableperiph() sam_apbc_enableperiph(MCLK_APBCMASK_SERCOM1)
#define sam_sercom2_enableperiph() sam_apbc_enableperiph(MCLK_APBCMASK_SERCOM2)
#define sam_sercom3_enableperiph() sam_apbc_enableperiph(MCLK_APBCMASK_SERCOM3)
#define sam_sercom4_enableperiph() sam_apbc_enableperiph(MCLK_APBCMASK_SERCOM4)
#define sam_tcc0_enableperiph() sam_apbc_enableperiph(MCLK_APBCMASK_TCC0)
#define sam_tcc1_enableperiph() sam_apbc_enableperiph(MCLK_APBCMASK_TCC1)
#define sam_tcc2_enableperiph() sam_apbc_enableperiph(MCLK_APBCMASK_TCC2)
#define sam_tc0_enableperiph() sam_apbc_enableperiph(MCLK_APBCMASK_TC0)
#define sam_tc1_enableperiph() sam_apbc_enableperiph(MCLK_APBCMASK_TC1)
#define sam_tc2_enableperiph() sam_apbc_enableperiph(MCLK_APBCMASK_TC2)
#define sam_tc3_enableperiph() sam_apbc_enableperiph(MCLK_APBCMASK_TC3)
#define sam_dac_enableperiph() sam_apbc_enableperiph(MCLK_APBCMASK_DAC)
#define sam_aes_enableperiph() sam_apbc_enableperiph(MCLK_APBCMASK_AES)
#define sam_trng_enableperiph() sam_apbc_enableperiph(MCLK_APBCMASK_TRNG)
#define sam_apbd_enableperiph(s) modifyreg32(SAM_MCLK_APBDMASK,0,s)
#define sam_evsys_enableperiph() sam_apbd_enableperiph(MCLK_APBDMASK_EVSYS)
#define sam_sercom5_enableperiph() sam_apbd_enableperiph(MCLK_APBDMASK_SERCOM5)
#define sam_tc4_enableperiph() sam_apbd_enableperiph(MCLK_APBDMASK_TC4)
#define sam_adc_enableperiph() sam_apbd_enableperiph(MCLK_APBDMASK_ADC)
#define sam_ac_enableperiph() sam_apbd_enableperiph(MCLK_APBDMASK_AC)
#define sam_ptc_enableperiph() sam_apbd_enableperiph(MCLK_APBDMASK_PTC)
#define sam_opamp_enableperiph() sam_apbd_enableperiph(MCLK_APBDMASK_OPAMP)
#define sam_ccl_enableperiph() sam_apbd_enableperiph(MCLK_APBDMASK_CCL)
#define sam_apbe_enableperiph(s) modifyreg32(SAM_MCLK_APBEMASK,0,s)
#define sam_pac_enableperiph() sam_apbe_enableperiph(MCLK_APBEMASK_PAC)
#define sam_apba_disableperiph(s) modifyreg32(SAM_MCLK_APBAMASK,s,0)
#define sam_pm_disableperiph() sam_apba_disableperiph(MCLK_APBAMASK_PM)
#define sam_mclk_disableperiph() sam_apba_disableperiph(MCLK_APBAMASK_MCLK)
#define sam_rstc_disableperiph() sam_apba_disableperiph(MCLK_APBAMASK_RSTC)
#define sam_oscctrl_disableperiph() sam_apba_disableperiph(MCLK_APBAMASK_OSCCTRL)
#define sam_osc32kctrl_disableperiph() sam_apba_disableperiph(MCLK_APBAMASK_OSC32KCTRL)
#define sam_supc_disableperiph() sam_apba_disableperiph(MCLK_APBAMASK_SUPC)
#define sam_gclk_disableperiph() sam_apba_disableperiph(MCLK_APBAMASK_GCLK)
#define sam_wdt_disableperiph() sam_apba_disableperiph(MCLK_APBAMASK_WDT)
#define sam_rtc_disableperiph() sam_apba_disableperiph(MCLK_APBAMASK_RTC)
#define sam_eic_disableperiph() sam_apba_disableperiph(MCLK_APBAMASK_EIC)
#define sam_port_disableperiph() sam_apba_disableperiph(MCLK_APBAMASK_PORT)
#define sam_apbb_disableperiph(s) modifyreg32(SAM_MCLK_APBBMASK,s,0)
#define sam_usb_disableperiph() sam_apbb_disableperiph(MCLK_APBBMASK_USB)
#define sam_dsu_disableperiph() sam_apbb_disableperiph(MCLK_APBBMASK_DSU)
#define sam_nvmctrl_disableperiph() sam_apbb_disableperiph(MCLK_APBBMASK_NVMCTRL)
#define sam_apbc_disableperiph(s) modifyreg32(SAM_MCLK_APBCMASK,s,0)
#define sam_sercom_disableperiph(n) sam_apbc_disableperiph(MCLK_APBCMASK_SERCOM(n))
#define sam_sercom0_disableperiph() sam_apbc_disableperiph(MCLK_APBCMASK_SERCOM0)
#define sam_sercom1_disableperiph() sam_apbc_disableperiph(MCLK_APBCMASK_SERCOM1)
#define sam_sercom2_disableperiph() sam_apbc_disableperiph(MCLK_APBCMASK_SERCOM2)
#define sam_sercom3_disableperiph() sam_apbc_disableperiph(MCLK_APBCMASK_SERCOM3)
#define sam_sercom4_disableperiph() sam_apbc_disableperiph(MCLK_APBCMASK_SERCOM4)
#define sam_tcc0_disableperiph() sam_apbc_disableperiph(MCLK_APBCMASK_TCC0)
#define sam_tcc1_disableperiph() sam_apbc_disableperiph(MCLK_APBCMASK_TCC1)
#define sam_tcc2_disableperiph() sam_apbc_disableperiph(MCLK_APBCMASK_TCC2)
#define sam_tc0_disableperiph() sam_apbc_disableperiph(MCLK_APBCMASK_TC0)
#define sam_tc1_disableperiph() sam_apbc_disableperiph(MCLK_APBCMASK_TC1)
#define sam_tc2_disableperiph() sam_apbc_disableperiph(MCLK_APBCMASK_TC2)
#define sam_tc3_disableperiph() sam_apbc_disableperiph(MCLK_APBCMASK_TC3)
#define sam_dac_disableperiph() sam_apbc_disableperiph(MCLK_APBCMASK_DAC)
#define sam_aes_disableperiph() sam_apbc_disableperiph(MCLK_APBCMASK_AES)
#define sam_trng_disableperiph() sam_apbc_disableperiph(MCLK_APBCMASK_TRNG)
#define sam_apbd_disableperiph(s) modifyreg32(SAM_MCLK_APBDMASK,s,0)
#define sam_evsys_disableperiph() sam_apbd_disableperiph(MCLK_APBDMASK_EVSYS)
#define sam_sercom5_disableperiph() sam_apbd_disableperiph(MCLK_APBDMASK_SERCOM5)
#define sam_tc4_disableperiph() sam_apbd_disableperiph(MCLK_APBDMASK_TC4)
#define sam_adc_disableperiph() sam_apbd_disableperiph(MCLK_APBDMASK_ADC)
#define sam_ac_disableperiph() sam_apbd_disableperiph(MCLK_APBDMASK_AC)
#define sam_ptc_disableperiph() sam_apbd_disableperiph(MCLK_APBDMASK_PTC)
#define sam_opamp_disableperiph() sam_apbd_disableperiph(MCLK_APBDMASK_OPAMP)
#define sam_ccl_disableperiph() sam_apbd_disableperiph(MCLK_APBDMASK_CCL)
#define sam_apbe_disableperiph(s) modifyreg32(SAM_MCLK_APBEMASK,s,0)
#define sam_pac_disableperiph() sam_apbe_disableperiph(MCLK_APBEMASK_PAC)
#define sam_apba_isenabled(s) (getreg32(SAM_MCLK_APBAMASK) & (s)) != 0)
#define sam_pm_isenabled() sam_apba_isenabled(MCLK_APBAMASK_PM)
#define sam_mclk_isenabled() sam_apba_isenabled(MCLK_APBAMASK_MCLK)
#define sam_rstc_isenabled() sam_apba_isenabled(MCLK_APBAMASK_RSTC)
#define sam_oscctrl_isenabled() sam_apba_isenabled(MCLK_APBAMASK_OSCCTRL)
#define sam_osc32kctrl_isenabled() sam_apba_isenabled(MCLK_APBAMASK_OSC32KCTRL)
#define sam_supc_isenabled() sam_apba_isenabled(MCLK_APBAMASK_SUPC)
#define sam_gclk_isenabled() sam_apba_isenabled(MCLK_APBAMASK_GCLK)
#define sam_wdt_isenabled() sam_apba_isenabled(MCLK_APBAMASK_WDT)
#define sam_rtc_isenabled() sam_apba_isenabled(MCLK_APBAMASK_RTC)
#define sam_eic_isenabled() sam_apba_isenabled(MCLK_APBAMASK_EIC)
#define sam_port_isenabled() sam_apba_isenabled(MCLK_APBAMASK_PORT)
#define sam_apbb_isenabled(s) (getreg32(SAM_MCLK_APBBMASK) & (s)) != 0)
#define sam_usb_isenabled() sam_apbb_isenabled(MCLK_APBBMASK_USB)
#define sam_dsu_isenabled() sam_apbb_isenabled(MCLK_APBBMASK_DSU)
#define sam_nvmctrl_isenabled() sam_apbb_isenabled(MCLK_APBBMASK_NVMCTRL)
#define sam_apbc_isenabled(s) (getreg32(SAM_MCLK_APBCMASK) & (s)) != 0)
#define sam_sercom_isenabled(n) sam_apbc_isenabled(MCLK_APBCMASK_SERCOM(n))
#define sam_sercom0_isenabled() sam_apbc_isenabled(MCLK_APBCMASK_SERCOM0)
#define sam_sercom1_isenabled() sam_apbc_isenabled(MCLK_APBCMASK_SERCOM1)
#define sam_sercom2_isenabled() sam_apbc_isenabled(MCLK_APBCMASK_SERCOM2)
#define sam_sercom3_isenabled() sam_apbc_isenabled(MCLK_APBCMASK_SERCOM3)
#define sam_sercom4_isenabled() sam_apbc_isenabled(MCLK_APBCMASK_SERCOM4)
#define sam_tcc0_isenabled() sam_apbc_isenabled(MCLK_APBCMASK_TCC0)
#define sam_tcc1_isenabled() sam_apbc_isenabled(MCLK_APBCMASK_TCC1)
#define sam_tcc2_isenabled() sam_apbc_isenabled(MCLK_APBCMASK_TCC2)
#define sam_tc0_isenabled() sam_apbc_isenabled(MCLK_APBCMASK_TC0)
#define sam_tc1_isenabled() sam_apbc_isenabled(MCLK_APBCMASK_TC1)
#define sam_tc2_isenabled() sam_apbc_isenabled(MCLK_APBCMASK_TC2)
#define sam_tc3_isenabled() sam_apbc_isenabled(MCLK_APBCMASK_TC3)
#define sam_dac_isenabled() sam_apbc_isenabled(MCLK_APBCMASK_DAC)
#define sam_aes_isenabled() sam_apbc_isenabled(MCLK_APBCMASK_AES)
#define sam_trng_isenabled() sam_apbc_isenabled(MCLK_APBCMASK_TRNG)
#define sam_apbd_isenabled(s) (getreg32(SAM_MCLK_APBDMASK) & (s)) != 0)
#define sam_evsys_isenabled() sam_apbd_isenabled(MCLK_APBDMASK_EVSYS)
#define sam_sercom5_isenabled() sam_apbd_isenabled(MCLK_APBDMASK_SERCOM5)
#define sam_tc4_isenabled() sam_apbd_isenabled(MCLK_APBDMASK_TC4)
#define sam_adc_isenabled() sam_apbd_isenabled(MCLK_APBDMASK_ADC)
#define sam_ac_isenabled() sam_apbd_isenabled(MCLK_APBDMASK_AC)
#define sam_ptc_isenabled() sam_apbd_isenabled(MCLK_APBDMASK_PTC)
#define sam_opamp_isenabled() sam_apbd_isenabled(MCLK_APBDMASK_OPAMP)
#define sam_ccl_isenabled() sam_apbd_isenabled(MCLK_APBDMASK_CCL)
#define sam_apbe_isenabled(s) (getreg32(SAM_MCLK_APBEMASK) & (s)) != 0)
#define sam_pac_isenabled() sam_apbe_isenabled(MCLK_APBEMASK_PAC)
/****************************************************************************
* Public Types
****************************************************************************/
/****************************************************************************
* Inline Functions
****************************************************************************/
#ifndef __ASSEMBLY__
/****************************************************************************
* Public Data
****************************************************************************/
#undef EXTERN
#if defined(__cplusplus)
#define EXTERN extern "C"
extern "C"
{
#else
#define EXTERN extern
#endif
/****************************************************************************
* Public Function Prototypes
****************************************************************************/
#undef EXTERN
#if defined(__cplusplus)
}
#endif
#endif /* __ASSEMBLY__ */
#endif /* CONFIG_ARCH_FAMILY_SAML21 */
#endif /* __ARCH_ARM_SRC_SAMDL_SAML_PERIPHCLKS_H */

22
configs/saml21-xplained/include/board.h
View File

@ -56,14 +56,20 @@
/* Clocking *************************************************************************/ /* Clocking *************************************************************************/
/* Overview /* Overview
* *
* OSC16M Output = 16MHz * Since there is not high speed crystal, we will run from the OSC16M clock source.
* `- GCLK1 Input = 16MHz Prescaler = 1 output = 16MHz * We will use its default, POR frequency of 4MHz to avoid an additional clock
* `- DFLL Input = 8MHz Multiplier = 3 output = 48MHz * switch.
*
* OSC16M Output = 4MHz
* `- GCLK1 Input = 4MHz Prescaler = 1 output = 4MHz
* `- DFLL Input = 4MHz Multiplier = 12 output = 48MHz
* `- GCLK0 Input = 48MHz Prescaler = 1 output = 48MHz * `- GCLK0 Input = 48MHz Prescaler = 1 output = 48MHz
* `- PM Input = 48Mhz CPU divider = 1 CPU frequency = 48MHz * `- PM Input = 48Mhz CPU divider = 1 CPU frequency = 48MHz
* APBA divider = 1 APBA frequency = 48MHz * APBA divider = 1 APBA frequency = 48MHz
* APBB divider = 1 APBB frequency = 48MHz * APBB divider = 1 APBB frequency = 48MHz
* APBC divider = 1 APBC frequency = 48MHz * APBC divider = 1 APBC frequency = 48MHz
* APBD divider = 1 APBD frequency = 48MHz
* APBE divider = 1 APBE frequency = 48MHz
* *
* The SAML21 Xplained Pro has one on-board crystal: * The SAML21 Xplained Pro has one on-board crystal:
* *
@ -104,6 +110,7 @@
* BOARD_XOSC32K_EN32KHZ - Boolean (defined / not defined) * BOARD_XOSC32K_EN32KHZ - Boolean (defined / not defined)
* BOARD_XOSC32K_ONDEMAND - Boolean (defined / not defined) * BOARD_XOSC32K_ONDEMAND - Boolean (defined / not defined)
* BOARD_XOSC32K_RUNINSTANDBY - Boolean (defined / not defined) * BOARD_XOSC32K_RUNINSTANDBY - Boolean (defined / not defined)
* BOARD_XOSC32K_WRITELOCK - Boolean (defined / not defined)
*/ */
#undef BOARD_XOSC32K_ENABLE #undef BOARD_XOSC32K_ENABLE
@ -115,6 +122,7 @@
#define BOARD_XOSC32K_EN32KHZ 1 #define BOARD_XOSC32K_EN32KHZ 1
#define BOARD_XOSC32K_ONDEMAND 1 #define BOARD_XOSC32K_ONDEMAND 1
#undef BOARD_XOSC32K_RUNINSTANDBY #undef BOARD_XOSC32K_RUNINSTANDBY
#undef BOARD_XOSC32K_WRITELOCK
/* OSC32 Configuration -- not used /* OSC32 Configuration -- not used
* *
@ -125,6 +133,7 @@
* BOARD_OSC32K_EN32KHZ - Boolean (defined / not defined) * BOARD_OSC32K_EN32KHZ - Boolean (defined / not defined)
* BOARD_OSC32K_ONDEMAND - Boolean (defined / not defined) * BOARD_OSC32K_ONDEMAND - Boolean (defined / not defined)
* BOARD_OSC32K_RUNINSTANDBY - Boolean (defined / not defined) * BOARD_OSC32K_RUNINSTANDBY - Boolean (defined / not defined)
* BOARD_OSC32K_WRITELOCK - Boolean (defined / not defined)
*/ */
#undef BOARD_OSC32K_ENABLE #undef BOARD_OSC32K_ENABLE
@ -134,15 +143,16 @@
#define BOARD_OSC32K_EN32KHZ 1 #define BOARD_OSC32K_EN32KHZ 1
#define BOARD_OSC32K_ONDEMAND 1 #define BOARD_OSC32K_ONDEMAND 1
#undef BOARD_OSC32K_RUNINSTANDBY #undef BOARD_OSC32K_RUNINSTANDBY
#undef BOARD_OSC32K_WRITELOCK
/* OSC16M Configuration -- always enabled /* OSC16M Configuration -- always enabled
* *
* BOARD_OSC16M_PRESCALER - See SYSCTRL_OSC16M_PRESC_DIV* definitions * BOARD_OSC16M_FSEL - See OSCCTRL_OSC16MCTRL_FSEL_* definitions
* BOARD_OSC16M_ONDEMAND - Boolean (defined / not defined) * BOARD_OSC16M_ONDEMAND - Boolean (defined / not defined)
* BOARD_OSC16M_RUNINSTANDBY - Boolean (defined / not defined) * BOARD_OSC16M_RUNINSTANDBY - Boolean (defined / not defined)
*/ */
#define BOARD_OSC16M_PRESCALER SYSCTRL_OSC16M_PRESC_DIV1 #define BOARD_OSC16M_FSEL OSCCTRL_OSC16MCTRL_FSEL_4MHZ
#define BOARD_OSC16M_ONDEMAND 1 #define BOARD_OSC16M_ONDEMAND 1
#undef BOARD_OSC16M_RUNINSTANDBY #undef BOARD_OSC16M_RUNINSTANDBY
@ -200,7 +210,7 @@
/* DFLL closed loop mode configuration */ /* DFLL closed loop mode configuration */
#define BOARD_DFLL_SRCGCLKGEN GCLK_CLKCTRL_GEN1 #define BOARD_DFLL_SRCGCLKGEN GCLK_CLKCTRL_GEN1
#define BOARD_DFLL_MULTIPLIER 3 #define BOARD_DFLL_MULTIPLIER 12
#define BOARD_DFLL_QUICKLOCK 1 #define BOARD_DFLL_QUICKLOCK 1
#define BOARD_DFLL_TRACKAFTERFINELOCK 1 #define BOARD_DFLL_TRACKAFTERFINELOCK 1
#define BOARD_DFLL_KEEPLOCKONWAKEUP 1 #define BOARD_DFLL_KEEPLOCKONWAKEUP 1