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Add LM3S8962 support

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git-svn-id: svn://svn.code.sf.net/p/nuttx/code/trunk@2914 42af7a65-404d-4744-a932-0658087f49c3
This commit is contained in:
patacongo 2010-09-03 15:14:28 +00:00
parent 11d40b9c1a
commit 859f2cf71a
8 changed files with 211 additions and 5 deletions
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4
ChangeLog
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@ -1250,3 +1250,7 @@
* arch/arm/src/lpc313x/lpc313x_spi.c - Fix compilation error when
when CONFIG_DEBUG is enabled.
* arch/arm/src/lm3s and arch/arm/include/lm3s - Support for the
lm3s8962 contributed by Larry Arnold.
* configs/lm328962-ek - Support for the TI/Stellaris EKC-LM3S8962
board (also contributed by Larry Arnold).

9
Documentation/NuttX.html
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@ -8,7 +8,7 @@
<tr align="center" bgcolor="#e4e4e4">
<td>
<h1><big><font color="#3c34ec"><i>NuttX RTOS</i></font></big></h1>
<p>Last Updated: August 30, 2010</p>
<p>Last Updated: September 3, 2010</p>
</td>
</tr>
</table>
@ -1922,6 +1922,10 @@ nuttx-5.10 2010-xx-xx Gregory Nutt &lt;spudmonkey@racsa.co.cr&gt;
* arch/arm/src/lpc313x/lpc313x_spi.c - Fix compilation error when
when CONFIG_DEBUG is enabled.
* arch/arm/src/lm3s and arch/arm/include/lm3s - Support for the
lm3s8962 contributed by Larry Arnold.
* configs/lm328962-ek - Support for the TI/Stellaris EKC-LM3S8962
board (also contributed by Larry Arnold).
pascal-2.1 2010-xx-xx Gregory Nutt &lt;spudmonkey@racsa.co.cr&gt;
@ -1931,6 +1935,9 @@ buildroot-1.9 2010-xx-xx <spudmonkey@racsa.co.cr>
* configs/arm926t-defconfig-nxflat: NXFLAT-only configuration for
arm926
* toolchain/gdb/gdb.mk - Remove ncurses dependency from gdb_target target.
* toolchain/gdb/gdb.mk - Added --disable-werror to GDB configuration line.
GDB 6.8 won't build because the tarball was released with -Werror enabled and
the build stops on the first warning.
</pre></ul>

45
arch/arm/include/lm3s/irq.h
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@ -219,6 +219,51 @@
# define LM3S_IRQ_GPIOJ (70) /* Vector 70: GPIO Port J */
/* Vector 71: Reserved */
# define NR_IRQS (71) /* (Really less because of reserved vectors) */
#elif defined(CONFIG_ARCH_CHIP_LM3S8962)
# define LM3S_IRQ_GPIOA (16) /* Vector 16: GPIO Port A */
# define LM3S_IRQ_GPIOB (17) /* Vector 17: GPIO Port B */
# define LM3S_IRQ_GPIOC (18) /* Vector 18: GPIO Port C */
# define LM3S_IRQ_GPIOD (19) /* Vector 19: GPIO Port D */
# define LM3S_IRQ_GPIOE (20) /* Vector 20: GPIO Port E */
# define LM3S_IRQ_UART0 (21) /* Vector 21: UART 0 */
# define LM3S_IRQ_UART1 (22) /* Vector 22: UART 1 */
# define LM3S_IRQ_SSI0 (23) /* Vector 23: SSI 0 */
# define LM3S_IRQ_I2C0 (24) /* Vector 24: I2C 0 */
# define LM3S_IRQ_PWMFAULT (25) /* Vector 25: PWM Fault */
# define LM3S_IRQ_PWM0 (26) /* Vector 26: PWM Generator 0 */
# define LM3S_IRQ_PWM1 (27) /* Vector 27: PWM Generator 1 */
# define LM3S_IRQ_PWM2 (28) /* Vector 28: PWM Generator 2 */
# define LM3S_IRQ_QEI0 (29) /* Vector 29: QEI0 */
# define LM3S_IRQ_ADC0 (30) /* Vector 30: ADC Sequence 0 */
# define LM3S_IRQ_ADC1 (31) /* Vector 31: ADC Sequence 1 */
# define LM3S_IRQ_ADC2 (32) /* Vector 32: ADC Sequence 2 */
# define LM3S_IRQ_ADC3 (33) /* Vector 33: ADC Sequence 3 */
# define LM3S_IRQ_WDOG (34) /* Vector 34: Watchdog Timer */
# define LM3S_IRQ_TIMER0A (35) /* Vector 35: Timer 0 A */
# define LM3S_IRQ_TIMER0B (36) /* Vector 36: Timer 0 B */
# define LM3S_IRQ_TIMER1A (37) /* Vector 37: Timer 1 A */
# define LM3S_IRQ_TIMER1B (38) /* Vector 38: Timer 1 B */
# define LM3S_IRQ_TIMER2A (39) /* Vector 39: Timer 2 A */
# define LM3S_IRQ_TIMER2B (40) /* Vector 40: Timer 3 B */
# define LM3S_IRQ_COMPARE0 (41) /* Vector 41: Analog Comparator 0 */
/* Vector 42: Reserved */
/* Vector 43: Reserved */
# define LM3S_IRQ_SYSCON (44) /* Vector 44: System Control */
# define LM3S_IRQ_FLASHCON (45) /* Vector 45: FLASH Control */
# define LM3S_IRQ_GPIOF (46) /* Vector 46: GPIO Port F */
# define LM3S_IRQ_GPIOG (47) /* Vector 47: GPIO Port G */
/* Vector 48: Reserved */
/* Vector 49: Reserved */
/* Vector 50: Reserved */
# define LM3S_IRQ_TIMER3A (51) /* Vector 51: Timer 3 A */
# define LM3S_IRQ_TIMER3B (52) /* Vector 52: Timer 3 B */
# define LM3S_IRQ_I2C1 (53) /* Vector 53: I2C 1 */
# define LM3S_IRQ_QEI1 (54) /* Vector 54: QEI1 */
# define LM3S_IRQ_CAN0 (54) /* Vector 55: CAN0 */
/* Vectors 56-57: Reserved */
# define LM3S_IRQ_ETHCON (58) /* Vector 58: Ethernet Controller */
# define LM3S_IRQ_HIBERNATE (59) /* Vector 59: Hibernation Module */
/* Vectors 60-70: Reserved */
#else
# error "IRQ Numbers not specified for this LM3S chip"
#endif

11
arch/arm/src/lm3s/chip.h
View File

@ -82,6 +82,17 @@
# define LM3S_NPWM 4 /* Four PWM generator modules */
# define LM3S_NQEI 2 /* Two quadrature encoders */
# define LM3S_NPORTS 9 /* 9 Ports (GPIOA-H,J) 0-65 GPIOs */
#elif defined(CONFIG_ARCH_CHIP_LM3S8962)
# define LM3S_NTIMERS 4 /* Four general purpose timers */
# define LM3S_NETHCONTROLLERS 1 /* One Ethernet controller */
# define LM3S_NSSI 1 /* One SSI module */
# define LM3S_NUARTS 3 /* Two UART modules */
# define LM3S_NI2C 2 /* One I2C module */
# define LM3S_NADC 1 /* One ADC module */
# define LM2S_NPWM 3 /* Three PWM generator modules */
# define LM3S_NQEI 2 /* Two quadrature encoders */
# define LM3S_NPORTS 7 /* 7 Ports (GPIOA-G), 5-42 GPIOs */
# define LC3S_CANCONTROLLER 1 /* One CAN controller */
#else
# error "Capabilities not specified for this LM3S chip"
#endif

7
arch/arm/src/lm3s/lm3s_gpio.c
View File

@ -147,13 +147,13 @@ static const uint32_t g_gpiobase[LM3S_NPORTS] =
LM3S_GPIOA_BASE, LM3S_GPIOB_BASE, LM3S_GPIOC_BASE, LM3S_GPIOD_BASE,
LM3S_GPIOE_BASE, LM3S_GPIOF_BASE, LM3S_GPIOG_BASE,
/* GPIOH exists on the LM3S6918 and th LM3S6B96, but not on the LM3S6965 */
/* GPIOH exists on the LM3S6918 and th LM3S6B96, but not on the LM3S6965 or LM3S8962*/
#if LM3S_NPORTS > 7
LM3S_GPIOH_BASE,
#endif
/* GPIOJ exists on the LM3S6B96, but not on the LM3S6918 or LM3S6965 */
/* GPIOJ exists on the LM3S6B96, but not on the LM3S6918 or LM3S6965 or LM3S8962*/
#if LM3S_NPORTS > 8
LM3S_GPIOJ_BASE,
@ -850,4 +850,5 @@ bool lm3s_gpioread(uint32_t pinset, bool value)
*/
return (getreg32(base + LM3S_GPIO_DATA_OFFSET + (1 << (pinno + 2))) != 0);
}
}

43
arch/arm/src/lm3s/lm3s_internal.h
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@ -294,6 +294,49 @@
# define GPIO_ETHPHY_LED0 (GPIO_FUNC_PFOUTPUT | GPIO_PORTF | 3) /* PF3: LED0 */
# define GPIO_UART2_RX (GPIO_FUNC_PFINPUT | GPIO_PORTG | 0) /* PA0: UART 0 receive (UGRx) */
# define GPIO_UART2_TX (GPIO_FUNC_PFOUTPUT | GPIO_PORTG | 1) /* PA1: UART 0 transmit (UGTx) */
#elif defined(CONFIG_ARCH_CHIP_LM3S8962)
# define GPIO_UART0_RX (GPIO_FUNC_PFINPUT | GPIO_PORTA | 0) /* PA0: UART 0 receive (U0Rx) */
# define GPIO_UART0_TX (GPIO_FUNC_PFOUTPUT | GPIO_PORTA | 1) /* PA1: UART 0 transmit (U0Tx) */
# define GPIO_SSI0_CLK (GPIO_FUNC_PFIO | GPIO_PORTA | 2) /* PA2: SSI0 clock (SSI0Clk) */
# define GPIO_SSI0_FSS (GPIO_FUNC_PFIO | GPIO_PORTA | 3) /* PA3: SSI0 frame (SSI0Fss) */
# define GPIO_SSI0_RX (GPIO_FUNC_PFINPUT | GPIO_PORTA | 4) /* PA4: SSI0 receive (SSI0Rx) */
# define GPIO_SSI0_TX (GPIO_FUNC_PFOUTPUT | GPIO_PORTA | 5) /* PA5: SSI0 transmit (SSI0Tx) */
# define GPIO_TMR1_CCP (GPIO_FUNC_PFIO | GPIO_PORTA | 6) /* PA6: Capture/Compare/PWM0 (CCP1) */
# define GPIO_PWM1_2 (GPIO_FUNC_PFOUTPUT | GPIO_PORTB | 0) /* PB0: PWM Generator 1, PWM2 */
# define GPIO_PWM1_3 (GPIO_FUNC_PFOUTPUT | GPIO_PORTB | 1) /* PB1: PWM Generator 1, PWM3 */
# define GPIO_I2C0_SCL (GPIO_FUNC_PFOUTPUT | GPIO_PORTB | 2) /* PB2: I2C0 clock (I2C0SCL) */
# define GPIO_I2C0_SDA (GPIO_FUNC_PFODIO | GPIO_PORTB | 3) /* PB3: I2C0 data (I2C0SDA) */
# define GPIO_CMP0_NIN (GPIO_FUNC_PFINPUT | GPIO_PORTB | 4) /* PB4: Analog comparator 0 negative input (C0-) */
# define GPIO_CMP0_OUT (GPIO_FUNC_PFOUTPUT | GPIO_PORTB | 5) /* PB5: Analog comparator 0 output (C0o) ( differs) */
# define GPIO_CMP0_PIN (GPIO_FUNC_PFINPUT | GPIO_PORTB | 6) /* PB6: Analog comparator 0 positive input (C0+) */
# define GPIO_JTAG_TRST (GPIO_FUNC_PFINPUT | GPIO_PORTB | 7) /* PB7: JTAG ~TRST */
# define GPIO_JTAG_TCK (GPIO_FUNC_PFINPUT | GPIO_PORTC | 0) /* PC0: JTAG/SWD CLK */
# define GPIO_JTAG_SWCLK (GPIO_FUNC_PFINPUT | GPIO_PORTC | 0) /* PC0: JTAG/SWD CLK */
# define GPIO_JTAG_TMS (GPIO_FUNC_PFIO | GPIO_PORTC | 1) /* PC1: JTAG TMS */
# define GPIO_JTAG_SWDIO (GPIO_FUNC_PFIO | GPIO_PORTC | 1) /* PC1: JTAG SWDIO */
# define GPIO_JTAG_TDI (GPIO_FUNC_PFINPUT | GPIO_PORTC | 2) /* PC2: JTAG TDI */
# define GPIO_JTAG_TDO (GPIO_FUNC_PFOUTPUT | GPIO_PORTC | 3) /* PC3: JTAG TDO */
# define GPIO_JTAG_SWO (GPIO_FUNC_PFOUTPUT | GPIO_PORTC | 3) /* PC3: JTAG SWO */
# define GPIO_QEI0_PHA (GPIO_FUNC_PFINPUT | GPIO_PORTC | 4) /* PC4: QEI module 0 phase A. */
# define GPIO_QEI0_PHB (GPIO_FUNC_PFINPUT | GPIO_PORTC | 6) /* PC6: QEI module 0 phase B. */
# define GPIO_CAN0_RX (GPIO_FUNC_PFINPUT | GPIO_PORTD | 0) /* PD0: CAN module RX */
# define GPIO_CAN0_TX (GPIO_FUNC_PFOUTPUT | GPIO_PORTD | 1) /* PD1: CAN module TX */
# define GPIO_UART1_RX (GPIO_FUNC_PFINPUT | GPIO_PORTD | 2) /* PD2: UART 1 receive (U1Rx) */
# define GPIO_UART1_TX (GPIO_FUNC_PFOUTPUT | GPIO_PORTD | 3) /* PD3: UART 1 transmit (U1Tx) */
# define GPIO_TMR0_CCP (GPIO_FUNC_PFIO | GPIO_PORTD | 4) /* PD4: Capture/Compare/PWM0 (CCP0) */
# define GPIO_PWM_FAULT (GPIO_FUNC_PFINPUT | GPIO_PORTD | 6) /* PD6: PWM Fault */
# define GPIO_QEI0_IDX (GPIO_FUNC_PFIO | GPIO_PORTD | 7) /* PC7: /* PD0: QEI module 0 index. ) */
# define GPIO_PWM2_4 (GPIO_FUNC_PFOUTPUT | GPIO_PORTE | 0) /* PE0: PWM Generator 2, PWM4 */
# define GPIO_PWM2_5 (GPIO_FUNC_PFOUTPUT | GPIO_PORTE | 1) /* PE1: PWM Generator 1, PWM5 */
# define GPIO_QEI1_PHB (GPIO_FUNC_PFINPUT | GPIO_PORTE | 2) /* PE2: QEI module 1 phase B. */
# define GPIO_QEI1_PHA (GPIO_FUNC_PFINPUT | GPIO_PORTE | 3) /* PE3: QEI module 1 phase A. */
# define GPIO_PWM0_0 (GPIO_FUNC_PFOUTPUT | GPIO_PORTF | 0) /* PF0: PWM Generator 0, PWM0 */
# define GPIO_QEI1_IDX (GPIO_FUNC_PFINPUT | GPIO_PORTE | 1) /* PF1: QEI module 1 index. ) */
# define GPIO_ETHPHY_LED1 (GPIO_FUNC_PFOUTPUT | GPIO_PORTF | 2) /* PF2: LED1 */
# define GPIO_ETHPHY_LED0 (GPIO_FUNC_PFOUTPUT | GPIO_PORTF | 3) /* PF3: LED0 */
# define GPIO_PWM0_1 (GPIO_FUNC_PFOUTPUT | GPIO_PORTG | 1) /* PG1:PWM Generator 0, PWM1 */
#else
# error "Unknown LM3S chip"
#endif

2
arch/arm/src/lm3s/lm3s_ssi.c
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@ -77,7 +77,7 @@
#endif
/* How many SSI modules does this chip support? The LM3S6918 supports 2 SSI
* modules, the LM3S6965 supports 1 module (others may support more than 2-- in
* modules, the LM3S6965 and LM3S8962 support 1 module (others may support more than 2-- in
* such case, the following must be expanded).
*/

95
arch/arm/src/lm3s/lm3s_vectors.S
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@ -296,6 +296,62 @@ lm3s_vectors:
.word lm3s_epi /* Vector 69: Reserved */
.word lm3s_gpioj /* Vector 70: GPIO J */
.word lm3s_reserved /* Vector 71: Reserved */
#elif defined(CONFIG_ARCH_CHIP_LM3S8962)
.word lm3s_gpioa /* Vector 16: GPIO Port A */
.word lm3s_gpiob /* Vector 17: GPIO Port B */
.word lm3s_gpioc /* Vector 18: GPIO Port C */
.word lm3s_gpiod /* Vector 19: GPIO Port D */
.word lm3s_gpioe /* Vector 20: GPIO Port E */
.word lm3s_uart0 /* Vector 21: UART 0 */
.word lm3s_uart1 /* Vector 22: UART 1 */
.word lm3s_ssi0 /* Vector 23: SSI 0 */
.word lm3s_i2c0 /* Vector 24: I2C 0 */
.word lm3s_pwmfault /* Vector 25: PWM Fault */
.word lm3s_pwm0 /* Vector 26: PWM Generator 0 */
.word lm3s_pwm1 /* Vector 27: PWM Generator 1 */
.word lm3s_pwm2 /* Vector 28: PWM Generator 2 */
.word lm3s_qei0 /* Vector 29: QEI0 */
.word lm3s_adc0 /* Vector 30: ADC Sequence 0 */
.word lm3s_adc1 /* Vector 31: ADC Sequence 1 */
.word lm3s_adc2 /* Vector 32: ADC Sequence 2 */
.word lm3s_adc3 /* Vector 33: ADC Sequence 3 */
.word lm3s_wdog /* Vector 34: Watchdog Timer */
.word lm3s_tmr0a /* Vector 35: Timer 0 A */
.word lm3s_tmr0b /* Vector 36: Timer 0 B */
.word lm3s_tmr1a /* Vector 37: Timer 1 A */
.word lm3s_tmr1b /* Vector 38: Timer 1 B */
.word lm3s_tmr2a /* Vector 39: Timer 2 A */
.word lm3s_tmr2b /* Vector 40: Timer 3 B */
.word lm3s_cmp0 /* Vector 41: Analog Comparator 0 */
.word lm3s_reserved /* Vector 42: Reserved */
.word lm3s_reserved /* Vector 43: Reserved */
.word lm3s_syscon /* Vector 44: System Control */
.word lm3s_flashcon /* Vector 45: FLASH Control */
.word lm3s_gpiof /* Vector 46: GPIO Port F */
.word lm3s_gpiog /* Vector 47: GPIO Port G */
.word lm3s_reserved /* Vector 48: Reserved */
.word lm3s_reserved /* Vector 49: Reserved */
.word lm3s_reserved /* Vector 50: Reserved */
.word lm3s_tmr3a /* Vector 51: Timer 3 A */
.word lm3s_tmr3b /* Vector 52: Timer 3 B */
.word lm3s_reserved /* Vector 53: Reserved*/
.word lm3s_qei1 /* Vector 54: QEI1 */
.word lm3s_can0 /* Vector 55: Can Controller */
.word lm3s_reserved /* Vector 56: Reserved */
.word lm3s_reserved /* Vector 57: Reserved */
.word lm3s_eth /* Vector 58: Ethernet Controller */
.word lm3s_hib /* Vector 59: Hibernation Module */
.word lm3s_reserved /* Vector 60: Reserved */
.word lm3s_reserved /* Vector 61: Reserved */
.word lm3s_reserved /* Vector 62: Reserved */
.word lm3s_reserved /* Vector 63: Reserved */
.word lm3s_reserved /* Vector 64: Reserved */
.word lm3s_reserved /* Vector 65: Reserved */
.word lm3s_reserved /* Vector 66: Reserved */
.word lm3s_reserved /* Vector 67: Reserved */
.word lm3s_reserved /* Vector 68: Reserved */
.word lm3s_reserved /* Vector 69: Reserved */
.word lm3s_reserved /* Vector 70: Reserved */
#else
# error "Vectors not specified for this LM3S chip"
#endif
@ -393,6 +449,45 @@ handlers:
HANDLER lm3s_qei1, LM3S_IRQ_QEI1 /* Vector 54: QEI 1 */
HANDLER lm3s_eth, LM3S_IRQ_ETHCON /* Vector 58: Ethernet Controller */
HANDLER lm3s_hib, LM3S_IRQ_HIBERNATE /* Vector 59: Hibernation Module */
#elif defined(CONFIG_ARCH_CHIP_LM3S8962)
HANDLER lm3s_gpioa, LM3S_IRQ_GPIOA /* Vector 16: GPIO Port A */
HANDLER lm3s_gpiob, LM3S_IRQ_GPIOB /* Vector 17: GPIO Port B */
HANDLER lm3s_gpioc, LM3S_IRQ_GPIOC /* Vector 18: GPIO Port C */
HANDLER lm3s_gpiod, LM3S_IRQ_GPIOD /* Vector 19: GPIO Port D */
HANDLER lm3s_gpioe, LM3S_IRQ_GPIOE /* Vector 20: GPIO Port E */
HANDLER lm3s_uart0, LM3S_IRQ_UART0 /* Vector 21: UART 0 */
HANDLER lm3s_uart1, LM3S_IRQ_UART1 /* Vector 22: UART 1 */
HANDLER lm3s_ssi0, LM3S_IRQ_SSI0 /* Vector 23: SSI 0 */
HANDLER lm3s_i2c0, LM3S_IRQ_I2C0 /* Vector 24: I2C 0 */
HANDLER lm3s_pwmfault, LM3S_IRQ_PWMFAULT /* Vector 25: PWM Fault */
HANDLER lm3s_pwm0, LM3S_IRQ_PWM0 /* Vector 26: PWM Generator 0 */
HANDLER lm3s_pwm1, LM3S_IRQ_PWM1 /* Vector 27: PWM Generator 1 */
HANDLER lm3s_pwm2, LM3S_IRQ_PWM2 /* Vector 28: PWM Generator 2 */
HANDLER lm3s_qei0, LM3S_IRQ_QEI0 /* Vector 29: QEI 0 */
HANDLER lm3s_adc0, LM3S_IRQ_ADC0 /* Vector 30: ADC Sequence 0 */
HANDLER lm3s_adc1, LM3S_IRQ_ADC1 /* Vector 31: ADC Sequence 1 */
HANDLER lm3s_adc2, LM3S_IRQ_ADC2 /* Vector 32: ADC Sequence 2 */
HANDLER lm3s_adc3, LM3S_IRQ_ADC3 /* Vector 33: ADC Sequence 3 */
HANDLER lm3s_wdog, LM3S_IRQ_WDOG /* Vector 34: Watchdog Timer */
HANDLER lm3s_tmr0a, LM3S_IRQ_TIMER0A /* Vector 35: Timer 0 A */
HANDLER lm3s_tmr0b, LM3S_IRQ_TIMER0B /* Vector 36: Timer 0 B */
HANDLER lm3s_tmr1a, LM3S_IRQ_TIMER1A /* Vector 37: Timer 1 A */
HANDLER lm3s_tmr1b, LM3S_IRQ_TIMER1B /* Vector 38: Timer 1 B */
HANDLER lm3s_tmr2a, LM3S_IRQ_TIMER2A /* Vector 39: Timer 2 A */
HANDLER lm3s_tmr2b, LM3S_IRQ_TIMER2B /* Vector 40: Timer 3 B */
HANDLER lm3s_cmp0, LM3S_IRQ_COMPARE0 /* Vector 41: Analog Comparator 0 */
HANDLER lm3s_cmp1, LM3S_IRQ_COMPARE1 /* Vector 42: Analog Comparator 1 */
HANDLER lm3s_syscon, LM3S_IRQ_SYSCON /* Vector 44: System Control */
HANDLER lm3s_flashcon, LM3S_IRQ_FLASHCON /* Vector 45: FLASH Control */
HANDLER lm3s_gpiof, LM3S_IRQ_GPIOF /* Vector 46: GPIO Port F */
HANDLER lm3s_gpiog, LM3S_IRQ_GPIOG /* Vector 47: GPIO Port G */
HANDLER lm3s_uart2, LM3S_IRQ_UART1 /* Vector 49: UART 1 */
HANDLER lm3s_tmr3a, LM3S_IRQ_TIMER3A /* Vector 51: Timer 3 A */
HANDLER lm3s_tmr3b, LM3S_IRQ_TIMER3B /* Vector 52: Timer 3 B */
HANDLER lm3s_i2c1, LM3S_IRQ_I2C1 /* Vector 53: I2C 1 */
HANDLER lm3s_qei1, LM3S_IRQ_QEI1 /* Vector 54: QEI 1 */
HANDLER lm3s_eth, LM3S_IRQ_ETHCON /* Vector 58: Ethernet Controller */
HANDLER lm3s_hib, LM3S_IRQ_HIBERNATE /* Vector 59: Hibernation Module */
#elif defined(CONFIG_ARCH_CHIP_LM3S9B96)
HANDLER lm3s_gpioa, LM3S_IRQ_GPIOA /* Vector 16: GPIO Port A */
HANDLER lm3s_gpiob, LM3S_IRQ_GPIOB /* Vector 17: GPIO Port B */