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arch/risc-v: re-add missing riscv_udelay source

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This was broken with: 9d9d591b93
This commit is contained in:
Richard Tucker 2022-06-03 11:10:57 +10:00 committed by Xiang Xiao
parent e8ac5c44f4
commit 85af65e72e
1 changed files with 7 additions and 1 deletions
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8
arch/risc-v/src/common/Make.defs
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@ -29,7 +29,7 @@ CMN_ASRCS += riscv_vectors.S riscv_exception_common.S riscv_mhartid.S
CMN_CSRCS += riscv_initialize.c riscv_swint.c riscv_mtimer.c
CMN_CSRCS += riscv_allocateheap.c riscv_createstack.c riscv_exit.c
CMN_CSRCS += riscv_assert.c riscv_blocktask.c riscv_copystate.c riscv_initialstate.c
CMN_CSRCS += riscv_modifyreg32.c riscv_mdelay.c riscv_puts.c
CMN_CSRCS += riscv_modifyreg32.c riscv_puts.c
CMN_CSRCS += riscv_releasepending.c riscv_reprioritizertr.c
CMN_CSRCS += riscv_releasestack.c riscv_stackframe.c riscv_schedulesigaction.c
CMN_CSRCS += riscv_sigdeliver.c riscv_unblocktask.c riscv_usestack.c
@ -37,6 +37,12 @@ CMN_CSRCS += riscv_idle.c riscv_tcbinfo.c riscv_cpuidlestack.c
CMN_CSRCS += riscv_exception.c riscv_getnewintctx.c riscv_doirq.c
CMN_CSRCS += riscv_saveusercontext.c
ifneq ($(CONFIG_ALARM_ARCH),y)
ifneq ($(CONFIG_TIMER_ARCH),y)
CMN_CSRCS += riscv_mdelay.c riscv_udelay.c
endif
endif
ifeq ($(CONFIG_SMP),y)
CMN_CSRCS += riscv_cpuindex.c riscv_cpupause.c riscv_cpustart.c
endif