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Typo fixes.

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This commit is contained in:
Fotis Panagiotopoulos 2023-02-17 13:26:18 +02:00 committed by Alan Carvalho de Assis
parent 70ce4b4fc1
commit 85ceb7920e
60 changed files with 91 additions and 91 deletions
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2
Documentation/components/binfmt.rst
View File

@ -56,7 +56,7 @@ Header Files
The interface to the binary loader is described in the header file
``include/nuttx/binfmt/binfmt.h``.
A brief summary of the data structurs and interfaces prototyped in that
A brief summary of the data structures and interfaces prototyped in that
header file are listed below.
Data Structures

2
arch/arm/src/am335x/am335x_serial.c
View File

@ -553,7 +553,7 @@ static inline void up_enablebreaks(struct up_dev_s *priv, bool enable)
/****************************************************************************
* Name: am335x_uart0config, uart1config, uart2config, ..., uart5config
*
* Descrption:
* Description:
* Configure the UART
*
****************************************************************************/

2
arch/arm/src/armv7-a/arm_gicv2.c
View File

@ -219,7 +219,7 @@ void arm_gic_initialize(void)
*
* NOTE: Only for processors that operate in both secure and non-secure
* state.
* REVISIT: This is here only for superstituous reasons. I don't think
* REVISIT: This is here only for superstitious reasons. I don't think
* I need this setting in this configuration.
*/

2
arch/arm/src/common/arm_backtrace_sp.c
View File

@ -170,7 +170,7 @@ static int backtrace_branch(unsigned long top, unsigned long sp,
* The up call up_backtrace_init_code_regions() will set the start
* and end addresses of the customized program sections, this method
* will help the different boards to configure the current text
* sections for some complicate platfroms
* sections for some complicate platforms
*
* Input Parameters:
* regions The start and end address of the text segment

2
arch/arm/src/lpc17xx_40xx/lpc17_40_pwm.h
View File

@ -81,7 +81,7 @@
LPC17_40_PWM1_CHANNEL6)
#if CONFIG_PWM_NCHANNELS > LPC17_40_PWM1_NCHANNELS
# error "PWM subystem has more channels then physical channels enabled"
# error "PWM subsystem has more channels then physical channels enabled"
#endif
/****************************************************************************

4
arch/arm/src/lpc214x/lpc214x_i2c.h
View File

@ -83,13 +83,13 @@
# define I2C_STAT_MXSLAWNAK (4 << I2C_STAT_SHIFT) /* SLA+W transmitted + NAK received */
# define I2C_STAT_MXDATAACK (5 << I2C_STAT_SHIFT) /* Data transmitted + ACK received */
# define I2C_STAT_MXDATANAK (6 << I2C_STAT_SHIFT) /* Data transmitted + NAK received */
# define I2C_STAT_MXARBLOST (7 << I2C_STAT_SHIFT) /* Abritration lost in SLA+W or data */
# define I2C_STAT_MXARBLOST (7 << I2C_STAT_SHIFT) /* Arbitration lost in SLA+W or data */
/* Master receive mode */
# define I2C_STAT_MRSTART (0 << I2C_STAT_SHIFT) /* Start transmitted */
# define I2C_STAT_MRRSTART (2 << I2C_STAT_SHIFT) /* Repeated start transmitted */
# define I2C_STAT_MRARBLOST (7 << I2C_STAT_SHIFT) /* Abritration lost in NAK bit */
# define I2C_STAT_MRARBLOST (7 << I2C_STAT_SHIFT) /* Arbitration lost in NAK bit */
# define I2C_STAT_MRSLARACK (8 << I2C_STAT_SHIFT) /* SLA+R transmitted + ACK received */
# define I2C_STAT_MRSLARNAK (9 << I2C_STAT_SHIFT) /* SLA+R transmitted + NAK received */
# define I2C_STAT_MRDATAACK (10 << I2C_STAT_SHIFT) /* Data received + send ACK */

6
arch/arm/src/phy62xx/ble/ble_controller.h
View File

@ -18,8 +18,8 @@
*
****************************************************************************/
#ifndef _BLE_CONROLLER_H_
#define _BLE_CONROLLER_H_
#ifndef _BLE_CONTROLLER_H_
#define _BLE_CONTROLLER_H_
/****************************************************************************
* Included Files
@ -423,7 +423,7 @@ typedef struct
uint32_t accessAddr; /* saved synchronization word to be used by Slave */
uint32_t initCRC; /* connection CRC initialization value (24 bits) */
uint8_t sleepClkAccuracy; /* peer's sleep clock accurracy; used by own device to determine timer drift */
uint8_t sleepClkAccuracy; /* peer's sleep clock accuracy; used by own device to determine timer drift */
connParam_t curParam;
/* current connection parameters */

2
arch/arm/src/rtl8720c/amebaz_coex.c
View File

@ -97,7 +97,7 @@ void bt_coex_handle_cmd_complete_evt(uint16_t opcode, uint16_t cause,
total_len--;
if (total_len <= 1)
{
printf("bt_coex_handle_cmd_complete_evt: not reprot to wifi");
printf("bt_coex_handle_cmd_complete_evt: not report to wifi");
return ;
}

2
arch/arm/src/s32k1xx/s32k1xx_lpi2c_slave.c
View File

@ -883,7 +883,7 @@ struct i2c_slave_s *s32k1xx_i2cbus_slave_initialize(int port)
*
* Description:
* Decrease the reference counter of the I2C slave device. When there are
* no more references left the I2C slave device is unitialized.
* no more references left the I2C slave device is uninitialized.
*
* Input Parameters:
* dev - Device structure as returned by s32k1xx_i2cbus_slave_initialize().

2
arch/arm/src/s32k1xx/s32k1xx_lpi2c_slave.h
View File

@ -68,7 +68,7 @@ struct i2c_slave_s *s32k1xx_i2cbus_slave_initialize(int port);
*
* Description:
* Decrease the reference counter of the I2C slave device. When there are
* no more references left the I2C slave device is unitialized.
* no more references left the I2C slave device is uninitialized.
*
* Input Parameters:
* dev - Device structure as returned by s32k1xx_i2cbus_slave_initialize().

2
arch/arm/src/s32k1xx/s32k1xx_serial.c
View File

@ -814,7 +814,7 @@ static int s32k1xx_dma_setup(struct uart_dev_s *dev)
modifyreg32(priv->uartbase + S32K1XX_LPUART_BAUD_OFFSET,
0, LPUART_BAUD_RDMAE);
/* Enable itnerrupt on Idel and erros */
/* Enable itnerrupt on Idel and errors */
modifyreg32(priv->uartbase + S32K1XX_LPUART_CTRL_OFFSET, 0,
LPUART_CTRL_PEIE |

8
arch/arm/src/s32k3xx/hardware/s32k3xx_mc_rgm.h
View File

@ -45,7 +45,7 @@
#define S32K3XX_MC_RGM_ERCTRL_OFFSET (0x20) /* External Reset Control Register (ERCTRL) */
#define S32K3XX_MC_RGM_RDSS_OFFSET (0x24) /* Reset During Standby Status Register (RDSS) */
#define S32K3XX_MC_RGM_FRENTC_OFFSET (0x28) /* Functional Reset Entry Timeout Control Register (FRENTC) */
#define S32K3XX_MC_RGM_LPDEBUG_OFFSET (0x2c) /* Low Power Debug Control Reguster (LPDEBUG) */
#define S32K3XX_MC_RGM_LPDEBUG_OFFSET (0x2c) /* Low Power Debug Control Register (LPDEBUG) */
/* MC_RGM Register Addresses ************************************************/
@ -165,8 +165,8 @@
/* Reset During Standby Status Register (RDSS) */
#define MC_RGM_RDSS_DES_RES (1 << 0) /* Bit 0: Destructive reset event occured during standby mode (DES_RES) */
#define MC_RGM_RDSS_FES_RES (1 << 1) /* Bit 1: Functional reset event occured during standby mode (FES_RES) */
#define MC_RGM_RDSS_DES_RES (1 << 0) /* Bit 0: Destructive reset event occurred during standby mode (DES_RES) */
#define MC_RGM_RDSS_FES_RES (1 << 1) /* Bit 1: Functional reset event occurred during standby mode (FES_RES) */
/* Bits 2-31: Reserved */
/* Functional Reset Entry Timeout Control Register (FRENTC) */
@ -175,7 +175,7 @@
#define MC_RGM_FRENTC_FRET_TIMEOUT_SHIFT (1) /* Bits 1-31: Functional Reset Entry Timer Value (FRET_TIMEOUT) */
#define MC_RGM_FRENTC_FRET_TIMEOUT_MASK (0x7fffffff << MC_RGM_FRENTC_FRET_TIMEOUT_SHIFT)
/* Low Power Debug Control Reguster (LPDEBUG) */
/* Low Power Debug Control Register (LPDEBUG) */
#define MC_RGM_LPDEBUG_LP_DBG_EN (1 << 0) /* Bit 0: Low-Power Debug Enable (LP_DBG_EN) */
/* Bits 1-31: Reserved */

2
arch/arm/src/tlsr82/tc32/tc32_switchcontext.S
View File

@ -123,7 +123,7 @@ tc32_switchcontext:
tmov r3, r13
tstorer r3, [r0]
/* r0 = r1 = next task tcb->regs (actualy sp) */
/* r0 = r1 = next task tcb->regs (actually sp) */
tmov r0, r1

2
arch/arm/src/xmc4/xmc4_clockconfig.c
View File

@ -66,7 +66,7 @@
* Pre-processor Definitions
****************************************************************************/
/* Oscilator reference frequency */
/* Oscillator reference frequency */
#define FOSCREF (2500000U)

2
arch/arm64/src/a64/hardware/a64_twi.h
View File

@ -186,7 +186,7 @@
#define TWI_STAT_TX_SAW_ACK (0xd0) /* Second Address byte+Write bit transmitted,ACK received */
#define TWI_STAT_TX_SAW_NAK (0xd8) /* Second Address byte+Write bit transmitted,ACK not received */
#define TWI_STAT_IDLE (0xf8) /* No relevant status infomation,INT_FLAG = 0 */
#define TWI_STAT_IDLE (0xf8) /* No relevant status information,INT_FLAG = 0 */
/****************************************************************************
* Public Types

2
arch/arm64/src/common/arm64_gicv2.c
View File

@ -927,7 +927,7 @@ static void arm_gic_initialize(void)
*
* NOTE: Only for processors that operate in both secure and non-secure
* state.
* REVISIT: This is here only for superstituous reasons. I don't think
* REVISIT: This is here only for superstitious reasons. I don't think
* I need this setting in this configuration.
*/

2
arch/ceva/src/xc5/xc5_initialstate.c
View File

@ -43,7 +43,7 @@
* has been created. This function is called to initialize
* the processor specific portions of the new TCB.
*
* This function must setup the intial architecture registers
* This function must setup the initial architecture registers
* and/or stack so that execution will begin at tcb->start
* on the next context switch.
*

2
arch/ceva/src/xc5/xc5_psu.c
View File

@ -32,7 +32,7 @@
* Pre-processor Definitions
****************************************************************************/
/* disable psu function temporily */
/* disable psu function temporarily */
#define CONFIG_XC5_PSU_ENABLE

2
arch/ceva/src/xm6/xm6_initialstate.c
View File

@ -49,7 +49,7 @@
* has been created. This function is called to initialize
* the processor specific portions of the new TCB.
*
* This function must setup the intial architecture registers
* This function must setup the initial architecture registers
* and/or stack so that execution will begin at tcb->start
* on the next context switch.
*

2
arch/ceva/src/xm6/xm6_psu.c
View File

@ -32,7 +32,7 @@
* Pre-processor Definitions
****************************************************************************/
/* disable psu function temporily */
/* disable psu function temporarily */
#define CEVAXM6_PSU_ENABLE 0

6
arch/risc-v/src/bl602/bl602_dma.c
View File

@ -269,7 +269,7 @@ int bl602_dma_channel_start(uint8_t channel_id)
/* Unmask interrupts for:
* - DMA_INT_TCOMPLETED
* - DMA_INT_ERR
* Note it is expected that the TC interupt to be enabled prior to this
* Note it is expected that the TC interrupt to be enabled prior to this
* function call if needed as it is nominally controlled via the LLI
* mechanism.
*/
@ -333,7 +333,7 @@ int bl602_dma_channel_stop(uint8_t channel_id)
* Name: riscv_dma_initialize
*
* Description:
* Intialize DMA controller.
* Initialize DMA controller.
*
* Input Parameters:
* None
@ -370,7 +370,7 @@ void weak_function riscv_dma_initialize(void)
putreg32(0, BL602_DMA_CH_N_REG(BL602_DMA_CONFIG_OFFSET, ch));
}
/* Attach DMA tranfer complete interrupt handler */
/* Attach DMA transfer complete interrupt handler */
irq_attach(BL602_IRQ_DMA_ALL, bl602_dma_int_handler, NULL);
up_enable_irq(BL602_IRQ_DMA_ALL);

2
arch/risc-v/src/bl602/bl602_dma.h
View File

@ -213,7 +213,7 @@ int bl602_dma_channel_stop(uint8_t channel_id);
* Name: bl602_dma_init
*
* Description:
* Intialize DMA controller.
* Initialize DMA controller.
*
* Input Parameters:
* None

8
arch/risc-v/src/bl602/bl602_head.S
View File

@ -58,16 +58,16 @@ bl602_start:
la a0, __boot2_pt_addr_src
la a1, __boot2_pt_addr_start
la a2, __boot2_pt_addr_end
bgeu a1, a2, bl602_entry_load_boot2_partiton_address_end
bgeu a1, a2, bl602_entry_load_boot2_partition_address_end
bl602_entry_load_boot2_partiton_address_loop:
bl602_entry_load_boot2_partition_address_loop:
lw t0, (a0)
sw t0, (a1)
addi a0, a0, 4
addi a1, a1, 4
bltu a1, a2, bl602_entry_load_boot2_partiton_address_loop
bltu a1, a2, bl602_entry_load_boot2_partition_address_loop
bl602_entry_load_boot2_partiton_address_end:
bl602_entry_load_boot2_partition_address_end:
/* Load boot2 flashCfg address */

6
arch/risc-v/src/bl602/bl602_rtc.h
View File

@ -89,9 +89,9 @@ void bl602_hbn_clear_rtc_int(void);
*
* Input Parameters:
* delay: RTC interrupt delay 32 clocks
* compval_low: RTC interrupt commpare value low 32 bits
* compval_high: RTC interrupt commpare value high 32 bits
* comp_mode: RTC interrupt commpare
* compval_low: RTC interrupt compare value low 32 bits
* compval_high: RTC interrupt compare value high 32 bits
* comp_mode: RTC interrupt compare
*
* Returned Value:
* None.

2
arch/sparc/src/bm3803/bm3803_exceptions.S
View File

@ -47,7 +47,7 @@
* l3 = trap type
*
* NOTE: By an executive defined convention, trap type is between 0 and 255 if
* it is an asynchonous trap and 256 and 511 if it is synchronous.
* it is an asynchronous trap and 256 and 511 if it is synchronous.
*/
.align 4

6
arch/sparc/src/bm3803/bm3803_head.S
View File

@ -29,7 +29,7 @@
#define RTRAP(_vector, _handler) mov %g0, %l0 ; sethi %hi(_handler), %l4 ; jmp %l4+%lo(_handler); mov _vector, %l3
#define TRAP(_vector, _handler) mov %psr, %l0; sethi %hi(_handler), %l4 ; jmp %l4+%lo(_handler); mov _vector, %l3
/* Unexcpected trap will halt the processor by forcing it to error state */
/* Unexpected trap will halt the processor by forcing it to error state */
#define BAD_TRAP ta 0; nop; nop; nop;
#define SOFT_TRAP BAD_TRAP /* Software trap. Treat as BAD_TRAP */
@ -87,7 +87,7 @@ _hardreset:
RTRAP(0,__start); ! 00 reset trap
BAD_TRAP; ! 01 instruction_access_exception
BAD_TRAP; ! 02 illegal_instruction
BAD_TRAP; ! 03 priveleged_instruction
BAD_TRAP; ! 03 privileged_instruction
TRAP(4,_fpdis_enable); ! 04 fp_disabled
WOTRAP(5,_window_overflow); ! 05 window_overflow
WUTRAP(6,_window_underflow); ! 06 window_underflow
@ -312,7 +312,7 @@ __start:
ldd [%g1], %f30
nop
! initial cache controler
! initial cache controller
set BM3803_REG, %g1
set 0x81000f,%g2 !open dcache,icache, dcache snoop,icache burst
! set 0x80000f,%g2 !open dcache,icache, dcache snoop

2
arch/sparc/src/bm3803/bm3803_oneshot_lowerhalf.c
View File

@ -148,7 +148,7 @@ static void bm3803_oneshot_handler(void *arg)
* lower An instance of the lower-half oneshot state structure. This
* structure must have been previously initialized via a call to
* oneshot_initialize();
* ts The location in which to return the maxumum delay.
* ts The location in which to return the maximum delay.
*
* Returned Value:
* Zero (OK) is returned on success; a negated errno value is returned

2
arch/sparc/src/bm3823/bm3823_exceptions.S
View File

@ -47,7 +47,7 @@
* l3 = trap type
*
* NOTE: By an executive defined convention, trap type is between 0 and 255 if
* it is an asynchonous trap and 256 and 511 if it is synchronous.
* it is an asynchronous trap and 256 and 511 if it is synchronous.
*/
.align 4

6
arch/sparc/src/bm3823/bm3823_head.S
View File

@ -29,7 +29,7 @@
#define RTRAP(_vector, _handler) mov %g0, %l0 ; sethi %hi(_handler), %l4 ; jmp %l4+%lo(_handler); mov _vector, %l3
#define TRAP(_vector, _handler) mov %psr, %l0; sethi %hi(_handler), %l4 ; jmp %l4+%lo(_handler); mov _vector, %l3
/* Unexcpected trap will halt the processor by forcing it to error state */
/* Unexpected trap will halt the processor by forcing it to error state */
#define BAD_TRAP ta 0; nop; nop; nop;
#define SOFT_TRAP BAD_TRAP /* Software trap. Treat as BAD_TRAP */
@ -87,7 +87,7 @@ _hardreset:
RTRAP(0,__start); ! 00 reset trap
BAD_TRAP; ! 01 instruction_access_exception
BAD_TRAP; ! 02 illegal_instruction
BAD_TRAP; ! 03 priveleged_instruction
BAD_TRAP; ! 03 privileged_instruction
TRAP(4,_fpdis_enable); ! 04 fp_disabled
WOTRAP(5,_window_overflow); ! 05 window_overflow
WUTRAP(6,_window_underflow); ! 06 window_underflow
@ -313,7 +313,7 @@ __start:
ldd [%g1], %f30
nop
! initial cache controler
! initial cache controller
set EXTER_REG, %g1
set 0x81000f,%g2 !open dcache,icache, dcache snoop,icache burst
! set 0x80000f,%g2 !open dcache,icache, dcache snoop

8
arch/x86_64/include/intel64/arch.h
View File

@ -48,7 +48,7 @@
/* Bit 1: Reserved */
#define X86_64_RFLAGS_PF (1 << 2) /* Bit 2: Parity Flag */
/* Bit 3: Reserved */
#define X86_64_RFLAGS_AF (1 << 4) /* Bit 4: Auxillary carry Flag */
#define X86_64_RFLAGS_AF (1 << 4) /* Bit 4: Auxiliary carry Flag */
/* Bit 5: Reserved */
#define X86_64_RFLAGS_ZF (1 << 6) /* Bit 6: Zero Flag */
#define X86_64_RFLAGS_SF (1 << 7) /* Bit 7: Sign Flag */
@ -295,11 +295,11 @@ begin_packed_struct struct gdt_entry_s
{
uint16_t limit_low; /* Lower 16-bits of segment limit */
uint32_t base_low:24; /* Lower 24-bits of base address */
uint8_t AC:1; /* 1: CPU accessed this segement */
uint8_t RW:1; /* 1: Data Segement 0: Code Segement */
uint8_t AC:1; /* 1: CPU accessed this segment */
uint8_t RW:1; /* 1: Data Segment 0: Code Segment */
uint8_t DC:1; /* Direction bit/Conforming bit. */
uint8_t EX:1; /* 1: Segment can be executed */
uint8_t S:1; /* S: 0:TSS 1:Code/Data Segement */
uint8_t S:1; /* S: 0:TSS 1:Code/Data Segment */
uint8_t DPL:2; /* DPL */
uint8_t P:1; /* Present? 1:Segment is preset */
uint8_t limit_high:4; /* Upper 4-bits of segment limit */

4
arch/xtensa/include/xtensa/xtensa_coproc.h
View File

@ -91,7 +91,7 @@
* The contents of a non-running thread's CPENABLE register.
* It represents the co-processors owned (and whose state is still needed)
* by the thread. When a thread is preempted, its CPENABLE is saved here.
* When a thread solicits a context-swtich, its CPENABLE is cleared - the
* When a thread solicits a context-switch, its CPENABLE is cleared - the
* compiler has saved the (caller-saved) co-proc state if it needs to.
* When a non-running thread loses ownership of a CP, its bit is cleared.
* When a thread runs, it's XTENSA_CPENABLE is loaded into the CPENABLE
@ -103,7 +103,7 @@
* Indicates whether the state of each co-processor is saved in the state
* save area. When the state of a thread is saved, only the state of
* co-procs still enabled in CPENABLE is saved. When the co-processor
* state is restored, the state is only resotred for a co-processor if
* state is restored, the state is only restored for a co-processor if
* this bit is set. This bist set is cleared after after co-processor
* state has been restored.
*

2
arch/xtensa/src/common/xtensa_int_handlers.S
View File

@ -111,7 +111,7 @@ g_intstacktop:
*
* Exit Conditions:
* This macro will use registers a2, a3 and a4.
* a2 - Points to the, possbily, new register save area.
* a2 - Points to the, possibly, new register save area.
*
****************************************************************************/

2
arch/xtensa/src/common/xtensa_mpu.c
View File

@ -105,7 +105,7 @@ void mpu_configure_region(uintptr_t base, size_t size,
* Xtensa ISA Reference Manual B4.6.5.3:
* The lowest address of each foregound segment
* must be no smaller than the lowest address of the
* preceding foregroud segment in numerical order.
* preceding foreground segment in numerical order.
*/
if (region < (XCHAL_MPU_ENTRIES - 1))

2
arch/xtensa/src/common/xtensa_vectors.S
View File

@ -242,7 +242,7 @@ _double_exception_vector:
break 1, 4 /* Unhandled double exception */
#endif
/* Can't use excetpion_entry because there is no relationship between EPC1
/* Can't use exception_entry because there is no relationship between EPC1
* DEPC and the current level. This can be handled by a separate ifeq
* block in the macro, however this part is not used, so let's not add
* this special case until we have an application for it.

4
arch/z16/src/z16f/z16f_timerisr.c
View File

@ -112,8 +112,8 @@ void up_timer_initialize(void)
/* Calculate timer reload value (continuous mode)
*
* timer_period = reload_value * divisor / system_clock_freqency
* timer_frequency = system_clock_freqency / divisor / reload_value
* timer_period = reload_value * divisor / system_clock_frequency
* timer_frequency = system_clock_frequency / divisor / reload_value
* or
* reload_value = (system_clock_frequency / timer_frequency / divisor
*

2
boards/arm/samd5e5/metro-m4/src/metro-m4.h
View File

@ -91,7 +91,7 @@
#define HAVE_PROGMEM_CHARDEV
#endif
/* This is the on-chip progmem memroy driver minor number */
/* This is the on-chip progmem memory driver minor number */
#define PROGMEM_MTD_MINOR 0

2
boards/arm/samv7/samv71-xult/src/sam_boot.c
View File

@ -138,7 +138,7 @@ void sam_boardinitialize(void)
* If CONFIG_BOARD_LATE_INITIALIZE is selected, then an additional
* initialization call will be performed in the boot-up sequence to a
* function called board_late_initialize(). board_late_initialize() will be
* called immediately after up_intitialize() is called and just before the
* called immediately after up_initialize() is called and just before the
* initial application is started. This additional initialization phase
* may be used, for example, to initialize board-specific device drivers.
*

2
boards/arm/stm32/photon/src/stm32_boot.c
View File

@ -87,7 +87,7 @@ void stm32_boardinitialize(void)
* If CONFIG_BOARD_LATE_INITIALIZE is selected, then an additional
* initialization call will be performed in the boot-up sequence to a
* function called board_late_initialize(). board_late_initialize() will
* be called immediately after up_intitialize() is called and just before
* be called immediately after up_initialize() is called and just before
* the initial application is started. This additional initialization
* phase may be used, for example, to initialize board-specific device
* drivers.

2
boards/arm/xmc4/xmc4500-relax/src/xmc4_boot.c
View File

@ -64,7 +64,7 @@ void xmc4_board_initialize(void)
* If CONFIG_BOARD_LATE_INITIALIZE is selected, then an additional
* initialization call will be performed in the boot-up sequence to a
* function called board_late_initialize(). board_late_initialize() will be
* called immediately after up_intitialize() is called and just before the
* called immediately after up_initialize() is called and just before the
* initial application is started. This additional initialization phase
* may be used, for example, to initialize board-specific device drivers.
*

2
boards/arm/xmc4/xmc4700-relax/src/xmc4_boot.c
View File

@ -64,7 +64,7 @@ void xmc4_board_initialize(void)
* If CONFIG_BOARD_LATE_INITIALIZE is selected, then an additional
* initialization call will be performed in the boot-up sequence to a
* function called board_late_initialize(). board_late_initialize() will be
* called immediately after up_intitialize() is called and just before the
* called immediately after up_initialize() is called and just before the
* initial application is started. This additional initialization phase
* may be used, for example, to initialize board-specific device drivers.
*

2
boards/boardctl.c
View File

@ -560,7 +560,7 @@ int boardctl(unsigned int cmd, uintptr_t arg)
/* CMD: BOARDIOC_OS_SYMTAB
* DESCRIPTION: Select the OS symbol table. This symbol table
* provides the symbol definitions exported by the OS to
* kernal modules.
* kernel modules.
* ARG: A pointer to an instance of struct boardioc_symtab_s
* CONFIGURATION: CONFIG_BOARDCTL_OS_SYMTAB
* DEPENDENCIES: None

2
crypto/ecb3_enc.c
View File

@ -10,7 +10,7 @@
* The implementation was written so as to conform with Netscapes SSL
* specification. This library and applications are
* FREE FOR COMMERCIAL AND NON-COMMERCIAL USE
* as long as the following conditions are aheared to.
* as long as the following conditions are adhered to.
*
* Copyright remains Eric Young's, and as such any Copyright notices in
* the code are not to be removed. If this code is used in a product,

2
crypto/ecb_enc.c
View File

@ -10,7 +10,7 @@
* The implementation was written so as to conform with Netscapes SSL
* specification. This library and applications are
* FREE FOR COMMERCIAL AND NON-COMMERCIAL USE
* as long as the following conditions are aheared to.
* as long as the following conditions are adhered to.
*
* Copyright remains Eric Young's, and as such any Copyright notices in
* the code are not to be removed. If this code is used in a product,

2
drivers/modem/alt1250/altmdm.c
View File

@ -81,7 +81,7 @@ typedef enum altmdm_state_e
ALTMDM_STATE_V4SET, /* Altcom version 4 command setting state */
ALTMDM_STATE_SLEEPSET, /* Sleep packet setting state */
ALTMDM_STATE_TXPREPARE, /* Normal packet setting state */
ALTMDM_STATE_TXREQ, /* TX request signal assersion state */
ALTMDM_STATE_TXREQ, /* TX request signal assertion state */
ALTMDM_STATE_HDRSREQ, /* Waiting for Slave request signal state */
ALTMDM_STATE_HDRTRX, /* SPI Header transaction state */
ALTMDM_STATE_SLEEPPKT, /* Sleep Packet body size adjustment

2
drivers/modem/alt1250/altmdm_event.c
View File

@ -143,7 +143,7 @@ uint32_t altmdm_event_wait(FAR struct altmdm_event_s *evt,
leave_critical_section(flags);
/* Wait for any event is occured related on the semaphore.. */
/* Wait for any event is occurred related on the semaphore.. */
if (timeout_ms > 0)
{

2
drivers/sensors/usensor.c
View File

@ -220,7 +220,7 @@ static int usensor_ioctl(FAR struct file *filep, int cmd,
* Description:
* This function registers usensor character node "/dev/usensor", so that
* application can register user sensor by this node. The node will
* manager all user sensors in this character dirver.
* manager all user sensors in this character driver.
****************************************************************************/
int usensor_initialize(void)

2
drivers/timers/arch_alarm.c
View File

@ -172,7 +172,7 @@ void up_alarm_set_lowerhalf(FAR struct oneshot_lowerhalf_s *lower)
*
* Description:
* Return the elapsed time since power-up (or, more correctly, since
* the archtecture-specific timer was initialized). This function is
* the architecture-specific timer was initialized). This function is
* functionally equivalent to:
*
* int clock_gettime(clockid_t clockid, FAR struct timespec *ts);

4
include/dsp.h
View File

@ -389,7 +389,7 @@ struct motor_phy_params_f32_s
float one_by_p; /* Inverse number of motor pole pairs */
};
/* PMSM motor physcial parameters */
/* PMSM motor physical parameters */
struct pmsm_phy_params_f32_s
{
@ -397,7 +397,7 @@ struct pmsm_phy_params_f32_s
float iner; /* Rotor inertia */
float ind_d; /* d-inductance */
float ind_q; /* q-inductance */
float one_by_iner; /* One by intertia */
float one_by_iner; /* One by inertia */
float one_by_indd; /* One by Ld */
float one_by_indq; /* One by Lq */
};

6
include/nuttx/arch.h
View File

@ -1513,7 +1513,7 @@ void up_timer_initialize(void);
*
* Description:
* Return the elapsed time since power-up (or, more correctly, since
* the archtecture-specific timer was initialized). This function is
* the architecture-specific timer was initialized). This function is
* functionally equivalent to:
*
* int clock_gettime(clockid_t clockid, FAR struct timespec *ts);
@ -2103,7 +2103,7 @@ char up_romgetc(FAR const char *ptr);
* Name: up_mdelay and up_udelay
*
* Description:
* Some device drivers may require that the plaform-specific logic
* Some device drivers may require that the platform-specific logic
* provides these timing loops for short delays.
*
****************************************************************************/
@ -2211,7 +2211,7 @@ void nxsched_process_cpuload_ticks(uint32_t ticks);
* Name: irq_dispatch
*
* Description:
* This function must be called from the achitecture-specific logic in
* This function must be called from the architecture-specific logic in
* order to dispatch an interrupt to the appropriate, registered handling
* logic.
*

2
include/nuttx/usb/audio.h
View File

@ -550,7 +550,7 @@
/* Input Terminal Types */
#define ADC_INTERM_UNDEF 0x0200 /* Undefined Type */
#define ADC_INTERM_MIC 0x0201 /* A generic microhpone */
#define ADC_INTERM_MIC 0x0201 /* A generic microphone */
#define ADC_INTERM_DESKTOP_MIC 0x0202 /* A desktop microphone */
#define ADC_INTERM_PERSONAL_MIC 0x0203 /* Head-mounted or clip-on microphone */
#define ADC_INTERM_OMNI_MIC 0x0204 /* Omni-directional microphone */

2
libs/libc/machine/arm/armv7-a/gnu/arch_strcmp.S
View File

@ -113,7 +113,7 @@ strcmp:
* both cases the other bits in r0 are all zero. For r3 the
* interesting byte is at the other end of the word, but the
* other bits are not necessarily zero. We need a signed result
* representing the differnece in the unsigned bytes, so for the
* representing the difference in the unsigned bytes, so for the
* little-endian case we can't just shift the interesting bits up.
*/
#ifdef __ARMEB__

4
libs/libc/machine/arm/armv7-m/gnu/arch_strcmp.S
View File

@ -99,7 +99,7 @@ def_fn strcmp
both cases the other bits in RESULT are all zero. For DATA2 the
interesting byte is at the other end of the word, but the
other bits are not necessarily zero. We need a signed result
representing the differnece in the unsigned bytes, so for the
representing the difference in the unsigned bytes, so for the
little-endian case we can't just shift the interesting bits
up. */
#ifdef __ARM_BIG_ENDIAN
@ -113,7 +113,7 @@ def_fn strcmp
#if 0
/* The assembly code below is based on the following alogrithm. */
/* The assembly code below is based on the following algorithm. */
#ifdef __ARM_BIG_ENDIAN
#define RSHIFT <<
#define LSHIFT >>

2
libs/libc/machine/arm/armv7-r/gnu/arch_strcmp.S
View File

@ -113,7 +113,7 @@ strcmp:
* both cases the other bits in r0 are all zero. For r3 the
* interesting byte is at the other end of the word, but the
* other bits are not necessarily zero. We need a signed result
* representing the differnece in the unsigned bytes, so for the
* representing the difference in the unsigned bytes, so for the
* little-endian case we can't just shift the interesting bits up.
*/
#ifdef __ARMEB__

4
libs/libc/machine/arm/armv8-m/gnu/arch_strcmp.S
View File

@ -129,7 +129,7 @@ def_fn strcmp
both cases the other bits in RESULT are all zero. For DATA2 the
interesting byte is at the other end of the word, but the
other bits are not necessarily zero. We need a signed result
representing the differnece in the unsigned bytes, so for the
representing the difference in the unsigned bytes, so for the
little-endian case we can't just shift the interesting bits
up. */
#ifdef __ARM_BIG_ENDIAN
@ -143,7 +143,7 @@ def_fn strcmp
#if 0
/* The assembly code below is based on the following alogrithm. */
/* The assembly code below is based on the following algorithm. */
#ifdef __ARM_BIG_ENDIAN
#define RSHIFT <<
#define LSHIFT >>

6
libs/libc/sched/task_setcanceltype.c
View File

@ -34,12 +34,12 @@
*
* Description:
* The task_setcanceltype() function atomically both sets the calling
* task's cancelability type to the indicated type and returns the
* previous cancelability type at the location referenced by oldtype
* task's cancellability type to the indicated type and returns the
* previous cancellability type at the location referenced by oldtype
* Legal values for type are TASK_CANCEL_DEFERRED and
* TASK_CANCEL_ASYNCHRONOUS.
*
* The cancelability state and type of any newly created tasks are
* The cancellability state and type of any newly created tasks are
* TASK_CANCEL_ENABLE and TASK_CANCEL_DEFERRED respectively.
*
****************************************************************************/

2
libs/libc/sched/task_testcancel.c
View File

@ -34,7 +34,7 @@
* Description:
* The task_testcancel() function creates a cancellation point in the
* calling thread. The task_testcancel() function has no effect if
* cancelability is disabled
* cancellability is disabled
*
****************************************************************************/

2
net/arp/arp.h
View File

@ -98,7 +98,7 @@ struct arp_hdr_s
uint16_t ah_hwtype; /* 16-bit Hardware type (Ethernet=0x001) */
uint16_t ah_protocol; /* 16-bit Protocol type (IP=0x0800) */
uint8_t ah_hwlen; /* 8-bit Hardware address size (6) */
uint8_t ah_protolen; /* 8-bit Procotol address size (4) */
uint8_t ah_protolen; /* 8-bit Protocol address size (4) */
uint16_t ah_opcode; /* 16-bit Operation */
uint8_t ah_shwaddr[6]; /* 48-bit Sender hardware address */
uint16_t ah_sipaddr[2]; /* 32-bit Sender IP address */

2
net/bluetooth/bluetooth_sockif.c
View File

@ -186,7 +186,7 @@ static int bluetooth_setup(FAR struct socket *psock)
* queried.
*
* Returned Value:
* The set of socket cababilities is returned.
* The set of socket capabilities is returned.
*
****************************************************************************/

2
net/devif/devif.h
View File

@ -583,7 +583,7 @@ int devif_loopback(FAR struct net_driver_s *dev);
* pkt/ipv[4|6]_input()/...
* |
* |
* NICs io vector receive(Orignal flat buffer)
* NICs io vector receive(Original flat buffer)
*
* Input Parameters:
* callback - Input callback of L3 stack

6
net/tcp/tcp_notifier.c
View File

@ -83,7 +83,7 @@ int tcp_readahead_notifier_setup(worker_t worker,
return 0;
}
/* Otherwise, this is just a simple wrapper around work_notifer_setup(). */
/* Otherwise, this is just a simple wrapper around work_notifier_setup(). */
info.evtype = WORK_TCP_READAHEAD;
info.qid = LPWORK;
@ -139,7 +139,7 @@ int tcp_writebuffer_notifier_setup(worker_t worker,
return 0;
}
/* Otherwise, this is just a simple wrapper around work_notifer_setup(). */
/* Otherwise, this is just a simple wrapper around work_notifier_setup(). */
info.evtype = WORK_TCP_WRITEBUFFER;
info.qid = LPWORK;
@ -192,7 +192,7 @@ int tcp_disconnect_notifier_setup(worker_t worker,
return 0;
}
/* Otherwise, this is just a simple wrapper around work_notifer_setup(). */
/* Otherwise, this is just a simple wrapper around work_notifier_setup(). */
info.evtype = WORK_TCP_DISCONNECT;
info.qid = LPWORK;