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STM32H7/STM32F30: Typos, register correction and extension

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* Correction in stm32h7x3xx_rcc
* Adding GPIO_TIM2_CH1OUT_1 to stm32f30xxx_pinmap
* Comment typo fix in drivers/mmcsd/mmcsd_spi.c
This commit is contained in:
GAEHWILER Reto 2020-03-03 09:20:58 -06:00 committed by Gregory Nutt
parent 7ffb5c11a0
commit 85e461c59c
3 changed files with 10 additions and 8 deletions
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1
arch/arm/src/stm32/hardware/stm32f30xxx_pinmap.h
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@ -302,6 +302,7 @@
#define GPIO_TIM2_CH1_ETR_2 (GPIO_ALT|GPIO_FLOAT|GPIO_AF1|GPIO_SPEED_50MHz|GPIO_PORTA|GPIO_PIN15)
#define GPIO_TIM2_CH1_ETR_3 (GPIO_ALT|GPIO_FLOAT|GPIO_AF1|GPIO_SPEED_50MHz|GPIO_PORTA|GPIO_PIN5)
#define GPIO_TIM2_CH1_ETR_4 (GPIO_ALT|GPIO_FLOAT|GPIO_AF2|GPIO_SPEED_50MHz|GPIO_PORTD|GPIO_PIN3)
#define GPIO_TIM2_CH1OUT_1 (GPIO_ALT|GPIO_PUSHPULL|GPIO_AF1|GPIO_SPEED_50MHz|GPIO_PORTA|GPIO_PIN15)
#define GPIO_TIM2_CH2IN_1 (GPIO_ALT|GPIO_FLOAT|GPIO_AF1|GPIO_SPEED_50MHz|GPIO_PORTA|GPIO_PIN1)
#define GPIO_TIM2_CH2OUT_1 (GPIO_ALT|GPIO_PUSHPULL|GPIO_AF1|GPIO_SPEED_50MHz|GPIO_PORTA|GPIO_PIN1)
#define GPIO_TIM2_CH2IN_2 (GPIO_ALT|GPIO_FLOAT|GPIO_AF1|GPIO_SPEED_50MHz|GPIO_PORTB|GPIO_PIN3)

15
arch/arm/src/stm32h7/hardware/stm32h7x3xx_rcc.h
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@ -263,18 +263,19 @@
# define RCC_CFGR_MCO1_HSI (0 << RCC_CFGR_MCO1_SHIFT) /* 000: HSI clock selected */
# define RCC_CFGR_MCO1_LSE (1 << RCC_CFGR_MCO1_SHIFT) /* 001: LSE oscillator selected */
# define RCC_CFGR_MCO1_HSE (2 << RCC_CFGR_MCO1_SHIFT) /* 010: HSE oscillator clock selected */
# define RCC_CFGR_MCO1_PLL (3 << RCC_CFGR_MCO1_SHIFT) /* 011: PLL clock selected */
# define RCC_CFGR_MCO1_PLL1Q (3 << RCC_CFGR_MCO1_SHIFT) /* 011: PLL clock selected */
# define RCC_CFGR_MCO1_HSI48 (4 << RCC_CFGR_MCO1_SHIFT) /* 100: HSI48 clock selected */
#define RCC_CFGR_MCO2PRE_SHIFT (25) /* Bits 25-28: MCO2 prescaler */
#define RCC_CFGR_MCO2PRE_MASK (0xf << RCC_CFGR_MCO2PRE_SHIFT)
# define RCC_CFGR_MCO2PRE(x) (((uint32_t)(x)) << RCC_CFGR_MCO2PRE_SHIFT)
#define RCC_CFGR_MCO2_SHIFT (29) /* Bits 29-31: Microcontroller Clock Output 2 */
#define RCC_CFGR_MCO2_MASK (7 << RCC_CFGR_MCO1_SHIFT)
# define RCC_CFGR_MCO2_HSI (0 << RCC_CFGR_MCO1_SHIFT) /* 000: HSI clock selected */
# define RCC_CFGR_MCO2_LSE (1 << RCC_CFGR_MCO1_SHIFT) /* 001: LSE oscillator selected */
# define RCC_CFGR_MCO2_HSE (2 << RCC_CFGR_MCO1_SHIFT) /* 010: HSE oscillator clock selected */
# define RCC_CFGR_MCO2_PLL (3 << RCC_CFGR_MCO1_SHIFT) /* 011: PLL clock selected */
# define RCC_CFGR_MCO2_HSI48 (4 << RCC_CFGR_MCO1_SHIFT) /* 100: HSI48 clock selected */
#define RCC_CFGR_MCO2_MASK (7 << RCC_CFGR_MCO2_SHIFT)
# define RCC_CFGR_MCO2_SYS (0 << RCC_CFGR_MCO2_SHIFT) /* 000: HSI clock selected */
# define RCC_CFGR_MCO2_PLL2P (1 << RCC_CFGR_MCO2_SHIFT) /* 001: PLL2 peripheral clock selected */
# define RCC_CFGR_MCO2_HSE (2 << RCC_CFGR_MCO2_SHIFT) /* 010: HSE oscillator clock selected */
# define RCC_CFGR_MCO2_PLL1P (3 << RCC_CFGR_MCO2_SHIFT) /* 011: PLL1 peripheral clock selected */
# define RCC_CFGR_MCO2_CSI (4 << RCC_CFGR_MCO2_SHIFT) /* 100: CSI clock selected */
# define RCC_CFGR_MCO2_LSI (5 << RCC_CFGR_MCO2_SHIFT) /* 101: LSI clock selected */
/* Bit definitions for RCC_D1CFGR */

2
drivers/mmcsd/mmcsd_spi.c
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@ -265,7 +265,7 @@ static struct mmcsd_slot_s g_mmcsdslot[CONFIG_MMCSD_NSLOTS];
static const uint32_t g_transpeedru[8] =
{
10000, /* 0: 10 Kbit/sec / 10 */
10000, /* 0: 100 Kbit/sec / 10 */
100000, /* 1: 1 Mbit/sec / 10 */
1000000, /* 2: 10 Mbit/sec / 10 */
10000000, /* 3: 100 Mbit/sec / 10 */