Add saml_i2c_slave.h for the SAML21
This commit is contained in:
Gregory Nutt
parent
53fe23f413
commit
85ee7fc8e8
@ -1,7 +1,7 @@
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/********************************************************************************************
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* arch/arm/src/samdl/chip/sam_i2c_slave.h
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* arch/arm/src/samdl/chip/samd_i2c_slave.h
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*
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* Copyright (C) 2014 Gregory Nutt. All rights reserved.
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* Copyright (C) 2014-2015 Gregory Nutt. All rights reserved.
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* Author: Gregory Nutt <gnutt@nuttx.org>
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*
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* References:
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@ -37,8 +37,8 @@
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*
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********************************************************************************************/
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#ifndef __ARCH_ARM_SRC_SAMDL_CHIP_SAM_I2C_SLAVE_H
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#define __ARCH_ARM_SRC_SAMDL_CHIP_SAM_I2C_SLAVE_H
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#ifndef __ARCH_ARM_SRC_SAMDL_CHIP_SAMD_I2C_SLAVE_H
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#define __ARCH_ARM_SRC_SAMDL_CHIP_SAMD_I2C_SLAVE_H
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/********************************************************************************************
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* Included Files
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@ -49,6 +49,8 @@
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#include "chip.h"
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#include "chip/sam_sercom.h"
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#ifdef CONFIG_ARCH_FAMILY_SAMD20
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/********************************************************************************************
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* Pre-processor Definitions
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********************************************************************************************/
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@ -56,7 +58,6 @@
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#define SAM_I2C_CTRLA_OFFSET 0x0000 /* Control A register */
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#define SAM_I2C_CTRLB_OFFSET 0x0004 /* Control B register */
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#define SAM_I2C_BAUD_OFFSET 0x000a /* Baud register */
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#define SAM_I2C_INTENCLR_OFFSET 0x000c /* Interrupt enable clear register */
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#define SAM_I2C_INTENSET_OFFSET 0x000d /* Interrupt enable set register */
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#define SAM_I2C_INTFLAG_OFFSET 0x000e /* Interrupt flag and status clear register */
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@ -68,7 +69,6 @@
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#define SAM_I2C0_CTRLA (SAM_SERCOM0_BASE+SAM_I2C_CTRLA_OFFSET)
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#define SAM_I2C0_CTRLB (SAM_SERCOM0_BASE+SAM_I2C_CTRLB_OFFSET)
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#define SAM_I2C0_BAUD (SAM_SERCOM0_BASE+SAM_I2C_BAUD_OFFSET)
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#define SAM_I2C0_INTENCLR (SAM_SERCOM0_BASE+SAM_I2C_INTENCLR_OFFSET)
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#define SAM_I2C0_INTENSET (SAM_SERCOM0_BASE+SAM_I2C_INTENSET_OFFSET)
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#define SAM_I2C0_INTFLAG (SAM_SERCOM0_BASE+SAM_I2C_INTFLAG_OFFSET)
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@ -78,7 +78,6 @@
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#define SAM_I2C1_CTRLA (SAM_SERCOM1_BASE+SAM_I2C_CTRLA_OFFSET)
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#define SAM_I2C1_CTRLB (SAM_SERCOM1_BASE+SAM_I2C_CTRLB_OFFSET)
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#define SAM_I2C1_BAUD (SAM_SERCOM1_BASE+SAM_I2C_BAUD_OFFSET)
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#define SAM_I2C1_INTENCLR (SAM_SERCOM1_BASE+SAM_I2C_INTENCLR_OFFSET)
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#define SAM_I2C1_INTENSET (SAM_SERCOM1_BASE+SAM_I2C_INTENSET_OFFSET)
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#define SAM_I2C1_INTFLAG (SAM_SERCOM1_BASE+SAM_I2C_INTFLAG_OFFSET)
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@ -88,7 +87,6 @@
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#define SAM_I2C2_CTRLA (SAM_SERCOM2_BASE+SAM_I2C_CTRLA_OFFSET)
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#define SAM_I2C2_CTRLB (SAM_SERCOM2_BASE+SAM_I2C_CTRLB_OFFSET)
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#define SAM_I2C2_BAUD (SAM_SERCOM2_BASE+SAM_I2C_BAUD_OFFSET)
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#define SAM_I2C2_INTENCLR (SAM_SERCOM2_BASE+SAM_I2C_INTENCLR_OFFSET)
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#define SAM_I2C2_INTENSET (SAM_SERCOM2_BASE+SAM_I2C_INTENSET_OFFSET)
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#define SAM_I2C2_INTFLAG (SAM_SERCOM2_BASE+SAM_I2C_INTFLAG_OFFSET)
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@ -98,7 +96,6 @@
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#define SAM_I2C3_CTRLA (SAM_SERCOM3_BASE+SAM_I2C_CTRLA_OFFSET)
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#define SAM_I2C3_CTRLB (SAM_SERCOM3_BASE+SAM_I2C_CTRLB_OFFSET)
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#define SAM_I2C3_BAUD (SAM_SERCOM3_BASE+SAM_I2C_BAUD_OFFSET)
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#define SAM_I2C3_INTENCLR (SAM_SERCOM3_BASE+SAM_I2C_INTENCLR_OFFSET)
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#define SAM_I2C3_INTENSET (SAM_SERCOM3_BASE+SAM_I2C_INTENSET_OFFSET)
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#define SAM_I2C3_INTFLAG (SAM_SERCOM3_BASE+SAM_I2C_INTFLAG_OFFSET)
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@ -108,7 +105,6 @@
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#define SAM_I2C4_CTRLA (SAM_SERCOM4_BASE+SAM_I2C_CTRLA_OFFSET)
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#define SAM_I2C4_CTRLB (SAM_SERCOM4_BASE+SAM_I2C_CTRLB_OFFSET)
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#define SAM_I2C4_BAUD (SAM_SERCOM4_BASE+SAM_I2C_BAUD_OFFSET)
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#define SAM_I2C4_INTENCLR (SAM_SERCOM4_BASE+SAM_I2C_INTENCLR_OFFSET)
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#define SAM_I2C4_INTENSET (SAM_SERCOM4_BASE+SAM_I2C_INTENSET_OFFSET)
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#define SAM_I2C4_INTFLAG (SAM_SERCOM4_BASE+SAM_I2C_INTFLAG_OFFSET)
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@ -118,7 +114,6 @@
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#define SAM_I2C5_CTRLA (SAM_SERCOM5_BASE+SAM_I2C_CTRLA_OFFSET)
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#define SAM_I2C5_CTRLB (SAM_SERCOM5_BASE+SAM_I2C_CTRLB_OFFSET)
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#define SAM_I2C5_BAUD (SAM_SERCOM5_BASE+SAM_I2C_BAUD_OFFSET)
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#define SAM_I2C5_INTENCLR (SAM_SERCOM5_BASE+SAM_I2C_INTENCLR_OFFSET)
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#define SAM_I2C5_INTENSET (SAM_SERCOM5_BASE+SAM_I2C_INTENSET_OFFSET)
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#define SAM_I2C5_INTFLAG (SAM_SERCOM5_BASE+SAM_I2C_INTFLAG_OFFSET)
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@ -164,15 +159,6 @@
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# define I2C_CTRLB_ACK (0) /* Send ACK */
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# define I2C_CTRLB_NCK I2C_CTRLB_ACKACT /* Send NACK */
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/* Baud register (16-bit baud value) */
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#define I2C_BAUD_SHIFT (0) /* Bits 0-7: Master Baud Rate */
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#define I2C_BAUD_MASK (0xff << I2C_BAUD_SHIFT)
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# define I2C_BAUD(n) ((uint16)(n) << I2C_BAUD_SHIFT)
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#define I2C_BAUDLOW_SHIFT (8) /* Bits 8-15: Master Baud Rate Low */
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#define I2C_BAUDLOW_MASK (0xff << I2C_BAUDLOW_SHIFT)
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# define I2C_BAUDLOW(n) (uint16)(n) << I2C_BAUDLOW_SHIFT)
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/* Interrupt enable clear, interrupt enable set, interrupt enable set, interrupt flag and
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* status clear registers.
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*/
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@ -197,10 +183,10 @@
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/* Address register */
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#define SPI_ADDR_GENCEN (1 << 0) /* Bit 0: General Call Address Enable */
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#define SPI_ADDR_SHIFT (0) /* Bits 1-7: Address */
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#define SPI_ADDR_SHIFT (1) /* Bits 1-7: Address */
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#define SPI_ADDR_MASK (0x7f << SPI_ADDR_SHIFT)
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# define SPI_ADDR(n) ((uint32_t)(n) << SPI_ADDR_SHIFT)
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#define SPI_ADDRMASK_SHIFT (16) /* Bits 17-23: Address Mask */
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#define SPI_ADDRMASK_SHIFT (17) /* Bits 17-23: Address Mask */
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#define SPI_ADDRMASK_MASK (0x7f << SPI_ADDRMASK_SHIFT)
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# define SPI_ADDRMASK(n) ((uint32_t)(n) << SPI_ADDRMASK_SHIFT)
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@ -220,4 +206,5 @@
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* Public Functions
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********************************************************************************************/
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#endif /* __ARCH_ARM_SRC_SAMDL_CHIP_SAM_I2C_SLAVE_H */
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#endif /* CONFIG_ARCH_FAMILY_SAMD20 */
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#endif /* __ARCH_ARM_SRC_SAMDL_CHIP_SAMD_I2C_SLAVE_H */
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209
arch/arm/src/samdl/chip/saml_i2c_slave.h
Normal file
209
arch/arm/src/samdl/chip/saml_i2c_slave.h
Normal file
@ -0,0 +1,209 @@
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/********************************************************************************************
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* arch/arm/src/samdl/chip/saml_i2c_slave.h
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*
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* Copyright (C) 2015 Gregory Nutt. All rights reserved.
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* Author: Gregory Nutt <gnutt@nuttx.org>
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*
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* References:
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* "Atmel SAM L21E / SAM L21G / SAM L21J Smart ARM-Based Microcontroller
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* Datasheet", Atmel-42385C-SAML21_Datasheet_Preliminary-03/20/15
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in
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* the documentation and/or other materials provided with the
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* distribution.
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* 3. Neither the name NuttX nor the names of its contributors may be
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* used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
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* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
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* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
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* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
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* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
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* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
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* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*
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********************************************************************************************/
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#ifndef __ARCH_ARM_SRC_SAMDL_CHIP_SAML_I2C_SLAVE_H
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#define __ARCH_ARM_SRC_SAMDL_CHIP_SAML_I2C_SLAVE_H
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/********************************************************************************************
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* Included Files
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********************************************************************************************/
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#include <nuttx/config.h>
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#include "chip.h"
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#include "chip/sam_sercom.h"
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#ifdef CONFIG_ARCH_FAMILY_SAML21
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/********************************************************************************************
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* Pre-processor Definitions
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********************************************************************************************/
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/* I2C register offsets *********************************************************************/
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#define SAM_I2C_CTRLA_OFFSET 0x0000 /* Control A register */
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#define SAM_I2C_CTRLB_OFFSET 0x0004 /* Control B register */
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#define SAM_I2C_INTENCLR_OFFSET 0x0014 /* Interrupt enable clear register */
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#define SAM_I2C_INTENSET_OFFSET 0x0016 /* Interrupt enable set register */
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#define SAM_I2C_INTFLAG_OFFSET 0x0018 /* Interrupt flag and status clear register */
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#define SAM_I2C_SYNCBUSY_OFFSET 0x001c /* Synchronization busy register */
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#define SAM_I2C_ADDR_OFFSET 0x0024 /* Address register */
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#define SAM_I2C_DATA_OFFSET 0x0028 /* Data register */
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/* I2C register addresses *******************************************************************/
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#define SAM_I2C0_CTRLA (SAM_SERCOM0_BASE+SAM_I2C_CTRLA_OFFSET)
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#define SAM_I2C0_CTRLB (SAM_SERCOM0_BASE+SAM_I2C_CTRLB_OFFSET)
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#define SAM_I2C0_INTENCLR (SAM_SERCOM0_BASE+SAM_I2C_INTENCLR_OFFSET)
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#define SAM_I2C0_INTENSET (SAM_SERCOM0_BASE+SAM_I2C_INTENSET_OFFSET)
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#define SAM_I2C0_INTFLAG (SAM_SERCOM0_BASE+SAM_I2C_INTFLAG_OFFSET)
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#define SAM_I2C0_ADDR (SAM_SERCOM0_BASE+SAM_I2C_ADDR_OFFSET)
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#define SAM_I2C0_DATA (SAM_SERCOM0_BASE+SAM_I2C_DATA_OFFSET)
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#define SAM_I2C1_CTRLA (SAM_SERCOM1_BASE+SAM_I2C_CTRLA_OFFSET)
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#define SAM_I2C1_CTRLB (SAM_SERCOM1_BASE+SAM_I2C_CTRLB_OFFSET)
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#define SAM_I2C1_INTENCLR (SAM_SERCOM1_BASE+SAM_I2C_INTENCLR_OFFSET)
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#define SAM_I2C1_INTENSET (SAM_SERCOM1_BASE+SAM_I2C_INTENSET_OFFSET)
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#define SAM_I2C1_INTFLAG (SAM_SERCOM1_BASE+SAM_I2C_INTFLAG_OFFSET)
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#define SAM_I2C1_ADDR (SAM_SERCOM1_BASE+SAM_I2C_ADDR_OFFSET)
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#define SAM_I2C1_DATA (SAM_SERCOM1_BASE+SAM_I2C_DATA_OFFSET)
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#define SAM_I2C2_CTRLA (SAM_SERCOM2_BASE+SAM_I2C_CTRLA_OFFSET)
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#define SAM_I2C2_CTRLB (SAM_SERCOM2_BASE+SAM_I2C_CTRLB_OFFSET)
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#define SAM_I2C2_INTENCLR (SAM_SERCOM2_BASE+SAM_I2C_INTENCLR_OFFSET)
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#define SAM_I2C2_INTENSET (SAM_SERCOM2_BASE+SAM_I2C_INTENSET_OFFSET)
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#define SAM_I2C2_INTFLAG (SAM_SERCOM2_BASE+SAM_I2C_INTFLAG_OFFSET)
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#define SAM_I2C2_ADDR (SAM_SERCOM2_BASE+SAM_I2C_ADDR_OFFSET)
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#define SAM_I2C2_DATA (SAM_SERCOM2_BASE+SAM_I2C_DATA_OFFSET)
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#define SAM_I2C3_CTRLA (SAM_SERCOM3_BASE+SAM_I2C_CTRLA_OFFSET)
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#define SAM_I2C3_CTRLB (SAM_SERCOM3_BASE+SAM_I2C_CTRLB_OFFSET)
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#define SAM_I2C3_INTENCLR (SAM_SERCOM3_BASE+SAM_I2C_INTENCLR_OFFSET)
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#define SAM_I2C3_INTENSET (SAM_SERCOM3_BASE+SAM_I2C_INTENSET_OFFSET)
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#define SAM_I2C3_INTFLAG (SAM_SERCOM3_BASE+SAM_I2C_INTFLAG_OFFSET)
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#define SAM_I2C3_ADDR (SAM_SERCOM3_BASE+SAM_I2C_ADDR_OFFSET)
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#define SAM_I2C3_DATA (SAM_SERCOM3_BASE+SAM_I2C_DATA_OFFSET)
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#define SAM_I2C4_CTRLA (SAM_SERCOM4_BASE+SAM_I2C_CTRLA_OFFSET)
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#define SAM_I2C4_CTRLB (SAM_SERCOM4_BASE+SAM_I2C_CTRLB_OFFSET)
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#define SAM_I2C4_INTENCLR (SAM_SERCOM4_BASE+SAM_I2C_INTENCLR_OFFSET)
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#define SAM_I2C4_INTENSET (SAM_SERCOM4_BASE+SAM_I2C_INTENSET_OFFSET)
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#define SAM_I2C4_INTFLAG (SAM_SERCOM4_BASE+SAM_I2C_INTFLAG_OFFSET)
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#define SAM_I2C4_ADDR (SAM_SERCOM4_BASE+SAM_I2C_ADDR_OFFSET)
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#define SAM_I2C4_DATA (SAM_SERCOM4_BASE+SAM_I2C_DATA_OFFSET)
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#define SAM_I2C5_CTRLA (SAM_SERCOM5_BASE+SAM_I2C_CTRLA_OFFSET)
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#define SAM_I2C5_CTRLB (SAM_SERCOM5_BASE+SAM_I2C_CTRLB_OFFSET)
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#define SAM_I2C5_INTENCLR (SAM_SERCOM5_BASE+SAM_I2C_INTENCLR_OFFSET)
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#define SAM_I2C5_INTENSET (SAM_SERCOM5_BASE+SAM_I2C_INTENSET_OFFSET)
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#define SAM_I2C5_INTFLAG (SAM_SERCOM5_BASE+SAM_I2C_INTFLAG_OFFSET)
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#define SAM_I2C5_ADDR (SAM_SERCOM5_BASE+SAM_I2C_ADDR_OFFSET)
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#define SAM_I2C5_DATA (SAM_SERCOM5_BASE+SAM_I2C_DATA_OFFSET)
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/* I2C register bit definitions *************************************************************/
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/* Control A register */
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#define I2C_CTRLA_SWRST (1 << 0) /* Bit 0: Software reset */
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#define I2C_CTRLA_ENABLE (1 << 1) /* Bit 1: Enable */
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#define I2C_CTRLA_MODE_SHIFT (2) /* Bits 2-4: Operating Mode */
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#define I2C_CTRLA_MODE_MASK (7 << I2C_CTRLA_MODE_SHIFT)
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# define I2C_CTRLA_MODE_SLAVE (4 << I2C_CTRLA_MODE_SHIFT) /* I2C slave mode */
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#define I2C_CTRLA_RUNSTDBY (1 << 7) /* Bit 7: Run in standby */
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#define I2C_CTRLA_PINOUT (1 << 16) /* Bit 16: Pin usage */
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# define I2C_CTRLA_1WIRE (0) /* 4-wire operation disabled */
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# define I2C_CTRLA_4WIRE I2C_CTRLA_PINOUT /* 4-wire operation enabled */
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#define I2C_CTRLA_SDAHOLD_SHIFT (20) /* Bits 20-21: SDA Hold Time */
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#define I2C_CTRLA_SDAHOLD_MASK (3 << I2C_CTRLA_SDAHOLD_SHIFT)
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# define I2C_CTRLA_SDAHOLD_DIS (0 << I2C_CTRLA_SDAHOLD_SHIFT) /* Disabled */
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# define I2C_CTRLA_SDAHOLD_75NS (1 << I2C_CTRLA_SDAHOLD_SHIFT) /* 50-100ns hold time */
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# define I2C_CTRLA_SDAHOLD_450NS (2 << I2C_CTRLA_SDAHOLD_SHIFT) /* 300-600ns hold time */
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# define I2C_CTRLA_SDAHOLD_600NS (3 << I2C_CTRLA_SDAHOLD_SHIFT) /* 400-800ns hold time */
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#define I2C_CTRLA_SEXTTOEN (1 << 23) /* Bit 23: Slave SCL low extend time-out */
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#define I2C_CTRLA_SPEED_SHIFT (24) /* Bits 24-25: Trnasfer speed */
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#define I2C_CTRLA_SPEED_MASK (3 << I2C_CTRLA_SPEED_SHIFT)
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# define I2C_CTRLA_SPEED_STD (0 << I2C_CTRLA_SPEED_SHIFT) /* Standard (<=100KHz) fast <=400KHz */
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# define I2C_CTRLA_SPEED_FAST (1 << I2C_CTRLA_SPEED_SHIFT) /* Fast-mode plase (<=1MHz) */
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# define I2C_CTRLA_SPEED_HIGH (2 << I2C_CTRLA_SPEED_SHIFT) /* High-speed mode (<=3.4Mhz */
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#define I2C_CTRLA_SCLSM (1 << 27) /* Bit 27: SCL clock stretch mode */
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#define I2C_CTRLA_LOWTOUT (1 << 30) /* Bit 30: SCL Low Time-Out */
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/* Control B register */
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#define I2C_CTRLB_SMEN (1 << 8) /* Bit 8: Smart Mode Enable */
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#define I2C_CTRLB_GCMD (1 << 9) /* Bit 9: PMBus group commend */
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#define I2C_CTRLB_AACKEN (1 << 10) /* Bit 10: Automatic acknowledge enable */
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#define I2C_CRLB_AMODE_SHIFT (14) /* Bits 14-15: Address Mode */
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#define I2C_CRLB_AMODE_MASK (3 << I2C_CRLB_AMODE_SHIFT)
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# define I2C_CRLB_AMODE_MASK (0 << I2C_CRLB_AMODE_SHIFT) /* ADDRMASK used to mask ADDR */
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# define I2C_CRLB_AMODE_2ADDRS (1 << I2C_CRLB_AMODE_SHIFT) /* Slave 2 addresses: ADDR & ADDRMASK */
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# define I2C_CRLB_AMODE_RANGE (2 << I2C_CRLB_AMODE_SHIFT) /* Slave range of addresses: ADDRMASK-ADDR */
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#define I2C_CTRLB_CMD_SHIFT (16) /* Bits 16-17: Command */
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#define I2C_CTRLB_CMD_MASK (3 << I2C_CTRLB_CMD_SHIFT)
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# define I2C_CTRLB_CMD_NOACTION (0 << I2C_CTRLB_CMD_SHIFT) /* No action */
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# define I2C_CTRLB_CMD_WAITSTART (2 << I2C_CTRLB_CMD_SHIFT) /* ACK (write) wait for START */
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# define I2C_CTRLB_CMD_ACKREAD (3 << I2C_CTRLB_CMD_SHIFT) /* ACK with read (context dependent) */
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#define I2C_CTRLB_ACKACT (1 << 18) /* Bit 18: Acknowledge Action */
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# define I2C_CTRLB_ACK (0) /* Send ACK */
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# define I2C_CTRLB_NCK I2C_CTRLB_ACKACT /* Send NACK */
|
||||
|
||||
/* Interrupt enable clear, interrupt enable set, interrupt enable set, interrupt flag and
|
||||
* status clear registers.
|
||||
*/
|
||||
|
||||
#define I2C_INT_PREC (1 << 0) /* Bit 0: Stop received interrupt */
|
||||
#define I2C_INT_AMATCH (1 << 1) /* Bit 1: Address match interrupt */
|
||||
#define I2C_INT_DRDY (1 << 2) /* Bit 2: Data ready interrupt */
|
||||
#define I2C_INT_ERROR (1 << 7) /* Bit 7: Error interrupt */
|
||||
|
||||
#define I2C_INT_ALL (0x87)
|
||||
|
||||
/* Synchronization busy register */
|
||||
|
||||
#define I2C_SYNCBUSY_SWRST (1 << 0) /* Bit 0: Software reset synchronization busy */
|
||||
#define I2C_SYNCBUSY_ENABLE (1 << 1) /* Bit 1: SERCOM enable synchronization busy */
|
||||
|
||||
/* Address register */
|
||||
|
||||
#define SPI_ADDR_GENCEN (1 << 0) /* Bit 0: General Call Address Enable */
|
||||
#define SPI_ADDR_SHIFT (1) /* Bits 1-10: Address */
|
||||
#define SPI_ADDR_MASK (0x3ff << SPI_ADDR_SHIFT)
|
||||
# define SPI_ADDR(n) ((uint32_t)(n) << SPI_ADDR_SHIFT)
|
||||
#define SPI_ADDR_TENBITEN (1 << 15) /* Bit 15: */
|
||||
#define SPI_ADDRMASK_SHIFT (17) /* Bits 17-26: Address Mask */
|
||||
#define SPI_ADDRMASK_MASK (0x3ff << SPI_ADDRMASK_SHIFT)
|
||||
# define SPI_ADDRMASK(n) ((uint32_t)(n) << SPI_ADDRMASK_SHIFT)
|
||||
|
||||
/* Data register */
|
||||
|
||||
#define I2C_DATA_MASK (0xff) /* Bits 0-7: Data */
|
||||
|
||||
/********************************************************************************************
|
||||
* Public Types
|
||||
********************************************************************************************/
|
||||
|
||||
/********************************************************************************************
|
||||
* Public Data
|
||||
********************************************************************************************/
|
||||
|
||||
/********************************************************************************************
|
||||
* Public Functions
|
||||
********************************************************************************************/
|
||||
|
||||
#endif /* CONFIG_ARCH_FAMILY_SAML21 */
|
||||
#endif /* __ARCH_ARM_SRC_SAMDL_CHIP_SAML_I2C_SLAVE_H */
|
||||
@ -204,7 +204,7 @@
|
||||
#define SPI_INT_SSL (1 << 3) /* Bit 3: Slave select low interrupt */
|
||||
#define SPI_INT_ERROR (1 << 7) /* Bit 7: Error interrupt */
|
||||
|
||||
#define SPI_INT_ALL (0x0f)
|
||||
#define SPI_INT_ALL (0x8f)
|
||||
|
||||
/* Status register */
|
||||
|
||||
|
||||
Loading…
Reference in New Issue
Block a user