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This commit adds an i.MX RT Ethernet drivers.

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Squashed commit of the following:

Author: Gregory Nutt <gnutt@nuttx.org>
    arch/arm/src/imxrt:  Add cache operations to permit the Ethernet driver to work with the D-Cache enabled, at least in write-through mode.

Author: Jake Choy <jakearcx@gmail.com>
    arch/arm/src/imxrt:  The Ethernet driver is now functional, at least with the D-Cache off.  The final fix was for the reference clock that needs to be forced to provide and input (SION).

Author: Gregory Nutt <gnutt@nuttx.org>
    Fix trivial coding standard issue.
    configs/imxrt1050-evk:  Correct CONFIG_RAM_SIZE in all configurations (5Kb not 5Mb).  I don't believe that CONFIG_RAM_SIZE is used at all in the i.MX RT so this is as grievous an error as it seems.  Also enabled built-in applications in all NSH configurations.
    arch/arm/src/imxrt/imxrt_enet.c:  Trivial and cosmetic.
    Cosmetic update to comments.
    arch/arm/src/imxrt/imxrt_enet.c:  Oops.. put the PHY interrupt init hooks in the wrong place.  That is a one-time initialization but imxrt_initphy() is called on each ifup.
    arch/arm/src/imxrt/imxrt_enet.c:  Add hooks for board-specific PHY initialization (not yet needed, but there when needed).
    Remove dangling white space at the end of lines
    arch/arm/src/imxrt/Kconfig:  Add option for board-specific PHY initialization.
    configs/imxrt1050-evk/src:  Add basic logic to support PHY interrupts.  Incomplete.. needs additional support in imxrt_enet.c to 1. call to initialize PHY interrupt features, and 2. IOCTL commands to access PHY registers.
    configs/imxrt1050-evk/README.txt: Trivial update.
    configs/imxrt1050-evk/netnsh/defconfig:  Disable LED support because pins conflict with PHY.  Enable device statists.  Enable NSH ifup and ifdown commmands
    arch/arm/src/imxrt:  Use macros in imxrt_periphclks.h vs. direct CCM CCGR accesses in Ethernet driver.
    arch/arm/src/imxrt:  Misc changes for a clean compilation of Ethernet deriver.  configs/imxrt1050-evk/netnsh:  Add an NSH configuration for testing Ethernet.

Author: Jake Choy <jakearcx@gmail.com>
    arch/arm/src/imxrt:  Initial WIP Ethernet driver.
This commit is contained in:
Jake Choy 2018-05-25 09:36:23 -06:00 committed by Gregory Nutt
parent e07504291e
commit 8601d767cc
15 changed files with 3550 additions and 14 deletions
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38
arch/arm/src/imxrt/Kconfig
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@ -69,6 +69,12 @@ config IMXRT_EDMA
default n
select ARCH_DMA
config IMXRT_ENET
bool "Ethernet"
default n
select ARCH_HAVE_PHY
select ARCH_HAVE_NETDEV_STATISTICS
menu "FlexIO Peripherals"
endmenu # FlexIO Peripherals
@ -179,6 +185,38 @@ config IMXRT_GPIO5_16_31_IRQ
endif # IMXRT_GPIO_IRQ
menu "Ethernet Configuration"
depends on IMXRT_ENET
config MXRT_ENET_NRXBUFFERS
int "Number Rx buffers"
default 6
config IMXRT_ENET_NTXBUFFERS
int "Number Tx buffers"
default 2
config IMXRT_ENET_ENHANCEDBD
bool # not optional
default n
config IMXRT_ENET_NETHIFS
int # Not optional
default 1
config IMXRT_ENET_PHYINIT
bool "Board-specific PHY Initialization"
default n
---help---
Some boards require specialized initialization of the PHY before it
can be used. This may include such things as configuring GPIOs,
resetting the PHY, etc. If CONFIG_IMXRT_ENET_PHYINIT is defined in
the configuration then the board specific logic must provide
imxrt_phy_boardinitialize(); The i.MXRT ENET driver will call this
function one time before it first uses the PHY.
endmenu # IMXRT_ENET
menu "Memory Configuration"
config IMXRT_DTCM

4
arch/arm/src/imxrt/Make.defs
View File

@ -123,3 +123,7 @@ endif
ifeq ($(CONFIG_IMXRT_EDMA),y)
CHIP_CSRCS += imxrt_edma.c
endif
ifeq ($(CONFIG_IMXRT_ENET),y)
CHIP_CSRCS += imxrt_enet.c
endif

4
arch/arm/src/imxrt/chip/imxrt105x_pinmux.h
View File

@ -41,6 +41,7 @@
*****************************************************************************************************/
#include <nuttx/config.h>
#include "chip/imxrt_iomuxc.h"
/*****************************************************************************************************
* Pre-processor Definitions
@ -187,7 +188,8 @@
#define GPIO_ENET_RX_ER_2 (GPIO_PERIPH | GPIO_ALT3 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_26_INDEX))
#define GPIO_ENET_TDATA00 (GPIO_PERIPH | GPIO_ALT3 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_22_INDEX))
#define GPIO_ENET_TDATA01 (GPIO_PERIPH | GPIO_ALT3 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_21_INDEX))
#define GPIO_ENET_TX_CLK_1 (GPIO_PERIPH | GPIO_ALT6 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_B1_10_INDEX) | \
#define GPIO_ENET_TX_CLK_1 (GPIO_PERIPH | GPIO_ALT6 | GPIO_SION_ENABLE | \
GPIO_PADMUX(IMXRT_PADMUX_GPIO_B1_10_INDEX) | \
IOMUX_SLEW_FAST | IOMUX_DRIVE_40OHM | IOMUX_SPEED_LOW | \
IOMUX_PULL_DOWN_100K | IOMUX_PULL_KEEP)
#define GPIO_ENET_TX_CLK_2 (GPIO_PERIPH | GPIO_ALT3 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_25_INDEX))

669
arch/arm/src/imxrt/chip/imxrt_enet.h Normal file
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@ -0,0 +1,669 @@
/********************************************************************************************
* arch/arm/src/imxrt/chip/imxrt_enet.h
*
* Copyright (C) 2018 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
********************************************************************************************/
#ifndef __ARCH_ARM_SRC_IMXRT_CHIP_IMXRT_ENET_H
#define __ARCH_ARM_SRC_IMXRT_CHIP_IMXRT_ENET_H
/********************************************************************************************
* Included Files
********************************************************************************************/
#include <nuttx/config.h>
#include "chip.h"
/********************************************************************************************
* Pre-processor Definitions
********************************************************************************************/
/* Register Offsets *************************************************************************/
#define IMXRT_ENET_EIR_OFFSET 0x0004 /* Interrupt Event Register */
#define IMXRT_ENET_EIMR_OFFSET 0x0008 /* Interrupt Mask Register */
#define IMXRT_ENET_RDAR_OFFSET 0x0010 /* Receive Descriptor Active Register */
#define IMXRT_ENET_TDAR_OFFSET 0x0014 /* Transmit Descriptor Active Register */
#define IMXRT_ENET_ECR_OFFSET 0x0024 /* Ethernet Control Register */
#define IMXRT_ENET_MMFR_OFFSET 0x0040 /* MII Management Frame Register */
#define IMXRT_ENET_MSCR_OFFSET 0x0044 /* MII Speed Control Register */
#define IMXRT_ENET_MIBC_OFFSET 0x0064 /* MIB Control Register */
#define IMXRT_ENET_RCR_OFFSET 0x0084 /* Receive Control Register */
#define IMXRT_ENET_TCR_OFFSET 0x00c4 /* Transmit Control Register */
#define IMXRT_ENET_PALR_OFFSET 0x00e4 /* Physical Address Lower Register */
#define IMXRT_ENET_PAUR_OFFSET 0x00e8 /* Physical Address Upper Register */
#define IMXRT_ENET_OPD_OFFSET 0x00ec /* Opcode/Pause Duration Register */
#define IMXRT_ENET_TXIC_OFFSET 0x00F0 /* Transmit Interrupt Coalescing Register */
#define IMXRT_ENET_RXIC_OFFSET 0x0100 /* Receive Interrupt Coalescing Register */
#define IMXRT_ENET_IAUR_OFFSET 0x0118 /* Descriptor Individual Upper Address Register */
#define IMXRT_ENET_IALR_OFFSET 0x011c /* Descriptor Individual Lower Address Register */
#define IMXRT_ENET_GAUR_OFFSET 0x0120 /* Descriptor Group Upper Address Register */
#define IMXRT_ENET_GALR_OFFSET 0x0124 /* Descriptor Group Lower Address Register */
#define IMXRT_ENET_TFWR_OFFSET 0x0144 /* Transmit FIFO Watermark Register */
#define IMXRT_ENET_RDSR_OFFSET 0x0180 /* Receive Descriptor Ring Start Register */
#define IMXRT_ENET_TDSR_OFFSET 0x0184 /* Transmit Buffer Descriptor Ring Start Register */
#define IMXRT_ENET_MRBR_OFFSET 0x0188 /* Maximum Receive Buffer Size Register */
#define IMXRT_ENET_RSFL_OFFSET 0x0190 /* Receive FIFO Section Full Threshold */
#define IMXRT_ENET_RSEM_OFFSET 0x0194 /* Receive FIFO Section Empty Threshold */
#define IMXRT_ENET_RAEM_OFFSET 0x0198 /* Receive FIFO Almost Empty Threshold */
#define IMXRT_ENET_RAFL_OFFSET 0x019c /* Receive FIFO Almost Full Threshold */
#define IMXRT_ENET_TSEM_OFFSET 0x01a0 /* Transmit FIFO Section Empty Threshold */
#define IMXRT_ENET_TAEM_OFFSET 0x01a4 /* Transmit FIFO Almost Empty Threshold */
#define IMXRT_ENET_TAFL_OFFSET 0x01a8 /* Transmit FIFO Almost Full Threshold */
#define IMXRT_ENET_TIPG_OFFSET 0x01ac /* Transmit Inter-Packet Gap */
#define IMXRT_ENET_FTRL_OFFSET 0x01b0 /* Frame Truncation Length */
#define IMXRT_ENET_TACC_OFFSET 0x01c0 /* Transmit Accelerator Function Configuration */
#define IMXRT_ENET_RACC_OFFSET 0x01c4 /* Receive Accelerator Function Configuration */
#define IMXRT_ENET_ATCR_OFFSET 0x0400 /* Timer Control Register */
#define IMXRT_ENET_ATVR_OFFSET 0x0404 /* Timer Value Register */
#define IMXRT_ENET_ATOFF_OFFSET 0x0408 /* Timer Offset Register */
#define IMXRT_ENET_ATPER_OFFSET 0x040c /* Timer Period Register */
#define IMXRT_ENET_ATCOR_OFFSET 0x0410 /* Timer Correction Register */
#define IMXRT_ENET_ATINC_OFFSET 0x0414 /* Time-Stamping Clock Period Register */
#define IMXRT_ENET_ATSTMP_OFFSET 0x0418 /* Timestamp of Last Transmitted Frame */
#define IMXRT_ENET_TGSR_OFFSET 0x0604 /* Timer Global Status Register */
#define IMXRT_ENET_TCSR0_OFFSET 0x0608 /* Timer Control Status Register */
#define IMXRT_ENET_TCCR0_OFFSET 0x060c /* Timer Compare Capture Register */
#define IMXRT_ENET_TCSR1_OFFSET 0x0610 /* Timer Control Status Register */
#define IMXRT_ENET_TCCR1_OFFSET 0x0614 /* Timer Compare Capture Register */
#define IMXRT_ENET_TCSR2_OFFSET 0x0618 /* Timer Control Status Register */
#define IMXRT_ENET_TCCR2_OFFSET 0x061c /* Timer Compare Capture Register */
#define IMXRT_ENET_TCSR3_OFFSET 0x0620 /* Timer Control Status Register */
#define IMXRT_ENET_TCCR3_OFFSET 0x0624 /* Timer Compare Capture Register */
/* Register Addresses ***********************************************************************/
#define IMXRT_ENET_EIR (IMXRT_ENET_BASE+IMXRT_ENET_EIR_OFFSET)
#define IMXRT_ENET_EIMR (IMXRT_ENET_BASE+IMXRT_ENET_EIMR_OFFSET)
#define IMXRT_ENET_RDAR (IMXRT_ENET_BASE+IMXRT_ENET_RDAR_OFFSET)
#define IMXRT_ENET_TDAR (IMXRT_ENET_BASE+IMXRT_ENET_TDAR_OFFSET)
#define IMXRT_ENET_ECR (IMXRT_ENET_BASE+IMXRT_ENET_ECR_OFFSET)
#define IMXRT_ENET_MMFR (IMXRT_ENET_BASE+IMXRT_ENET_MMFR_OFFSET)
#define IMXRT_ENET_MSCR (IMXRT_ENET_BASE+IMXRT_ENET_MSCR_OFFSET)
#define IMXRT_ENET_MIBC (IMXRT_ENET_BASE+IMXRT_ENET_MIBC_OFFSET)
#define IMXRT_ENET_RCR (IMXRT_ENET_BASE+IMXRT_ENET_RCR_OFFSET)
#define IMXRT_ENET_TCR (IMXRT_ENET_BASE+IMXRT_ENET_TCR_OFFSET)
#define IMXRT_ENET_PALR (IMXRT_ENET_BASE+IMXRT_ENET_PALR_OFFSET)
#define IMXRT_ENET_PAUR (IMXRT_ENET_BASE+IMXRT_ENET_PAUR_OFFSET)
#define IMXRT_ENET_OPD (IMXRT_ENET_BASE+IMXRT_ENET_OPD_OFFSET)
#define IMXRT_ENET_IAUR (IMXRT_ENET_BASE+IMXRT_ENET_IAUR_OFFSET)
#define IMXRT_ENET_IALR (IMXRT_ENET_BASE+IMXRT_ENET_IALR_OFFSET)
#define IMXRT_ENET_GAUR (IMXRT_ENET_BASE+IMXRT_ENET_GAUR_OFFSET)
#define IMXRT_ENET_GALR (IMXRT_ENET_BASE+IMXRT_ENET_GALR_OFFSET)
#define IMXRT_ENET_TFWR (IMXRT_ENET_BASE+IMXRT_ENET_TFWR_OFFSET)
#define IMXRT_ENET_RDSR (IMXRT_ENET_BASE+IMXRT_ENET_RDSR_OFFSET)
#define IMXRT_ENET_TDSR (IMXRT_ENET_BASE+IMXRT_ENET_TDSR_OFFSET)
#define IMXRT_ENET_MRBR (IMXRT_ENET_BASE+IMXRT_ENET_MRBR_OFFSET)
#define IMXRT_ENET_RSFL (IMXRT_ENET_BASE+IMXRT_ENET_RSFL_OFFSET)
#define IMXRT_ENET_RSEM (IMXRT_ENET_BASE+IMXRT_ENET_RSEM_OFFSET)
#define IMXRT_ENET_RAEM (IMXRT_ENET_BASE+IMXRT_ENET_RAEM_OFFSET)
#define IMXRT_ENET_RAFL (IMXRT_ENET_BASE+IMXRT_ENET_RAFL_OFFSET)
#define IMXRT_ENET_TSEM (IMXRT_ENET_BASE+IMXRT_ENET_TSEM_OFFSET)
#define IMXRT_ENET_TAEM (IMXRT_ENET_BASE+IMXRT_ENET_TAEM_OFFSET)
#define IMXRT_ENET_TAFL (IMXRT_ENET_BASE+IMXRT_ENET_TAFL_OFFSET)
#define IMXRT_ENET_TIPG (IMXRT_ENET_BASE+IMXRT_ENET_TIPG_OFFSET)
#define IMXRT_ENET_FTRL (IMXRT_ENET_BASE+IMXRT_ENET_FTRL_OFFSET)
#define IMXRT_ENET_TACC (IMXRT_ENET_BASE+IMXRT_ENET_TACC_OFFSET)
#define IMXRT_ENET_RACC (IMXRT_ENET_BASE+IMXRT_ENET_RACC_OFFSET)
#define IMXRT_ENET_ATCR (IMXRT_ENET_BASE+IMXRT_ENET_ATCR_OFFSET)
#define IMXRT_ENET_ATVR (IMXRT_ENET_BASE+IMXRT_ENET_ATVR_OFFSET)
#define IMXRT_ENET_ATOFF (IMXRT_ENET_BASE+IMXRT_ENET_ATOFF_OFFSET)
#define IMXRT_ENET_ATPER (IMXRT_ENET_BASE+IMXRT_ENET_ATPER_OFFSET)
#define IMXRT_ENET_ATCOR (IMXRT_ENET_BASE+IMXRT_ENET_ATCOR_OFFSET)
#define IMXRT_ENET_ATINC (IMXRT_ENET_BASE+IMXRT_ENET_ATINC_OFFSET)
#define IMXRT_ENET_ATSTMP (IMXRT_ENET_BASE+IMXRT_ENET_ATSTMP_OFFSET)
#define IMXRT_ENET_TGSR (IMXRT_ENET_BASE+IMXRT_ENET_TGSR_OFFSET)
#define IMXRT_ENET_TCSR0 (IMXRT_ENET_BASE+IMXRT_ENET_TCSR0_OFFSET)
#define IMXRT_ENET_TCCR0 (IMXRT_ENET_BASE+IMXRT_ENET_TCCR0_OFFSET)
#define IMXRT_ENET_TCSR1 (IMXRT_ENET_BASE+IMXRT_ENET_TCSR1_OFFSET)
#define IMXRT_ENET_TCCR1 (IMXRT_ENET_BASE+IMXRT_ENET_TCCR1_OFFSET)
#define IMXRT_ENET_TCSR2 (IMXRT_ENET_BASE+IMXRT_ENET_TCSR2_OFFSET)
#define IMXRT_ENET_TCCR2 (IMXRT_ENET_BASE+IMXRT_ENET_TCCR2_OFFSET)
#define IMXRT_ENET_TCSR3 (IMXRT_ENET_BASE+IMXRT_ENET_TCSR3_OFFSET)
#define IMXRT_ENET_TCCR3 (IMXRT_ENET_BASE+IMXRT_ENET_TCCR3_OFFSET)
/* Register Bit Definitions *****************************************************************/
/* Interrupt Event Register, Interrupt Mask Register */
/* Bits 0-14: Reserved */
#define ENET_INT_TS_TIMER (1 << 15) /* Bit 15: Timestamp timer */
#define ENET_INT_TS_AVAIL (1 << 16) /* Bit 16: Transmit timestamp available */
#define ENET_INT_WAKEUP (1 << 17) /* Bit 17: Node wake-up request indication */
#define ENET_INT_PLR (1 << 18) /* Bit 18: Payload receive error */
#define ENET_INT_UN (1 << 19) /* Bit 19: Transmit FIFO underrun */
#define ENET_INT_RL (1 << 20) /* Bit 20: Collision Retry Limit */
#define ENET_INT_LC (1 << 21) /* Bit 21: Late Collision */
#define ENET_INT_EBERR (1 << 22) /* Bit 22: Ethernet Bus Error */
#define ENET_INT_MII (1 << 23) /* Bit 23: MII Interrupt */
#define ENET_INT_RXB (1 << 24) /* Bit 24: Receive Buffer Interrupt */
#define ENET_INT_RXF (1 << 25) /* Bit 25: Receive Frame Interrupt */
#define ENET_INT_TXB (1 << 26) /* Bit 26: Transmit Buffer Interrupt */
#define ENET_INT_TXF (1 << 27) /* Bit 27: Transmit Frame Interrupt */
#define ENET_INT_GRA (1 << 28) /* Bit 28: Graceful Stop Complete */
#define ENET_INT_BABT (1 << 29) /* Bit 29: Babbling Transmit Error */
#define ENET_INT_BABR (1 << 30) /* Bit 30: Babbling Receive Error */
/* Bit 31: Reserved */
/* Receive Descriptor Active Register */
/* Bits 0-23: Reserved */
#define ENET_RDAR (1 << 24) /* Bit 24: Receive descriptor active */
/* Bits 25-31: Reserved */
/* Transmit Descriptor Active Register */
/* Bits 0-23: Reserved */
#define ENET_TDAR (1 << 24) /* Bit 24: Transmit descriptor active */
/* Bits 25-31: Reserved */
/* Ethernet Control Register */
#define ENET_ECR_RESET (1 << 0) /* Bit 0: Ethernet MAC reset */
#define ENET_ECR_ETHEREN (1 << 1) /* Bit 1: Ethernet enable */
#define ENET_ECR_MAGICEN (1 << 2) /* Bit 2: Magic packet detection enable */
#define ENET_ECR_SLEEP (1 << 3) /* Bit 3: Sleep mode enable */
#define ENET_ECR_EN1588 (1 << 4) /* Bit 4: EN1588 enable */
/* Bit 5: Reserved */
#define ENET_ECR_DBGEN (1 << 6) /* Bit 6: Debug enable */
#define ENET_ECR_STOPEN (1 << 7) /* Bit 7: STOPEN Signal Control */
#ifdef IMXRT_ENET_HAS_DBSWAP
#define ENET_ECR_DBSWP (1 << 8) /* Bit 8: Swap bytes */
#endif
/* Bits 9-31: Reserved */
/* MII Management Frame Register */
#define ENET_MMFR_DATA_SHIFT (0) /* Bits 0-15: Management frame data */
#define ENET_MMFR_DATA_MASK (0xffff << ENET_MMFR_DATA_SHIFT)
#define ENET_MMFR_TA_SHIFT (16) /* Bits 16-17: Turn around */
#define ENET_MMFR_TA_MASK (3 << ENET_MMFR_TA_SHIFT)
#define ENET_MMFR_RA_SHIFT (18) /* Bits 18-22: Register address */
#define ENET_MMFR_RA_MASK (31 << ENET_MMFR_RA_SHIFT)
#define ENET_MMFR_PA_SHIFT (23) /* Bits 23-27: PHY address */
#define ENET_MMFR_PA_MASK (31 << ENET_MMFR_PA_SHIFT)
#define ENET_MMFR_OP_SHIFT (28) /* Bits 28-29: Operation code */
#define ENET_MMFR_OP_MASK (3 << ENET_MMFR_OP_SHIFT)
# define ENET_MMFR_OP_WRNOTMII (0 << ENET_MMFR_OP_SHIFT) /* Write frame, not MII compliant */
# define ENET_MMFR_OP_WRMII (1 << ENET_MMFR_OP_SHIFT) /* Write frame, MII management frame */
# define ENET_MMFR_OP_RDMII (2 << ENET_MMFR_OP_SHIFT) /* Read frame, MII management frame */
# define ENET_MMFR_OP_RdNOTMII (3 << ENET_MMFR_OP_SHIFT) /* Read frame, not MII compliant */
#define ENET_MMFR_ST_SHIFT (30) /* Bits 30-31: Start of frame delimiter */
#define ENET_MMFR_ST_MASK (3 << ENET_MMFR_ST_SHIFT)
/* MII Speed Control Register */
/* Bit 0: Reserved */
#define ENET_MSCR_MII_SPEED_SHIFT (1) /* Bits 1-6: MII speed */
#define ENET_MSCR_MII_SPEED_MASK (63 << ENET_MSCR_MII_SPEED_SHIFT)
#define ENET_MSCR_DIS_PRE (1 << 7) /* Bit 7: Disable preamble */
#define ENET_MSCR_HOLDTIME_SHIFT (8) /* Bits 8-10: Holdtime on MDIO output */
#define ENET_MSCR_HOLDTIME_MASK (7 << ENET_MSCR_HOLDTIME_SHIFT)
# define ENET_MSCR_HOLDTIME_1CYCLE (0 << ENET_MSCR_HOLDTIME_SHIFT) /* 1 internal module clock cycle */
# define ENET_MSCR_HOLDTIME_2CYCLES (1 << ENET_MSCR_HOLDTIME_SHIFT) /* 2 internal module clock cycles */
# define ENET_MSCR_HOLDTIME_3CYCLES (2 << ENET_MSCR_HOLDTIME_SHIFT) /* 3 internal module clock cycles */
# define ENET_MSCR_HOLDTIME_8CYCLES (7 << ENET_MSCR_HOLDTIME_SHIFT) /* 8 internal module clock cycles */
/* Bits 11-31: Reserved */
/* MIB Control Register */
/* Bits 0-28: Reserved */
#define ENET_MIBC_MIB_CLEAR (1 << 29) /* Bit 29: MIB clear */
#define ENET_MIBC_MIB_IDLE (1 << 30) /* Bit 30: MIB idle */
#define ENET_MIBC_MIB_DIS (1 << 31) /* Bit 31: Disable MIB logic */
/* Receive Control Register */
#define ENET_RCR_LOOP (1 << 0) /* Bit 0: Internal loopback */
#define ENET_RCR_DRT (1 << 1) /* Bit 1: Disable receive on transmit */
#define ENET_RCR_MII_MODE (1 << 2) /* Bit 2: Media independent interface mode */
#define ENET_RCR_PROM (1 << 3) /* Bit 3: Promiscuous mode */
#define ENET_RCR_BC_REJ (1 << 4) /* Bit 4: Broadcast frame reject */
#define ENET_RCR_FCE (1 << 5) /* Bit 5: Flow control enable */
/* Bits 6-7: Reserved */
#define ENET_RCR_RMII_MODE (1 << 8) /* Bit 8: RMII mode enable */
#define ENET_RCR_RMII_10T (1 << 9) /* Bit 9: Enables 10-Mbps mode of the RMII */
/* Bits 10-11: Reserved */
#define ENET_RCR_PADEN (1 << 12) /* Bit 12: Enable frame padding remove on receive */
#define ENET_RCR_PAUFWD (1 << 13) /* Bit 13: Terminate/forward pause frames */
#define ENET_RCR_CRCFWD (1 << 14) /* Bit 14: Terminate/forward received CRC */
#define ENET_RCR_CFEN (1 << 15) /* Bit 15: MAC control frame enable */
#define ENET_RCR_MAX_FL_SHIFT (16) /* Bits 16-29: Maximum frame length */
#define ENET_RCR_MAX_FL_MASK (0x3fff << ENET_RCR_MAX_FL_SHIFT)
#define ENET_RCR_NLC (1 << 30) /* Bit 30: Payload length check disable */
#define ENET_RCR_GRS (1 << 31) /* Bit 31: Graceful receive stopped */
/* Transmit Control Register */
#define ENET_TCR_GTS (1 << 0) /* Bit 0: Graceful transmit stop */
/* Bit 1: Reserved */
#define ENET_TCR_ADDINS (1 << 8) /* Bit 8: Set MAC address on transmit */
#define ENET_TCR_FDEN (1 << 2) /* Bit 2: Full duplex enable */
#define ENET_TCR_TFC_PAUSE (1 << 3) /* Bit 3: Transmit frame control pause */
#define ENET_TCR_RFC_PAUSE (1 << 4) /* Bit 4: Receive frame control pause */
#define ENET_TCR_ADDSEL_SHIFT (5) /* Bits 5-7: Source MAC address select on transmit */
#define ENET_TCR_ADDSEL_MASK (7 << ENET_TCR_ADDSEL_SHIFT)
# define ENET_TCR_ADDSEL_PADDR12 (0 << ENET_TCR_ADDSEL_SHIFT) /* Node MAC address programmed on PADDR1/2 registers */
#define ENET_TCR_CRCFWD (1 << 9) /* Bit 9: Forward frame from application with CRC */
/* Bits 10-31: Reserved */
/* Physical Address Lower/Upper Register (32-bits of 48-address) */
/* Physical Address Upper Register */
#define ENET_PAUR_TYPE_SHIFT (0) /* Bits 0-15: Type field in PAUSE frame */
#define ENET_PAUR_TYPE_MASK (0xffff << ENET_PAUR_TYPE_MASK)
#define ENET_PAUR_PADDR2_SHIFT (16) /* Bits 16-31: Bytes 4 and 5 of the 6-byte address */
#define ENET_PAUR_PADDR2_MASK (0xffff << ENET_PAUR_PADDR2_SHIFT)
/* Opcode/Pause Duration Register */
#define ENET_OPD_PAUSE_DUR_SHIFT (0) /* Bits 0-15: Pause duration */
#define ENET_OPD_PAUSE_DUR_MASK (0xffff << ENET_OPD_PAUSE_DUR_SHIFT)
#define ENET_OPD_OPCODE_SHIFT (16) /* Bits 16-31: Opcode field in PAUSE frames */
#define ENET_OPD_OPCODE_MASK (0xffff << ENET_OPD_OPCODE_SHIFT)
/* Descriptor Individual Uupper/Lower Address Register (64-bit address in two 32-bit registers) */
/* Descriptor Group Upper/Lower Address Register (64-bit address in two 32-bit registers) */
/* Transmit Interrupt Coalescing Register */
#define ENET_TXIC_ICTT_SHIFT (0) /* Bits 0-15: Interrupt coalescing timer threshold */
#define ENET_TXIC_ICTT_SHIFT_MASK (0xffff << ENET_TXIC_ICTT_SHIFT)
/* Bits 16-19: Reserved */
#define ENET_TXIC_ICFT_SHIFT (20) /* Bits 0-15: Interrupt coalescing timer threshold */
#define ENET_TXIC_ICFT_SHIFT_MASK (0xff << ENET_TXIC_ICFT_SHIFT)
#define ENET_TXIC_ICTT_ICCS (1 << 30) /* Bit 30: Interrupt Coalescing Timer Clock Source Select */
#define ENET_TXIC_ICTT_ICEN (1 << 31) /* Bit 31: Eable/disabel Interrupt Coalescing */
/* Receive Interrupt Coalescing Register */
#define ENET_RXIC_ICTT_SHIFT (0) /* Bits 0-15: Interrupt coalescing timer threshold */
#define ENET_RXIC_ICTT_SHIFT_MASK (0xffff << ENET_TXIC_ICTT_SHIFT)
/* Bits 16-19: Reserved */
#define ENET_RXIC_ICFT_SHIFT (20) /* Bits 0-15: Interrupt coalescing timer threshold */
#define ENET_RXIC_ICFT_SHIFT_MASK (0xff << ENET_TXIC_ICFT_SHIFT)
#define ENET_RXIC_ICTT_ICCS (1 << 30) /* Bit 30: Interrupt Coalescing Timer Clock Source Select */
#define ENET_RXIC_ICTT_ICEN (1 << 31) /* Bit 31: Eable/disabel Interrupt Coalescing */
/* Transmit FIFO Watermark Register */
#define ENET_TFWR_TFWR_SHIFT (0) /* Bits 0-5: Transmit FIFO write */
/* Bits 6-7: Reserved */
#define ENET_TFWR_TFWR_MASK (63 << ENET_TFWR_TFWR_SHIFT)
#define ENET_TFWR_STRFWD (1 << 8) /* Bit 8: Store and forward enable */
/* Bits 9-31: Reserved */
/* Receive Descriptor Ring Start Register */
/* Bits 0-2: Reserved */
#define ENET_RDSR_SHIFT (3) /* Bits 3-31: Start of the receive buffer descriptor queue */
#define ENET_RDSR_MASK (0xfffffff8)
/* Transmit Buffer Descriptor Ring Start Register */
/* Bits 0-2: Reserved */
#define ENET_TDSR_SHIFT (3) /* Bits 3-31: Start of the transmit buffer descriptor queue */
#define ENET_TDSR_MASK (0xfffffff8)
/* Maximum Receive Buffer Size Register */
/* Bits 14-31: Reserved */
#define ENET_MRBR_SHIFT (4) /* Bits 4-13: Receive buffer size in bytes */
#define ENET_MRBR_MASK (0x3ff << ENET_MRBR_SHIFT)
/* Bits 0-3: Reserved */
/* Receive FIFO Section Full Threshold */
/* Bits 8-31: Reserved */
#define ENET_RSFL_SHIFT (0) /* Bits 0-7: Value of receive FIFO section full threshold */
#define ENET_RSFL_MASK (0xff << ENET_RSFL_SHIFT)
/* Receive FIFO Section Empty Threshold */
#define ENET_RSEM_SHIFT (0) /* Bits 0-7: Value of the receive FIFO section empty threshold */
#define ENET_RSEM_MASK (0xff << ENET_RSEM_SHIFT)
/* Bits 8-31: Reserved */
/* Receive FIFO Almost Empty Threshold */
#define ENET_RAEM_SHIFT (0) /* Bits 0-7: Value of the receive FIFO almost empty threshold */
#define ENET_RAEM_MASK (0xff << ENET_RAEM_SHIFT)
/* Bits 8-31: Reserved */
/* Receive FIFO Almost Full Threshold */
#define ENET_RAFL_SHIFT (0) /* Bits 0-7: Value of the receive FIFO almost full threshold */
#define ENET_RAFL_MASK (0xff << ENET_RAFL_SHIFT)
/* Bits 8-31: Reserved */
/* Transmit FIFO Section Empty Threshold */
#define ENET_TSEM_SHIFT (0) /* Bits 0-7: Value of the transmit FIFO section empty threshold */
#define ENET_TSEM_MASK (0xff << ENET_TSEM_SHIFT)
/* Bits 8-31: Reserved */
/* Transmit FIFO Almost Empty Threshold */
#define ENET_TAEM_SHIFT (0) /* Bits 0-7: Value of the transmit FIFO section empty threshold */
#define ENET_TAEM_MASK (0xff << ENET_TAEM_SHIFT)
/* Bits 8-31: Reserved */
/* Transmit FIFO Almost Full Threshold */
#define ENET_TAFL_SHIFT (0) /* Bits 0-7: Value of the transmit FIFO section empty threshold */
#define ENET_TAFL_MASK (0xff << ENET_TAFL_SHIFT)
/* Bits 8-31: Reserved */
/* Transmit Inter-Packet Gap */
#define ENET_TIPG_SHIFT (0) /* Bits 0-4: Value of the transmit FIFO section empty threshold */
#define ENET_TIPG_MASK (31 << ENET_TIPG_SHIFT)
/* Bits 5-31: Reserved */
/* Frame Truncation Length */
#define ENET_FTRL_SHIFT (0) /* Bits 0-13: Value of the transmit FIFO section empty threshold */
#define ENET_FTRL_MASK (0x3fff << ENET_FTRL_SHIFT)
/* Bits 14-31: Reserved */
/* Transmit Accelerator Function Configuration */
#define ENET_TACC_SHIFT16 (1 << 0) /* Bit 0: TX FIFO shift-16 */
/* Bits 1-2: Reserved */
#define ENET_TACC_IPCHK (1 << 3) /* Bit 3: Enables insertion of IP header checksum */
#define ENET_TACC_PROCHK (1 << 4) /* Bit 4: Enables insertion of protocol checksum */
/* Bits 5-31: Reserved */
/* Receive Accelerator Function Configuration */
#define ENET_RACC_PADREM (1 << 0) /* Bit 0: Enable padding removal for short IP frames */
#define ENET_RACC_IPDIS (1 << 1) /* Bit 1: Enable discard of frames with wrong IPv4 header checksum */
#define ENET_RACC_PRODIS (1 << 2) /* Bit 2: Enable discard of frames with wrong protocol checksum */
/* Bits 3-5: Reserved */
#define ENET_RACC_LINEDIS (1 << 6) /* Bit 6: Enable discard of frames with MAC layer errors */
#define ENET_RACC_SHIFT16 (1 << 7) /* Bit 7: RX FIFO shift-16 */
/* Bits 8-31: Reserved */
/* Timer Control Register */
#define ENET_ATCR_EN (1 << 0) /* Bit 0: Enable timer */
/* Bit 1: Reserved */
#define ENET_ATCR_OFFEN (1 << 2) /* Bit 2: Enable one-shot offset event */
#define ENET_ATCR_OFFRST (1 << 3) /* Bit 3: Reset timer on offset event */
#define ENET_ATCR_PEREN (1 << 4) /* Bit 4: Enable periodical event */
/* Bits 5-6: Reserved */
#define ENET_ATCR_PINPER (1 << 7) /* Bit 7: Enables event signal output assertion on period event */
/* Bit 8: Reserved */
#define ENET_ATCR_RESTART (1 << 9) /* Bit 9: Reset timer */
/* Bit 10: Reserved */
#define ENET_ATCR_CAPTURE (1 << 11) /* Bit 11: Capture timer value */
/* Bit 12: Reserved */
#define ENET_ATCR_SLAVE (1 << 13) /* Bit 13: Enable timer slave mode */
/* Bits 14-31: Reserved */
/* Timer Value Register (32-bit timer value) */
/* Timer Offset Register (32-bit offset value) */
/* Timer Period Register (32-bit timer period) */
/* Timer Correction Register */
#define ENET_ATCOR_MASK (0x7fffffff) /* Bits 0-3: Correction counter wrap-around value */
/* Bit 31: Reserved */
/* Time-Stamping Clock Period Register */
#define ENET_ATINC_INC_SHIFT (0) /* Bits 0-6: Clock period of the timestamping clock (ts_clk) in nanoseconds */
#define ENET_ATINC_INC_MASK (0x7f << ENET_ATINC_INC_SHIFT)
/* Bit 7: Reserved */
#define ENET_ATINC_INC_CORR_SHIFT (8) /* Bits 8-14: Correction increment value */
#define ENET_ATINC_INC_CORR_MASK (0x7f << ENET_ATINC_INC_CORR_SHIFT)
/* Bits 15-31: Reserved */
/* Timestamp of Last Transmitted Frame (32-bit timestamp) */
/* Timer Global Status Register */
#define ENET_TGSR_TF0 (1 << 0) /* Bit 0: Copy of Timer Flag for channel 0 */
#define ENET_TGSR_TF1 (1 << 1) /* Bit 1: Copy of Timer Flag for channel 1 */
#define ENET_TGSR_TF2 (1 << 2) /* Bit 2: Copy of Timer Flag for channel 2 */
#define ENET_TGSR_TF3 (1 << 3) /* Bit 3: Copy of Timer Flag for channel 3 */
/* Bits 14-31: Reserved */
/* Timer Control Status Register n */
#define ENET_TCSR_TDRE (1 << 0) /* Bit 0: Timer DMA Request Enable */
/* Bit 1: Reserved */
#define ENET_TCSR_TMODE_SHIFT (2) /* Bits 2-5: Timer Mode */
#define ENET_TCSR_TMODE_MASK (15 << ENET_TCSR_TMODE_SHIFT)
# define ENET_TCSR_TMODE_DISABLED (0 << ENET_TCSR_TMODE_SHIFT) /* Disabled */
# define ENET_TCSR_TMODE_ICRISING (1 << ENET_TCSR_TMODE_SHIFT) /* Input Capture on rising edge */
# define ENET_TCSR_TMODE_ICFALLLING (2 << ENET_TCSR_TMODE_SHIFT) /* Input Capture on falling edge */
# define ENET_TCSR_TMODE_ICBOTH (3 << ENET_TCSR_TMODE_SHIFT) /* Input Capture on both edges */
# define ENET_TCSR_TMODE_OCSW (4 << ENET_TCSR_TMODE_SHIFT) /* Output Compare, S/W only */
# define ENET_TCSR_TMODE_OCTOGGLE (5 << ENET_TCSR_TMODE_SHIFT) /* Output Compare, toggle on compare */
# define ENET_TCSR_TMODE_OCCLR (6 << ENET_TCSR_TMODE_SHIFT) /* Output Compare, clear on compare */
# define ENET_TCSR_TMODE_OCSET (7 << ENET_TCSR_TMODE_SHIFT) /* Output Compare, set on compare */
# define ENET_TCSR_TMODE_OCSETCLR (9 << ENET_TCSR_TMODE_SHIFT) /* Output Compare, set on compare, clear on overflow */
# define ENET_TCSR_TMODE_OCCLRSET (10 << ENET_TCSR_TMODE_SHIFT) /* Output Compare, clear on compare, set on overflow */
# define ENET_TCSR_TMODE_PCPULSEL (14 << ENET_TCSR_TMODE_SHIFT) /* Output Compare, pulse low on compare */
# define ENET_TCSR_TMODE_PCPULSEH (15 << ENET_TCSR_TMODE_SHIFT) /* Output Compare, pulse high on compare */
#define ENET_TCSR_TIE (1 << 6) /* Bit 6: Timer interrupt enable */
#define ENET_TCSR_TF (1 << 7) /* Bit 7: Timer Flag */
/* Bits 8-31: Reserved */
/* Timer Compare Capture Register (32-bit compare value) */
/* Buffer Descriptors ***********************************************************************/
/* Endian-independent descriptor offsets */
#define DESC_STATUS1_OFFSET (0)
#define DESC_LENGTH_OFFSET (2)
#define DESC_DATAPTR_OFFSET (4)
#define DESC_LEGACY_LEN (8)
#define DESC_STATUS2_OFFSET (8)
#define DESC_LENPROTO_OFFSET (12)
#define DESC_CHECKSUM_OFFSET (14)
#define DESC_BDU_OFFSET (16)
#define DESC_TIMESTAMP_OFFSET (20)
#define DESC_ENHANCED_LEN (32)
/* Legacy/Common TX Buffer Descriptor Bit Definitions.
*
* The descriptors are represented by structures Unfortunately, when the
* structures are overlayed on the data, the bytes are reversed because
* the underlying hardware writes the data in big-endian byte order.
*/
#ifdef IMXRT_ENET_HAS_DBSWAP
# ifndef CONFIG_ENDIAN_BIG
# define IMXRT_USE_DBSWAP
# endif
#else
# ifndef CONFIG_ENDIAN_BIG
# define IMXRT_BUFFERS_SWAP
# endif
#endif
#ifndef IMXRT_BUFFERS_SWAP
# define TXDESC_ABC (1 << 9) /* Legacy */
# define TXDESC_TC (1 << 10) /* Common */
# define TXDESC_L (1 << 11) /* Common */
# define TXDESC_TO2 (1 << 12) /* Common */
# define TXDESC_W (1 << 13) /* Common */
# define TXDESC_TO1 (1 << 14) /* Common */
# define TXDESC_R (1 << 15) /* Common */
#else
# define TXDESC_ABC (1 << 1) /* Legacy */
# define TXDESC_TC (1 << 2) /* Common */
# define TXDESC_L (1 << 3) /* Common */
# define TXDESC_TO2 (1 << 4) /* Common */
# define TXDESC_W (1 << 5) /* Common */
# define TXDESC_TO1 (1 << 6) /* Common */
# define TXDESC_R (1 << 7) /* Common */
#endif
/* Enhanced (only) TX Buffer Descriptor Bit Definitions */
#ifndef IMXRT_BUFFERS_SWAP
# define TXDESC_TSE (1 << 8)
# define TXDESC_OE (1 << 9)
# define TXDESC_LCE (1 << 10)
# define TXDESC_FE (1 << 11)
# define TXDESC_EE (1 << 12)
# define TXDESC_UE (1 << 13)
# define TXDESC_TXE (1 << 15)
# define TXDESC_IINS (1 << 27)
# define TXDESC_PINS (1 << 28)
# define TXDESC_TS (1 << 29)
# define TXDESC_INT (1 << 30)
# define TXDESC_BDU (1 << 31)
#else
# define TXDESC_IINS (1 << 3)
# define TXDESC_PINS (1 << 4)
# define TXDESC_TS (1 << 5)
# define TXDESC_INT (1 << 6)
# define TXDESC_TSE (1 << 16)
# define TXDESC_OE (1 << 17)
# define TXDESC_LCE (1 << 18)
# define TXDESC_FE (1 << 19)
# define TXDESC_EE (1 << 20)
# define TXDESC_UE (1 << 21)
# define TXDESC_TXE (1 << 23)
# define TXDESC_BDU (1 << 7)
#endif
/* Legacy (and Common) RX Buffer Descriptor Bit Definitions */
#ifndef IMXRT_BUFFERS_SWAP
# define RXDESC_TR (1 << 0)
# define RXDESC_OV (1 << 1)
# define RXDESC_CR (1 << 2)
# define RXDESC_NO (1 << 4)
# define RXDESC_LG (1 << 5)
# define RXDESC_MC (1 << 6)
# define RXDESC_BC (1 << 7)
# define RXDESC_M (1 << 8)
# define RXDESC_L (1 << 11)
# define RXDESC_R02 (1 << 12)
# define RXDESC_W (1 << 13)
# define RXDESC_R01 (1 << 14)
# define RXDESC_E (1 << 15)
#else
# define RXDESC_M (1 << 0)
# define RXDESC_L (1 << 3)
# define RXDESC_R02 (1 << 4)
# define RXDESC_W (1 << 5)
# define RXDESC_R01 (1 << 6)
# define RXDESC_E (1 << 7)
# define RXDESC_TR (1 << 8)
# define RXDESC_OV (1 << 9)
# define RXDESC_CR (1 << 10)
# define RXDESC_NO (1 << 12)
# define RXDESC_LG (1 << 13)
# define RXDESC_MC (1 << 14)
# define RXDESC_BC (1 << 15)
#endif
/* Enhanced (only) TX Buffer Descriptor Bit Definitions */
#ifndef IMXRT_BUFFERS_SWAP
# define RXDESC_FRAG (1 << 0)
# define RXDESC_IPV6 (1 << 1)
# define RXDESC_VLAN (1 << 2)
# define RXDESC_PCR (1 << 4)
# define RXDESC_ICE (1 << 5)
# define RXDESC_INT (1 << 23)
# define RXDESC_UC (1 << 24)
# define RXDESC_CE (1 << 25)
# define RXDESC_PE (1 << 26)
# define RXDESC_ME (1 << 31)
# define RXDESC_BDU (1 << 31)
#else
# define RXDESC_UC (1 << 0)
# define RXDESC_CE (1 << 1)
# define RXDESC_PE (1 << 2)
# define RXDESC_ME (1 << 7)
# define RXDESC_INT (1 << 15)
# define RXDESC_FRAG (1 << 24)
# define RXDESC_IPV6 (1 << 25)
# define RXDESC_VLAN (1 << 26)
# define RXDESC_PCR (1 << 28)
# define RXDESC_ICE (1 << 29)
# define RXDESC_BDU (1 << 7)
#endif
/********************************************************************************************
* Public Types
********************************************************************************************/
/* Buffer Descriptors ***********************************************************************/
/* Legacy Buffer Descriptor */
#ifdef CONFIG_ENET_ENHANCEDBD
#ifdef IMXRT_USE_DBSWAP
/* When DBSWP is used to swap the bytes in hardware, it is done 32-bits
* at a time. Therefore, all 16 bit elements need to be swapped to
* compensate.
*/
struct enet_desc_s
{
uint16_t length; /* Data length */
uint16_t status1; /* Control and status */
uint8_t *data; /* Buffer address */
uint32_t status2; /* Extended status */
uint16_t checksum; /* Payload checksum */
uint16_t lenproto; /* Header length + Protocol type */
uint32_t bdu; /* BDU */
uint32_t timestamp; /* Time stamp */
uint32_t reserved1; /* unused */
uint32_t reserved2; /* unused */
};
#else
struct enet_desc_s
{
uint16_t status1; /* Control and status */
uint16_t length; /* Data length */
uint8_t *data; /* Buffer address */
uint32_t status2; /* Extended status */
uint16_t lenproto; /* Header length + Protocol type */
uint16_t checksum; /* Payload checksum */
uint32_t bdu; /* BDU */
uint32_t timestamp; /* Time stamp */
uint32_t reserved1; /* unused */
uint32_t reserved2; /* unused */
};
#endif /* IMXRT_USE_DBSWAP */
#else /* CONFIG_ENET_ENHANCEDBD */
#ifdef IMXRT_USE_DBSWAP
struct enet_desc_s
{
uint16_t length; /* Data length */
uint16_t status1; /* Control and status */
uint8_t *data; /* Buffer address */
};
#else
struct enet_desc_s
{
uint16_t status1; /* Control and status */
uint16_t length; /* Data length */
uint8_t *data; /* Buffer address */
};
#endif /* IMXRT_USE_DBSWAP */
#endif /* CONFIG_ENET_ENHANCEDBD */
/********************************************************************************************
* Public Data
********************************************************************************************/
/********************************************************************************************
* Public Functions
********************************************************************************************/
#endif /* __ARCH_ARM_SRC_IMXRT_CHIP_IMXRT_ENET_H */

3
arch/arm/src/imxrt/chip/imxrt_iomuxc.h
View File

@ -1359,7 +1359,8 @@
# define PADMUX_MUXMODE_ALT4 (4 << PADMUX_MUXMODE_SHIFT)
# define PADMUX_MUXMODE_ALT5 (5 << PADMUX_MUXMODE_SHIFT)
# define PADMUX_MUXMODE_ALT7 (7 << PADMUX_MUXMODE_SHIFT)
#define PADMUX_SION (1 << 4) /* Bit 4: Software Input On Field */
#define PADMUX_SION_SHIFT (4) /* Bit 4: Software Input On Field */
# define PADMUX_SION (1 << PADMUX_SION_SHIFT)
/* Pad Control Registers */

22
arch/arm/src/imxrt/imxrt_config.h
View File

@ -199,6 +199,28 @@
# undef CONFIG_LPUART7_FLOWCONTROL
# undef CONFIG_LPUART8_FLOWCONTROL
/* Ethernet controller configuration */
#ifndef CONFIG_IMXRT_ENET_NRXBUFFERS
# define CONFIG_IMXRT_ENET_NRXBUFFERS 6
#endif
#ifndef CONFIG_IMXRT_ENET_NTXBUFFERS
# define CONFIG_IMXRT_ENET_NTXBUFFERS 2
#endif
#ifndef CONFIG_IMXRT_ENET_NETHIFS
# define CONFIG_IMXRT_ENET_NETHIFS 1
#endif
#define IMXRT_ENET_HAS_DBSWAP 1
/* EMAC Default Interrupt Priorities */
#ifndef CONFIG_IMXRT_ENET_PRIO
# define CONFIG_IMXRT_ENET_PRIO NVIC_SYSH_PRIORITY_DEFAULT
#endif
/************************************************************************************
* Public Functions
************************************************************************************/

2287
arch/arm/src/imxrt/imxrt_enet.c Normal file
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File diff suppressed because it is too large Load Diff

124
arch/arm/src/imxrt/imxrt_enet.h Normal file
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@ -0,0 +1,124 @@
/************************************************************************************
* arch/arm/src/imxrt/imxrt_enet.h
*
* Copyright (C) 2018 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
************************************************************************************/
#ifndef __ARCH_ARM_SRC_IMXRT_IMXRT_ENET_H
#define __ARCH_ARM_SRC_IMXRT_IMXRT_ENET_H
/************************************************************************************
* Included Files
************************************************************************************/
#include <nuttx/config.h>
#include "chip/imxrt_enet.h"
#ifdef CONFIG_IMXRT_ENET
/************************************************************************************
* Pre-processor Definitions
************************************************************************************/
/* Definitions for use with imxrt_phy_boardinitialize */
#define EMAC_INTF 0
/************************************************************************************
* Public Functions
************************************************************************************/
#ifndef __ASSEMBLY__
#undef EXTERN
#if defined(__cplusplus)
#define EXTERN extern "C"
extern "C"
{
#else
#define EXTERN extern
#endif
/************************************************************************************
* Function: up_netinitialize
*
* Description:
* Initialize the first network interface. If there are more than one
* interface in the chip, then board-specific logic will have to provide
* this function to determine which, if any, Ethernet controllers should
* be initialized. Also prototyped in up_internal.h.
*
* Input Parameters:
* None
*
* Returned Value:
* OK on success; Negated errno on failure.
*
* Assumptions:
* Called very early in the initialization sequence.
*
************************************************************************************/
void up_netinitialize(void);
/************************************************************************************
* Function: imxrt_phy_boardinitialize
*
* Description:
* Some boards require specialized initialization of the PHY before it can be
* used. This may include such things as configuring GPIOs, resetting the PHY,
* etc. If CONFIG_IMXRT_ENET_PHYINIT is defined in the configuration then the
* board specific logic must provide imxrt_phyinitialize(); The i.MX RT Ethernet
* driver will call this function one time before it first uses the PHY.
*
* Input Parameters:
* intf - Always zero for now.
*
* Returned Value:
* OK on success; Negated errno on failure.
*
************************************************************************************/
#ifdef CONFIG_IMXRT_ENET_PHYINIT
int imxrt_phy_boardinitialize(int intf);
#endif
#undef EXTERN
#if defined(__cplusplus)
}
#endif
#endif /* __ASSEMBLY__ */
#endif /* CONFIG_IMXRT_ENET */
#endif /* __ARCH_ARM_SRC_IMXRT_IMXRT_ENET_H */

11
arch/arm/src/imxrt/imxrt_gpio.c
View File

@ -463,11 +463,16 @@ static inline int imxrt_gpio_configperiph(gpio_pinset_t pinset)
/* Configure pin as a peripheral */
index = ((pinset & GPIO_PADMUX_MASK) >> GPIO_PADMUX_SHIFT);
index = ((pinset & GPIO_PADMUX_MASK) >> GPIO_PADMUX_SHIFT);
regaddr = imxrt_padmux_address(index);
value = ((pinset & GPIO_ALT_MASK) >> GPIO_ALT_SHIFT);
regval = (value << PADMUX_MUXMODE_SHIFT);
value = ((pinset & GPIO_ALT_MASK) >> GPIO_ALT_SHIFT);
#if GPIO_SION_SHIFT >= PADMUX_SION_SHIFT
value |= ((pinset & GPIO_SION_MASK) >> (GPIO_SION_SHIFT - PADMUX_SION_SHIFT));
#else
value |= ((pinset & GPIO_SION_MASK) << (PADMUX_SION_SHIFT - GPIO_SION_SHIFT));
#endif
regval = (value << PADMUX_MUXMODE_SHIFT);
putreg32(regval, regaddr);

15
arch/arm/src/imxrt/imxrt_gpio.h
View File

@ -55,8 +55,8 @@
*
* ENCODING IIXX XXXX XXXX XXXX MMMM MMMM MMMM MMMM
* GPIO INPUT 00.. ..EE .GGP PPPP MMMM MMMM MMMM MMMM
* GPIO OUTPUT 01V. .... .GGP PPPP MMMM MMMM MMMM MMMM
* PERIPHERAL 10AA A... IIII IIII MMMM MMMM MMMM MMMM
* GPIO OUTPUT 01V. .S.. .GGP PPPP MMMM MMMM MMMM MMMM
* PERIPHERAL 10AA AS.. IIII IIII MMMM MMMM MMMM MMMM
*/
/* Input/Output Selection:
@ -136,7 +136,7 @@
/* Peripheral Alternate Function:
*
* PERIPHERAL 10AA A... .... .... MMMM MMMM MMMM MMMM
* PERIPHERAL ..AA A... .... .... .... .... .... ....
*/
#define GPIO_ALT_SHIFT (27) /* Bits 27-29: Peripheral alternate function */
@ -150,6 +150,15 @@
# define GPIO_ALT6 (6 << GPIO_ALT_SHIFT) /* Alternate function 6 */
# define GPIO_ALT7 (7 << GPIO_ALT_SHIFT) /* Alternate function 7 */
/* Peripheral Software Input On Field:
*
* PERIPHERAL .... .S.. .... .... .... .... .... ....
*/
#define GPIO_SION_SHIFT (26) /* Bits 26: Peripheral SION function */
#define GPIO_SION_MASK (1 << GPIO_SION_SHIFT)
# define GPIO_SION_ENABLE (1 << GPIO_SION_SHIFT) /* enable SION */
/* Interrupt edge/level configuration
*
* GPIO INPUT ... ..EE .... .... .... .... .... ....

10
configs/imxrt1050-evk/README.txt
View File

@ -166,6 +166,16 @@ Configurations
Configuration sub-directories
-----------------------------
netnsh:
This configuration is similar to the nsh configuration except that is
has networking enabled, both IPv4 and IPv6. This NSH configuration is
focused on network-related testing.
NOTES:
1. LED support is disabled because there is a conflict between the LED
GPIO and PHY pin usage.
nsh:
Configures the NuttShell (nsh) located at examples/nsh. This NSH

60
configs/imxrt1050-evk/netnsh/defconfig Normal file
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@ -0,0 +1,60 @@
# CONFIG_ARCH_LEDS is not set
CONFIG_ARCH="arm"
CONFIG_ARCH_BOARD="imxrt1050-evk"
CONFIG_ARCH_BOARD_IMXRT1050_EVK=y
CONFIG_ARCH_CHIP_IMXRT=y
CONFIG_ARCH_CHIP_MIMXRT1052DVL6A=y
CONFIG_ARCH_STACKDUMP=y
CONFIG_ARMV7M_DCACHE=y
CONFIG_ARMV7M_DCACHE_WRITETHROUGH=y
CONFIG_ARMV7M_ICACHE=y
CONFIG_ARMV7M_USEBASEPRI=y
CONFIG_BOARD_LOOPSPERMSEC=104926
CONFIG_BUILTIN=y
CONFIG_ETH0_PHY_KSZ8081=y
CONFIG_EXAMPLES_NSH=y
CONFIG_FS_PROCFS=y
CONFIG_IDLETHREAD_STACKSIZE=2048
CONFIG_IMXRT_ENET=y
CONFIG_IMXRT_LPUART1=y
CONFIG_INTELHEX_BINARY=y
CONFIG_LPUART1_SERIAL_CONSOLE=y
CONFIG_MAX_TASKS=16
CONFIG_MAX_WDOGPARMS=2
CONFIG_NET=y
CONFIG_NETDEV_STATISTICS=y
CONFIG_NETUTILS_TELNETD=y
CONFIG_NET_ARP_SEND=y
CONFIG_NET_BROADCAST=y
CONFIG_NET_HOSTNAME="i.MXRT1050 EVK"
CONFIG_NET_ICMP=y
CONFIG_NET_ICMP_SOCKET=y
CONFIG_NET_ICMPv6=y
CONFIG_NET_ICMPv6_NEIGHBOR=y
CONFIG_NET_ICMPv6_SOCKET=y
CONFIG_NET_IPv6=y
CONFIG_NET_SOCKOPTS=y
CONFIG_NET_STATISTICS=y
CONFIG_NET_TCP=y
CONFIG_NET_TCPBACKLOG=y
CONFIG_NET_TCP_WRITE_BUFFERS=y
CONFIG_NET_UDP=y
CONFIG_NET_UDP_WRITE_BUFFERS=y
CONFIG_NFILE_DESCRIPTORS=8
CONFIG_NFILE_STREAMS=8
CONFIG_NSH_ARCHINIT=y
CONFIG_NSH_BUILTIN_APPS=y
CONFIG_NSH_FILEIOSIZE=512
CONFIG_NSH_LINELEN=64
CONFIG_NSH_NOMAC=y
CONFIG_NSH_READLINE=y
CONFIG_PREALLOC_MQ_MSGS=4
CONFIG_PREALLOC_WDOGS=16
CONFIG_RAM_SIZE=524288
CONFIG_RAM_START=0x20200000
CONFIG_SCHED_LPWORK=y
CONFIG_START_DAY=14
CONFIG_START_MONTH=3
CONFIG_SYSTEM_PING6=y
CONFIG_SYSTEM_PING=y
CONFIG_USER_ENTRYPOINT="nsh_main"

4
configs/imxrt1050-evk/src/Makefile
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@ -58,4 +58,8 @@ ifeq ($(CONFIG_ARCH_BUTTONS),y)
CSRCS += imxrt_buttons.c
endif
ifeq ($(CONFIG_IMXRT_ENET),y)
CSRCS += imxrt_ethernet.c
endif
include $(TOPDIR)/configs/Board.mk

33
configs/imxrt1050-evk/src/imxrt1050-evk.h
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@ -49,6 +49,7 @@
#include <nuttx/irq.h>
#include "imxrt_gpio.h"
#include "imxrt_iomuxc.h"
/****************************************************************************
* Pre-processor Definitions
@ -76,10 +77,11 @@
* must be configured as ALT5, GPIO1_IO09
*/
#define IOMUX_LED (IOMUX_PULL_NONE | IOMUX_CMOS_OUTPUT | IOMUX_DRIVE_40OHM | \
IOMUX_SPEED_MEDIUM | IOMUX_SLEW_SLOW)
#define GPIO_LED (GPIO_OUTPUT | GPIO_OUTPUT_ZERO | GPIO_PORT1 | GPIO_PIN9 | \
IOMUX_LED)
#define IOMUX_LED (IOMUX_PULL_NONE | IOMUX_CMOS_OUTPUT | \
IOMUX_DRIVE_40OHM | IOMUX_SPEED_MEDIUM | \
IOMUX_SLEW_SLOW)
#define GPIO_LED (GPIO_OUTPUT | GPIO_OUTPUT_ZERO | GPIO_PORT1 | \
GPIO_PIN9 | IOMUX_LED)
/* Buttons
*
@ -88,9 +90,28 @@
* 1. SW8 (IRQ88) GPIO5-00
*
*/
#define IOMUX_SW8 (IOMUX_SLEW_FAST | IOMUX_DRIVE_50OHM | \
IOMUX_SPEED_MEDIUM | IOMUX_PULL_UP_100K | \
_IOMUX_PULL_ENABLE)
#define GPIO_SW8 (GPIO_INTERRUPT | GPIO_INT_FALLINGEDGE | \
GPIO_PORT5 | GPIO_PIN0 | IOMUX_SW8)
#define GPIO_SW8 (GPIO_INTERRUPT | GPIO_INT_FALLINGEDGE | \
GPIO_PORT5 | GPIO_PIN0)
/* GPIOAD_B0_10 */
#define IOMUX_ENET_INT (IOMUX_SLEW_FAST | IOMUX_DRIVE_50OHM | \
IOMUX_SPEED_MEDIUM | IOMUX_PULL_UP_100K | \
_IOMUX_PULL_ENABLE)
#define GPIO_ENET_INT (GPIO_OUTPUT | GPIO_OUTPUT_ONE | \
GPIO_PORT1 | GPIO_PIN10 | IOMUX_ENET_INT)
#define GPIO_ENET_IRQ IMXRT_IRQ_GPIO1_10
/* GPIOAD_B0_09 */
#define IOMUX_ENET_RST (IOMUX_SLEW_FAST | IOMUX_DRIVE_50OHM | \
IOMUX_SPEED_MEDIUM | IOMUX_PULL_UP_100K | \
_IOMUX_PULL_ENABLE)
#define GPIO_ENET_RST (GPIO_OUTPUT | GPIO_OUTPUT_ZERO | \
GPIO_PORT1 | GPIO_PIN9 | IOMUX_ENET_RST)
/****************************************************************************
* Public Types

280
configs/imxrt1050-evk/src/imxrt_ethernet.c Normal file
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@ -0,0 +1,280 @@
/****************************************************************************
* configs/imxrt1050-evk/src/imxrt_ethernet.c
*
* Copyright (C) 2018 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
****************************************************************************/
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
/* Force verbose debug on in this file only to support unit-level testing. */
#ifdef CONFIG_NETDEV_PHY_DEBUG
# undef CONFIG_DEBUG_INFO
# define CONFIG_DEBUG_INFO 1
# undef CONFIG_DEBUG_NET
# define CONFIG_DEBUG_NET 1
#endif
#include <string.h>
#include <assert.h>
#include <debug.h>
#include <nuttx/irq.h>
#include <nuttx/arch.h>
#include "imxrt_gpio.h"
#include "imxrt_enet.h"
#include "imxrt1050-evk.h"
#ifdef CONFIG_IMXRT_ENET
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
#define IMXRT_ENET_DEVNAME "eth0"
/* Debug ********************************************************************/
/* Extra, in-depth debug output that is only available if
* CONFIG_NETDEV_PHY_DEBUG us defined.
*/
#ifdef CONFIG_NETDEV_PHY_DEBUG
# define phyerr _err
# define phywarn _warn
# define phyinfo _info
#else
# define phyerr(x...)
# define phywarn(x...)
# define phyinfo(x...)
#endif
/************************************************************************************
* Private Functions
************************************************************************************/
/************************************************************************************
* Name: imxrt_enet_phy_enable
************************************************************************************/
#ifdef CONFIG_IMXRT_GPIO1_0_15_IRQ
static void imxrt_enet_phy_enable(bool enable)
{
phyinfo("IRQ%d: enable=%d\n", GPIO_ENET_INT, enable);
if (enable)
{
up_enable_irq(GPIO_ENET_IRQ);
}
else
{
up_disable_irq(GPIO_ENET_IRQ);
}
}
#endif
/************************************************************************************
* Public Functions
************************************************************************************/
/************************************************************************************
* Function: imxrt_phy_boardinitialize
*
* Description:
* Some boards require specialized initialization of the PHY before it can be
* used. This may include such things as configuring GPIOs, resetting the PHY,
* etc. If CONFIG_IMXRT_ENET_PHYINIT is defined in the configuration then the
* board specific logic must provide imxrt_phyinitialize(); The i.MX RT Ethernet
* driver will call this function one time before it first uses the PHY.
*
* Input Parameters:
* intf - Always zero for now.
*
* Returned Value:
* OK on success; Negated errno on failure.
*
************************************************************************************/
void weak_function imxrt_phy_boardinitialize(void)
{
#ifdef CONFIG_IMXRT_GPIO1_0_15_IRQ
/* Configure the PHY interrupt pin */
phyinfo("Configuring interrupt: %08x\n", GPIO_ENET_INT);
imxrt_config_gpio(GPIO_ENET_INT);
#endif
/* Configure the PHY reset pin. This will also take the PHY out of reset. */
phyinfo("Configuring reset: %08x\n", GPIO_ENET_RST);
imxrt_config_gpio(GPIO_ENET_RST);
}
/****************************************************************************
* Name: arch_phy_irq
*
* Description:
* This function may be called to register an interrupt handler that will
* be called when a PHY interrupt occurs. This function both attaches
* the interrupt handler and enables the interrupt if 'handler' is non-
* NULL. If handler is NULL, then the interrupt is detached and disabled
* instead.
*
* The PHY interrupt is always disabled upon return. The caller must
* call back through the enable function point to control the state of
* the interrupt.
*
* This interrupt may or may not be available on a given platform depending
* on how the network hardware architecture is implemented. In a typical
* case, the PHY interrupt is provided to board-level logic as a GPIO
* interrupt (in which case this is a board-specific interface and really
* should be called board_phy_irq()); In other cases, the PHY interrupt
* may be cause by the chip's MAC logic (in which case arch_phy_irq()) is
* an appropriate name. Other other boards, there may be no PHY interrupts
* available at all. If client attachable PHY interrupts are available
* from the board or from the chip, then CONFIG_ARCH_PHY_INTERRUPT should
* be defined to indicate that fact.
*
* Typical usage:
* a. OS service logic (not application logic*) attaches to the PHY
* PHY interrupt and enables the PHY interrupt.
* b. When the PHY interrupt occurs: (1) the interrupt should be
* disabled and () work should be scheduled on the worker thread (or
* perhaps a dedicated application thread).
* c. That worker thread should use the SIOCGMIIPHY, SIOCGMIIREG,
* and SIOCSMIIREG ioctl calls** to communicate with the PHY,
* determine what network event took place (Link Up/Down?), and
* take the appropriate actions.
* d. It should then interact the PHY to clear any pending
* interrupts, then re-enable the PHY interrupt.
*
* * This is an OS internal interface and should not be used from
* application space. Rather applications should use the SIOCMIISIG
* ioctl to receive a signal when a PHY event occurs.
* ** This interrupt is really of no use if the Ethernet MAC driver
* does not support these ioctl calls.
*
* Input Parameters:
* intf - Identifies the network interface. For example "eth0". Only
* useful on platforms that support multiple Ethernet interfaces
* and, hence, multiple PHYs and PHY interrupts.
* handler - The client interrupt handler to be invoked when the PHY
* asserts an interrupt. Must reside in OS space, but can
* signal tasks in user space. A value of NULL can be passed
* in order to detach and disable the PHY interrupt.
* arg - The argument that will accompany the interrupt
* enable - A function pointer that be unsed to enable or disable the
* PHY interrupt.
*
* Returned Value:
* Zero (OK) returned on success; a negated errno value is returned on
* failure.
*
****************************************************************************/
#ifdef CONFIG_IMXRT_GPIO1_0_15_IRQ
int arch_phy_irq(FAR const char *intf, xcpt_t handler, void *arg,
phy_enable_t *enable)
{
irqstate_t flags;
gpio_pinset_t pinset;
phy_enable_t enabler;
int irq;
DEBUGASSERT(intf);
ninfo("%s: handler=%p\n", intf, handler);
phyinfo("EMAC: devname=%s\n", IMXRT_ENET_DEVNAME);
if (strcmp(intf, IMXRT_ENET_DEVNAME) == 0)
{
phyinfo("Select EMAC\n");
pinset = GPIO_ENET_INT;
irq = GPIO_ENET_IRQ;
enabler = imxrt_enet_phy_enable;
}
else
{
nerr("ERROR: Unsupported interface: %s\n", intf);
return NULL;
}
/* Disable interrupts until we are done. This guarantees that the
* following operations are atomic.
*/
flags = spin_lock_irqsave();
/* Configure the interrupt */
if (handler)
{
/* The interrupt pin has already been configured as an interrupting
* input (by imxrt_phy_boardinitialize() above).
*
* Attach the new button handler.
*/
phyinfo("Attach IRQ%d\n", irq);
(void)irq_attach(irq, handler, arg);
}
else
{
phyinfo("Detach IRQ%d\n", irq);
(void)irq_detach(irq);
enabler = NULL;
}
/* Return with the interrupt disabled in either case */
up_disable_irq(GPIO_ENET_IRQ);
/* Return the enabling function pointer */
if (enable)
{
*enable = enabler;
}
/* Return the old handler (so that it can be restored) */
spin_unlock_irqrestore(flags);
return OK;
}
#endif /* CONFIG_IMXRT_GPIO1_0_15_IRQ */
#endif /* CONFIG_IMXRT_ENET */