SAMV7 MCAN: some fixes from early testing
This commit is contained in:
Gregory Nutt
parent
73a96ab078
commit
86f7a58954
@ -729,10 +729,8 @@
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*/
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#define MCAN_RXCOMMON_INTS (MCAN_INT_CRCE | MCAN_INT_FOE | MCAN_INT_STE)
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#define MCAN_RXFIFO0_INTS (MCAN_INT_RF0N | MCAN_INT_RF0W | MCAN_INT_RF0L | \
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MCAN_INT_RF0L)
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#define MCAN_RXFIFO1_INTS (MCAN_INT_RF1N | MCAN_INT_RF1W | MCAN_INT_RF1L | \
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MCAN_INT_RF1L)
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#define MCAN_RXFIFO0_INTS (MCAN_INT_RF0N | MCAN_INT_RF0W | MCAN_INT_RF0L)
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#define MCAN_RXFIFO1_INTS (MCAN_INT_RF1N | MCAN_INT_RF1W | MCAN_INT_RF1L)
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#define MCAN_RXFIFO_INTS (MCAN_RXFIFO0_INTS | MCAN_RXFIFO1_INTS | \
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MCAN_INT_HPM | MCAN_RXCOMMON_INTS)
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#define MCAN_RXDEDBUF_INTS (MCAN_INT_DRX | MCAN_RXCOMMON_INTS)
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@ -860,7 +858,6 @@ struct sam_mcan_s
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{
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const struct sam_config_s *config; /* The constant configuration */
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bool initialized; /* True: Device has been initialized */
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bool txenabled; /* True: TX interrupts have been enabled */
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sem_t locksem; /* Enforces mutually exclusive access */
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sem_t txfsem; /* Used to wait for TX FIFO availability */
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uint32_t rxints; /* Configured RX interrupts */
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@ -949,7 +946,6 @@ static int mcan1_interrupt(int irq, void *context);
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/* Hardware initialization */
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static void mcan_configure_interrupts(FAR struct sam_mcan_s *priv);
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static int mcan_hw_initialize(FAR struct sam_mcan_s *priv);
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/****************************************************************************
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@ -2000,12 +1996,10 @@ static void mcan_txint(FAR struct can_dev_s *dev, bool enable)
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if (enable)
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{
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regval |= priv->txints | MCAN_COMMON_INTS;
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priv->txenabled = true;
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}
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else
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{
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regval &= ~priv->txints;
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priv->txenabled = false;
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}
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mcan_putreg(priv, SAM_MCAN_IE_OFFSET, regval);
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@ -2174,7 +2168,6 @@ static int mcan_send(FAR struct can_dev_s *dev, FAR struct can_msg_s *msg)
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FAR uint32_t *txbuffer = 0;
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FAR const uint8_t *src;
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FAR uint8_t *dest;
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irqstate_t flags;
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uint32_t regval;
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unsigned int msglen;
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unsigned int ndx;
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@ -2286,19 +2279,6 @@ static int mcan_send(FAR struct can_dev_s *dev, FAR struct can_msg_s *msg)
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mcan_putreg(priv, SAM_MCAN_TXBAR_OFFSET, (1 << ndx));
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/* If we have not been asked to suppress TX interrupts, then enable
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* TX interrupts now.
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*/
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if (priv->txenabled)
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{
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flags = irqsave();
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regval = mcan_getreg(priv, SAM_MCAN_IE_OFFSET);
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regval |= priv->txints;
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mcan_putreg(priv, SAM_MCAN_IE_OFFSET, priv->txints);
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irqrestore(flags);
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}
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mcan_dev_unlock(priv);
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return OK;
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}
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@ -2322,18 +2302,32 @@ static bool mcan_txready(FAR struct can_dev_s *dev)
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FAR struct sam_mcan_s *priv = dev->cd_priv;
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uint32_t regval;
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bool notfull;
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#ifdef CONFIG_DEBUG
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int sval;
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#endif
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/* Get exclusive access to the MCAN peripheral */
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mcan_dev_lock(priv);
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/* Return the state of the TX FIFOQ
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/* Return the state of the TX FIFOQ. Return TRUE if the TX FIFO/Queue is
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* not full.
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*
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* REVISIT: Dedicated TX buffers are not supported.
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*/
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regval = mcan_getreg(priv, SAM_MCAN_IR_OFFSET);
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notfull = ((regval & MCAN_INT_TEFF) == 0);
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regval = mcan_getreg(priv, SAM_MCAN_TXFQS_OFFSET);
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notfull = ((regval & MCAN_TXFQS_TFQF) == 0);
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#ifdef CONFIG_DEBUG
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/* As a sanity check, the txfsem should also track the number of elements
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* the TX FIFO/queue. Make sure that they are consistent.
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*/
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(void)sem_getvalue(&priv->txfsem, &sval);
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DEBUGASSERT(((notfull && sval > 0) || (!notfull && sval <= 0)) &&
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(sval <= priv->config->ntxfifoq));
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#endif
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mcan_dev_unlock(priv);
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return notfull;
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@ -2361,22 +2355,42 @@ static bool mcan_txempty(FAR struct can_dev_s *dev)
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{
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FAR struct sam_mcan_s *priv = dev->cd_priv;
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uint32_t regval;
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bool txempty;
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int sval;
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bool empty;
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DEBUGASSERT(priv != NULL && priv->config != NULL);
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/* Get exclusive access to the MCAN peripheral */
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mcan_dev_lock(priv);
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/* Return the state of the TX FIFOQ
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/* Return the state of the TX FIFOQ. Return TRUE if the TX FIFO/Queue is
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* empty. We don't have a reliable indication that the FIFO is empty, so
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* we have to use some heuristics.
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*
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* REVISIT: Dedicated TX buffers are not supported.
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*/
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regval = mcan_getreg(priv, SAM_MCAN_IR_OFFSET);
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txempty = ((regval & MCAN_INT_TFE) != 0);
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regval = mcan_getreg(priv, SAM_MCAN_TXFQS_OFFSET);
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if (((regval & MCAN_TXFQS_TFQF) != 0))
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{
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return false;
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}
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/* The TX FIFO/Queue is not full, but is it empty? The txfsem should
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* track the number of elements the TX FIFO/queue in use.
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*
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* Since the FIFO is not full, the semaphore count should be greater
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* than zero. If it is equal to the full count of TX FIFO/Queue
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* elements, then there is no transfer in progress.
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*/
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(void)sem_getvalue(&priv->txfsem, &sval);
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DEBUGASSERT(sval > 0 && sval <= priv->config->ntxfifoq);
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empty = (sval == priv->config->ntxfifoq);
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mcan_dev_unlock(priv);
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return txempty;
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return empty;
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}
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/****************************************************************************
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@ -2513,6 +2527,9 @@ static void mcan_interrupt(FAR struct can_dev_s *dev)
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uint32_t regval;
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unsigned int nelem;
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unsigned int ndx;
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#ifdef CONFIG_DEBUG
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int sval;
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#endif
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DEBUGASSERT(priv && priv->config);
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config = priv->config;
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@ -2532,7 +2549,7 @@ static void mcan_interrupt(FAR struct can_dev_s *dev)
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/* Clear the error indications */
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mcan_putreg(priv, SAM_MCAN_IE_OFFSET, MCAN_CMNERR_INTS);
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mcan_putreg(priv, SAM_MCAN_IR_OFFSET, MCAN_CMNERR_INTS);
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}
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/* Check for transmission errors */
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@ -2543,7 +2560,7 @@ static void mcan_interrupt(FAR struct can_dev_s *dev)
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/* Clear the error indications */
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mcan_putreg(priv, SAM_MCAN_IE_OFFSET, MCAN_TXERR_INTS);
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mcan_putreg(priv, SAM_MCAN_IR_OFFSET, MCAN_TXERR_INTS);
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}
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/* Check for successful completion of a transmission */
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@ -2554,7 +2571,7 @@ static void mcan_interrupt(FAR struct can_dev_s *dev)
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* other TX-related interrupts)
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*/
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mcan_putreg(priv, SAM_MCAN_IE_OFFSET, priv->txints);
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mcan_putreg(priv, SAM_MCAN_IR_OFFSET, priv->txints);
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/* Indicate that there is one more buffer free in the TX FIFOQ by
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* "releasing" it. This may have the effect of waking up a thread
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@ -2564,13 +2581,21 @@ static void mcan_interrupt(FAR struct can_dev_s *dev)
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*/
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mcan_buffer_release(priv);
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DEBUGASSERT(priv->txfsem.semcount <= config->ntxfifoq);
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#ifdef CONFIG_DEBUG
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(void)sem_getvalue(&priv->txfsem, &sval);
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DEBUGASSERT(sval <= config->ntxfifoq);
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#endif
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/* Report that the TX transfer is complete to the upper half logic */
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can_txdone(dev);
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}
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else if ((pending & priv->txints) != 0)
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{
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/* Clear unhandled TX events */
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mcan_putreg(priv, SAM_MCAN_IE_OFFSET, priv->txints);
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mcan_putreg(priv, SAM_MCAN_IR_OFFSET, priv->txints);
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}
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#if 0 /* Not used */
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@ -2626,20 +2651,18 @@ static void mcan_interrupt(FAR struct can_dev_s *dev)
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/* Clear the error indications */
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mcan_putreg(priv, SAM_MCAN_IE_OFFSET, MCAN_RXERR_INTS);
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mcan_putreg(priv, SAM_MCAN_IR_OFFSET, MCAN_RXERR_INTS);
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}
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/* Check for successful reception of a new message in RX FIFO0 */
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if ((pending & MCAN_INT_RF0N) != 0)
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{
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DEBUGASSERT(priv->txfsem.semcount <= config->nrxfifo0);
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/* Clear the RX FIFO0 interrupt (and all other FIFO0-related
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* interrupts)
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*/
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mcan_putreg(priv, SAM_MCAN_IE_OFFSET, MCAN_RXFIFO0_INTS);
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mcan_putreg(priv, SAM_MCAN_IR_OFFSET, MCAN_RXFIFO0_INTS);
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pending &= ~MCAN_RXFIFO0_INTS;
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/* Handle the newly received message in FIFO0 */
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@ -2672,13 +2695,11 @@ static void mcan_interrupt(FAR struct can_dev_s *dev)
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if ((pending & MCAN_INT_RF1N) != 0)
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{
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DEBUGASSERT(priv->txfsem.semcount <= config->nrxfifo1);
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/* Clear the RX FIFO1 interrupt (and all other FIFO1-related
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* interrupts)
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*/
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mcan_putreg(priv, SAM_MCAN_IE_OFFSET, MCAN_RXFIFO1_INTS);
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mcan_putreg(priv, SAM_MCAN_IR_OFFSET, MCAN_RXFIFO1_INTS);
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pending &= ~MCAN_RXFIFO1_INTS;
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/* Handle the newly received message in FIFO1 */
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@ -2711,7 +2732,7 @@ static void mcan_interrupt(FAR struct can_dev_s *dev)
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if ((pending & priv->rxints) != 0)
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{
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mcan_putreg(priv, SAM_MCAN_IE_OFFSET, priv->rxints);
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mcan_putreg(priv, SAM_MCAN_IR_OFFSET, priv->rxints);
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}
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}
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@ -2761,59 +2782,6 @@ static int mcan1_interrupt(int irq, void *context)
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}
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#endif
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/****************************************************************************
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* Name: mcan_configure_interrupts
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*
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* Description:
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* Configure interrupt lines.
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*
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* Input Parameter:
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* priv - A pointer to the private data structure for this MCAN peripheral
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*
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* Returned Value:
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* Zero on success; a negated errno value on failure.
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*
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****************************************************************************/
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static void mcan_configure_interrupts(FAR struct sam_mcan_s *priv)
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{
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uint32_t regval;
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/* Select RX-related interrupts */
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#if 0 /* Dedicated RX buffers are not used by this driver */
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priv->rxints = MCAN_RXDEDBUF_INTS;
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#else
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priv->rxints = MCAN_RXFIFO_INTS;
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#endif
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/* Select RX-related interrupts */
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#if 0 /* Dedicated TX buffers are not used by this driver */
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priv->txints = MCAN_TXDEDBUF_INTS;
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#else
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priv->txints = MCAN_TXFIFOQ_INTS;
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#endif
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/* Direct to Line 0.
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* REVISIT: Only interrupt line 0 is used by this driver.
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*/
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regval = mcan_getreg(priv, SAM_MCAN_ILS_OFFSET);
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regval |= (priv->rxints | priv->txints | MCAN_COMMON_INTS);
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mcan_putreg(priv, SAM_MCAN_ILS_OFFSET, regval);
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/* Make sure that interrupt line 0 is enabled. */
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regval = mcan_getreg(priv, SAM_MCAN_ILE_OFFSET);
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regval |= MCAN_ILE_EINT0;
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mcan_putreg(priv, SAM_MCAN_ILE_OFFSET, regval);
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/* Clear any pending interrupts but do not yet enable a interrupt */
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mcan_putreg(priv, SAM_MCAN_IE_OFFSET, MCAN_INT_ALL);
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}
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/****************************************************************************
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* Name: mcan_hw_initialize
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*
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@ -2939,7 +2907,7 @@ static int mcan_hw_initialize(struct sam_mcan_s *priv)
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MCAN_RXESC_F0DS(config->rxfifo0ecode);
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mcan_putreg(priv, SAM_MCAN_RXESC_OFFSET, regval);
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regval = MCAN_TXESC_TBDS(config->txbufferesize);
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regval = MCAN_TXESC_TBDS(config->txbufferecode);
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mcan_putreg(priv, SAM_MCAN_TXESC_OFFSET, regval);
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/* Configure Message Filters */
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@ -3042,8 +3010,35 @@ static int mcan_hw_initialize(struct sam_mcan_s *priv)
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#endif
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/* Configure interrupt lines */
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/* Select RX-related interrupts */
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mcan_configure_interrupts(priv);
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#if 0 /* Dedicated RX buffers are not used by this driver */
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priv->rxints = MCAN_RXDEDBUF_INTS;
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#else
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priv->rxints = MCAN_RXFIFO_INTS;
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#endif
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/* Select TX-related interrupts */
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#if 0 /* Dedicated TX buffers are not used by this driver */
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priv->txints = MCAN_TXDEDBUF_INTS;
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#else
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priv->txints = MCAN_TXFIFOQ_INTS;
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#endif
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/* Direct all interrupts to Line 0.
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*
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* Bits in the ILS register correspond to each MCAN interrupt; A bit
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* set to '1' is directed to interrupt line 1; a bit cleared to '0'
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* is directed interrupt line 0.
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*
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* REVISIT: Nothing is done here. Only interrupt line 0 is used by
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* this driver and ILS was already cleared above.
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*/
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/* Enable only interrupt line 0. */
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mcan_putreg(priv, SAM_MCAN_ILE_OFFSET, MCAN_ILE_EINT0);
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/* Disable initialization mode to enable normal operation */
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