commit
8705ce816a
@ -299,9 +299,7 @@ struct sam_ep_s
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struct sam_rqhead_s reqq; /* Read/write request queue */
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struct sam_rqhead_s pendq; /* Write requests pending stall sent */
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volatile uint8_t epstate; /* State of the endpoint (see enum sam_epstate_e) */
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uint8_t stalled:1; /* true: Endpoint is stalled */
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uint8_t pending:1; /* true: IN Endpoint stall is pending */
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uint8_t halted:1; /* true: Endpoint feature halted */
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uint8_t zlpneeded:1; /* Zero length packet needed at end of transfer */
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uint8_t zlpsent:1; /* Zero length packet has been sent */
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uint8_t txbusy:1; /* Write request queue is busy (recursion avoidance kludge) */
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@ -820,7 +818,7 @@ static void sam_req_complete(struct sam_ep_s *privep, int16_t result)
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privreq->flink = NULL;
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privreq->req.callback(&privep->ep, &privreq->req);
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/* Reset the endpoint state and restore the stalled indication */
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/* Reset the endpoint state */
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privep->epstate = UDP_EPSTATE_IDLE;
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privep->zlpneeded = false;
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@ -895,8 +893,8 @@ static void sam_req_wrsetup(struct sam_usbdev_s *priv,
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privep->epstate = UDP_EPSTATE_SENDING;
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/* Set TXPKTRDY to notify the USB hardware that there is TX data in the
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* endpoint FIFO. We will be notified that the endpoint’s FIFO has been
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* released by the USB device when TXCOMP in the endpoint’s UDPEP_CSRx
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* endpoint FIFO. We will be notified that the endpoint's FIFO has been
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* released by the USB device when TXCOMP in the endpoint's UDPEP_CSRx
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* register has been set.
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*/
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@ -1404,7 +1402,6 @@ static void sam_ep0_setup(struct sam_usbdev_s *priv)
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/* Assume NOT stalled; no TX in progress */
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ep0->stalled = false;
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ep0->pending = false;
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ep0->epstate = UDP_EPSTATE_IDLE;
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@ -1470,7 +1467,7 @@ static void sam_ep0_setup(struct sam_usbdev_s *priv)
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response.w = 0; /* Not stalled */
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nbytes = 2; /* Response size: 2 bytes */
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if (privep->stalled)
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if (privep->epstate == UDP_EPSTATE_STALLED)
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{
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/* Endpoint stalled */
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@ -1547,7 +1544,6 @@ static void sam_ep0_setup(struct sam_usbdev_s *priv)
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value.w == USB_FEATURE_ENDPOINTHALT && len.w == 0)
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{
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privep = &priv->eplist[epno];
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privep->halted = false;
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ret = sam_ep_resume(privep);
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if (ret < 0)
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@ -1596,7 +1592,6 @@ static void sam_ep0_setup(struct sam_usbdev_s *priv)
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value.w == USB_FEATURE_ENDPOINTHALT && len.w == 0)
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{
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privep = &priv->eplist[epno];
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privep->halted = true;
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ret = sam_ep_stall(privep);
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if (ret < 0)
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@ -2559,9 +2554,7 @@ static void sam_ep_reset(struct sam_usbdev_s *priv, uint8_t epno)
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/* Reset endpoint status */
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privep->epstate = UDP_EPSTATE_DISABLED;
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privep->stalled = false;
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privep->pending = false;
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privep->halted = false;
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privep->zlpneeded = false;
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privep->zlpsent = false;
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privep->txbusy = false;
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@ -2633,7 +2626,6 @@ static int sam_ep_stall(struct sam_ep_s *privep)
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/* Put endpoint into stalled state */
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privep->epstate = UDP_EPSTATE_STALLED;
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privep->stalled = true;
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privep->pending = false;
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sam_csr_setbits(epno, UDPEP_CSR_FORCESTALL);
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@ -2671,7 +2663,6 @@ static int sam_ep_resume(struct sam_ep_s *privep)
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/* Return endpoint to Idle state */
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privep->stalled = false;
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privep->pending = false;
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privep->epstate = UDP_EPSTATE_IDLE;
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@ -2682,8 +2673,24 @@ static int sam_ep_resume(struct sam_ep_s *privep)
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/* Reset the endpoint FIFO */
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sam_putreg(UDP_RSTEP(epno), SAM_UDP_RSTEP);
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/*
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* We need to add a delay between setting and clearing the endpoint reset
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* bit in SAM_UDP_RSTEP. Without the delay the USB controller will (may?)
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* not reset the endpoint.
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*
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* If the endpoint is not being reset, the Data Toggle (DTGLE) bit will
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* not to be cleared which will cause the next transaction to fail if
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* DTGLE is 1. If that happens the host will time-out and reset the bus.
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*
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* Adding this delay may also fix the USBMSC_STALL_RACEWAR in
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* usbmsc_scsi.c, however this has not been verified yet.
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*/
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up_udelay(10);
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sam_putreg(0, SAM_UDP_RSTEP);
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/* Copy any requests in the pending request queue to the working
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* request queue.
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*/
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@ -3170,10 +3177,10 @@ static int sam_ep_submit(struct usbdev_ep_s *ep, struct usbdev_req_s *req)
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{
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/* Check if the endpoint is stalled (or there is a stall pending) */
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if (privep->stalled || privep->pending)
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if ((privep->epstate == UDP_EPSTATE_STALLED) || privep->pending)
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{
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/* Yes.. in this case, save the request in a special "pending"
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* queue. They will stay queuee until the stall is cleared.
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* queue. They will stay queued until the stall is cleared.
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*/
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uinfo("Pending stall clear\n");
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@ -3650,9 +3657,7 @@ static void sam_reset(struct sam_usbdev_s *priv)
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/* Reset endpoint status */
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privep->stalled = false;
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privep->pending = false;
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privep->halted = false;
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privep->zlpneeded = false;
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privep->zlpsent = false;
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privep->txbusy = false;
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@ -449,7 +449,7 @@ f Application Configuration -> Network Utilities
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Timers
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======
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Tiva timers may be enbled in 32-bit periodic mode using these settings.
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Tiva timers may be enabled in 32-bit periodic mode using these settings.
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This settings enables the "upper half" timer driver:
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@ -827,7 +827,7 @@ static int inline usbmsc_cmdmodesense6(FAR struct usbmsc_dev_s *priv,
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{
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/* Store the mode data length and return the total message size */
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mph->mdlen = mdlen - 1;
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mph->mdlen = mdlen + SCSIRESP_MODEPARAMETERHDR6_SIZEOF - 1;
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priv->nreqbytes = mdlen + SCSIRESP_MODEPARAMETERHDR6_SIZEOF;
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}
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}
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