risc-v/k230: initial rv64ilp32 support
This enables NuttX FLAT build with rv64ilp32 on CanMV230 device. Signed-off-by: Yanfeng Liu <yfliu2008@qq.com>
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@ -27,7 +27,7 @@
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/* Devices Base Address */
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#define K230_PLIC_BASE 0xF00000000UL
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#define K230_PLIC_BASE UINT64_C(0xF00000000)
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#define K230_CLINT_BASE (K230_PLIC_BASE + 0x04000000)
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#define K230_CPU1_BOOTA 0x91102104UL
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#define K230_CPU1_RESET 0x9110100cUL
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@ -46,5 +46,5 @@
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/* Enable RV PBMT */
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#define MENVCFG_PBMT (1ul << 62)
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#define MENVCFG_PBMT (UINT64_C(1) << 62)
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#endif /* __ARCH_RISCV_SRC_K230_HARDWARE_K230_MEMORYMAP_H */
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@ -169,7 +169,7 @@ void k230_hart_big_stop(void)
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putreg32(RESET_RQST_BIT | RESET_RQST_ENW, K230_CPU1_RESET);
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up_udelay(RESET_WAIT_USEC);
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sinfo("reg: %x\n", getreg32(K230_CPU1_RESET));
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sinfo("reg: %" PRIx32 "\n", getreg32(K230_CPU1_RESET));
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}
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/****************************************************************************
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@ -184,7 +184,7 @@ void k230_hart_big_boot(uintptr_t addr)
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/* learned from U-Boot baremetal and RTT sysctl_reset_cpu */
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if (addr) putreg32(addr, K230_CPU1_BOOTA);
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sinfo("addr=%lx\n", addr);
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sinfo("addr=%"PRIxPTR"\n", addr);
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/* 0x10001000 clear DONE bit */
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@ -36,7 +36,15 @@
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#include "riscv_ipi.h"
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#include "chip.h"
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#define STATUS_LOW (READ_CSR(CSR_STATUS) & 0xffffffff) /* STATUS low part */
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/****************************************************************************
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* Preprocessor definitions
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****************************************************************************/
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/* lower word of STATUS register */
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#define STATUS_LOW (uint32_t)(READ_CSR(CSR_STATUS) & UINT32_MAX)
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#define IE_STS_IRQ "ie=%"PRIxREG" sts=%"PRIx32" irq=%d\n"
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#define IE_STS_CTX "ie=%"PRIxREG" sts=%"PRIx32" ctx=%d\n"
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/****************************************************************************
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* Public Functions
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@ -70,7 +78,7 @@ void up_irqinitialize(void)
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for (id = 1; id <= NR_IRQS; id++)
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{
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putreg32(1, (uintptr_t)(K230_PLIC_PRIORITY + 4 * id));
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putreg32(1, K230_PLIC_PRIORITY + 4 * id);
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}
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sinfo("prioritized %d irqs\n", NR_IRQS);
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@ -140,7 +148,7 @@ void up_disable_irq(int irq)
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}
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}
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sinfo("ie=%lx sts=%lx irq=%d\n", READ_CSR(CSR_IE), STATUS_LOW, irq);
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sinfo(IE_STS_IRQ, READ_CSR(CSR_IE), STATUS_LOW, irq);
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}
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/****************************************************************************
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@ -184,7 +192,7 @@ void up_enable_irq(int irq)
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}
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}
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sinfo("ie=%lx sts=%lx irq=%d\n", READ_CSR(CSR_IE), STATUS_LOW, irq);
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sinfo(IE_STS_IRQ, READ_CSR(CSR_IE), STATUS_LOW, irq);
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}
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irqstate_t up_irq_enable(void)
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@ -198,8 +206,6 @@ irqstate_t up_irq_enable(void)
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/* Read and enable global interrupts (M/SIE) in m/sstatus */
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oldstat = READ_AND_SET_CSR(CSR_STATUS, STATUS_IE);
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sinfo("ie=%lx sts=%lx ctx=%d\n", READ_CSR(CSR_IE), STATUS_LOW,
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XCPTCONTEXT_SIZE);
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sinfo(IE_STS_CTX, READ_CSR(CSR_IE), STATUS_LOW, XCPTCONTEXT_SIZE);
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return oldstat;
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}
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@ -53,7 +53,7 @@
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* riscv_dispatch_irq
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****************************************************************************/
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void *riscv_dispatch_irq(uintptr_t vector, uintptr_t *regs)
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void *riscv_dispatch_irq(uintreg_t vector, uintreg_t *regs)
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{
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int irq = (vector >> RV_IRQ_MASK) | (vector & 0xf);
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