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Merged nuttx/arch into master

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ziggurat29 2016-03-26 10:53:16 -05:00
commit 873cdc20eb
4 changed files with 112 additions and 100 deletions
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2
arch/arm/src/stm32l4/Kconfig
View File

@ -416,7 +416,7 @@ config STM32L4_DISABLE_IDLE_SLEEP_DURING_DEBUG
instruction, the debugger will disconnect, terminating the debug session.
config ARCH_BOARD_STM32L4_CUSTOM_CLOCKCONFIG
bool "Custom clock configuration"
bool "Custom clock configuration"
default n
---help---
Enables special, board-specific STM32 clock configuration.

154
arch/arm/src/stm32l4/chip/stm32l4_rng.h
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@ -1,77 +1,77 @@
/************************************************************************************
* arch/arm/src/stm32/chip/stm32l4_rng.h
*
* Copyright (C) 2012 Max Holtzberg. All rights reserved.
* Author: Max Holtzberg <mh@uvc.de>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
************************************************************************************/
#ifndef __ARCH_ARM_STC_STM32_CHIP_STM32L4_RNG_H
#define __ARCH_ARM_STC_STM32_CHIP_STM32L4_RNG_H
/************************************************************************************
* Included Files
************************************************************************************/
#include <nuttx/config.h>
#include "chip.h"
/************************************************************************************
* Pre-processor Definitions
************************************************************************************/
/* Register Offsets *****************************************************************/
#define STM32L4_RNG_CR_OFFSET 0x0000 /* RNG Control Register */
#define STM32L4_RNG_SR_OFFSET 0x0004 /* RNG Status Register */
#define STM32L4_RNG_DR_OFFSET 0x0008 /* RNG Data Register */
/* Register Addresses ***************************************************************/
#define STM32L4_RNG_CR (STM32L4_RNG_BASE+STM32L4_RNG_CR_OFFSET)
#define STM32L4_RNG_SR (STM32L4_RNG_BASE+STM32L4_RNG_SR_OFFSET)
#define STM32L4_RNG_DR (STM32L4_RNG_BASE+STM32L4_RNG_DR_OFFSET)
/* Register Bitfield Definitions ****************************************************/
/* RNG Control Register */
#define RNG_CR_RNGEN (1 << 2) /* Bit 2: RNG enable */
#define RNG_CR_IE (1 << 3) /* Bit 3: Interrupt enable */
/* RNG Status Register */
#define RNG_SR_DRDY (1 << 0) /* Bit 0: Data ready */
#define RNG_SR_CECS (1 << 1) /* Bit 1: Clock error current status */
#define RNG_SR_SECS (1 << 2) /* Bit 2: Seed error current status */
#define RNG_SR_CEIS (1 << 5) /* Bit 5: Clock error interrupt status */
#define RNG_SR_SEIS (1 << 6) /* Bit 6: Seed error interrupt status */
#endif /* __ARCH_ARM_STC_STM32_CHIP_STM32L4_RNG_H */
/************************************************************************************
* arch/arm/src/stm32/chip/stm32l4_rng.h
*
* Copyright (C) 2012 Max Holtzberg. All rights reserved.
* Author: Max Holtzberg <mh@uvc.de>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
************************************************************************************/
#ifndef __ARCH_ARM_STC_STM32_CHIP_STM32L4_RNG_H
#define __ARCH_ARM_STC_STM32_CHIP_STM32L4_RNG_H
/************************************************************************************
* Included Files
************************************************************************************/
#include <nuttx/config.h>
#include "chip.h"
/************************************************************************************
* Pre-processor Definitions
************************************************************************************/
/* Register Offsets *****************************************************************/
#define STM32L4_RNG_CR_OFFSET 0x0000 /* RNG Control Register */
#define STM32L4_RNG_SR_OFFSET 0x0004 /* RNG Status Register */
#define STM32L4_RNG_DR_OFFSET 0x0008 /* RNG Data Register */
/* Register Addresses ***************************************************************/
#define STM32L4_RNG_CR (STM32L4_RNG_BASE+STM32L4_RNG_CR_OFFSET)
#define STM32L4_RNG_SR (STM32L4_RNG_BASE+STM32L4_RNG_SR_OFFSET)
#define STM32L4_RNG_DR (STM32L4_RNG_BASE+STM32L4_RNG_DR_OFFSET)
/* Register Bitfield Definitions ****************************************************/
/* RNG Control Register */
#define RNG_CR_RNGEN (1 << 2) /* Bit 2: RNG enable */
#define RNG_CR_IE (1 << 3) /* Bit 3: Interrupt enable */
/* RNG Status Register */
#define RNG_SR_DRDY (1 << 0) /* Bit 0: Data ready */
#define RNG_SR_CECS (1 << 1) /* Bit 1: Clock error current status */
#define RNG_SR_SECS (1 << 2) /* Bit 2: Seed error current status */
#define RNG_SR_CEIS (1 << 5) /* Bit 5: Clock error interrupt status */
#define RNG_SR_SEIS (1 << 6) /* Bit 6: Seed error interrupt status */
#endif /* __ARCH_ARM_STC_STM32_CHIP_STM32L4_RNG_H */

35
arch/arm/src/stm32l4/stm32l4_rng.c
View File

@ -95,13 +95,17 @@ static const struct file_operations g_rngops =
#ifndef CONFIG_DISABLE_POLL
, 0 /* poll */
#endif
#ifndef CONFIG_DISABLE_PSEUDOFS_OPERATIONS
, 0 /* unlink */
#endif
};
/****************************************************************************
* Private functions
****************************************************************************/
static int stm32l4_rnginitialize()
static int stm32l4_rnginitialize(void)
{
uint32_t regval;
@ -131,7 +135,7 @@ static int stm32l4_rnginitialize()
return OK;
}
static void stm32l4_rngenable()
static void stm32l4_rngenable(void)
{
uint32_t regval;
@ -142,8 +146,8 @@ static void stm32l4_rngenable()
putreg32(regval, STM32L4_RNG_CR);
/* XXX see stm32l4_rngdisable(), below; if interrupts are disabled there,
then they should also be enabled here (also, they should not be enabled
in stm32l4_rnginitialize())
* then they should also be enabled here (also, they should not be enabled
* in stm32l4_rnginitialize())
*/
}
@ -155,10 +159,10 @@ static void stm32l4_rngdisable()
putreg32(regval, STM32L4_RNG_CR);
/* XXX I believe it's appropriate to also disable the interrupt, and clear
any interrupt pending bit. This 'disable' is called from within the
interrupt handler when the buffer has been finally filled, but if there
is still another interrupt pending, then the handler will be entered one
last time, and attempt to touch some now-invalid objects
* any interrupt pending bit. This 'disable' is called from within the
* interrupt handler when the buffer has been finally filled, but if there
* is still another interrupt pending, then the handler will be entered one
* last time, and attempt to touch some now-invalid objects
*/
}
@ -170,14 +174,18 @@ static int stm32l4_rnginterrupt(int irq, void *context)
rngsr = getreg32(STM32L4_RNG_SR);
if (rngsr & RNG_SR_CEIS) /* Check for clock error int stat */
{
/* clear it, we will try again. */
/* Clear it, we will try again. */
putreg32(rngsr & ~RNG_SR_CEIS, STM32L4_RNG_SR);
return OK;
}
if (rngsr & RNG_SR_SEIS) /* Check for seed error in int stat */
{
uint32_t crval;
/* clear seed error, then disable/enable the rng and try again. */
/* Clear seed error, then disable/enable the rng and try again. */
putreg32(rngsr & ~RNG_SR_SEIS, STM32L4_RNG_SR);
crval = getreg32(STM32L4_RNG_CR);
crval &= ~RNG_CR_RNGEN;
@ -186,9 +194,11 @@ static int stm32l4_rnginterrupt(int irq, void *context)
putreg32(crval, STM32L4_RNG_CR);
return OK;
}
if (!(rngsr & RNG_SR_DRDY)) /* Data ready must be set */
{
/* This random value is not valid, we will try again. */
return OK;
}
@ -276,7 +286,8 @@ static ssize_t stm32l4_rngread(struct file *filep, char *buffer, size_t buflen)
sem_wait(&g_rngdev.rd_readsem);
/* done with the operation semaphore */
/* Done with the operation semaphore */
sem_destroy(&g_rngdev.rd_readsem);
/* Free RNG via the device semaphore for next use */
@ -291,7 +302,7 @@ static ssize_t stm32l4_rngread(struct file *filep, char *buffer, size_t buflen)
* Public Functions
****************************************************************************/
void up_rnginitialize()
void up_rnginitialize(void)
{
stm32l4_rnginitialize();
register_driver("/dev/random", &g_rngops, 0444, NULL);

21
arch/arm/src/stm32l4/stm32l4x6xx_rcc.c
View File

@ -689,7 +689,9 @@ static void stm32l4_stdclockconfig(void)
/* XXX The choice of clock source to PLL (all three) is independent
* of the sys clock source choice, review the STM32L4_BOARD_USEHSI
* name; probably split it into two, one for PLL source and one
* for sys clock source */
* for sys clock source.
*/
#ifdef STM32L4_BOARD_USEHSI
regval |= RCC_PLLCFG_PLLSRC_HSI;
#else /* if STM32L4_BOARD_USEHSE */
@ -743,7 +745,6 @@ static void stm32l4_stdclockconfig(void)
while ((getreg32(STM32L4_RCC_CR) & RCC_CR_PLLSAI1RDY) == 0)
{
}
#endif
#ifdef CONFIG_STM32L4_SAI2PLL
@ -754,8 +755,8 @@ static void stm32l4_stdclockconfig(void)
/* Enable the SAI2 PLL */
/* Set the PLL dividers and multipliers to configure the SAI2 PLL */
regval = (STM32L4_PLLSAI2CFG_PLLN | STM32L4_PLLSAI2CFG_PLLP
| STM32L4_PLLSAI2CFG_PLLR);
regval = (STM32L4_PLLSAI2CFG_PLLN | STM32L4_PLLSAI2CFG_PLLP |
STM32L4_PLLSAI2CFG_PLLR);
#ifdef STM32L4_PLLSAI2CFG_PLLP_ENABLED
regval |= RCC_PLLSAI2CFG_PLLPEN;
@ -777,7 +778,6 @@ static void stm32l4_stdclockconfig(void)
while ((getreg32(STM32L4_RCC_CR) & RCC_CR_PLLSAI2RDY) == 0)
{
}
#endif
/* Enable FLASH prefetch, instruction cache, data cache, and 5 wait states */
@ -819,18 +819,19 @@ static void stm32l4_stdclockconfig(void)
#endif
#if defined(STM32L4_USE_CLK48)
/*XXX sanity if sdmmc1 or usb or rng, then we need to set the clk48 source
/* XXX sanity if sdmmc1 or usb or rng, then we need to set the clk48 source
* and then we can also do away with STM32L4_USE_CLK48, and give better
* warning messages */
/*XXX sanity if our STM32L4_CLK48_SEL is YYY then we need to have already
* enabled ZZZ */
* warning messages
*
* XXX sanity if our STM32L4_CLK48_SEL is YYY then we need to have already
* enabled ZZZ
*/
regval = getreg32(STM32L4_RCC_CCIPR);
regval &= RCC_CCIPR_CLK48SEL_MASK;
regval |= STM32L4_CLK48_SEL;
putreg32(regval, STM32L4_RCC_CCIPR);
#endif
}
}
#endif