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Merged in kloper/arch/atmega2560 (pull request #46)

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Atmega2560
This commit is contained in:
Gregory Nutt 2015-12-29 12:20:09 -06:00
commit 87a6662998
20 changed files with 416 additions and 69 deletions
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1
arch/avr/include/at90usb/irq.h
View File

@ -94,6 +94,7 @@
#define AT90USB_IRQ_SPMRDY 36 /* 0x004a Store Program Memory Ready */
#define NR_IRQS 37
#define XCPTCONTEXT_REGS 37 /* Size of the register state save array (in bytes) */
/****************************************************************************
* Public Types

77
arch/avr/include/atmega/irq.h
View File

@ -56,6 +56,7 @@
*/
#if defined(CONFIG_ARCH_CHIP_ATMEGA128)
# define ATMEGA_IRQ_INT0 0 /* 0x0002 External Interrupt Request 0 */
# define ATMEGA_IRQ_INT1 1 /* 0x0004 External Interrupt Request 1 */
# define ATMEGA_IRQ_INT2 2 /* 0x0006 External Interrupt Request 2 */
@ -90,7 +91,13 @@
# define ATMEGA_IRQ_U1TX 31 /* 0x0040 USART1 Tx Complete */
# define ATMEGA_IRQ_TWI 32 /* 0x0042 TWI Two-wire Serial Interface */
# define ATMEGA_IRQ_SPMRDY 33 /* 0x0044 Store Program Memory Ready */
# define NR_IRQS 34
# define ATMEGA_PC_SIZE 16
# define XCPTCONTEXT_REGS 37 /* Size of the register state save array (in bytes) */
#elif defined(CONFIG_ARCH_CHIP_ATMEGA1284P)
# define ATMEGA_IRQ_INT0 0 /* 0x0002 External Interrupt Request 0 */
# define ATMEGA_IRQ_INT1 1 /* 0x0004 External Interrupt Request 1 */
# define ATMEGA_IRQ_INT2 2 /* 0x0006 External Interrupt Request 2 */
@ -125,12 +132,78 @@
# define ATMEGA_IRQ_T3COMPA 31 /* 0x0040 TIMER3 COMPA Timer/Counter3 Compare Match A */
# define ATMEGA_IRQ_T3COMPB 32 /* 0x0042 TIMER3 COMPB Timer/Counter3 Compare Match B */
# define ATMEGA_IRQ_T3OVF 33 /* 0x0044 TIMER3 OVF Timer/Counter3 Overflow */
# define NR_IRQS 34
# define ATMEGA_PC_SIZE 16
# define XCPTCONTEXT_REGS 37 /* Size of the register state save array (in bytes) */
#elif defined(CONFIG_ARCH_CHIP_ATMEGA2560)
# define ATMEGA_IRQ_INT0 2 /* 0x0002 INT0 External Interrupt Request 0 */
# define ATMEGA_IRQ_INT1 3 /* 0x0004 INT1 External Interrupt Request 1 */
# define ATMEGA_IRQ_INT2 4 /* 0x0006 INT2 External Interrupt Request 2 */
# define ATMEGA_IRQ_INT3 5 /* 0x0008 INT3 External Interrupt Request 3 */
# define ATMEGA_IRQ_INT4 6 /* 0x000A INT4 External Interrupt Request 4 */
# define ATMEGA_IRQ_INT5 7 /* 0x000C INT5 External Interrupt Request 5 */
# define ATMEGA_IRQ_INT6 8 /* 0x000E INT6 External Interrupt Request 6 */
# define ATMEGA_IRQ_INT7 9 /* 0x0010 INT7 External Interrupt Request 7 */
# define ATMEGA_IRQ_PCINT0 10 /* 0x0012 PCINT0 Pin Change Interrupt Req 0 */
# define ATMEGA_IRQ_PCINT1 11 /* 0x0014 PCINT1 Pin Change Interrupt Req 1 */
# define ATMEGA_IRQ_PCINT2 12 /* 0x0016 PCINT2 Pin Change Interrupt Req 2 */
# define ATMEGA_IRQ_WDT 13 /* 0x0018 WDT Watchdog Time-out Interrupt */
# define ATMEGA_IRQ_TIM2_COMPA 14 /* 0x001A TIMER2 COMPA Timer/Counter2 Compare Match A */
# define ATMEGA_IRQ_TIM2_COMPB 15 /* 0x001C TIMER2 COMPB Timer/Counter2 Compare Match B */
# define ATMEGA_IRQ_TIM2_OVF 16 /* 0x001E TIMER2 OVF Timer/Counter2 Overflow */
# define ATMEGA_IRQ_TIM1_CAPT 17 /* 0x0020 TIMER1 CAPT Timer/Counter1 Capture Event */
# define ATMEGA_IRQ_TIM1_COMPA 18 /* 0x0022 TIMER1 COMPA Timer/Counter1 Compare Match A */
# define ATMEGA_IRQ_TIM1_COMPB 19 /* 0x0024 TIMER1 COMPB Timer/Counter1 Compare Match B */
# define ATMEGA_IRQ_TIM1_COMPC 20 /* 0x0026 TIMER1 COMPC Timer/Counter1 Compare Match C */
# define ATMEGA_IRQ_TIM1_OVF 21 /* 0x0028 TIMER1 OVF Timer/Counter1 Overflow */
# define ATMEGA_IRQ_TIM0_COMPA 22 /* 0x002A TIMER0 COMPA Timer/Counter0 Compare Match A */
# define ATMEGA_IRQ_TIM0_COMPB 23 /* 0x002C TIMER0 COMPB Timer/Counter0 Compare match B */
# define ATMEGA_IRQ_TIM0_OVF 24 /* 0x002E TIMER0 OVF Timer/Counter0 Overflow */
# define ATMEGA_IRQ_SPI_STC 25 /* 0x0030 SPI, STC SPI Serial Transfer Complete */
# define ATMEGA_IRQ_USART0_RXC 26 /* 0x0032 USART0 RX USART0 Rx Complete */
# define ATMEGA_IRQ_USART0_UDRE 27 /* 0x0034 USART0 UDRE USART0 Data Register Empty */
# define ATMEGA_IRQ_USART0_TXC 28 /* 0x0036 USART0 TX USART0 Tx Complete */
# define ATMEGA_IRQ_ANA_COMP 29 /* 0x0038 ANALOG COMP Analog Comparator */
# define ATMEGA_IRQ_ADC 30 /* 0x003A ADC ADC Conversion Complete */
# define ATMEGA_IRQ_EE_RDY 31 /* 0x003C EE READY EEPROM Ready */
# define ATMEGA_IRQ_TIM3_CAPT 32 /* 0x003E TIMER3 CAPT Timer/Counter3 Capture Event */
# define ATMEGA_IRQ_TIM3_COMPA 33 /* 0x0040 TIMER3 COMPA Timer/Counter3 Compare Match A */
# define ATMEGA_IRQ_TIM3_COMPB 34 /* 0x0042 TIMER3 COMPB Timer/Counter3 Compare Match B */
# define ATMEGA_IRQ_TIM3_COMPC 35 /* 0x0044 TIMER3 COMPC Timer/Counter3 Compare Match C */
# define ATMEGA_IRQ_TIM3_OVF 36 /* 0x0046 TIMER3 OVF Timer/Counter3 Overflow */
# define ATMEGA_IRQ_USART1_RXC 37 /* 0x0048 USART1 RX USART1 Rx Complete */
# define ATMEGA_IRQ_USART1_UDRE 38 /* 0x004A USART1 UDRE USART1 Data Register Empty */
# define ATMEGA_IRQ_USART1_TXC 39 /* 0x004C USART1 TX USART1 Tx Complete */
# define ATMEGA_IRQ_TWI 40 /* 0x004E TWI 2-wire Serial Interface */
# define ATMEGA_IRQ_SPM_RDY 41 /* 0x0050 SPM READY Store Program Memory Ready */
# define ATMEGA_IRQ_TIM4_CAPT 42 /* 0x0052 TIMER4 CAPT Timer/Counter4 Capture Event */
# define ATMEGA_IRQ_TIM4_COMPA 43 /* 0x0054 TIMER4 COMPA Timer/Counter4 Compare Match A */
# define ATMEGA_IRQ_TIM4_COMPB 44 /* 0x0056 TIMER4 COMPB Timer/Counter4 Compare Match B */
# define ATMEGA_IRQ_TIM4_COMPC 45 /* 0x0058 TIMER4 COMPC Timer/Counter4 Compare Match C */
# define ATMEGA_IRQ_TIM4_OVF 46 /* 0x005A TIMER4 OVF Timer/Counter4 Overflow */
# define ATMEGA_IRQ_TIM5_CAPT 47 /* 0x005C TIMER5 CAPT Timer/Counter5 Capture Event */
# define ATMEGA_IRQ_TIM5_COMPA 48 /* 0x005E TIMER5 COMPA Timer/Counter5 Compare Match A */
# define ATMEGA_IRQ_TIM5_COMPB 49 /* 0x0060 TIMER5 COMPB Timer/Counter5 Compare Match B */
# define ATMEGA_IRQ_TIM5_COMPC 50 /* 0x0062 TIMER5 COMPC Timer/Counter5 Compare Match C */
# define ATMEGA_IRQ_TIM5_OVF 51 /* 0x0064 TIMER5 OVF Timer/Counter5 Overflow */
# define ATMEGA_IRQ_USART2_RXC 52 /* 0x0066 USART2 RX USART2 Rx Complete */
# define ATMEGA_IRQ_USART2_UDRE 53 /* 0x0068 USART2 UDRE USART2 Data Register Empty */
# define ATMEGA_IRQ_USART2_TXC 54 /* 0x006A USART2 TX USART2 Tx Complete */
# define ATMEGA_IRQ_USART3_RXC 55 /* 0x006C USART3 RX USART3 Rx Complete */
# define ATMEGA_IRQ_USART3_UDRE 56 /* 0x006E USART3 UDRE USART3 Data Register Empty */
# define ATMEGA_IRQ_USART3_TXC 57 /* 0x0070 USART3 TX USART3 Tx Complete */
# define NR_IRQS 58
# define ATMEGA_PC_SIZE 24
# define XCPTCONTEXT_REGS 38 /* Size of the register state save array (in bytes) */
#else
#error "Unrecognized chip"
#endif
#define NR_IRQS 34
/****************************************************************************
* Public Types
****************************************************************************/

15
arch/avr/include/avr/irq.h
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@ -91,12 +91,11 @@
/* The program counter is automatically pushed when the interrupt occurs */
#define REG_PCH 35 /* PC */
#define REG_PCL 36
/* Size of the register state save array (in bytes) */
#define XCPTCONTEXT_REGS 37
#define REG_PC0 35 /* PC */
#define REG_PC1 36
#if ATMEGA_PC_SIZE > 16
#define REG_PC2 37
#endif
/****************************************************************************
* Public Types
@ -116,8 +115,8 @@ struct xcptcontext
/* These are saved copies of PC and SR used during signal processing.*/
uint8_t saved_pcl;
uint8_t saved_pch;
uint8_t saved_pc1;
uint8_t saved_pc0;
uint8_t saved_sreg;
#endif

4
arch/avr/src/Makefile
View File

@ -138,10 +138,10 @@ board/libboard$(LIBEXT):
nuttx$(EXEEXT): $(HEAD_OBJ) board/libboard$(LIBEXT)
@echo "LD: nuttx"
$(Q) $(LD) --entry=__start $(LDFLAGS) $(LIBPATHS) -o $(NUTTX)$(EXEEXT) $(HEAD_OBJ) $(EXTRA_OBJS) \
$(Q) $(LD) --entry=__start $(LDFLAGS) $(LIBPATHS) -o $(NUTTX) $(HEAD_OBJ) $(EXTRA_OBJS) \
--start-group $(LDLIBS) $(EXTRA_LIBS) $(LIBGCC) --end-group
ifneq ($(CONFIG_WINDOWS_NATIVE),y)
$(Q) $(NM) $(NUTTX)$(EXEEXT) | \
$(Q) $(NM) $(NUTTX) | \
grep -v '\(compiled\)\|\(\$(OBJEXT)$$\)\|\( [aUw] \)\|\(\.\.ng$$\)\|\(LASH[RL]DI\)' | \
sort > $(TOPDIR)/System.map
endif

4
arch/avr/src/at90usb/at90usb_exceptions.S
View File

@ -112,8 +112,8 @@
* On Entry:
* The return PC and the saved r24 is on the stack, r24 now contains the IRQ number
*
* PCL
* PCH
* PC1
* PC0
* R0
* --- <- SP
*

20
arch/avr/src/atmega/Kconfig
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@ -20,6 +20,11 @@ config ARCH_CHIP_ATMEGA1284P
---help---
Atmel ATMega1284P 8-bit AVR.
config ARCH_CHIP_ATMEGA2560
bool "ATMega2560"
---help---
Atmel ATMega2560 8-bit AVR.
endchoice # ATMega Configuration Options
menu "ATMega Peripheral Selections"
@ -33,5 +38,20 @@ config AVR_USART1
select ARCH_HAVE_USART1
endmenu # ATMega Peripheral Selections
menu "Low level UART driver options"
depends on AVR_USART0 || AVR_USART1
config SERIAL_TERMIOS
bool "Serial driver TERMIOS supported"
depends on AVR_USART0 || AVR_USART1
default n
---help---
Serial driver supports termios.h interfaces (tcsetattr, tcflush, etc.).
If this is not defined, then the terminal settings (baud, parity, etc).
are not configurable at runtime; serial streams cannot be flushed, etc..
endmenu
endif

61
arch/avr/src/atmega/atmega_exceptions.S
View File

@ -131,6 +131,63 @@
HANDLER atmega_t3compa, ATMEGA_IRQ_T3COMPA, excpt_common /* TIMER3 COMPA timer/counter3 compare match a */
HANDLER atmega_t3compb, ATMEGA_IRQ_T3COMPB, excpt_common /* TIMER3 COMPB timer/counter3 compare match b */
HANDLER atmega_t3ovf, ATMEGA_IRQ_T3OVF, excpt_common /* TIMER3 OVF timer/counter3 overflow */
#elif defined(CONFIG_ARCH_CHIP_ATMEGA2560)
HANDLER atmega_int0, ATMEGA_IRQ_INT0, excpt_common /* 0x0002 INT0 External Interrupt Request 0 */
HANDLER atmega_int1, ATMEGA_IRQ_INT1, excpt_common /* 0x0004 INT1 External Interrupt Request 1 */
HANDLER atmega_int2, ATMEGA_IRQ_INT2, excpt_common /* 0x0006 INT2 External Interrupt Request 2 */
HANDLER atmega_int3, ATMEGA_IRQ_INT3, excpt_common /* 0x0008 INT3 External Interrupt Request 3 */
HANDLER atmega_int4, ATMEGA_IRQ_INT4, excpt_common /* 0x000A INT4 External Interrupt Request 4 */
HANDLER atmega_int5, ATMEGA_IRQ_INT5, excpt_common /* 0x000C INT5 External Interrupt Request 5 */
HANDLER atmega_int6, ATMEGA_IRQ_INT6, excpt_common /* 0x000E INT6 External Interrupt Request 6 */
HANDLER atmega_int7, ATMEGA_IRQ_INT7, excpt_common /* 0x0010 INT7 External Interrupt Request 7 */
HANDLER atmega_pcint0, ATMEGA_IRQ_PCINT0, excpt_common /* 0x0012 PCINT0 Pin Change Interrupt Req 0 */
HANDLER atmega_pcint1, ATMEGA_IRQ_PCINT1, excpt_common /* 0x0014 PCINT1 Pin Change Interrupt Req 1 */
HANDLER atmega_pcint2, ATMEGA_IRQ_PCINT2, excpt_common /* 0x0016 PCINT2 Pin Change Interrupt Req 2 */
HANDLER atmega_wdt, ATMEGA_IRQ_WDT, excpt_common /* 0x0018 WDT Watchdog Time-out Interrupt */
HANDLER atmega_tim2_compa, ATMEGA_IRQ_TIM2_COMPA, excpt_common /* 0x001A TIMER2 COMPA Timer/Counter2 Compare Match A */
HANDLER atmega_tim2_compb, ATMEGA_IRQ_TIM2_COMPB, excpt_common /* 0x001C TIMER2 COMPB Timer/Counter2 Compare Match B */
HANDLER atmega_tim2_ovf, ATMEGA_IRQ_TIM2_OVF, excpt_common /* 0x001E TIMER2 OVF Timer/Counter2 Overflow */
HANDLER atmega_tim1_capt, ATMEGA_IRQ_TIM1_CAPT, excpt_common /* 0x0020 TIMER1 CAPT Timer/Counter1 Capture Event */
HANDLER atmega_tim1_compa, ATMEGA_IRQ_TIM1_COMPA, excpt_common /* 0x0022 TIMER1 COMPA Timer/Counter1 Compare Match A */
HANDLER atmega_tim1_compb, ATMEGA_IRQ_TIM1_COMPB, excpt_common /* 0x0024 TIMER1 COMPB Timer/Counter1 Compare Match B */
HANDLER atmega_tim1_compc, ATMEGA_IRQ_TIM1_COMPC, excpt_common /* 0x0026 TIMER1 COMPC Timer/Counter1 Compare Match C */
HANDLER atmega_tim1_ovf, ATMEGA_IRQ_TIM1_OVF, excpt_common /* 0x0028 TIMER1 OVF Timer/Counter1 Overflow */
HANDLER atmega_tim0_compa, ATMEGA_IRQ_TIM0_COMPA, excpt_common /* 0x002A TIMER0 COMPA Timer/Counter0 Compare Match A */
HANDLER atmega_tim0_compb, ATMEGA_IRQ_TIM0_COMPB, excpt_common /* 0x002C TIMER0 COMPB Timer/Counter0 Compare match B */
HANDLER atmega_tim0_ovf, ATMEGA_IRQ_TIM0_OVF, excpt_common /* 0x002E TIMER0 OVF Timer/Counter0 Overflow */
HANDLER atmega_spi_stc, ATMEGA_IRQ_SPI_STC, excpt_common /* 0x0030 SPI, STC SPI Serial Transfer Complete */
HANDLER atmega_usart0_rxc, ATMEGA_IRQ_USART0_RXC, excpt_common /* 0x0032 USART0 RX USART0 Rx Complete */
HANDLER atmega_usart0_udre, ATMEGA_IRQ_USART0_UDRE, excpt_common /* 0x0034 USART0 UDRE USART0 Data Register Empty */
HANDLER atmega_usart0_txc, ATMEGA_IRQ_USART0_TXC, excpt_common /* 0x0036 USART0 TX USART0 Tx Complete */
HANDLER atmega_ana_comp, ATMEGA_IRQ_ANA_COMP, excpt_common /* 0x0038 ANALOG COMP Analog Comparator */
HANDLER atmega_adc, ATMEGA_IRQ_ADC, excpt_common /* 0x003A ADC ADC Conversion Complete */
HANDLER atmega_ee_rdy, ATMEGA_IRQ_EE_RDY, excpt_common /* 0x003C EE READY EEPROM Ready */
HANDLER atmega_tim3_capt, ATMEGA_IRQ_TIM3_CAPT, excpt_common /* 0x003E TIMER3 CAPT Timer/Counter3 Capture Event */
HANDLER atmega_tim3_compa, ATMEGA_IRQ_TIM3_COMPA, excpt_common /* 0x0040 TIMER3 COMPA Timer/Counter3 Compare Match A */
HANDLER atmega_tim3_compb, ATMEGA_IRQ_TIM3_COMPB, excpt_common /* 0x0042 TIMER3 COMPB Timer/Counter3 Compare Match B */
HANDLER atmega_tim3_compc, ATMEGA_IRQ_TIM3_COMPC, excpt_common /* 0x0044 TIMER3 COMPC Timer/Counter3 Compare Match C */
HANDLER atmega_tim3_ovf, ATMEGA_IRQ_TIM3_OVF, excpt_common /* 0x0046 TIMER3 OVF Timer/Counter3 Overflow */
HANDLER atmega_usart1_rxc, ATMEGA_IRQ_USART1_RXC, excpt_common /* 0x0048 USART1 RX USART1 Rx Complete */
HANDLER atmega_usart1_udre, ATMEGA_IRQ_USART1_UDRE, excpt_common /* 0x004A USART1 UDRE USART1 Data Register Empty */
HANDLER atmega_usart1_txc, ATMEGA_IRQ_USART1_TXC, excpt_common /* 0x004C USART1 TX USART1 Tx Complete */
HANDLER atmega_twi, ATMEGA_IRQ_TWI, excpt_common /* 0x004E TWI 2-wire Serial Interface */
HANDLER atmega_spm_rdy, ATMEGA_IRQ_SPM_RDY, excpt_common /* 0x0050 SPM READY Store Program Memory Ready */
HANDLER atmega_tim4_capt, ATMEGA_IRQ_TIM4_CAPT, excpt_common /* 0x0052 TIMER4 CAPT Timer/Counter4 Capture Event */
HANDLER atmega_tim4_compa, ATMEGA_IRQ_TIM4_COMPA, excpt_common /* 0x0054 TIMER4 COMPA Timer/Counter4 Compare Match A */
HANDLER atmega_tim4_compb, ATMEGA_IRQ_TIM4_COMPB, excpt_common /* 0x0056 TIMER4 COMPB Timer/Counter4 Compare Match B */
HANDLER atmega_tim4_compc, ATMEGA_IRQ_TIM4_COMPC, excpt_common /* 0x0058 TIMER4 COMPC Timer/Counter4 Compare Match C */
HANDLER atmega_tim4_ovf, ATMEGA_IRQ_TIM4_OVF, excpt_common /* 0x005A TIMER4 OVF Timer/Counter4 Overflow */
HANDLER atmega_tim5_capt, ATMEGA_IRQ_TIM5_CAPT, excpt_common /* 0x005C TIMER5 CAPT Timer/Counter5 Capture Event */
HANDLER atmega_tim5_compa, ATMEGA_IRQ_TIM5_COMPA, excpt_common /* 0x005E TIMER5 COMPA Timer/Counter5 Compare Match A */
HANDLER atmega_tim5_compb, ATMEGA_IRQ_TIM5_COMPB, excpt_common /* 0x0060 TIMER5 COMPB Timer/Counter5 Compare Match B */
HANDLER atmega_tim5_compc, ATMEGA_IRQ_TIM5_COMPC, excpt_common /* 0x0062 TIMER5 COMPC Timer/Counter5 Compare Match C */
HANDLER atmega_tim5_ovf, ATMEGA_IRQ_TIM5_OVF, excpt_common /* 0x0064 TIMER5 OVF Timer/Counter5 Overflow */
HANDLER atmega_usart2_rxc, ATMEGA_IRQ_USART2_RXC, excpt_common /* 0x0066 USART2 RX USART2 Rx Complete */
HANDLER atmega_usart2_udre, ATMEGA_IRQ_USART2_UDRE, excpt_common /* 0x0068 USART2 UDRE USART2 Data Register Empty */
HANDLER atmega_usart2_txc, ATMEGA_IRQ_USART2_TXC, excpt_common /* 0x006A USART2 TX USART2 Tx Complete */
HANDLER atmega_usart3_rxc, ATMEGA_IRQ_USART3_RXC, excpt_common /* 0x006C USART3 RX USART3 Rx Complete */
HANDLER atmega_usart3_udre, ATMEGA_IRQ_USART3_UDRE, excpt_common /* 0x006E USART3 UDRE USART3 Data Register Empty */
HANDLER atmega_usart3_txc, ATMEGA_IRQ_USART3_TXC, excpt_common /* 0x0070 USART3 TX USART3 Tx Complete */
#else
# error "Unrecognized chip"
#endif
@ -144,8 +201,8 @@
* On Entry:
* The return PC and the saved r24 is on the stack, r24 now contains the IRQ number
*
* PCL
* PCH
* PC1
* PC0
* R0
* --- <- SP
*

126
arch/avr/src/atmega/atmega_head.S
View File

@ -39,10 +39,12 @@
#include <nuttx/config.h>
#include <arch/irq.h>
#include <avr/io.h>
#include <avr/common.h>
#include <avr/sfr_defs.h>
#include <arch/irq.h>
/****************************************************************************
* Pre-processor definitions
****************************************************************************/
@ -147,6 +149,63 @@
.global atmega_t3compa /* TIMER3 COMPA timer/counter3 compare match a */
.global atmega_t3compb /* TIMER3 COMPB timer/counter3 compare match b */
.global atmega_t3ovf /* TIMER3 OVF timer/counter3 overflow */
#elif defined(CONFIG_ARCH_CHIP_ATMEGA2560)
.global atmega_int0 /* 0x0002 INT0 External Interrupt Request 0 */
.global atmega_int1 /* 0x0004 INT1 External Interrupt Request 1 */
.global atmega_int2 /* 0x0006 INT2 External Interrupt Request 2 */
.global atmega_int3 /* 0x0008 INT3 External Interrupt Request 3 */
.global atmega_int4 /* 0x000A INT4 External Interrupt Request 4 */
.global atmega_int5 /* 0x000C INT5 External Interrupt Request 5 */
.global atmega_int6 /* 0x000E INT6 External Interrupt Request 6 */
.global atmega_int7 /* 0x0010 INT7 External Interrupt Request 7 */
.global atmega_pcint0 /* 0x0012 PCINT0 Pin Change Interrupt Req 0 */
.global atmega_pcint1 /* 0x0014 PCINT1 Pin Change Interrupt Req 1 */
.global atmega_pcint2 /* 0x0016 PCINT2 Pin Change Interrupt Req 2 */
.global atmega_wdt /* 0x0018 WDT Watchdog Time-out Interrupt */
.global atmega_tim2_compa /* 0x001A TIMER2 COMPA Timer/Counter2 Compare Match A */
.global atmega_tim2_compb /* 0x001C TIMER2 COMPB Timer/Counter2 Compare Match B */
.global atmega_tim2_ovf /* 0x001E TIMER2 OVF Timer/Counter2 Overflow */
.global atmega_tim1_capt /* 0x0020 TIMER1 CAPT Timer/Counter1 Capture Event */
.global atmega_tim1_compa /* 0x0022 TIMER1 COMPA Timer/Counter1 Compare Match A */
.global atmega_tim1_compb /* 0x0024 TIMER1 COMPB Timer/Counter1 Compare Match B */
.global atmega_tim1_compc /* 0x0026 TIMER1 COMPC Timer/Counter1 Compare Match C */
.global atmega_tim1_ovf /* 0x0028 TIMER1 OVF Timer/Counter1 Overflow */
.global atmega_tim0_compa /* 0x002A TIMER0 COMPA Timer/Counter0 Compare Match A */
.global atmega_tim0_compb /* 0x002C TIMER0 COMPB Timer/Counter0 Compare match B */
.global atmega_tim0_ovf /* 0x002E TIMER0 OVF Timer/Counter0 Overflow */
.global atmega_spi_stc /* 0x0030 SPI, STC SPI Serial Transfer Complete */
.global atmega_usart0_rxc /* 0x0032 USART0 RX USART0 Rx Complete */
.global atmega_usart0_udre /* 0x0034 USART0 UDRE USART0 Data Register Empty */
.global atmega_usart0_txc /* 0x0036 USART0 TX USART0 Tx Complete */
.global atmega_ana_comp /* 0x0038 ANALOG COMP Analog Comparator */
.global atmega_adc /* 0x003A ADC ADC Conversion Complete */
.global atmega_ee_rdy /* 0x003C EE READY EEPROM Ready */
.global atmega_tim3_capt /* 0x003E TIMER3 CAPT Timer/Counter3 Capture Event */
.global atmega_tim3_compa /* 0x0040 TIMER3 COMPA Timer/Counter3 Compare Match A */
.global atmega_tim3_compb /* 0x0042 TIMER3 COMPB Timer/Counter3 Compare Match B */
.global atmega_tim3_compc /* 0x0044 TIMER3 COMPC Timer/Counter3 Compare Match C */
.global atmega_tim3_ovf /* 0x0046 TIMER3 OVF Timer/Counter3 Overflow */
.global atmega_usart1_rxc /* 0x0048 USART1 RX USART1 Rx Complete */
.global atmega_usart1_udre /* 0x004A USART1 UDRE USART1 Data Register Empty */
.global atmega_usart1_txc /* 0x004C USART1 TX USART1 Tx Complete */
.global atmega_twi /* 0x004E TWI 2-wire Serial Interface */
.global atmega_spm_rdy /* 0x0050 SPM READY Store Program Memory Ready */
.global atmega_tim4_capt /* 0x0052 TIMER4 CAPT Timer/Counter4 Capture Event */
.global atmega_tim4_compa /* 0x0054 TIMER4 COMPA Timer/Counter4 Compare Match A */
.global atmega_tim4_compb /* 0x0056 TIMER4 COMPB Timer/Counter4 Compare Match B */
.global atmega_tim4_compc /* 0x0058 TIMER4 COMPC Timer/Counter4 Compare Match C */
.global atmega_tim4_ovf /* 0x005A TIMER4 OVF Timer/Counter4 Overflow */
.global atmega_tim5_capt /* 0x005C TIMER5 CAPT Timer/Counter5 Capture Event */
.global atmega_tim5_compa /* 0x005E TIMER5 COMPA Timer/Counter5 Compare Match A */
.global atmega_tim5_compb /* 0x0060 TIMER5 COMPB Timer/Counter5 Compare Match B */
.global atmega_tim5_compc /* 0x0062 TIMER5 COMPC Timer/Counter5 Compare Match C */
.global atmega_tim5_ovf /* 0x0064 TIMER5 OVF Timer/Counter5 Overflow */
.global atmega_usart2_rxc /* 0x0066 USART2 RX USART2 Rx Complete */
.global atmega_usart2_udre /* 0x0068 USART2 UDRE USART2 Data Register Empty */
.global atmega_usart2_txc /* 0x006A USART2 TX USART2 Tx Complete */
.global atmega_usart3_rxc /* 0x006C USART3 RX USART3 Rx Complete */
.global atmega_usart3_udre /* 0x006E USART3 UDRE USART3 Data Register Empty */
.global atmega_usart3_txc /* 0x0070 USART3 TX USART3 Tx Complete */
#else
#error "Unrecognized chip"
#endif
@ -241,6 +300,63 @@ vectortab:
vector atmega_t3compa /* TIMER3 COMPA timer/counter3 compare match a */
vector atmega_t3compb /* TIMER3 COMPB timer/counter3 compare match b */
vector atmega_t3ovf /* TIMER3 OVF timer/counter3 overflow */
#elif defined(CONFIG_ARCH_CHIP_ATMEGA2560)
vector atmega_int0 /* 0x0002 INT0 External Interrupt Request 0 */
vector atmega_int1 /* 0x0004 INT1 External Interrupt Request 1 */
vector atmega_int2 /* 0x0006 INT2 External Interrupt Request 2 */
vector atmega_int3 /* 0x0008 INT3 External Interrupt Request 3 */
vector atmega_int4 /* 0x000A INT4 External Interrupt Request 4 */
vector atmega_int5 /* 0x000C INT5 External Interrupt Request 5 */
vector atmega_int6 /* 0x000E INT6 External Interrupt Request 6 */
vector atmega_int7 /* 0x0010 INT7 External Interrupt Request 7 */
vector atmega_pcint0 /* 0x0012 PCINT0 Pin Change Interrupt Req 0 */
vector atmega_pcint1 /* 0x0014 PCINT1 Pin Change Interrupt Req 1 */
vector atmega_pcint2 /* 0x0016 PCINT2 Pin Change Interrupt Req 2 */
vector atmega_wdt /* 0x0018 WDT Watchdog Time-out Interrupt */
vector atmega_tim2_compa /* 0x001A TIMER2 COMPA Timer/Counter2 Compare Match A */
vector atmega_tim2_compb /* 0x001C TIMER2 COMPB Timer/Counter2 Compare Match B */
vector atmega_tim2_ovf /* 0x001E TIMER2 OVF Timer/Counter2 Overflow */
vector atmega_tim1_capt /* 0x0020 TIMER1 CAPT Timer/Counter1 Capture Event */
vector atmega_tim1_compa /* 0x0022 TIMER1 COMPA Timer/Counter1 Compare Match A */
vector atmega_tim1_compb /* 0x0024 TIMER1 COMPB Timer/Counter1 Compare Match B */
vector atmega_tim1_compc /* 0x0026 TIMER1 COMPC Timer/Counter1 Compare Match C */
vector atmega_tim1_ovf /* 0x0028 TIMER1 OVF Timer/Counter1 Overflow */
vector atmega_tim0_compa /* 0x002A TIMER0 COMPA Timer/Counter0 Compare Match A */
vector atmega_tim0_compb /* 0x002C TIMER0 COMPB Timer/Counter0 Compare match B */
vector atmega_tim0_ovf /* 0x002E TIMER0 OVF Timer/Counter0 Overflow */
vector atmega_spi_stc /* 0x0030 SPI, STC SPI Serial Transfer Complete */
vector atmega_usart0_rxc /* 0x0032 USART0 RX USART0 Rx Complete */
vector atmega_usart0_udre /* 0x0034 USART0 UDRE USART0 Data Register Empty */
vector atmega_usart0_txc /* 0x0036 USART0 TX USART0 Tx Complete */
vector atmega_ana_comp /* 0x0038 ANALOG COMP Analog Comparator */
vector atmega_adc /* 0x003A ADC ADC Conversion Complete */
vector atmega_ee_rdy /* 0x003C EE READY EEPROM Ready */
vector atmega_tim3_capt /* 0x003E TIMER3 CAPT Timer/Counter3 Capture Event */
vector atmega_tim3_compa /* 0x0040 TIMER3 COMPA Timer/Counter3 Compare Match A */
vector atmega_tim3_compb /* 0x0042 TIMER3 COMPB Timer/Counter3 Compare Match B */
vector atmega_tim3_compc /* 0x0044 TIMER3 COMPC Timer/Counter3 Compare Match C */
vector atmega_tim3_ovf /* 0x0046 TIMER3 OVF Timer/Counter3 Overflow */
vector atmega_usart1_rxc /* 0x0048 USART1 RX USART1 Rx Complete */
vector atmega_usart1_udre /* 0x004A USART1 UDRE USART1 Data Register Empty */
vector atmega_usart1_txc /* 0x004C USART1 TX USART1 Tx Complete */
vector atmega_twi /* 0x004E TWI 2-wire Serial Interface */
vector atmega_spm_rdy /* 0x0050 SPM READY Store Program Memory Ready */
vector atmega_tim4_capt /* 0x0052 TIMER4 CAPT Timer/Counter4 Capture Event */
vector atmega_tim4_compa /* 0x0054 TIMER4 COMPA Timer/Counter4 Compare Match A */
vector atmega_tim4_compb /* 0x0056 TIMER4 COMPB Timer/Counter4 Compare Match B */
vector atmega_tim4_compc /* 0x0058 TIMER4 COMPC Timer/Counter4 Compare Match C */
vector atmega_tim4_ovf /* 0x005A TIMER4 OVF Timer/Counter4 Overflow */
vector atmega_tim5_capt /* 0x005C TIMER5 CAPT Timer/Counter5 Capture Event */
vector atmega_tim5_compa /* 0x005E TIMER5 COMPA Timer/Counter5 Compare Match A */
vector atmega_tim5_compb /* 0x0060 TIMER5 COMPB Timer/Counter5 Compare Match B */
vector atmega_tim5_compc /* 0x0062 TIMER5 COMPC Timer/Counter5 Compare Match C */
vector atmega_tim5_ovf /* 0x0064 TIMER5 OVF Timer/Counter5 Overflow */
vector atmega_usart2_rxc /* 0x0066 USART2 RX USART2 Rx Complete */
vector atmega_usart2_udre /* 0x0068 USART2 UDRE USART2 Data Register Empty */
vector atmega_usart2_txc /* 0x006A USART2 TX USART2 Tx Complete */
vector atmega_usart3_rxc /* 0x006C USART3 RX USART3 Rx Complete */
vector atmega_usart3_udre /* 0x006E USART3 UDRE USART3 Data Register Empty */
vector atmega_usart3_txc /* 0x0070 USART3 TX USART3 Tx Complete */
#else
#error "Unrecognized chip"
#endif
@ -254,6 +370,14 @@ vectortab:
.func __start
__start:
/* no interrupts! Useful for software reset by jumping to address 0 */
cli
#if defined(EIND)
/* set EIND to 0, just to be sure we are sane */
out _SFR_IO_ADDR(EIND), 0 // EIND = 0x3c
#endif /* EIND */
/* Clear the zero register, clear the status register and initialize the
* IDLE thread stack
*/

2
arch/avr/src/atmega/atmega_lowinit.c
View File

@ -131,7 +131,7 @@ void up_lowinit(void)
#ifdef CONFIG_ARCH_CHIP_ATMEGA1284P
CLKPR = 0x80;
CLKPR = 0;
#else
#elif defined(XDIV)
XDIV = 0;
#endif

10
arch/avr/src/atmega/atmega_serial.c
View File

@ -561,12 +561,13 @@ static int usart1_txinterrupt(int irq, void *context)
#ifdef CONFIG_AVR_USART0
static int usart0_ioctl(struct file *filep, int cmd, unsigned long arg)
{
#if 0 /* Reserved for future growth */
#if CONFIG_SERIAL_TERMIOS
int ret = OK;
switch (cmd)
{
case xxx: /* Add commands here */
case TCGETS:
case TCSETS:
break;
default:
@ -584,12 +585,13 @@ static int usart0_ioctl(struct file *filep, int cmd, unsigned long arg)
#ifdef CONFIG_AVR_USART1
static int usart1_ioctl(struct file *filep, int cmd, unsigned long arg)
{
#if 0 /* Reserved for future growth */
#if CONFIG_SERIAL_TERMIOS
int ret = OK;
switch (cmd)
{
case xxx: /* Add commands here */
case TCGETS:
case TCSETS:
break;
default:

8
arch/avr/src/atmega/atmega_timerisr.c
View File

@ -172,11 +172,17 @@ void up_timer_initialize(void)
/* Attach the timer interrupt vector */
#if defined(ATMEGA_IRQ_T1COMPA)
(void)irq_attach(ATMEGA_IRQ_T1COMPA, (xcpt_t)up_timerisr);
#elif defined(ATMEGA_IRQ_TIM1_COMPA)
(void)irq_attach(ATMEGA_IRQ_TIM1_COMPA, (xcpt_t)up_timerisr);
#else
# error "Unable to find IRQ for timer"
#endif
/* Enable the interrupt on compare match A */
#ifdef CONFIG_ARCH_CHIP_ATMEGA1284P
#if defined(TIMSK1)
TIMSK1 |= (1 << OCIE1A);
#else
TIMSK |= (1 << OCIE1A);

2
arch/avr/src/avr/Toolchain.defs
View File

@ -80,6 +80,8 @@ else ifeq ($(CONFIG_ARCH_CHIP_AT90USB1286),y)
ARCHCPUFLAGS += -mmcu=at90usb1286
else ifeq ($(CONFIG_ARCH_CHIP_AT90USB1287),y)
ARCHCPUFLAGS += -mmcu=at90usb1287
else ifeq ($(CONFIG_ARCH_CHIP_ATMEGA2560),y)
ARCHCPUFLAGS += -mmcu=atmega2560
else
$(error "No valid CONFIG_ARCH_CHIP_ set in the configuration")
endif

65
arch/avr/src/avr/excptmacros.h
View File

@ -99,16 +99,16 @@
* sp - Points to the top of the stack. The PC is already on the stack.
* Only the stack is available for storage
*
* PCL
* PCH
* PC1
* PC0
* --- <- SP
*
* At completion:
* Stack pointer is incremented by one, the saved r24 is on the stack, r24 now contains the
* IRQ number
*
* PCL
* PCH
* PC1
* PC0
* R0
* --- <- SP
*
@ -134,8 +134,8 @@
* sp - Points to the top of the stack
* Only the stack is available for storage
*
* PCL
* PCH
* PC1
* PC0
* R24
* --- <- SP
*
@ -333,10 +333,13 @@
.macro USER_SAVE
/* Pop the return address from the stack (PCH then PCL). R18:19 are Call-used */
/* Pop the return address from the stack (PC0 then PC1). R18:19 are Call-used */
pop r19 /* r19=PCH */
pop r18 /* r18=PCL */
#if ATMEGA_PC_SIZE > 16
pop r20
#endif /* ATMEGA_PC_SIZE */
pop r19
pop r18
/* Save the current stack pointer as it would be after the return(SPH then SPL). */
@ -398,9 +401,11 @@
adiw r26, 2 /* Two registers: r24-r25 */
/* Save the return address that we have saved in r18:19*/
st x+, r19 /* r19=PCH */
st x+, r18 /* r18=PCL */
#if ATMEGA_PC_SIZE > 16
st x+, r20
#endif /* ATMEGA_PC_SIZE */
st x+, r19
st x+, r18
.endm
/********************************************************************************************
@ -424,12 +429,16 @@
.macro TCB_RESTORE, regs
/* X [r36:27] points to the register save block. Get an offset pointer to the PC in
/* X [r26:27] points to the register save block. Get an offset pointer to the PC in
* Y [r28:29]
*/
movw r28, r26 /* Get a pointer to the PCH/PCL storage location */
adiw r28, REG_PCH
movw r28, r26 /* Get a pointer to the PC0/PC1 storage location */
#if ATMEGA_PC_SIZE <= 16
adiw r28, REG_PC0
#else
adiw r28, REG_PC2
#endif
/* Fetch and set the new stack pointer */
@ -441,21 +450,35 @@
/* Fetch the return address and save it at the bottom of the new stack so
* that we can iret to switch contexts. The new stack is now:
*
* PCL
* PCH
* PC2 (for 24-bit PC arch)
* PC1
* PC0
* --- <- SP
*/
ld r25, y+ /* Load PCH (r25) then PCL (r24) */
#if ATMEGA_PC_SIZE <= 16
ld r25, y+ /* Load PC0 (r25) then PC1 (r24) */
ld r24, y+
push r24 /* Push PCH and PCL on the stack (PCL then PCH) */
push r24 /* Push PC0 and PC1 on the stack (PC1 then PC0) */
push r25
#else
ld r25, y /* Load PC2 (r25) */
subi r28,1
push r25
ld r25, y /* Load PC1 (r25) */
subi r28,1
push r25
ld r25, y /* Load PC0 (r25) */
subi r28,1
push r25
#endif
/* Then get value of X [r26:r27]. Save X on the new stack where we can
* recover it later. The new stack is now:
*
* PCL
* PCH
* PC2 (for 24-bit PC arch)
* PC1
* PC0
* R26
* R27
* --- <- SP

2
arch/avr/src/avr/up_createstack.c
View File

@ -160,7 +160,9 @@ int up_create_stack(FAR struct tcb_s *tcb, size_t stack_size, uint8_t ttype)
tcb->adj_stack_ptr = (FAR void *)top_of_stack;
tcb->adj_stack_size = stack_size;
#if defined(ARCH_HAVE_LEDS)
board_autoled_on(LED_STACKCREATED);
#endif
return OK;
}

9
arch/avr/src/avr/up_dumpstate.c
View File

@ -151,10 +151,17 @@ static inline void up_registerdump(void)
current_regs[REG_R28], current_regs[REG_R29],
current_regs[REG_R30], current_regs[REG_R31]);
#if !defined(REG_PC2)
lldbg("PC: %02x%02x SP: %02x%02x SREG: %02x\n",
current_regs[REG_PCH], current_regs[REG_PCL],
current_regs[REG_PC0], current_regs[REG_PC1],
current_regs[REG_SPH], current_regs[REG_SPL],
current_regs[REG_SREG]);
#else
lldbg("PC: %02x%02x%02x SP: %02x%02x SREG: %02x\n",
current_regs[REG_PC0], current_regs[REG_PC1], current_regs[REG_PC2],
current_regs[REG_SPH], current_regs[REG_SPL],
current_regs[REG_SREG]);
#endif
}
}

10
arch/avr/src/avr/up_initialstate.c
View File

@ -96,8 +96,14 @@ void up_initial_state(struct tcb_s *tcb)
/* Save the task entry point */
xcp->regs[REG_PCH] = (uint8_t)((uint16_t)tcb->start >> 8);
xcp->regs[REG_PCL] = (uint8_t)((uint16_t)tcb->start & 0xff);
#if !defined(REG_PC2)
xcp->regs[REG_PC0] = (uint8_t)((uint16_t)tcb->start >> 8);
xcp->regs[REG_PC1] = (uint8_t)((uint16_t)tcb->start & 0xff);
#else
xcp->regs[REG_PC0] = (uint8_t)((uint32_t)tcb->start >> 16);
xcp->regs[REG_PC1] = (uint8_t)((uint32_t)tcb->start >> 8);
xcp->regs[REG_PC2] = (uint8_t)((uint32_t)tcb->start & 0xff);
#endif
/* Enable or disable interrupts, based on user configuration */

36
arch/avr/src/avr/up_schedulesigaction.c
View File

@ -154,16 +154,24 @@ void up_schedule_sigaction(struct tcb_s *tcb, sig_deliver_t sigdeliver)
*/
tcb->xcp.sigdeliver = sigdeliver;
tcb->xcp.saved_pcl = current_regs[REG_PCL];
tcb->xcp.saved_pch = current_regs[REG_PCH];
tcb->xcp.saved_pc0 = current_regs[REG_PC0];
tcb->xcp.saved_pc1 = current_regs[REG_PC1];
#if defined(REG_PC2)
tcb->xcp.saved_pc2 = current_regs[REG_PC2];
#endif
tcb->xcp.saved_sreg = current_regs[REG_SREG];
/* Then set up to vector to the trampoline with interrupts
* disabled
*/
current_regs[REG_PCL] = (uint16_t)up_sigdeliver & 0xff;
current_regs[REG_PCH] = (uint16_t)up_sigdeliver >> 8;
#if !defined(REG_PC2)
current_regs[REG_PC0] = (uint16_t)up_sigdeliver >> 8;
current_regs[REG_PC1] = (uint16_t)up_sigdeliver & 0xff;
#else
current_regs[REG_PC0] = (uint32_t)up_sigdeliver >> 16;
current_regs[REG_PC1] = (uint32_t)up_sigdeliver >> 8;
current_regs[REG_PC2] = (uint32_t)up_sigdeliver & 0xff;
#endif
current_regs[REG_SREG] &= ~(1 << SREG_I);
/* And make sure that the saved context in the TCB
@ -188,16 +196,26 @@ void up_schedule_sigaction(struct tcb_s *tcb, sig_deliver_t sigdeliver)
*/
tcb->xcp.sigdeliver = sigdeliver;
tcb->xcp.saved_pcl = tcb->xcp.regs[REG_PCL];
tcb->xcp.saved_pch = tcb->xcp.regs[REG_PCH];
tcb->xcp.saved_pc0 = tcb->xcp.regs[REG_PC0];
tcb->xcp.saved_pc1 = tcb->xcp.regs[REG_PC1];
#if defined(REG_PC2)
tcb->xcp.saved_pc2 = tcb->xcp.regs[REG_PC2];
#endif
tcb->xcp.saved_sreg = tcb->xcp.regs[REG_SREG];
/* Then set up to vector to the trampoline with interrupts
* disabled
*/
tcb->xcp.regs[REG_PCL] = (uint16_t)up_sigdeliver & 0xff;
tcb->xcp.regs[REG_PCH] = (uint16_t)up_sigdeliver >> 8;
#if !defined(REG_PC2)
tcb->xcp.regs[REG_PC0] = (uint16_t)up_sigdeliver >> 8;
tcb->xcp.regs[REG_PC1] = (uint16_t)up_sigdeliver & 0xff;
#else
tcb->xcp.regs[REG_PC0] = (uint32_t)up_sigdeliver >> 16;
tcb->xcp.regs[REG_PC1] = (uint32_t)up_sigdeliver >> 8;
tcb->xcp.regs[REG_PC2] = (uint32_t)up_sigdeliver & 0xff;
#endif
tcb->xcp.regs[REG_SREG] &= ~(1 << SREG_I);
}
}

7
arch/avr/src/avr/up_sigdeliver.c
View File

@ -101,8 +101,11 @@ void up_sigdeliver(void)
/* Save the real return state on the stack. */
up_copystate(regs, rtcb->xcp.regs);
regs[REG_PCL] = rtcb->xcp.saved_pcl;
regs[REG_PCH] = rtcb->xcp.saved_pch;
regs[REG_PC0] = rtcb->xcp.saved_pc0;
regs[REG_PC1] = rtcb->xcp.saved_pc1;
#if defined(REG_PC2)
regs[REG_PC2] = rtcb->xcp.saved_pc2;
#endif
regs[REG_SREG] = rtcb->xcp.saved_sreg;
/* Get a local copy of the sigdeliver function pointer. We do this so that

2
arch/avr/src/avr/up_switchcontext.S
View File

@ -39,6 +39,8 @@
#include <nuttx/config.h>
#include <arch/irq.h>
#include "excptmacros.h"
/************************************************************************************

2
arch/avr/src/common/up_initialize.c
View File

@ -297,6 +297,8 @@ void up_initialize(void)
up_usbinitialize();
#if defined(ARCH_HAVE_LEDS)
board_autoled_on(LED_IRQSENABLED);
#endif
}