SAMA5D4: Various changes to get the SAMA4D-EK to build
This commit is contained in:
Gregory Nutt
parent
a295209481
commit
87eacd6bf2
@ -137,7 +137,7 @@
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* for example)
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*/
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#elif defined(CONFIG_ARCH_CHIP_ATSAMA5D41) || defined(CONFIG_ARCH_CHIP_ATSAMA5D42) \
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#elif defined(CONFIG_ARCH_CHIP_ATSAMA5D41) || defined(CONFIG_ARCH_CHIP_ATSAMA5D42) || \
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defined(CONFIG_ARCH_CHIP_ATSAMA5D43) || defined(CONFIG_ARCH_CHIP_ATSAMA5D44)
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# undef ATSAMA5D3 /* Not SAMA5D3 family */
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# define ATSAMA5D4 1 /* SAMA5D4 family */
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@ -55,6 +55,8 @@
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#if defined(ATSAMA5D3)
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# include <arch/sama5/sama5d3_irq.h>
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#elif defined(ATSAMA5D4)
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# include <arch/sama5/sama5d4_irq.h>
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#else
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# error Unrecognized SAMA5 family
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#endif
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@ -85,7 +85,7 @@
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#define SAM_PID_UHPHS (32) /* USB Host High Speed */
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#define SAM_PID_UDPHS (33) /* USB Device High Speed */
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#define SAM_PID_GMAC (34) /* Gigabit Ethernet MAC */
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#define SAM_PID_EMAC (35) /* Ethernet MAC */
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#define SAM_PID_EMAC0 (35) /* Ethernet MAC 0 */
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#define SAM_PID_LCDC (36) /* LCD Controller */
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#define SAM_PID_ISI (37) /* Image Sensor Interface */
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#define SAM_PID_SSC0 (38) /* Synchronous Serial Controller 0 */
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@ -139,7 +139,7 @@
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#define SAM_IRQ_UHPHS SAM_PID_UHPHS /* USB Host High Speed */
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#define SAM_IRQ_UDPHS SAM_PID_UDPHS /* USB Device High Speed */
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#define SAM_IRQ_GMAC SAM_PID_GMAC /* Gigabit Ethernet MAC */
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#define SAM_IRQ_EMAC SAM_PID_EMAC /* Ethernet MAC */
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#define SAM_IRQ_EMAC0 SAM_PID_EMAC /* Ethernet MAC 0 */
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#define SAM_IRQ_LCDC SAM_PID_LCDC /* LCD Controller */
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#define SAM_IRQ_ISI SAM_PID_ISI /* Image Sensor Interface */
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#define SAM_IRQ_SSC0 SAM_PID_SSC0 /* Synchronous Serial Controller 0 */
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438
arch/arm/include/sama5/sama5d4_irq.h
Executable file
438
arch/arm/include/sama5/sama5d4_irq.h
Executable file
@ -0,0 +1,438 @@
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/****************************************************************************************
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* arch/arm/include/sama5/sama5d4x_irq.h
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*
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* Copyright (C) 2014 Gregory Nutt. All rights reserved.
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* Author: Gregory Nutt <gnutt@nuttx.org>
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in
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* the documentation and/or other materials provided with the
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* distribution.
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* 3. Neither the name NuttX nor the names of its contributors may be
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* used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
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* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
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* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
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* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
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* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
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* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
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* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*
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****************************************************************************************/
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/* This file should never be included directed but, rather, only indirectly through
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* nuttx/irq.h
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*/
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#ifndef __ARCH_ARM_INCLUDE_SAMA5_SAMA5D4X_IRQ_H
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#define __ARCH_ARM_INCLUDE_SAMA5_SAMA5D4X_IRQ_H
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/****************************************************************************************
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* Included Files
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****************************************************************************************/
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/****************************************************************************************
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* Definitions
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****************************************************************************************/
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/* SAMA5D3 Peripheral Identifiers */
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#define SAM_PID_FIQ (0) /* Advanced Interrupt Controller FIQ */
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#define SAM_PID_SYS (1) /* System Controller Interrupt PMC */
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#define SAM_PID_ARM (2) /* Performance Monitor Unit */
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#define SAM_PID_PIT (3) /* Periodic Interval Timer Interrupt */
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#define SAM_PID_WDT (4) /* Watchdog timer Interrupt */
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#define SAM_PID_PIOD (5) /* Parallel I/O Controller D */
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#define SAM_PID_USART0 (6) /* USART 0 */
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#define SAM_PID_USART1 (7) /* USART 1 */
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#define SAM_PID_XDMAC0 (8) /* DMA Controller 0 */
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#define SAM_PID_ICM (9) /* Integrity Check Monitor */
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#define SAM_PID_CPKCC (10) /* Classic Public Key Crypto Controller */
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/* 11 Undefined */
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#define SAM_PID_AES (12) /* Advanced Encryption Standard */
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#define SAM_PID_AESB (13) /* AES bridge */
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#define SAM_PID_TDES (14) /* Triple Data Encryption Standard */
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#define SAM_PID_SHA (15) /* Secure Hash Algorithm */
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#define SAM_PID_MPDDRC (16) /* MPDDR controller */
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#define SAM_PID_MATRIX1 (17) /* H32MX, 32-bit AHB Matrix */
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#define SAM_PID_MATRIX0 (18) /* H64MX, 64-bit AHB Matrix */
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#define SAM_PID_VDEC (19) /* Video Decoder */
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#define SAM_PID_SBM (20) /* Secure Box Module */
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/* 21 Undefined */
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#define SAM_PID_HSMC (22) /* Multi-bit ECC Interrupt */
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#define SAM_PID_PIOA (23) /* Parallel I/O Controller A */
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#define SAM_PID_PIOB (24) /* Parallel I/O Controller B */
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#define SAM_PID_PIOC (25) /* Parallel I/O Controller C */
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#define SAM_PID_PIOE (26) /* Parallel I/O Controller E */
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#define SAM_PID_UART0 (27) /* UART 0 */
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#define SAM_PID_UART1 (28) /* UART 1 */
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#define SAM_PID_USART2 (29) /* USART 2 */
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#define SAM_PID_USART3 (30) /* USART 3 */
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#define SAM_PID_USART4 (31) /* USART 4 */
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#define SAM_PID_TWI0 (32) /* Two-Wire Interface 0 */
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#define SAM_PID_TWI1 (33) /* Two-Wire Interface 1 */
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#define SAM_PID_TWI2 (34) /* Two-Wire Interface 2 */
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#define SAM_PID_HSMCI0 (35) /* High Speed Multimedia Card Interface 0 */
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#define SAM_PID_HSMCI1 (36) /* High Speed Multimedia Card Interface 1 */
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#define SAM_PID_SPI0 (37) /* Serial Peripheral Interface 0 */
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#define SAM_PID_SPI1 (38) /* Serial Peripheral Interface 1 */
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#define SAM_PID_SPI2 (39) /* Serial Peripheral Interface 2 */
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#define SAM_PID_TC0 (40) /* Timer Counter 0 (ch. 0, 1, 2) */
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#define SAM_PID_TC1 (41) /* Timer Counter 1 (ch. 3, 4, 5) */
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#define SAM_PID_TC2 (42) /* Timer Counter 2 (ch. 6, 7, 8) */
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#define SAM_PID_PWM (43) /* Pulse Width Modulation Controller */
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#define SAM_PID_ADC (44) /* Touch Screen ADC Controller */
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#define SAM_PID_DBGU (45) /* Debug Unit Interrupt */
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#define SAM_PID_UHPHS (46) /* USB Host High Speed */
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#define SAM_PID_UDPHS (47) /* USB Device High Speed */
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#define SAM_PID_SSC0 (48) /* Synchronous Serial Controller 0 */
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#define SAM_PID_SSC1 (49) /* Synchronous Serial Controller 1 */
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#define SAM_PID_XDMAC1 (50) /* DMA Controller 1 */
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#define SAM_PID_LCDC (51) /* LCD Controller */
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#define SAM_PID_ISI (52) /* Image Sensor Interface */
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#define SAM_PID_TRNG (53) /* True Random Number Generator */
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#define SAM_PID_EMAC0 (54) /* Ethernet MAC 0 */
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#define SAM_PID_EMAC1 (55) /* Ethernet MAC 1 */
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#define SAM_PID_AICID (56) /* IRQ Interrupt ID */
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#define SAM_PID_SFC (57) /* Fuse Controller */
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/* 58 Reserved */
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#define SAM_PID_SECURAM (59) /* Secured RAM */
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/* 60 Undefined */
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#define SAM_PID_SMD (61) /* SMD Soft Modem */
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#define SAM_PID_TWI3 (62) /* Two-Wire Interface 3 */
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#define SAM_PID_CATB (63) /* Watchdog timer Interrupt */
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#define SAM_PID_SFR (64) /* Special Function Register */
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#define SAM_PID_AIC (65) /* Advanced Interrupt Controller */
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#define SAM_PID_SAIC (66) /* Secured Advanced Interrupt Controller */
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#define SAM_PID_L2CC (67) /* L2 Cache Controller */
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/* External interrupts vectors numbers (same as peripheral ID) */
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#define SAM_IRQ_FIQ SAM_PID_FIQ /* Advanced Interrupt Controller FIQ */
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#define SAM_IRQ_SYS SAM_PID_SYS /* System Controller Interrupt PMC */
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#define SAM_IRQ_ARM SAM_PID_ARM /* Performance Monitor Unit */
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#define SAM_IRQ_PIT SAM_PID_PIT /* Periodic Interval Timer Interrupt */
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#define SAM_IRQ_WDT SAM_PID_WDT /* Watchdog timer Interrupt */
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#define SAM_IRQ_PIOD SAM_PID_PIOD /* Parallel I/O Controller D */
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#define SAM_IRQ_USART0 SAM_PID_USART0 /* USART 0 */
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#define SAM_IRQ_USART1 SAM_PID_USART1 /* USART 1 */
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#define SAM_IRQ_XDMAC0 SAM_PID_XDMAC0 /* DMA Controller 0 */
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#define SAM_IRQ_ICM SAM_PID_ICM /* Integrity Check Monitor */
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#define SAM_IRQ_CPKCC SAM_PID_CPKCC /* Classic Public Key Crypto Controller */
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#define SAM_IRQ_AES SAM_PID_AES /* Advanced Encryption Standard */
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#define SAM_IRQ_AESB SAM_PID_AESB /* AES bridge */
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#define SAM_IRQ_TDES SAM_PID_TDES /* Triple Data Encryption Standard */
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#define SAM_IRQ_SHA SAM_PID_SHA /* Secure Hash Algorithm */
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#define SAM_IRQ_MPDDRC SAM_PID_MPDDRC /* MPDDR controller */
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#define SAM_IRQ_MATRIX1 SAM_PID_MATRIX1 /* H32MX, 32-bit AHB Matrix */
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#define SAM_IRQ_MATRIX0 SAM_PID_MATRIX0 /* H64MX, 64-bit AHB Matrix */
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#define SAM_IRQ_VDEC SAM_PID_VDEC /* Video Decoder */
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#define SAM_IRQ_SBM SAM_PID_SBM /* Secure Box Module */
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#define SAM_IRQ_HSMC SAM_PID_HSMC /* Multi-bit ECC Interrupt */
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#define SAM_IRQ_PIOA SAM_PID_PIOA /* Parallel I/O Controller A */
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#define SAM_IRQ_PIOB SAM_PID_PIOB /* Parallel I/O Controller B */
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#define SAM_IRQ_PIOC SAM_PID_PIOC /* Parallel I/O Controller C */
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#define SAM_IRQ_PIOE SAM_PID_PIOE /* Parallel I/O Controller E */
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#define SAM_IRQ_UART0 SAM_PID_UART0 /* UART 0 */
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#define SAM_IRQ_UART1 SAM_PID_UART1 /* UART 1 */
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#define SAM_IRQ_USART2 SAM_PID_USART2 /* USART 2 */
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#define SAM_IRQ_USART3 SAM_PID_USART3 /* USART 3 */
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#define SAM_IRQ_USART4 SAM_PID_USART4 /* USART 4 */
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#define SAM_IRQ_TWI0 SAM_PID_TWI0 /* Two-Wire Interface 0 */
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#define SAM_IRQ_TWI1 SAM_PID_TWI1 /* Two-Wire Interface 1 */
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#define SAM_IRQ_TWI2 SAM_PID_TWI2 /* Two-Wire Interface 2 */
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#define SAM_IRQ_HSMCI0 SAM_PID_HSMCI0 /* High Speed Multimedia Card Interface 0 */
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#define SAM_IRQ_HSMCI1 SAM_PID_HSMCI1 /* High Speed Multimedia Card Interface 1 */
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#define SAM_IRQ_SPI0 SAM_PID_SPI0 /* Serial Peripheral Interface 0 */
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#define SAM_IRQ_SPI1 SAM_PID_SPI1 /* Serial Peripheral Interface 1 */
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#define SAM_IRQ_SPI2 SAM_PID_SPI2 /* Serial Peripheral Interface 2 */
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#define SAM_IRQ_TC0 SAM_PID_TC0 /* Timer Counter 0 (ch. 0, 1, 2) */
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#define SAM_IRQ_TC1 SAM_PID_TC1 /* Timer Counter 1 (ch. 3, 4, 5) */
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#define SAM_IRQ_TC2 SAM_PID_TC2 /* Timer Counter 2 (ch. 6, 7, 8) */
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#define SAM_IRQ_PWM SAM_PID_PWM /* Pulse Width Modulation Controller */
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#define SAM_IRQ_ADC SAM_PID_ADC /* Touch Screen ADC Controller */
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#define SAM_IRQ_DBGU SAM_PID_DBGU /* Debug Unit Interrupt */
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#define SAM_IRQ_UHPHS SAM_PID_UHPHS /* USB Host High Speed */
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#define SAM_IRQ_UDPHS SAM_PID_UDPHS /* USB Device High Speed */
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#define SAM_IRQ_SSC0 SAM_PID_SSC0 /* Synchronous Serial Controller 0 */
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#define SAM_IRQ_SSC1 SAM_PID_SSC1 /* Synchronous Serial Controller 1 */
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#define SAM_IRQ_XDMAC1 SAM_PID_XDMAC1 /* DMA Controller 1 */
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#define SAM_IRQ_LCDC SAM_PID_LCDC /* LCD Controller */
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#define SAM_IRQ_ISI SAM_PID_ISI /* Image Sensor Interface */
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#define SAM_IRQ_TRNG SAM_PID_TRNG /* True Random Number Generator */
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#define SAM_IRQ_EMAC0 SAM_PID_EMAC0 /* Ethernet MAC 0 */
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#define SAM_IRQ_EMAC1 SAM_PID_EMAC1 /* Ethernet MAC 1 */
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#define SAM_IRQ_AICID SAM_PID_AICID /* IRQ Interrupt ID */
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#define SAM_IRQ_SFC SAM_PID_SFC /* Fuse Controller */
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#define SAM_IRQ_SECURAM SAM_PID_SECURAM /* Secured RAM */
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#define SAM_IRQ_SMD SAM_PID_SMD /* SMD Soft Modem */
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#define SAM_IRQ_TWI3 SAM_PID_TWI3 /* Two-Wire Interface 3 */
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#define SAM_IRQ_CATB SAM_PID_CATB /* Watchdog timer Interrupt */
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#define SAM_IRQ_SFR SAM_PID_SFR /* Special Function Register */
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#define SAM_IRQ_AIC SAM_PID_AIC /* Advanced Interrupt Controller */
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#define SAM_IRQ_SAIC SAM_PID_SAIC /* Secured Advanced Interrupt Controller */
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#define SAM_IRQ_L2CC SAM_PID_L2CC /* L2 Cache Controller */
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#define SAM_IRQ_NINT (SAM_PID_L2CC + 1)
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/* PIO interrupts (derived from SAM_IRQ_PIOA/B/C/D/E/F) */
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#ifdef CONFIG_SAMA5_PIOA_IRQ
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# define SAM_IRQ_PIOA_PINS (SAM_IRQ_NINT)
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# define SAM_IRQ_PA0 (SAM_IRQ_PIOA_PINS+0) /* PIOA, PIN 0 */
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# define SAM_IRQ_PA1 (SAM_IRQ_PIOA_PINS+1) /* PIOA, PIN 1 */
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# define SAM_IRQ_PA2 (SAM_IRQ_PIOA_PINS+2) /* PIOA, PIN 2 */
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# define SAM_IRQ_PA3 (SAM_IRQ_PIOA_PINS+3) /* PIOA, PIN 3 */
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# define SAM_IRQ_PA4 (SAM_IRQ_PIOA_PINS+4) /* PIOA, PIN 4 */
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# define SAM_IRQ_PA5 (SAM_IRQ_PIOA_PINS+5) /* PIOA, PIN 5 */
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# define SAM_IRQ_PA6 (SAM_IRQ_PIOA_PINS+6) /* PIOA, PIN 6 */
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# define SAM_IRQ_PA7 (SAM_IRQ_PIOA_PINS+7) /* PIOA, PIN 7 */
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# define SAM_IRQ_PA8 (SAM_IRQ_PIOA_PINS+8) /* PIOA, PIN 8 */
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# define SAM_IRQ_PA9 (SAM_IRQ_PIOA_PINS+9) /* PIOA, PIN 9 */
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# define SAM_IRQ_PA10 (SAM_IRQ_PIOA_PINS+10) /* PIOA, PIN 10 */
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# define SAM_IRQ_PA11 (SAM_IRQ_PIOA_PINS+11) /* PIOA, PIN 11 */
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# define SAM_IRQ_PA12 (SAM_IRQ_PIOA_PINS+12) /* PIOA, PIN 12 */
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# define SAM_IRQ_PA13 (SAM_IRQ_PIOA_PINS+13) /* PIOA, PIN 13 */
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# define SAM_IRQ_PA14 (SAM_IRQ_PIOA_PINS+14) /* PIOA, PIN 14 */
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# define SAM_IRQ_PA15 (SAM_IRQ_PIOA_PINS+15) /* PIOA, PIN 15 */
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# define SAM_IRQ_PA16 (SAM_IRQ_PIOA_PINS+16) /* PIOA, PIN 16 */
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# define SAM_IRQ_PA17 (SAM_IRQ_PIOA_PINS+17) /* PIOA, PIN 17 */
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# define SAM_IRQ_PA18 (SAM_IRQ_PIOA_PINS+18) /* PIOA, PIN 18 */
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# define SAM_IRQ_PA19 (SAM_IRQ_PIOA_PINS+19) /* PIOA, PIN 19 */
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# define SAM_IRQ_PA20 (SAM_IRQ_PIOA_PINS+20) /* PIOA, PIN 20 */
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# define SAM_IRQ_PA21 (SAM_IRQ_PIOA_PINS+21) /* PIOA, PIN 21 */
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# define SAM_IRQ_PA22 (SAM_IRQ_PIOA_PINS+22) /* PIOA, PIN 22 */
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# define SAM_IRQ_PA23 (SAM_IRQ_PIOA_PINS+23) /* PIOA, PIN 23 */
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# define SAM_IRQ_PA24 (SAM_IRQ_PIOA_PINS+24) /* PIOA, PIN 24 */
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# define SAM_IRQ_PA25 (SAM_IRQ_PIOA_PINS+25) /* PIOA, PIN 25 */
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# define SAM_IRQ_PA26 (SAM_IRQ_PIOA_PINS+26) /* PIOA, PIN 26 */
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# define SAM_IRQ_PA27 (SAM_IRQ_PIOA_PINS+27) /* PIOA, PIN 27 */
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# define SAM_IRQ_PA28 (SAM_IRQ_PIOA_PINS+28) /* PIOA, PIN 28 */
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# define SAM_IRQ_PA29 (SAM_IRQ_PIOA_PINS+29) /* PIOA, PIN 29 */
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# define SAM_IRQ_PA30 (SAM_IRQ_PIOA_PINS+30) /* PIOA, PIN 30 */
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# define SAM_IRQ_PA31 (SAM_IRQ_PIOA_PINS+31) /* PIOA, PIN 31 */
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# define SAM_NPIOAIRQS 32
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#else
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# define SAM_NPIOAIRQS 0
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#endif
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#ifdef CONFIG_SAMA5_PIOB_IRQ
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# define SAM_IRQ_PIOB_PINS (SAM_IRQ_NINT + SAM_NPIOAIRQS)
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# define SAM_IRQ_PB0 (SAM_IRQ_PIOB_PINS+0) /* PIOB, PIN 0 */
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# define SAM_IRQ_PB1 (SAM_IRQ_PIOB_PINS+1) /* PIOB, PIN 1 */
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# define SAM_IRQ_PB2 (SAM_IRQ_PIOB_PINS+2) /* PIOB, PIN 2 */
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# define SAM_IRQ_PB3 (SAM_IRQ_PIOB_PINS+3) /* PIOB, PIN 3 */
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# define SAM_IRQ_PB4 (SAM_IRQ_PIOB_PINS+4) /* PIOB, PIN 4 */
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# define SAM_IRQ_PB5 (SAM_IRQ_PIOB_PINS+5) /* PIOB, PIN 5 */
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# define SAM_IRQ_PB6 (SAM_IRQ_PIOB_PINS+6) /* PIOB, PIN 6 */
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# define SAM_IRQ_PB7 (SAM_IRQ_PIOB_PINS+7) /* PIOB, PIN 7 */
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# define SAM_IRQ_PB8 (SAM_IRQ_PIOB_PINS+8) /* PIOB, PIN 8 */
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# define SAM_IRQ_PB9 (SAM_IRQ_PIOB_PINS+9) /* PIOB, PIN 9 */
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# define SAM_IRQ_PB10 (SAM_IRQ_PIOB_PINS+10) /* PIOB, PIN 10 */
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# define SAM_IRQ_PB11 (SAM_IRQ_PIOB_PINS+11) /* PIOB, PIN 11 */
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# define SAM_IRQ_PB12 (SAM_IRQ_PIOB_PINS+12) /* PIOB, PIN 12 */
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# define SAM_IRQ_PB13 (SAM_IRQ_PIOB_PINS+13) /* PIOB, PIN 13 */
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# define SAM_IRQ_PB14 (SAM_IRQ_PIOB_PINS+14) /* PIOB, PIN 14 */
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# define SAM_IRQ_PB15 (SAM_IRQ_PIOB_PINS+15) /* PIOB, PIN 15 */
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# define SAM_IRQ_PB16 (SAM_IRQ_PIOB_PINS+16) /* PIOB, PIN 16 */
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# define SAM_IRQ_PB17 (SAM_IRQ_PIOB_PINS+17) /* PIOB, PIN 17 */
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# define SAM_IRQ_PB18 (SAM_IRQ_PIOB_PINS+18) /* PIOB, PIN 18 */
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# define SAM_IRQ_PB19 (SAM_IRQ_PIOB_PINS+19) /* PIOB, PIN 19 */
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# define SAM_IRQ_PB20 (SAM_IRQ_PIOB_PINS+20) /* PIOB, PIN 20 */
|
||||
# define SAM_IRQ_PB21 (SAM_IRQ_PIOB_PINS+21) /* PIOB, PIN 21 */
|
||||
# define SAM_IRQ_PB22 (SAM_IRQ_PIOB_PINS+22) /* PIOB, PIN 22 */
|
||||
# define SAM_IRQ_PB23 (SAM_IRQ_PIOB_PINS+23) /* PIOB, PIN 23 */
|
||||
# define SAM_IRQ_PB24 (SAM_IRQ_PIOB_PINS+24) /* PIOB, PIN 24 */
|
||||
# define SAM_IRQ_PB25 (SAM_IRQ_PIOB_PINS+25) /* PIOB, PIN 25 */
|
||||
# define SAM_IRQ_PB26 (SAM_IRQ_PIOB_PINS+26) /* PIOB, PIN 26 */
|
||||
# define SAM_IRQ_PB27 (SAM_IRQ_PIOB_PINS+27) /* PIOB, PIN 27 */
|
||||
# define SAM_IRQ_PB28 (SAM_IRQ_PIOB_PINS+28) /* PIOB, PIN 28 */
|
||||
# define SAM_IRQ_PB29 (SAM_IRQ_PIOB_PINS+29) /* PIOB, PIN 29 */
|
||||
# define SAM_IRQ_PB30 (SAM_IRQ_PIOB_PINS+30) /* PIOB, PIN 30 */
|
||||
# define SAM_IRQ_PB31 (SAM_IRQ_PIOB_PINS+31) /* PIOB, PIN 31 */
|
||||
# define SAM_NPIOBIRQS 32
|
||||
#else
|
||||
# define SAM_NPIOBIRQS 0
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_SAMA5_PIOC_IRQ
|
||||
# define SAM_IRQ_PIOC_PINS (SAM_IRQ_NINT + SAM_NPIOAIRQS + SAM_NPIOBIRQS)
|
||||
# define SAM_IRQ_PC0 (SAM_IRQ_PIOC_PINS+0) /* PIOC, PIN 0 */
|
||||
# define SAM_IRQ_PC1 (SAM_IRQ_PIOC_PINS+1) /* PIOC, PIN 1 */
|
||||
# define SAM_IRQ_PC2 (SAM_IRQ_PIOC_PINS+2) /* PIOC, PIN 2 */
|
||||
# define SAM_IRQ_PC3 (SAM_IRQ_PIOC_PINS+3) /* PIOC, PIN 3 */
|
||||
# define SAM_IRQ_PC4 (SAM_IRQ_PIOC_PINS+4) /* PIOC, PIN 4 */
|
||||
# define SAM_IRQ_PC5 (SAM_IRQ_PIOC_PINS+5) /* PIOC, PIN 5 */
|
||||
# define SAM_IRQ_PC6 (SAM_IRQ_PIOC_PINS+6) /* PIOC, PIN 6 */
|
||||
# define SAM_IRQ_PC7 (SAM_IRQ_PIOC_PINS+7) /* PIOC, PIN 7 */
|
||||
# define SAM_IRQ_PC8 (SAM_IRQ_PIOC_PINS+8) /* PIOC, PIN 8 */
|
||||
# define SAM_IRQ_PC9 (SAM_IRQ_PIOC_PINS+9) /* PIOC, PIN 9 */
|
||||
# define SAM_IRQ_PC10 (SAM_IRQ_PIOC_PINS+10) /* PIOC, PIN 10 */
|
||||
# define SAM_IRQ_PC11 (SAM_IRQ_PIOC_PINS+11) /* PIOC, PIN 11 */
|
||||
# define SAM_IRQ_PC12 (SAM_IRQ_PIOC_PINS+12) /* PIOC, PIN 12 */
|
||||
# define SAM_IRQ_PC13 (SAM_IRQ_PIOC_PINS+13) /* PIOC, PIN 13 */
|
||||
# define SAM_IRQ_PC14 (SAM_IRQ_PIOC_PINS+14) /* PIOC, PIN 14 */
|
||||
# define SAM_IRQ_PC15 (SAM_IRQ_PIOC_PINS+15) /* PIOC, PIN 15 */
|
||||
# define SAM_IRQ_PC16 (SAM_IRQ_PIOC_PINS+16) /* PIOC, PIN 16 */
|
||||
# define SAM_IRQ_PC17 (SAM_IRQ_PIOC_PINS+17) /* PIOC, PIN 17 */
|
||||
# define SAM_IRQ_PC18 (SAM_IRQ_PIOC_PINS+18) /* PIOC, PIN 18 */
|
||||
# define SAM_IRQ_PC19 (SAM_IRQ_PIOC_PINS+19) /* PIOC, PIN 19 */
|
||||
# define SAM_IRQ_PC20 (SAM_IRQ_PIOC_PINS+20) /* PIOC, PIN 20 */
|
||||
# define SAM_IRQ_PC21 (SAM_IRQ_PIOC_PINS+21) /* PIOC, PIN 21 */
|
||||
# define SAM_IRQ_PC22 (SAM_IRQ_PIOC_PINS+22) /* PIOC, PIN 22 */
|
||||
# define SAM_IRQ_PC23 (SAM_IRQ_PIOC_PINS+23) /* PIOC, PIN 23 */
|
||||
# define SAM_IRQ_PC24 (SAM_IRQ_PIOC_PINS+24) /* PIOC, PIN 24 */
|
||||
# define SAM_IRQ_PC25 (SAM_IRQ_PIOC_PINS+25) /* PIOC, PIN 25 */
|
||||
# define SAM_IRQ_PC26 (SAM_IRQ_PIOC_PINS+26) /* PIOC, PIN 26 */
|
||||
# define SAM_IRQ_PC27 (SAM_IRQ_PIOC_PINS+27) /* PIOC, PIN 27 */
|
||||
# define SAM_IRQ_PC28 (SAM_IRQ_PIOC_PINS+28) /* PIOC, PIN 28 */
|
||||
# define SAM_IRQ_PC29 (SAM_IRQ_PIOC_PINS+29) /* PIOC, PIN 29 */
|
||||
# define SAM_IRQ_PC30 (SAM_IRQ_PIOC_PINS+30) /* PIOC, PIN 30 */
|
||||
# define SAM_IRQ_PC31 (SAM_IRQ_PIOC_PINS+31) /* PIOC, PIN 31 */
|
||||
# define SAM_NPIOCIRQS 32
|
||||
#else
|
||||
# define SAM_NPIOCIRQS 0
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_SAMA5_PIOD_IRQ
|
||||
# define SAM_IRQ_PIOD_PINS (SAM_IRQ_NINT + SAM_NPIOAIRQS + SAM_NPIOBIRQS + \
|
||||
SAM_NPIOCIRQS)
|
||||
# define SAM_IRQ_PD0 (SAM_IRQ_PIOD_PINS+0) /* PIOD, PIN 0 */
|
||||
# define SAM_IRQ_PD1 (SAM_IRQ_PIOD_PINS+1) /* PIOD, PIN 1 */
|
||||
# define SAM_IRQ_PD2 (SAM_IRQ_PIOD_PINS+2) /* PIOD, PIN 2 */
|
||||
# define SAM_IRQ_PD3 (SAM_IRQ_PIOD_PINS+3) /* PIOD, PIN 3 */
|
||||
# define SAM_IRQ_PD4 (SAM_IRQ_PIOD_PINS+4) /* PIOD, PIN 4 */
|
||||
# define SAM_IRQ_PD5 (SAM_IRQ_PIOD_PINS+5) /* PIOD, PIN 5 */
|
||||
# define SAM_IRQ_PD6 (SAM_IRQ_PIOD_PINS+6) /* PIOD, PIN 6 */
|
||||
# define SAM_IRQ_PD7 (SAM_IRQ_PIOD_PINS+7) /* PIOD, PIN 7 */
|
||||
# define SAM_IRQ_PD8 (SAM_IRQ_PIOD_PINS+8) /* PIOD, PIN 8 */
|
||||
# define SAM_IRQ_PD9 (SAM_IRQ_PIOD_PINS+9) /* PIOD, PIN 9 */
|
||||
# define SAM_IRQ_PD10 (SAM_IRQ_PIOD_PINS+10) /* PIOD, PIN 10 */
|
||||
# define SAM_IRQ_PD11 (SAM_IRQ_PIOD_PINS+11) /* PIOD, PIN 11 */
|
||||
# define SAM_IRQ_PD12 (SAM_IRQ_PIOD_PINS+12) /* PIOD, PIN 12 */
|
||||
# define SAM_IRQ_PD13 (SAM_IRQ_PIOD_PINS+13) /* PIOD, PIN 13 */
|
||||
# define SAM_IRQ_PD14 (SAM_IRQ_PIOD_PINS+14) /* PIOD, PIN 14 */
|
||||
# define SAM_IRQ_PD15 (SAM_IRQ_PIOD_PINS+15) /* PIOD, PIN 15 */
|
||||
# define SAM_IRQ_PD16 (SAM_IRQ_PIOD_PINS+16) /* PIOD, PIN 16 */
|
||||
# define SAM_IRQ_PD17 (SAM_IRQ_PIOD_PINS+17) /* PIOD, PIN 17 */
|
||||
# define SAM_IRQ_PD18 (SAM_IRQ_PIOD_PINS+18) /* PIOD, PIN 18 */
|
||||
# define SAM_IRQ_PD19 (SAM_IRQ_PIOD_PINS+19) /* PIOD, PIN 19 */
|
||||
# define SAM_IRQ_PD20 (SAM_IRQ_PIOD_PINS+20) /* PIOD, PIN 20 */
|
||||
# define SAM_IRQ_PD21 (SAM_IRQ_PIOD_PINS+21) /* PIOD, PIN 21 */
|
||||
# define SAM_IRQ_PD22 (SAM_IRQ_PIOD_PINS+22) /* PIOD, PIN 22 */
|
||||
# define SAM_IRQ_PD23 (SAM_IRQ_PIOD_PINS+23) /* PIOD, PIN 23 */
|
||||
# define SAM_IRQ_PD24 (SAM_IRQ_PIOD_PINS+24) /* PIOD, PIN 24 */
|
||||
# define SAM_IRQ_PD25 (SAM_IRQ_PIOD_PINS+25) /* PIOD, PIN 25 */
|
||||
# define SAM_IRQ_PD26 (SAM_IRQ_PIOD_PINS+26) /* PIOD, PIN 26 */
|
||||
# define SAM_IRQ_PD27 (SAM_IRQ_PIOD_PINS+27) /* PIOD, PIN 27 */
|
||||
# define SAM_IRQ_PD28 (SAM_IRQ_PIOD_PINS+28) /* PIOD, PIN 28 */
|
||||
# define SAM_IRQ_PD29 (SAM_IRQ_PIOD_PINS+29) /* PIOD, PIN 29 */
|
||||
# define SAM_IRQ_PD30 (SAM_IRQ_PIOD_PINS+30) /* PIOD, PIN 30 */
|
||||
# define SAM_IRQ_PD31 (SAM_IRQ_PIOD_PINS+31) /* PIOD, PIN 31 */
|
||||
# define SAM_NPIODIRQS 32
|
||||
#else
|
||||
# define SAM_NPIODIRQS 0
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_SAMA5_PIOE_IRQ
|
||||
# define SAM_IRQ_PIOE_PINS (SAM_IRQ_NINT + SAM_NPIOAIRQS + \
|
||||
SAM_NPIOBIRQS + SAM_NPIOCIRQS + SAM_NPIODIRQS)
|
||||
# define SAM_IRQ_PE0 (SAM_IRQ_PIOE_PINS+0) /* PIOE, PIN 0 */
|
||||
# define SAM_IRQ_PE1 (SAM_IRQ_PIOE_PINS+1) /* PIOE, PIN 1 */
|
||||
# define SAM_IRQ_PE2 (SAM_IRQ_PIOE_PINS+2) /* PIOE, PIN 2 */
|
||||
# define SAM_IRQ_PE3 (SAM_IRQ_PIOE_PINS+3) /* PIOE, PIN 3 */
|
||||
# define SAM_IRQ_PE4 (SAM_IRQ_PIOE_PINS+4) /* PIOE, PIN 4 */
|
||||
# define SAM_IRQ_PE5 (SAM_IRQ_PIOE_PINS+5) /* PIOE, PIN 5 */
|
||||
# define SAM_IRQ_PE6 (SAM_IRQ_PIOE_PINS+6) /* PIOE, PIN 6 */
|
||||
# define SAM_IRQ_PE7 (SAM_IRQ_PIOE_PINS+7) /* PIOE, PIN 7 */
|
||||
# define SAM_IRQ_PE8 (SAM_IRQ_PIOE_PINS+8) /* PIOE, PIN 8 */
|
||||
# define SAM_IRQ_PE9 (SAM_IRQ_PIOE_PINS+9) /* PIOE, PIN 9 */
|
||||
# define SAM_IRQ_PE10 (SAM_IRQ_PIOE_PINS+10) /* PIOE, PIN 10 */
|
||||
# define SAM_IRQ_PE11 (SAM_IRQ_PIOE_PINS+11) /* PIOE, PIN 11 */
|
||||
# define SAM_IRQ_PE12 (SAM_IRQ_PIOE_PINS+12) /* PIOE, PIN 12 */
|
||||
# define SAM_IRQ_PE13 (SAM_IRQ_PIOE_PINS+13) /* PIOE, PIN 13 */
|
||||
# define SAM_IRQ_PE14 (SAM_IRQ_PIOE_PINS+14) /* PIOE, PIN 14 */
|
||||
# define SAM_IRQ_PE15 (SAM_IRQ_PIOE_PINS+15) /* PIOE, PIN 15 */
|
||||
# define SAM_IRQ_PE16 (SAM_IRQ_PIOE_PINS+16) /* PIOE, PIN 16 */
|
||||
# define SAM_IRQ_PE17 (SAM_IRQ_PIOE_PINS+17) /* PIOE, PIN 17 */
|
||||
# define SAM_IRQ_PE18 (SAM_IRQ_PIOE_PINS+18) /* PIOE, PIN 18 */
|
||||
# define SAM_IRQ_PE19 (SAM_IRQ_PIOE_PINS+19) /* PIOE, PIN 19 */
|
||||
# define SAM_IRQ_PE20 (SAM_IRQ_PIOE_PINS+20) /* PIOE, PIN 20 */
|
||||
# define SAM_IRQ_PE21 (SAM_IRQ_PIOE_PINS+21) /* PIOE, PIN 21 */
|
||||
# define SAM_IRQ_PE22 (SAM_IRQ_PIOE_PINS+22) /* PIOE, PIN 22 */
|
||||
# define SAM_IRQ_PE23 (SAM_IRQ_PIOE_PINS+23) /* PIOE, PIN 23 */
|
||||
# define SAM_IRQ_PE24 (SAM_IRQ_PIOE_PINS+24) /* PIOE, PIN 24 */
|
||||
# define SAM_IRQ_PE25 (SAM_IRQ_PIOE_PINS+25) /* PIOE, PIN 25 */
|
||||
# define SAM_IRQ_PE26 (SAM_IRQ_PIOE_PINS+26) /* PIOE, PIN 26 */
|
||||
# define SAM_IRQ_PE27 (SAM_IRQ_PIOE_PINS+27) /* PIOE, PIN 27 */
|
||||
# define SAM_IRQ_PE28 (SAM_IRQ_PIOE_PINS+28) /* PIOE, PIN 28 */
|
||||
# define SAM_IRQ_PE29 (SAM_IRQ_PIOE_PINS+29) /* PIOE, PIN 29 */
|
||||
# define SAM_IRQ_PE30 (SAM_IRQ_PIOE_PINS+30) /* PIOE, PIN 30 */
|
||||
# define SAM_IRQ_PE31 (SAM_IRQ_PIOE_PINS+31) /* PIOE, PIN 31 */
|
||||
# define SAM_NPIOEIRQS 32
|
||||
#else
|
||||
# define SAM_NPIOEIRQS 0
|
||||
#endif
|
||||
|
||||
/* Total number of IRQ numbers */
|
||||
|
||||
#define NR_IRQS (SAM_IRQ_NINT + \
|
||||
SAM_NPIOAIRQS + SAM_NPIOBIRQS + SAM_NPIOCIRQS + \
|
||||
SAM_NPIODIRQS + SAM_NPIOEIRQS )
|
||||
|
||||
/****************************************************************************************
|
||||
* Public Types
|
||||
****************************************************************************************/
|
||||
|
||||
/****************************************************************************************
|
||||
* Inline functions
|
||||
****************************************************************************************/
|
||||
|
||||
/****************************************************************************************
|
||||
* Public Variables
|
||||
****************************************************************************************/
|
||||
|
||||
/****************************************************************************************
|
||||
* Public Function Prototypes
|
||||
****************************************************************************************/
|
||||
|
||||
#ifndef __ASSEMBLY__
|
||||
#ifdef __cplusplus
|
||||
#define EXTERN extern "C"
|
||||
extern "C" {
|
||||
#else
|
||||
#define EXTERN extern
|
||||
#endif
|
||||
|
||||
#undef EXTERN
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
#endif
|
||||
|
||||
#endif /* __ARCH_ARM_INCLUDE_SAMA5_SAMA5D4X_IRQ_H */
|
||||
@ -157,7 +157,7 @@
|
||||
# define SAM_RSTC_OFFSET 0x00068600 /* 0x00068600-0x0006860f: RSTC */
|
||||
# define SAM_SHDC_OFFSET 0x00068610 /* 0x00068610-0x0006862f: SHDC */
|
||||
# define SAM_PITC_OFFSET 0x00068630 /* 0x00068630-0x0006863f: PITC */
|
||||
# define SAM_WDTC_OFFSET 0x00068640 /* 0x00068640-0x0006864f: WDTC */
|
||||
# define SAM_WDT_OFFSET 0x00068640 /* 0x00068640-0x0006864f: WDTC */
|
||||
# define SAM_SCKCR_OFFSET 0x00068650 /* 0x00068650-0x000686af: SCKCR */
|
||||
# define SAM_RTCC_OFFSET 0x000686b0 /* 0x000686b0-0x000688cf: RTCC */
|
||||
# define SAM_DBGU_OFFSET 0x00069000 /* 0x00069000-0x0006bfff: DBGU */
|
||||
@ -246,8 +246,8 @@
|
||||
#define SAM_NFCCR_NSECTIONS _NSECTIONS(SAM_NFCCR_SIZE)
|
||||
|
||||
#define SAM_PERIPHA_NSECTIONS _NSECTIONS(SAM_PERIPHA_SIZE)
|
||||
#define SAM_PERIPHB_NSECTIONS _NSECTIONS(SAM_PERIPHB_NSECTIONS)
|
||||
#define SAM_PERIPHC_NSECTIONS _NSECTIONS(SAM_PERIPHC_NSECTIONS)
|
||||
#define SAM_PERIPHB_NSECTIONS _NSECTIONS(SAM_PERIPHB_SIZE)
|
||||
#define SAM_PERIPHC_NSECTIONS _NSECTIONS(SAM_PERIPHC_SIZE)
|
||||
|
||||
/* Section MMU Flags */
|
||||
|
||||
@ -344,31 +344,31 @@
|
||||
* the high vectors must reside.
|
||||
*/
|
||||
|
||||
#define SAM_INTMEM_VSECTION 0x00000000 /* 0x00000000-0x0fffffff: Internal Memories */
|
||||
# define SAM_BOOTMEM_VSECTION 0x00000000 /* 0x00000000-0x000fffff: Boot memory */
|
||||
# define SAM_ROM_VSECTION 0x00000000 /* 0x00000000-0x000fffff: ROM */
|
||||
# define SAM_NFCSRAM_VSECTION 0x00100000 /* 0x00100000-0x001fffff: NFC SRAM */
|
||||
# define SAM_ISRAM_VSECTION 0x00200000 /* 0x00200000-0x0020ffff: SRAM */
|
||||
# define SAM_ISRAM0_PADDR 0x00200000 /* 0x00200000-0x0020ffff: SRAM0 */
|
||||
# define SAM_ISRAM1_PADDR 0x00210000 /* 0x00210000-0x002fffff: SRAM1 */
|
||||
# define SAM_VDEC_VSECTION 0x00300000 /* 0x00300000-0x0030ffff: VDEC */
|
||||
# define SAM_UDPHSRAM_VSECTION 0x00400000 /* 0x00400000-0x004fffff: UDPH SRAM */
|
||||
# define SAM_UHPOHCI_VSECTION 0x00500000 /* 0x00500000-0x005fffff: UHP OHCI */
|
||||
# define SAM_UHPEHCI_VSECTION 0x00600000 /* 0x00600000-0x006fffff: UHP EHCI */
|
||||
# define SAM_AXIMX_VSECTION 0x00700000 /* 0x00700000-0x007fffff: AXI Matr */
|
||||
# define SAM_DAP_VSECTION 0x00800000 /* 0x00800000-0x008fffff: DAP */
|
||||
# define SAM_SMD_VSECTION 0x00900000 /* 0x00900000-0x009fffff: SMD */
|
||||
# define SAM_L2CC_VSECTION 0x00a00000 /* 0x00a00000-0x00afffff: L2CC */
|
||||
|
||||
#define SAM_EBICS0_VSECTION 0x10000000 /* 0x10000000-0x1fffffff: EBI Chip select 0 */
|
||||
#define SAM_DDRCS_VSECTION 0x20000000 /* 0x20000000-0x3fffffff: EBI DDRCS */
|
||||
#define SAM_EBICS1_VSECTION 0x60000000 /* 0x60000000-0x6fffffff: EBI Chip select 1 */
|
||||
#define SAM_EBICS2_VSECTION 0x70000000 /* 0x70000000-0x7fffffff: EBI Chip select 2 */
|
||||
#define SAM_EBICS3_VSECTION 0x80000000 /* 0x80000000-0x8fffffff: EBI Chip select 2 */
|
||||
#define SAM_NFCCR_VSECTION 0x90000000 /* 0x90000000-0x9fffffff: NFC Command Registers */
|
||||
#define SAM_PERIPHA_VSECTION 0xf0000000 /* 0xf0000000-0xf0023fff: Internal Peripherals A */
|
||||
#define SAM_PERIPHB_VSECTION 0xf8000000 /* 0xf8000000-0xf803c3ff: Internal Peripherals B */
|
||||
#define SAM_PERIPHC_VSECTION 0xfc000000 /* 0xfc000000-0xfc06efff: Internal Peripherals C */
|
||||
# define SAM_INTMEM_VSECTION 0x00000000 /* 0x00000000-0x0fffffff: Internal Memories */
|
||||
# define SAM_BOOTMEM_VSECTION 0x00000000 /* 0x00000000-0x000fffff: Boot memory */
|
||||
# define SAM_ROM_VSECTION 0x00000000 /* 0x00000000-0x000fffff: ROM */
|
||||
# define SAM_NFCSRAM_VSECTION 0x00100000 /* 0x00100000-0x001fffff: NFC SRAM */
|
||||
# define SAM_ISRAM_VSECTION 0x00200000 /* 0x00200000-0x0020ffff: SRAM */
|
||||
# define SAM_ISRAM0_VADDR 0x00200000 /* 0x00200000-0x0020ffff: SRAM0 */
|
||||
# define SAM_ISRAM1_VADDR 0x00210000 /* 0x00210000-0x002fffff: SRAM1 */
|
||||
# define SAM_VDEC_VSECTION 0x00300000 /* 0x00300000-0x0030ffff: VDEC */
|
||||
# define SAM_UDPHSRAM_VSECTION 0x00400000 /* 0x00400000-0x004fffff: UDPH SRAM */
|
||||
# define SAM_UHPOHCI_VSECTION 0x00500000 /* 0x00500000-0x005fffff: UHP OHCI */
|
||||
# define SAM_UHPEHCI_VSECTION 0x00600000 /* 0x00600000-0x006fffff: UHP EHCI */
|
||||
# define SAM_AXIMX_VSECTION 0x00700000 /* 0x00700000-0x007fffff: AXI Matr */
|
||||
# define SAM_DAP_VSECTION 0x00800000 /* 0x00800000-0x008fffff: DAP */
|
||||
# define SAM_SMD_VSECTION 0x00900000 /* 0x00900000-0x009fffff: SMD */
|
||||
# define SAM_L2CC_VSECTION 0x00a00000 /* 0x00a00000-0x00afffff: L2CC */
|
||||
# define SAM_EBICS0_VSECTION 0x10000000 /* 0x10000000-0x1fffffff: EBI Chip select 0 */
|
||||
# define SAM_DDRCS_VSECTION 0x20000000 /* 0x20000000-0x3fffffff: EBI DDRCS */
|
||||
# define SAM_EBICS1_VSECTION 0x60000000 /* 0x60000000-0x6fffffff: EBI Chip select 1 */
|
||||
# define SAM_EBICS2_VSECTION 0x70000000 /* 0x70000000-0x7fffffff: EBI Chip select 2 */
|
||||
# define SAM_EBICS3_VSECTION 0x80000000 /* 0x80000000-0x8fffffff: EBI Chip select 2 */
|
||||
# define SAM_NFCCR_VSECTION 0x90000000 /* 0x90000000-0x9fffffff: NFC Command Registers */
|
||||
# define SAM_PERIPHA_VSECTION 0xf0000000 /* 0xf0000000-0xf0023fff: Internal Peripherals A */
|
||||
# define SAM_PERIPHB_VSECTION 0xf8000000 /* 0xf8000000-0xf803c3ff: Internal Peripherals B */
|
||||
# define SAM_PERIPHC_VSECTION 0xfc000000 /* 0xfc000000-0xfc06efff: Internal Peripherals C */
|
||||
#endif /* !CONFIG_ARCH_ROMPGTABLE */
|
||||
|
||||
/* Peripheral virtual base addresses */
|
||||
|
||||
@ -425,7 +425,7 @@
|
||||
#define SAM_RSTC_VBASE (SAM_PERIPHC_VSECTION+SAM_RSTC_OFFSET)
|
||||
#define SAM_SHDC_VBASE (SAM_PERIPHC_VSECTION+SAM_SHDC_OFFSET)
|
||||
#define SAM_PITC_VBASE (SAM_PERIPHC_VSECTION+SAM_PITC_OFFSET)
|
||||
#define SAM_WDTC_VBASE (SAM_PERIPHC_VSECTION+SAM_WDTC_OFFSET)
|
||||
#define SAM_WDT_VBASE (SAM_PERIPHC_VSECTION+SAM_WDT_OFFSET)
|
||||
#define SAM_SCKCR_VBASE (SAM_PERIPHC_VSECTION+SAM_SCKCR_OFFSET)
|
||||
#define SAM_RTCC_VBASE (SAM_PERIPHC_VSECTION+SAM_RTCC_OFFSET)
|
||||
#define SAM_DBGU_VBASE (SAM_PERIPHC_VSECTION+SAM_DBGU_OFFSET)
|
||||
@ -712,7 +712,7 @@
|
||||
|
||||
# define PGTABLE_L2_OFFSET 0x000002000
|
||||
# define PGTABLE_L2_SIZE 0x000001c00
|
||||
#endif
|
||||
#endif /* CONFIG_ARCH_LOWVECTORS */
|
||||
|
||||
/* Paging L2 page table base addresses
|
||||
*
|
||||
@ -754,7 +754,7 @@
|
||||
# endif
|
||||
# define SAM_VECTOR_VADDR 0xffff0000
|
||||
|
||||
#endif
|
||||
#endif /* CONFIG_ARCH_LOWVECTORS */
|
||||
|
||||
/************************************************************************************
|
||||
* Public Types
|
||||
|
||||
@ -120,10 +120,10 @@
|
||||
#define PIO_EBI_A15 (PIO_PERIPHA | PIO_CFG_DEFAULT | PIO_PORT_PIOE | PIO_PIN15)
|
||||
#define PIO_EBI_A16 (PIO_PERIPHA | PIO_CFG_DEFAULT | PIO_PORT_PIOE | PIO_PIN16)
|
||||
#define PIO_EBI_A17 (PIO_PERIPHA | PIO_CFG_DEFAULT | PIO_PORT_PIOE | PIO_PIN17)
|
||||
#define PIO_EBI_A18 (PIO_PERIPHA | PIO_CFG_DEFAULT | PIO_PORT_PIOE | PIO_PIN18)
|
||||
#define PIO_EBI_A18 (PIO_PERIPHC | PIO_CFG_DEFAULT | PIO_PORT_PIOE | PIO_PIN26)
|
||||
#define PIO_EBI_A19 (PIO_PERIPHA | PIO_CFG_DEFAULT | PIO_PORT_PIOE | PIO_PIN19)
|
||||
#define PIO_EBI_A19 (PIO_PERIPHC | PIO_CFG_DEFAULT | PIO_PORT_PIOE | PIO_PIN28)
|
||||
#define PIO_EBI_A18_1 (PIO_PERIPHA | PIO_CFG_DEFAULT | PIO_PORT_PIOE | PIO_PIN18)
|
||||
#define PIO_EBI_A18_2 (PIO_PERIPHC | PIO_CFG_DEFAULT | PIO_PORT_PIOE | PIO_PIN26)
|
||||
#define PIO_EBI_A19_1 (PIO_PERIPHA | PIO_CFG_DEFAULT | PIO_PORT_PIOE | PIO_PIN19)
|
||||
#define PIO_EBI_A19_2 (PIO_PERIPHC | PIO_CFG_DEFAULT | PIO_PORT_PIOE | PIO_PIN28)
|
||||
#define PIO_EBI_A20 (PIO_PERIPHA | PIO_CFG_DEFAULT | PIO_PORT_PIOE | PIO_PIN20)
|
||||
#define PIO_EBI_A21 (PIO_PERIPHA | PIO_CFG_DEFAULT | PIO_PORT_PIOC | PIO_PIN17)
|
||||
#define PIO_EBI_A22 (PIO_PERIPHA | PIO_CFG_DEFAULT | PIO_PORT_PIOC | PIO_PIN18)
|
||||
|
||||
@ -264,17 +264,33 @@ static const struct section_mapping_s section_mapping[] =
|
||||
},
|
||||
#endif
|
||||
|
||||
/* SAMA5 Internal Peripherals */
|
||||
/* SAMA5 Internal Peripherals
|
||||
*
|
||||
* Naming of peripheral sections differs between the SAMA5D3 and SAMA5D4.
|
||||
* There is nothing called SYSC in the SAMA5D4 memory map. The third
|
||||
* peripheral section is un-named in the SAMA5D4 memory map, but I have
|
||||
* chosen the name PERIPHC for this usage.
|
||||
*/
|
||||
|
||||
{ SAM_PERIPHA_PSECTION, SAM_PERIPHA_VSECTION,
|
||||
SAM_PERIPHA_MMUFLAGS, SAM_PERIPHA_NSECTIONS
|
||||
},
|
||||
|
||||
{ SAM_PERIPHB_PSECTION, SAM_PERIPHB_VSECTION,
|
||||
SAM_PERIPHB_MMUFLAGS, SAM_PERIPHB_NSECTIONS
|
||||
},
|
||||
|
||||
#ifdef SAM_PERIPHC_PSECTION
|
||||
{ SAM_PERIPHC_PSECTION, SAM_PERIPHC_VSECTION,
|
||||
SAM_PERIPHC_MMUFLAGS, SAM_PERIPHC_NSECTIONS
|
||||
},
|
||||
#endif
|
||||
|
||||
#ifdef SAM_SYSC_PSECTION
|
||||
{ SAM_SYSC_PSECTION, SAM_SYSC_VSECTION,
|
||||
SAM_SYSC_MMUFLAGS, SAM_SYSC_NSECTIONS
|
||||
},
|
||||
#endif
|
||||
|
||||
/* LCDC Framebuffer. This entry reprograms a part of one of the above
|
||||
* regions, making it non-cacheable and non-buffereable.
|
||||
|
||||
@ -1625,7 +1625,7 @@ static int sam_ifup(struct uip_driver_s *dev)
|
||||
/* Enable the EMAC interrupt */
|
||||
|
||||
priv->ifup = true;
|
||||
up_enable_irq(SAM_IRQ_EMAC);
|
||||
up_enable_irq(SAM_IRQ_EMAC0);
|
||||
return OK;
|
||||
}
|
||||
|
||||
@ -1655,7 +1655,7 @@ static int sam_ifdown(struct uip_driver_s *dev)
|
||||
/* Disable the EMAC interrupt */
|
||||
|
||||
flags = irqsave();
|
||||
up_disable_irq(SAM_IRQ_EMAC);
|
||||
up_disable_irq(SAM_IRQ_EMAC0);
|
||||
|
||||
/* Cancel the TX poll timer and TX timeout timers */
|
||||
|
||||
@ -2718,7 +2718,7 @@ static void sam_emac_reset(struct sam_emac_s *priv)
|
||||
|
||||
/* Disable clocking to the EMAC peripheral */
|
||||
|
||||
sam_emac_disableclk();
|
||||
sam_emac0_disableclk();
|
||||
}
|
||||
|
||||
/****************************************************************************
|
||||
@ -2785,7 +2785,7 @@ static int sam_emac_configure(struct sam_emac_s *priv)
|
||||
|
||||
/* Enable clocking to the EMAC peripheral */
|
||||
|
||||
sam_emac_enableclk();
|
||||
sam_emac0_enableclk();
|
||||
|
||||
/* Disable TX, RX, interrupts, etc. */
|
||||
|
||||
@ -2925,16 +2925,16 @@ int sam_emac_initialize(void)
|
||||
* the interface is in the 'up' state.
|
||||
*/
|
||||
|
||||
ret = irq_attach(SAM_IRQ_EMAC, sam_emac_interrupt);
|
||||
ret = irq_attach(SAM_IRQ_EMAC0, sam_emac_interrupt);
|
||||
if (ret < 0)
|
||||
{
|
||||
nlldbg("ERROR: Failed to attach the handler to the IRQ%d\n", SAM_IRQ_EMAC);
|
||||
nlldbg("ERROR: Failed to attach the handler to the IRQ%d\n", SAM_IRQ_EMAC0);
|
||||
goto errout_with_buffers;
|
||||
}
|
||||
|
||||
/* Enable clocking to the EMAC peripheral (just for sam_ifdown()) */
|
||||
|
||||
sam_emac_enableclk();
|
||||
sam_emac0_enableclk();
|
||||
|
||||
/* Put the interface in the down state (disabling clocking again). */
|
||||
|
||||
|
||||
@ -114,6 +114,38 @@ static inline uintptr_t periphb_physregaddr(uintptr_t virtregaddr)
|
||||
#endif
|
||||
}
|
||||
|
||||
/****************************************************************************
|
||||
* Name: periphc_physregaddr
|
||||
*
|
||||
* Description:
|
||||
* Given the virtual address of a peripheral C register, return the
|
||||
* physical address of the register
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
#ifdef SAM_PERIPHC_VSECTION
|
||||
static inline uintptr_t periphc_physregaddr(uintptr_t virtregaddr)
|
||||
{
|
||||
#if SAM_PERIPHB_PSECTION != SAM_PERIPHB_VSECTION
|
||||
/* Get the offset into the virtual memory region section containing the
|
||||
* register
|
||||
*/
|
||||
|
||||
uintptr_t sectoffset = virtregaddr - SAM_PERIPHC_VSECTION;
|
||||
|
||||
/* Add that offset to the physical base address of the memory region */
|
||||
|
||||
return SAM_PERIPHC_PSECTION + sectoffset;
|
||||
|
||||
#else
|
||||
/* 1-to-1 mapping */
|
||||
|
||||
return virtregaddr;
|
||||
|
||||
#endif
|
||||
}
|
||||
#endif
|
||||
|
||||
/****************************************************************************
|
||||
* Name: sysc_physregaddr
|
||||
*
|
||||
@ -123,6 +155,7 @@ static inline uintptr_t periphb_physregaddr(uintptr_t virtregaddr)
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
#ifdef SAM_SYSC_VSECTION
|
||||
static inline uintptr_t sysc_physregaddr(uintptr_t virtregaddr)
|
||||
{
|
||||
#if SAM_SYSC_PSECTION != SAM_SYSC_VSECTION
|
||||
@ -143,6 +176,7 @@ static inline uintptr_t sysc_physregaddr(uintptr_t virtregaddr)
|
||||
|
||||
#endif
|
||||
}
|
||||
#endif
|
||||
|
||||
/****************************************************************************
|
||||
* Name: isram_physramaddr
|
||||
@ -687,13 +721,29 @@ uintptr_t sam_physregaddr(uintptr_t virtregaddr)
|
||||
return periphb_physregaddr(virtregaddr);
|
||||
}
|
||||
|
||||
/* Check for a system controller register */
|
||||
/* Check for a system controller/peripheral C register
|
||||
*
|
||||
* Naming of peripheral sections differs between the SAMA5D3 and SAMA5D4.
|
||||
* There is nothing called SYSC in the SAMA5D4 memory map. The third
|
||||
* peripheral section is un-named in the SAMA5D4 memory map, but I have
|
||||
* chosen the name PERIPHC for this usage.
|
||||
*/
|
||||
|
||||
#ifdef SAM_PERIPHC_VSECTION
|
||||
else if (virtregaddr >= SAM_PERIPHC_VSECTION &&
|
||||
virtregaddr < (SAM_PERIPHC_VSECTION + SAM_PERIPHC_SIZE))
|
||||
{
|
||||
return periphc_physregaddr(virtregaddr);
|
||||
}
|
||||
#endif
|
||||
|
||||
#ifdef SAM_SYSC_VSECTION
|
||||
else if (virtregaddr >= SAM_SYSC_VSECTION &&
|
||||
virtregaddr < (SAM_SYSC_VSECTION + SAM_SYSC_SIZE))
|
||||
{
|
||||
return sysc_physregaddr(virtregaddr);
|
||||
}
|
||||
#endif
|
||||
|
||||
/* Check for NFCS SRAM. If NFC SRAM is being used by the NAND logic,
|
||||
* then it will be treated as peripheral space.
|
||||
|
||||
@ -1,7 +1,7 @@
|
||||
/************************************************************************************
|
||||
* arch/arm/src/sama5/sam_periphclks.h
|
||||
*
|
||||
* Copyright (C) 2013 Gregory Nutt. All rights reserved.
|
||||
* Copyright (C) 2013-2014 Gregory Nutt. All rights reserved.
|
||||
* Author: Gregory Nutt <gnutt@nuttx.org>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
@ -33,211 +33,26 @@
|
||||
*
|
||||
************************************************************************************/
|
||||
|
||||
#ifndef __ARCH_ARM_SRC_SAMA5_SAMS_PERIPHCLKS_H
|
||||
#define __ARCH_ARM_SRC_SAMA5_SAMS_PERIPHCLKS_H
|
||||
#ifndef __ARCH_ARM_SRC_SAMA5_SAM_PERIPHCLKS_H
|
||||
#define __ARCH_ARM_SRC_SAMA5_SAM_PERIPHCLKS_H
|
||||
|
||||
/************************************************************************************
|
||||
* Included Files
|
||||
************************************************************************************/
|
||||
|
||||
/* chip.h holds the characteristics of the configured chip */
|
||||
|
||||
#include <nuttx/config.h>
|
||||
#include <stdint.h>
|
||||
#include <arch/irq.h>
|
||||
#include "chip/sam_pmc.h"
|
||||
#include <arch/sama5/chip.h>
|
||||
|
||||
/************************************************************************************
|
||||
* Pre-processor Definitions
|
||||
************************************************************************************/
|
||||
/* Helper macros */
|
||||
/* Include the correctly logic for the configured chip */
|
||||
|
||||
#define sam_enableperiph0(s) putreg32((1 << (s)), SAM_PMC_PCER0)
|
||||
#define sam_enableperiph1(s) putreg32((1 << ((s) - 32)), SAM_PMC_PCER1)
|
||||
#define sam_disableperiph0(s) putreg32((1 << (s)), SAM_PMC_PCDR0)
|
||||
#define sam_disableperiph1(s) putreg32((1 << ((s) - 32)), SAM_PMC_PCDR1)
|
||||
#define sam_isenabled0(s) (getreg32(SAM_PMC_PCER0) & (1 << (s)) != 0)
|
||||
#define sam_isenabled1(s) (getreg32(SAM_PMC_PCER1) & (1 << ((s) - 32)) != 0)
|
||||
|
||||
#define sam_dbgu_enableclk() sam_enableperiph0(SAM_PID_DBGU)
|
||||
#define sam_pit_enableclk() sam_enableperiph0(SAM_PID_PIT)
|
||||
#define sam_wdt_enableclk() sam_enableperiph0(SAM_PID_WDT)
|
||||
#define sam_hsmc_enableclk() sam_enableperiph0(SAM_PID_HSMC)
|
||||
#define sam_pioa_enableclk() sam_enableperiph0(SAM_PID_PIOA)
|
||||
#define sam_piob_enableclk() sam_enableperiph0(SAM_PID_PIOB)
|
||||
#define sam_pioc_enableclk() sam_enableperiph0(SAM_PID_PIOC)
|
||||
#define sam_piod_enableclk() sam_enableperiph0(SAM_PID_PIOD)
|
||||
#define sam_pioe_enableclk() sam_enableperiph0(SAM_PID_PIOE)
|
||||
#define sam_smd_enableclk() sam_enableperiph0(SAM_PID_SMD)
|
||||
#define sam_usart0_enableclk() sam_enableperiph0(SAM_PID_USART0)
|
||||
#define sam_usart1_enableclk() sam_enableperiph0(SAM_PID_USART1)
|
||||
#define sam_usart2_enableclk() sam_enableperiph0(SAM_PID_USART2)
|
||||
#define sam_usart3_enableclk() sam_enableperiph0(SAM_PID_USART3)
|
||||
#define sam_uart0_enableclk() sam_enableperiph0(SAM_PID_UART0)
|
||||
#define sam_uart1_enableclk() sam_enableperiph0(SAM_PID_UART1)
|
||||
#define sam_twi0_enableclk() sam_enableperiph0(SAM_PID_TWI0)
|
||||
#define sam_twi1_enableclk() sam_enableperiph0(SAM_PID_TWI1)
|
||||
#define sam_twi2_enableclk() sam_enableperiph0(SAM_PID_TWI2)
|
||||
#define sam_hsmci0_enableclk() sam_enableperiph0(SAM_PID_HSMCI0)
|
||||
#define sam_hsmci1_enableclk() sam_enableperiph0(SAM_PID_HSMCI1)
|
||||
#define sam_hsmci2_enableclk() sam_enableperiph0(SAM_PID_HSMCI2)
|
||||
#define sam_spi0_enableclk() sam_enableperiph0(SAM_PID_SPI0)
|
||||
#define sam_spi1_enableclk() sam_enableperiph0(SAM_PID_SPI1)
|
||||
#define sam_tc0_enableclk() sam_enableperiph0(SAM_PID_TC0)
|
||||
#define sam_tc1_enableclk() sam_enableperiph0(SAM_PID_TC1)
|
||||
#define sam_pwm_enableclk() sam_enableperiph0(SAM_PID_PWM)
|
||||
#define sam_adc_enableclk() sam_enableperiph0(SAM_PID_ADC)
|
||||
#define sam_dmac0_enableclk() sam_enableperiph0(SAM_PID_DMAC0)
|
||||
#define sam_dmac1_enableclk() sam_enableperiph0(SAM_PID_DMAC1)
|
||||
|
||||
#define sam_uhphs_enableclk() sam_enableperiph1(SAM_PID_UHPHS)
|
||||
#define sam_udphs_enableclk() sam_enableperiph1(SAM_PID_UDPHS)
|
||||
#define sam_gmac_enableclk() sam_enableperiph1(SAM_PID_GMAC)
|
||||
#define sam_emac_enableclk() sam_enableperiph1(SAM_PID_EMAC)
|
||||
#define sam_lcdc_enableclk() sam_enableperiph1(SAM_PID_LCDC)
|
||||
#define sam_isi_enableclk() sam_enableperiph1(SAM_PID_ISI)
|
||||
#define sam_ssc0_enableclk() sam_enableperiph1(SAM_PID_SSC0)
|
||||
#define sam_ssc1_enableclk() sam_enableperiph1(SAM_PID_SSC1)
|
||||
#define sam_can0_enableclk() sam_enableperiph1(SAM_PID_CAN0)
|
||||
#define sam_can1_enableclk() sam_enableperiph1(SAM_PID_CAN1)
|
||||
#define sam_sha_enableclk() sam_enableperiph1(SAM_PID_SHA)
|
||||
#define sam_aes_enableclk() sam_enableperiph1(SAM_PID_AES)
|
||||
#define sam_tdes_enableclk() sam_enableperiph1(SAM_PID_TDES)
|
||||
#define sam_trng_enableclk() sam_enableperiph1(SAM_PID_TRNG)
|
||||
#define sam_arm_enableclk() sam_enableperiph1(SAM_PID_ARM)
|
||||
#define sam_aic_enableclk() sam_enableperiph1(SAM_PID_AIC)
|
||||
#define sam_fuse_enableclk() sam_enableperiph1(SAM_PID_FUSE)
|
||||
#define sam_mpddrc_enableclk() sam_enableperiph1(SAM_PID_MPDDRC)
|
||||
|
||||
#define sam_dbgu_disableclk() sam_disableperiph0(SAM_PID_DBGU)
|
||||
#define sam_pit_disableclk() sam_disableperiph0(SAM_PID_PIT)
|
||||
#define sam_wdt_disableclk() sam_disableperiph0(SAM_PID_WDT)
|
||||
#define sam_hsmc_disableclk() sam_disableperiph0(SAM_PID_HSMC)
|
||||
#define sam_pioa_disableclk() sam_disableperiph0(SAM_PID_PIOA)
|
||||
#define sam_piob_disableclk() sam_disableperiph0(SAM_PID_PIOB)
|
||||
#define sam_pioc_disableclk() sam_disableperiph0(SAM_PID_PIOC)
|
||||
#define sam_piod_disableclk() sam_disableperiph0(SAM_PID_PIOD)
|
||||
#define sam_pioe_disableclk() sam_disableperiph0(SAM_PID_PIOE)
|
||||
#define sam_smd_disableclk() sam_disableperiph0(SAM_PID_SMD)
|
||||
#define sam_usart0_disableclk() sam_disableperiph0(SAM_PID_USART0)
|
||||
#define sam_usart1_disableclk() sam_disableperiph0(SAM_PID_USART1)
|
||||
#define sam_usart2_disableclk() sam_disableperiph0(SAM_PID_USART2)
|
||||
#define sam_usart3_disableclk() sam_disableperiph0(SAM_PID_USART3)
|
||||
#define sam_uart0_disableclk() sam_disableperiph0(SAM_PID_UART0)
|
||||
#define sam_uart1_disableclk() sam_disableperiph0(SAM_PID_UART1)
|
||||
#define sam_twi0_disableclk() sam_disableperiph0(SAM_PID_TWI0)
|
||||
#define sam_twi1_disableclk() sam_disableperiph0(SAM_PID_TWI1)
|
||||
#define sam_twi2_disableclk() sam_disableperiph0(SAM_PID_TWI2)
|
||||
#define sam_hsmci0_disableclk() sam_disableperiph0(SAM_PID_HSMCI0)
|
||||
#define sam_hsmci1_disableclk() sam_disableperiph0(SAM_PID_HSMCI1)
|
||||
#define sam_hsmci2_disableclk() sam_disableperiph0(SAM_PID_HSMCI2)
|
||||
#define sam_spi0_disableclk() sam_disableperiph0(SAM_PID_SPI0)
|
||||
#define sam_spi1_disableclk() sam_disableperiph0(SAM_PID_SPI1)
|
||||
#define sam_tc0_disableclk() sam_disableperiph0(SAM_PID_TC0)
|
||||
#define sam_tc1_disableclk() sam_disableperiph0(SAM_PID_TC1)
|
||||
#define sam_pwm_disableclk() sam_disableperiph0(SAM_PID_PWM)
|
||||
#define sam_adc_disableclk() sam_disableperiph0(SAM_PID_ADC)
|
||||
#define sam_dmac0_disableclk() sam_disableperiph0(SAM_PID_DMAC0)
|
||||
#define sam_dmac1_disableclk() sam_disableperiph0(SAM_PID_DMAC1)
|
||||
|
||||
#define sam_uhphs_disableclk() sam_disableperiph1(SAM_PID_UHPHS)
|
||||
#define sam_udphs_disableclk() sam_disableperiph1(SAM_PID_UDPHS)
|
||||
#define sam_gmac_disableclk() sam_disableperiph1(SAM_PID_GMAC)
|
||||
#define sam_emac_disableclk() sam_disableperiph1(SAM_PID_EMAC)
|
||||
#define sam_lcdc_disableclk() sam_disableperiph1(SAM_PID_LCDC)
|
||||
#define sam_isi_disableclk() sam_disableperiph1(SAM_PID_ISI)
|
||||
#define sam_ssc0_disableclk() sam_disableperiph1(SAM_PID_SSC0)
|
||||
#define sam_ssc1_disableclk() sam_disableperiph1(SAM_PID_SSC1)
|
||||
#define sam_can0_disableclk() sam_disableperiph1(SAM_PID_CAN0)
|
||||
#define sam_can1_disableclk() sam_disableperiph1(SAM_PID_CAN1)
|
||||
#define sam_sha_disableclk() sam_disableperiph1(SAM_PID_SHA)
|
||||
#define sam_aes_disableclk() sam_disableperiph1(SAM_PID_AES)
|
||||
#define sam_tdes_disableclk() sam_disableperiph1(SAM_PID_TDES)
|
||||
#define sam_trng_disableclk() sam_disableperiph1(SAM_PID_TRNG)
|
||||
#define sam_arm_disableclk() sam_disableperiph1(SAM_PID_ARM)
|
||||
#define sam_aic_disableclk() sam_disableperiph1(SAM_PID_AIC)
|
||||
#define sam_fuse_disableclk() sam_disableperiph1(SAM_PID_FUSE)
|
||||
#define sam_mpddrc_disableclk() sam_disableperiph1(SAM_PID_MPDDRC)
|
||||
|
||||
#define sam_dbgu_isenabled() sam_isenabled0(SAM_PID_DBGU)
|
||||
#define sam_pit_isenabled() sam_isenabled0(SAM_PID_PIT)
|
||||
#define sam_wdt_isenabled() sam_isenabled0(SAM_PID_WDT)
|
||||
#define sam_hsmc_isenabled() sam_isenabled0(SAM_PID_HSMC)
|
||||
#define sam_pioa_isenabled() sam_isenabled0(SAM_PID_PIOA)
|
||||
#define sam_piob_isenabled() sam_isenabled0(SAM_PID_PIOB)
|
||||
#define sam_pioc_isenabled() sam_isenabled0(SAM_PID_PIOC)
|
||||
#define sam_piod_isenabled() sam_isenabled0(SAM_PID_PIOD)
|
||||
#define sam_pioe_isenabled() sam_isenabled0(SAM_PID_PIOE)
|
||||
#define sam_smd_isenabled() sam_isenabled0(SAM_PID_SMD)
|
||||
#define sam_usart0_isenabled() sam_isenabled0(SAM_PID_USART0)
|
||||
#define sam_usart1_isenabled() sam_isenabled0(SAM_PID_USART1)
|
||||
#define sam_usart2_isenabled() sam_isenabled0(SAM_PID_USART2)
|
||||
#define sam_usart3_isenabled() sam_isenabled0(SAM_PID_USART3)
|
||||
#define sam_uart0_isenabled() sam_isenabled0(SAM_PID_UART0)
|
||||
#define sam_uart1_isenabled() sam_isenabled0(SAM_PID_UART1)
|
||||
#define sam_twi0_isenabled() sam_isenabled0(SAM_PID_TWI0)
|
||||
#define sam_twi1_isenabled() sam_isenabled0(SAM_PID_TWI1)
|
||||
#define sam_twi2_isenabled() sam_isenabled0(SAM_PID_TWI2)
|
||||
#define sam_hsmci0_isenabled() sam_isenabled0(SAM_PID_HSMCI0)
|
||||
#define sam_hsmci1_isenabled() sam_isenabled0(SAM_PID_HSMCI1)
|
||||
#define sam_hsmci2_isenabled() sam_isenabled0(SAM_PID_HSMCI2)
|
||||
#define sam_spi0_isenabled() sam_isenabled0(SAM_PID_SPI0)
|
||||
#define sam_spi1_isenabled() sam_isenabled0(SAM_PID_SPI1)
|
||||
#define sam_tc0_isenabled() sam_isenabled0(SAM_PID_TC0)
|
||||
#define sam_tc1_isenabled() sam_isenabled0(SAM_PID_TC1)
|
||||
#define sam_pwm_isenabled() sam_isenabled0(SAM_PID_PWM)
|
||||
#define sam_adc_isenabled() sam_isenabled0(SAM_PID_ADC)
|
||||
#define sam_dmac0_isenabled() sam_isenabled0(SAM_PID_DMAC0)
|
||||
#define sam_dmac1_isenabled() sam_isenabled0(SAM_PID_DMAC1)
|
||||
|
||||
#define sam_uhphs_isenabled() sam_isenabled1(SAM_PID_UHPHS)
|
||||
#define sam_udphs_isenabled() sam_isenabled1(SAM_PID_UDPHS)
|
||||
#define sam_gmac_isenabled() sam_isenabled1(SAM_PID_GMAC)
|
||||
#define sam_emac_isenabled() sam_isenabled1(SAM_PID_EMAC)
|
||||
#define sam_lcdc_isenabled() sam_isenabled1(SAM_PID_LCDC)
|
||||
#define sam_isi_isenabled() sam_isenabled1(SAM_PID_ISI)
|
||||
#define sam_ssc0_isenabled() sam_isenabled1(SAM_PID_SSC0)
|
||||
#define sam_ssc1_isenabled() sam_isenabled1(SAM_PID_SSC1)
|
||||
#define sam_can0_isenabled() sam_isenabled1(SAM_PID_CAN0)
|
||||
#define sam_can1_isenabled() sam_isenabled1(SAM_PID_CAN1)
|
||||
#define sam_sha_isenabled() sam_isenabled1(SAM_PID_SHA)
|
||||
#define sam_aes_isenabled() sam_isenabled1(SAM_PID_AES)
|
||||
#define sam_tdes_isenabled() sam_isenabled1(SAM_PID_TDES)
|
||||
#define sam_trng_isenabled() sam_isenabled1(SAM_PID_TRNG)
|
||||
#define sam_arm_isenabled() sam_isenabled1(SAM_PID_ARM)
|
||||
#define sam_aic_isenabled() sam_isenabled1(SAM_PID_AIC)
|
||||
#define sam_fuse_isenabled() sam_isenabled1(SAM_PID_FUSE)
|
||||
#define sam_mpddrc_isenabled() sam_isenabled1(SAM_PID_MPDDRC)
|
||||
|
||||
/************************************************************************************
|
||||
* Public Types
|
||||
************************************************************************************/
|
||||
|
||||
/************************************************************************************
|
||||
* Inline Functions
|
||||
************************************************************************************/
|
||||
|
||||
#ifndef __ASSEMBLY__
|
||||
|
||||
/************************************************************************************
|
||||
* Public Data
|
||||
************************************************************************************/
|
||||
|
||||
#undef EXTERN
|
||||
#if defined(__cplusplus)
|
||||
#define EXTERN extern "C"
|
||||
extern "C"
|
||||
{
|
||||
#if defined(ATSAMA5D3)
|
||||
# include "sama5d3x_periphclks.h"
|
||||
#elif defined(ATSAMA5D4)
|
||||
# include "sama5d4x_periphclks.h"
|
||||
#else
|
||||
#define EXTERN extern
|
||||
# error Unrecognized SAMA5 family
|
||||
#endif
|
||||
|
||||
/************************************************************************************
|
||||
* Public Function Prototypes
|
||||
************************************************************************************/
|
||||
|
||||
#undef EXTERN
|
||||
#if defined(__cplusplus)
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __ASSEMBLY__ */
|
||||
#endif /* __ARCH_ARM_SRC_SAMA5_SAMS_PERIPHCLKS_H */
|
||||
#endif /* __ARCH_ARM_SRC_SAMA5_SAM_PERIPHCLKS_H */
|
||||
|
||||
@ -56,7 +56,7 @@
|
||||
#include "chip/sam_pio.h"
|
||||
|
||||
/****************************************************************************
|
||||
* Definitions
|
||||
* Pre-processor Definitions
|
||||
****************************************************************************/
|
||||
|
||||
/****************************************************************************
|
||||
@ -68,7 +68,24 @@
|
||||
****************************************************************************/
|
||||
|
||||
#ifdef CONFIG_DEBUG_GPIO
|
||||
static const char g_portchar[4] = { 'A', 'B', 'C', 'D' };
|
||||
static const char g_portchar[SAM_NPIO] =
|
||||
{
|
||||
'A', 'B', 'C', 'D', 'E'
|
||||
};
|
||||
#endif
|
||||
|
||||
/* SAM_PION_VBASE will only be defined if the PIO register blocks are
|
||||
* contiguous. If not defined, then we need to do a table lookup.
|
||||
*/
|
||||
|
||||
#ifndef SAM_PION_VBASE
|
||||
static const uintptr_t g_piobase[SAM_NPIO] =
|
||||
{
|
||||
SAM_PIOA_VBASE, SAM_PIOB_VBASE, SAM_PIOC_VBASE, SAM_PIOD_VBASE,
|
||||
SAM_PIOE_VBASE
|
||||
};
|
||||
|
||||
# define SAM_PION_VBASE(n) (g_piobase[(n)])
|
||||
#endif
|
||||
|
||||
/****************************************************************************
|
||||
@ -85,7 +102,15 @@ static const char g_portchar[4] = { 'A', 'B', 'C', 'D' };
|
||||
static inline uintptr_t sam_piobase(pio_pinset_t cfgset)
|
||||
{
|
||||
int port = (cfgset & PIO_PORT_MASK) >> PIO_PORT_SHIFT;
|
||||
return SAM_PION_VBASE(port);
|
||||
|
||||
if (port < SAM_NPIO)
|
||||
{
|
||||
return SAM_PION_VBASE(port);
|
||||
}
|
||||
else
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
}
|
||||
|
||||
/****************************************************************************
|
||||
@ -394,10 +419,20 @@ static inline int sam_configperiph(uintptr_t base, uint32_t pin,
|
||||
|
||||
int sam_configpio(pio_pinset_t cfgset)
|
||||
{
|
||||
uintptr_t base = sam_piobase(cfgset);
|
||||
uint32_t pin = sam_piopin(cfgset);
|
||||
uintptr_t base;
|
||||
uint32_t pin;
|
||||
irqstate_t flags;
|
||||
int ret;
|
||||
int ret;
|
||||
|
||||
/* Sanity check */
|
||||
|
||||
base = sam_piobase(cfgset);
|
||||
if (base == 0)
|
||||
{
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
pin = sam_piopin(cfgset);
|
||||
|
||||
/* Disable interrupts to prohibit re-entrance. */
|
||||
|
||||
@ -454,13 +489,16 @@ void sam_piowrite(pio_pinset_t pinset, bool value)
|
||||
uintptr_t base = sam_piobase(pinset);
|
||||
uint32_t pin = sam_piopin(pinset);
|
||||
|
||||
if (value)
|
||||
if (base != 0)
|
||||
{
|
||||
putreg32(pin, base + SAM_PIO_SODR_OFFSET);
|
||||
}
|
||||
else
|
||||
{
|
||||
putreg32(pin, base + SAM_PIO_CODR_OFFSET);
|
||||
if (value)
|
||||
{
|
||||
putreg32(pin, base + SAM_PIO_SODR_OFFSET);
|
||||
}
|
||||
else
|
||||
{
|
||||
putreg32(pin, base + SAM_PIO_CODR_OFFSET);
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
@ -475,19 +513,26 @@ void sam_piowrite(pio_pinset_t pinset, bool value)
|
||||
bool sam_pioread(pio_pinset_t pinset)
|
||||
{
|
||||
uintptr_t base = sam_piobase(pinset);
|
||||
uint32_t pin = sam_piopin(pinset);
|
||||
uint32_t pin;
|
||||
uint32_t regval;
|
||||
|
||||
if ((pinset & PIO_MODE_MASK) == PIO_OUTPUT)
|
||||
if (base != 0)
|
||||
{
|
||||
regval = getreg32(base + SAM_PIO_ODSR_OFFSET);
|
||||
}
|
||||
else
|
||||
{
|
||||
regval = getreg32(base + SAM_PIO_PDSR_OFFSET);
|
||||
pin = sam_piopin(pinset);
|
||||
|
||||
if ((pinset & PIO_MODE_MASK) == PIO_OUTPUT)
|
||||
{
|
||||
regval = getreg32(base + SAM_PIO_ODSR_OFFSET);
|
||||
}
|
||||
else
|
||||
{
|
||||
regval = getreg32(base + SAM_PIO_PDSR_OFFSET);
|
||||
}
|
||||
|
||||
return (regval & pin) != 0;
|
||||
}
|
||||
|
||||
return (regval & pin) != 0;
|
||||
return 0;
|
||||
}
|
||||
|
||||
/************************************************************************************
|
||||
|
||||
@ -47,7 +47,7 @@
|
||||
#include <stdbool.h>
|
||||
|
||||
/************************************************************************************
|
||||
* Definitions
|
||||
* Pre-processor Definitions
|
||||
************************************************************************************/
|
||||
/* Configuration ********************************************************************/
|
||||
|
||||
@ -67,6 +67,8 @@
|
||||
#define PIO_HAVE_SCHMITT 1
|
||||
#define PIO_HAVE_DRIVE 1
|
||||
|
||||
#define SAM_NPIO 5 /* (5) PIOA-E */
|
||||
|
||||
/* Bit-encoded input to sam_configpio() ********************************************/
|
||||
|
||||
/* 32-bit Encoding:
|
||||
|
||||
243
arch/arm/src/sama5/sama5d3x_periphclks.h
Normal file
243
arch/arm/src/sama5/sama5d3x_periphclks.h
Normal file
@ -0,0 +1,243 @@
|
||||
/************************************************************************************
|
||||
* arch/arm/src/sama5/sama5d3x_periphclks.h
|
||||
*
|
||||
* Copyright (C) 2013-2014 Gregory Nutt. All rights reserved.
|
||||
* Author: Gregory Nutt <gnutt@nuttx.org>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in
|
||||
* the documentation and/or other materials provided with the
|
||||
* distribution.
|
||||
* 3. Neither the name NuttX nor the names of its contributors may be
|
||||
* used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
|
||||
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
|
||||
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
|
||||
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
|
||||
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
|
||||
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
|
||||
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
************************************************************************************/
|
||||
|
||||
#ifndef __ARCH_ARM_SRC_SAMA5_SAMAD53X_PERIPHCLKS_H
|
||||
#define __ARCH_ARM_SRC_SAMA5_SAMAD53X_PERIPHCLKS_H
|
||||
|
||||
/************************************************************************************
|
||||
* Included Files
|
||||
************************************************************************************/
|
||||
|
||||
#include <nuttx/config.h>
|
||||
#include <stdint.h>
|
||||
#include <arch/irq.h>
|
||||
#include "chip/sam_pmc.h"
|
||||
|
||||
/************************************************************************************
|
||||
* Pre-processor Definitions
|
||||
************************************************************************************/
|
||||
/* Helper macros */
|
||||
|
||||
#define sam_enableperiph0(s) putreg32((1 << (s)), SAM_PMC_PCER0)
|
||||
#define sam_enableperiph1(s) putreg32((1 << ((s) - 32)), SAM_PMC_PCER1)
|
||||
#define sam_disableperiph0(s) putreg32((1 << (s)), SAM_PMC_PCDR0)
|
||||
#define sam_disableperiph1(s) putreg32((1 << ((s) - 32)), SAM_PMC_PCDR1)
|
||||
#define sam_isenabled0(s) (getreg32(SAM_PMC_PCER0) & (1 << (s)) != 0)
|
||||
#define sam_isenabled1(s) (getreg32(SAM_PMC_PCER1) & (1 << ((s) - 32)) != 0)
|
||||
|
||||
#define sam_dbgu_enableclk() sam_enableperiph0(SAM_PID_DBGU)
|
||||
#define sam_pit_enableclk() sam_enableperiph0(SAM_PID_PIT)
|
||||
#define sam_wdt_enableclk() sam_enableperiph0(SAM_PID_WDT)
|
||||
#define sam_hsmc_enableclk() sam_enableperiph0(SAM_PID_HSMC)
|
||||
#define sam_pioa_enableclk() sam_enableperiph0(SAM_PID_PIOA)
|
||||
#define sam_piob_enableclk() sam_enableperiph0(SAM_PID_PIOB)
|
||||
#define sam_pioc_enableclk() sam_enableperiph0(SAM_PID_PIOC)
|
||||
#define sam_piod_enableclk() sam_enableperiph0(SAM_PID_PIOD)
|
||||
#define sam_pioe_enableclk() sam_enableperiph0(SAM_PID_PIOE)
|
||||
#define sam_smd_enableclk() sam_enableperiph0(SAM_PID_SMD)
|
||||
#define sam_usart0_enableclk() sam_enableperiph0(SAM_PID_USART0)
|
||||
#define sam_usart1_enableclk() sam_enableperiph0(SAM_PID_USART1)
|
||||
#define sam_usart2_enableclk() sam_enableperiph0(SAM_PID_USART2)
|
||||
#define sam_usart3_enableclk() sam_enableperiph0(SAM_PID_USART3)
|
||||
#define sam_uart0_enableclk() sam_enableperiph0(SAM_PID_UART0)
|
||||
#define sam_uart1_enableclk() sam_enableperiph0(SAM_PID_UART1)
|
||||
#define sam_twi0_enableclk() sam_enableperiph0(SAM_PID_TWI0)
|
||||
#define sam_twi1_enableclk() sam_enableperiph0(SAM_PID_TWI1)
|
||||
#define sam_twi2_enableclk() sam_enableperiph0(SAM_PID_TWI2)
|
||||
#define sam_hsmci0_enableclk() sam_enableperiph0(SAM_PID_HSMCI0)
|
||||
#define sam_hsmci1_enableclk() sam_enableperiph0(SAM_PID_HSMCI1)
|
||||
#define sam_hsmci2_enableclk() sam_enableperiph0(SAM_PID_HSMCI2)
|
||||
#define sam_spi0_enableclk() sam_enableperiph0(SAM_PID_SPI0)
|
||||
#define sam_spi1_enableclk() sam_enableperiph0(SAM_PID_SPI1)
|
||||
#define sam_tc0_enableclk() sam_enableperiph0(SAM_PID_TC0)
|
||||
#define sam_tc1_enableclk() sam_enableperiph0(SAM_PID_TC1)
|
||||
#define sam_pwm_enableclk() sam_enableperiph0(SAM_PID_PWM)
|
||||
#define sam_adc_enableclk() sam_enableperiph0(SAM_PID_ADC)
|
||||
#define sam_dmac0_enableclk() sam_enableperiph0(SAM_PID_DMAC0)
|
||||
#define sam_dmac1_enableclk() sam_enableperiph0(SAM_PID_DMAC1)
|
||||
|
||||
#define sam_uhphs_enableclk() sam_enableperiph1(SAM_PID_UHPHS)
|
||||
#define sam_udphs_enableclk() sam_enableperiph1(SAM_PID_UDPHS)
|
||||
#define sam_gmac_enableclk() sam_enableperiph1(SAM_PID_GMAC)
|
||||
#define sam_emac0_enableclk() sam_enableperiph1(SAM_PID_EMAC0)
|
||||
#define sam_lcdc_enableclk() sam_enableperiph1(SAM_PID_LCDC)
|
||||
#define sam_isi_enableclk() sam_enableperiph1(SAM_PID_ISI)
|
||||
#define sam_ssc0_enableclk() sam_enableperiph1(SAM_PID_SSC0)
|
||||
#define sam_ssc1_enableclk() sam_enableperiph1(SAM_PID_SSC1)
|
||||
#define sam_can0_enableclk() sam_enableperiph1(SAM_PID_CAN0)
|
||||
#define sam_can1_enableclk() sam_enableperiph1(SAM_PID_CAN1)
|
||||
#define sam_sha_enableclk() sam_enableperiph1(SAM_PID_SHA)
|
||||
#define sam_aes_enableclk() sam_enableperiph1(SAM_PID_AES)
|
||||
#define sam_tdes_enableclk() sam_enableperiph1(SAM_PID_TDES)
|
||||
#define sam_trng_enableclk() sam_enableperiph1(SAM_PID_TRNG)
|
||||
#define sam_arm_enableclk() sam_enableperiph1(SAM_PID_ARM)
|
||||
#define sam_aic_enableclk() sam_enableperiph1(SAM_PID_AIC)
|
||||
#define sam_fuse_enableclk() sam_enableperiph1(SAM_PID_FUSE)
|
||||
#define sam_mpddrc_enableclk() sam_enableperiph1(SAM_PID_MPDDRC)
|
||||
|
||||
#define sam_dbgu_disableclk() sam_disableperiph0(SAM_PID_DBGU)
|
||||
#define sam_pit_disableclk() sam_disableperiph0(SAM_PID_PIT)
|
||||
#define sam_wdt_disableclk() sam_disableperiph0(SAM_PID_WDT)
|
||||
#define sam_hsmc_disableclk() sam_disableperiph0(SAM_PID_HSMC)
|
||||
#define sam_pioa_disableclk() sam_disableperiph0(SAM_PID_PIOA)
|
||||
#define sam_piob_disableclk() sam_disableperiph0(SAM_PID_PIOB)
|
||||
#define sam_pioc_disableclk() sam_disableperiph0(SAM_PID_PIOC)
|
||||
#define sam_piod_disableclk() sam_disableperiph0(SAM_PID_PIOD)
|
||||
#define sam_pioe_disableclk() sam_disableperiph0(SAM_PID_PIOE)
|
||||
#define sam_smd_disableclk() sam_disableperiph0(SAM_PID_SMD)
|
||||
#define sam_usart0_disableclk() sam_disableperiph0(SAM_PID_USART0)
|
||||
#define sam_usart1_disableclk() sam_disableperiph0(SAM_PID_USART1)
|
||||
#define sam_usart2_disableclk() sam_disableperiph0(SAM_PID_USART2)
|
||||
#define sam_usart3_disableclk() sam_disableperiph0(SAM_PID_USART3)
|
||||
#define sam_uart0_disableclk() sam_disableperiph0(SAM_PID_UART0)
|
||||
#define sam_uart1_disableclk() sam_disableperiph0(SAM_PID_UART1)
|
||||
#define sam_twi0_disableclk() sam_disableperiph0(SAM_PID_TWI0)
|
||||
#define sam_twi1_disableclk() sam_disableperiph0(SAM_PID_TWI1)
|
||||
#define sam_twi2_disableclk() sam_disableperiph0(SAM_PID_TWI2)
|
||||
#define sam_hsmci0_disableclk() sam_disableperiph0(SAM_PID_HSMCI0)
|
||||
#define sam_hsmci1_disableclk() sam_disableperiph0(SAM_PID_HSMCI1)
|
||||
#define sam_hsmci2_disableclk() sam_disableperiph0(SAM_PID_HSMCI2)
|
||||
#define sam_spi0_disableclk() sam_disableperiph0(SAM_PID_SPI0)
|
||||
#define sam_spi1_disableclk() sam_disableperiph0(SAM_PID_SPI1)
|
||||
#define sam_tc0_disableclk() sam_disableperiph0(SAM_PID_TC0)
|
||||
#define sam_tc1_disableclk() sam_disableperiph0(SAM_PID_TC1)
|
||||
#define sam_pwm_disableclk() sam_disableperiph0(SAM_PID_PWM)
|
||||
#define sam_adc_disableclk() sam_disableperiph0(SAM_PID_ADC)
|
||||
#define sam_dmac0_disableclk() sam_disableperiph0(SAM_PID_DMAC0)
|
||||
#define sam_dmac1_disableclk() sam_disableperiph0(SAM_PID_DMAC1)
|
||||
|
||||
#define sam_uhphs_disableclk() sam_disableperiph1(SAM_PID_UHPHS)
|
||||
#define sam_udphs_disableclk() sam_disableperiph1(SAM_PID_UDPHS)
|
||||
#define sam_gmac_disableclk() sam_disableperiph1(SAM_PID_GMAC)
|
||||
#define sam_emac0_disableclk() sam_disableperiph1(SAM_PID_EMAC0)
|
||||
#define sam_lcdc_disableclk() sam_disableperiph1(SAM_PID_LCDC)
|
||||
#define sam_isi_disableclk() sam_disableperiph1(SAM_PID_ISI)
|
||||
#define sam_ssc0_disableclk() sam_disableperiph1(SAM_PID_SSC0)
|
||||
#define sam_ssc1_disableclk() sam_disableperiph1(SAM_PID_SSC1)
|
||||
#define sam_can0_disableclk() sam_disableperiph1(SAM_PID_CAN0)
|
||||
#define sam_can1_disableclk() sam_disableperiph1(SAM_PID_CAN1)
|
||||
#define sam_sha_disableclk() sam_disableperiph1(SAM_PID_SHA)
|
||||
#define sam_aes_disableclk() sam_disableperiph1(SAM_PID_AES)
|
||||
#define sam_tdes_disableclk() sam_disableperiph1(SAM_PID_TDES)
|
||||
#define sam_trng_disableclk() sam_disableperiph1(SAM_PID_TRNG)
|
||||
#define sam_arm_disableclk() sam_disableperiph1(SAM_PID_ARM)
|
||||
#define sam_aic_disableclk() sam_disableperiph1(SAM_PID_AIC)
|
||||
#define sam_fuse_disableclk() sam_disableperiph1(SAM_PID_FUSE)
|
||||
#define sam_mpddrc_disableclk() sam_disableperiph1(SAM_PID_MPDDRC)
|
||||
|
||||
#define sam_dbgu_isenabled() sam_isenabled0(SAM_PID_DBGU)
|
||||
#define sam_pit_isenabled() sam_isenabled0(SAM_PID_PIT)
|
||||
#define sam_wdt_isenabled() sam_isenabled0(SAM_PID_WDT)
|
||||
#define sam_hsmc_isenabled() sam_isenabled0(SAM_PID_HSMC)
|
||||
#define sam_pioa_isenabled() sam_isenabled0(SAM_PID_PIOA)
|
||||
#define sam_piob_isenabled() sam_isenabled0(SAM_PID_PIOB)
|
||||
#define sam_pioc_isenabled() sam_isenabled0(SAM_PID_PIOC)
|
||||
#define sam_piod_isenabled() sam_isenabled0(SAM_PID_PIOD)
|
||||
#define sam_pioe_isenabled() sam_isenabled0(SAM_PID_PIOE)
|
||||
#define sam_smd_isenabled() sam_isenabled0(SAM_PID_SMD)
|
||||
#define sam_usart0_isenabled() sam_isenabled0(SAM_PID_USART0)
|
||||
#define sam_usart1_isenabled() sam_isenabled0(SAM_PID_USART1)
|
||||
#define sam_usart2_isenabled() sam_isenabled0(SAM_PID_USART2)
|
||||
#define sam_usart3_isenabled() sam_isenabled0(SAM_PID_USART3)
|
||||
#define sam_uart0_isenabled() sam_isenabled0(SAM_PID_UART0)
|
||||
#define sam_uart1_isenabled() sam_isenabled0(SAM_PID_UART1)
|
||||
#define sam_twi0_isenabled() sam_isenabled0(SAM_PID_TWI0)
|
||||
#define sam_twi1_isenabled() sam_isenabled0(SAM_PID_TWI1)
|
||||
#define sam_twi2_isenabled() sam_isenabled0(SAM_PID_TWI2)
|
||||
#define sam_hsmci0_isenabled() sam_isenabled0(SAM_PID_HSMCI0)
|
||||
#define sam_hsmci1_isenabled() sam_isenabled0(SAM_PID_HSMCI1)
|
||||
#define sam_hsmci2_isenabled() sam_isenabled0(SAM_PID_HSMCI2)
|
||||
#define sam_spi0_isenabled() sam_isenabled0(SAM_PID_SPI0)
|
||||
#define sam_spi1_isenabled() sam_isenabled0(SAM_PID_SPI1)
|
||||
#define sam_tc0_isenabled() sam_isenabled0(SAM_PID_TC0)
|
||||
#define sam_tc1_isenabled() sam_isenabled0(SAM_PID_TC1)
|
||||
#define sam_pwm_isenabled() sam_isenabled0(SAM_PID_PWM)
|
||||
#define sam_adc_isenabled() sam_isenabled0(SAM_PID_ADC)
|
||||
#define sam_dmac0_isenabled() sam_isenabled0(SAM_PID_DMAC0)
|
||||
#define sam_dmac1_isenabled() sam_isenabled0(SAM_PID_DMAC1)
|
||||
|
||||
#define sam_uhphs_isenabled() sam_isenabled1(SAM_PID_UHPHS)
|
||||
#define sam_udphs_isenabled() sam_isenabled1(SAM_PID_UDPHS)
|
||||
#define sam_gmac_isenabled() sam_isenabled1(SAM_PID_GMAC)
|
||||
#define sam_emac_isenabled() sam_isenabled1(SAM_PID_EMAC)
|
||||
#define sam_lcdc_isenabled() sam_isenabled1(SAM_PID_LCDC)
|
||||
#define sam_isi_isenabled() sam_isenabled1(SAM_PID_ISI)
|
||||
#define sam_ssc0_isenabled() sam_isenabled1(SAM_PID_SSC0)
|
||||
#define sam_ssc1_isenabled() sam_isenabled1(SAM_PID_SSC1)
|
||||
#define sam_can0_isenabled() sam_isenabled1(SAM_PID_CAN0)
|
||||
#define sam_can1_isenabled() sam_isenabled1(SAM_PID_CAN1)
|
||||
#define sam_sha_isenabled() sam_isenabled1(SAM_PID_SHA)
|
||||
#define sam_aes_isenabled() sam_isenabled1(SAM_PID_AES)
|
||||
#define sam_tdes_isenabled() sam_isenabled1(SAM_PID_TDES)
|
||||
#define sam_trng_isenabled() sam_isenabled1(SAM_PID_TRNG)
|
||||
#define sam_arm_isenabled() sam_isenabled1(SAM_PID_ARM)
|
||||
#define sam_aic_isenabled() sam_isenabled1(SAM_PID_AIC)
|
||||
#define sam_fuse_isenabled() sam_isenabled1(SAM_PID_FUSE)
|
||||
#define sam_mpddrc_isenabled() sam_isenabled1(SAM_PID_MPDDRC)
|
||||
|
||||
/************************************************************************************
|
||||
* Public Types
|
||||
************************************************************************************/
|
||||
|
||||
/************************************************************************************
|
||||
* Inline Functions
|
||||
************************************************************************************/
|
||||
|
||||
#ifndef __ASSEMBLY__
|
||||
|
||||
/************************************************************************************
|
||||
* Public Data
|
||||
************************************************************************************/
|
||||
|
||||
#undef EXTERN
|
||||
#if defined(__cplusplus)
|
||||
#define EXTERN extern "C"
|
||||
extern "C"
|
||||
{
|
||||
#else
|
||||
#define EXTERN extern
|
||||
#endif
|
||||
|
||||
/************************************************************************************
|
||||
* Public Function Prototypes
|
||||
************************************************************************************/
|
||||
|
||||
#undef EXTERN
|
||||
#if defined(__cplusplus)
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __ASSEMBLY__ */
|
||||
#endif /* __ARCH_ARM_SRC_SAMA5_SAMAD53X_PERIPHCLKS_H */
|
||||
297
arch/arm/src/sama5/sama5d4x_periphclks.h
Normal file
297
arch/arm/src/sama5/sama5d4x_periphclks.h
Normal file
@ -0,0 +1,297 @@
|
||||
/************************************************************************************
|
||||
* arch/arm/src/sama5/sama5d4x_periphclks.h
|
||||
*
|
||||
* Copyright (C) 2014 Gregory Nutt. All rights reserved.
|
||||
* Author: Gregory Nutt <gnutt@nuttx.org>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in
|
||||
* the documentation and/or other materials provided with the
|
||||
* distribution.
|
||||
* 3. Neither the name NuttX nor the names of its contributors may be
|
||||
* used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
|
||||
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
|
||||
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
|
||||
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
|
||||
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
|
||||
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
|
||||
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
************************************************************************************/
|
||||
|
||||
#ifndef __ARCH_ARM_SRC_SAMA5_SAMAD54X_PERIPHCLKS_H
|
||||
#define __ARCH_ARM_SRC_SAMA5_SAMAD54X_PERIPHCLKS_H
|
||||
|
||||
/************************************************************************************
|
||||
* Included Files
|
||||
************************************************************************************/
|
||||
|
||||
#include <nuttx/config.h>
|
||||
#include <stdint.h>
|
||||
#include <arch/irq.h>
|
||||
#include "chip/sam_pmc.h"
|
||||
|
||||
/************************************************************************************
|
||||
* Pre-processor Definitions
|
||||
************************************************************************************/
|
||||
/* Helper macros */
|
||||
|
||||
#define sam_enableperiph0(s) putreg32((1 << (s)), SAM_PMC_PCER0)
|
||||
#define sam_enableperiph1(s) putreg32((1 << ((s) - 32)), SAM_PMC_PCER1)
|
||||
#define sam_enableperiph2(s) putreg32((1 << ((s) - 64)), SAM_PMC_PCER2)
|
||||
#define sam_disableperiph0(s) putreg32((1 << (s)), SAM_PMC_PCDR0)
|
||||
#define sam_disableperiph1(s) putreg32((1 << ((s) - 32)), SAM_PMC_PCDR1)
|
||||
#define sam_disableperiph2(s) putreg32((1 << ((s) - 63)), SAM_PMC_PCDR2)
|
||||
#define sam_isenabled0(s) (getreg32(SAM_PMC_PCER0) & (1 << (s)) != 0)
|
||||
#define sam_isenabled1(s) (getreg32(SAM_PMC_PCER1) & (1 << ((s) - 32)) != 0)
|
||||
#define sam_isenabled2(s) (getreg32(SAM_PMC_PCER2) & (1 << ((s) - 64)) != 0)
|
||||
|
||||
/* Enable peripheral clocking */
|
||||
|
||||
#define sam_arm_enableclk() sam_enableperiph0(SAM_PID_ARM)
|
||||
#define sam_pit_enableclk() sam_enableperiph0(SAM_PID_PIT)
|
||||
#define sam_wdt_enableclk() sam_enableperiph0(SAM_PID_WDT)
|
||||
#define sam_piod_enableclk() sam_enableperiph0(SAM_PID_PIOD)
|
||||
#define sam_usart0_enableclk() sam_enableperiph0(SAM_PID_USART0)
|
||||
#define sam_usart1_enableclk() sam_enableperiph0(SAM_PID_USART1)
|
||||
#define sam_xdmac0_enableclk() sam_enableperiph0(SAM_PID_XDMAC0)
|
||||
#define sam_icm_enableclk() sam_enableperiph0(SAM_PID_ICM)
|
||||
#define sam_cpkcc_enableclk() sam_enableperiph0(SAM_PID_CPKCC)
|
||||
#define sam_aes_enableclk() sam_enableperiph0(SAM_PID_AES)
|
||||
#define sam_aesb_enableclk() sam_enableperiph0(SAM_PID_AESB)
|
||||
#define sam_tdes_enableclk() sam_enableperiph0(SAM_PID_TDES)
|
||||
#define sam_sha_enableclk() sam_enableperiph0(SAM_PID_SHA)
|
||||
#define sam_mpddrc_enableclk() sam_enableperiph0(SAM_PID_MPDDRC)
|
||||
#define sam_matrix1_enableclk() sam_enableperiph0(SAM_PID_MATRIX1)
|
||||
#define sam_matrix0_enableclk() sam_enableperiph0(SAM_PID_MATRIX0)
|
||||
#define sam_vdec_enableclk() sam_enableperiph0(SAM_PID_VDEC)
|
||||
#define sam_sbm_enableclk() sam_enableperiph0(SAM_PID_SBM)
|
||||
#define sam_hsmc_enableclk() sam_enableperiph0(SAM_PID_HSMC)
|
||||
#define sam_pioa_enableclk() sam_enableperiph0(SAM_PID_PIOA)
|
||||
#define sam_piob_enableclk() sam_enableperiph0(SAM_PID_PIOB)
|
||||
#define sam_pioc_enableclk() sam_enableperiph0(SAM_PID_PIOC)
|
||||
#define sam_pioe_enableclk() sam_enableperiph0(SAM_PID_PIOE)
|
||||
#define sam_uart0_enableclk() sam_enableperiph0(SAM_PID_UART0)
|
||||
#define sam_uart1_enableclk() sam_enableperiph0(SAM_PID_UART1)
|
||||
#define sam_usart2_enableclk() sam_enableperiph0(SAM_PID_USART2)
|
||||
#define sam_usart3_enableclk() sam_enableperiph0(SAM_PID_USART3)
|
||||
#define sam_usart4_enableclk() sam_enableperiph0(SAM_PID_USART4)
|
||||
|
||||
#define sam_twi0_enableclk() sam_enableperiph1(SAM_PID_TWI0)
|
||||
#define sam_twi1_enableclk() sam_enableperiph1(SAM_PID_TWI1)
|
||||
#define sam_twi2_enableclk() sam_enableperiph1(SAM_PID_TWI2)
|
||||
#define sam_hsmci0_enableclk() sam_enableperiph1(SAM_PID_HSMCI0)
|
||||
#define sam_hsmci1_enableclk() sam_enableperiph1(SAM_PID_HSMCI1)
|
||||
#define sam_spi0_enableclk() sam_enableperiph1(SAM_PID_SPI0)
|
||||
#define sam_spi1_enableclk() sam_enableperiph1(SAM_PID_SPI1)
|
||||
#define sam_spi2_enableclk() sam_enableperiph1(SAM_PID_SPI2)
|
||||
#define sam_tc0_enableclk() sam_enableperiph1(SAM_PID_TC0)
|
||||
#define sam_tc1_enableclk() sam_enableperiph1(SAM_PID_TC1)
|
||||
#define sam_tc2_enableclk() sam_enableperiph1(SAM_PID_TC2)
|
||||
#define sam_pwm_enableclk() sam_enableperiph1(SAM_PID_PWM)
|
||||
#define sam_adc_enableclk() sam_enableperiph1(SAM_PID_ADC)
|
||||
#define sam_dbgu_enableclk() sam_enableperiph1(SAM_PID_DBGU)
|
||||
#define sam_uhphs_enableclk() sam_enableperiph1(SAM_PID_UHPHS)
|
||||
#define sam_udphs_enableclk() sam_enableperiph1(SAM_PID_UDPHS)
|
||||
#define sam_ssc0_enableclk() sam_enableperiph1(SAM_PID_SSC0)
|
||||
#define sam_ssc1_enableclk() sam_enableperiph1(SAM_PID_SSC1)
|
||||
#define sam_xdmac1_enableclk() sam_enableperiph1(SAM_PID_XDMAC1)
|
||||
#define sam_lcdc_enableclk() sam_enableperiph1(SAM_PID_LCDC)
|
||||
#define sam_isi_enableclk() sam_enableperiph1(SAM_PID_ISI)
|
||||
#define sam_trng_enableclk() sam_enableperiph1(SAM_PID_TRNG)
|
||||
#define sam_emac0_enableclk() sam_enableperiph1(SAM_PID_EMAC0)
|
||||
#define sam_emac1_enableclk() sam_enableperiph1(SAM_PID_EMAC1)
|
||||
#define sam_aicid_enableclk() sam_enableperiph1(SAM_PID_AICID)
|
||||
#define sam_sfc_enableclk() sam_enableperiph1(SAM_PID_SFC)
|
||||
#define sam_secureram_enableclk() sam_enableperiph1(SAM_PID_SECURAM)
|
||||
#define sam_smd_enableclk() sam_enableperiph1(SAM_PID_SMD)
|
||||
#define sam_twi3_enableclk() sam_enableperiph1(SAM_PID_TWI3)
|
||||
#define sam_catb_enableclk() sam_enableperiph1(SAM_PID_CATB)
|
||||
|
||||
#define sam_sfr_enableclk() sam_enableperiph2(SAM_PID_CATB)
|
||||
#define sam_aic_enableclk() sam_enableperiph2(SAM_PID_CATB)
|
||||
#define sam_saic_enableclk() sam_enableperiph2(SAM_PID_CATB)
|
||||
#define sam_l2cc_enableclk() sam_enableperiph2(SAM_PID_CATB)
|
||||
|
||||
/* Disable peripheral clocking */
|
||||
|
||||
#define sam_arm_disableclk() sam_disableperiph0(SAM_PID_ARM)
|
||||
#define sam_pit_disableclk() sam_disableperiph0(SAM_PID_PIT)
|
||||
#define sam_wdt_disableclk() sam_disableperiph0(SAM_PID_WDT)
|
||||
#define sam_piod_disableclk() sam_disableperiph0(SAM_PID_PIOD)
|
||||
#define sam_usart0_disableclk() sam_disableperiph0(SAM_PID_USART0)
|
||||
#define sam_usart1_disableclk() sam_disableperiph0(SAM_PID_USART1)
|
||||
#define sam_xdmac0_disableclk() sam_disableperiph0(SAM_PID_XDMAC0)
|
||||
#define sam_icm_disableclk() sam_disableperiph0(SAM_PID_ICM)
|
||||
#define sam_cpkcc_disableclk() sam_disableperiph0(SAM_PID_CPKCC)
|
||||
#define sam_aes_disableclk() sam_disableperiph0(SAM_PID_AES)
|
||||
#define sam_aesb_disableclk() sam_disableperiph0(SAM_PID_AESB)
|
||||
#define sam_tdes_disableclk() sam_disableperiph0(SAM_PID_TDES)
|
||||
#define sam_sha_disableclk() sam_disableperiph0(SAM_PID_SHA)
|
||||
#define sam_mpddrc_disableclk() sam_disableperiph0(SAM_PID_MPDDRC)
|
||||
#define sam_matrix1_disableclk() sam_disableperiph0(SAM_PID_MATRIX1)
|
||||
#define sam_matrix0_disableclk() sam_disableperiph0(SAM_PID_MATRIX0)
|
||||
#define sam_vdec_disableclk() sam_disableperiph0(SAM_PID_VDEC)
|
||||
#define sam_sbm_disableclk() sam_disableperiph0(SAM_PID_SBM)
|
||||
#define sam_hsmc_disableclk() sam_disableperiph0(SAM_PID_HSMC)
|
||||
#define sam_pioa_disableclk() sam_disableperiph0(SAM_PID_PIOA)
|
||||
#define sam_piob_disableclk() sam_disableperiph0(SAM_PID_PIOB)
|
||||
#define sam_pioc_disableclk() sam_disableperiph0(SAM_PID_PIOC)
|
||||
#define sam_pioe_disableclk() sam_disableperiph0(SAM_PID_PIOE)
|
||||
#define sam_uart0_disableclk() sam_disableperiph0(SAM_PID_UART0)
|
||||
#define sam_uart1_disableclk() sam_disableperiph0(SAM_PID_UART1)
|
||||
#define sam_usart2_disableclk() sam_disableperiph0(SAM_PID_USART2)
|
||||
#define sam_usart3_disableclk() sam_disableperiph0(SAM_PID_USART3)
|
||||
#define sam_usart4_disableclk() sam_disableperiph0(SAM_PID_USART4)
|
||||
|
||||
#define sam_twi0_disableclk() sam_disableperiph1(SAM_PID_TWI0)
|
||||
#define sam_twi1_disableclk() sam_disableperiph1(SAM_PID_TWI1)
|
||||
#define sam_twi2_disableclk() sam_disableperiph1(SAM_PID_TWI2)
|
||||
#define sam_hsmci0_disableclk() sam_disableperiph1(SAM_PID_HSMCI0)
|
||||
#define sam_hsmci1_disableclk() sam_disableperiph1(SAM_PID_HSMCI1)
|
||||
#define sam_spi0_disableclk() sam_disableperiph1(SAM_PID_SPI0)
|
||||
#define sam_spi1_disableclk() sam_disableperiph1(SAM_PID_SPI1)
|
||||
#define sam_spi2_disableclk() sam_disableperiph1(SAM_PID_SPI2)
|
||||
#define sam_tc0_disableclk() sam_disableperiph1(SAM_PID_TC0)
|
||||
#define sam_tc1_disableclk() sam_disableperiph1(SAM_PID_TC1)
|
||||
#define sam_tc2_disableclk() sam_disableperiph1(SAM_PID_TC2)
|
||||
#define sam_pwm_disableclk() sam_disableperiph1(SAM_PID_PWM)
|
||||
#define sam_adc_disableclk() sam_disableperiph1(SAM_PID_ADC)
|
||||
#define sam_dbgu_disableclk() sam_disableperiph1(SAM_PID_DBGU)
|
||||
#define sam_uhphs_disableclk() sam_disableperiph1(SAM_PID_UHPHS)
|
||||
#define sam_udphs_disableclk() sam_disableperiph1(SAM_PID_UDPHS)
|
||||
#define sam_ssc0_disableclk() sam_disableperiph1(SAM_PID_SSC0)
|
||||
#define sam_ssc1_disableclk() sam_disableperiph1(SAM_PID_SSC1)
|
||||
#define sam_xdmac1_disableclk() sam_disableperiph1(SAM_PID_XDMAC1)
|
||||
#define sam_lcdc_disableclk() sam_disableperiph1(SAM_PID_LCDC)
|
||||
#define sam_isi_disableclk() sam_disableperiph1(SAM_PID_ISI)
|
||||
#define sam_trng_disableclk() sam_disableperiph1(SAM_PID_TRNG)
|
||||
#define sam_emac0_disableclk() sam_disableperiph1(SAM_PID_EMAC0)
|
||||
#define sam_emac1_disableclk() sam_disableperiph1(SAM_PID_EMAC1)
|
||||
#define sam_aicid_disableclk() sam_disableperiph1(SAM_PID_AICID)
|
||||
#define sam_sfc_disableclk() sam_disableperiph1(SAM_PID_SFC)
|
||||
#define sam_secureram_disableclk() sam_disableperiph1(SAM_PID_SECURAM)
|
||||
#define sam_smd_disableclk() sam_disableperiph1(SAM_PID_SMD)
|
||||
#define sam_twi3_disableclk() sam_disableperiph1(SAM_PID_TWI3)
|
||||
#define sam_catb_disableclk() sam_disableperiph1(SAM_PID_CATB)
|
||||
|
||||
#define sam_sfr_disableclk() sam_disableperiph2(SAM_PID_CATB)
|
||||
#define sam_aic_disableclk() sam_disableperiph2(SAM_PID_CATB)
|
||||
#define sam_saic_disableclk() sam_disableperiph2(SAM_PID_CATB)
|
||||
#define sam_l2cc_disableclk() sam_disableperiph2(SAM_PID_CATB)
|
||||
|
||||
/* Test if peripheral clocking is enabled */
|
||||
|
||||
#define sam_arm_isenabled() sam_isenabled0(SAM_PID_ARM)
|
||||
#define sam_pit_isenabled() sam_isenabled0(SAM_PID_PIT)
|
||||
#define sam_wdt_isenabled() sam_isenabled0(SAM_PID_WDT)
|
||||
#define sam_piod_isenabled() sam_isenabled0(SAM_PID_PIOD)
|
||||
#define sam_usart0_isenabled() sam_isenabled0(SAM_PID_USART0)
|
||||
#define sam_usart1_isenabled() sam_isenabled0(SAM_PID_USART1)
|
||||
#define sam_xdmac0_isenabled() sam_isenabled0(SAM_PID_XDMAC0)
|
||||
#define sam_icm_isenabled() sam_isenabled0(SAM_PID_ICM)
|
||||
#define sam_cpkcc_isenabled() sam_isenabled0(SAM_PID_CPKCC)
|
||||
#define sam_aes_isenabled() sam_isenabled0(SAM_PID_AES)
|
||||
#define sam_aesb_isenabled() sam_isenabled0(SAM_PID_AESB)
|
||||
#define sam_tdes_isenabled() sam_isenabled0(SAM_PID_TDES)
|
||||
#define sam_sha_isenabled() sam_isenabled0(SAM_PID_SHA)
|
||||
#define sam_mpddrc_isenabled() sam_isenabled0(SAM_PID_MPDDRC)
|
||||
#define sam_matrix1_isenabled() sam_isenabled0(SAM_PID_MATRIX1)
|
||||
#define sam_matrix0_isenabled() sam_isenabled0(SAM_PID_MATRIX0)
|
||||
#define sam_vdec_isenabled() sam_isenabled0(SAM_PID_VDEC)
|
||||
#define sam_sbm_isenabled() sam_isenabled0(SAM_PID_SBM)
|
||||
#define sam_hsmc_isenabled() sam_isenabled0(SAM_PID_HSMC)
|
||||
#define sam_pioa_isenabled() sam_isenabled0(SAM_PID_PIOA)
|
||||
#define sam_piob_isenabled() sam_isenabled0(SAM_PID_PIOB)
|
||||
#define sam_pioc_isenabled() sam_isenabled0(SAM_PID_PIOC)
|
||||
#define sam_pioe_isenabled() sam_isenabled0(SAM_PID_PIOE)
|
||||
#define sam_uart0_isenabled() sam_isenabled0(SAM_PID_UART0)
|
||||
#define sam_uart1_isenabled() sam_isenabled0(SAM_PID_UART1)
|
||||
#define sam_usart2_isenabled() sam_isenabled0(SAM_PID_USART2)
|
||||
#define sam_usart3_isenabled() sam_isenabled0(SAM_PID_USART3)
|
||||
#define sam_usart4_isenabled() sam_isenabled0(SAM_PID_USART4)
|
||||
|
||||
#define sam_twi0_isenabled() sam_isenabled1(SAM_PID_TWI0)
|
||||
#define sam_twi1_isenabled() sam_isenabled1(SAM_PID_TWI1)
|
||||
#define sam_twi2_isenabled() sam_isenabled1(SAM_PID_TWI2)
|
||||
#define sam_hsmci0_isenabled() sam_isenabled1(SAM_PID_HSMCI0)
|
||||
#define sam_hsmci1_isenabled() sam_isenabled1(SAM_PID_HSMCI1)
|
||||
#define sam_spi0_isenabled() sam_isenabled1(SAM_PID_SPI0)
|
||||
#define sam_spi1_isenabled() sam_isenabled1(SAM_PID_SPI1)
|
||||
#define sam_spi2_isenabled() sam_isenabled1(SAM_PID_SPI2)
|
||||
#define sam_tc0_isenabled() sam_isenabled1(SAM_PID_TC0)
|
||||
#define sam_tc1_isenabled() sam_isenabled1(SAM_PID_TC1)
|
||||
#define sam_tc2_isenabled() sam_isenabled1(SAM_PID_TC2)
|
||||
#define sam_pwm_isenabled() sam_isenabled1(SAM_PID_PWM)
|
||||
#define sam_adc_isenabled() sam_isenabled1(SAM_PID_ADC)
|
||||
#define sam_dbgu_isenabled() sam_isenabled1(SAM_PID_DBGU)
|
||||
#define sam_uhphs_isenabled() sam_isenabled1(SAM_PID_UHPHS)
|
||||
#define sam_udphs_isenabled() sam_isenabled1(SAM_PID_UDPHS)
|
||||
#define sam_ssc0_isenabled() sam_isenabled1(SAM_PID_SSC0)
|
||||
#define sam_ssc1_isenabled() sam_isenabled1(SAM_PID_SSC1)
|
||||
#define sam_xdmac1_isenabled() sam_isenabled1(SAM_PID_XDMAC1)
|
||||
#define sam_lcdc_isenabled() sam_isenabled1(SAM_PID_LCDC)
|
||||
#define sam_isi_isenabled() sam_isenabled1(SAM_PID_ISI)
|
||||
#define sam_trng_isenabled() sam_isenabled1(SAM_PID_TRNG)
|
||||
#define sam_emac0_isenabled() sam_isenabled1(SAM_PID_EMAC0)
|
||||
#define sam_emac1_isenabled() sam_isenabled1(SAM_PID_EMAC1)
|
||||
#define sam_aicid_isenabled() sam_isenabled1(SAM_PID_AICID)
|
||||
#define sam_sfc_isenabled() sam_isenabled1(SAM_PID_SFC)
|
||||
#define sam_secureram_isenabled() sam_isenabled1(SAM_PID_SECURAM)
|
||||
#define sam_smd_isenabled() sam_isenabled1(SAM_PID_SMD)
|
||||
#define sam_twi3_isenabled() sam_isenabled1(SAM_PID_TWI3)
|
||||
#define sam_catb_isenabled() sam_isenabled1(SAM_PID_CATB)
|
||||
|
||||
#define sam_sfr_isenabled() sam_isenabled2(SAM_PID_CATB)
|
||||
#define sam_aic_isenabled() sam_isenabled2(SAM_PID_CATB)
|
||||
#define sam_saic_isenabled() sam_isenabled2(SAM_PID_CATB)
|
||||
#define sam_l2cc_isenabled() sam_isenabled2(SAM_PID_CATB)
|
||||
|
||||
/************************************************************************************
|
||||
* Public Types
|
||||
************************************************************************************/
|
||||
|
||||
/************************************************************************************
|
||||
* Inline Functions
|
||||
************************************************************************************/
|
||||
|
||||
#ifndef __ASSEMBLY__
|
||||
|
||||
/************************************************************************************
|
||||
* Public Data
|
||||
************************************************************************************/
|
||||
|
||||
#undef EXTERN
|
||||
#if defined(__cplusplus)
|
||||
#define EXTERN extern "C"
|
||||
extern "C"
|
||||
{
|
||||
#else
|
||||
#define EXTERN extern
|
||||
#endif
|
||||
|
||||
/************************************************************************************
|
||||
* Public Function Prototypes
|
||||
************************************************************************************/
|
||||
|
||||
#undef EXTERN
|
||||
#if defined(__cplusplus)
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __ASSEMBLY__ */
|
||||
#endif /* __ARCH_ARM_SRC_SAMA5_SAMAD54X_PERIPHCLKS_H */
|
||||
@ -128,7 +128,7 @@ CONFIG_SAMA5_HAVE_CAN0=y
|
||||
CONFIG_SAMA5_HAVE_CAN1=y
|
||||
CONFIG_SAMA5_HAVE_LCDC=y
|
||||
CONFIG_SAMA5_HAVE_GMAC=y
|
||||
CONFIG_SAMA5_HAVE_EMAC=y
|
||||
CONFIG_SAMA5_HAVE_EMAC0=y
|
||||
CONFIG_SAMA5_HAVE_HSMCI2=y
|
||||
CONFIG_SAMA5_HAVE_TC1=y
|
||||
# CONFIG_ARCH_CHIP_ATSAMA5D31 is not set
|
||||
|
||||
@ -133,7 +133,7 @@ CONFIG_USBHOST_ISOC_DISABLE=y
|
||||
# CONFIG_SAMA5_HAVE_CAN1 is not set
|
||||
CONFIG_SAMA5_HAVE_LCDC=y
|
||||
CONFIG_SAMA5_HAVE_GMAC=y
|
||||
# CONFIG_SAMA5_HAVE_EMAC is not set
|
||||
# CONFIG_SAMA5_HAVE_EMAC0 is not set
|
||||
# CONFIG_SAMA5_HAVE_HSMCI2 is not set
|
||||
# CONFIG_SAMA5_HAVE_TC1 is not set
|
||||
# CONFIG_ARCH_CHIP_ATSAMA5D31 is not set
|
||||
|
||||
@ -128,7 +128,7 @@ CONFIG_ARMV7A_TOOLCHAIN_CODESOURCERYW=y
|
||||
# CONFIG_SAMA5_HAVE_CAN1 is not set
|
||||
CONFIG_SAMA5_HAVE_LCDC=y
|
||||
CONFIG_SAMA5_HAVE_GMAC=y
|
||||
# CONFIG_SAMA5_HAVE_EMAC is not set
|
||||
# CONFIG_SAMA5_HAVE_EMAC0 is not set
|
||||
# CONFIG_SAMA5_HAVE_HSMCI2 is not set
|
||||
# CONFIG_SAMA5_HAVE_TC1 is not set
|
||||
# CONFIG_ARCH_CHIP_ATSAMA5D31 is not set
|
||||
|
||||
@ -128,7 +128,7 @@ CONFIG_ARMV7A_TOOLCHAIN_CODESOURCERYW=y
|
||||
# CONFIG_SAMA5_HAVE_CAN1 is not set
|
||||
CONFIG_SAMA5_HAVE_LCDC=y
|
||||
CONFIG_SAMA5_HAVE_GMAC=y
|
||||
# CONFIG_SAMA5_HAVE_EMAC is not set
|
||||
# CONFIG_SAMA5_HAVE_EMAC0 is not set
|
||||
# CONFIG_SAMA5_HAVE_HSMCI2 is not set
|
||||
# CONFIG_SAMA5_HAVE_TC1 is not set
|
||||
# CONFIG_ARCH_CHIP_ATSAMA5D31 is not set
|
||||
|
||||
@ -128,7 +128,7 @@ CONFIG_ARMV7A_TOOLCHAIN_CODESOURCERYW=y
|
||||
# CONFIG_SAMA5_HAVE_CAN1 is not set
|
||||
CONFIG_SAMA5_HAVE_LCDC=y
|
||||
CONFIG_SAMA5_HAVE_GMAC=y
|
||||
# CONFIG_SAMA5_HAVE_EMAC is not set
|
||||
# CONFIG_SAMA5_HAVE_EMAC0 is not set
|
||||
# CONFIG_SAMA5_HAVE_HSMCI2 is not set
|
||||
# CONFIG_SAMA5_HAVE_TC1 is not set
|
||||
# CONFIG_ARCH_CHIP_ATSAMA5D31 is not set
|
||||
|
||||
@ -128,7 +128,7 @@ CONFIG_ARMV7A_TOOLCHAIN_CODESOURCERYW=y
|
||||
# CONFIG_SAMA5_HAVE_CAN1 is not set
|
||||
CONFIG_SAMA5_HAVE_LCDC=y
|
||||
CONFIG_SAMA5_HAVE_GMAC=y
|
||||
# CONFIG_SAMA5_HAVE_EMAC is not set
|
||||
# CONFIG_SAMA5_HAVE_EMAC0 is not set
|
||||
# CONFIG_SAMA5_HAVE_HSMCI2 is not set
|
||||
# CONFIG_SAMA5_HAVE_TC1 is not set
|
||||
# CONFIG_ARCH_CHIP_ATSAMA5D31 is not set
|
||||
|
||||
@ -128,7 +128,7 @@ CONFIG_ARMV7A_TOOLCHAIN_CODESOURCERYW=y
|
||||
# CONFIG_SAMA5_HAVE_CAN1 is not set
|
||||
CONFIG_SAMA5_HAVE_LCDC=y
|
||||
CONFIG_SAMA5_HAVE_GMAC=y
|
||||
# CONFIG_SAMA5_HAVE_EMAC is not set
|
||||
# CONFIG_SAMA5_HAVE_EMAC0 is not set
|
||||
# CONFIG_SAMA5_HAVE_HSMCI2 is not set
|
||||
# CONFIG_SAMA5_HAVE_TC1 is not set
|
||||
# CONFIG_ARCH_CHIP_ATSAMA5D31 is not set
|
||||
|
||||
@ -128,7 +128,7 @@ CONFIG_ARMV7A_TOOLCHAIN_CODESOURCERYW=y
|
||||
# CONFIG_SAMA5_HAVE_CAN1 is not set
|
||||
CONFIG_SAMA5_HAVE_LCDC=y
|
||||
CONFIG_SAMA5_HAVE_GMAC=y
|
||||
# CONFIG_SAMA5_HAVE_EMAC is not set
|
||||
# CONFIG_SAMA5_HAVE_EMAC0 is not set
|
||||
# CONFIG_SAMA5_HAVE_HSMCI2 is not set
|
||||
# CONFIG_SAMA5_HAVE_TC1 is not set
|
||||
# CONFIG_ARCH_CHIP_ATSAMA5D31 is not set
|
||||
|
||||
@ -122,28 +122,54 @@ CONFIG_ARMV7A_TOOLCHAIN_CODESOURCERYW=y
|
||||
#
|
||||
# SAMA5 Configuration Options
|
||||
#
|
||||
CONFIG_SAMA5_HAVE_AESB=y
|
||||
CONFIG_SAMA5_HAVE_ICM=y
|
||||
CONFIG_SAMA5_HAVE_UART0=y
|
||||
CONFIG_SAMA5_HAVE_UART1=y
|
||||
CONFIG_SAMA5_HAVE_CAN0=y
|
||||
CONFIG_SAMA5_HAVE_CAN1=y
|
||||
CONFIG_SAMA5_HAVE_USART4=y
|
||||
# CONFIG_SAMA5_HAVE_CAN0 is not set
|
||||
# CONFIG_SAMA5_HAVE_CAN1 is not set
|
||||
# CONFIG_SAMA5_HAVE_DMA is not set
|
||||
CONFIG_SAMA5_HAVE_DDR32=y
|
||||
CONFIG_SAMA5_HAVE_XDMA=y
|
||||
CONFIG_SAMA5_HAVE_L2CC=y
|
||||
CONFIG_SAMA5_HAVE_LCDC=y
|
||||
CONFIG_SAMA5_HAVE_GMAC=y
|
||||
CONFIG_SAMA5_HAVE_EMAC=y
|
||||
CONFIG_SAMA5_HAVE_HSMCI2=y
|
||||
# CONFIG_SAMA5_HAVE_GMAC is not set
|
||||
CONFIG_SAMA5_HAVE_EMAC0=y
|
||||
CONFIG_SAMA5_HAVE_EMAC1=y
|
||||
# CONFIG_SAMA5_HAVE_HSMCI2 is not set
|
||||
CONFIG_SAMA5_HAVE_SAIC=y
|
||||
CONFIG_SAMA5_HAVE_SBM=y
|
||||
CONFIG_SAMA5_HAVE_SFC=y
|
||||
CONFIG_SAMA5_HAVE_SPI2=y
|
||||
CONFIG_SAMA5_HAVE_TC1=y
|
||||
CONFIG_SAMA5_HAVE_TC2=y
|
||||
CONFIG_SAMA5_HAVE_TWI3=y
|
||||
CONFIG_SAMA5_HAVE_VDEC=y
|
||||
# CONFIG_ARCH_CHIP_SAMA5D3 is not set
|
||||
CONFIG_ARCH_CHIP_SAMA5D4=y
|
||||
# CONFIG_ARCH_CHIP_ATSAMA5D31 is not set
|
||||
# CONFIG_ARCH_CHIP_ATSAMA5D33 is not set
|
||||
# CONFIG_ARCH_CHIP_ATSAMA5D34 is not set
|
||||
# CONFIG_ARCH_CHIP_ATSAMA5D35 is not set
|
||||
# CONFIG_ARCH_CHIP_ATSAMA5D36 is not set
|
||||
# CONFIG_ARCH_CHIP_ATSAMA5D41 is not set
|
||||
# CONFIG_ARCH_CHIP_ATSAMA5D42 is not set
|
||||
# CONFIG_ARCH_CHIP_ATSAMA5D43 is not set
|
||||
CONFIG_ARCH_CHIP_ATSAMA5D44=y
|
||||
|
||||
#
|
||||
# SAMA5 Peripheral Support
|
||||
#
|
||||
# CONFIG_SAMA5_AES is not set
|
||||
# CONFIG_SAMA5_TDES is not set
|
||||
# CONFIG_SAMA5_AESB is not set
|
||||
CONFIG_SAMA5_DBGU=y
|
||||
# CONFIG_SAMA5_L2CC is not set
|
||||
# CONFIG_SAMA5_PIT is not set
|
||||
# CONFIG_SAMA5_WDT is not set
|
||||
# CONFIG_SAMA5_RTC is not set
|
||||
# CONFIG_SAMA5_ICM is not set
|
||||
CONFIG_SAMA5_HSMC=y
|
||||
# CONFIG_SAMA5_SMD is not set
|
||||
# CONFIG_SAMA5_UART0 is not set
|
||||
@ -152,35 +178,37 @@ CONFIG_SAMA5_HSMC=y
|
||||
# CONFIG_SAMA5_USART1 is not set
|
||||
# CONFIG_SAMA5_USART2 is not set
|
||||
# CONFIG_SAMA5_USART3 is not set
|
||||
# CONFIG_SAMA5_USART4 is not set
|
||||
# CONFIG_SAMA5_TWI0 is not set
|
||||
# CONFIG_SAMA5_TWI1 is not set
|
||||
# CONFIG_SAMA5_TWI2 is not set
|
||||
# CONFIG_SAMA5_TWI3 is not set
|
||||
# CONFIG_SAMA5_HSMCI0 is not set
|
||||
# CONFIG_SAMA5_HSMCI1 is not set
|
||||
# CONFIG_SAMA5_HSMCI2 is not set
|
||||
# CONFIG_SAMA5_SAIC is not set
|
||||
# CONFIG_SAMA5_SBM is not set
|
||||
# CONFIG_SAMA5_SFC is not set
|
||||
# CONFIG_SAMA5_SPI0 is not set
|
||||
# CONFIG_SAMA5_SPI1 is not set
|
||||
# CONFIG_SAMA5_SPI2 is not set
|
||||
# CONFIG_SAMA5_TC0 is not set
|
||||
# CONFIG_SAMA5_TC1 is not set
|
||||
# CONFIG_SAMA5_TC2 is not set
|
||||
# CONFIG_SAMA5_PWM is not set
|
||||
# CONFIG_SAMA5_ADC is not set
|
||||
# CONFIG_SAMA5_DMAC0 is not set
|
||||
# CONFIG_SAMA5_DMAC1 is not set
|
||||
# CONFIG_SAMA5_XDMAC is not set
|
||||
# CONFIG_SAMA5_UHPHS is not set
|
||||
# CONFIG_SAMA5_UDPHS is not set
|
||||
# CONFIG_SAMA5_GMAC is not set
|
||||
# CONFIG_SAMA5_EMAC0 is not set
|
||||
# CONFIG_SAMA5_EMAC1 is not set
|
||||
# CONFIG_SAMA5_LCDC is not set
|
||||
# CONFIG_SAMA5_ISI is not set
|
||||
# CONFIG_SAMA5_CAN0 is not set
|
||||
# CONFIG_SAMA5_CAN1 is not set
|
||||
# CONFIG_SAMA5_SHA is not set
|
||||
# CONFIG_SAMA5_AES is not set
|
||||
# CONFIG_SAMA5_TDES is not set
|
||||
# CONFIG_SAMA5_TRNG is not set
|
||||
# CONFIG_SAMA5_ARM is not set
|
||||
# CONFIG_SAMA5_FUSE is not set
|
||||
# CONFIG_SAMA5_MPDDRC is not set
|
||||
# CONFIG_SAMA5_VDEC is not set
|
||||
# CONFIG_SAMA5_PIO_IRQ is not set
|
||||
|
||||
#
|
||||
@ -220,6 +248,7 @@ CONFIG_ARCH_HAVE_IRQPRIO=y
|
||||
CONFIG_ARCH_HAVE_VFORK=y
|
||||
CONFIG_ARCH_HAVE_MMU=y
|
||||
CONFIG_ARCH_NAND_HWECC=y
|
||||
# CONFIG_ARCH_HAVE_EXTCLK is not set
|
||||
# CONFIG_PAGING is not set
|
||||
# CONFIG_ARCH_IRQPRIO is not set
|
||||
CONFIG_ARCH_STACKDUMP=y
|
||||
@ -389,6 +418,7 @@ CONFIG_DEV_NULL=y
|
||||
# CONFIG_I2S is not set
|
||||
# CONFIG_RTC is not set
|
||||
# CONFIG_WATCHDOG is not set
|
||||
# CONFIG_TIMER is not set
|
||||
# CONFIG_ANALOG is not set
|
||||
# CONFIG_AUDIO_DEVICES is not set
|
||||
# CONFIG_VIDEO_DEVICES is not set
|
||||
@ -576,6 +606,7 @@ CONFIG_BUILTIN_PROXY_STACKSIZE=1024
|
||||
# CONFIG_EXAMPLES_BUTTONS is not set
|
||||
# CONFIG_EXAMPLES_CAN is not set
|
||||
# CONFIG_EXAMPLES_CONFIGDATA is not set
|
||||
# CONFIG_EXAMPLES_CPUHOG is not set
|
||||
# CONFIG_EXAMPLES_CXXTEST is not set
|
||||
# CONFIG_EXAMPLES_DHCPD is not set
|
||||
# CONFIG_EXAMPLES_ELF is not set
|
||||
@ -603,13 +634,14 @@ CONFIG_EXAMPLES_NSH_CXXINITIALIZE=y
|
||||
# CONFIG_EXAMPLES_NXLINES is not set
|
||||
# CONFIG_EXAMPLES_NXTEXT is not set
|
||||
# CONFIG_EXAMPLES_OSTEST is not set
|
||||
# CONFIG_EXAMPLES_PASHELLO is not set
|
||||
# CONFIG_EXAMPLES_PIPE is not set
|
||||
# CONFIG_EXAMPLES_POSIXSPAWN is not set
|
||||
# CONFIG_EXAMPLES_QENCODER is not set
|
||||
# CONFIG_EXAMPLES_RGMP is not set
|
||||
# CONFIG_EXAMPLES_ROMFS is not set
|
||||
# CONFIG_EXAMPLES_SENDMAIL is not set
|
||||
# CONFIG_EXAMPLES_SERIALBLASTER is not set
|
||||
# CONFIG_EXAMPLES_SERIALRX is not set
|
||||
# CONFIG_EXAMPLES_SERLOOP is not set
|
||||
# CONFIG_EXAMPLES_SLCD is not set
|
||||
# CONFIG_EXAMPLES_SMART_TEST is not set
|
||||
@ -794,6 +826,10 @@ CONFIG_NSH_CONSOLE=y
|
||||
CONFIG_SYSTEM_READLINE=y
|
||||
CONFIG_READLINE_ECHO=y
|
||||
|
||||
#
|
||||
# P-Code Support
|
||||
#
|
||||
|
||||
#
|
||||
# Power Off
|
||||
#
|
||||
|
||||
Loading…
Reference in New Issue
Block a user