From 87f893887d57f611568e225be88ec938c046d6e1 Mon Sep 17 00:00:00 2001 From: Gregory Nutt Date: Mon, 23 Feb 2015 16:36:35 -0600 Subject: [PATCH] PIC32MZ: Most related to start up file a FLASH device configuration setup --- arch/mips/src/pic32mz/Kconfig | 466 ++-------- .../src/pic32mz/chip/pic32mzec-features.h | 46 +- arch/mips/src/pic32mz/pic32mz-config.h | 803 ++++-------------- arch/mips/src/pic32mz/pic32mz-head.S | 141 +-- configs/pic32mz-starterkit/include/board.h | 43 +- configs/pic32mz-starterkit/nsh/defconfig | 35 +- .../pic32mz-starterkit/scripts/c32-release.ld | 11 +- .../scripts/mips-release.ld | 11 +- 8 files changed, 374 insertions(+), 1182 deletions(-) diff --git a/arch/mips/src/pic32mz/Kconfig b/arch/mips/src/pic32mz/Kconfig index 8f9cf676bd..fe65330343 100644 --- a/arch/mips/src/pic32mz/Kconfig +++ b/arch/mips/src/pic32mz/Kconfig @@ -15,7 +15,6 @@ config ARCH_CHIP_PIC32MZ2048ECH select ARCH_CHIP_PIC32MZEC ---help--- Microchip PIC32MZ2048ECH (MIPS32) - ARCH_CHIP_PIC32MZ1 config ARCH_CHIP_PIC32MZ2048ECM bool "PIC32MZ2048ECH" @@ -233,344 +232,6 @@ config PIC32MZ_CTMU endmenu -menu "PIC32MZ Peripheral Interrupt Priorities" - -config PIC32MZ_CTPRIO - int "Core Timer Interrupt (CT)" - default 16 - ---help--- - Core Timer Interrupt. Range 4-31, Default 16. - -config PIC32MZ_CS0PRIO - int "Core Software Interrupt 0 (CS0)" - default 16 - ---help--- - Core Software Interrupt 0. Range 4-31, Default 16. - -config PIC32MZ_CS1PRIO - int "Core Software Interrupt 1 (CS1)" - default 16 - ---help--- - Core Software Interrupt 1. Range 4-31, Default 16. - -config PIC32MZ_INT0PRIO - int "External Interrupt 0 (INT0)" - default 16 - ---help--- - External Interrupt 0. Range 4-31, Default 16. - -config PIC32MZ_INT1PRIO - int "External Interrupt 1 (INT1)" - default 16 - ---help--- - External Interrupt 1. Range 4-31, Default 16. - -config PIC32MZ_INT2PRIO - int "External Interrupt 2 (INT2)" - default 16 - ---help--- - External Interrupt 2. Range 4-31, Default 16. - -config PIC32MZ_INT3PRIO - int "External Interrupt 3 (INT3)" - default 16 - ---help--- - External Interrupt 3. Range 4-31, Default 16. - -config PIC32MZ_INT4PRIO - int "External Interrupt 4 (INT4)" - default 16 - ---help--- - External Interrupt 4. Range 4-31, Default 16. - -config PIC32MZ_FSCMPRIO - int "Fail-Safe Clock Monitor (FSCM)" - default 16 - depends on PIC32MZ_ - ---help--- - Fail-Safe Clock Monitor. Range 4-31, Default 16. - -config PIC32MZ_T1PRIO - int "Timer 1 (T1)" - default 16 - ---help--- - Timer 1 (System timer) priority. Range 4-31, Default 16. - -config PIC32MZ_T2PRIO - int "Timer 2 (T2)" - default 16 - depends on PIC32MZ_T2 - ---help--- - Timer 2 priority. Range 4-31, Default 16. - -config PIC32MZ_T3PRIO - int "Timer 3 (T3)" - default 16 - depends on PIC32MZ_T3 - ---help--- - Timer 3 priority. Range 4-31, Default 16. - -config PIC32MZ_T4PRIO - int "Timer 4 (T4)" - default 16 - depends on PIC32MZ_T4 - ---help--- - Timer 4 priority. Range 4-31, Default 16. - -config PIC32MZ_T5PRIO - int "Timer 5 (T5)" - default 16 - depends on PIC32MZ_ - ---help--- - Timer 5 priority. Range 4-31, Default 16. - -config PIC32MZ_IC1PRIO - int "Input Capture 1 (IC1)" - default 16 - depends on PIC32MZ_IC1 - ---help--- - Input Capture 1. Range 4-31, Default 16. - -config PIC32MZ_IC2PRIO - int "Input Capture 2 (IC2)" - default 16 - depends on PIC32MZ_IC2 - ---help--- - Input Capture 2. Range 4-31, Default 16. - -config PIC32MZ_IC3PRIO - int "Input Capture 3 (IC3)" - default 16 - depends on PIC32MZ_IC3 - ---help--- - Input Capture 3. Range 4-31, Default 16. - -config PIC32MZ_IC4PRIO - int "Input Capture 4 (IC4)" - default 16 - depends on PIC32MZ_IC4 - ---help--- - Input Capture 4. Range 4-31, Default 16. - -config PIC32MZ_IC5PRIO - int "Input Capture 5 (IC5)" - default 16 - depends on PIC32MZ_IC5 - ---help--- - Input Capture 5. Range 4-31, Default 16. - -config PIC32MZ_OC1PRIO - int "Output Compare 1 (OC1)" - default 16 - depends on PIC32MZ_OC1 - ---help--- - Output Compare 1. Range 4-31, Default 16. - -config PIC32MZ_OC2PRIO - int "Output Compare 2 (OC2)" - default 16 - depends on PIC32MZ_OC2 - ---help--- - Output Compare 2. Range 4-31, Default 16. - -config PIC32MZ_OC3PRIO - int "Output Compare 3 (OC3)" - default 16 - depends on PIC32MZ_OC3 - ---help--- - Output Compare 3. Range 4-31, Default 16. - -config PIC32MZ_OC4PRIO - int "Output Compare 4 (OC4)" - default 16 - depends on PIC32MZ_OC4 - ---help--- - Output Compare 4. Range 4-31, Default 16. - -config PIC32MZ_OC5PRIO - int "Output Compare 5 (OC5)" - default 16 - depends on PIC32MZ_OC5 - ---help--- - Output Compare 5. Range 4-31, Default 16. - -config PIC32MZ_I2C1PRIO - int "I2C1" - default 16 - depends on PIC32MZ_I2C1 - ---help--- - I2C 1. Range 4-31, Default 16. - -config PIC32MZ_I2C2PRIO - int "I2C2" - default 16 - depends on PIC32MZ_I2C3 - ---help--- - I2C 2. Range 4-31, Default 16. - -config PIC32MZ_I2C3PRIO - int "I2C3" - default 16 - depends on PIC32MZ_I2C3 - ---help--- - I2C 3. Range 4-31, Default 16. - -config PIC32MZ_I2C4PRIO - int "I2C4" - default 16 - depends on PIC32MZ_I2C4 - ---help--- - I2C 4. Range 4-31, Default 16. - -config PIC32MZ_I2C5PRIO - int "I2C5" - default 16 - depends on PIC32MZ_I2C5 - ---help--- - I2C 5. Range 4-31, Default 16. - -config PIC32MZ_SPI1PRIO - int "SPI1" - default 16 - depends on PIC32MZ_SPI1 - ---help--- - SPI 2 - -config PIC32MZ_SPI2PRIO - int "SPI2" - default 16 - depends on PIC32MZ_SPI2 - ---help--- - SPI 2 - -config PIC32MZ_UART1PRIO - int "UART1" - default 16 - depends on PIC32MZ_UART1 - ---help--- - UART 1. Range 4-31, Default 16. - -config PIC32MZ_UART2PRIO - int "UART2" - default 16 - depends on PIC32MZ_UART2 - ---help--- - UART 2. Range 4-31, Default 16. - -config PIC32MZ_CNPRIO - int "CN" - default 16 - depends on PIC32MZ_CN - ---help--- - Input Change Interrupt. Range 4-31, Default 16. - -config PIC32MZ_ADCPRIO - int "ADC1" - default 16 - depends on PIC32MZ_ADC1 - ---help--- - ADC1 Convert Done. Range 4-31, Default 16. - -config PIC32MZ_PMPPRIO - int "Parallel Master Port (PMP)" - default 16 - depends on PIC32MZ_PMP - ---help--- - Parallel Master Port. Range 4-31, Default 16. - -config PIC32MZ_CM1PRIO - int "Comparator 1 (CM1)" - default 16 - depends on PIC32MZ_CM1 - ---help--- - Comparator 1. Range 4-31, Default 16. - -config PIC32MZ_CM2PRIO - int "Comparator 2 (CM2)" - default 16 - depends on PIC32MZ_CM2 - ---help--- - Comparator 2. Range 4-31, Default 16. - -config PIC32MZ_RTCCPRIO - int "Real-Time Clock and Calendar (RTCC)" - default 16 - depends on PIC32MZ_RTCC - ---help--- - Real-Time Clock and Calendar. Range 4-31, Default 16. - -config PIC32MZ_DMA0PRIO - int "DMA0" - default 16 - depends on PIC32MZ_DMA - ---help--- - DMA Channel 0. Range 4-31, Default 16. - -config PIC32MZ_DMA1PRIO - int "DMA1" - default 16 - depends on PIC32MZ_DMA - ---help--- - DMA Channel 1. Range 4-31, Default 16. - -config PIC32MZ_DMA2PRIO - int "DMA2" - default 16 - depends on PIC32MZ_DMA - ---help--- - DMA Channel 2. Range 4-31, Default 16. - -config PIC32MZ_DMA3PRIO - int "DMA3" - default 16 - depends on PIC32MZ_DMA - ---help--- - DMA Channel 3. Range 4-31, Default 16. - -config PIC32MZ_DMA4PRIO - int "DMA4" - default 16 - depends on PIC32MZ_DMA - ---help--- - DMA Channel 4. Range 4-31, Default 16. - -config PIC32MZ_DMA5PRIO - int "DMA5" - default 16 - depends on PIC32MZ_DMA - ---help--- - DMA Channel 5. Range 4-31, Default 16. - -config PIC32MZ_DMA6PRIO - int "DMA6" - default 16 - depends on PIC32MZ_DMA - ---help--- - DMA Channel 6. Range 4-31, Default 16. - -config PIC32MZ_DMA7PRIO - int "DMA7" - default 16 - depends on PIC32MZ_DMA - ---help--- - DMA Channel 7. Range 4-31, Default 16. - -config PIC32MZ_FCEPRIO - int "FCE" - default 16 - depends on PIC32MZ_FLASH - ---help--- - Flash Control Event. Range 4-31, Default 16. - -config PIC32MZ_USBPRIO - int "USB" - default 16 - depends on PIC32MZ_USBDEV || PIC32MZ_USBHOST - ---help--- - USB. Range 4-31, Default 16. - -endmenu - menu "PIC32MZ PHY/Ethernet device driver settings" depends on PIC32MZ_ETHERNET @@ -649,93 +310,100 @@ endmenu menu "Device Configuration 0 (DEVCFG0)" -config PIC32MZ_DEBUGGER - int "Debugger" - default 3 +config PIC32MZ_DEBUGGER_ENABLE + bool "Background debugger enable" + default n ---help--- - Background Debugger Enable. Default 3 (disabled). The value 2 enables. + Background Debugger Enable -config PIC32MZ_ICESEL - int "ICE channel" - default 1 +config PIC32MZ_JTAG_ENABLE + bool "JTAG enable" + default y ---help--- - In-Circuit Emulator/Debugger Communication Channel Select. Default 1 (PG2) + JTAG Enable -config PIC32MZ_PROGFLASHWP - hex "Program FLASH write protect" - default 0x3ff if ARCH_CHIP_PIC32MZ1 || ARCH_CHIP_PIC32MZ2 - default 0xff if !ARCH_CHIP_PIC32MZ1 && !ARCH_CHIP_PIC32MZ2 +config PIC32MZ_ICESEL_CH2 + bool "ICE channel 2" + default n ---help--- - Program FLASH write protect. Default 0xff (disabled) + In-Circuit Emulator/Debugger Communication Channel Select. Default: Channel (PG2) -config PIC32MZ_BOOTFLASHWP - int "Boot FLASH write protect" - default 1 +config PIC32MZ_TRACE_ENABLE + bool "Trace enable" + default n ---help--- - Default 1 (disabled) - -config PIC32MZ_CODEWP - int "Code write protect" - default 1 - ---help--- - Default 1 (disabled) + Trace Enable endmenu menu "Device Configuration 1 (DEVCFG1)" -config PIC32MZ_OSCOUT - int "USB ID" +config CONFIG_PIC32MZ_OSCIOFNC + int "CLKO Enable" default 0 - depends on ARCH_CHIP_PIC32MZ1 || ARCH_CHIP_PIC32MZ2 + range 0 1 + +config PIC32MZ_WDTENABLE + bool "Watchdog enable" + default 0 + range 0 1 ---help--- - USB USBID Selection. Default 1 if USB enabled (USBID pin is controlled by the USB - module), but 0 (GPIO) otherwise. + Enabled watchdog on power up. Default 0 (watchdog can be enabled later by software). endmenu menu "Device Configuration 3 (DEVCFG3)" -config PIC32MZ_USBIDO - int "USB ID" - default 1 if PIC32MZ_USB - default 0 if !PIC32MZ_USB +config PIC32MZ_USERID + hex "User ID" + default 0x584e ---help--- - USB USBID Selection. Default 1 if USB enabled (USBID pin is controlled by the USB - module), but 0 (GPIO) otherwise. - -config PIC32MZ_VBUSIO - int "USB VBUSON" - default 1 if PIC32MZ_USB - default 0 if !PIC32MZ_USB - ---help--- - USB VBUSON Selection (Default 1 if USB enabled (VBUSON pin is controlled by the USB - module, but 0 (GPIO) otherwise. - -config PIC32MZ_WDENABLE - bool "Watchdog enable" - default 0 - ---help--- - Enabled watchdog on power up. Default 0 (watchdog can be enabled later by software). - -config PIC32MZ_FETHIO - int "Ethernet I/O pins" - default 1 - ---help--- - Ethernet I/O Pin Selection bit: - - 1 = Default Ethernet I/O Pins - 0 = Alternate Ethernet I/O Pins + User-provided ID visible in DEVCFG3 config PIC32MZ_FMIIEN int "Ethernet MII" default 1 + range 0 1 ---help--- - Ethernet MII Enable bit + Ethernet MII enable selection - 1 = MII enabled 0 = RMII enabled + 1 = MII enabled + +config PIC32MZ_PGL1WAY + int + default 0 + range 0 1 + +config PIC32MZ_PMDL1WAY + int + default 0 + range 0 1 + +config PIC32MZ_IOL1WAY + int + default 0 + range 0 1 + +config PIC32MZ_FETHIO + int "Ethernet I/O pins" + default 1 + range 0 1 + ---help--- + Ethernet I/O pin selection + + 0 = Alternate Ethernet I/O pins + 1 = Default Ethernet I/O pins + +config PIC32MZ_FUSBIDIO + int "USB USBID selection" + default 1 + range 0 1 + ---help--- + USB USBID selection + + 0 = USBID pin is controlled by the port function + 1 = USBID pin is controlled by the USB module endmenu - endif diff --git a/arch/mips/src/pic32mz/chip/pic32mzec-features.h b/arch/mips/src/pic32mz/chip/pic32mzec-features.h index 1863e69eac..83aa92cd2d 100644 --- a/arch/mips/src/pic32mz/chip/pic32mzec-features.h +++ b/arch/mips/src/pic32mz/chip/pic32mzec-features.h @@ -203,20 +203,20 @@ # define CFGEBIA_EBIA7EN (1 << 7) /* Bit 7: EBI address pin 7 enable */ # define CFGEBIA_EBIA8EN (1 << 8) /* Bit 8: EBI address pin 8 enable */ # define CFGEBIA_EBIA9EN (1 << 9) /* Bit 9: EBI address pin 9 enable */ -# define CFGEBIA_EBIA0EN (1 << 10) /* Bit 10: EBI address pin 10 enable */ -# define CFGEBIA_EBIA1EN (1 << 11) /* Bit 11: EBI address pin 11 enable */ -# define CFGEBIA_EBIA2EN (1 << 12) /* Bit 12: EBI address pin 12 enable */ -# define CFGEBIA_EBIA3EN (1 << 13) /* Bit 13: EBI address pin 13 enable */ -# define CFGEBIA_EBIA4EN (1 << 14) /* Bit 14: EBI address pin 14 enable */ -# define CFGEBIA_EBIA5EN (1 << 15) /* Bit 15: EBI address pin 15 enable */ -# define CFGEBIA_EBIA6EN (1 << 16) /* Bit 16: EBI address pin 16 enable */ -# define CFGEBIA_EBIA7EN (1 << 17) /* Bit 17: EBI address pin 17 enable */ -# define CFGEBIA_EBIA8EN (1 << 18) /* Bit 18: EBI address pin 18 enable */ -# define CFGEBIA_EBIA9EN (1 << 19) /* Bit 19: EBI address pin 19 enable */ -# define CFGEBIA_EBIA0EN (1 << 20) /* Bit 20: EBI address pin 20 enable */ -# define CFGEBIA_EBIA1EN (1 << 21) /* Bit 21: EBI address pin 21 enable */ -# define CFGEBIA_EBIA2EN (1 << 22) /* Bit 22: EBI address pin 22 enable */ -# define CFGEBIA_EBIA3EN (1 << 23) /* Bit 23: EBI address pin 23 enable */ +# define CFGEBIA_EBIA10EN (1 << 10) /* Bit 10: EBI address pin 10 enable */ +# define CFGEBIA_EBIA11EN (1 << 11) /* Bit 11: EBI address pin 11 enable */ +# define CFGEBIA_EBIA12EN (1 << 12) /* Bit 12: EBI address pin 12 enable */ +# define CFGEBIA_EBIA13EN (1 << 13) /* Bit 13: EBI address pin 13 enable */ +# define CFGEBIA_EBIA14EN (1 << 14) /* Bit 14: EBI address pin 14 enable */ +# define CFGEBIA_EBIA15EN (1 << 15) /* Bit 15: EBI address pin 15 enable */ +# define CFGEBIA_EBIA16EN (1 << 16) /* Bit 16: EBI address pin 16 enable */ +# define CFGEBIA_EBIA17EN (1 << 17) /* Bit 17: EBI address pin 17 enable */ +# define CFGEBIA_EBIA18EN (1 << 18) /* Bit 18: EBI address pin 18 enable */ +# define CFGEBIA_EBIA19EN (1 << 19) /* Bit 19: EBI address pin 19 enable */ +# define CFGEBIA_EBIA20EN (1 << 20) /* Bit 20: EBI address pin 20 enable */ +# define CFGEBIA_EBIA21EN (1 << 21) /* Bit 21: EBI address pin 21 enable */ +# define CFGEBIA_EBIA22EN (1 << 22) /* Bit 22: EBI address pin 22 enable */ +# define CFGEBIA_EBIA23EN (1 << 23) /* Bit 23: EBI address pin 23 enable */ #define CFGEBIA_EBIPINEN (1 << 31) /* Bit 31: EBI Pin Enable bit */ /* External bus interface address pin control register */ @@ -308,11 +308,17 @@ #define DEVCFG3_USERID_SHIFT (0) /* Bit 0-15: 16-bit user defined value */ #define DEVCFG3_USERID_MASK (0xffff << DEVCFG3_USERID_SHIFT) # define DEVCFG3_USERID(n) ((uint32_t)(n) << DEVCFG3_USERID_SHIFT) +#define DEVCFG3_FMIIEN_SHIFT (24) /* Bit 24: Ethernet MII Enable Configuration bit */ #define DEVCFG3_FMIIEN (1 << 24) /* Bit 24: Ethernet MII Enable Configuration bit */ +#define DEVCFG3_FETHIO_SHIFT (25) /* Bit 25: Ethernet I/O Pin Selection Configuration bit */ #define DEVCFG3_FETHIO (1 << 25) /* Bit 25: Ethernet I/O Pin Selection Configuration bit */ +#define DEVCFG3_PGL1WAY_SHIFT (27) /* Bit 27: Permission Group Lock One Way Configuration bit */ #define DEVCFG3_PGL1WAY (1 << 27) /* Bit 27: Permission Group Lock One Way Configuration bit */ +#define DEVCFG3_PMDL1WAY_SHIFT (28) /* Bit 28: Peripheral Module Disable Configuration bit */ #define DEVCFG3_PMDL1WAY (1 << 28) /* Bit 28: Peripheral Module Disable Configuration bit */ +#define DEVCFG3_IOL1WAY_SHIFT (29) /* Bit 29: Peripheral Pin Select Configuration bit */ #define DEVCFG3_IOL1WAY (1 << 29) /* Bit 29: Peripheral Pin Select Configuration bit */ +#define DEVCFG3_FUSBIDIO_SHIFT (30) /* Bit 30: USB USBID Selection bit */ #define DEVCFG3_FUSBIDIO (1 << 30) /* Bit 30: USB USBID Selection bit */ #define DEVCFG3_RWO 0x84ff0000 /* Bits 16-23, 31: Reserved, write as one */ @@ -357,12 +363,12 @@ #define DEVCFG1_FNOSC_SHIFT (0) /* Bits 0-2: Oscillator Selection bits */ #define DEVCFG1_FNOSC_MASK (7 << DEVCFG1_FNOSC_SHIFT) -# define DEVCFG1_FNOSC_FRCDIV (0 << DEVCFG1_FNOSC_SHIFT) /* FRC divided by FRCDIV */ +# define DEVCFG1_FNOSC_FRC (0 << DEVCFG1_FNOSC_SHIFT) /* FRC divided by FRCDIV */ # define DEVCFG1_FNOSC_SPLL (1 << DEVCFG1_FNOSC_SHIFT) /* SPLL */ # define DEVCFG1_FNOSC_POSC (2 << DEVCFG1_FNOSC_SHIFT) /* POSC (HS, EC) */ # define DEVCFG1_FNOSC_SOSC (4 << DEVCFG1_FNOSC_SHIFT) /* SOSC */ # define DEVCFG1_FNOSC_LPRC (5 << DEVCFG1_FNOSC_SHIFT) /* LPRC */ -# define DEVCFG1_FNOSC_FRCDIV20 (7 << DEVCFG1_FNOSC_SHIFT) /* FRC divided by FRCDIV<2:0> */ +# define DEVCFG1_FNOSC_FRCDIV (7 << DEVCFG1_FNOSC_SHIFT) /* FRC divided by FRCDIV<2:0> */ #define DEVCFG1_DMTINV_SHIFT (3) /* Bits 3-5: Deadman Timer Count Window Interval bits */ #define DEVCFG1_DMTINV_MASK (7 << DEVCFG1_DMTINV_SHIFT) # define DEVCFG1_DMTINV_0 (0 << DEVCFG1_DMTINV_SHIFT) /* Window/Interval value zero */ @@ -410,9 +416,9 @@ # define DEVCFG1_WDTPS_262144 (18 << DEVCFG1_WDTPS_SHIFT) /* 1:262144 */ # define DEVCFG1_WDTPS_524288 (19 << DEVCFG1_WDTPS_SHIFT) /* 1:524288 */ # define DEVCFG1_WDTPS_1048576 (20 << DEVCFG1_WDTPS_SHIFT) /* 1:1048576 */ -#define DEVCFG1_WDTSPGM (1 << 21) /* Bit 21: Watchdog Timer Stop During Flash Programming bit */ -#define DEVCFG1_WINDIS (1 << 22) /* Bit 22: Watchdog Timer Window Enable bit */ -#define DEVCFG1_FWDTEN (1 << 23) /* Bit 23: Watchdog Timer Enable bit */ +#define DEVCFG1_WDTSPGM (1 << 21) /* Bit 21: Watchdog Timer Stop During Flash Programming bit */ +#define DEVCFG1_WINDIS (1 << 22) /* Bit 22: Watchdog Timer Window Enable bit */ +#define DEVCFG1_FWDTEN (1 << 23) /* Bit 23: Watchdog Timer Enable bit */ #define DEVCFG1_FWDTWINSZ_SHIFT (24) /* Bits 24-25: Watchdog Timer Window Size bits */ #define DEVCFG1_FWDTWINSZ_MASK (3 << DEVCFG1_FWDTWINSZ_SHIFT) # define DEVCFG1_FWDTWINSZ_75 (0 << DEVCFG1_FWDTWINSZ_SHIFT) /* Window size is 75% */ @@ -422,7 +428,7 @@ #define DEVCFG1_DMTCNT_SHIFT (26) /* Bits 26-30: Deadman Timer Count Select bits */ #define DEVCFG1_DMTCNT_MASK (31 << DEVCFG1_DMTCNT_SHIFT) # define DEVCFG1_DMTCNT(n) ((uint32_t)((n)-8) << DEVCFG1_DMTCNT_SHIFT) /* 2**n, n=8..31 */ -#define DEVCFG1_FDMTEN (1 << 31) /* Bit 31: Deadman Timer enable bit */ +#define DEVCFG1_FDMTEN (1 << 31) /* Bit 31: Deadman Timer enable bit */ #define DEVCFG1_RWO 0x00003800 /* Bits 11-13: Reserved, write as one */ diff --git a/arch/mips/src/pic32mz/pic32mz-config.h b/arch/mips/src/pic32mz/pic32mz-config.h index fee8207737..c00062a96b 100644 --- a/arch/mips/src/pic32mz/pic32mz-config.h +++ b/arch/mips/src/pic32mz/pic32mz-config.h @@ -41,458 +41,13 @@ ************************************************************************************/ #include + +#include #include /************************************************************************************ * Pre-processor Definitions ************************************************************************************/ -/* Interrupt Priorities *************************************************************/ - -#ifndef CONFIG_PIC32MZ_CTPRIO /* Core Timer Interrupt */ -# define CONFIG_PIC32MZ_CTPRIO (INT_IPC_MID_PRIORITY << 2) -#endif -#if CONFIG_PIC32MZ_CTPRIO < 4 -# error "CONFIG_PIC32MZ_CTPRIO is too small" -#endif -#if CONFIG_PIC32MZ_CTPRIO > 31 -# error "CONFIG_PIC32MZ_CTPRIO is too large" -#endif - -#ifndef CONFIG_PIC32MZ_CS0PRIO /* Core Software Interrupt 0 */ -# define CONFIG_PIC32MZ_CS0PRIO (INT_IPC_MID_PRIORITY << 2) -#endif -#if CONFIG_PIC32MZ_CS0PRIO < 4 -# error "CONFIG_PIC32MZ_CS0PRIO is too small" -#endif -#if CONFIG_PIC32MZ_CS0PRIO > 31 -# error "CONFIG_PIC32MZ_CS0PRIO is too large" -#endif - -#ifndef CONFIG_PIC32MZ_CS1PRIO /* Core Software Interrupt 1 */ -# define CONFIG_PIC32MZ_CS1PRIO (INT_IPC_MID_PRIORITY << 2) -#endif -#if CONFIG_PIC32MZ_CS1PRIO < 4 -# error "CONFIG_PIC32MZ_CS1PRIO is too small" -#endif -#if CONFIG_PIC32MZ_CS1PRIO > 31 -# error "CONFIG_PIC32MZ_CS1PRIO is too large" -#endif - -#ifndef CONFIG_PIC32MZ_INT0PRIO /* External interrupt 0 */ -# define CONFIG_PIC32MZ_INT0PRIO (INT_IPC_MID_PRIORITY << 2) -#endif -#if CONFIG_PIC32MZ_INT0PRIO < 4 -# error "CONFIG_PIC32MZ_INT0PRIO is too small" -#endif -#if CONFIG_PIC32MZ_INT0PRIO > 31 -# error "CONFIG_PIC32MZ_INT0PRIO is too large" -#endif - -#ifndef CONFIG_PIC32MZ_INT1PRIO /* External interrupt 1 */ -# define CONFIG_PIC32MZ_INT1PRIO (INT_IPC_MID_PRIORITY << 2) -#endif -#if CONFIG_PIC32MZ_INT1PRIO < 4 -# error "CONFIG_PIC32MZ_INT1PRIO is too small" -#endif -#if CONFIG_PIC32MZ_INT1PRIO > 31 -# error "CONFIG_PIC32MZ_INT1PRIO is too large" -#endif - -#ifndef CONFIG_PIC32MZ_INT2PRIO /* External interrupt 2 */ -# define CONFIG_PIC32MZ_INT2PRIO (INT_IPC_MID_PRIORITY << 2) -#endif -#if CONFIG_PIC32MZ_INT2PRIO < 4 -# error "CONFIG_PIC32MZ_INT2PRIO is too small" -#endif -#if CONFIG_PIC32MZ_INT2PRIO > 31 -# error "CONFIG_PIC32MZ_INT2PRIO is too large" -#endif - -#ifndef CONFIG_PIC32MZ_INT3PRIO /* External interrupt 3 */ -# define CONFIG_PIC32MZ_INT3PRIO (INT_IPC_MID_PRIORITY << 2) -#endif -#if CONFIG_PIC32MZ_INT3PRIO < 4 -# error "CONFIG_PIC32MZ_INT3PRIO is too small" -#endif -#if CONFIG_PIC32MZ_INT3PRIO > 31 -# error "CONFIG_PIC32MZ_INT3PRIO is too large" -#endif - -#ifndef CONFIG_PIC32MZ_INT4PRIO /* External interrupt 4 */ -# define CONFIG_PIC32MZ_INT4PRIO (INT_IPC_MID_PRIORITY << 2) -#endif -#if CONFIG_PIC32MZ_INT4PRIO < 4 -# error "CONFIG_PIC32MZ_INT4PRIO is too small" -#endif -#if CONFIG_PIC32MZ_INT4PRIO > 31 -# error "CONFIG_PIC32MZ_INT4PRIO is too large" -#endif - -#ifndef CONFIG_PIC32MZ_FSCMPRIO /* Fail-Safe Clock Monitor */ -# define CONFIG_PIC32MZ_FSCMPRIO (INT_IPC_MID_PRIORITY << 2) -#endif -#if CONFIG_PIC32MZ_FSCMPRIO < 4 -# error "CONFIG_PIC32MZ_FSCMPRIO is too small" -#endif -#if CONFIG_PIC32MZ_FSCMPRIO > 31 -# error "CONFIG_PIC32MZ_FSCMPRIO is too large" -#endif - -#ifndef CONFIG_PIC32MZ_T1PRIO /* Timer 1 (System timer) priority */ -# define CONFIG_PIC32MZ_T1PRIO (INT_IPC_MID_PRIORITY << 2) -#endif -#if CONFIG_PIC32MZ_T1PRIO < 4 -# error "CONFIG_PIC32MZ_T1PRIO is too small" -#endif -#if CONFIG_PIC32MZ_T1PRIO > 31 -# error "CONFIG_PIC32MZ_T1PRIO is too large" -#endif - -#ifndef CONFIG_PIC32MZ_T2PRIO /* Timer 2 priority */ -# define CONFIG_PIC32MZ_T2PRIO (INT_IPC_MID_PRIORITY << 2) -#endif -#if CONFIG_PIC32MZ_T2PRIO < 4 -# error "CONFIG_PIC32MZ_T2PRIO is too small" -#endif -#if CONFIG_PIC32MZ_T2PRIO > 31 -# error "CONFIG_PIC32MZ_T2PRIO is too large" -#endif - -#ifndef CONFIG_PIC32MZ_T3PRIO /* Timer 3 priority */ -# define CONFIG_PIC32MZ_T3PRIO (INT_IPC_MID_PRIORITY << 2) -#endif -#if CONFIG_PIC32MZ_T3PRIO < 4 -# error "CONFIG_PIC32MZ_T3PRIO is too small" -#endif -#if CONFIG_PIC32MZ_T3PRIO > 31 -# error "CONFIG_PIC32MZ_T3PRIO is too large" -#endif - -#ifndef CONFIG_PIC32MZ_T4PRIO /* Timer 4 priority */ -# define CONFIG_PIC32MZ_T4PRIO (INT_IPC_MID_PRIORITY << 2) -#endif -#if CONFIG_PIC32MZ_T4PRIO < 4 -# error "CONFIG_PIC32MZ_T4PRIO is too small" -#endif -#if CONFIG_PIC32MZ_T4PRIO > 31 -# error "CONFIG_PIC32MZ_T4PRIO is too large" -#endif - -#ifndef CONFIG_PIC32MZ_T5PRIO /* Timer 5 priority */ -# define CONFIG_PIC32MZ_T5PRIO (INT_IPC_MID_PRIORITY << 2) -#endif -#if CONFIG_PIC32MZ_T5PRIO < 4 -# error "CONFIG_PIC32MZ_T5PRIO is too small" -#endif -#if CONFIG_PIC32MZ_T5PRIO > 31 -# error "CONFIG_PIC32MZ_T5PRIO is too large" -#endif - -#ifndef CONFIG_PIC32MZ_IC1PRIO /* Input Capture 1 */ -# define CONFIG_PIC32MZ_IC1PRIO (INT_IPC_MID_PRIORITY << 2) -#endif -#if CONFIG_PIC32MZ_IC1PRIO < 4 -# error "CONFIG_PIC32MZ_IC1PRIO is too small" -#endif -#if CONFIG_PIC32MZ_IC1PRIO > 31 -# error "CONFIG_PIC32MZ_IC1PRIO is too large" -#endif - -#ifndef CONFIG_PIC32MZ_IC2PRIO /* Input Capture 2 */ -# define CONFIG_PIC32MZ_IC2PRIO (INT_IPC_MID_PRIORITY << 2) -#endif -#if CONFIG_PIC32MZ_IC2PRIO < 4 -# error "CONFIG_PIC32MZ_IC2PRIO is too small" -#endif -#if CONFIG_PIC32MZ_IC2PRIO > 31 -# error "CONFIG_PIC32MZ_IC2PRIO is too large" -#endif - -#ifndef CONFIG_PIC32MZ_IC3PRIO /* Input Capture 3 */ -# define CONFIG_PIC32MZ_IC3PRIO (INT_IPC_MID_PRIORITY << 2) -#endif -#if CONFIG_PIC32MZ_IC3PRIO < 4 -# error "CONFIG_PIC32MZ_IC3PRIO is too small" -#endif -#if CONFIG_PIC32MZ_IC3PRIO > 31 -# error "CONFIG_PIC32MZ_IC3PRIO is too large" -#endif - -#ifndef CONFIG_PIC32MZ_IC4PRIO /* Input Capture 4 */ -# define CONFIG_PIC32MZ_IC4PRIO (INT_IPC_MID_PRIORITY << 2) -#endif -#if CONFIG_PIC32MZ_IC4PRIO < 4 -# error "CONFIG_PIC32MZ_IC4PRIO is too small" -#endif -#if CONFIG_PIC32MZ_IC4PRIO > 31 -# error "CONFIG_PIC32MZ_IC4PRIO is too large" -#endif - -#ifndef CONFIG_PIC32MZ_IC5PRIO /* Input Capture 5 */ -# define CONFIG_PIC32MZ_IC5PRIO (INT_IPC_MID_PRIORITY << 2) -#endif -#if CONFIG_PIC32MZ_IC5PRIO < 4 -# error "CONFIG_PIC32MZ_IC5PRIO is too small" -#endif -#if CONFIG_PIC32MZ_IC5PRIO > 31 -# error "CONFIG_PIC32MZ_IC5PRIO is too large" -#endif - -#ifndef CONFIG_PIC32MZ_OC1PRIO /* Output Compare 1 */ -# define CONFIG_PIC32MZ_OC1PRIO (INT_IPC_MID_PRIORITY << 2) -#endif -#if CONFIG_PIC32MZ_OC1PRIO < 4 -# error "CONFIG_PIC32MZ_OC1PRIO is too small" -#endif -#if CONFIG_PIC32MZ_OC1PRIO > 31 -# error "CONFIG_PIC32MZ_OC1PRIO is too large" -#endif - -#ifndef CONFIG_PIC32MZ_OC2PRIO /* Output Compare 2 */ -# define CONFIG_PIC32MZ_OC2PRIO (INT_IPC_MID_PRIORITY << 2) -#endif -#if CONFIG_PIC32MZ_OC2PRIO < 4 -# error "CONFIG_PIC32MZ_OC2PRIO is too small" -#endif -#if CONFIG_PIC32MZ_OC2PRIO > 31 -# error "CONFIG_PIC32MZ_OC2PRIO is too large" -#endif - -#ifndef CONFIG_PIC32MZ_OC3PRIO /* Output Compare 3 */ -# define CONFIG_PIC32MZ_OC3PRIO (INT_IPC_MID_PRIORITY << 2) -#endif -#if CONFIG_PIC32MZ_OC3PRIO < 4 -# error "CONFIG_PIC32MZ_OC3PRIO is too small" -#endif -#if CONFIG_PIC32MZ_OC3PRIO > 31 -# error "CONFIG_PIC32MZ_OC3PRIO is too large" -#endif - -#ifndef CONFIG_PIC32MZ_OC4PRIO /* Output Compare 4 */ -# define CONFIG_PIC32MZ_OC4PRIO (INT_IPC_MID_PRIORITY << 2) -#endif -#if CONFIG_PIC32MZ_OC4PRIO < 4 -# error "CONFIG_PIC32MZ_OC4PRIO is too small" -#endif -#if CONFIG_PIC32MZ_OC4PRIO > 31 -# error "CONFIG_PIC32MZ_OC4PRIO is too large" -#endif - -#ifndef CONFIG_PIC32MZ_OC5PRIO /* Output Compare 5 */ -# define CONFIG_PIC32MZ_OC5PRIO (INT_IPC_MID_PRIORITY << 2) -#endif -#if CONFIG_PIC32MZ_OC5PRIO < 4 -# error "CONFIG_PIC32MZ_OC5PRIO is too small" -#endif -#if CONFIG_PIC32MZ_OC5PRIO > 31 -# error "CONFIG_PIC32MZ_OC5PRIO is too large" -#endif - -#ifndef CONFIG_PIC32MZ_I2C1PRIO /* I2C 1 */ -# define CONFIG_PIC32MZ_I2C1PRIO (INT_IPC_MID_PRIORITY << 2) -#endif -#if CONFIG_PIC32MZ_I2C1PRIO < 4 -# error "CONFIG_PIC32MZ_I2C1PRIO is too small" -#endif -#if CONFIG_PIC32MZ_I2C1PRIO > 31 -# error "CONFIG_PIC32MZ_I2C1PRIO is too large" -#endif - -#ifndef CONFIG_PIC32MZ_I2C2PRIO /* I2C 2 */ -# define CONFIG_PIC32MZ_I2C2PRIO (INT_IPC_MID_PRIORITY << 2) -#endif -#if CONFIG_PIC32MZ_I2C2PRIO < 4 -# error "CONFIG_PIC32MZ_I2C2PRIO is too small" -#endif -#if CONFIG_PIC32MZ_I2C2PRIO > 31 -# error "CONFIG_PIC32MZ_I2C2PRIO is too large" -#endif - -#ifndef CONFIG_PIC32MZ_SPI1PRIO /* SPI 1 */ -# define CONFIG_PIC32MZ_SPI1PRIO (INT_IPC_MID_PRIORITY << 2) -#endif -#if CONFIG_PIC32MZ_SPI1PRIO < 4 -# error "CONFIG_PIC32MZ_SPI1PRIO is too small" -#endif -#if CONFIG_PIC32MZ_SPI1PRIO > 31 -# error "CONFIG_PIC32MZ_SPI1PRIO is too large" -#endif - -#ifndef CONFIG_PIC32MZ_SPI2PRIO /* SPI 2 */ -# define CONFIG_PIC32MZ_SPI2PRIO (INT_IPC_MID_PRIORITY << 2) -#endif -#if CONFIG_PIC32MZ_SPI2PRIO < 4 -# error "CONFIG_PIC32MZ_SPI2PRIO is too small" -#endif -#if CONFIG_PIC32MZ_SPI2PRIO > 31 -# error "CONFIG_PIC32MZ_SPI2PRIO is too large" -#endif - -#ifndef CONFIG_PIC32MZ_UART1PRIO /* UART 1 */ -# define CONFIG_PIC32MZ_UART1PRIO (INT_IPC_MID_PRIORITY << 2) -#endif -#if CONFIG_PIC32MZ_UART1PRIO < 4 -# error "CONFIG_PIC32MZ_UART1PRIO is too small" -#endif -#if CONFIG_PIC32MZ_UART1PRIO > 31 -# error "CONFIG_PIC32MZ_UART1PRIO is too large" -#endif - -#ifndef CONFIG_PIC32MZ_UART2PRIO /* UART 2 */ -# define CONFIG_PIC32MZ_UART2PRIO (INT_IPC_MID_PRIORITY << 2) -#endif -#if CONFIG_PIC32MZ_UART2PRIO < 4 -# error "CONFIG_PIC32MZ_UART2PRIO is too small" -#endif -#if CONFIG_PIC32MZ_UART2PRIO > 31 -# error "CONFIG_PIC32MZ_UART2PRIO is too large" -#endif - -#ifndef CONFIG_PIC32MZ_CNPRIO /* Input Change Interrupt */ -# define CONFIG_PIC32MZ_CNPRIO (INT_IPC_MID_PRIORITY << 2) -#endif -#if CONFIG_PIC32MZ_CNPRIO < 4 -# error "CONFIG_PIC32MZ_CNPRIO is too small" -#endif -#if CONFIG_PIC32MZ_CNPRIO > 31 -# error "CONFIG_PIC32MZ_CNPRIO is too large" -#endif - -#ifndef CONFIG_PIC32MZ_ADCPRIO /* ADC1 Convert Done */ -# define CONFIG_PIC32MZ_ADCPRIO (INT_IPC_MID_PRIORITY << 2) -#endif -#if CONFIG_PIC32MZ_ADCPRIO < 4 -# error "CONFIG_PIC32MZ_ADCPRIO is too small" -#endif -#if CONFIG_PIC32MZ_ADCPRIO > 31 -# error "CONFIG_PIC32MZ_ADCPRIO is too large" -#endif - -#ifndef CONFIG_PIC32MZ_PMPPRIO /* Parallel Master Port */ -# define CONFIG_PIC32MZ_PMPPRIO (INT_IPC_MID_PRIORITY << 2) -#endif -#if CONFIG_PIC32MZ_PMPPRIO < 4 -# error "CONFIG_PIC32MZ_PMPPRIO is too small" -#endif -#if CONFIG_PIC32MZ_PMPPRIO > 31 -# error "CONFIG_PIC32MZ_PMPPRIO is too large" -#endif - -#ifndef CONFIG_PIC32MZ_CM1PRIO /* Comparator 1 */ -# define CONFIG_PIC32MZ_CM1PRIO (INT_IPC_MID_PRIORITY << 2) -#endif -#if CONFIG_PIC32MZ_CM1PRIO < 4 -# error "CONFIG_PIC32MZ_CM1PRIO is too small" -#endif -#if CONFIG_PIC32MZ_CM1PRIO > 31 -# error "CONFIG_PIC32MZ_CM1PRIO is too large" -#endif - -#ifndef CONFIG_PIC32MZ_CM2PRIO /* Comparator 2 */ -# define CONFIG_PIC32MZ_CM2PRIO (INT_IPC_MID_PRIORITY << 2) -#endif -#if CONFIG_PIC32MZ_CM2PRIO < 4 -# error "CONFIG_PIC32MZ_CM2PRIO is too small" -#endif -#if CONFIG_PIC32MZ_CM2PRIO > 31 -# error "CONFIG_PIC32MZ_CM2PRIO is too large" -#endif - -#ifndef CONFIG_PIC32MZ_FSCMPRIO /* Fail-Safe Clock Monitor */ -# define CONFIG_PIC32MZ_FSCMPRIO (INT_IPC_MID_PRIORITY << 2) -#endif -#if CONFIG_PIC32MZ_FSCMPRIO < 4 -# error "CONFIG_PIC32MZ_FSCMPRIO is too small" -#endif -#if CONFIG_PIC32MZ_FSCMPRIO > 31 -# error "CONFIG_PIC32MZ_FSCMPRIO is too large" -#endif - -#ifndef CONFIG_PIC32MZ_RTCCPRIO /* Real-Time Clock and Calendar */ -# define CONFIG_PIC32MZ_RTCCPRIO (INT_IPC_MID_PRIORITY << 2) -#endif -#if CONFIG_PIC32MZ_RTCCPRIO < 4 -# error "CONFIG_PIC32MZ_RTCCPRIO is too small" -#endif -#if CONFIG_PIC32MZ_RTCCPRIO > 31 -# error "CONFIG_PIC32MZ_RTCCPRIO is too large" -#endif - -#ifndef CONFIG_PIC32MZ_DMA0PRIO /* DMA Channel 0 */ -# define CONFIG_PIC32MZ_DMA0PRIO (INT_IPC_MID_PRIORITY << 2) -#endif -#if CONFIG_PIC32MZ_DMA0PRIO < 4 -# error "CONFIG_PIC32MZ_DMA0PRIO is too small" -#endif -#if CONFIG_PIC32MZ_DMA0PRIO > 31 -# error "CONFIG_PIC32MZ_DMA0PRIO is too large" -#endif - -#ifndef CONFIG_PIC32MZ_DMA1PRIO /* DMA Channel 1 */ -# define CONFIG_PIC32MZ_DMA1PRIO (INT_IPC_MID_PRIORITY << 2) -#endif -#if CONFIG_PIC32MZ_DMA1PRIO < 4 -# error "CONFIG_PIC32MZ_DMA1PRIO is too small" -#endif -#if CONFIG_PIC32MZ_DMA1PRIO > 31 -# error "CONFIG_PIC32MZ_DMA1PRIO is too large" -#endif - -#ifndef CONFIG_PIC32MZ_DMA2PRIO /* DMA Channel 2 */ -# define CONFIG_PIC32MZ_DMA2PRIO (INT_IPC_MID_PRIORITY << 2) -#endif -#if CONFIG_PIC32MZ_DMA2PRIO < 4 -# error "CONFIG_PIC32MZ_DMA2PRIO is too small" -#endif -#if CONFIG_PIC32MZ_DMA2PRIO > 31 -# error "CONFIG_PIC32MZ_DMA2PRIO is too large" -#endif - -#ifndef CONFIG_PIC32MZ_DMA3PRIO /* DMA Channel 3 */ -# define CONFIG_PIC32MZ_DMA3PRIO (INT_IPC_MID_PRIORITY << 2) -#endif -#if CONFIG_PIC32MZ_DMA3PRIO < 4 -# error "CONFIG_PIC32MZ_DMA3PRIO is too small" -#endif -#if CONFIG_PIC32MZ_DMA3PRIO > 31 -# error "CONFIG_PIC32MZ_DMA3PRIO is too large" -#endif - -#ifndef CONFIG_PIC32MZ_FCEPRIO /* Flash Control Event */ -# define CONFIG_PIC32MZ_FCEPRIO (INT_IPC_MID_PRIORITY << 2) -#endif -#if CONFIG_PIC32MZ_FCEPRIO < 4 -# error "CONFIG_PIC32MZ_FCEPRIO is too small" -#endif -#if CONFIG_PIC32MZ_FCEPRIO > 31 -# error "CONFIG_PIC32MZ_FCEPRIO is too large" -#endif - -#ifndef CONFIG_PIC32MZ_USBPRIO /* USB */ -# define CONFIG_PIC32MZ_USBPRIO (INT_IPC_MID_PRIORITY << 2) -#endif -#if CONFIG_PIC32MZ_USBPRIO < 4 -# error "CONFIG_PIC32MZ_USBPRIO is too small" -#endif -#if CONFIG_PIC32MZ_USBPRIO > 31 -# error "CONFIG_PIC32MZ_USBPRIO is too large" -#endif - -/* SYS calls ************************************************************************/ -/* SYS call 1 and 2 are defined for internal use by the PIC32MZ port (see - * arch/mips/include/mips32/syscall.h). In addition, SYS call 3 is the return from - * a SYS call in kernel mode. The first four syscall values must, therefore, be - * reserved (0 is not used). - */ - -#ifdef CONFIG_BUILD_KERNEL -# if !defined(CONFIG_SYS_RESERVED) || CONFIG_SYS_RESERVED < 4 -# error "CONFIG_SYS_RESERVED must be defined to be 4 for a kernel build" -# elif CONFIG_SYS_RESERVED > 4 -# warning "CONFIG_SYS_RESERVED should be defined to be 4 for a kernel build" -# endif -#endif - /* UARTs ****************************************************************************/ /* Don't enable UARTs not supported by the chip. */ @@ -592,185 +147,154 @@ /* Device Configuration *************************************************************/ /* DEVCFG3 */ +/* Configurable settings */ #ifndef CONFIG_PIC32MZ_USERID /* User ID */ -# define CONFIG_PIC32MZ_USERID 0x584e /* "NutX" */ +# define CONFIG_PIC32MZ_USERID 0x584e /* "NX" */ #endif -#ifndef CONFIG_PIC32MZ_PMDL1WAY /* Peripheral module disable configuration */ -# define CONFIG_PIC32MZ_PMDL1WAY 0 -#endif - -#ifndef CONFIG_PIC32MZ_IOL1WAY /* Peripheral pin select configuration */ -# define CONFIG_PIC32MZ_IOL1WAY 0 -#endif - -#ifndef CONFIG_PIC32MZ_SRSSEL /* Shadow register interrupt priority */ -# define CONFIG_PIC32MZ_SRSSEL INT_IPC_MIN_PRIORITY -#endif - -/* Unless overridden in the .config file, all pins are in the default setting */ - #ifndef CONFIG_PIC32MZ_FMIIEN /* Ethernet MII enable: 0=RMII 1=MII */ # define CONFIG_PIC32MZ_FMIIEN 1 /* MII enabled */ #endif +#ifndef CONFIG_PIC32MZ_PGL1WAY /* Permission group lock one way configuration */ +# define CONFIG_PIC32MZ_PGL1WAY 0 /* Allow multiple configurations */ +#endif + +#ifndef CONFIG_PIC32MZ_PMDL1WAY /* Peripheral module disable configuration */ +# define CONFIG_PIC32MZ_PMDL1WAY 0 /* Allow multiple reconfigurations */ +#endif + +#ifndef CONFIG_PIC32MZ_IOL1WAY /* Peripheral pin select configuration */ +# define CONFIG_PIC32MZ_IOL1WAY 0 /* Allow multiple reconfigurations */ +#endif + #ifndef CONFIG_PIC32MZ_FETHIO /* Ethernet I/O Pins 0=alternate 1=default */ # define CONFIG_PIC32MZ_FETHIO 1 /* Default Ethernet I/O Pins */ #endif -#ifndef CONFIG_PIC32MZ_FCANIO /* SCM1 pin C selection */ -# define CONFIG_PIC32MZ_FCANIO 1 /* Default CAN I/O Pins */ -#endif - -#ifndef CONFIG_PIC32MZ_FSCM1IO /* SCM1 pin C selection */ -# define CONFIG_PIC32MZ_FSCM1IO 1 /* Default pin for SCM1C */ -#endif - -/* USB or Ports? */ - -#ifdef CONFIG_PIC32MZ_USB -# ifndef CONFIG_PIC32MZ_USBIDO /* USB USBID Selection */ -# define CONFIG_PIC32MZ_USBIDO 1 /* USBID pin is controlled by the USB module */ -# endif -# ifndef CONFIG_PIC32MZ_VBUSIO /* USB VBUSON Selection */ -# define CONFIG_PIC32MZ_VBUSIO 1 /* VBUSON pin is controlled by the USB module */ -# endif -#else -# ifndef CONFIG_PIC32MZ_USBIDO /* USB USBID Selection */ -# define CONFIG_PIC32MZ_USBIDO 0 /* USBID pin is controlled by the Port function */ -# endif -# ifndef CONFIG_PIC32MZ_VBUSIO /* USB VBUSON Selection */ -# define CONFIG_PIC32MZ_VBUSIO 0 /* VBUSON pin is controlled by the Port function */ +#ifndef CONFIG_PIC32MZ_FUSBIDIO /* USB USBID selection: 0=GPIO 1=USB */ +# ifdef CONFIG_PIC32MZ_USB +# define CONFIG_PIC32MZ_FUSBIDIO 0 /* USBID pin is controlled by the IOPORT configuration */ +# else +# define CONFIG_PIC32MZ_FUSBIDIO 1 /* USBID pin is controlled by the USB module */ # endif #endif /* DEVCFG2 */ +/* PLL Input Divider bits */ #undef CONFIG_PIC32MZ_PLLIDIV #if BOARD_PLL_IDIV == 1 -# define CONFIG_PIC32MZ_PLLIDIV DEVCFG2_FPLLIDIV_DIV1 +# define CONFIG_PIC32MZ_PLLIDIV DEVCFG2_FPLLIDIV_1 #elif BOARD_PLL_IDIV == 2 -# define CONFIG_PIC32MZ_PLLIDIV DEVCFG2_FPLLIDIV_DIV2 +# define CONFIG_PIC32MZ_PLLIDIV DEVCFG2_FPLLIDIV_2 #elif BOARD_PLL_IDIV == 3 -# define CONFIG_PIC32MZ_PLLIDIV DEVCFG2_FPLLIDIV_DIV3 +# define CONFIG_PIC32MZ_PLLIDIV DEVCFG2_FPLLIDIV_3 #elif BOARD_PLL_IDIV == 4 -# define CONFIG_PIC32MZ_PLLIDIV DEVCFG2_FPLLIDIV_DIV4 +# define CONFIG_PIC32MZ_PLLIDIV DEVCFG2_FPLLIDIV_4 #elif BOARD_PLL_IDIV == 5 -# define CONFIG_PIC32MZ_PLLIDIV DEVCFG2_FPLLIDIV_DIV5 +# define CONFIG_PIC32MZ_PLLIDIV DEVCFG2_FPLLIDIV_5 #elif BOARD_PLL_IDIV == 6 -# define CONFIG_PIC32MZ_PLLIDIV DEVCFG2_FPLLIDIV_DIV6 -#elif BOARD_PLL_IDIV == 10 -# define CONFIG_PIC32MZ_PLLIDIV DEVCFG2_FPLLIDIV_DIV10 -#elif BOARD_PLL_IDIV == 12 -# define CONFIG_PIC32MZ_PLLIDIV DEVCFG2_FPLLIDIV_DIV12 +# define CONFIG_PIC32MZ_PLLIDIV DEVCFG2_FPLLIDIV_6 +#elif BOARD_PLL_IDIV == 7 +# define CONFIG_PIC32MZ_PLLIDIV DEVCFG2_FPLLIDIV_7 +#elif BOARD_PLL_IDIV == 8 +# define CONFIG_PIC32MZ_PLLIDIV DEVCFG2_FPLLIDIV_8 #else # error "Unsupported BOARD_PLL_IDIV" #endif +/* System PLL Divided Input Clock Frequency Range bits */ + +#if BOARD_PLL_INPUT < 5000000 +# error BOARD_PLL_INPUT too low +# define CONFIG_PIC32MZ_FPLLRNG DEVCFG2_FPLLRNG_BYPASS /* < 5 MHz */ +#elif BOARD_PLL_INPUT < 9000000 +# define CONFIG_PIC32MZ_FPLLRNG DEVCFG2_FPLLRNG_5_10MHZ /* 5-10 MHz */ +#elif BOARD_PLL_INPUT < 14500000 +# define CONFIG_PIC32MZ_FPLLRNG DEVCFG2_FPLLRNG_8_16MHZ /* 8-16 MHz */ +#elif BOARD_PLL_INPUT < 23500000 +# define CONFIG_PIC32MZ_FPLLRNG DEVCFG2_FPLLRNG_13_26MHZ /* 13-26 MHz */ +#elif BOARD_PLL_INPUT < 39000000 +# define CONFIG_PIC32MZ_FPLLRNG DEVCFG2_FPLLRNG_21_42MHZ /* 21-42 MHz */ +#elif BOARD_PLL_INPUT < 64000000 +# define CONFIG_PIC32MZ_FPLLRNG DEVCFG2_FPLLRNG_34_64MHZ /* 36-64 MHz */ +#else +# error BOARD_PLL_INPUT too high +# define CONFIG_PIC32MZ_FPLLRNG DEVCFG2_FPLLRNG_34_64MHZ /* 36-64 MHz */ +#endif + +/* PLL multiplier */ + #undef CONFIG_PIC32MZ_PLLMULT -#if BOARD_PLL_MULT == 15 -# define CONFIG_PIC32MZ_PLLMULT DEVCFG2_FPLLMULT_MUL15 -#elif BOARD_PLL_MULT == 16 -# define CONFIG_PIC32MZ_PLLMULT DEVCFG2_FPLLMULT_MUL16 -#elif BOARD_PLL_MULT == 17 -# define CONFIG_PIC32MZ_PLLMULT DEVCFG2_FPLLMULT_MUL17 -#elif BOARD_PLL_MULT == 18 -# define CONFIG_PIC32MZ_PLLMULT DEVCFG2_FPLLMULT_MUL18 -#elif BOARD_PLL_MULT == 19 -# define CONFIG_PIC32MZ_PLLMULT DEVCFG2_FPLLMULT_MUL19 -#elif BOARD_PLL_MULT == 20 -# define CONFIG_PIC32MZ_PLLMULT DEVCFG2_FPLLMULT_MUL20 -#elif BOARD_PLL_MULT == 21 -# define CONFIG_PIC32MZ_PLLMULT DEVCFG2_FPLLMULT_MUL21 -#elif BOARD_PLL_MULT == 24 -# define CONFIG_PIC32MZ_PLLMULT DEVCFG2_FPLLMULT_MUL24 +#if BOARD_PLL_MULT >= 1 && BOARD_PLL_MULT <= 128 +# define CONFIG_PIC32MZ_PLLMULT ((BOARD_PLL_MULT-1) << DEVCFG2_FPLLIDIV_SHIFT) #else # error "Unsupported BOARD_PLL_MULT" #endif -#undef CONFIG_PIC32MZ_UPLLIDIV -#if BOARD_UPLL_IDIV == 1 -# define CONFIG_PIC32MZ_UPLLIDIV DEVCFG2_FUPLLIDIV_DIV1 -#elif BOARD_UPLL_IDIV == 2 -# define CONFIG_PIC32MZ_UPLLIDIV DEVCFG2_FUPLLIDIV_DIV2 -#elif BOARD_UPLL_IDIV == 3 -# define CONFIG_PIC32MZ_UPLLIDIV DEVCFG2_FUPLLIDIV_DIV3 -#elif BOARD_UPLL_IDIV == 4 -# define CONFIG_PIC32MZ_UPLLIDIV DEVCFG2_FUPLLIDIV_DIV4 -#elif BOARD_UPLL_IDIV == 5 -# define CONFIG_PIC32MZ_UPLLIDIV DEVCFG2_FUPLLIDIV_DIV5 -#elif BOARD_UPLL_IDIV == 6 -# define CONFIG_PIC32MZ_UPLLIDIV DEVCFG2_FUPLLIDIV_DIV6 -#elif BOARD_UPLL_IDIV == 10 -# define CONFIG_PIC32MZ_UPLLIDIV DEVCFG2_FUPLLIDIV_DIV10 -#elif BOARD_UPLL_IDIV == 12 -# define CONFIG_PIC32MZ_UPLLIDIV DEVCFG2_FUPLLIDIV_DIV12 -#else -# error "Unsupported BOARD_UPLL_IDIV" -#endif - -#ifndef CONFIG_PIC32MZ_FUPLLEN -# if defined(CONFIG_PIC32MZ_USBDEV) || defined(CONFIG_PIC32MZ_USBHOST) -# define CONFIG_PIC32MZ_FUPLLEN 0 /* Enable */ -# else -# define CONFIG_PIC32MZ_FUPLLEN 1 /* Bypass and disable */ -# endif -#endif +/* PLL output divider */ #undef CONFIG_PIC32MZ_PLLODIV -#if BOARD_PLL_ODIV == 1 -# define CONFIG_PIC32MZ_PLLODIV DEVCFG2_FPLLODIV_DIV1 -#elif BOARD_PLL_ODIV == 2 -# define CONFIG_PIC32MZ_PLLODIV DEVCFG2_FPLLODIV_DIV2 +#if BOARD_PLL_ODIV == 2 +# define CONFIG_PIC32MZ_PLLODIV DEVCFG2_FPLLODIV_2 #elif BOARD_PLL_ODIV == 4 -# define CONFIG_PIC32MZ_PLLODIV DEVCFG2_FPLLODIV_DIV2 +# define CONFIG_PIC32MZ_PLLODIV DEVCFG2_FPLLODIV_4 #elif BOARD_PLL_ODIV == 8 -# define CONFIG_PIC32MZ_PLLODIV DEVCFG2_FPLLODIV_DIV2 +# define CONFIG_PIC32MZ_PLLODIV DEVCFG2_FPLLODIV_8 #elif BOARD_PLL_ODIV == 16 -# define CONFIG_PIC32MZ_PLLODIV DEVCFG2_FPLLODIV_DIV2 +# define CONFIG_PIC32MZ_PLLODIV DEVCFG2_FPLLODIV_16 #elif BOARD_PLL_ODIV == 32 -# define CONFIG_PIC32MZ_PLLODIV DEVCFG2_FPLLODIV_DIV2 -#elif BOARD_PLL_ODIV == 64 -# define CONFIG_PIC32MZ_PLLODIV DEVCFG2_FPLLODIV_DIV2 -#elif BOARD_PLL_ODIV == 128 -# define CONFIG_PIC32MZ_PLLODIV DEVCFG2_FPLLODIV_DIV2 +# define CONFIG_PIC32MZ_PLLODIV DEVCFG2_FPLLODIV_32 #else # error "Unsupported BOARD_PLL_ODIV" #endif -/* DEVCFG1 */ +/* Not yet configurable settings (REVISIT) */ + /* System PLL Input Clock Select bit */ +#define CONFIG_PIC32MZ_FPLLICLK 0 /* POSC is selected as input to the System PLL */ + /* USB PLL Input Frequency Select bit */ +#define CONFIG_PIC32MZ_UPLLFSEL DEVCFG2_UPLLFSEL + +/* DEVCFG1 */ +/* Configurable settings */ + +#undef CONFIG_PIC32MZ_FNOSC +#if defined(BOARD_FNOSC_FRC) +# define CONFIG_PIC32MZ_FNOSC DEVCFG1_FNOSC_FRC +#elif defined(BOARD_FNOSC_SPLL) +# define CONFIG_PIC32MZ_FNOSC DEVCFG1_FNOSC_SPLL +#elif defined(BOARD_FNOSC_POSC) +# define CONFIG_PIC32MZ_FNOSC DEVCFG1_FNOSC_POSC +#elif defined(BOARD_FNOSC_SOSC) +# define CONFIG_PIC32MZ_FNOSC DEVCFG1_FNOSC_SOSC +#elif defined(BOARD_FNOSC_LPRC) +# define CONFIG_PIC32MZ_FNOSC DEVCFG1_FNOSC_LPRC +#elif defined(BOARD_FNOSC_FRCDIV) +# define CONFIG_PIC32MZ_FNOSC DEVCFG1_FNOSC_FRCDIV +#else +# error "Unknown board FNOSC selection" +#endif + +#undef CONFIG_PIC32MZ_FSOSCEN #ifdef BOARD_SOSC_ENABLE # define CONFIG_PIC32MZ_FSOSCEN DEVCFG1_FSOSCEN #else # define CONFIG_PIC32MZ_FSOSCEN 0 #endif +#undef CONFIG_PIC32MZ_IESO #ifdef BOARD_SOSC_IESO -# define CONFIG_PIC32MZ_IESO DEVCFG1_IESO +# define CONFIG_PIC32MZ_IESO DEVCFG1_IESO #else -# define CONFIG_PIC32MZ_IESO 0 -#endif - -#undef CONFIG_PIC32MZ_PBDIV -#if BOARD_PBDIV == 1 -# define CONFIG_PIC32MZ_PBDIV DEVCFG1_FPBDIV_DIV1 -#elif BOARD_PBDIV == 2 -# define CONFIG_PIC32MZ_PBDIV DEVCFG1_FPBDIV_DIV2 -#elif BOARD_PBDIV == 4 -# define CONFIG_PIC32MZ_PBDIV DEVCFG1_FPBDIV_DIV4 -#elif BOARD_PBDIV == 8 -# define CONFIG_PIC32MZ_PBDIV DEVCFG1_FPBDIV_DIV8 -#else -# error "Unsupported BOARD_PBDIV" +# define CONFIG_PIC32MZ_IESO 0 #endif #undef CONFIG_PIC32MZ_POSCMOD #if defined(BOARD_POSC_ECMODE) # define CONFIG_PIC32MZ_POSCMOD DEVCFG1_POSCMOD_EC -#elif defined(BOARD_POSC_XTMODE) -# define CONFIG_PIC32MZ_POSCMOD DEVCFG1_POSCMOD_XT #elif defined(BOARD_POSC_HSMODE) # define CONFIG_PIC32MZ_POSCMOD DEVCFG1_POSCMOD_HS #elif defined(BOARD_POSC_DISABLED) @@ -779,23 +303,12 @@ # error "Unknown board POSC mode" #endif -#undef CONFIG_PIC32MZ_FNOSC -#if defined(BOARD_FNOSC_FRC) -# define CONFIG_PIC32MZ_FNOSC DEVCFG1_FNOSC_FRC -#elif defined(BOARD_FNOSC_FRCPLL) -# define CONFIG_PIC32MZ_FNOSC DEVCFG1_FNOSC_FRCPLL -#elif defined(BOARD_FNOSC_POSC) -# define CONFIG_PIC32MZ_FNOSC DEVCFG1_FNOSC_POSC -#elif defined(BOARD_FNOSC_POSCPLL) -# define CONFIG_PIC32MZ_FNOSC DEVCFG1_FNOSC_POSCPLL -#elif defined(BOARD_FNOSC_SOSC) -# define CONFIG_PIC32MZ_FNOSC DEVCFG1_FNOSC_SOSC -#elif defined(BOARD_FNOSC_LPRC) -# define CONFIG_PIC32MZ_FNOSC DEVCFG1_FNOSC_LPRC -#elif defined(BOARD_FNOSC_FRCDIV) -# define CONFIG_PIC32MZ_FNOSC DEVCFG1_FNOSC_FRCDIV +#ifdef CONFIG_PIC32MZ_OSCIOFNC +# undef CONFIG_PIC32MZ_OSCIOFNC +# define CONFIG_PIC32MZ_OSCIOFNC DEVCFG1_OSCIOFNC #else -# error "Unknown board FNOSC selection" +# undef CONFIG_PIC32MZ_OSCIOFNC +# define CONFIG_PIC32MZ_OSCIOFNC 0 #endif #undef CONFIG_PIC32MZ_FCKSM @@ -803,99 +316,117 @@ # if defined(BOARD_POSC_FSCM) # define CONFIG_PIC32MZ_FCKSM DEVCFG1_FCKSM_BOTH # else -# define CONFIG_PIC32MZ_FCKSM DEVCFG1_FCKSM_CSONLY +# define CONFIG_PIC32MZ_FCKSM DEVCFG1_FCKSM_SWITCH # endif #else -# define CONFIG_PIC32MZ_FCKSM DEVCFG1_FCKSM_NONE +# if defined(BOARD_POSC_FSCM) +# define CONFIG_PIC32MZ_FCKSM DEVCFG1_FCKSM_MONITOR +# else +# define CONFIG_PIC32MZ_FCKSM DEVCFG1_FCKSM_NONE +# endif #endif -#ifndef CONFIG_PIC32MZ_OSCOUT -# define CONFIG_PIC32MZ_OSCOUT 0 -#endif - -#undef CONFIG_PIC32MZ_WDPS +#undef CONFIG_PIC32MZ_WDTPS #if BOARD_WD_PRESCALER == 1 -# define CONFIG_PIC32MZ_WDPS DEVCFG1_WDTPS_1 +# define CONFIG_PIC32MZ_WDTPS DEVCFG1_WDTPS_1 #elif BOARD_WD_PRESCALER == 2 -# define CONFIG_PIC32MZ_WDPS DEVCFG1_WDTPS_2 +# define CONFIG_PIC32MZ_WDTPS DEVCFG1_WDTPS_2 #elif BOARD_WD_PRESCALER == 4 -# define CONFIG_PIC32MZ_WDPS DEVCFG1_WDTPS_4 +# define CONFIG_PIC32MZ_WDTPS DEVCFG1_WDTPS_4 #elif BOARD_WD_PRESCALER == 8 -# define CONFIG_PIC32MZ_WDPS DEVCFG1_WDTPS_8 +# define CONFIG_PIC32MZ_WDTPS DEVCFG1_WDTPS_8 #elif BOARD_WD_PRESCALER == 16 -# define CONFIG_PIC32MZ_WDPS DEVCFG1_WDTPS_16 +# define CONFIG_PIC32MZ_WDTPS DEVCFG1_WDTPS_16 #elif BOARD_WD_PRESCALER == 32 -# define CONFIG_PIC32MZ_WDPS DEVCFG1_WDTPS_32 +# define CONFIG_PIC32MZ_WDTPS DEVCFG1_WDTPS_32 #elif BOARD_WD_PRESCALER == 64 -# define CONFIG_PIC32MZ_WDPS DEVCFG1_WDTPS_64 +# define CONFIG_PIC32MZ_WDTPS DEVCFG1_WDTPS_64 #elif BOARD_WD_PRESCALER == 128 -# define CONFIG_PIC32MZ_WDPS DEVCFG1_WDTPS_128 +# define CONFIG_PIC32MZ_WDTPS DEVCFG1_WDTPS_128 #elif BOARD_WD_PRESCALER == 256 -# define CONFIG_PIC32MZ_WDPS DEVCFG1_WDTPS_256 +# define CONFIG_PIC32MZ_WDTPS DEVCFG1_WDTPS_256 #elif BOARD_WD_PRESCALER == 512 -# define CONFIG_PIC32MZ_WDPS DEVCFG1_WDTPS_512 +# define CONFIG_PIC32MZ_WDTPS DEVCFG1_WDTPS_512 #elif BOARD_WD_PRESCALER == 1024 -# define CONFIG_PIC32MZ_WDPS DEVCFG1_WDTPS_1024 +# define CONFIG_PIC32MZ_WDTPS DEVCFG1_WDTPS_1024 #elif BOARD_WD_PRESCALER == 2048 -# define CONFIG_PIC32MZ_WDPS DEVCFG1_WDTPS_2048 +# define CONFIG_PIC32MZ_WDTPS DEVCFG1_WDTPS_2048 #elif BOARD_WD_PRESCALER == 4096 -# define CONFIG_PIC32MZ_WDPS DEVCFG1_WDTPS_4096 +# define CONFIG_PIC32MZ_WDTPS DEVCFG1_WDTPS_4096 #elif BOARD_WD_PRESCALER == 8192 -# define CONFIG_PIC32MZ_WDPS DEVCFG1_WDTPS_8192 +# define CONFIG_PIC32MZ_WDTPS DEVCFG1_WDTPS_8192 #elif BOARD_WD_PRESCALER == 16384 -# define CONFIG_PIC32MZ_WDPS DEVCFG1_WDTPS_16384 +# define CONFIG_PIC32MZ_WDTPS DEVCFG1_WDTPS_16384 #elif BOARD_WD_PRESCALER == 32768 -# define CONFIG_PIC32MZ_WDPS DEVCFG1_WDTPS_32768 +# define CONFIG_PIC32MZ_WDTPS DEVCFG1_WDTPS_32768 #elif BOARD_WD_PRESCALER == 65536 -# define CONFIG_PIC32MZ_WDPS DEVCFG1_WDTPS_65536 +# define CONFIG_PIC32MZ_WDTPS DEVCFG1_WDTPS_65536 #elif BOARD_WD_PRESCALER == 131072 -# define CONFIG_PIC32MZ_WDPS DEVCFG1_WDTPS_131072 +# define CONFIG_PIC32MZ_WDTPS DEVCFG1_WDTPS_131072 #elif BOARD_WD_PRESCALER == 262144 -# define CONFIG_PIC32MZ_WDPS DEVCFG1_WDTPS_262144 +# define CONFIG_PIC32MZ_WDTPS DEVCFG1_WDTPS_262144 #elif BOARD_WD_PRESCALER == 524288 -# define CONFIG_PIC32MZ_WDPS DEVCFG1_WDTPS_524288 +# define CONFIG_PIC32MZ_WDTPS DEVCFG1_WDTPS_524288 #elif BOARD_WD_PRESCALER == 1048576 -# define CONFIG_PIC32MZ_WDPS DEVCFG1_WDTPS_1048576 +# define CONFIG_PIC32MZ_WDTPS DEVCFG1_WDTPS_1048576 #else # error "Unsupported BOARD_WD_PRESCALER" #endif -#undef CONFIG_PIC32MZ_WDENABLE -#if BOARD_WD_ENABLE -# define CONFIG_PIC32MZ_WDENABLE DEVCFG1_FWDTEN +#undef CONFIG_PIC32MZ_FWDTEN +#if CONFIG_PIC32MZ_WDTENABLE +# define CONFIG_PIC32MZ_FWDTEN DEVCFG1_FWDTEN #else -# define CONFIG_PIC32MZ_WDENABLE 0 +# define CONFIG_PIC32MZ_FWDTEN 0 #endif +/* Not yet configurable settings */ + +#define CONFIG_PIC32MZ_DMTINV DEVCFG1_FNOSC_FRCDIV +#define CONFIG_PIC32MZ_WDTSPGM DEVCFG1_WDTSPGM +#define CONFIG_PIC32MZ_WINDIS DEVCFG1_WINDIS +#define CONFIG_PIC32MZ_FWDTWINSZ DEVCFG1_FWDTWINSZ_25 +#define CONFIG_PIC32MZ_DMTCNT DEVCFG1_DMTCNT_MASK +#define CONFIG_PIC32MZ_FDMTEN 0 + /* DEVCFG0 */ +/* Configurable settings */ -#ifndef CONFIG_PIC32MZ_DEBUGGER /* Background Debugger Enable */ -# define CONFIG_PIC32MZ_DEBUGGER 3 /* disabled */ +#undef CONFIG_PIC32MZ_DEBUGGER +#ifdef CONFIG_PIC32MZ_DEBUGGER_ENABLE +# define CONFIG_PIC32MZ_DEBUGGER DEVCFG0_DEBUG_ENABLED +#else +# define CONFIG_PIC32MZ_DEBUGGER DEVCFG0_DEBUG_DISABLED #endif -#ifndef CONFIG_PIC32MZ_ICESEL /* In-Circuit Emulator/Debugger Communication Channel Select */ -# if defined(CHIP_PIC32MZ1) || defined(CHIP_PIC32MZ2) -# define CONFIG_PIC32MZ_ICESEL 3 /* Default PGEC1/PGED1 */ -# else -# define CONFIG_PIC32MZ_ICESEL 1 /* Default PGEC1/PGED1 */ -# endif +#undef CONFIG_PIC32MZ_JTAGEN +#ifdef CONFIG_PIC32MZ_JTAG_ENABLE +# define CONFIG_PIC32MZ_JTAGEN DEVCFG0_JTAGEN +#else +# define CONFIG_PIC32MZ_JTAGEN 0 #endif -#ifndef CONFIG_PIC32MZ_PROGFLASHWP /* Program FLASH write protect */ -# if defined(CHIP_PIC32MZ1) || defined(CHIP_PIC32MZ2) -# define CONFIG_PIC32MZ_PROGFLASHWP 0x3ff /* Disabled */ -# else -# define CONFIG_PIC32MZ_PROGFLASHWP 0xff /* Disabled */ -# endif +#undef CONFIG_PIC32MZ_ICESEL +#ifdef CONFIG_PIC32MZ_ICESEL_CH2 +# define CONFIG_PIC32MZ_ICESEL DEVCFG0_ICESEL_2 +#else +# define CONFIG_PIC32MZ_ICESEL DEVCFG0_ICESEL_1 #endif -#ifndef CONFIG_PIC32MZ_BOOTFLASHWP -# define CONFIG_PIC32MZ_BOOTFLASHWP 1 /* Disabled */ +#undef CONFIG_PIC32MZ_TRCEN +#ifdef CONFIG_PIC32MZ_TRACE_ENABLE +# define CONFIG_PIC32MZ_TRCEN DEVCFG0_TRCEN +#else +# define CONFIG_PIC32MZ_TRCEN 0 #endif -#ifndef CONFIG_PIC32MZ_CODEWP -# define CONFIG_PIC32MZ_CODEWP 1 /* Disabled */ -#endif +/* Not yet configurable settings */ + +#define CONFIG_PIC32MZ_BOOTISA 0 /* microMIPS always */ +#define CONFIG_PIC32MZ_FECCCON DEVCFG0_FECCCON_DISWR +#define CONFIG_PIC32MZ_FSLEEP DEVCFG0_FSLEEP +#define CONFIG_PIC32MZ_DBGPER DEVCFG0_DBGPER_MASK +#define CONFIG_PIC32MZ_EJTAGBEN DEVCFG0_EJTAGBEN /************************************************************************************ * Public Types diff --git a/arch/mips/src/pic32mz/pic32mz-head.S b/arch/mips/src/pic32mz/pic32mz-head.S index 1e1ea244b4..b6f089bfdc 100644 --- a/arch/mips/src/pic32mz/pic32mz-head.S +++ b/arch/mips/src/pic32mz/pic32mz-head.S @@ -43,8 +43,7 @@ #include #include "pic32mz-config.h" -// REVISIT -//#include "pic32mz-bmx.h" +#include "chip/pic32mz-features.h" #include "pic32mz-excptmacros.h" /**************************************************************************** @@ -116,7 +115,7 @@ .globl __reset .global __start .global halt - .global devconfig + .global devcfg #if CONFIG_ARCH_INTERRUPTSTACK > 3 .global g_intstackbase #ifdef CONFIG_PIC32MZ_NESTED_INTERRUPTS @@ -157,6 +156,7 @@ .section .reset, "ax", @progbits .align 2 .set noreorder + .set nomips16 .set micromips .ent __reset @@ -643,79 +643,88 @@ halt: ****************************************************************************/ .section .devcfg, "a" - .type devconfig, object -devconfig: -devconfig3: -#if defined(CHIP_PIC32MZ1) || defined(CHIP_PIC32MZ2) + .type devcfg, object +devcfg: +devcfg3: + .long CONFIG_PIC32MZ_USERID << DEVCFG3_USERID_SHIFT | \ + CONFIG_PIC32MZ_FMIIEN << DEVCFG3_FMIIEN_SHIFT | \ + CONFIG_PIC32MZ_FETHIO << DEVCFG3_FETHIO_SHIFT | \ + CONFIG_PIC32MZ_PGL1WAY << DEVCFG3_PGL1WAY_SHIFT | \ + CONFIG_PIC32MZ_PMDL1WAY << DEVCFG3_PMDL1WAY_SHIFT | \ + CONFIG_PIC32MZ_IOL1WAY << DEVCFG3_IOL1WAY_SHIFT | \ + CONFIG_PIC32MZ_FUSBIDIO << DEVCFG3_FUSBIDIO_SHIFT | \ + DEVCFG3_RWO - .long CONFIG_PIC32MZ_USERID << DEVCFG3_USERID_SHIFT | \ - CONFIG_PIC32MZ_PMDL1WAY << 28 | CONFIG_PIC32MZ_IOL1WAY << 29 | \ - CONFIG_PIC32MZ_USBIDO << 30 | CONFIG_PIC32MZ_VBUSIO << 31 | \ - DEVCFG3_UNUSED +devcfg2: + .long CONFIG_PIC32MZ_PLLIDIV | CONFIG_PIC32MZ_FPLLRNG | \ + CONFIG_PIC32MZ_FPLLICLK | CONFIG_PIC32MZ_PLLMULT | \ + CONFIG_PIC32MZ_PLLODIV | CONFIG_PIC32MZ_UPLLFSEL | \ + DEVCFG2_RWO -#elif defined(CHIP_PIC32MZ3) || defined(CHIP_PIC32MZ4) +devcfg1: + .long CONFIG_PIC32MZ_FNOSC | CONFIG_PIC32MZ_DMTINV |\ + CONFIG_PIC32MZ_FSOSCEN | CONFIG_PIC32MZ_IESO | \ + CONFIG_PIC32MZ_POSCMOD | CONFIG_PIC32MZ_OSCIOFNC | \ + CONFIG_PIC32MZ_FCKSM | CONFIG_PIC32MZ_WDTPS | \ + CONFIG_PIC32MZ_WDTSPGM | CONFIG_PIC32MZ_WINDIS | \ + CONFIG_PIC32MZ_FWDTEN | CONFIG_PIC32MZ_FWDTWINSZ | \ + CONFIG_PIC32MZ_DMTCNT | CONFIG_PIC32MZ_FSOSCEN | \ + CONFIG_PIC32MZ_FSOSCEN | CONFIG_PIC32MZ_FDMTEN | \ + DEVCFG1_RWO - .long CONFIG_PIC32MZ_USERID << DEVCFG3_USERID_SHIFT | \ - DEVCFG3_UNUSED +devcfg0: + .long CONFIG_PIC32MZ_DEBUGGER | CONFIG_PIC32MZ_JTAGEN | \ + CONFIG_PIC32MZ_ICESEL | CONFIG_PIC32MZ_TRCEN | \ + CONFIG_PIC32MZ_BOOTISA | CONFIG_PIC32MZ_FECCCON | \ + CONFIG_PIC32MZ_FSLEEP | CONFIG_PIC32MZ_DBGPER | \ + CONFIG_PIC32MZ_EJTAGBEN | DEVCFG0_RW0 -#elif defined(CHIP_PIC32MZ5) || defined(CHIP_PIC32MZ6) || defined(CHIP_PIC32MZ7) + .size devcfg, .-devcfg - .long CONFIG_PIC32MZ_USERID << DEVCFG3_USERID_SHIFT | \ - CONFIG_PIC32MZ_SRSSEL << DEVCFG3_FSRSSEL_SHIFT | \ - CONFIG_PIC32MZ_FMIIEN << 24 | CONFIG_PIC32MZ_FETHIO << 25 | \ - CONFIG_PIC32MZ_FCANIO << 26 | CONFIG_PIC32MZ_FSCM1IO << 29 | \ - CONFIG_PIC32MZ_USBIDO << 30 | CONFIG_PIC32MZ_VBUSIO << 31 | \ - DEVCFG3_UNUSED +/* Every word in the configuration space and sequence space has an + * associated alternate word. During device start-up, primary words are + * read and if uncorrectable ECC errors are found, the BCFGERR flag is set + * and alternate words are used. + */ -#endif + .section .adevcfg, "a" + .type adevcfg, object +adevcfg: +adevcfg3: + .long CONFIG_PIC32MZ_USERID << DEVCFG3_USERID_SHIFT | \ + CONFIG_PIC32MZ_FMIIEN << DEVCFG3_FMIIEN_SHIFT | \ + CONFIG_PIC32MZ_FETHIO << DEVCFG3_FETHIO_SHIFT | \ + CONFIG_PIC32MZ_PGL1WAY << DEVCFG3_PGL1WAY_SHIFT | \ + CONFIG_PIC32MZ_PMDL1WAY << DEVCFG3_PMDL1WAY_SHIFT | \ + CONFIG_PIC32MZ_IOL1WAY << DEVCFG3_IOL1WAY_SHIFT | \ + CONFIG_PIC32MZ_FUSBIDIO << DEVCFG3_FUSBIDIO_SHIFT | \ + DEVCFG3_RWO -devconfig2: - .long CONFIG_PIC32MZ_PLLIDIV | CONFIG_PIC32MZ_PLLMULT | \ - CONFIG_PIC32MZ_UPLLIDIV | CONFIG_PIC32MZ_PLLODIV | \ - CONFIG_PIC32MZ_FUPLLEN << 15 | DEVCFG2_UNUSED +adevcfg2: + .long CONFIG_PIC32MZ_PLLIDIV | CONFIG_PIC32MZ_FPLLRNG | \ + CONFIG_PIC32MZ_FPLLICLK | CONFIG_PIC32MZ_PLLMULT | \ + CONFIG_PIC32MZ_PLLODIV | CONFIG_PIC32MZ_UPLLFSEL | \ + DEVCFG2_RWO -devconfig1: -#if defined(CHIP_PIC32MZ1) || defined(CHIP_PIC32MZ2) +adevcfg1: + .long CONFIG_PIC32MZ_FNOSC | CONFIG_PIC32MZ_DMTINV |\ + CONFIG_PIC32MZ_FSOSCEN | CONFIG_PIC32MZ_IESO | \ + CONFIG_PIC32MZ_POSCMOD | CONFIG_PIC32MZ_OSCIOFNC | \ + CONFIG_PIC32MZ_FCKSM | CONFIG_PIC32MZ_WDTPS | \ + CONFIG_PIC32MZ_WDTSPGM | CONFIG_PIC32MZ_WINDIS | \ + CONFIG_PIC32MZ_FWDTEN | CONFIG_PIC32MZ_FWDTWINSZ | \ + CONFIG_PIC32MZ_DMTCNT | CONFIG_PIC32MZ_FSOSCEN | \ + CONFIG_PIC32MZ_FSOSCEN | CONFIG_PIC32MZ_FDMTEN | \ + DEVCFG1_RWO - .long CONFIG_PIC32MZ_FNOSC | CONFIG_PIC32MZ_FSOSCEN | \ - CONFIG_PIC32MZ_IESO | CONFIG_PIC32MZ_POSCMOD | \ - CONFIG_PIC32MZ_OSCOUT << 10 | \ - CONFIG_PIC32MZ_PBDIV | CONFIG_PIC32MZ_FCKSM | \ - DEVCFG1_WINDIS | CONFIG_PIC32MZ_WDENABLE | \ - DEVCFG1_FWDTWINSZ_75 | DEVCFG1_UNUSED +adevcfg0: + .long CONFIG_PIC32MZ_DEBUGGER | CONFIG_PIC32MZ_JTAGEN | \ + CONFIG_PIC32MZ_ICESEL | CONFIG_PIC32MZ_TRCEN | \ + CONFIG_PIC32MZ_BOOTISA | CONFIG_PIC32MZ_FECCCON | \ + CONFIG_PIC32MZ_FSLEEP | CONFIG_PIC32MZ_DBGPER | \ + CONFIG_PIC32MZ_EJTAGBEN | DEVCFG0_RW0 -#else - - .long CONFIG_PIC32MZ_FNOSC | CONFIG_PIC32MZ_FSOSCEN | \ - CONFIG_PIC32MZ_IESO | CONFIG_PIC32MZ_POSCMOD | \ - CONFIG_PIC32MZ_OSCOUT << 10 | \ - CONFIG_PIC32MZ_PBDIV | CONFIG_PIC32MZ_FCKSM | \ - CONFIG_PIC32MZ_WDENABLE | DEVCFG1_UNUSED - -#endif - -devconfig0: -#if defined(CHIP_PIC32MZ1) || defined(CHIP_PIC32MZ2) - - .long CONFIG_PIC32MZ_DEBUGGER << DEVCFG0_DEBUG_SHIFT | \ - DEVCFG0_JTAGEN | \ - CONFIG_PIC32MZ_ICESEL << DEVCFG0_ICESEL_SHIFT | \ - CONFIG_PIC32MZ_PROGFLASHWP << DEVCFG0_PWP_SHIFT | \ - CONFIG_PIC32MZ_BOOTFLASHWP << 24 | \ - CONFIG_PIC32MZ_CODEWP << 28 | \ - DEVCFG0_UNUSED - -#else - - .long CONFIG_PIC32MZ_DEBUGGER << DEVCFG0_DEBUG_SHIFT | \ - CONFIG_PIC32MZ_ICESEL << 3 | \ - CONFIG_PIC32MZ_PROGFLASHWP << DEVCFG0_PWP_SHIFT | \ - CONFIG_PIC32MZ_BOOTFLASHWP << 24 | \ - CONFIG_PIC32MZ_CODEWP << 28 | \ - DEVCFG0_UNUSED - -#endif - .size devconfig, .-devconfig + .size adevcfg, .-adevcfg /**************************************************************************** * Global Data diff --git a/configs/pic32mz-starterkit/include/board.h b/configs/pic32mz-starterkit/include/board.h index 1bc4f48a38..0783095490 100644 --- a/configs/pic32mz-starterkit/include/board.h +++ b/configs/pic32mz-starterkit/include/board.h @@ -54,53 +54,28 @@ /* Clocking *****************************************************************/ /* Crystal frequencies */ -#define BOARD_POSC_FREQ 8000000 /* Primary OSC XTAL frequency (8MHz) */ -#define BOARD_SOSC_FREQ 32768 /* Secondary OSC XTAL frequency (32.768KHz) */ +#define BOARD_POSC_FREQ 24000000 /* Primary OSC XTAL frequency (24MHz) */ +#define BOARD_SOSC_FREQ 32768 /* Secondary OSC XTAL frequency (32.768KHz) */ /* Oscillator modes */ -#define BOARD_FNOSC_POSCPLL 1 /* Use primary oscillator w/PLL */ -#define BOARD_POSC_HSMODE 1 /* High-speed crystal (HS) mode */ +#define BOARD_FNOSC_POSC 1 /* Use primary oscillator */ +#define BOARD_POSC_HSMODE 1 /* High-speed crystal (HS) mode */ /* PLL configuration and resulting CPU clock. * CPU_CLOCK = ((POSC_FREQ / IDIV) * MULT) / ODIV */ #define BOARD_PLL_INPUT BOARD_POSC_FREQ -#define BOARD_PLL_IDIV 2 /* PLL input divider */ -#define BOARD_PLL_MULT 20 /* PLL multiplier */ -#define BOARD_PLL_ODIV 1 /* PLL output divider */ +#define BOARD_PLL_IDIV 3 /* PLL input divider */ +#define BOARD_PLL_MULT 50 /* PLL multiplier */ +#define BOARD_PLL_ODIV 2 /* PLL output divider */ -#define BOARD_CPU_CLOCK 80000000 /* CPU clock (80MHz = 8MHz * 20 / 2) */ - -/* USB PLL configuration. - * USB_CLOCK = ((POSC_XTAL / IDIV) * 24) / 2 - */ - -#define BOARD_UPLL_IDIV 2 /* USB PLL divider (revisit) */ -#define BOARD_USB_CLOCK 48000000 /* USB clock (8MHz / 2) * 24 / 2) */ - -/* Peripheral clock is divided down from CPU clock. - * PBCLOCK = CPU_CLOCK / PBDIV - */ - -#define BOARD_PBDIV 2 /* Peripheral clock divisor (PBDIV) */ -#define BOARD_PBCLOCK 40000000 /* Peripheral clock (PBCLK = 80MHz/2) */ +#define BOARD_CPU_CLOCK 200000000 /* CPU clock: 200MHz = (24MHz / 3) * 50 / 2) */ /* Watchdog pre-scaler (re-visit) */ -#define BOARD_WD_ENABLE 0 /* Watchdog is disabled */ -#define BOARD_WD_PRESCALER 8 /* Watchdog pre-scaler */ - -/* Ethernet MII clocking. - * - * The clock divider used to create the MII Management Clock (MDC). The MIIM - * module uses the SYSCLK as an input clock. According to the IEEE 802.3 - * Specification this should be no faster than 2.5 MHz. However, some PHYs - * support clock rates up to 12.5 MHz. - */ - -#define BOARD_EMAC_MIIM_DIV 32 /* Ideal: 80MHz/32 = 2.5MHz */ +#define BOARD_WD_PRESCALER 8 /* Watchdog pre-scaler */ /* LED definitions **********************************************************/ /* LED Configuration ********************************************************/ diff --git a/configs/pic32mz-starterkit/nsh/defconfig b/configs/pic32mz-starterkit/nsh/defconfig index 73d288a580..e9c1d04428 100644 --- a/configs/pic32mz-starterkit/nsh/defconfig +++ b/configs/pic32mz-starterkit/nsh/defconfig @@ -143,41 +143,30 @@ CONFIG_PIC32MZ_UART1=y # CONFIG_PIC32MZ_ETHERNET is not set # CONFIG_PIC32MZ_CTMU is not set -# -# PIC32MZ Peripheral Interrupt Priorities -# -CONFIG_PIC32MZ_CTPRIO=16 -CONFIG_PIC32MZ_CS0PRIO=16 -CONFIG_PIC32MZ_CS1PRIO=16 -CONFIG_PIC32MZ_INT0PRIO=16 -CONFIG_PIC32MZ_INT1PRIO=16 -CONFIG_PIC32MZ_INT2PRIO=16 -CONFIG_PIC32MZ_INT3PRIO=16 -CONFIG_PIC32MZ_INT4PRIO=16 -CONFIG_PIC32MZ_T1PRIO=16 -CONFIG_PIC32MZ_UART1PRIO=16 - # # Device Configuration 0 (DEVCFG0) # -CONFIG_PIC32MZ_DEBUGGER=2 -CONFIG_PIC32MZ_ICESEL=1 -CONFIG_PIC32MZ_PROGFLASHWP=0xff -CONFIG_PIC32MZ_BOOTFLASHWP=1 -CONFIG_PIC32MZ_CODEWP=1 +# CONFIG_PIC32MZ_DEBUGGER_ENABLE is not set +CONFIG_PIC32MZ_JTAG_ENABLE=y +# CONFIG_PIC32MZ_ICESEL_CH2 is not set +# CONFIG_PIC32MZ_TRACE_ENABLE is not set # # Device Configuration 1 (DEVCFG1) # +CONFIG_CONFIG_PIC32MZ_OSCIOFNC=0 +# CONFIG_PIC32MZ_WDTENABLE is not set # # Device Configuration 3 (DEVCFG3) # -CONFIG_PIC32MZ_USBIDO=0 -CONFIG_PIC32MZ_VBUSIO=0 -# CONFIG_PIC32MZ_WDENABLE is not set -CONFIG_PIC32MZ_FETHIO=0 +CONFIG_PIC32MZ_USERID=0x584e CONFIG_PIC32MZ_FMIIEN=0 +CONFIG_PIC32MZ_PGL1WAY=0 +CONFIG_PIC32MZ_PMDL1WAY=0 +CONFIG_PIC32MZ_IOL1WAY=0 +CONFIG_PIC32MZ_FETHIO=0 +CONFIG_PIC32MZ_FUSBIDIO=1 # # Architecture Options diff --git a/configs/pic32mz-starterkit/scripts/c32-release.ld b/configs/pic32mz-starterkit/scripts/c32-release.ld index b385bc21a9..e19fc073f6 100644 --- a/configs/pic32mz-starterkit/scripts/c32-release.ld +++ b/configs/pic32mz-starterkit/scripts/c32-release.ld @@ -59,7 +59,8 @@ MEMORY * JTAG 0x1fc00480 KSEG1 16 1168 * Exceptions 0x1fc00490 KSEG0 8192-1168 8192 (4Kb) * Debug code 0x1fc02000 KSEG1 4096-16 12272 - * DEVCFG3-0 0x1fc0ff40 KSEG1 16 12288 (12Kb) + * ADEVCFG3-0 0x1fc0ff40 KSEG1 16 12288 (12Kb) + * DEVCFG3-0 0x1fc0ffc0 KSEG1 16 12288 (12Kb) * * Exceptions assume: * @@ -77,7 +78,8 @@ MEMORY kseg1_dbgexcpt (rx) : ORIGIN = 0xbfc00480, LENGTH = 16 kseg0_bootmem (rx) : ORIGIN = 0x9fc00490, LENGTH = 8192-1168 kseg1_dbgcode (rx) : ORIGIN = 0xbfc02000, LENGTH = 4096-16 - kseg1_devcfg (r) : ORIGIN = 0x1fc0ff40, LENGTH = 192 + kseg1_adevcfg (r) : ORIGIN = 0x1fc0ff40, LENGTH = 128 + kseg1_devcfg (r) : ORIGIN = 0x1fc0ffc0, LENGTH = 128 /* The The PIC32MZ2048ECH144 and PIC32MZ2048ECM144 chips have has 512Kb * of data memory at physical address 0x00000000. Since the PIC32MZ @@ -159,6 +161,11 @@ SECTIONS .dbg_code = ORIGIN(kseg1_dbgcode); + .adevcfg : + { + KEEP (*(.adevcfg)) + } > kseg1_adevcfg + .devcfg : { KEEP (*(.devcfg)) diff --git a/configs/pic32mz-starterkit/scripts/mips-release.ld b/configs/pic32mz-starterkit/scripts/mips-release.ld index 94ed775a4a..cc51d43fe0 100644 --- a/configs/pic32mz-starterkit/scripts/mips-release.ld +++ b/configs/pic32mz-starterkit/scripts/mips-release.ld @@ -59,7 +59,8 @@ MEMORY * JTAG 0x1fc00480 KSEG1 16 1168 * Exceptions 0x1fc00490 KSEG0 8192-1168 8192 (4Kb) * Debug code 0x1fc02000 KSEG1 4096-16 12272 - * DEVCFG3-0 0x1fc0ff40 KSEG1 16 12288 (12Kb) + * ADEVCFG3-0 0x1fc0ff40 KSEG1 16 12288 (12Kb) + * DEVCFG3-0 0x1fc0ffc0 KSEG1 16 12288 (12Kb) * * Exceptions assume: * @@ -77,7 +78,8 @@ MEMORY kseg1_dbgexcpt (rx) : ORIGIN = 0xbfc00480, LENGTH = 16 kseg0_bootmem (rx) : ORIGIN = 0x9fc00490, LENGTH = 8192-1168 kseg1_dbgcode (rx) : ORIGIN = 0xbfc02000, LENGTH = 4096-16 - kseg1_devcfg (r) : ORIGIN = 0x1fc0ff40, LENGTH = 192 + kseg1_adevcfg (r) : ORIGIN = 0x1fc0ff40, LENGTH = 128 + kseg1_devcfg (r) : ORIGIN = 0x1fc0ffc0, LENGTH = 128 /* The The PIC32MZ2048ECH144 and PIC32MZ2048ECM144 chips have has 512Kb * of data memory at physical address 0x00000000. Since the PIC32MZ @@ -159,6 +161,11 @@ SECTIONS .dbg_code = ORIGIN(kseg1_dbgcode); + .adevcfg : + { + KEEP (*(.adevcfg)) + } > kseg1_adevcfg + .devcfg : { KEEP (*(.devcfg))