xtensa/esp32: Support to select different clock source for RTC controller and close TODOs.
This commit is contained in:
Sara Souza
Xiang Xiao
parent
a8cbcd084f
commit
87fabb2bc7
@ -211,6 +211,44 @@ config ESP32_XTAL_26MHz
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endchoice # On-board Crystal Frequency
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choice ESP32_RTC_CLK_SRC
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prompt "RTC clock source"
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default ESP32_RTC_CLK_SRC_INT_RC
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---help---
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Choose which clock is used as RTC clock source.
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- "Internal 150kHz oscillator" option provides lowest deep sleep current
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consumption, and does not require extra external components. However
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frequency stability with respect to temperature is poor, so time may
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drift in deep/light sleep modes.
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- "External 32kHz crystal" provides better frequency stability, at the
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expense of slightly higher (1uA) deep sleep current consumption.
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- "External 32kHz oscillator" allows using 32kHz clock generated by an
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external circuit. In this case, external clock signal must be connected
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to 32K_XN pin. Amplitude should be <1.2V in case of sine wave signal,
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and <1V in case of square wave signal. Common mode voltage should be
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0.1 < Vcm < 0.5Vamp, where Vamp is the signal amplitude.
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Additionally, 1nF capacitor must be connected between 32K_XP pin and
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ground. 32K_XP pin can not be used as a GPIO in this case.
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- "Internal 8.5MHz oscillator divided by 256" option results in higher
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deep sleep current (by 5uA) but has better frequency stability than
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the internal 150kHz oscillator. It does not require external components.
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config ESP32_RTC_CLK_SRC_INT_RC
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bool "Internal 150kHz RC oscillator"
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config ESP32_RTC_CLK_SRC_EXT_XTAL
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bool "External 32kHz crystal"
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select ESP_SYSTEM_RTC_EXT_XTAL
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config ESP32_RTC_CLK_SRC_EXT_OSC
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bool "External 32kHz oscillator at 32K_XN pin"
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config ESP32_RTC_CLK_SRC_INT_8MD256
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bool "Internal 8.5MHz oscillator, divided by 256 (~33kHz)"
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endchoice
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config ESP32_RT_TIMER
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bool "Real-time Timer"
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default n
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@ -70,12 +70,36 @@
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#define DELAY_FAST_CLK_SWITCH 3
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#define XTAL_32K_DAC_VAL 3
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#define XTAL_32K_DAC_VAL 1
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#define XTAL_32K_DRES_VAL 3
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#define XTAL_32K_DBIAS_VAL 0
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#define XTAL_32K_EXT_DAC_VAL 2
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#define XTAL_32K_EXT_DRES_VAL 3
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#define XTAL_32K_EXT_DBIAS_VAL 1
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#define DELAY_SLOW_CLK_SWITCH 300
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#define DELAY_8M_ENABLE 50
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#define RETRY_CAL_EXT 1
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/* Lower threshold for a reasonably-looking calibration value for a 32k XTAL.
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* The ideal value (assuming 32768 Hz frequency)
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* is 1000000/32768*(2**19) = 16*10^6.
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*/
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#define MIN_32K_XTAL_CAL_VAL 15000000L
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/* Frequency of the 8M oscillator is 8.5MHz +/- 5%, at the default DCAP
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* setting
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*/
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#define RTC_FAST_CLK_FREQ_8M 8500000
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#define RTC_SLOW_CLK_FREQ_150K 150000
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#define RTC_SLOW_CLK_FREQ_8MD256 (RTC_FAST_CLK_FREQ_8M / 256)
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#define RTC_SLOW_CLK_FREQ_32K 32768
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/* Number of fractional bits in values returned by rtc_clk_cal */
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#define RTC_CLK_CAL_FRACT 19
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@ -237,6 +261,9 @@ static uint32_t IRAM_ATTR esp32_rtc_clk_cal_internal(
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static void IRAM_ATTR esp32_rtc_clk_slow_freq_set(
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enum esp32_rtc_slow_freq_e slow_freq);
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static void esp32_select_rtc_slow_clk(enum esp32_slow_clk_sel_e slow_clk);
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static void esp32_rtc_clk_32k_enable(int ac, int res, int bias);
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static void IRAM_ATTR esp32_rtc_clk_8m_enable(bool clk_8m_en, bool d256_en);
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static uint32_t IRAM_ATTR esp32_rtc_clk_slow_freq_get_hz(void);
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#ifdef CONFIG_RTC_DRIVER
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static void IRAM_ATTR esp32_rt_cb_handler(FAR void *arg);
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@ -285,8 +312,6 @@ volatile bool g_rtc_enabled = false;
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* Private Functions
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****************************************************************************/
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extern void ets_delay_us(uint32_t us);
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/****************************************************************************
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* Name: esp32_rtc_sleep_pd
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*
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@ -338,7 +363,7 @@ static void IRAM_ATTR esp32_rtc_clk_fast_freq_set(
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enum esp32_rtc_fast_freq_e fast_freq)
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{
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REG_SET_FIELD(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_FAST_CLK_RTC_SEL, fast_freq);
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ets_delay_us(DELAY_FAST_CLK_SWITCH);
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up_udelay(DELAY_FAST_CLK_SWITCH);
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}
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/****************************************************************************
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@ -375,7 +400,9 @@ static inline bool esp32_clk_val_is_valid(uint32_t val)
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* slowclk_cycles - number of slow clock cycles to count.
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*
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* Returned Value:
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* Number of XTAL clock cycles within the given number of slow clock cycles
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* Number of XTAL clock cycles within the given number of slow clock
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* cycles.
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* In case of error, return 0 cycle.
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*
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****************************************************************************/
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@ -385,21 +412,26 @@ static uint32_t IRAM_ATTR esp32_rtc_clk_cal_internal(
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uint32_t expected_freq;
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uint32_t us_time_estimate;
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uint32_t us_timer_max;
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uint32_t clks_state;
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uint32_t clks_mask;
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int timeout_us;
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enum esp32_rtc_slow_freq_e slow_freq;
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enum esp32_rtc_xtal_freq_e xtal_freq;
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/* Get the current state */
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clks_mask = (RTC_CNTL_DIG_XTAL32K_EN_M | RTC_CNTL_DIG_CLK8M_D256_EN_M);
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clks_state = getreg32(RTC_CNTL_CLK_CONF_REG);
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clks_state &= clks_mask;
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/* Enable requested clock (150k clock is always on) */
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int dig_32k_xtal_state = REG_GET_FIELD(RTC_CNTL_CLK_CONF_REG,
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RTC_CNTL_DIG_XTAL32K_EN);
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if (cal_clk == RTC_CAL_32K_XTAL && !dig_32k_xtal_state)
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if (cal_clk == RTC_CAL_32K_XTAL && !(clks_state & RTC_CNTL_DIG_XTAL32K_EN))
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{
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REG_SET_FIELD(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_DIG_XTAL32K_EN, 1);
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}
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if (cal_clk == RTC_CAL_8MD256)
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else if (cal_clk == RTC_CAL_8MD256 &&
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!(clks_state & RTC_CNTL_DIG_CLK8M_D256_EN))
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{
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modifyreg32(RTC_CNTL_CLK_CONF_REG, 0, RTC_CNTL_DIG_CLK8M_D256_EN);
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}
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@ -414,13 +446,11 @@ static uint32_t IRAM_ATTR esp32_rtc_clk_cal_internal(
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slow_freq = REG_GET_FIELD(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_ANA_CLK_RTC_SEL);
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if (cal_clk == RTC_CAL_32K_XTAL ||
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(cal_clk == RTC_CAL_RTC_MUX && slow_freq == RTC_SLOW_FREQ_32K_XTAL))
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if (cal_clk == RTC_CAL_32K_XTAL || slow_freq == RTC_SLOW_FREQ_32K_XTAL)
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{
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expected_freq = 32768; /* standard 32k XTAL */
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}
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else if (cal_clk == RTC_CAL_8MD256 ||
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(cal_clk == RTC_CAL_RTC_MUX && slow_freq == RTC_SLOW_FREQ_8MD256))
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else if (cal_clk == RTC_CAL_8MD256 || slow_freq == RTC_SLOW_FREQ_8MD256)
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{
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expected_freq = RTC_FAST_CLK_FREQ_APPROX / 256;
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}
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@ -448,6 +478,7 @@ static uint32_t IRAM_ATTR esp32_rtc_clk_cal_internal(
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if (us_time_estimate >= us_timer_max)
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{
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rtcerr("Estimated time overflows TIMG_RTC_CALI_VALUE\n");
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return 0;
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}
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@ -456,12 +487,9 @@ static uint32_t IRAM_ATTR esp32_rtc_clk_cal_internal(
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modifyreg32(TIMG_RTCCALICFG_REG(0), TIMG_RTC_CALI_START, 0);
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modifyreg32(TIMG_RTCCALICFG_REG(0), 0, TIMG_RTC_CALI_START);
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/* Wait the expected time calibration should take.
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* TODO: if running under RTOS, and us_time_estimate > RTOS tick, use the
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* RTOS delay function.
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*/
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/* Wait the expected time calibration should take */
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ets_delay_us(us_time_estimate);
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up_udelay(us_time_estimate);
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/* Wait for calibration to finish up to another us_time_estimate */
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@ -470,21 +498,20 @@ static uint32_t IRAM_ATTR esp32_rtc_clk_cal_internal(
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TIMG_RTC_CALI_RDY) && (timeout_us > 0))
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{
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timeout_us--;
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ets_delay_us(1);
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up_udelay(1);
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}
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REG_SET_FIELD(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_DIG_XTAL32K_EN,
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dig_32k_xtal_state);
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/* Restore the previous clocks states */
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if (cal_clk == RTC_CAL_8MD256)
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{
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modifyreg32(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_DIG_CLK8M_D256_EN, 0);
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}
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modifyreg32(RTC_CNTL_CLK_CONF_REG, clks_mask, clks_state);
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/* Verify if this calibration occured within the timeout */
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if (timeout_us == 0)
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{
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/* timed out waiting for calibration */
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/* Timed out waiting for calibration */
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rtcerr("Timed out waiting for calibration\n");
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return 0;
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}
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@ -513,7 +540,116 @@ static void IRAM_ATTR esp32_rtc_clk_slow_freq_set(
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REG_SET_FIELD(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_DIG_XTAL32K_EN,
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(slow_freq == RTC_SLOW_FREQ_32K_XTAL) ? 1 : 0);
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ets_delay_us(DELAY_SLOW_CLK_SWITCH);
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up_udelay(DELAY_SLOW_CLK_SWITCH);
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}
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/****************************************************************************
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* Name: esp32_rtc_clk_32k_enable
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*
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* Description:
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* Enable 32 kHz XTAL oscillator
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*
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* Input Parameters:
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* ac - The current of XTAL oscillator.
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* res - The resistance of XTAL oscillator.
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* bias - The bias voltage of XTAL oscillator.
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*
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* Returned Value:
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* None
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*
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****************************************************************************/
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static void esp32_rtc_clk_32k_enable(int ac, int res, int bias)
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{
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modifyreg32(RTC_IO_XTAL_32K_PAD_REG, RTC_IO_X32P_RDE | RTC_IO_X32P_RUE |
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RTC_IO_X32N_RUE | RTC_IO_X32N_RDE | RTC_IO_X32N_FUN_IE |
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RTC_IO_X32P_FUN_IE, RTC_IO_X32N_MUX_SEL | RTC_IO_X32P_MUX_SEL);
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/* Set the parameters of xtal */
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REG_SET_FIELD(RTC_IO_XTAL_32K_PAD_REG, RTC_IO_DAC_XTAL_32K, ac);
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REG_SET_FIELD(RTC_IO_XTAL_32K_PAD_REG, RTC_IO_DRES_XTAL_32K, res);
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REG_SET_FIELD(RTC_IO_XTAL_32K_PAD_REG, RTC_IO_DBIAS_XTAL_32K, bias);
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/* Power up external xtal */
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modifyreg32(RTC_IO_XTAL_32K_PAD_REG, 0, RTC_IO_XPD_XTAL_32K_M);
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}
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/****************************************************************************
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* Name: esp32_rtc_clk_8m_enable
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*
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* Description:
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* Enable or disable 8 MHz internal oscillator
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*
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* Input Parameters:
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* clk_8m_en - true to enable 8MHz generator, false to disable
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* d256_en - true to enable /256 divider, false to disable
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*
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* Returned Value:
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* None
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*
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****************************************************************************/
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static void IRAM_ATTR esp32_rtc_clk_8m_enable(bool clk_8m_en, bool d256_en)
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{
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if (clk_8m_en)
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{
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modifyreg32(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_ENB_CK8M, 0);
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/* no need to wait once enabled by software */
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REG_SET_FIELD(RTC_CNTL_TIMER1_REG, RTC_CNTL_CK8M_WAIT, 1);
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if (d256_en)
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{
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modifyreg32(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_ENB_CK8M_DIV, 0);
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}
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else
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{
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modifyreg32(RTC_CNTL_CLK_CONF_REG, 0, RTC_CNTL_ENB_CK8M_DIV);
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}
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up_udelay(DELAY_8M_ENABLE);
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}
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else
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{
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modifyreg32(RTC_CNTL_CLK_CONF_REG, 0, RTC_CNTL_ENB_CK8M);
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REG_SET_FIELD(RTC_CNTL_TIMER1_REG, RTC_CNTL_CK8M_WAIT,
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RTC_CNTL_CK8M_WAIT_DEFAULT);
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}
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}
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/****************************************************************************
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* Name: esp32_rtc_clk_slow_freq_get_hz
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*
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* Description:
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* Get the approximate frequency of RTC_SLOW_CLK, in Hz
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*
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* Input Parameters:
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* None
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*
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* Returned Value:
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* slow_clk_freq - RTC_SLOW_CLK frequency, in Hz
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*
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****************************************************************************/
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static uint32_t IRAM_ATTR esp32_rtc_clk_slow_freq_get_hz(void)
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{
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enum esp32_rtc_slow_freq_e slow_clk_freq =
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REG_GET_FIELD(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_ANA_CLK_RTC_SEL);
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switch (slow_clk_freq)
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{
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case RTC_SLOW_FREQ_RTC:
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return RTC_SLOW_CLK_FREQ_150K;
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case RTC_SLOW_FREQ_32K_XTAL:
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return RTC_SLOW_CLK_FREQ_32K;
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case RTC_SLOW_FREQ_8MD256:
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return RTC_SLOW_CLK_FREQ_8MD256;
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}
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return OK;
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}
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/****************************************************************************
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@ -532,22 +668,79 @@ static void IRAM_ATTR esp32_rtc_clk_slow_freq_set(
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static void esp32_select_rtc_slow_clk(enum esp32_slow_clk_sel_e slow_clk)
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{
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/* Number of times to repeat 32k XTAL calibration before giving up and
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* switching to the internal RC.
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*/
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int retry_32k_xtal = RETRY_CAL_EXT;
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uint32_t cal_val = 0;
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uint64_t cal_dividend;
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enum esp32_rtc_slow_freq_e rtc_slow_freq = slow_clk &
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RTC_CNTL_ANA_CLK_RTC_SEL_V;
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do
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{
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if (rtc_slow_freq == RTC_SLOW_FREQ_32K_XTAL)
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{
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/* 32k XTAL oscillator needs to be enabled and running before
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* it can be used. Hardware doesn't have a direct way of checking
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* if the oscillator is running. Here we use rtc_clk_cal function
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* to count the number of main XTAL cycles in the given number of
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* 32k XTAL oscillator cycles. If the 32k XTAL has not started up,
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* calibration will time out, returning 0.
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*/
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rtcinfo("Waiting for 32k oscillator to start up\n");
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if (slow_clk == SLOW_CLK_32K_XTAL)
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{
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esp32_rtc_clk_32k_enable(XTAL_32K_DAC_VAL, XTAL_32K_DRES_VAL,
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XTAL_32K_DBIAS_VAL);
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}
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else if (slow_clk == SLOW_CLK_32K_EXT_OSC)
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{
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esp32_rtc_clk_32k_enable(XTAL_32K_EXT_DAC_VAL,
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XTAL_32K_EXT_DRES_VAL, XTAL_32K_EXT_DBIAS_VAL);
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}
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if (SLOW_CLK_CAL_CYCLES > 0)
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{
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cal_val = esp32_rtc_clk_cal(RTC_CAL_32K_XTAL,
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SLOW_CLK_CAL_CYCLES);
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if (cal_val == 0 || cal_val < MIN_32K_XTAL_CAL_VAL)
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{
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if (retry_32k_xtal-- > 0)
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{
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continue;
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}
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rtc_slow_freq = RTC_SLOW_FREQ_RTC;
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}
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}
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}
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else if (rtc_slow_freq == RTC_SLOW_FREQ_8MD256)
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{
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esp32_rtc_clk_8m_enable(true, true);
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}
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esp32_rtc_clk_slow_freq_set(rtc_slow_freq);
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if (SLOW_CLK_CAL_CYCLES > 0)
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{
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/* 32k XTAL oscillator has some frequency drift at startup. Improve
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* calibration routine to wait until the frequency is stable.
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*/
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/* TODO: 32k XTAL oscillator has some frequency drift at startup.
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* Improve calibration routine to wait until the frequency is stable.
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*/
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cal_val = esp32_rtc_clk_cal(RTC_CAL_RTC_MUX, SLOW_CLK_CAL_CYCLES);
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cal_val = esp32_rtc_clk_cal(RTC_CAL_RTC_MUX,
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SLOW_CLK_CAL_CYCLES);
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}
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else
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{
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cal_dividend = (1ULL << RTC_CLK_CAL_FRACT) * 1000000ULL;
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cal_val = (uint32_t) (cal_dividend /
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esp32_rtc_clk_slow_freq_get_hz());
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}
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}
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while (cal_val == 0);
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rtcinfo("RTC_SLOW_CLK calibration value: %d\n", cal_val);
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putreg32((uint32_t)cal_val, RTC_SLOW_CLK_CAL_REG);
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}
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@ -867,7 +1060,7 @@ void IRAM_ATTR esp32_rtc_bbpll_configure(
|
||||
/* Raise the voltage */
|
||||
|
||||
REG_SET_FIELD(RTC_CNTL_REG, RTC_CNTL_DIG_DBIAS_WAK, DIG_DBIAS_240M);
|
||||
ets_delay_us(DELAY_PLL_DBIAS_RAISE);
|
||||
up_udelay(DELAY_PLL_DBIAS_RAISE);
|
||||
|
||||
/* Configure 480M PLL */
|
||||
|
||||
@ -948,7 +1141,16 @@ void IRAM_ATTR esp32_rtc_bbpll_configure(
|
||||
void esp32_rtc_clk_set(void)
|
||||
{
|
||||
enum esp32_rtc_fast_freq_e fast_freq = RTC_FAST_FREQ_8M;
|
||||
enum esp32_slow_clk_sel_e slow_clk = RTC_SLOW_FREQ_RTC;
|
||||
enum esp32_slow_clk_sel_e slow_clk = SLOW_CLK_150K;
|
||||
|
||||
#if defined(CONFIG_ESP32_RTC_CLK_SRC_EXT_CRYS)
|
||||
slow_clk = SLOW_CLK_32K_XTAL;
|
||||
#elif defined(CONFIG_ESP32_RTC_CLK_SRC_EXT_OSC)
|
||||
slow_clk = SLOW_CLK_32K_EXT_OSC;
|
||||
#elif defined(CONFIG_ESP32_RTC_CLK_SRC_INT_8MD256)
|
||||
slow_clk = SLOW_CLK_8MD256;
|
||||
#endif
|
||||
|
||||
esp32_rtc_clk_fast_freq_set(fast_freq);
|
||||
esp32_select_rtc_slow_clk(slow_clk);
|
||||
}
|
||||
@ -1094,7 +1296,7 @@ uint64_t IRAM_ATTR esp32_rtc_time_get(void)
|
||||
|
||||
while ((getreg32(RTC_CNTL_TIME_UPDATE_REG) & RTC_CNTL_TIME_VALID) == 0)
|
||||
{
|
||||
ets_delay_us(1);
|
||||
up_udelay(1);
|
||||
}
|
||||
|
||||
modifyreg32(RTC_CNTL_INT_CLR_REG, 0, RTC_CNTL_TIME_VALID_INT_CLR);
|
||||
@ -1115,18 +1317,27 @@ uint64_t IRAM_ATTR esp32_rtc_time_get(void)
|
||||
* slow_clk_period - Period of slow clock in microseconds
|
||||
*
|
||||
* Returned Value:
|
||||
* number of slow clock cycles
|
||||
* Number of slow clock cycles
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
uint64_t IRAM_ATTR esp32_rtc_time_us_to_slowclk(uint64_t time_in_us,
|
||||
uint32_t period)
|
||||
{
|
||||
/* Overflow will happen in this function if time_in_us >= 2^45,
|
||||
* which is about 400 days. TODO: fix overflow.
|
||||
*/
|
||||
uint64_t slow_clk_cycles = 0;
|
||||
uint64_t max_time_in_us = (UINT64_C(1) << 45) - 1;
|
||||
|
||||
return (time_in_us << RTC_CLK_CAL_FRACT) / period;
|
||||
/* Handle overflow that would happen if time_in_us >= 2^45 */
|
||||
|
||||
while (time_in_us > max_time_in_us)
|
||||
{
|
||||
time_in_us -= max_time_in_us;
|
||||
slow_clk_cycles += ((max_time_in_us << RTC_CLK_CAL_FRACT) / period);
|
||||
}
|
||||
|
||||
slow_clk_cycles += ((time_in_us << RTC_CLK_CAL_FRACT) / period);
|
||||
|
||||
return slow_clk_cycles;
|
||||
}
|
||||
|
||||
/****************************************************************************
|
||||
@ -1252,11 +1463,11 @@ void IRAM_ATTR esp32_rtc_wait_for_slow_cycle(void)
|
||||
|
||||
/* RDY needs some time to go low */
|
||||
|
||||
ets_delay_us(1);
|
||||
up_udelay(1);
|
||||
|
||||
while (!(getreg32(TIMG_RTCCALICFG_REG(0)) & TIMG_RTC_CALI_RDY))
|
||||
{
|
||||
ets_delay_us(1);
|
||||
up_udelay(1);
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
@ -505,8 +505,8 @@ static int esp32_wdt_pre(FAR struct esp32_wdt_dev_s *dev, uint16_t pre)
|
||||
* Name: esp32_rtc_clk
|
||||
*
|
||||
* Description:
|
||||
* Check the RTC clock source and return the necessary cycles to complete
|
||||
* 1 ms. NOTE: TODO.
|
||||
* Check the RTC clock source and return the necessary cycles to complete
|
||||
* 1 ms.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
@ -528,6 +528,10 @@ static uint16_t esp32_rtc_clk(FAR struct esp32_wdt_dev_s *dev)
|
||||
|
||||
period_13q19 = esp32_rtc_clk_cal(slow_clk_rtc, SLOW_CLK_CAL_CYCLES);
|
||||
|
||||
/* Assert no error happened during the calibration */
|
||||
|
||||
DEBUGASSERT(period_13q19 != 0);
|
||||
|
||||
/* Convert from Q13.19 format to float */
|
||||
|
||||
period = Q_TO_FLOAT(period_13q19);
|
||||
|
||||
Loading…
Reference in New Issue
Block a user