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Add an NSH configuration for the Arduino Due; Pluse several fixes related to the Due and to the SAM3X in general

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This commit is contained in:
Gregory Nutt 2013-06-28 14:32:08 -06:00
parent 4fe041a10b
commit 880d7f261b
2 changed files with 11 additions and 1 deletions
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2
arch/arm/src/sam34/chip/sam3x_memorymap.h
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@ -65,7 +65,7 @@
/* Internal SRAM memory region */
#define SAM_INTSRAM0_BASE 0x20000000 /* 0x20000000-0x2007ffff: Internal SRAM 0 */
#define SAM_INTSRAM1_BASE 0x20080000 /* 0x20080000-0x200fffff: Internal SRAM 0 */
#define SAM_INTSRAM1_BASE 0x20080000 /* 0x20080000-0x200fffff: Internal SRAM 1 */
#define SAM_NFCSRAM_BASE 0x20100000 /* 0x20100000-0x2017ffff: NAND FLASH controller (SRAM) */
#define SAM_UOTGHSRAM_BASE 0x20180000 /* 0x20100000-0x201fffff: UOTGHS controller (DMA) */
/* 0x20200000-0x201fffff: Undefined */

10
arch/arm/src/sam34/sam_allocateheap.c
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@ -53,6 +53,7 @@
#include "chip.h"
#include "sam_mpuinit.h"
#include "sam_periphclks.h"
/****************************************************************************
* Private Definitions
@ -317,6 +318,15 @@ void up_addregion(void)
#endif /* HAVE_SRAM1_REGION */
#ifdef HAVE_NFCSRAM_REGION
#if defined(CONFIG_ARCH_CHIP_SAM3X) || defined(CONFIG_ARCH_CHIP_SAM3A)
/* In the 3X/3A family I note that clocking must appled to the SMC module
* in order for the NFCS SRAM to be functional. I don't recall such an
* issue with the 3U.
*/
sam_smc_enableclk();
#endif
/* Allow user access to the heap memory */
sam_mpu_uheap(SAM_NFCSRAM_BASE, SAM34_NFCSRAM_SIZE);