From 8846bb9c1cc10c83ef2ec0c6417530c3ae0e21c1 Mon Sep 17 00:00:00 2001 From: Titus von Boxberg Date: Wed, 19 Jul 2017 20:40:10 +0200 Subject: [PATCH] Updated linker maps for STM32F769NI --- configs/stm32f769i-disco/scripts/flash.ld | 20 +++++++-------- configs/stm32f769i-disco/scripts/memory.ld | 30 +++++++++++----------- 2 files changed, 25 insertions(+), 25 deletions(-) diff --git a/configs/stm32f769i-disco/scripts/flash.ld b/configs/stm32f769i-disco/scripts/flash.ld index 2def39783c..51a2cbbea3 100644 --- a/configs/stm32f769i-disco/scripts/flash.ld +++ b/configs/stm32f769i-disco/scripts/flash.ld @@ -35,12 +35,12 @@ * ****************************************************************************/ -/* The STM32F769NIH6 has 1024Kb of main FLASH memory. This FLASH memory can +/* The STM32F769NIH6 has 2048Kb of main FLASH memory. This FLASH memory can * be accessed from either the AXIM interface at address 0x0800:0000 or from * the ITCM interface at address 0x0020:0000. * * Additional information, including the option bytes, is available at at - * FLASH at address 0x1ff0:0000 (AXIM) or 0x0010:0000 (ITCM). + * FLASH at address 0x1ff0:0000. * * In the STM32F769NIH6, two different boot spaces can be selected through * the BOOT pin and the boot base address programmed in the BOOT_ADD0 and @@ -51,16 +51,16 @@ * 2) BOOT=1: Boot address defined by user option byte BOOT_ADD1[15:0]. * ST programmed value: System bootloader at 0x0010:0000 * - * NuttX does not modify these option byes. On the unmodified STM32F769I + * NuttX does not modify these option bytes. On the unmodified STM32F769I * DISCO board, the BOOT0 pin is at ground so by default, the STM32 will boot * to address 0x0020:0000 in ITCM FLASH. * - * The STM32F769NIH6 also has 320Kb of data SRAM (in addition to ITCM SRAM). + * The STM32F769NIH6 also has 512Kb of data SRAM (in addition to ITCM SRAM). * SRAM is split up into three blocks: * - * 1) 64Kb of DTCM SRM beginning at address 0x2000:0000 - * 2) 240Kb of SRAM1 beginning at address 0x2001:0000 - * 3) 16Kb of SRAM2 beginning at address 0x2004:c000 + * 1) 128Kb of DTCM SRM beginning at address 0x2000:0000 + * 2) 368Kb of SRAM1 beginning at address 0x2002:0000 + * 3) 16Kb of SRAM2 beginning at address 0x2007:c000 * * When booting from FLASH, FLASH memory is aliased to address 0x0000:0000 * where the code expects to begin execution by jumping to the entry point in @@ -71,9 +71,9 @@ MEMORY { itcm (rwx) : ORIGIN = 0x00200000, LENGTH = 1024K flash (rx) : ORIGIN = 0x08000000, LENGTH = 1024K - dtcm (rwx) : ORIGIN = 0x20000000, LENGTH = 64K - sram1 (rwx) : ORIGIN = 0x20010000, LENGTH = 240K - sram2 (rwx) : ORIGIN = 0x2004c000, LENGTH = 16K + dtcm (rwx) : ORIGIN = 0x20000000, LENGTH = 128K + sram1 (rwx) : ORIGIN = 0x20020000, LENGTH = 368K + sram2 (rwx) : ORIGIN = 0x2007c000, LENGTH = 16K } OUTPUT_ARCH(arm) diff --git a/configs/stm32f769i-disco/scripts/memory.ld b/configs/stm32f769i-disco/scripts/memory.ld index 72296925a9..748620b1a8 100644 --- a/configs/stm32f769i-disco/scripts/memory.ld +++ b/configs/stm32f769i-disco/scripts/memory.ld @@ -33,12 +33,12 @@ * ****************************************************************************/ -/* The STM32F769NIH6 has 1024Kb of main FLASH memory. This FLASH memory can +/* The STM32F769NIH6 has 2048Kb of main FLASH memory. This FLASH memory can * be accessed from either the AXIM interface at address 0x0800:0000 or from * the ITCM interface at address 0x0020:0000. * * Additional information, including the option bytes, is available at at - * FLASH at address 0x1ff0:0000 (AXIM) or 0x0010:0000 (ITCM). + * FLASH at address 0x1ff0:0000. * * In the STM32F769NIH6, two different boot spaces can be selected through * the BOOT pin and the boot base address programmed in the BOOT_ADD0 and @@ -49,16 +49,16 @@ * 2) BOOT=1: Boot address defined by user option byte BOOT_ADD1[15:0]. * ST programmed value: System bootloader at 0x0010:0000 * - * NuttX does not modify these option byes. On the unmodified STM32F769I + * NuttX does not modify these option bytes. On the unmodified STM32F769I * DISCO board, the BOOT0 pin is at ground so by default, the STM32 will boot * to address 0x0020:0000 in ITCM FLASH. * - * The STM32F769NIH6 also has 320Kb of data SRAM (in addition to ITCM SRAM). + * The STM32F769NIH6 also has 512Kb of data SRAM (in addition to ITCM SRAM). * SRAM is split up into three blocks: * - * 1) 64Kb of DTCM SRM beginning at address 0x2000:0000 - * 2) 240Kb of SRAM1 beginning at address 0x2001:0000 - * 3) 16Kb of SRAM2 beginning at address 0x2004:c000 + * 1) 128Kb of DTCM SRM beginning at address 0x2000:0000 + * 2) 368Kb of SRAM1 beginning at address 0x2002:0000 + * 3) 16Kb of SRAM2 beginning at address 0x2007:c000 * * When booting from FLASH, FLASH memory is aliased to address 0x0000:0000 * where the code expects to begin execution by jumping to the entry point in @@ -108,22 +108,22 @@ MEMORY { /* ITCM boot address */ - itcm (rwx) : ORIGIN = 0x00200000, LENGTH = 1024K + itcm (rwx) : ORIGIN = 0x00200000, LENGTH = 2048K - /* 1024KB FLASH */ + /* 2048KB FLASH */ kflash (rx) : ORIGIN = 0x08000000, LENGTH = 128K uflash (rx) : ORIGIN = 0x08020000, LENGTH = 128K - xflash (rx) : ORIGIN = 0x08040000, LENGTH = 768K + xflash (rx) : ORIGIN = 0x08040000, LENGTH = 1792K - /* 240KB of contiguous SRAM1 */ + /* 368KB of contiguous SRAM1 */ ksram (rwx) : ORIGIN = 0x20010000, LENGTH = 4K usram (rwx) : ORIGIN = 0x20011000, LENGTH = 4K - xsram (rwx) : ORIGIN = 0x20012000, LENGTH = 240K - 8K + xsram (rwx) : ORIGIN = 0x20012000, LENGTH = 368K - 8K - /* DTCM SRAM */ + /* DTCM SRAM */ - dtcm (rwx) : ORIGIN = 0x20000000, LENGTH = 64K - sram2 (rwx) : ORIGIN = 0x2004c000, LENGTH = 16K + dtcm (rwx) : ORIGIN = 0x20000000, LENGTH = 128K + sram2 (rwx) : ORIGIN = 0x2007c000, LENGTH = 16K }