arch/arm/samv7: fix print specifiers issues
Signed-off-by: Petro Karashchenko <petro.karashchenko@gmail.com>
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afaa2028f6
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88c1a55efd
@ -98,9 +98,9 @@
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* occur in multiples of full change lines.
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*/
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#ifdef CONFIG_ARMV7M_DCACHE
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#ifdef CONFIG_ARCH_DCACHE
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# define MCAN_ALIGN ARMV7M_DCACHE_LINESIZE
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# define MCAN_ALIGN_MASK (MCAN_ALIGN-1)
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# define MCAN_ALIGN_MASK (MCAN_ALIGN - 1)
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# define MCAN_ALIGN_UP(n) (((n) + MCAN_ALIGN_MASK) & ~MCAN_ALIGN_MASK)
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# ifndef CONFIG_ARMV7M_DCACHE_WRITETHROUGH
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@ -729,7 +729,7 @@
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*/
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#define MCAN_RXCOMMON_INTS_REVA (MCAN_INT_CRCE | MCAN_INT_FOE | MCAN_INT_STE)
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#define MCAN_RXCOMMON_INTS (MCAN_INT_PEA | MCAN_INT_PED)
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#define MCAN_RXCOMMON_INTS (MCAN_INT_PEA | MCAN_INT_PED)
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#define MCAN_RXFIFO0_INTS (MCAN_INT_RF0N | MCAN_INT_RF0W | MCAN_INT_RF0L)
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#define MCAN_RXFIFO1_INTS (MCAN_INT_RF1N | MCAN_INT_RF1W | MCAN_INT_RF1L)
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#define MCAN_RXFIFO_INTS (MCAN_RXFIFO0_INTS | MCAN_RXFIFO1_INTS | \
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@ -738,7 +738,7 @@
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#define MCAN_RXERR_INTS_REVA (MCAN_INT_RF0L | MCAN_INT_RF1L | MCAN_INT_CRCE | \
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MCAN_INT_FOE | MCAN_INT_STE)
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#define MCAN_RXERR_INTS (MCAN_INT_RF0L | MCAN_INT_RF1L | MCAN_INT_PEA | \
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#define MCAN_RXERR_INTS (MCAN_INT_RF0L | MCAN_INT_RF1L | MCAN_INT_PEA | \
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MCAN_INT_PED)
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/* TX FIFOQ mode interrupts
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@ -929,11 +929,11 @@ static uint8_t mcan_bytes2dlc(struct sam_mcan_s *priv, uint8_t nbytes);
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#ifdef CONFIG_CAN_EXTID
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static int mcan_add_extfilter(struct sam_mcan_s *priv,
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struct canioc_extfilter_s *extconfig);
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struct canioc_extfilter_s *extconfig);
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static int mcan_del_extfilter(struct sam_mcan_s *priv, int ndx);
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#endif
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static int mcan_add_stdfilter(struct sam_mcan_s *priv,
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struct canioc_stdfilter_s *stdconfig);
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struct canioc_stdfilter_s *stdconfig);
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static int mcan_del_stdfilter(struct sam_mcan_s *priv, int ndx);
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/* CAN driver methods */
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@ -944,7 +944,7 @@ static void mcan_shutdown(struct can_dev_s *dev);
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static void mcan_rxint(struct can_dev_s *dev, bool enable);
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static void mcan_txint(struct can_dev_s *dev, bool enable);
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static int mcan_ioctl(struct can_dev_s *dev, int cmd,
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unsigned long arg);
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unsigned long arg);
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static int mcan_remoterequest(struct can_dev_s *dev, uint16_t id);
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static int mcan_send(struct can_dev_s *dev, struct can_msg_s *msg);
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static bool mcan_txready(struct can_dev_s *dev);
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@ -954,7 +954,7 @@ static bool mcan_txempty(struct can_dev_s *dev);
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#if 0 /* Not Used */
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static bool mcan_dedicated_rxbuffer_available(struct sam_mcan_s *priv,
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int bufndx);
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int bufndx);
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#endif
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#ifdef CONFIG_CAN_ERRORS
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static void mcan_error(struct can_dev_s *dev, uint32_t status);
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@ -986,10 +986,11 @@ static const struct can_ops_s g_mcanops =
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};
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#ifdef CONFIG_SAMV7_MCAN0
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/* Message RAM allocation */
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/* MCAN0 message RAM allocation */
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static uint32_t g_mcan0_msgram[MCAN0_MSGRAM_WORDS]
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#ifdef CONFIG_ARMV7M_DCACHE
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#ifdef CONFIG_ARCH_DCACHE
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__attribute__((aligned(MCAN_ALIGN)));
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#else
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;
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@ -1084,10 +1085,11 @@ static struct can_dev_s g_mcan0dev =
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#endif /* CONFIG_SAMV7_MCAN0 */
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#ifdef CONFIG_SAMV7_MCAN1
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/* MCAN1 message RAM allocation */
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static uint32_t g_mcan1_msgram[MCAN1_MSGRAM_WORDS]
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#ifdef CONFIG_ARMV7M_DCACHE
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#ifdef CONFIG_ARCH_DCACHE
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__attribute__((aligned(MCAN_ALIGN)));
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#else
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;
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@ -1249,7 +1251,7 @@ static uint32_t mcan_getreg(struct sam_mcan_s *priv, int offset)
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/* Show the register value read */
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caninfo("%08x->%08x\n", regaddr, regval);
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caninfo("%08" PRIx32 "->%08" PRIx32 "\n", regaddr, regval);
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return regval;
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}
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@ -1287,7 +1289,7 @@ static void mcan_putreg(struct sam_mcan_s *priv, int offset,
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/* Show the register value being written */
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caninfo("%08x<-%08x\n", regaddr, regval);
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caninfo("%08" PRIx32 "<-%08" PRIx32 "\n", regaddr, regval);
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/* Write the value */
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@ -1299,6 +1301,7 @@ static void mcan_putreg(struct sam_mcan_s *priv, int offset,
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uint32_t regval)
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{
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const struct sam_config_s *config = priv->config;
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putreg32(regval, config->base + offset);
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}
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@ -1601,7 +1604,7 @@ static void mcan_buffer_release(struct sam_mcan_s *priv)
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else
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{
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canerr("ERROR: txfsem would increment beyond %d\n",
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priv->config->ntxfifoq);
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priv->config->ntxfifoq);
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}
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}
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@ -2940,7 +2943,7 @@ static int mcan_send(struct can_dev_s *dev, struct can_msg_s *msg)
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config = priv->config;
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caninfo("MCAN%d\n", config->port);
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caninfo("MCAN%d ID: %"PRIu32" DLC: %u\n",
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caninfo("MCAN%d ID: %" PRIu32 " DLC: %u\n",
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config->port, (uint32_t)msg->cm_hdr.ch_id, msg->cm_hdr.ch_dlc);
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/* That that FIFO elements were configured.
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@ -3019,7 +3022,7 @@ static int mcan_send(struct can_dev_s *dev, struct can_msg_s *msg)
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}
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txbuffer[0] = regval;
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reginfo("T0: %08x\n", regval);
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reginfo("T0: %08" PRIx32 "\n", regval);
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/* Format word T1:
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* Data Length Code (DLC) - Value from message structure
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@ -3041,7 +3044,7 @@ static int mcan_send(struct can_dev_s *dev, struct can_msg_s *msg)
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}
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#endif
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reginfo("T1: %08x\n", txbuffer[1]);
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reginfo("T1: %08" PRIx32 "\n", txbuffer[1]);
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/* Followed by the amount of data corresponding to the DLC (T2..) */
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@ -3189,7 +3192,7 @@ static bool mcan_txempty(struct can_dev_s *dev)
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*/
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regval = mcan_getreg(priv, SAM_MCAN_TXFQS_OFFSET);
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if (((regval & MCAN_TXFQS_TFQF) != 0))
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if ((regval & MCAN_TXFQS_TFQF) != 0)
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{
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nxmutex_unlock(&priv->lock);
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return false;
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@ -3371,9 +3374,9 @@ static void mcan_error(struct can_dev_s *dev, uint32_t status)
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data[3] |= (CAN_ERROR3_CRCSEQ | CAN_ERROR3_CRCDEL);
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}
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if ((lec == MCAN_PSR_EC_BIT0_ERROR) || \
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(lec == MCAN_PSR_EC_BIT1_ERROR) || \
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(dlec == MCAN_PSR_EC_BIT0_ERROR) || \
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if ((lec == MCAN_PSR_EC_BIT0_ERROR) ||
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(lec == MCAN_PSR_EC_BIT1_ERROR) ||
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(dlec == MCAN_PSR_EC_BIT0_ERROR) ||
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(dlec == MCAN_PSR_EC_BIT1_ERROR))
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{
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/* Bit Error */
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@ -3389,8 +3392,8 @@ static void mcan_error(struct can_dev_s *dev, uint32_t status)
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errbits |= CAN_ERROR_NOACK;
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}
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if ((lec == MCAN_PSR_EC_FORM_ERROR) || \
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(dlec == MCAN_PSR_EC_FORM_ERROR))
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if ((lec == MCAN_PSR_EC_FORM_ERROR) ||
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(dlec == MCAN_PSR_EC_FORM_ERROR))
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{
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/* Format Error */
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@ -3398,8 +3401,8 @@ static void mcan_error(struct can_dev_s *dev, uint32_t status)
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data[2] |= CAN_ERROR2_FORM;
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}
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if ((lec == MCAN_PSR_EC_STUFF_ERROR) || \
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(dlec == MCAN_PSR_EC_STUFF_ERROR))
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if ((lec == MCAN_PSR_EC_STUFF_ERROR) ||
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(dlec == MCAN_PSR_EC_STUFF_ERROR))
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{
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/* Stuff Error */
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@ -3465,10 +3468,10 @@ static void mcan_receive(struct can_dev_s *dev, uint32_t *rxbuffer,
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/* Format the CAN header */
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/* Work R0 contains the CAN ID */
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/* Word R0 contains the CAN ID */
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regval = *rxbuffer++;
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reginfo("R0: %08x\n", regval);
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reginfo("R0: %08" PRIx32 "\n", regval);
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#ifdef CONFIG_CAN_ERRORS
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hdr.ch_error = 0;
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@ -3516,7 +3519,7 @@ static void mcan_receive(struct can_dev_s *dev, uint32_t *rxbuffer,
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/* Word R1 contains the DLC and timestamp */
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regval = *rxbuffer++;
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reginfo("R1: %08x\n", regval);
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reginfo("R1: %08" PRIx32 "\n", regval);
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hdr.ch_dlc = (regval & BUFFER_R1_DLC_MASK) >> BUFFER_R1_DLC_SHIFT;
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@ -3601,7 +3604,7 @@ static int mcan_interrupt(int irq, void *context, void *arg)
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if ((pending & MCAN_TXERR_INTS) != 0)
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{
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psr = mcan_getreg(priv, SAM_MCAN_PSR_OFFSET);
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canerr("ERROR: TX %08"PRIx32", PSR %08"PRIx32"\n",
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canerr("ERROR: TX %08" PRIx32 ", PSR %08" PRIx32 "\n",
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pending & MCAN_TXERR_INTS, psr);
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/* An Acknowledge-Error will occur if for example the device
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@ -3645,7 +3648,7 @@ static int mcan_interrupt(int irq, void *context, void *arg)
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if ((pending & MCAN_RXERR_INTS) != 0)
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{
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psr = mcan_getreg(priv, SAM_MCAN_PSR_OFFSET);
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canerr("ERROR: RX %08"PRIx32", PSR %08"PRIx32"\n",
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canerr("ERROR: RX %08" PRIx32 ", PSR %08" PRIx32 "\n",
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pending & MCAN_RXERR_INTS, psr);
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/* To prevent Interrupt-Flooding the current active
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@ -3688,8 +3691,8 @@ static int mcan_interrupt(int irq, void *context, void *arg)
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ie |= MCAN_INT_ACKE;
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mcan_putreg(priv, SAM_MCAN_IE_OFFSET, ie);
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}
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else if ((priv->rev == 1) && \
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((ie & (MCAN_INT_PEA | MCAN_INT_PED)) == 0))
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else if ((priv->rev == 1) &&
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((ie & (MCAN_INT_PEA | MCAN_INT_PED)) == 0))
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{
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ie |= MCAN_INT_PEA | MCAN_INT_PED;
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mcan_putreg(priv, SAM_MCAN_IE_OFFSET, ie);
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@ -3849,7 +3852,7 @@ static int mcan_interrupt(int irq, void *context, void *arg)
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if ((regval & MCAN_RXF0S_RF0L) != 0)
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{
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canerr("ERROR: Message lost: %08"PRIx32"\n", regval);
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canerr("ERROR: Message lost: %08" PRIx32 "\n", regval);
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}
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else
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{
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