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Two changes for STM32F7.

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1) The first enables building with CONFIG_ARCH_IDLE_CUSTOM enabled.
2) The second allows changing voltage output scaling setting and prevents enabling over-drive mode for low frequencies (STM32 F74xx, 75xx, 76xx, 77xx)
This commit is contained in:
Jussi Kivilinna 2017-11-21 06:42:04 -06:00 committed by Gregory Nutt
parent 8bb54368c8
commit 88cf9cf133
3 changed files with 71 additions and 25 deletions
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6
arch/arm/src/stm32f7/Make.defs
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@ -47,13 +47,17 @@ CMN_ASRCS = up_saveusercontext.S up_fullcontextrestore.S up_switchcontext.S
CMN_ASRCS += up_testset.S vfork.S
CMN_CSRCS = up_assert.c up_blocktask.c up_copyfullstate.c up_createstack.c
CMN_CSRCS += up_mdelay.c up_udelay.c up_exit.c up_idle.c up_initialize.c
CMN_CSRCS += up_mdelay.c up_udelay.c up_exit.c up_initialize.c
CMN_CSRCS += up_initialstate.c up_interruptcontext.c up_memfault.c up_modifyreg8.c
CMN_CSRCS += up_modifyreg16.c up_modifyreg32.c up_releasepending.c
CMN_CSRCS += up_releasestack.c up_reprioritizertr.c up_schedulesigaction.c
CMN_CSRCS += up_sigdeliver.c up_stackframe.c up_systemreset.c up_unblocktask.c up_usestack.c
CMN_CSRCS += up_doirq.c up_hardfault.c up_svcall.c up_vfork.c
ifneq ($(CONFIG_ARCH_IDLE_CUSTOM),y)
CMN_CSRCS += up_idle.c
endif
# Configuration-dependent common files
ifeq ($(CONFIG_ARMV7M_CMNVECTOR),y)

45
arch/arm/src/stm32f7/stm32f74xx75xx_rcc.c
View File

@ -68,6 +68,12 @@
# error BOARD_FLASH_WAITSTATES is out of range
#endif
/* Voltage output scale (default to Scale 1 mode) */
#ifndef STM32_PWR_VOS_SCALE
# define STM32_PWR_VOS_SCALE PWR_CR1_VOS_SCALE_1
#endif
/****************************************************************************
* Private Data
****************************************************************************/
@ -732,7 +738,7 @@ static void stm32_stdclockconfig(void)
regval = getreg32(STM32_PWR_CR1);
regval &= ~PWR_CR1_VOS_MASK;
regval |= PWR_CR1_VOS_SCALE_1;
regval |= STM32_PWR_VOS_SCALE;
putreg32(regval, STM32_PWR_CR1);
/* Set the HCLK source/divider */
@ -788,20 +794,35 @@ static void stm32_stdclockconfig(void)
{
}
/* Enable the Over-drive to extend the clock frequency to 216 Mhz */
/* Over-drive is needed if
* - Voltage output scale 1 mode is selected and SYSCLK frequency is
* over 180 Mhz.
* - Voltage output scale 2 mode is selected and SYSCLK frequence is
* over 168 Mhz.
*/
regval = getreg32(STM32_PWR_CR1);
regval |= PWR_CR1_ODEN;
putreg32(regval, STM32_PWR_CR1);
while ((getreg32(STM32_PWR_CSR1) & PWR_CSR1_ODRDY) == 0)
if ((STM32_PWR_VOS_SCALE == PWR_CR1_VOS_SCALE_1 &&
STM32_SYSCLK_FREQUENCY > 180000000) ||
(STM32_PWR_VOS_SCALE == PWR_CR1_VOS_SCALE_2 &&
STM32_SYSCLK_FREQUENCY > 168000000))
{
}
/* Enable the Over-drive to extend the clock frequency up to
* 216 Mhz.
*/
regval = getreg32(STM32_PWR_CR1);
regval |= PWR_CR1_ODSWEN;
putreg32(regval, STM32_PWR_CR1);
while ((getreg32(STM32_PWR_CSR1) & PWR_CSR1_ODSWRDY) == 0)
{
regval = getreg32(STM32_PWR_CR1);
regval |= PWR_CR1_ODEN;
putreg32(regval, STM32_PWR_CR1);
while ((getreg32(STM32_PWR_CSR1) & PWR_CSR1_ODRDY) == 0)
{
}
regval = getreg32(STM32_PWR_CR1);
regval |= PWR_CR1_ODSWEN;
putreg32(regval, STM32_PWR_CR1);
while ((getreg32(STM32_PWR_CSR1) & PWR_CSR1_ODSWRDY) == 0)
{
}
}
/* Configure FLASH wait states */

45
arch/arm/src/stm32f7/stm32f76xx77xx_rcc.c
View File

@ -77,6 +77,12 @@
# error BOARD_FLASH_WAITSTATES is out of range
#endif
/* Voltage output scale (default to Scale 1 mode) */
#ifndef STM32_PWR_VOS_SCALE
# define STM32_PWR_VOS_SCALE PWR_CR1_VOS_SCALE_1
#endif
/****************************************************************************
* Private Functions
****************************************************************************/
@ -738,7 +744,7 @@ static void stm32_stdclockconfig(void)
regval = getreg32(STM32_PWR_CR1);
regval &= ~PWR_CR1_VOS_MASK;
regval |= PWR_CR1_VOS_SCALE_1;
regval |= STM32_PWR_VOS_SCALE;
putreg32(regval, STM32_PWR_CR1);
/* Set the HCLK source/divider */
@ -794,20 +800,35 @@ static void stm32_stdclockconfig(void)
{
}
/* Enable the Over-drive to extend the clock frequency to 216 Mhz */
/* Over-drive is needed if
* - Voltage output scale 1 mode is selected and SYSCLK frequency is
* over 180 Mhz.
* - Voltage output scale 2 mode is selected and SYSCLK frequence is
* over 168 Mhz.
*/
regval = getreg32(STM32_PWR_CR1);
regval |= PWR_CR1_ODEN;
putreg32(regval, STM32_PWR_CR1);
while ((getreg32(STM32_PWR_CSR1) & PWR_CSR1_ODRDY) == 0)
if ((STM32_PWR_VOS_SCALE == PWR_CR1_VOS_SCALE_1 &&
STM32_SYSCLK_FREQUENCY > 180000000) ||
(STM32_PWR_VOS_SCALE == PWR_CR1_VOS_SCALE_2 &&
STM32_SYSCLK_FREQUENCY > 168000000))
{
}
/* Enable the Over-drive to extend the clock frequency up to
* 216 Mhz.
*/
regval = getreg32(STM32_PWR_CR1);
regval |= PWR_CR1_ODSWEN;
putreg32(regval, STM32_PWR_CR1);
while ((getreg32(STM32_PWR_CSR1) & PWR_CSR1_ODSWRDY) == 0)
{
regval = getreg32(STM32_PWR_CR1);
regval |= PWR_CR1_ODEN;
putreg32(regval, STM32_PWR_CR1);
while ((getreg32(STM32_PWR_CSR1) & PWR_CSR1_ODRDY) == 0)
{
}
regval = getreg32(STM32_PWR_CR1);
regval |= PWR_CR1_ODSWEN;
putreg32(regval, STM32_PWR_CR1);
while ((getreg32(STM32_PWR_CSR1) & PWR_CSR1_ODSWRDY) == 0)
{
}
}
/* Configure FLASH wait states */