From 88fde06d5b9d0d9d06bb498d99f528af5637e1b6 Mon Sep 17 00:00:00 2001 From: patacongo Date: Thu, 3 Nov 2011 01:16:48 +0000 Subject: [PATCH] A few more AVR32 fixes git-svn-id: svn://svn.code.sf.net/p/nuttx/code/trunk@4078 42af7a65-404d-4744-a932-0658087f49c3 --- arch/mips/include/mips32/cp0.h | 2 +- arch/mips/include/mips32/registers.h | 10 +++++----- 2 files changed, 6 insertions(+), 6 deletions(-) diff --git a/arch/mips/include/mips32/cp0.h b/arch/mips/include/mips32/cp0.h index b2886be32d..91f6d2d0e0 100755 --- a/arch/mips/include/mips32/cp0.h +++ b/arch/mips/include/mips32/cp0.h @@ -278,7 +278,7 @@ # define CP0_CAUSE_IP5 (0x13 << CP0_CAUSE_IP_SHIFT) /* Hardware interrupt 3 */ # define CP0_CAUSE_IP6 (0x14 << CP0_CAUSE_IP_SHIFT) /* Hardware interrupt 4 */ # define CP0_CAUSE_IP7 (0x15 << CP0_CAUSE_IP_SHIFT) /* Hardware interrupt 5, timer or performance counter interrupt */ -#define CP0_CAUSE_WP (1 << 22) /* Watch exception was deferred +#define CP0_CAUSE_WP (1 << 22) /* Watch exception was deferred */ #define CP0_CAUSE_IV (1 << 23) /* Bit 23: Interrupt exception uses special interrupt vector */ #define CP0_CAUSE_CE_SHIFT (28) /* Bits 28-29: Coprocessor unit number fo Coprocessor Unusable exception */ #define CP0_CAUSE_CE_MASK (3 << CP0_CAUSE_CE_SHIFT) diff --git a/arch/mips/include/mips32/registers.h b/arch/mips/include/mips32/registers.h index 997bc51d6a..e541a8e531 100755 --- a/arch/mips/include/mips32/registers.h +++ b/arch/mips/include/mips32/registers.h @@ -93,11 +93,6 @@ #define s6 $22 #define s7 $23 -/* Register 30 may be either an additional static register or a frame pointer */ - -#define s8 $30 -#define fp $30 - /* Reserved for use by interrupt/trap handling logic */ #define k0 $26 @@ -111,6 +106,11 @@ #define sp $29 +/* Register 30 may be either an additional static register or a frame pointer */ + +#define s8 $30 +#define fp $30 + /* Return address register: Contains the function return address */ #define ra $31