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tiva/cc13x2_cc26x2: Fix nxstyle errors

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arch/arm/src/tiva/hardware/cc13x2_cc26x2/cc13x2_cc26x2_aon_pmctl.h:

    * Fix nxstyle errors.
This commit is contained in:
Nathan Hartman 2020-10-27 10:50:44 -04:00 committed by Xiang Xiao
parent 8339bac6e4
commit 892c6b254a
1 changed files with 53 additions and 52 deletions
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105
arch/arm/src/tiva/hardware/cc13x2_cc26x2/cc13x2_cc26x2_aon_pmctl.h
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@ -1,10 +1,11 @@
/********************************************************************************************************************
/****************************************************************************
* arch/arm/src/tiva/hardware/cc13x2_cc26x2/cc13x2_cc26x2_aon_pmctl.h
*
* Copyright (C) 2018 Gregory Nutt. All rights reserved.
* Authors: Gregory Nutt <gnutt@nuttx.org>
*
* Technical content derives from a TI header file that has a compatible BSD license:
* Technical content derives from a TI header file that has a compatible BSD
* license:
*
* Copyright (c) 2015-2017, Texas Instruments Incorporated
* All rights reserved.
@ -36,23 +37,23 @@
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
********************************************************************************************************************/
****************************************************************************/
#ifndef __ARCH_ARM_SRC_TIVA_HARDWARE_CC13X2_CC26X2_CC13X2_CC26X2_AON_PMCTL_H
#define __ARCH_ARM_SRC_TIVA_HARDWARE_CC13X2_CC26X2_CC13X2_CC26X2_AON_PMCTL_H
/********************************************************************************************************************
/****************************************************************************
* Included Files
********************************************************************************************************************/
****************************************************************************/
#include <nuttx/config.h>
#include "hardware/tiva_memorymap.h"
/********************************************************************************************************************
/****************************************************************************
* Pre-processor Definitions
********************************************************************************************************************/
****************************************************************************/
/* AON PMCTL Register Offsets ***************************************************************************************/
/* AON PMCTL Register Offsets ***********************************************/
#define TIVA_AON_PMCTL_AUXSCECLK_OFFSET 0x0004 /* AUX SCE Clock Management */
#define TIVA_AON_PMCTL_RAMCFG_OFFSET 0x0008 /* RAM Configuration */
@ -67,7 +68,7 @@
#define TIVA_AON_PMCTL_JTAGCFG_OFFSET 0x0034 /* JTAG Configuration */
#define TIVA_AON_PMCTL_JTAGUSERCODE_OFFSET 0x003c /* JTAG USERCODE */
/* AON PMCTL Register Addresses *************************************************************************************/
/* AON PMCTL Register Addresses *********************************************/
#define TIVA_AON_PMCTL_AUXSCECLK (TIVA_AON_PMCTL_BASE + TIVA_AON_PMCTL_AUXSCECLK_OFFSET)
#define TIVA_AON_PMCTL_RAMCFG (TIVA_AON_PMCTL_BASE + TIVA_AON_PMCTL_RAMCFG_OFFSET)
@ -82,21 +83,21 @@
#define TIVA_AON_PMCTL_JTAGCFG (TIVA_AON_PMCTL_BASE + TIVA_AON_PMCTL_JTAGCFG_OFFSET)
#define TIVA_AON_PMCTL_JTAGUSERCODE (TIVA_AON_PMCTL_BASE + TIVA_AON_PMCTL_JTAGUSERCODE_OFFSET)
/* AON PMCTL Bitfield Definitions ***********************************************************************************/
/* AON PMCTL Bitfield Definitions *******************************************/
/* TIVA_AON_PMCTL_AUXSCECLK */
#define AON_PMCTL_AUXSCECLK_SRC (1 << 0) /* Bit 0: Clock source for AUX dmaon in active mode */
#define AON_PMCTL_AUXSCECLK_SRC (1 << 0) /* Bit 0: Clock source for AUX dmaon in active mode */
# define AON_PMCTL_AUXSCECLK_SCLK_HFDIV2 (0) /* HF Clock divided by 2 (SCLK_HFDIV2) */
# define AON_PMCTL_AUXSCECLK_SCLK_MF AON_PMCTL_AUXSCECLK_SRC /* MF Clock (SCLK_MF) */
#define AON_PMCTL_AUXSCECLK_PD_SRC (1 << 8) /* Bit 8: Clock source for AUX dmaon in powerdown mode */
#define AON_PMCTL_AUXSCECLK_PD_SRC (1 << 8) /* Bit 8: Clock source for AUX dmaon in powerdown mode */
# define AON_PMCTL_AUXSCECLK_PD_NO_CLOCK (0) /* No clock */
# define AON_PMCTL_AUXSCECLK_PD_SCLK_LF AON_PMCTL_AUXSCECLK_PD_SRC /* LF clock (SCLK_LF) */
/* TIVA_AON_PMCTL_RAMCFG */
#define AON_PMCTL_RAMCFG_BUS_SRAM_RET_EN_SHIFT (0) /* Bits 0-3: Select banks for retention during MCU
* bus domain power off */
#define AON_PMCTL_RAMCFG_BUS_SRAM_RET_EN_SHIFT (0) /* Bits 0-3: Select banks for retention during MCU
* bus domain power off */
#define AON_PMCTL_RAMCFG_BUS_SRAM_RET_EN_MASK (15 << AON_PMCTL_RAMCFG_BUS_SRAM_RET_EN_SHIFT)
# define AON_PMCTL_RAMCFG_BUS_SRAM_RET_EN_RET_NONE (0 << AON_PMCTL_RAMCFG_BUS_SRAM_RET_EN_SHIFT) /* Retention is disabled */
# define AON_PMCTL_RAMCFG_BUS_SRAM_RET_EN_RET_LEVEL1 (1 << AON_PMCTL_RAMCFG_BUS_SRAM_RET_EN_SHIFT) /* Retention on for all banks SRAM:BANK0
@ -107,20 +108,20 @@
* -BANK3 */
# define AON_PMCTL_RAMCFG_BUS_SRAM_RET_EN_RET_FULL (15 << AON_PMCTL_RAMCFG_BUS_SRAM_RET_EN_SHIFT) /* Retention on for all banks SRAM:BANK0
* -BANK4 */
#define AON_PMCTL_RAMCFG_AUX_SRAM_RET_EN (1 << 16) /* Bit 16 */
#define AON_PMCTL_RAMCFG_AUX_SRAM_PWR_OFF (1 << 17) /* Bit 17 */
#define AON_PMCTL_RAMCFG_AUX_SRAM_RET_EN (1 << 16) /* Bit 16 */
#define AON_PMCTL_RAMCFG_AUX_SRAM_PWR_OFF (1 << 17) /* Bit 17 */
/* TIVA_AON_PMCTL_PWRCTL */
#define AON_PMCTL_PWRCTL_DCDC_EN (1 << 0) /* Bit 0: Select to use DCDC or GLC0 during recharge of VDDR */
# define AON_PMCTL_PWRCTL_DCDC_EN_GLD0 (0) /* Use GLDO for recharge of VDDR */
# define AON_PMCTL_PWRCTL_DCDC_EN_DCDC AON_PMCTL_PWRCTL_DCDC_EN /* Use DCDC for recharge of VDDR */
#define AON_PMCTL_PWRCTL_EXT_REG_MODE (1 << 1) /* Bit 1: Status of source for VDDR supply */
#define AON_PMCTL_PWRCTL_DCDC_EN (1 << 0) /* Bit 0: Select to use DCDC or GLC0 during recharge of VDDR */
# define AON_PMCTL_PWRCTL_DCDC_EN_GLD0 (0) /* Use GLDO for recharge of VDDR */
# define AON_PMCTL_PWRCTL_DCDC_EN_DCDC AON_PMCTL_PWRCTL_DCDC_EN /* Use DCDC for recharge of VDDR */
#define AON_PMCTL_PWRCTL_EXT_REG_MODE (1 << 1) /* Bit 1: Status of source for VDDR supply */
# define AON_PMCTL_PWRCTL_EXT_REG_DCDCGLD0 (0) /* DCDC or GLDO are generating VDDR */
# define AON_PMCTL_PWRCTL_EXT_REG_EXTERNAL AON_PMCTL_PWRCTL_EXT_REG_MODE /* External regulator supplies VDDR */
#define AON_PMCTL_PWRCTL_DCDC_ACTIVE (1 << 2) /* Bit 2: Select DCDC regulator for VDDR in active mode */
# define AON_PMCTL_PWRCTL_DCDC_ACTIVE_GLD0 (0) /* Use GLDO for regulation of VDDR in active mode */
# define AON_PMCTL_PWRCTL_DCDC_ACTIVE_DCDC AON_PMCTL_PWRCTL_DCDC_ACTIVE /* Use DCDC for regulation of VDDR in active mode */
#define AON_PMCTL_PWRCTL_DCDC_ACTIVE (1 << 2) /* Bit 2: Select DCDC regulator for VDDR in active mode */
# define AON_PMCTL_PWRCTL_DCDC_ACTIVE_GLD0 (0) /* Use GLDO for regulation of VDDR in active mode */
# define AON_PMCTL_PWRCTL_DCDC_ACTIVE_DCDC AON_PMCTL_PWRCTL_DCDC_ACTIVE /* Use DCDC for regulation of VDDR in active mode */
/* TIVA_AON_PMCTL_PWRSTAT */
@ -134,26 +135,26 @@
/* TIVA_AON_PMCTL_RECHARGECFG */
#define AON_PMCTL_RECHARGECFG_PER_E_SHIFT (0) /* Bits 0-2 */
#define AON_PMCTL_RECHARGECFG_PER_E_SHIFT (0) /* Bits 0-2 */
#define AON_PMCTL_RECHARGECFG_PER_E_MASK (7 << AON_PMCTL_RECHARGECFG_PER_E_SHIFT)
# define AON_PMCTL_RECHARGECFG_PER_E(n) ((uint32_t)(n) << AON_PMCTL_RECHARGECFG_PER_E_SHIFT)
#define AON_PMCTL_RECHARGECFG_PER_M_SHIFT (3) /* Bits 3-7 */
#define AON_PMCTL_RECHARGECFG_PER_M_SHIFT (3) /* Bits 3-7 */
#define AON_PMCTL_RECHARGECFG_PER_M_MASK (31 << AON_PMCTL_RECHARGECFG_PER_M_SHIFT)
# define AON_PMCTL_RECHARGECFG_PER_M(n) ((uint32_t)(n) << AON_PMCTL_RECHARGECFG_PER_M_SHIFT)
#define AON_PMCTL_RECHARGECFG_MAX_PER_E_SHIFT (8) /* Bits 8-10 */
#define AON_PMCTL_RECHARGECFG_MAX_PER_E_SHIFT (8) /* Bits 8-10 */
#define AON_PMCTL_RECHARGECFG_MAX_PER_E_MASK (7 << AON_PMCTL_RECHARGECFG_MAX_PER_E_SHIFT)
# define AON_PMCTL_RECHARGECFG_MAX_PER_E(n) ((uint32_t)(n) << AON_PMCTL_RECHARGECFG_MAX_PER_E_SHIFT)
#define AON_PMCTL_RECHARGECFG_MAX_PER_M_SHIFT (11) /* Bits 11-15 */
#define AON_PMCTL_RECHARGECFG_MAX_PER_M_SHIFT (11) /* Bits 11-15 */
#define AON_PMCTL_RECHARGECFG_MAX_PER_M_MASK (31 << AON_PMCTL_RECHARGECFG_MAX_PER_M_SHIFT)
# define AON_PMCTL_RECHARGECFG_MAX_PER_M(n) ((uint32_t)(n) << AON_PMCTL_RECHARGECFG_MAX_PER_M_SHIFT)
#define AON_PMCTL_RECHARGECFG_C1_SHIFT (16) /* Bits 16-19 */
#define AON_PMCTL_RECHARGECFG_C1_SHIFT (16) /* Bits 16-19 */
#define AON_PMCTL_RECHARGECFG_C1_MASK (15 << AON_PMCTL_RECHARGECFG_C1_SHIFT)
# define AON_PMCTL_RECHARGECFG_C1(n) ((uint32_t)(n) << AON_PMCTL_RECHARGECFG_C1_SHIFT)
#define AON_PMCTL_RECHARGECFG_C2_SHIFT (20) /* Bits 20-23 */
#define AON_PMCTL_RECHARGECFG_C2_SHIFT (20) /* Bits 20-23 */
#define AON_PMCTL_RECHARGECFG_C2_MASK (15 << AON_PMCTL_RECHARGECFG_C2_SHIFT)
# define AON_PMCTL_RECHARGECFG_C2(n) ((uint32_t)(n) << AON_PMCTL_RECHARGECFG_C2_SHIFT)
#define AON_PMCTL_RECHARGECFG_MODE_SHIFT (30) /* Bits 30-3: Selects recharge algorithm for VDDR when the system is
* running on the uLDO */
#define AON_PMCTL_RECHARGECFG_MODE_SHIFT (30) /* Bits 30-3: Selects recharge algorithm for VDDR when the system is
* running on the uLDO */
#define AON_PMCTL_RECHARGECFG_MODE_MASK (3 << AON_PMCTL_RECHARGECFG_MODE_SHIFT)
# define AON_PMCTL_RECHARGECFG_MODE_OFF (0 << AON_PMCTL_RECHARGECFG_MODE_SHIFT) /* Recharge disabled */
# define AON_PMCTL_RECHARGECFG_MODE_STATIC (1 << AON_PMCTL_RECHARGECFG_MODE_SHIFT) /* Static timer */
@ -162,10 +163,10 @@
/* TIVA_AON_PMCTL_RECHARGESTAT */
#define AON_PMCTL_RECHARGESTAT_MAX_USED_PER_SHIFT (0) /* Bits 0-15: Mzx 32KHz periods between recharge cycles and VDDR
* is still above BDDR_OK threshold. */
#define AON_PMCTL_RECHARGESTAT_MAX_USED_PER_SHIFT (0) /* Bits 0-15: Mzx 32KHz periods between recharge cycles and VDDR
* is still above BDDR_OK threshold. */
#define AON_PMCTL_RECHARGESTAT_MAX_USED_PER_MASK (0xffff << AON_PMCTL_RECHARGESTAT_MAX_USED_PER_SHIFT)
#define AON_PMCTL_RECHARGESTAT_VDDR_SMPLS_SHIFT (16) /* Bits 16-19: The last 4 VDDR samples */
#define AON_PMCTL_RECHARGESTAT_VDDR_SMPLS_SHIFT (16) /* Bits 16-19: The last 4 VDDR samples */
#define AON_PMCTL_RECHARGESTAT_VDDR_SMPLS_MASK (15 << AON_PMCTL_RECHARGESTAT_VDDR_SMPLS_SHIFT)
# define AON_PMCTL_RECHARGESTAT_VDDR_SMPL0 (1 << AON_PMCTL_RECHARGESTAT_VDDR_SMPLS_SHIFT)
# define AON_PMCTL_RECHARGESTAT_VDDR_SMPL1 (2 << AON_PMCTL_RECHARGESTAT_VDDR_SMPLS_SHIFT)
@ -174,16 +175,16 @@
/* TIVA_AON_PMCTL_OSCCFG */
#define AON_PMCTL_OSCCFG_PER_E_SHIFT (0) /* Bits 0-2 */
#define AON_PMCTL_OSCCFG_PER_E_SHIFT (0) /* Bits 0-2 */
#define AON_PMCTL_OSCCFG_PER_E_MASK (7 << AON_PMCTL_OSCCFG_PER_E_SHIFT)
# define AON_PMCTL_OSCCFG_PER_E(n) ((uint32_t)(n) << AON_PMCTL_OSCCFG_PER_E_SHIFT)
#define AON_PMCTL_OSCCFG_PER_M_SHIFT (3) /* Bits 3-7 */
#define AON_PMCTL_OSCCFG_PER_M_SHIFT (3) /* Bits 3-7 */
#define AON_PMCTL_OSCCFG_PER_M_MASK (31 << AON_PMCTL_OSCCFG_PER_M_SHIFT)
# define AON_PMCTL_OSCCFG_PER_M(n) ((uint32_t)(n) << AON_PMCTL_OSCCFG_PER_M_SHIFT)
/* TIVA_AON_PMCTL_RESETCTL */
#define AON_PMCTL_RESETCTL_RESET_SRC_SHIFT (1) /* Bits 1-3: Shows the root cause of the last system reset */
#define AON_PMCTL_RESETCTL_RESET_SRC_SHIFT (1) /* Bits 1-3: Shows the root cause of the last system reset */
#define AON_PMCTL_RESETCTL_RESET_SRC_MASK (7 << AON_PMCTL_RESETCTL_RESET_SRC_SHIFT)
# define AON_PMCTL_RESETCTL_RESET_SRC_PWR_ON (0 << AON_PMCTL_RESETCTL_RESET_SRC_SHIFT) /* Power on reset */
# define AON_PMCTL_RESETCTL_RESET_SRC_PIN_RESET (1 << AON_PMCTL_RESETCTL_RESET_SRC_SHIFT) /* Reset pin */
@ -194,21 +195,21 @@
* power management timeout detection */
# define AON_PMCTL_RESETCTL_RESET_SRC_WARMRESET (7 << AON_PMCTL_RESETCTL_RESET_SRC_SHIFT) /* Software reset via PRCM warm reset */
#define AON_PMCTL_RESETCTL_MCU_WARM_RESET (1 << 4) /* Bit 4 */
#define AON_PMCTL_RESETCTL_CLK_LOSS_EN (1 << 5) /* Bit 5: Controls reset generation in case SCLK_LF, SCLK_MF or
* SCLK_HF is lost when clock loss detection is enabled */
#define AON_PMCTL_RESETCTL_VDD_LOSS_EN (1 << 6) /* Bit 6: Controls reset generation in case VDD is lost */
#define AON_PMCTL_RESETCTL_VDDR_LOSS_EN (1 << 7) /* Bit 7: Controls reset generation in case VDDR is lost */
#define AON_PMCTL_RESETCTL_VDDS_LOSS_EN (1 << 8) /* Bit 8: Controls reset generation in case VDDS is lost */
#define AON_PMCTL_RESETCTL_BOOT_DET_0 (1 << 12) /* Bit 12 */
#define AON_PMCTL_RESETCTL_BOOT_DET_1 (1 << 13) /* Bit 13 */
#define AON_PMCTL_RESETCTL_GPIO_WU_FROM_SD (1 << 14) /* Bit 14: A wakeup from SHUTDOWN on an IO event has occurred */
#define AON_PMCTL_RESETCTL_WU_FROM_SD (1 << 15) /* Bit 15: Wakeup from Shutdown */
#define AON_PMCTL_RESETCTL_BOOT_DET_0_SET (1 << 16) /* Bit 16 */
#define AON_PMCTL_RESETCTL_BOOT_DET_1_SET (1 << 17) /* Bit 17 */
#define AON_PMCTL_RESETCTL_BOOT_DET_0_CLR (1 << 24) /* Bit 24 */
#define AON_PMCTL_RESETCTL_BOOT_DET_1_CLR (1 << 25) /* Bit 25 */
#define AON_PMCTL_RESETCTL_SYSRESET (1 << 31) /* Bit 31: Cold reset */
#define AON_PMCTL_RESETCTL_MCU_WARM_RESET (1 << 4) /* Bit 4 */
#define AON_PMCTL_RESETCTL_CLK_LOSS_EN (1 << 5) /* Bit 5: Controls reset generation in case SCLK_LF, SCLK_MF or
* SCLK_HF is lost when clock loss detection is enabled */
#define AON_PMCTL_RESETCTL_VDD_LOSS_EN (1 << 6) /* Bit 6: Controls reset generation in case VDD is lost */
#define AON_PMCTL_RESETCTL_VDDR_LOSS_EN (1 << 7) /* Bit 7: Controls reset generation in case VDDR is lost */
#define AON_PMCTL_RESETCTL_VDDS_LOSS_EN (1 << 8) /* Bit 8: Controls reset generation in case VDDS is lost */
#define AON_PMCTL_RESETCTL_BOOT_DET_0 (1 << 12) /* Bit 12 */
#define AON_PMCTL_RESETCTL_BOOT_DET_1 (1 << 13) /* Bit 13 */
#define AON_PMCTL_RESETCTL_GPIO_WU_FROM_SD (1 << 14) /* Bit 14: A wakeup from SHUTDOWN on an IO event has occurred */
#define AON_PMCTL_RESETCTL_WU_FROM_SD (1 << 15) /* Bit 15: Wakeup from Shutdown */
#define AON_PMCTL_RESETCTL_BOOT_DET_0_SET (1 << 16) /* Bit 16 */
#define AON_PMCTL_RESETCTL_BOOT_DET_1_SET (1 << 17) /* Bit 17 */
#define AON_PMCTL_RESETCTL_BOOT_DET_0_CLR (1 << 24) /* Bit 24 */
#define AON_PMCTL_RESETCTL_BOOT_DET_1_CLR (1 << 25) /* Bit 25 */
#define AON_PMCTL_RESETCTL_SYSRESET (1 << 31) /* Bit 31: Cold reset */
/* TIVA_AON_PMCTL_SLEEPCTL */