16550 UART Driver: Add a configuration option to indicate the the THR empty bit is inverted. This is the the case for the moxART SoC. Based comments from Anton D. Kachalov

This commit is contained in:
Gregory Nutt 2015-07-29 16:31:21 -06:00
parent f230c87fba
commit 8935ff34d5
5 changed files with 36 additions and 9 deletions

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@ -10770,4 +10770,7 @@
* configs/moxa: Moxa NP51x0 series of 2-port advanced RS-232/422/485 * configs/moxa: Moxa NP51x0 series of 2-port advanced RS-232/422/485
serial device servers. From Anton D. Kachalov (2015-07-29). serial device servers. From Anton D. Kachalov (2015-07-29).
* drivers/net/ and include/nuttx/net: Add support for a Faraday * drivers/net/ and include/nuttx/net: Add support for a Faraday
FTMAC100 Ethernet MAC Driver. From Anton D. Kachalov (2015-07-29). * FTMAC100 Ethernet MAC Driver. From Anton D. Kachalov (2015-07-29).
* 16550 UART Driver: Add a configuration option to indicate the the
THR empty bit is inverted. This is the the case for the moxART SoC.
Based comments from Anton D. Kachalov (2015-07-29).

@ -1 +1 @@
Subproject commit e098a90e99ca1268e121cebd7942d7c17a48e114 Subproject commit 73e7501f1278e5e0e0919baf0c217176b8cc02a6

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@ -19,11 +19,13 @@ config 16550_UART
default n default n
if 16550_UART if 16550_UART
config 16550_UART0 config 16550_UART0
bool "16550 UART0" bool "16550 UART0"
default n default n
if 16550_UART0 if 16550_UART0
config 16550_UART0_BASE config 16550_UART0_BASE
hex "16550 UART0 base address" hex "16550 UART0 base address"
@ -82,13 +84,14 @@ config 16550_UART0_OFLOWCONTROL
---help--- ---help---
Enable 16550 UART0 CTS flow control Enable 16550 UART0 CTS flow control
endif endif # 16550_UART0
config 16550_UART1 config 16550_UART1
bool "16550 UART1" bool "16550 UART1"
default n default n
if 16550_UART1 if 16550_UART1
config 16550_UART1_BASE config 16550_UART1_BASE
hex "16550 UART1 base address" hex "16550 UART1 base address"
@ -147,13 +150,14 @@ config 16550_UART1_OFLOWCONTROL
---help--- ---help---
Enable 16550 UART1 CTS flow control Enable 16550 UART1 CTS flow control
endif endif # 16550_UART1
config 16550_UART2 config 16550_UART2
bool "16550 UART2" bool "16550 UART2"
default n default n
if 16550_UART2 if 16550_UART2
config 16550_UART2_BASE config 16550_UART2_BASE
hex "16550 UART2 base address" hex "16550 UART2 base address"
@ -212,13 +216,14 @@ config 16550_UART2_OFLOWCONTROL
---help--- ---help---
Enable 16550 UART2 CTS flow control Enable 16550 UART2 CTS flow control
endif endif # 16550_UART2
config 16550_UART3 config 16550_UART3
bool "16550 UART3" bool "16550 UART3"
default n default n
if 16550_UART3 if 16550_UART3
config 16550_UART3_BASE config 16550_UART3_BASE
hex "16550 UART3 base address" hex "16550 UART3 base address"
@ -277,7 +282,7 @@ config 16550_UART3_OFLOWCONTROL
---help--- ---help---
Enable 16550 UART3 CTS flow control Enable 16550 UART3 CTS flow control
endif endif # 16550_UART3
choice choice
prompt "16550 Serial Console" prompt "16550 Serial Console"
@ -303,7 +308,7 @@ config 16550_UART3_SERIAL_CONSOLE
config 16550_NO_SERIAL_CONSOLE config 16550_NO_SERIAL_CONSOLE
bool "No 16550 serial console" bool "No 16550 serial console"
endchoice endchoice # 16550 Serial Console
config 16550_SUPRESS_CONFIG config 16550_SUPRESS_CONFIG
bool "Suppress 16550 configuration" bool "Suppress 16550 configuration"
@ -332,7 +337,18 @@ config 16550_ADDRWIDTH
---help--- ---help---
The bit width of registers. Options are 8, 16, or 32. Default: 8 The bit width of registers. Options are 8, 16, or 32. Default: 8
endif config 16550_THRNE
bool "Use THRNE"
default n if !ARCH_CHIP_MOXART
default y if ARCH_CHIP_MOXART
---help---
The 16550 UART has a bit in the line status register, THRE, that
indicates that the Transmit Holding Register (THR) is Empty (N).
This bit is inverted in at least one variant (the moxART SoC).
In that case, this setting must be included to use this bit as
THR *Not* Empty (THRNE).
endif # 16550_UART
# #
# MCU serial peripheral driver? # MCU serial peripheral driver?

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@ -1057,7 +1057,11 @@ static bool u16550_txempty(struct uart_dev_s *dev)
static void u16550_putc(struct u16550_s *priv, int ch) static void u16550_putc(struct u16550_s *priv, int ch)
{ {
#ifdef CONFIG_16550_THRNE
while ((u16550_serialin(priv, UART_LSR_OFFSET) & UART_LSR_THRNE) == 0);
#else
while ((u16550_serialin(priv, UART_LSR_OFFSET) & UART_LSR_THRE) != 0); while ((u16550_serialin(priv, UART_LSR_OFFSET) & UART_LSR_THRE) != 0);
#endif
u16550_serialout(priv, UART_THR_OFFSET, (uart_datawidth_t)ch); u16550_serialout(priv, UART_THR_OFFSET, (uart_datawidth_t)ch);
} }

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@ -299,7 +299,11 @@
#define UART_LSR_PE (1 << 2) /* Bit 2: Parity Error */ #define UART_LSR_PE (1 << 2) /* Bit 2: Parity Error */
#define UART_LSR_FE (1 << 3) /* Bit 3: Framing Error */ #define UART_LSR_FE (1 << 3) /* Bit 3: Framing Error */
#define UART_LSR_BI (1 << 4) /* Bit 4: Break Interrupt */ #define UART_LSR_BI (1 << 4) /* Bit 4: Break Interrupt */
#define UART_LSR_THRE (1 << 5) /* Bit 5: Transmitter Holding Register Empty */ #ifdef CONFIG_16550_THRNE
# define UART_LSR_THRNE (1 << 5) /* Bit 5: Transmitter Holding Register Not Empty */
#else
# define UART_LSR_THRE (1 << 5) /* Bit 5: Transmitter Holding Register Empty */
#endif
#define UART_LSR_TEMT (1 << 6) /* Bit 6: Transmitter Empty */ #define UART_LSR_TEMT (1 << 6) /* Bit 6: Transmitter Empty */
#define UART_LSR_RXFE (1 << 7) /* Bit 7: Error in RX FIFO (RXFE) */ #define UART_LSR_RXFE (1 << 7) /* Bit 7: Error in RX FIFO (RXFE) */