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SAMA5: Update slow clock logic. Things work a little differently on the SAMA5D3

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This commit is contained in:
Gregory Nutt 2014-07-19 13:25:59 -06:00
parent 813eade679
commit 8986bd3976
1 changed files with 6 additions and 0 deletions
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6
arch/arm/src/sama5/chip/sam_sckc.h
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@ -58,6 +58,12 @@
/* Slow Clock Controller Configuration Register */ /* Slow Clock Controller Configuration Register */
#ifdef ATSAMA5D3
# define SCKC_CR_RCEN (1 << 0) /* Bit 0: Internal 32 kHz RC Oscillator */
# define SCKC_CR_OSC32EN (1 << 1) /* Bit 1: 32768 Hz Oscillator */
# define SCKC_CR_OSC32BYP (1 << 2) /* Bit 2: 2768Hz Oscillator Bypass */
#endif
#define SCKC_CR_OSCSEL (1 << 3) /* Bit 3: Slow Clock Selector */ #define SCKC_CR_OSCSEL (1 << 3) /* Bit 3: Slow Clock Selector */
#endif /* __ARCH_ARM_SRC_SAMA5_CHIP_SAM_SCKC_H */ #endif /* __ARCH_ARM_SRC_SAMA5_CHIP_SAM_SCKC_H */