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arch/risc-v/riscv_misaligned: Correct sw source register

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If source register of sw instruction is x0, we must point it to a constant zero
since in NuttX's context,
value of index 0 is EPC.

Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
This commit is contained in:
Huang Qi 2022-04-13 16:22:54 +08:00 committed by Xiang Xiao
parent 370152f3ba
commit 898d789a5f
1 changed files with 12 additions and 1 deletions
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13
arch/risc-v/src/common/riscv_misaligned.c
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@ -363,6 +363,7 @@ static bool decode_insn_compressed(uintptr_t *regs, riscv_insn_ctx_t *ctx)
static bool decode_insn(uintptr_t *regs, riscv_insn_ctx_t *ctx)
{
static const uintptr_t x0;
uint32_t in;
int32_t imm;
riscv_insn_t insn;
@ -418,7 +419,17 @@ static bool decode_insn(uintptr_t *regs, riscv_insn_ctx_t *ctx)
imm = sext(insn.s.imm2 | insn.s.imm1 << 5, 12);
ctx->dest = (uint8_t *)regs[insn.s.rs1] + imm;
ctx->src = (uint8_t *)&regs[insn.s.rs2];
/* If source register is x0, target it to constant register */
if (insn.s.rs2 == 0)
{
ctx->src = (uint8_t *)&x0;
}
else
{
ctx->src = (uint8_t *)&regs[insn.s.rs2];
}
/* Get data wide bit */