From 898d789a5fd604550178c36cc7061cab3e0da9c6 Mon Sep 17 00:00:00 2001 From: Huang Qi Date: Wed, 13 Apr 2022 16:22:54 +0800 Subject: [PATCH] arch/risc-v/riscv_misaligned: Correct sw source register If source register of sw instruction is x0, we must point it to a constant zero since in NuttX's context, value of index 0 is EPC. Signed-off-by: Huang Qi --- arch/risc-v/src/common/riscv_misaligned.c | 13 ++++++++++++- 1 file changed, 12 insertions(+), 1 deletion(-) diff --git a/arch/risc-v/src/common/riscv_misaligned.c b/arch/risc-v/src/common/riscv_misaligned.c index 54148f0f4b..4358dfe64f 100644 --- a/arch/risc-v/src/common/riscv_misaligned.c +++ b/arch/risc-v/src/common/riscv_misaligned.c @@ -363,6 +363,7 @@ static bool decode_insn_compressed(uintptr_t *regs, riscv_insn_ctx_t *ctx) static bool decode_insn(uintptr_t *regs, riscv_insn_ctx_t *ctx) { + static const uintptr_t x0; uint32_t in; int32_t imm; riscv_insn_t insn; @@ -418,7 +419,17 @@ static bool decode_insn(uintptr_t *regs, riscv_insn_ctx_t *ctx) imm = sext(insn.s.imm2 | insn.s.imm1 << 5, 12); ctx->dest = (uint8_t *)regs[insn.s.rs1] + imm; - ctx->src = (uint8_t *)®s[insn.s.rs2]; + + /* If source register is x0, target it to constant register */ + + if (insn.s.rs2 == 0) + { + ctx->src = (uint8_t *)&x0; + } + else + { + ctx->src = (uint8_t *)®s[insn.s.rs2]; + } /* Get data wide bit */