Merged in plwm/nuttx/stm32f746g-disco-sdram (pull request #665)
Add support for STM32F746G-disco board SDRAM * add support for STM32F746G-disco board SDRAM * changed fb config to use SDRAM and fixed compilation Approved-by: GregoryN <gnutt@nuttx.org>
This commit is contained in:
Marcin Wyrwas
GregoryN
parent
8a1f3d6fa1
commit
898fdbded0
143
arch/arm/src/stm32f7/stm32_fmc.h
Normal file
143
arch/arm/src/stm32f7/stm32_fmc.h
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@ -0,0 +1,143 @@
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/************************************************************************************
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* arch/arm/src/stm32f7/stm32_fmc.h
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*
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* Copyright (C) 2018 Gregory Nutt. All rights reserved.
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* Author: Gregory Nutt <gnutt@nuttx.org>
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*
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* Redistribution and use in source and binary forms, with or without
|
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* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in
|
||||
* the documentation and/or other materials provided with the
|
||||
* distribution.
|
||||
* 3. Neither the name NuttX nor the names of its contributors may be
|
||||
* used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
|
||||
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
|
||||
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
|
||||
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
|
||||
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
|
||||
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
|
||||
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*
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************************************************************************************/
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#ifndef __ARCH_ARM_SRC_STM32_STM32F7_FMC_H
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#define __ARCH_ARM_SRC_STM32_STM32F7_FMC_H
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/************************************************************************************
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* Included Files
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************************************************************************************/
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#include <nuttx/config.h>
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#include "chip.h"
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/************************************************************************************
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* Pre-processor Definitions
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************************************************************************************/
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/* Register Offsets *****************************************************************/
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#define STM32_FMC_SDCR1_OFFSET 0x0140 /* SDRAM Control Register, Bank 0 */
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#define STM32_FMC_SDCR2_OFFSET 0x0144 /* SDRAM Control Register, Bank 1 */
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#define STM32_FMC_SDTR1_OFFSET 0x0148 /* SDRAM Timing Register, Bank 0 */
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#define STM32_FMC_SDTR2_OFFSET 0x014c /* SDRAM Timing Register, Bank 1 */
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#define STM32_FMC_SDCMR_OFFSET 0x0150 /* SDRAM Config Memory register */
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#define STM32_FMC_SDRTR_OFFSET 0x0154 /* SDRAM Refresh Timing Register maybe */
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#define STM32_FMC_SDSR_OFFSET 0x0158 /* SDRAM Status Register */
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/* Register Addresses ***************************************************************/
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#define STM32_FMC_SDCR1 (STM32_FMC_BASE+STM32_FMC_SDCR1_OFFSET)
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#define STM32_FMC_SDCR2 (STM32_FMC_BASE+STM32_FMC_SDCR2_OFFSET)
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#define STM32_FMC_SDTR1 (STM32_FMC_BASE+STM32_FMC_SDTR1_OFFSET)
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#define STM32_FMC_SDTR2 (STM32_FMC_BASE+STM32_FMC_SDTR2_OFFSET)
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#define STM32_FMC_SDCMR (STM32_FMC_BASE+STM32_FMC_SDCMR_OFFSET)
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#define STM32_FMC_SDRTR (STM32_FMC_BASE+STM32_FMC_SDRTR_OFFSET)
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#define STM32_FMC_SDSR (STM32_FMC_BASE+STM32_FMC_SDSR_OFFSET)
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/* Register Bitfield Definitions ****************************************************/
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#define FMC_SDRAM_CR_COLBITS_8 0x00000000
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#define FMC_SDRAM_CR_COLBITS_9 0x00000001
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#define FMC_SDRAM_CR_COLBITS_10 0x00000002
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#define FMC_SDRAM_CR_COLBITS_11 0x00000003
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#define FMC_SDRAM_CR_ROWBITS_11 0x00000000
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#define FMC_SDRAM_CR_ROWBITS_12 0x00000004
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#define FMC_SDRAM_CR_ROWBITS_13 0x00000008
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#define FMC_SDRAM_CR_WIDTH_8 0x00000000
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#define FMC_SDRAM_CR_WIDTH_16 0x00000010
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#define FMC_SDRAM_CR_WIDTH_32 0x00000020
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#define FMC_SDRAM_CR_BANKS_2 0x00000000
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#define FMC_SDRAM_CR_BANKS_4 0x00000040
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#define FMC_SDRAM_CR_CASLAT_1 0x00000080
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#define FMC_SDRAM_CR_CASLAT_2 0x00000100
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#define FMC_SDRAM_CR_CASLAT_3 0x00000180
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#define FMC_SDRAM_CR_WRITE_PROT 0x00000200
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#define FMC_SDRAM_CR_SDCLK_DISABLE 0x00000000
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#define FMC_SDRAM_CR_SDCLK_2X 0x00000800
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#define FMC_SDRAM_CR_SDCLK_3X 0x00000C00
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#define FMC_SDRAM_CR_BURST_READ 0x00001000
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#define FMC_SDRAM_CR_RPIPE_0 0x00000000
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#define FMC_SDRAM_CR_RPIPE_1 0x00002000
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#define FMC_SDRAM_CR_RPIPE_2 0x00004000
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#define FMC_SDRAM_TR_TMRD_SHIFT 0
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#define FMC_SDRAM_TR_TXSR_SHIFT 4
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#define FMC_SDRAM_TR_TRAS_SHIFT 8
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#define FMC_SDRAM_TR_TRC_SHIFT 12
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#define FMC_SDRAM_TR_TWR_SHIFT 16
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#define FMC_SDRAM_TR_TRP_SHIFT 20
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#define FMC_SDRAM_TR_TRCD_SHIFT 24
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#define FMC_SDRAM_MODE_CMD_NORMAL 0
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#define FMC_SDRAM_MODE_CMD_CLK_ENABLE 1
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#define FMC_SDRAM_MODE_CMD_PALL 2
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#define FMC_SDRAM_MODE_CMD_AUTO_REFRESH 3
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#define FMC_SDRAM_MODE_CMD_LOAD_MODE 4
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#define FMC_SDRAM_MODE_CMD_SELF_REFRESH 5
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#define FMC_SDRAM_MODE_CMD_POWER_DOWN 6
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#define FMC_SDRAM_CMD_BANK_1 0x00000010
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#define FMC_SDRAM_CMD_BANK_2 0x00000008
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#define FMC_SDRAM_AUTO_REFRESH_SHIFT 5
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#define FMC_SDRAM_MODEREG_SHIFT 9
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#define FMC_SDRAM_MODEREG_BURST_LENGTH_1 (0x0000 << FMC_SDRAM_MODEREG_SHIFT)
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#define FMC_SDRAM_MODEREG_BURST_LENGTH_2 (0x0001 << FMC_SDRAM_MODEREG_SHIFT)
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#define FMC_SDRAM_MODEREG_BURST_LENGTH_4 (0x0002 << FMC_SDRAM_MODEREG_SHIFT)
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#define FMC_SDRAM_MODEREG_BURST_LENGTH_8 (0x0004 << FMC_SDRAM_MODEREG_SHIFT)
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#define FMC_SDRAM_MODEREG_BURST_TYPE_SEQUENTIAL (0x0000 << FMC_SDRAM_MODEREG_SHIFT)
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#define FMC_SDRAM_MODEREG_BURST_TYPE_INTERLEAVED (0x0008 << FMC_SDRAM_MODEREG_SHIFT)
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#define FMC_SDRAM_MODEREG_CAS_LATENCY_2 (0x0020 << FMC_SDRAM_MODEREG_SHIFT)
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#define FMC_SDRAM_MODEREG_CAS_LATENCY_3 (0x0030 << FMC_SDRAM_MODEREG_SHIFT)
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#define FMC_SDRAM_MODEREG_OPERATING_MODE_STANDARD (0x0000 << FMC_SDRAM_MODEREG_SHIFT)
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#define FMC_SDRAM_MODEREG_WRITEBURST_MODE_PROGRAMMED (0x0000 << FMC_SDRAM_MODEREG_SHIFT)
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#define FMC_SDRAM_MODEREG_WRITEBURST_MODE_SINGLE (0x0200 << FMC_SDRAM_MODEREG_SHIFT)
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#endif /* __ARCH_ARM_SRC_STM32_STM32F7_FMC_H */
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@ -3,49 +3,6 @@ README.txt
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STM32F746G-DISCO LTDC Framebuffer demo example
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Preparation
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-----------
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As of writing this text, SDRAM support is not implemented for this board.
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Therefore to make this demo work following changes are required to heap
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management function:
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diff --git a/stm32_allocateheap.c b/stm32_allocateheap.c
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--- a/stm32_allocateheap.c
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+++ b/stm32_allocateheap.c
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@@ -93,7 +93,7 @@
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/* Set the start and end of SRAM1 and SRAM2 */
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#define SRAM1_START STM32_SRAM1_BASE
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-#define SRAM1_END (SRAM1_START + STM32F7_SRAM1_SIZE)
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+#define SRAM1_END (SRAM1_START + 131072)
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#define SRAM2_START STM32_SRAM2_BASE
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#define SRAM2_END (SRAM2_START + STM32F7_SRAM2_SIZE)
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@@ -385,17 +385,17 @@ void up_addregion(void)
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/* Allow user-mode access to the STM32F20xxx/STM32F40xxx SRAM2 heap */
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- stm32_mpu_uheap((uintptr_t)SRAM2_START, SRAM2_END-SRAM2_START);
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+/* stm32_mpu_uheap((uintptr_t)SRAM2_START, SRAM2_END-SRAM2_START); */
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#endif
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/* Colorize the heap for debug */
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- up_heap_color((FAR void *)SRAM2_START, SRAM2_END-SRAM2_START);
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+/* up_heap_color((FAR void *)SRAM2_START, SRAM2_END-SRAM2_START); */
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/* Add the STM32F20xxx/STM32F40xxx SRAM2 user heap region. */
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- kumm_addregion((FAR void *)SRAM2_START, SRAM2_END-SRAM2_START);
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+/* kumm_addregion((FAR void *)SRAM2_START, SRAM2_END-SRAM2_START); */
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#ifdef HAVE_DTCM
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#if defined(CONFIG_BUILD_PROTECTED) && defined(CONFIG_MM_KERNEL_HEAP)
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Configure and build
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-------------------
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@ -57,7 +14,7 @@ Configuration
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------------
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This configuration provides 1 LTDC with
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8pp CLUT pixel format and a resolution of 480x272.
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16bpp pixel format and a resolution of 480x272.
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Loading
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@ -70,7 +27,8 @@ Executing
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---------
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The ltdc is initialized during boot up. Interaction with NSH is via the serial
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console at 115200 8N1 baud. From the nsh comandline execute the fb example:
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console provided by ST-LINK USB at 115200 8N1 baud.
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From the nsh comandline execute the fb example:
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nsh> fb
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@ -1,6 +1,7 @@
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# CONFIG_ARCH_FPU is not set
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# CONFIG_NSH_DISABLE_IFCONFIG is not set
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# CONFIG_NSH_DISABLE_PS is not set
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# CONFIG_STM32F7_FB_CMAP is not set
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# CONFIG_STM32F7_LTDC_L2 is not set
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CONFIG_ARCH="arm"
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CONFIG_ARCH_BOARD="stm32f746g-disco"
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@ -17,6 +18,7 @@ CONFIG_ARMV7M_TOOLCHAIN_GNU_EABIL=y
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CONFIG_BOARD_INITIALIZE=y
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CONFIG_BOARD_LOOPSPERMSEC=43103
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CONFIG_BUILTIN=y
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CONFIG_DEBUG_FULLOPT=y
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CONFIG_DEBUG_SYMBOLS=y
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CONFIG_DISABLE_POLL=y
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CONFIG_DRIVERS_VIDEO=y
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@ -50,11 +52,10 @@ CONFIG_SPI=y
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CONFIG_START_DAY=6
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CONFIG_START_MONTH=12
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CONFIG_START_YEAR=2011
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CONFIG_STM32F7_FMC=y
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CONFIG_STM32F7_LTDC=y
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CONFIG_STM32F7_LTDC_FB_BASE=0x20030000
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CONFIG_STM32F7_LTDC_FB_SIZE=130560
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CONFIG_STM32F7_LTDC_INTERFACE=y
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CONFIG_STM32F7_LTDC_L1_L8=y
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CONFIG_STM32F7_LTDC_FB_BASE=0xc0000000
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CONFIG_STM32F7_LTDC_FB_SIZE=261120
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CONFIG_STM32F7_USART1=y
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CONFIG_TASK_NAME_SIZE=0
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CONFIG_USART1_SERIAL_CONSOLE=y
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@ -68,4 +68,8 @@ ifeq ($(CONFIG_STM32F7_LTDC),y)
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CSRCS += stm32_lcd.c
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endif
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ifeq ($(CONFIG_STM32F7_FMC),y)
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CSRCS += stm32_extmem.c
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endif
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include $(TOPDIR)/configs/Board.mk
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@ -89,6 +89,10 @@ void stm32_boardinitialize(void)
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board_autoled_initialize();
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#endif
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#ifdef CONFIG_STM32F7_FMC
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stm32_enablefmc();
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#endif
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}
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/************************************************************************************
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249
configs/stm32f746g-disco/src/stm32_extmem.c
Normal file
249
configs/stm32f746g-disco/src/stm32_extmem.c
Normal file
@ -0,0 +1,249 @@
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/************************************************************************************
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* configs/stm32f746g-disco/src/stm32_extmem.c
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*
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* Copyright (C) 2018 Marcin Wyrwas. All rights reserved.
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* Author: Marcin Wyrwas <mvp1@wp.pl>
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*
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* Redistribution and use in source and binary forms, with or without
|
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* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in
|
||||
* the documentation and/or other materials provided with the
|
||||
* distribution.
|
||||
* 3. Neither the name NuttX nor the names of its contributors may be
|
||||
* used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
|
||||
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
|
||||
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
|
||||
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
|
||||
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
|
||||
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
|
||||
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
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************************************************************************************/
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/************************************************************************************
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* Included Files
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************************************************************************************/
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#include <nuttx/config.h>
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#include <stdint.h>
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#include <assert.h>
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#include <debug.h>
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#include "chip.h"
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#include "up_arch.h"
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#include "stm32_fmc.h"
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#include "stm32_gpio.h"
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#include "stm32_rcc.h"
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#include "stm32f746g-disco.h"
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#include <arch/board/board.h>
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/************************************************************************************
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* Pre-processor Definitions
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************************************************************************************/
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#ifndef CONFIG_STM32F7_FMC
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# warning "FMC is not enabled"
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#endif
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#if STM32F7_NGPIO < 7
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# error "Required GPIO ports not enabled"
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#endif
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#define STM32_FMC_NADDRCONFIGS 22
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#define STM32_FMC_NDATACONFIGS 16
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#define STM32_SDRAM_CLKEN FMC_SDRAM_MODE_CMD_CLK_ENABLE | FMC_SDRAM_CMD_BANK_1
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#define STM32_SDRAM_PALL FMC_SDRAM_MODE_CMD_PALL | FMC_SDRAM_CMD_BANK_1
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#define STM32_SDRAM_REFRESH FMC_SDRAM_MODE_CMD_AUTO_REFRESH | FMC_SDRAM_CMD_BANK_1 |\
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(7 << FMC_SDRAM_AUTO_REFRESH_SHIFT)
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#define STM32_SDRAM_MODEREG FMC_SDRAM_MODE_CMD_LOAD_MODE | FMC_SDRAM_CMD_BANK_1 |\
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FMC_SDRAM_MODEREG_BURST_LENGTH_1 | \
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FMC_SDRAM_MODEREG_BURST_TYPE_SEQUENTIAL |\
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FMC_SDRAM_MODEREG_CAS_LATENCY_3 |\
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FMC_SDRAM_MODEREG_WRITEBURST_MODE_SINGLE
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/************************************************************************************
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* Public Data
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************************************************************************************/
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/* GPIO configurations common to most external memories */
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static const uint32_t g_addressconfig[STM32_FMC_NADDRCONFIGS] =
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{
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GPIO_FMC_A0, GPIO_FMC_A1, GPIO_FMC_A2, GPIO_FMC_A3, GPIO_FMC_A4 , GPIO_FMC_A5,
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GPIO_FMC_A6, GPIO_FMC_A7, GPIO_FMC_A8, GPIO_FMC_A9, GPIO_FMC_A10, GPIO_FMC_A11,
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GPIO_FMC_SDCKE0_1, GPIO_FMC_SDNE0_3, GPIO_FMC_SDNWE_3, GPIO_FMC_NBL0,
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GPIO_FMC_SDNRAS, GPIO_FMC_NBL1, GPIO_FMC_BA0, GPIO_FMC_BA1,
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GPIO_FMC_SDCLK, GPIO_FMC_SDNCAS
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};
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static const uint32_t g_dataconfig[STM32_FMC_NDATACONFIGS] =
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{
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GPIO_FMC_D0, GPIO_FMC_D1 , GPIO_FMC_D2, GPIO_FMC_D3, GPIO_FMC_D4 , GPIO_FMC_D5,
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GPIO_FMC_D6, GPIO_FMC_D7, GPIO_FMC_D8, GPIO_FMC_D9, GPIO_FMC_D10, GPIO_FMC_D11,
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GPIO_FMC_D12, GPIO_FMC_D13, GPIO_FMC_D14, GPIO_FMC_D15
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};
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/************************************************************************************
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* Private Data
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************************************************************************************/
|
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/************************************************************************************
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* Private Functions
|
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************************************************************************************/
|
||||
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/************************************************************************************
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* Public Functions
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||||
************************************************************************************/
|
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/************************************************************************************
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* Name: stm32_extmemgpios
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*
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* Description:
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* Initialize GPIOs for external memory usage
|
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*
|
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************************************************************************************/
|
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static void stm32_extmemgpios(const uint32_t *gpios, int ngpios)
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{
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int i;
|
||||
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/* Configure GPIOs */
|
||||
|
||||
for (i = 0; i < ngpios; i++)
|
||||
{
|
||||
stm32_configgpio(gpios[i]);
|
||||
}
|
||||
}
|
||||
|
||||
/************************************************************************************
|
||||
* Name: stm32_sdramcommand
|
||||
*
|
||||
* Description:
|
||||
* Initialize data line GPIOs for external memory access
|
||||
*
|
||||
************************************************************************************/
|
||||
|
||||
static void stm32_sdramcommand(uint32_t command)
|
||||
{
|
||||
uint32_t regval;
|
||||
volatile uint32_t timeout = 0xFFFF;
|
||||
|
||||
regval = getreg32( STM32_FMC_SDSR ) & 0x00000020;
|
||||
while ((regval != 0) && timeout-- > 0)
|
||||
{
|
||||
regval = getreg32( STM32_FMC_SDSR ) & 0x00000020;
|
||||
}
|
||||
putreg32(command, STM32_FMC_SDCMR);
|
||||
timeout = 0xFFFF;
|
||||
regval = getreg32( STM32_FMC_SDSR ) & 0x00000020;
|
||||
while ((regval != 0) && timeout-- > 0)
|
||||
{
|
||||
regval = getreg32( STM32_FMC_SDSR ) & 0x00000020;
|
||||
}
|
||||
}
|
||||
|
||||
/************************************************************************************
|
||||
* Name: stm32_enablefmc
|
||||
*
|
||||
* Description:
|
||||
* enable clocking to the FMC module
|
||||
*
|
||||
************************************************************************************/
|
||||
|
||||
void stm32_enablefmc(void)
|
||||
{
|
||||
uint32_t regval;
|
||||
volatile int count;
|
||||
|
||||
/* Enable GPIOs as FMC / memory pins */
|
||||
|
||||
stm32_extmemgpios(g_addressconfig, STM32_FMC_NADDRCONFIGS);
|
||||
stm32_extmemgpios(g_dataconfig, STM32_FMC_NDATACONFIGS);
|
||||
|
||||
/* Enable AHB clocking to the FMC */
|
||||
|
||||
regval = getreg32( STM32_RCC_AHB3ENR);
|
||||
regval |= RCC_AHB3ENR_FMCEN;
|
||||
putreg32(regval, STM32_RCC_AHB3ENR);
|
||||
|
||||
/* Configure and enable the SDRAM bank1
|
||||
*
|
||||
* FMC clock = 216MHz/2 = 108MHz
|
||||
* 108MHz = 9,26 ns
|
||||
* All timings from the datasheet for Speedgrade -6A (=6ns)
|
||||
*/
|
||||
|
||||
putreg32(FMC_SDRAM_CR_RPIPE_0 |
|
||||
FMC_SDRAM_CR_BURST_READ |
|
||||
FMC_SDRAM_CR_SDCLK_2X |
|
||||
FMC_SDRAM_CR_CASLAT_3 |
|
||||
FMC_SDRAM_CR_BANKS_4 |
|
||||
FMC_SDRAM_CR_WIDTH_16 |
|
||||
FMC_SDRAM_CR_ROWBITS_12 |
|
||||
FMC_SDRAM_CR_COLBITS_8,
|
||||
STM32_FMC_SDCR1);
|
||||
|
||||
putreg32((1 << FMC_SDRAM_TR_TRCD_SHIFT) | /* tRCD min = 18ns */
|
||||
(1 << FMC_SDRAM_TR_TRP_SHIFT) | /* tRP min = 18ns */
|
||||
(1 << FMC_SDRAM_TR_TWR_SHIFT) | /* tWR = 2CLK */
|
||||
(6 << FMC_SDRAM_TR_TRC_SHIFT) | /* tRC min = 64ns */
|
||||
(4 << FMC_SDRAM_TR_TRAS_SHIFT) | /* tRAS min = 46ns */
|
||||
(7 << FMC_SDRAM_TR_TXSR_SHIFT) | /* tXSR min = 74ns */
|
||||
(1 << FMC_SDRAM_TR_TMRD_SHIFT), /* tMRD = 2CLK */
|
||||
STM32_FMC_SDTR1);
|
||||
|
||||
/* SDRAM Initialization sequence */
|
||||
|
||||
stm32_sdramcommand(STM32_SDRAM_CLKEN); /* Clock enable command */
|
||||
for (count = 0; count < 10000; count++) ; /* Delay */
|
||||
stm32_sdramcommand(STM32_SDRAM_PALL); /* Precharge ALL command */
|
||||
stm32_sdramcommand(STM32_SDRAM_REFRESH); /* Auto refresh command */
|
||||
stm32_sdramcommand(STM32_SDRAM_MODEREG); /* Mode Register program */
|
||||
|
||||
/* Set refresh count
|
||||
*
|
||||
* FMC_CLK = 108MHz
|
||||
* Refresh_Rate = 64ms / 4096 rows = 15.63us
|
||||
* Counter = (FMC_CLK * Refresh_Rate) - 20
|
||||
*/
|
||||
|
||||
putreg32(1668 << 1, STM32_FMC_SDRTR);
|
||||
}
|
||||
|
||||
/************************************************************************************
|
||||
* Name: stm32_disablefmc
|
||||
*
|
||||
* Description:
|
||||
* enable clocking to the FMC module
|
||||
*
|
||||
************************************************************************************/
|
||||
|
||||
void stm32_disablefmc(void)
|
||||
{
|
||||
uint32_t regval;
|
||||
|
||||
/* Disable AHB clocking to the FMC */
|
||||
|
||||
regval = getreg32(STM32_RCC_AHB3ENR);
|
||||
regval &= ~(uint32_t)RCC_AHB3ENR_FMCEN;
|
||||
putreg32(regval, STM32_RCC_AHB3ENR);
|
||||
}
|
||||
@ -159,6 +159,32 @@ void weak_function stm32_spidev_initialize(void);
|
||||
void arch_sporadic_initialize(void);
|
||||
#endif
|
||||
|
||||
/****************************************************************************
|
||||
|
||||
* Name: stm32_enablefmc
|
||||
*
|
||||
* Description:
|
||||
* enable clocking to the FMC module
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
#ifdef CONFIG_STM32F7_FMC
|
||||
void stm32_enablefmc(void);
|
||||
#endif
|
||||
|
||||
/****************************************************************************
|
||||
|
||||
* Name: stm32_disablefmc
|
||||
*
|
||||
* Description:
|
||||
* disable clocking to the FMC module
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
#ifdef CONFIG_STM32F7_FMC
|
||||
void stm32_disablefmc(void);
|
||||
#endif
|
||||
|
||||
#endif /* __ASSEMBLY__ */
|
||||
|
||||
#endif /* __CONFIGS_STM32F746G_DISCO_SRC_STM32F746G_DISCO_H */
|
||||
|
||||
Loading…
Reference in New Issue
Block a user