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I2S register bit definitions

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git-svn-id: svn://svn.code.sf.net/p/nuttx/code/trunk@2719 42af7a65-404d-4744-a932-0658087f49c3
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patacongo 2010-05-30 19:40:34 +00:00
parent 58499e5e8e
commit 89975a4f67
1 changed files with 85 additions and 23 deletions
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108
arch/arm/src/lpc17xx/lpc17_i2s.h
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@ -86,33 +86,95 @@
/* Register bit definitions *********************************************************/
/* Digital Audio Output Register */
#define I2S_DAO_
#define I2S_DAO_WDWID_SHIFT (0) /* Bits 0-1: Selects the number of bytes in data */
#define I2S_DAO_WDWID_MASK (3 << I2S_DAO_WDWID_SHIFT)
# define I2S_DAO_WDWID_8BITS (0 << I2S_DAO_WDWID_SHIFT)
# define I2S_DAO_WDWID_16BITS (1 << I2S_DAO_WDWID_SHIFT)
# define I2S_DAO_WDWID_32BITS (2 << I2S_DAO_WDWID_SHIFT)
#define I2S_DAO_MONO (1 << 2) /* Bit 2: Mono format */
#define I2S_DAO_STOP (1 << 3) /* Bit 3: Disable FIFOs / mute mode */
#define I2S_DAO_RESET (1 << 4) /* Bit 4: Reset TX channel and FIFO */
#define I2S_DAO_WSSEL (1 << 5) /* Bit 5: Slave mode select */
#define I2S_DAO_WSHALFPER_SHIFT (6) /* Bits 6-14: Word select half period minus 1 */
#define I2S_DAO_WSHALFPER_MASK (0x01ff << I2S_DAO_WSHALFPER_SHIFT)
#define I2S_DAO_MUTE (1 << 15) /* Bit 15: Send only zeros on channel */
/* Bits 16-31: Reserved */
/* Digital Audio Input Register */
#define I2S_DAI_
/* Transmit FIFO */
#define I2S_TXFIFO_
/* Receive FIFO */
#define I2S_RXFIFO_
#define I2S_DAI_WDWID_SHIFT (0) /* Bits 0-1: Selects the number of bytes in data */
#define I2S_DAI_WDWID_MASK (3 << I2S_DAI_WDWID_SHIFT)
# define I2S_DAI_WDWID_8BITS (0 << I2S_DAI_WDWID_SHIFT)
# define I2S_DAI_WDWID_16BITS (1 << I2S_DAI_WDWID_SHIFT)
# define I2S_DAI_WDWID_32BITS (2 << I2S_DAI_WDWID_SHIFT)
#define I2S_DAI_MONO (1 << 2) /* Bit 2: Mono format */
#define I2S_DAI_STOP (1 << 3) /* Bit 3: Disable FIFOs / mute mode */
#define I2S_DAI_RESET (1 << 4) /* Bit 4: Reset TX channel and FIFO */
#define I2S_DAI_WSSEL (1 << 5) /* Bit 5: Slave mode select */
#define I2S_DAI_WSHALFPER_SHIFT (6) /* Bits 6-14: Word select half period minus 1 */
#define I2S_DAI_WSHALFPER_MASK (0x01ff << I2S_DAI_WSHALFPER_SHIFT)
/* Bits 15-31: Reserved */
/* Transmit FIFO: 8 × 32-bit transmit FIFO */
/* Receive FIFO: 8 × 32-bit receive FIFO */
/* Status Feedback Register */
#define I2S_STATE_
/* DMA Configuration Register 1 */
#define I2S_DMA1_
/* DMA Configuration Register 2 */
#define I2S_DMA2_
#define I2S_STATE_IRQ (1 << 0) /* Bit 0: Receive Transmit Interrupt */
#define I2S_STATE_DMAREQ1 (1 << 1) /* Bit 1: Receive or Transmit DMA Request 1 */
#define I2S_STATE_DMAREQ2 (1 << 2) /* Bit 2: Receive or Transmit DMA Request 2 */
/* Bits 3-7: Reserved */
#define I2S_STATE_RXLEVEL_SHIFT (8) /* Bits 8-11: Current level of the Receive FIFO */
#define I2S_STATE_RXLEVEL_MASK (15 << I2S_STATE_RXLEVEL_SHIFT)
/* Bits 12-15: Reserved */
#define I2S_STATE_TXLEVEL_SHIFT (16) /* Bits 16-19: Current level of the Transmit FIFO */
#define I2S_STATE_TXLEVEL_MASK (15 << I2S_STATE_TXLEVEL_SHIFT)
/* Bits 20-31: Reserved */
/* DMA Configuration Register 1 and 2 */
#define I2S_DMA_RXDMAEN (1 << 0) /* Bit 0: Enable DMA1 for I2S receive */
#define I2S_DMA_TXDMAEN (1 << 1) /* Bit 1: Enable DMA1 for I2S transmit */
/* Bits 3-7: Reserved */
#define I2S_DMA_RXDEPTH_SHIFT (8) /* Bits 8-11: FIFO level that triggers RX request on DMA1 */
#define I2S_DMA_RXDEPTH_MASK (15 << I2S_DMA_RXDEPTH_SHIFT)
/* Bits 12-15: Reserved */
#define I2S_DMA_TXDEPTH_SHIFT (16) /* Bits 16-19: FIFO level that triggers a TX request on DMA1 */
#define I2S_DMA_TXDEPTH_MASK (15 << I2S_DMA_TXDEPTH_SHIFT)
/* Bits 20-31: Reserved */
/* Interrupt Request Control Register */
#define I2S_IRQ_
/* Transmit MCLK divider */
#define I2S_TXRATE_
/* Receive MCLK divider */
#define I2S_RXRATE_
/* Transmit bit rate divider */
#define I2S_TXBITRATE_
/* Receive bit rate divider */
#define I2S_RXBITRATE_
/* Transmit mode control */
#define I2S_TXMODE_
/* Receive mode control */
#define I2S_RXMODE_
#define I2S_IRQ_RXEN (1 << 0) /* Bit 0: Enable I2S receive interrupt */
#define I2S_IRQ_TXEN (1 << 1) /* Bit 1: Enable I2S transmit interrupt */
/* Bits 3-7: Reserved */
#define I2S_IRQ_RXDEPTH_SHIFT (8) /* Bits 8-11: Set FIFO level for irq request */
#define I2S_IRQ_RXDEPTH_MASK (15 << I2S_IRQ_RXDEPTH_SHIFT)
/* Bits 12-15: Reserved */
#define I2S_IRQ_TXDEPTH_SHIFT (16) /* Bits 16-19: Set FIFO level for irq request */
#define I2S_IRQ_TXDEPTH_MASK (15 << I2S_IRQ_TXDEPTH_SHIFT)
/* Bits 20-31: Reserved */
/* Transmit and Receive MCLK divider */
#define I2S_RATE_YDIV_SHIFT (0) /* Bits 0-7: I2S transmit MCLK rate denominator */
#define I2S_RATE_YDIV_MASK (0xff << I2S_RATE_YDIV_SHIFT)
#define I2S_RATE_XDIV_SHIFT (8) /* Bits 8-15: I2S transmit MCLK rate numerator */
#define I2S_RATE_XDIV_MASK (0xff << I2S_RATE_XDIV_SHIFT)
/* Bits 16-31: Reserved */
/* Transmit and received bit rate divider */
#define I2S_BITRATE_SHIFT (0) /* Bits 0-5: I2S transmit bit rate */
#define I2S_BITRATE_MASK (0x3f << I2S_BITRATE_SHIFT)
/* Bits 6-31: Reserved */
/* Transmit and Receive mode control */
#define I2S_MODE_CLKSEL_SHIFT (0) /* Bits 0-1: Clock source for bit clock divider */
#define I2S_MODE_CLKSEL_MASK (3 << I2S_MODE_CLKSEL_SHIFT)
# define I2S_MODE_CLKSEL_FRACDIV (0 << I2S_MODE_CLKSEL_SHIFT) /* TX/RX fractional rate divider */
# define I2S_MODE_CLKSEL_RXMCLK (2 << I2S_MODE_CLKSEL_SHIFT) /* RX_CLCK for TX_MCLK source */
# define I2S_MODE_CLKSEL_TXMCLK (2 << I2S_MODE_CLKSEL_SHIFT) /* TX_CLCK for RX_MCLK source */
#define I2S_MODE_4PIN (1 << 2) /* Bit 2: Transmit/Receive 4-pin mode selection */
#define I2S_MODE_MCENA (1 << 3) /* Bit 3: Enable for the TX/RX_MCLK output */
/* Bits 4-31: Reserved */
/************************************************************************************
* Public Types