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Un-neccesary, cosmetic changes to label names and comments

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This commit is contained in:
Gregory Nutt 2013-09-22 08:54:06 -06:00
parent 3ceac07042
commit 8a1e33cb10
6 changed files with 11 additions and 9 deletions
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4
arch/arm/src/armv7-a/cp15_clean_dcache.S
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@ -103,11 +103,11 @@ cp15_clean_dcache:
/* Loop, cleaning each cache line by writing its contents to memory */ /* Loop, cleaning each cache line by writing its contents to memory */
4: 1:
mcr CP15_DCCMVAC(r0) /* Clean data cache line to PoC by VA */ mcr CP15_DCCMVAC(r0) /* Clean data cache line to PoC by VA */
add r0, r0, r2 /* R12=Next cache line */ add r0, r0, r2 /* R12=Next cache line */
cmp r0, r1 /* Loop until all cache lines have been cleaned */ cmp r0, r1 /* Loop until all cache lines have been cleaned */
blo 4b blo 1b
dsb dsb
bx lr bx lr

4
arch/arm/src/armv7-a/cp15_coherent_dcache.S
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@ -120,11 +120,11 @@ cp15_coherent_dcache:
bic r12, r0, r3 /* R12=aligned start address */ bic r12, r0, r3 /* R12=aligned start address */
/* Loop, invalidating each I cache line to memory */ /* Loop, invalidating each I cache line to memory */
2: 1:
mcr CP15_ICIMVAU(r12) /* Invalidate instruction cache by VA to PoU */ mcr CP15_ICIMVAU(r12) /* Invalidate instruction cache by VA to PoU */
add r12, r12, r2 /* R12=Next cache line */ add r12, r12, r2 /* R12=Next cache line */
cmp r12, r1 /* Loop until all cache lines have been invalidated */ cmp r12, r1 /* Loop until all cache lines have been invalidated */
blo 2b blo 1b
mov r0, #0 mov r0, #0
mcr CP15_BPIALLIS(r0) /* Invalidate entire branch predictor array Inner Shareable */ mcr CP15_BPIALLIS(r0) /* Invalidate entire branch predictor array Inner Shareable */

4
arch/arm/src/armv7-a/cp15_flush_dcache.S
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@ -103,11 +103,11 @@ cp15_flush_dcache:
/* Loop, cleaning and invaliding each D cache line in the address range */ /* Loop, cleaning and invaliding each D cache line in the address range */
5: 1:
mcrne CP15_DCCIMVAC(r0) /* Clean and invalidate data cache line by VA to PoC */ mcrne CP15_DCCIMVAC(r0) /* Clean and invalidate data cache line by VA to PoC */
add r0, r0, r2 /* R12=Next cache line */ add r0, r0, r2 /* R12=Next cache line */
cmp r0, r1 /* Loop until all cache lines have been cleaned */ cmp r0, r1 /* Loop until all cache lines have been cleaned */
blo 5b blo 1b
dsb dsb
bx lr bx lr

4
arch/arm/src/armv7-a/cp15_invalidate_dcache.S
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@ -110,11 +110,11 @@ cp15_invalidate_dcache:
mcrne CP15_DCCIMVAC(r1) /* Clean and invalidate data cache line by VA to PoC */ mcrne CP15_DCCIMVAC(r1) /* Clean and invalidate data cache line by VA to PoC */
/* Loop, invalidating each D cache line */ /* Loop, invalidating each D cache line */
3: 1:
mcr CP15_DCIMVAC(r0) /* Invalidate data cache line by VA to PoC */ mcr CP15_DCIMVAC(r0) /* Invalidate data cache line by VA to PoC */
add r0, r0, r2 /* R12=Next cache line */ add r0, r0, r2 /* R12=Next cache line */
cmp r0, r1 /* Loop until all cache lines have been invalidate */ cmp r0, r1 /* Loop until all cache lines have been invalidate */
blo 3b blo 1b
dsb dsb
bx lr bx lr

2
arch/arm/src/armv7-a/cp15_invalidate_dcache_all.S
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@ -96,6 +96,7 @@ cp15_invalidate_dcache_all:
mov r1, #0 /* r1 = way loop counter */ mov r1, #0 /* r1 = way loop counter */
way_loop: way_loop:
mov r3, #0 /* r3 = set loop counter */ mov r3, #0 /* r3 = set loop counter */
set_loop: set_loop:
mov r2, r1, lsl #30 /* r2 = way loop counter << 30 */ mov r2, r1, lsl #30 /* r2 = way loop counter << 30 */
@ -104,6 +105,7 @@ set_loop:
add r3, r3, #1 /* Increment set counter */ add r3, r3, #1 /* Increment set counter */
cmp r0, r3 /* Last set? */ cmp r0, r3 /* Last set? */
bne set_loop /* Keep looping if not */ bne set_loop /* Keep looping if not */
add r1, r1, #1 /* Increment the way counter */ add r1, r1, #1 /* Increment the way counter */
cmp r1, #4 /* Last way? (four ways assumed) */ cmp r1, #4 /* Last way? (four ways assumed) */
bne way_loop /* Keep looping if not */ bne way_loop /* Keep looping if not */

2
arch/arm/src/sama5/sam_udphs.c
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@ -2420,7 +2420,7 @@ static void sam_dma_interrupt(struct sam_usbdev_s *priv, int epno)
/* This is an OUT endpoint. Invalidate the data cache for /* This is an OUT endpoint. Invalidate the data cache for
* region that just completed DMA. This will force the * region that just completed DMA. This will force the
* buffer data to be reloaded from RAM. when it is accessed * buffer data to be reloaded from RAM when it is accessed.
*/ */
DEBUGASSERT(USB_ISEPOUT(privep->ep.eplog)); DEBUGASSERT(USB_ISEPOUT(privep->ep.eplog));