arch/intel64: clear BSS in __nxstart

BSS nulling can now be optimized by the compiler, so it is necessary
to enable SSE instructions early in __nxstart

Signed-off-by: p-szafonimateusz <p-szafonimateusz@xiaomi.com>

arch/x86_64/src/intel64/intel64_head.S

@@ -266,15 +266,6 @@ start64:
     mov     %ax,    %fs
     mov     %ax,    %gs
 
-    /* Clear out bss section */
-    movabs  $_sbss, %rbx
-    movabs  $_ebss, %rdx
-clear_bss:
-    movb    $0,    (%rbx)
-    inc     %rbx
-    cmp     %rbx,   %rdx
-    jne     clear_bss
-
     /* Properly setup RSP to idle stack */
     movabs  $g_idle_topstack,    %rbx
     mov     (%rbx),   %rsp

arch/x86_64/src/intel64/intel64_lowsetup.c

@@ -89,10 +89,6 @@ void intel64_lowsetup(void)
 
   setgdt((void *)gdt64, (uintptr_t)(&gdt64_low_end - &gdt64_low) - 1);
 
-  /* Do some checking on CPU compatibilities */
-
-  x86_64_check_and_enable_capability();
-
   /* Revoke the lower memory */
 
   __revoke_low_memory();

arch/x86_64/src/intel64/intel64_start.c

@@ -107,6 +107,24 @@ static void x86_64_mb2_config(void)
 
 void __nxstart(void)
 {
+  uint64_t *dest = NULL;
+
+  /* Do some checking on CPU compatibilities at the top of this function.
+   * BSS cleanup can be optimized with vector instructions, so we need to
+   * enable SSE at this point.
+   */
+
+  x86_64_check_and_enable_capability();
+
+  /* Clear .bss. The compiler can optimize this with vector instructions,
+   * so this *must be* called after enabling SSE instructions.
+   */
+
+  for (dest = (uint64_t *)_sbss; dest < (uint64_t *)_ebss; )
+    {
+      *dest++ = 0;
+    }
+
   /* Low-level, pre-OS initialization */
 
   intel64_lowsetup();