drivers: add UART 16550 compatible PCI device support
add support for UART 16550 compatible PCI device. For now we support qemu serial PCI devices and AX99100 based cards. Signed-off-by: p-szafonimateusz <p-szafonimateusz@xiaomi.com>
This commit is contained in:
p-szafonimateusz
Xiang Xiao
parent
ceb2921d79
commit
8ab0785d71
@ -63,4 +63,10 @@ if(CONFIG_UART_BTH4)
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list(APPEND SRCS uart_bth4.c)
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endif()
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# UART PCI drivers
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if(CONFIG_16550_PCI_UART)
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list(APPEND SRCS uart_pci_16550.c)
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endif()
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target_sources(drivers PRIVATE ${SRCS})
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@ -79,6 +79,10 @@ if 16550_UART
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source "drivers/serial/Kconfig-16550"
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endif
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if PCI
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source "drivers/serial/Kconfig-pci"
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endif
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#
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# MCU serial peripheral driver?
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#
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327
drivers/serial/Kconfig-pci
Normal file
327
drivers/serial/Kconfig-pci
Normal file
@ -0,0 +1,327 @@
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#
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# For a description of the syntax of this configuration file,
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# see the file kconfig-language.txt in the NuttX tools repository.
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#
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config 16550_PCI_UART
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bool "16550 UART PCI support"
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default n
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select 16550_UART
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if 16550_PCI_UART
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config 16550_PCI_UART0
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bool "16550 UART0 PCI"
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default n
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---help---
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Support for PCI UART0, will be registered as /dev/ttyS0
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config 16550_PCI_UART1
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bool "16550 UART1 PCI"
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default n
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---help---
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Support for PCI UART1, will be registered as /dev/ttyS1
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config 16550_PCI_UART2
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bool "16550 UART2 PCI"
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default n
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---help---
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Support for PCI UART2, will be registered as /dev/ttyS2
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config 16550_PCI_UART3
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bool "16550 UART3 PCI"
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default n
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---help---
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Support for PCI UART3, will be registered as /dev/ttyS3
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config 16550_PCI_UART_QEMU
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bool "16550 PCI QEMU devices"
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default n
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---help---
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Enable support for QEMU serial devices (pci-serial, pci-serial-2x
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pci-serial-4x)
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config 16550_PCI_UART_AX99100
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bool "16550 PCI AX99100 device"
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default n
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---help---
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Enable support for AX99100 serial port device.
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endif # 16550_PCI_UART
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if 16550_PCI_UART0
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config 16550_PCI_UART0_VENDOR
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hex "16550 UART0 PCI vendor"
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---help---
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PCI vendor number that will be associated with UART0
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config 16550_PCI_UART0_DEVICE
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hex "16550 UART0 PCI device"
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---help---
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PCI device number that will be associated with UART0
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config 16550_PCI_UART0_PORT
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int "16550 UART0 PCI port"
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default 0
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---help---
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Port in multi-port device. Starts from 0.
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Must be set to 0 for single port devices .
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config 16550_PCI_UART0_CLOCK
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int "16550 UART0 PCI clock"
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config 16550_PCI_UART0_BAUD
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int "16550 UART0 PCI BAUD"
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default 115200
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config 16550_PCI_UART0_PARITY
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int "16550 UART0 PCI parity"
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default 0
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range 0 2
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---help---
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16550 UART0 PCI parity. 0=None, 1=Odd, 2=Even. Default: None
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config 16550_PCI_UART0_BITS
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int "16550 UART0 PCI number of bits"
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default 8
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---help---
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16550 UART0 PCI number of bits. Default: 8
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config 16550_PCI_UART0_2STOP
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int "16550 UART0 PCI two stop bits"
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default 0
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---help---
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0=1 stop bit, 1=Two stop bits. Default: 1 stop bit
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config 16550_PCI_UART0_RXBUFSIZE
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int "16550 UART0 PCI Rx buffer size"
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default 256
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---help---
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16550 UART0 PCI Rx buffer size. Default: 256
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config 16550_PCI_UART0_TXBUFSIZE
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int "16550 UART0 PCI Tx buffer size"
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default 256
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---help---
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16550 UART0 PCI Tx buffer size. Default: 256
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endif # 16550_PCI_UART0
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if 16550_PCI_UART1
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config 16550_PCI_UART1_VENDOR
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hex "16550 UART1 PCI vendor"
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default 16550_PCI_UART0_VENDOR
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---help---
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PCI vendor number that will be associated with UART1
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config 16550_PCI_UART1_DEVICE
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hex "16550 UART1 PCI device"
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default 16550_PCI_UART0_DEVICE
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---help---
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PCI device number that will be associated with UART1
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config 16550_PCI_UART1_PORT
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int "16550 UART1 PCI port"
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default 1
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---help---
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Port in multi-port device. Starts from 0.
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Must be set to 0 for single port devices .
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config 16550_PCI_UART1_CLOCK
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int "16550 UART1 PCI clock"
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config 16550_PCI_UART1_BAUD
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int "16550 UART1 PCI BAUD"
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default 115200
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config 16550_PCI_UART1_PARITY
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int "16550 UART1 PCI parity"
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default 0
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range 0 2
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---help---
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16550 UART1 PCI parity. 0=None, 1=Odd, 2=Even. Default: None
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config 16550_PCI_UART1_BITS
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int "16550 UART1 PCI number of bits"
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default 8
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---help---
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16550 UART1 PCI number of bits. Default: 8
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config 16550_PCI_UART1_2STOP
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int "16550 UART1 PCI two stop bits"
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default 0
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---help---
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0=1 stop bit, 1=Two stop bits. Default: 1 stop bit
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config 16550_PCI_UART1_RXBUFSIZE
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int "16550 UART1 PCI Rx buffer size"
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default 256
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---help---
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16550 UART1 PCI Rx buffer size. Default: 256
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config 16550_PCI_UART1_TXBUFSIZE
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int "16550 UART1 PCI Tx buffer size"
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default 256
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---help---
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16550 UART1 PCI Tx buffer size. Default: 256
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endif # 16550_PCI_UART1
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if 16550_PCI_UART2
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config 16550_PCI_UART2_VENDOR
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hex "16550 UART2 PCI vendor"
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default 16550_PCI_UART1_VENDOR
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---help---
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PCI vendor number that will be associated with UART2
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config 16550_PCI_UART2_DEVICE
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hex "16550 UART2 PCI device"
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default 16550_PCI_UART1_DEVICE
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---help---
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PCI device number that will be associated with UART2
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config 16550_PCI_UART2_PORT
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int "16550 UART2 PCI port"
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default 2
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---help---
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Port in multi-port device. Starts from 0.
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Must be set to 0 for single port devices .
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config 16550_PCI_UART2_CLOCK
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int "16550 UART2 PCI clock"
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config 16550_PCI_UART2_BAUD
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int "16550 UART2 PCI BAUD"
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default 115200
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config 16550_PCI_UART2_PARITY
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int "16550 UART2 PCI parity"
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default 0
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range 0 2
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---help---
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16550 UART2 PCI parity. 0=None, 1=Odd, 2=Even. Default: None
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config 16550_PCI_UART2_BITS
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int "16550 UART2 PCI number of bits"
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default 8
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---help---
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16550 UART2 PCI number of bits. Default: 8
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config 16550_PCI_UART2_2STOP
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int "16550 UART2 PCI two stop bits"
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default 0
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---help---
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0=1 stop bit, 1=Two stop bits. Default: 1 stop bit
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config 16550_PCI_UART2_RXBUFSIZE
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int "16550 UART2 PCI Rx buffer size"
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default 256
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---help---
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16550 UART2 PCI Rx buffer size. Default: 256
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config 16550_PCI_UART2_TXBUFSIZE
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int "16550 UART2 PCI Tx buffer size"
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default 256
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---help---
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16550 UART2 PCI Tx buffer size. Default: 256
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endif # 16550_PCI_UART2
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if 16550_PCI_UART3
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config 16550_PCI_UART3_VENDOR
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hex "16550 UART3 PCI vendor"
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default 16550_PCI_UART2_VENDOR
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---help---
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PCI vendor number that will be associated with UART3
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config 16550_PCI_UART3_DEVICE
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hex "16550 UART3 PCI device"
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default 16550_PCI_UART2_DEVICE
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---help---
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PCI device number that will be associated with UART3
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config 16550_PCI_UART3_PORT
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int "16550 UART3 PCI port"
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default 3
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---help---
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Port in multi-port device. Starts from 0.
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Must be set to 0 for single port devices .
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config 16550_PCI_UART3_CLOCK
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int "16550 UART3 PCI clock"
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config 16550_PCI_UART3_BAUD
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int "16550 UART3 PCI BAUD"
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default 115200
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config 16550_PCI_UART3_PARITY
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int "16550 UART3 PCI parity"
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default 0
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range 0 2
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---help---
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16550 UART3 PCI parity. 0=None, 1=Odd, 2=Even. Default: None
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config 16550_PCI_UART3_BITS
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int "16550 UART3 PCI number of bits"
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default 8
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---help---
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16550 UART3 PCI number of bits. Default: 8
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config 16550_PCI_UART3_2STOP
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int "16550 UART3 PCI two stop bits"
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default 0
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---help---
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0=1 stop bit, 1=Two stop bits. Default: 1 stop bit
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config 16550_PCI_UART3_RXBUFSIZE
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int "16550 UART3 PCI Rx buffer size"
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default 256
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---help---
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16550 UART3 PCI Rx buffer size. Default: 256
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config 16550_PCI_UART3_TXBUFSIZE
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int "16550 UART3 PCI Tx buffer size"
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default 256
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---help---
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16550 UART3 PCI Tx buffer size. Default: 256
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endif # 16550_PCI_UART3
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config 16550_PCI_CONSOLE
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bool
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depends on 16550_PCI_UART && 16550_NO_SERIAL_CONSOLE
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select SERIAL_CONSOLE
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choice
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prompt "16550 PCI Serial Console"
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default 16550_PCI_NO_SERIAL_CONSOLE
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depends on DEV_CONSOLE && 16550_PCI_UART
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config 16550_PCI_UART0_SERIAL_CONSOLE
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bool "16550 PCI UART0 serial console"
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depends on 16550_PCI_UART0
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select 16550_PCI_CONSOLE
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config 16550_PCI_UART1_SERIAL_CONSOLE
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bool "16550 PCI UART1 serial console"
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depends on 16550_PCI_UART1
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select 16550_PCI_CONSOLE
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config 16550_PCI_UART2_SERIAL_CONSOLE
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bool "16550 PCI UART2 serial console"
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depends on 16550_PCI_UART2
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select 16550_PCI_CONSOLE
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config 16550_PCI_UART3_SERIAL_CONSOLE
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bool "16550 PCI UART3 serial console"
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depends on 16550_PCI_UART3
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select 16550_PCI_CONSOLE
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config 16550_PCI_NO_SERIAL_CONSOLE
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bool "No 16550 PCI serial console"
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endchoice # 16550 Serial Console
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@ -75,6 +75,12 @@ ifeq ($(CONFIG_RAM_UART),y)
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CSRCS += uart_ram.c
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endif
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# UART PCI drivers
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ifeq ($(CONFIG_16550_PCI_UART),y)
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CSRCS += uart_pci_16550.c
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endif
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# Include serial build support
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DEPPATH += --dep-path serial
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810
drivers/serial/uart_pci_16550.c
Normal file
810
drivers/serial/uart_pci_16550.c
Normal file
@ -0,0 +1,810 @@
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/*****************************************************************************
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* drivers/serial/uart_pci_16550.c
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*
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* Licensed to the Apache Software Foundation (ASF) under one or more
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* contributor license agreements. See the NOTICE file distributed with
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* this work for additional information regarding copyright ownership. The
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* ASF licenses this file to you under the Apache License, Version 2.0 (the
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* "License"); you may not use this file except in compliance with the
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* License. You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
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* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
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* License for the specific language governing permissions and limitations
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* under the License.
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*
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*****************************************************************************/
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/* Serial driver for 16550 UART PCI */
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/*****************************************************************************
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* Included Files
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*****************************************************************************/
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#include <nuttx/config.h>
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#include <sys/types.h>
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#include <sys/param.h>
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#include <stdint.h>
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#include <stdbool.h>
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#include <unistd.h>
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#include <debug.h>
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#include <nuttx/spinlock.h>
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#include <nuttx/fs/ioctl.h>
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#include <nuttx/pci/pci.h>
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#include <nuttx/serial/uart_16550.h>
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#include <nuttx/serial/uart_pci_16550.h>
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/*****************************************************************************
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* Pre-processor Definitions
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*****************************************************************************/
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#define PCI_U16550_DEV_PATH0 "/dev/ttyS0"
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#define PCI_U16550_DEV_PATH1 "/dev/ttyS1"
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#define PCI_U16550_DEV_PATH2 "/dev/ttyS2"
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#define PCI_U16550_DEV_PATH3 "/dev/ttyS3"
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/* UART PCI console support */
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#if defined(CONFIG_16550_PCI_UART0_SERIAL_CONSOLE)
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# define CONSOLE_DEV g_pci_u16550_dev0
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#elif defined(CONFIG_16550_PCI_UART1_SERIAL_CONSOLE)
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# define CONSOLE_DEV g_pci_u16550_dev1
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#elif defined(CONFIG_16550_PCI_UART2_SERIAL_CONSOLE)
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# define CONSOLE_DEV g_pci_u16550_dev2
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#elif defined(CONFIG_16550_PCI_UART3_SERIAL_CONSOLE)
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# define CONSOLE_DEV g_pci_u16550_dev3
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#endif
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/*****************************************************************************
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* Private Types
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*****************************************************************************/
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/* Extend default PCI devie type */
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struct pci_u16550_type_s
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{
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uint8_t ports; /* Number of ports */
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uint8_t regincr; /* Address increment */
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uint8_t portincr; /* Port address increment */
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};
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/* Extend default UART 16550 strucutre */
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struct pci_u16550_priv_s
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{
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/* Common UART 16550 data must be first */
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struct u16550_s common;
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FAR struct pci_device_s *pcidev;
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uint16_t vendor;
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uint16_t device;
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uint8_t port;
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FAR const char *path;
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};
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/*****************************************************************************
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* Private Functions Definitions
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*****************************************************************************/
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static uart_datawidth_t pci_u16550_getreg_mem(FAR struct u16550_s *priv,
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unsigned int offset);
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static void pci_u16550_putreg_mem(FAR struct u16550_s *priv,
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unsigned int offset,
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uart_datawidth_t value);
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static uart_datawidth_t pci_u16550_getreg_io(FAR struct u16550_s *priv,
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unsigned int offset);
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static void pci_u16550_putreg_io(FAR struct u16550_s *priv,
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unsigned int offset,
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uart_datawidth_t value);
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static int pci_u16550_ioctl(FAR struct u16550_s *priv, int cmd,
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unsigned long arg);
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static FAR struct dma_chan_s *pci_u16550_dmachan(FAR struct u16550_s *priv,
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unsigned int ident);
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static int pci_u16550_interrupt(int irq, FAR void *context, FAR void *arg);
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static int pci_u16550_initialize(FAR struct pci_u16550_priv_s *priv,
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FAR const struct pci_u16550_type_s *type,
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uintptr_t base,
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FAR struct pci_device_s *dev,
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bool mmio);
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static int pci_u16550_register(FAR uart_dev_t *dev);
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static int pci_u16550_probe(FAR struct pci_device_s *dev);
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/*****************************************************************************
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* Private Data
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*****************************************************************************/
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#ifdef CONFIG_16550_PCI_UART_QEMU
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static const struct pci_u16550_type_s g_pci_u16550_qemu_x1 =
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{
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.ports = 1,
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.regincr = 1,
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.portincr = 0,
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};
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static const struct pci_u16550_type_s g_pci_u16550_qemu_x2 =
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{
|
||||
.ports = 2,
|
||||
.regincr = 1,
|
||||
.portincr = 8,
|
||||
};
|
||||
|
||||
static const struct pci_u16550_type_s g_pci_u16550_qemu_x4 =
|
||||
{
|
||||
.ports = 4,
|
||||
.regincr = 1,
|
||||
.portincr = 8,
|
||||
};
|
||||
#endif /* CONFIG_16550_PCI_UART_QEMU */
|
||||
|
||||
#ifdef CONFIG_16550_PCI_UART_AX99100
|
||||
static const struct pci_u16550_type_s g_pci_u16550_ax99100_x2 =
|
||||
{
|
||||
.ports = 2,
|
||||
.regincr = 1,
|
||||
.portincr = 8,
|
||||
};
|
||||
#endif /* CONFIG_16550_PCI_UART_AX99100 */
|
||||
|
||||
static const struct pci_device_id_s g_pci_u16550_id_table[] =
|
||||
{
|
||||
#ifdef CONFIG_16550_PCI_UART_QEMU
|
||||
{
|
||||
PCI_DEVICE(0x1b36, 0x0002),
|
||||
.driver_data = (uintptr_t)&g_pci_u16550_qemu_x1
|
||||
},
|
||||
{
|
||||
PCI_DEVICE(0x1b36, 0x0003),
|
||||
.driver_data = (uintptr_t)&g_pci_u16550_qemu_x2
|
||||
},
|
||||
{
|
||||
PCI_DEVICE(0x1b36, 0x0004),
|
||||
.driver_data = (uintptr_t)&g_pci_u16550_qemu_x4
|
||||
},
|
||||
#endif
|
||||
#ifdef CONFIG_16550_PCI_UART_AX99100
|
||||
{
|
||||
PCI_DEVICE(0x125b, 0x9100),
|
||||
.driver_data = (uintptr_t)&g_pci_u16550_ax99100_x2
|
||||
},
|
||||
#endif
|
||||
{ }
|
||||
};
|
||||
|
||||
static struct pci_driver_s g_pci_u16550_drv =
|
||||
{
|
||||
.id_table = g_pci_u16550_id_table,
|
||||
.probe = pci_u16550_probe,
|
||||
};
|
||||
|
||||
/* UART 16550 ops for MMIO operations */
|
||||
|
||||
static const struct u16550_ops_s g_pci_u16550_mem_ops =
|
||||
{
|
||||
.isr = pci_u16550_interrupt,
|
||||
.getreg = pci_u16550_getreg_mem,
|
||||
.putreg = pci_u16550_putreg_mem,
|
||||
.ioctl = pci_u16550_ioctl,
|
||||
.dmachan = pci_u16550_dmachan,
|
||||
};
|
||||
|
||||
/* UART 16550 ops for IO operations */
|
||||
|
||||
static const struct u16550_ops_s g_pci_u16550_io_ops =
|
||||
{
|
||||
.isr = pci_u16550_interrupt,
|
||||
.getreg = pci_u16550_getreg_io,
|
||||
.putreg = pci_u16550_putreg_io,
|
||||
.ioctl = pci_u16550_ioctl,
|
||||
.dmachan = pci_u16550_dmachan,
|
||||
};
|
||||
|
||||
/* I/O buffers */
|
||||
|
||||
#ifdef CONFIG_16550_PCI_UART0
|
||||
static char g_pci_u16550_rxbuffer0[CONFIG_16550_PCI_UART0_RXBUFSIZE];
|
||||
static char g_pci_u16550_txbuffer0[CONFIG_16550_PCI_UART0_TXBUFSIZE];
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_16550_PCI_UART1
|
||||
static char g_pci_u16550_rxbuffer1[CONFIG_16550_PCI_UART1_RXBUFSIZE];
|
||||
static char g_pci_u16550_txbuffer1[CONFIG_16550_PCI_UART1_TXBUFSIZE];
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_16550_PCI_UART2
|
||||
static char g_pci_u16550_rxbuffer2[CONFIG_16550_PCI_UART2_RXBUFSIZE];
|
||||
static char g_pci_u16550_txbuffer2[CONFIG_16550_PCI_UART2_TXBUFSIZE];
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_16550_PCI_UART3
|
||||
static char g_pci_u16550_rxbuffer3[CONFIG_16550_PCI_UART3_RXBUFSIZE];
|
||||
static char g_pci_u16550_txbuffer3[CONFIG_16550_PCI_UART3_TXBUFSIZE];
|
||||
#endif
|
||||
|
||||
/* This describes the state of the 16550 UART0 PCI port. */
|
||||
|
||||
#ifdef CONFIG_16550_PCI_UART0
|
||||
static struct pci_u16550_priv_s g_pci_u16550_priv0 =
|
||||
{
|
||||
/* UART 16550 common data */
|
||||
|
||||
.common =
|
||||
{
|
||||
.baud = CONFIG_16550_PCI_UART0_BAUD,
|
||||
.uartclk = CONFIG_16550_PCI_UART0_CLOCK,
|
||||
.parity = CONFIG_16550_PCI_UART0_PARITY,
|
||||
.bits = CONFIG_16550_PCI_UART0_BITS,
|
||||
.stopbits2 = CONFIG_16550_PCI_UART0_2STOP,
|
||||
#if defined(CONFIG_16550_PCI_UART0_IFLOWCONTROL) || \
|
||||
defined(CONFIG_16550_PCI_UART0_OFLOWCONTROL)
|
||||
.flow = true,
|
||||
#endif
|
||||
.rxtrigger = 2,
|
||||
},
|
||||
|
||||
/* PCI specific data */
|
||||
|
||||
.vendor = CONFIG_16550_PCI_UART0_VENDOR,
|
||||
.device = CONFIG_16550_PCI_UART0_DEVICE,
|
||||
.port = CONFIG_16550_PCI_UART0_PORT,
|
||||
.path = PCI_U16550_DEV_PATH0
|
||||
};
|
||||
|
||||
static uart_dev_t g_pci_u16550_dev0 =
|
||||
{
|
||||
.recv =
|
||||
{
|
||||
.size = CONFIG_16550_PCI_UART0_RXBUFSIZE,
|
||||
.buffer = g_pci_u16550_rxbuffer0,
|
||||
},
|
||||
.xmit =
|
||||
{
|
||||
.size = CONFIG_16550_PCI_UART0_TXBUFSIZE,
|
||||
.buffer = g_pci_u16550_txbuffer0,
|
||||
},
|
||||
.priv = &g_pci_u16550_priv0.common,
|
||||
#ifdef CONFIG_16550_PCI_UART0_SERIAL_CONSOLE
|
||||
.isconsole = true,
|
||||
#endif
|
||||
};
|
||||
#endif
|
||||
|
||||
/* This describes the state of the 16550 UART1 PCI port. */
|
||||
|
||||
#ifdef CONFIG_16550_PCI_UART1
|
||||
static struct pci_u16550_priv_s g_pci_u16550_priv1 =
|
||||
{
|
||||
/* UART 16550 common data */
|
||||
|
||||
.common =
|
||||
{
|
||||
.baud = CONFIG_16550_PCI_UART1_BAUD,
|
||||
.uartclk = CONFIG_16550_PCI_UART1_CLOCK,
|
||||
.parity = CONFIG_16550_PCI_UART1_PARITY,
|
||||
.bits = CONFIG_16550_PCI_UART1_BITS,
|
||||
.stopbits2 = CONFIG_16550_PCI_UART1_2STOP,
|
||||
#if defined(CONFIG_16550_PCI_UART1_IFLOWCONTROL) || \
|
||||
defined(CONFIG_16550_PCI_UART1_OFLOWCONTROL)
|
||||
.flow = true,
|
||||
#endif
|
||||
.rxtrigger = 2,
|
||||
},
|
||||
|
||||
/* PCI specific data */
|
||||
|
||||
.vendor = CONFIG_16550_PCI_UART1_VENDOR,
|
||||
.device = CONFIG_16550_PCI_UART1_DEVICE,
|
||||
.port = CONFIG_16550_PCI_UART1_PORT,
|
||||
.path = PCI_U16550_DEV_PATH1
|
||||
};
|
||||
|
||||
static uart_dev_t g_pci_u16550_dev1 =
|
||||
{
|
||||
.recv =
|
||||
{
|
||||
.size = CONFIG_16550_PCI_UART1_RXBUFSIZE,
|
||||
.buffer = g_pci_u16550_rxbuffer1,
|
||||
},
|
||||
.xmit =
|
||||
{
|
||||
.size = CONFIG_16550_PCI_UART1_TXBUFSIZE,
|
||||
.buffer = g_pci_u16550_txbuffer1,
|
||||
},
|
||||
.priv = &g_pci_u16550_priv1.common,
|
||||
#ifdef CONFIG_16550_PCI_UART1_SERIAL_CONSOLE
|
||||
.isconsole = true,
|
||||
#endif
|
||||
};
|
||||
#endif
|
||||
|
||||
/* This describes the state of the 16550 UART2 PCI port. */
|
||||
|
||||
#ifdef CONFIG_16550_PCI_UART2
|
||||
static struct pci_u16550_priv_s g_pci_u16550_priv2 =
|
||||
{
|
||||
/* UART 16550 common data */
|
||||
|
||||
.common =
|
||||
{
|
||||
.baud = CONFIG_16550_PCI_UART2_BAUD,
|
||||
.uartclk = CONFIG_16550_PCI_UART2_CLOCK,
|
||||
.parity = CONFIG_16550_PCI_UART2_PARITY,
|
||||
.bits = CONFIG_16550_PCI_UART2_BITS,
|
||||
.stopbits2 = CONFIG_16550_PCI_UART2_2STOP,
|
||||
#if defined(CONFIG_16550_PCI_UART2_IFLOWCONTROL) || \
|
||||
defined(CONFIG_16550_PCI_UART2_OFLOWCONTROL)
|
||||
.flow = true,
|
||||
#endif
|
||||
.rxtrigger = 2,
|
||||
},
|
||||
|
||||
/* PCI specific data */
|
||||
|
||||
.vendor = CONFIG_16550_PCI_UART2_VENDOR,
|
||||
.device = CONFIG_16550_PCI_UART2_DEVICE,
|
||||
.port = CONFIG_16550_PCI_UART2_PORT,
|
||||
.path = PCI_U16550_DEV_PATH2
|
||||
};
|
||||
|
||||
static uart_dev_t g_pci_u16550_dev2 =
|
||||
{
|
||||
.recv =
|
||||
{
|
||||
.size = CONFIG_16550_PCI_UART2_RXBUFSIZE,
|
||||
.buffer = g_pci_u16550_rxbuffer2,
|
||||
},
|
||||
.xmit =
|
||||
{
|
||||
.size = CONFIG_16550_PCI_UART2_TXBUFSIZE,
|
||||
.buffer = g_pci_u16550_txbuffer2,
|
||||
},
|
||||
.priv = &g_pci_u16550_priv2.common,
|
||||
#ifdef CONFIG_16550_PCI_UART2_SERIAL_CONSOLE
|
||||
.isconsole = true,
|
||||
#endif
|
||||
};
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_16550_PCI_UART3
|
||||
static struct pci_u16550_priv_s g_pci_u16550_priv3 =
|
||||
{
|
||||
/* UART 16550 common data */
|
||||
|
||||
.common =
|
||||
{
|
||||
.baud = CONFIG_16550_PCI_UART3_BAUD,
|
||||
.uartclk = CONFIG_16550_PCI_UART3_CLOCK,
|
||||
.parity = CONFIG_16550_PCI_UART3_PARITY,
|
||||
.bits = CONFIG_16550_PCI_UART3_BITS,
|
||||
.stopbits2 = CONFIG_16550_PCI_UART3_2STOP,
|
||||
#if defined(CONFIG_16550_PCI_UART3_IFLOWCONTROL) || \
|
||||
defined(CONFIG_16550_PCI_UART3_OFLOWCONTROL)
|
||||
.flow = true,
|
||||
#endif
|
||||
.rxtrigger = 2,
|
||||
},
|
||||
|
||||
/* PCI specific data */
|
||||
|
||||
.vendor = CONFIG_16550_PCI_UART3_VENDOR,
|
||||
.device = CONFIG_16550_PCI_UART3_DEVICE,
|
||||
.port = CONFIG_16550_PCI_UART3_PORT,
|
||||
.path = PCI_U16550_DEV_PATH3
|
||||
};
|
||||
|
||||
static uart_dev_t g_pci_u16550_dev3 =
|
||||
{
|
||||
.recv =
|
||||
{
|
||||
.size = CONFIG_16550_PCI_UART3_RXBUFSIZE,
|
||||
.buffer = g_pci_u16550_rxbuffer3,
|
||||
},
|
||||
.xmit =
|
||||
{
|
||||
.size = CONFIG_16550_PCI_UART3_TXBUFSIZE,
|
||||
.buffer = g_pci_u16550_txbuffer3,
|
||||
},
|
||||
.priv = &g_pci_u16550_priv3.common,
|
||||
#ifdef CONFIG_16550_PCI_UART3_SERIAL_CONSOLE
|
||||
.isconsole = true,
|
||||
#endif
|
||||
};
|
||||
#endif
|
||||
|
||||
/* PCI devices */
|
||||
|
||||
static uart_dev_t *const g_pci_u16550_dev[] =
|
||||
{
|
||||
#ifdef CONFIG_16550_PCI_UART0
|
||||
&g_pci_u16550_dev0,
|
||||
#endif
|
||||
#ifdef CONFIG_16550_PCI_UART1
|
||||
&g_pci_u16550_dev1,
|
||||
#endif
|
||||
#ifdef CONFIG_16550_PCI_UART2
|
||||
&g_pci_u16550_dev2,
|
||||
#endif
|
||||
#ifdef CONFIG_16550_PCI_UART3
|
||||
&g_pci_u16550_dev3,
|
||||
#endif
|
||||
};
|
||||
|
||||
/*****************************************************************************
|
||||
* Private Functions
|
||||
*****************************************************************************/
|
||||
|
||||
/*****************************************************************************
|
||||
* Name: pci_u16550_getreg_mem
|
||||
*****************************************************************************/
|
||||
|
||||
static uart_datawidth_t pci_u16550_getreg_mem(FAR struct u16550_s *priv,
|
||||
unsigned int offset)
|
||||
{
|
||||
uintptr_t addr = priv->uartbase + offset;
|
||||
|
||||
return *((FAR volatile uart_datawidth_t *)addr);
|
||||
}
|
||||
|
||||
/*****************************************************************************
|
||||
* Name: pci_u16550_putreg_mem
|
||||
*****************************************************************************/
|
||||
|
||||
static void pci_u16550_putreg_mem(FAR struct u16550_s *priv,
|
||||
unsigned int offset,
|
||||
uart_datawidth_t value)
|
||||
{
|
||||
uintptr_t addr = priv->uartbase + offset;
|
||||
|
||||
*((FAR volatile uart_datawidth_t *)addr) = value;
|
||||
}
|
||||
|
||||
/*****************************************************************************
|
||||
* Name: pci_u16550_getreg_io
|
||||
*****************************************************************************/
|
||||
|
||||
static uart_datawidth_t pci_u16550_getreg_io(FAR struct u16550_s *priv,
|
||||
unsigned int offset)
|
||||
{
|
||||
FAR struct pci_u16550_priv_s *p = (FAR struct pci_u16550_priv_s *)priv;
|
||||
uintptr_t addr = priv->uartbase + offset;
|
||||
uint8_t ret = 0;
|
||||
|
||||
pci_read_io_byte(p->pcidev, addr, &ret);
|
||||
return ret;
|
||||
}
|
||||
|
||||
/*****************************************************************************
|
||||
* Name: pci_u16550_putreg_io
|
||||
*****************************************************************************/
|
||||
|
||||
static void pci_u16550_putreg_io(FAR struct u16550_s *priv,
|
||||
unsigned int offset,
|
||||
uart_datawidth_t value)
|
||||
{
|
||||
FAR struct pci_u16550_priv_s *p = (FAR struct pci_u16550_priv_s *)priv;
|
||||
uintptr_t addr = priv->uartbase + offset;
|
||||
|
||||
pci_write_io_byte(p->pcidev, addr, value);
|
||||
}
|
||||
|
||||
/*****************************************************************************
|
||||
* Name: pci_u16550_ioctl
|
||||
*****************************************************************************/
|
||||
|
||||
static int pci_u16550_ioctl(FAR struct u16550_s *priv, int cmd,
|
||||
unsigned long arg)
|
||||
{
|
||||
return -ENOTTY;
|
||||
}
|
||||
|
||||
/*****************************************************************************
|
||||
* Name: pci_u16550_dmachan
|
||||
*****************************************************************************/
|
||||
|
||||
static FAR struct dma_chan_s *pci_u16550_dmachan(FAR struct u16550_s *priv,
|
||||
unsigned int ident)
|
||||
{
|
||||
return NULL;
|
||||
}
|
||||
|
||||
/*****************************************************************************
|
||||
* Name: pci_u16550_interrupt
|
||||
*
|
||||
* Description:
|
||||
* Handle PCI interrupt.
|
||||
*
|
||||
*****************************************************************************/
|
||||
|
||||
static int pci_u16550_interrupt(int irq, FAR void *context, FAR void *arg)
|
||||
{
|
||||
FAR struct uart_dev_s *dev = (FAR struct uart_dev_s *)arg;
|
||||
|
||||
DEBUGASSERT(dev != NULL);
|
||||
u16550_interrupt(0, NULL, dev);
|
||||
|
||||
return OK;
|
||||
}
|
||||
|
||||
/*****************************************************************************
|
||||
* Name: pci_u16550_initialize
|
||||
*
|
||||
* Description:
|
||||
* Initialize UART 16550 PCI device.
|
||||
*
|
||||
*****************************************************************************/
|
||||
|
||||
static int pci_u16550_initialize(FAR struct pci_u16550_priv_s *priv,
|
||||
FAR const struct pci_u16550_type_s *type,
|
||||
uintptr_t base,
|
||||
FAR struct pci_device_s *dev,
|
||||
bool mmio)
|
||||
{
|
||||
int ret = 0;
|
||||
|
||||
/* Configure UART PCI */
|
||||
|
||||
priv->common.uartbase = base;
|
||||
|
||||
if (mmio)
|
||||
{
|
||||
priv->common.ops = &g_pci_u16550_mem_ops;
|
||||
}
|
||||
else
|
||||
{
|
||||
priv->common.ops = &g_pci_u16550_io_ops;
|
||||
}
|
||||
|
||||
priv->common.regincr = type->regincr;
|
||||
priv->pcidev = dev;
|
||||
|
||||
/* Allocate and connect MSI if supported */
|
||||
|
||||
ret = pci_alloc_irq(dev, &priv->common.irq, 1);
|
||||
if (ret != 1)
|
||||
{
|
||||
pcierr("Failed to allocate MSI %d\n", ret);
|
||||
goto legacy_irq;
|
||||
}
|
||||
|
||||
ret = pci_connect_irq(dev, &priv->common.irq, 1);
|
||||
if (ret == OK)
|
||||
{
|
||||
return OK;
|
||||
}
|
||||
|
||||
pci_release_irq(dev, &priv->common.irq, 1);
|
||||
|
||||
legacy_irq:
|
||||
|
||||
/* Get legacy IRQ if MSI not supported */
|
||||
|
||||
priv->common.irq = pci_get_irq(dev);
|
||||
|
||||
/* Attach interrupts early to prevent unexpected isr fault */
|
||||
|
||||
ret = irq_attach(priv->common.irq, priv->common.ops->isr, dev);
|
||||
if (ret != OK)
|
||||
{
|
||||
pcierr("Failed to attach irq %d\n", ret);
|
||||
}
|
||||
|
||||
return OK;
|
||||
}
|
||||
|
||||
/*****************************************************************************
|
||||
* Name: pci_u16550_register
|
||||
*
|
||||
* Description:
|
||||
* Register UART 16550 PCI device.
|
||||
*
|
||||
*****************************************************************************/
|
||||
|
||||
static int pci_u16550_register(FAR uart_dev_t *dev)
|
||||
{
|
||||
FAR struct pci_u16550_priv_s *priv =
|
||||
(FAR struct pci_u16550_priv_s *)dev->priv;
|
||||
int ret = OK;
|
||||
|
||||
/* Bind with 16550 common driver */
|
||||
|
||||
ret = u16550_bind(dev);
|
||||
if (ret < 0)
|
||||
{
|
||||
/* No associated device found */
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
DEBUGASSERT(dev->ops);
|
||||
|
||||
/* Register driver */
|
||||
|
||||
pciinfo("Register %s", priv->path);
|
||||
|
||||
ret = uart_register(priv->path, dev);
|
||||
if (ret < 0)
|
||||
{
|
||||
return ret;
|
||||
}
|
||||
|
||||
#ifdef CONFIG_16550_PCI_CONSOLE
|
||||
/* Register console */
|
||||
|
||||
if (dev->isconsole)
|
||||
{
|
||||
ret = uart_register("/dev/console", dev);
|
||||
}
|
||||
#endif
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
/*****************************************************************************
|
||||
* Name: pci_u16550_probe
|
||||
*
|
||||
* Description:
|
||||
* Initialize device.
|
||||
*
|
||||
*****************************************************************************/
|
||||
|
||||
static int pci_u16550_probe(FAR struct pci_device_s *dev)
|
||||
{
|
||||
FAR const struct pci_u16550_type_s *type = NULL;
|
||||
FAR uart_dev_t *udev = NULL;
|
||||
FAR struct pci_u16550_priv_s *priv = NULL;
|
||||
uintptr_t base = 0;
|
||||
size_t i;
|
||||
uint8_t port;
|
||||
bool mmio = false;
|
||||
int ret;
|
||||
|
||||
/* Get type data associated with this PCI device card */
|
||||
|
||||
type = (FAR const struct pci_u16550_type_s *)dev->id->driver_data;
|
||||
|
||||
/* Not found private data */
|
||||
|
||||
if (type == NULL)
|
||||
{
|
||||
return -ENODEV;
|
||||
}
|
||||
|
||||
pci_set_master(dev);
|
||||
pciinfo("Enabled bus mastering\n");
|
||||
pci_enable_device(dev);
|
||||
pciinfo("Enabled memory resources\n");
|
||||
|
||||
/* Hardcode BAR 0 for now */
|
||||
|
||||
if (pci_resource_flags(dev, 0) == PCI_RESOURCE_IO)
|
||||
{
|
||||
base = pci_resource_start(dev, 0);
|
||||
}
|
||||
else
|
||||
{
|
||||
/* If the BAR is MMIO then it must be mapped */
|
||||
|
||||
base = (uintptr_t)pci_map_bar(dev, 0);
|
||||
mmio = true;
|
||||
}
|
||||
|
||||
for (port = 0; port < type->ports; port++)
|
||||
{
|
||||
/* Get port address */
|
||||
|
||||
base += type->portincr * port;
|
||||
|
||||
/* Take the instance that matches the configuration */
|
||||
|
||||
udev = NULL;
|
||||
for (i = 0; i < nitems(g_pci_u16550_dev); i++)
|
||||
{
|
||||
udev = g_pci_u16550_dev[i];
|
||||
priv = (FAR struct pci_u16550_priv_s *)udev->priv;
|
||||
|
||||
if (priv->vendor == dev->vendor &&
|
||||
priv->device == dev->device &&
|
||||
priv->port == port)
|
||||
{
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
/* Not found */
|
||||
|
||||
if (udev == NULL)
|
||||
{
|
||||
return -ENODEV;
|
||||
}
|
||||
|
||||
/* Device already registered */
|
||||
|
||||
if (udev->ops != NULL)
|
||||
{
|
||||
return -EBUSY;
|
||||
}
|
||||
|
||||
/* Initialize device */
|
||||
|
||||
ret = pci_u16550_initialize(priv, type, base, dev, mmio);
|
||||
if (ret < 0)
|
||||
{
|
||||
return ret;
|
||||
}
|
||||
|
||||
/* Register UART device */
|
||||
|
||||
ret = pci_u16550_register(udev);
|
||||
if (ret < 0)
|
||||
{
|
||||
return ret;
|
||||
}
|
||||
}
|
||||
|
||||
return OK;
|
||||
}
|
||||
|
||||
/*****************************************************************************
|
||||
* Name: up_putc
|
||||
*
|
||||
* Description:
|
||||
* Provide priority, low-level access to support OS debug writes.
|
||||
*
|
||||
*****************************************************************************/
|
||||
|
||||
#ifdef CONFIG_16550_PCI_CONSOLE
|
||||
int up_putc(int ch)
|
||||
{
|
||||
irqstate_t flags;
|
||||
|
||||
/* Console not initialized yet */
|
||||
|
||||
if (CONSOLE_DEV.ops == NULL)
|
||||
{
|
||||
return ch;
|
||||
}
|
||||
|
||||
/* All interrupts must be disabled to prevent re-entrancy and to prevent
|
||||
* interrupts from firing in the serial driver code.
|
||||
*/
|
||||
|
||||
flags = spin_lock_irqsave(NULL);
|
||||
|
||||
/* Check for LF */
|
||||
|
||||
if (ch == '\n')
|
||||
{
|
||||
/* Add CR */
|
||||
|
||||
u16550_putc(CONSOLE_DEV.priv, '\r');
|
||||
}
|
||||
|
||||
u16550_putc(CONSOLE_DEV.priv, ch);
|
||||
spin_unlock_irqrestore(NULL, flags);
|
||||
|
||||
return ch;
|
||||
}
|
||||
#endif
|
||||
|
||||
/*****************************************************************************
|
||||
* Public Functions
|
||||
*****************************************************************************/
|
||||
|
||||
/*****************************************************************************
|
||||
* Name: pci_u16550_init
|
||||
*
|
||||
* Description:
|
||||
* Register a pci driver
|
||||
*
|
||||
*****************************************************************************/
|
||||
|
||||
int pci_u16550_init(void)
|
||||
{
|
||||
return pci_register_driver(&g_pci_u16550_drv);
|
||||
}
|
||||
51
include/nuttx/serial/uart_pci_16550.h
Normal file
51
include/nuttx/serial/uart_pci_16550.h
Normal file
@ -0,0 +1,51 @@
|
||||
/****************************************************************************
|
||||
* include/nuttx/serial/uart_pci_16550.h
|
||||
*
|
||||
* Licensed to the Apache Software Foundation (ASF) under one or more
|
||||
* contributor license agreements. See the NOTICE file distributed with
|
||||
* this work for additional information regarding copyright ownership. The
|
||||
* ASF licenses this file to you under the Apache License, Version 2.0 (the
|
||||
* "License"); you may not use this file except in compliance with the
|
||||
* License. You may obtain a copy of the License at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
|
||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
|
||||
* License for the specific language governing permissions and limitations
|
||||
* under the License.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
#ifndef __INCLUDE_NUTTX_SERIAL_UART_PCI_16550_H
|
||||
#define __INCLUDE_NUTTX_SERIAL_UART_PCI_16550_H
|
||||
|
||||
/****************************************************************************
|
||||
* Included Files
|
||||
****************************************************************************/
|
||||
|
||||
#include <nuttx/config.h>
|
||||
|
||||
/****************************************************************************
|
||||
* Public Function Prototypes
|
||||
****************************************************************************/
|
||||
|
||||
#ifdef __cplusplus
|
||||
#define EXTERN extern "C"
|
||||
extern "C"
|
||||
{
|
||||
#else
|
||||
#define EXTERN extern
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_16550_PCI_UART
|
||||
int pci_u16550_init(void);
|
||||
#endif
|
||||
|
||||
#undef EXTERN
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __INCLUDE_NUTTX_SERIAL_UART_PCI_16550_H */
|
||||
Loading…
Reference in New Issue
Block a user