From 6b517ed017c763853efe4a04b69cf7fbe5e5e4a3 Mon Sep 17 00:00:00 2001 From: Gregory Nutt Date: Thu, 16 Jun 2016 06:28:04 -0600 Subject: [PATCH 01/75] Centralize definitions associated with CONFIG_DEBUG_WATCHDOG --- Kconfig | 37 ++++- arch/arm/src/sam34/sam_wdt.c | 14 -- arch/arm/src/sama5/sam_wdt.c | 14 -- arch/arm/src/samv7/sam_rswdt.c | 14 -- arch/arm/src/samv7/sam_wdt.c | 14 -- arch/arm/src/stm32/stm32_iwdg.c | 14 -- arch/arm/src/stm32/stm32_wwdg.c | 14 -- configs/sam4s-xplained-pro/src/sam_wdt.c | 54 ++------ drivers/timers/watchdog.c | 18 --- include/debug.h | 168 +++++++++++++++-------- 10 files changed, 156 insertions(+), 205 deletions(-) diff --git a/Kconfig b/Kconfig index 3e781bcc57..74de7c7db3 100644 --- a/Kconfig +++ b/Kconfig @@ -405,10 +405,6 @@ config DEBUG_FEATURES Note that enabling this option by itself does not produce debug output. Debug output must also be selected on a subsystem-by-subsystem basis. -config ARCH_HAVE_HEAPCHECK - bool - default n - if DEBUG_FEATURES comment "Debug SYSLOG Output Controls" @@ -1321,14 +1317,39 @@ config DEBUG_USB_INFO endif # DEBUG_USB config DEBUG_WATCHDOG - bool "Watchdog Timer Debug Output" + bool "Watchdog Timer Debug Features" default n depends on WATCHDOG ---help--- - Enable watchdog timer debug SYSLOG output (disabled by default). + Enable watchdog timer debug features. + Support for this debug option is architecture-specific and may not be available for some MCUs. +if DEBUG_WATCHDOG + +config DEBUG_WATCHDOG_ERROR + bool "Watchdog Timer Error Output" + default n + depends on DEBUG_ERROR + ---help--- + Enable watchdog time error output to SYSLOG. + +config DEBUG_WATCHDOG_WARN + bool "Watchdog Timer Warnings Output" + default n + depends on DEBUG_WARN + ---help--- + Enable watchdog time warning output to SYSLOG. + +config DEBUG_WATCHDOG_INFO + bool "Watchdog Timer Informational Output" + default n + depends on DEBUG_INFO + ---help--- + Enable watchdog time informational output to SYSLOG. + +endif # DEBUG_WATCHDOG endif # DEBUG_FEATURES config ARCH_HAVE_STACKCHECK @@ -1346,6 +1367,10 @@ config STACK_COLORATION Only supported by a few architectures. +config ARCH_HAVE_HEAPCHECK + bool + default n + config HEAP_COLORATION bool "Heap coloration" default n diff --git a/arch/arm/src/sam34/sam_wdt.c b/arch/arm/src/sam34/sam_wdt.c index 8fc5abf70c..d54297f5ab 100644 --- a/arch/arm/src/sam34/sam_wdt.c +++ b/arch/arm/src/sam34/sam_wdt.c @@ -81,20 +81,6 @@ # define CONFIG_SAM34_WDT_DEFTIMOUT WDT_MAXTIMEOUT #endif -/* Debug ********************************************************************/ -/* Non-standard debug that may be enabled just for testing the watchdog - * driver. NOTE: that only llerr types are used so that the output is - * immediately available. - */ - -#ifdef CONFIG_DEBUG_WATCHDOG -# define wderr llerr -# define wdinfo llinfo -#else -# define wderr(x...) -# define wdinfo(x...) -#endif - /**************************************************************************** * Private Types ****************************************************************************/ diff --git a/arch/arm/src/sama5/sam_wdt.c b/arch/arm/src/sama5/sam_wdt.c index 60b079df58..be77357e97 100644 --- a/arch/arm/src/sama5/sam_wdt.c +++ b/arch/arm/src/sama5/sam_wdt.c @@ -80,20 +80,6 @@ #define WDT_MINTIMEOUT ((1000 + WDT_FREQUENCY - 1) / WDT_FREQUENCY) #define WDT_MAXTIMEOUT ((4096 * 1000) / WDT_FREQUENCY) -/* Debug ********************************************************************/ -/* Non-standard debug that may be enabled just for testing the watchdog - * driver. NOTE: that only llerr types are used so that the output is - * immediately available. - */ - -#ifdef CONFIG_DEBUG_WATCHDOG -# define wderr llerr -# define wdinfo llinfo -#else -# define wderr(x...) -# define wdinfo(x...) -#endif - /**************************************************************************** * Private Types ****************************************************************************/ diff --git a/arch/arm/src/samv7/sam_rswdt.c b/arch/arm/src/samv7/sam_rswdt.c index a176d22d9c..a097a7056f 100644 --- a/arch/arm/src/samv7/sam_rswdt.c +++ b/arch/arm/src/samv7/sam_rswdt.c @@ -80,20 +80,6 @@ #define RSWDT_MINTIMEOUT ((1000 + RSWDT_FREQUENCY - 1) / RSWDT_FREQUENCY) #define RSWDT_MAXTIMEOUT ((4096 * 1000) / RSWDT_FREQUENCY) -/* Debug ********************************************************************/ -/* Non-standard debug that may be enabled just for testing the watchdog - * driver. NOTE: that only llerr types are used so that the output is - * immediately available. - */ - -#ifdef CONFIG_DEBUG_WATCHDOG -# define wderr llerr -# define wdinfo llinfo -#else -# define wderr(x...) -# define wdinfo(x...) -#endif - /**************************************************************************** * Private Types ****************************************************************************/ diff --git a/arch/arm/src/samv7/sam_wdt.c b/arch/arm/src/samv7/sam_wdt.c index e55405785c..1c2d81cd9b 100644 --- a/arch/arm/src/samv7/sam_wdt.c +++ b/arch/arm/src/samv7/sam_wdt.c @@ -80,20 +80,6 @@ #define WDT_MINTIMEOUT ((1000 + WDT_FREQUENCY - 1) / WDT_FREQUENCY) #define WDT_MAXTIMEOUT ((4096 * 1000) / WDT_FREQUENCY) -/* Debug ********************************************************************/ -/* Non-standard debug that may be enabled just for testing the watchdog - * driver. NOTE: that only llerr types are used so that the output is - * immediately available. - */ - -#ifdef CONFIG_DEBUG_WATCHDOG -# define wderr llerr -# define wdinfo llinfo -#else -# define wderr(x...) -# define wdinfo(x...) -#endif - /**************************************************************************** * Private Types ****************************************************************************/ diff --git a/arch/arm/src/stm32/stm32_iwdg.c b/arch/arm/src/stm32/stm32_iwdg.c index cc38922ff5..ab6b052714 100644 --- a/arch/arm/src/stm32/stm32_iwdg.c +++ b/arch/arm/src/stm32/stm32_iwdg.c @@ -105,20 +105,6 @@ # error "Both CONFIG_STM32_IWDG_ONETIMESETUP and CONFIG_STM32_IWDG_DEFERREDSETUP are defined" #endif -/* Debug ********************************************************************/ -/* Non-standard debug that may be enabled just for testing the watchdog - * driver. NOTE: that only llerr types are used so that the output is - * immediately available. - */ - -#ifdef CONFIG_DEBUG_WATCHDOG -# define wderr llerr -# define wdinfo llinfo -#else -# define wderr(x...) -# define wdinfo(x...) -#endif - /**************************************************************************** * Private Types ****************************************************************************/ diff --git a/arch/arm/src/stm32/stm32_wwdg.c b/arch/arm/src/stm32/stm32_wwdg.c index 28a1bd8201..116d8d56ac 100644 --- a/arch/arm/src/stm32/stm32_wwdg.c +++ b/arch/arm/src/stm32/stm32_wwdg.c @@ -81,20 +81,6 @@ # define CONFIG_STM32_WWDG_DEFTIMOUT WWDG_MAXTIMEOUT #endif -/* Debug ********************************************************************/ -/* Non-standard debug that may be enabled just for testing the watchdog - * driver. NOTE: that only llerr types are used so that the output is - * immediately available. - */ - -#ifdef CONFIG_DEBUG_WATCHDOG -# define wderr llerr -# define wdinfo llinfo -#else -# define wderr(x...) -# define wdinfo(x...) -#endif - /**************************************************************************** * Private Types ****************************************************************************/ diff --git a/configs/sam4s-xplained-pro/src/sam_wdt.c b/configs/sam4s-xplained-pro/src/sam_wdt.c index 5ad2a36255..4223671f39 100644 --- a/configs/sam4s-xplained-pro/src/sam_wdt.c +++ b/configs/sam4s-xplained-pro/src/sam_wdt.c @@ -82,34 +82,6 @@ # error "WDT_THREAD_INTERVAL must be greater than or equal to WDT_MINTIME" #endif -/* Debug ***************************************************************************/ -/* Non-standard debug that may be enabled just for testing the watchdog timer */ - -#ifndef CONFIG_DEBUG_FEATURES -# undef CONFIG_DEBUG_WATCHDOG -#endif - -#ifdef CONFIG_DEBUG_WATCHDOG -# define wdgerr err -# define wdgllerr llerr -# ifdef CONFIG_DEBUG_INFO -# define wdginfo info -# define wdgllinfo llinfo -# else -# define wdginfo(x...) -# define wdgllinfo(x...) -# endif -#else -# define wdgerr(x...) -# define wdgllerr(x...) -# define wdginfo(x...) -# define wdgllinfo(x...) -#endif - -/************************************************************************************ - * Private Functions - ************************************************************************************/ - /************************************************************************************ * Public Functions ************************************************************************************/ @@ -124,21 +96,21 @@ static int wdog_daemon(int argc, char *argv[]) /* Open the watchdog device for reading */ - wdginfo("Opening.\n"); + wdinfo("Opening.\n"); fd = open(CONFIG_WATCHDOG_DEVPATH, O_RDONLY); if (fd < 0) { - wdgerr("ERROR: open %s failed: %d\n", CONFIG_WATCHDOG_DEVPATH, errno); + wderr("ERROR: open %s failed: %d\n", CONFIG_WATCHDOG_DEVPATH, errno); goto errout; } /* Start the watchdog timer. */ - wdginfo("Starting.\n"); + wdinfo("Starting.\n"); ret = ioctl(fd, WDIOC_START, 0); if (ret < 0) { - wdgerr("ERROR: ioctl(WDIOC_START) failed: %d\n", errno); + wderr("ERROR: ioctl(WDIOC_START) failed: %d\n", errno); goto errout_with_dev; } @@ -147,11 +119,11 @@ static int wdog_daemon(int argc, char *argv[]) { usleep((CONFIG_WDT_THREAD_INTERVAL)*1000); - wdginfo("ping\n"); + wdinfo("ping\n"); ret = ioctl(fd, WDIOC_KEEPALIVE, 0); if (ret < 0) { - wdgerr("ERROR: ioctl(WDIOC_KEEPALIVE) failed: %d\n", errno); + wderr("ERROR: ioctl(WDIOC_KEEPALIVE) failed: %d\n", errno); goto errout_with_dev; } } @@ -181,36 +153,36 @@ int sam_watchdog_initialize(void) /* Initialize tha register the watchdog timer device */ - wdginfo("Initializing Watchdog driver...\n"); + wdinfo("Initializing Watchdog driver...\n"); sam_wdtinitialize(CONFIG_WATCHDOG_DEVPATH); /* Open the watchdog device */ - wdginfo("Opening.\n"); + wdinfo("Opening.\n"); fd = open(CONFIG_WATCHDOG_DEVPATH, O_RDONLY); if (fd < 0) { - wdgerr("ERROR: open %s failed: %d\n", CONFIG_WATCHDOG_DEVPATH, errno); + wderr("ERROR: open %s failed: %d\n", CONFIG_WATCHDOG_DEVPATH, errno); goto errout; } /* Set the watchdog timeout */ - wdginfo("Timeout = %d.\n", CONFIG_WDT_TIMEOUT); + wdinfo("Timeout = %d.\n", CONFIG_WDT_TIMEOUT); ret = ioctl(fd, WDIOC_SETTIMEOUT, (unsigned long)CONFIG_WDT_TIMEOUT); if (ret < 0) { - wdgerr("ERROR: ioctl(WDIOC_SETTIMEOUT) failed: %d\n", errno); + wderr("ERROR: ioctl(WDIOC_SETTIMEOUT) failed: %d\n", errno); goto errout_with_dev; } /* Set the watchdog minimum time */ - wdginfo("MinTime = %d.\n", CONFIG_WDT_MINTIME); + wdinfo("MinTime = %d.\n", CONFIG_WDT_MINTIME); ret = ioctl(fd, WDIOC_MINTIME, (unsigned long)CONFIG_WDT_MINTIME); if (ret < 0) { - wdgerr("ERROR: ioctl(WDIOC_MINTIME) failed: %d\n", errno); + wderr("ERROR: ioctl(WDIOC_MINTIME) failed: %d\n", errno); goto errout_with_dev; } diff --git a/drivers/timers/watchdog.c b/drivers/timers/watchdog.c index 13b23efd51..e9320a9612 100644 --- a/drivers/timers/watchdog.c +++ b/drivers/timers/watchdog.c @@ -56,24 +56,6 @@ #ifdef CONFIG_WATCHDOG -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ -/* Debug ********************************************************************/ -/* Non-standard debug that may be enabled just for testing the watchdog driver */ - -#ifdef CONFIG_DEBUG_WATCHDOG -# define wderr err -# define wdinfo info -# define wdllerr llerr -# define wdllinfo llinfo -#else -# define wderr(x...) -# define wdinfo(x...) -# define wdllerr(x...) -# define wdllinfo(x...) -#endif - /**************************************************************************** * Private Type Definitions ****************************************************************************/ diff --git a/include/debug.h b/include/debug.h index c644cb48bc..e6c835e552 100644 --- a/include/debug.h +++ b/include/debug.h @@ -285,30 +285,6 @@ # define nllinfo(x...) #endif -#ifdef CONFIG_DEBUG_USB_ERROR -# define uerr(format, ...) err(format, ##__VA_ARGS__) -# define ullerr(format, ...) llerr(format, ##__VA_ARGS__) -#else -# define uerr(x...) -# define ullerr(x...) -#endif - -#ifdef CONFIG_DEBUG_USB_WARN -# define uwarn(format, ...) warn(format, ##__VA_ARGS__) -# define ullwarn(format, ...) llwarn(format, ##__VA_ARGS__) -#else -# define uwarn(x...) -# define ullwarn(x...) -#endif - -#ifdef CONFIG_DEBUG_USB_INFO -# define uinfo(format, ...) info(format, ##__VA_ARGS__) -# define ullinfo(format, ...) llinfo(format, ##__VA_ARGS__) -#else -# define uinfo(x...) -# define ullinfo(x...) -#endif - #ifdef CONFIG_DEBUG_FS_ERROR # define ferr(format, ...) err(format, ##__VA_ARGS__) # define fllerr(format, ...) llerr(format, ##__VA_ARGS__) @@ -765,6 +741,54 @@ # define spillinfo(x...) #endif +#ifdef CONFIG_DEBUG_USB_ERROR +# define uerr(format, ...) err(format, ##__VA_ARGS__) +# define ullerr(format, ...) llerr(format, ##__VA_ARGS__) +#else +# define uerr(x...) +# define ullerr(x...) +#endif + +#ifdef CONFIG_DEBUG_USB_WARN +# define uwarn(format, ...) warn(format, ##__VA_ARGS__) +# define ullwarn(format, ...) llwarn(format, ##__VA_ARGS__) +#else +# define uwarn(x...) +# define ullwarn(x...) +#endif + +#ifdef CONFIG_DEBUG_USB_INFO +# define uinfo(format, ...) info(format, ##__VA_ARGS__) +# define ullinfo(format, ...) llinfo(format, ##__VA_ARGS__) +#else +# define uinfo(x...) +# define ullinfo(x...) +#endif + +#ifdef CONFIG_DEBUG_WATCHDOG_ERROR +# define wderr(format, ...) err(format, ##__VA_ARGS__) +# define wdllerr(format, ...) llerr(format, ##__VA_ARGS__) +#else +# define wderr(x...) +# define wdllerr(x...) +#endif + +#ifdef CONFIG_DEBUG_WATCHDOG_WARN +# define wdwarn(format, ...) warn(format, ##__VA_ARGS__) +# define wdllwarn(format, ...) llwarn(format, ##__VA_ARGS__) +#else +# define wdwarn(x...) +# define wdllwarn(x...) +#endif + +#ifdef CONFIG_DEBUG_WATCHDOG_INFO +# define wdinfo(format, ...) info(format, ##__VA_ARGS__) +# define wdllinfo(format, ...) llinfo(format, ##__VA_ARGS__) +#else +# define wdinfo(x...) +# define wdllinfo(x...) +#endif + #else /* CONFIG_CPP_HAVE_VARARGS */ /* Variadic macros NOT supported */ @@ -898,30 +922,6 @@ # define nllinfo (void) #endif -#ifdef CONFIG_DEBUG_USB_ERROR -# define uerr err -# define ullerr llerr -#else -# define uerr (void) -# define ullerr (void) -#endif - -#ifdef CONFIG_DEBUG_USB_WARN -# define uwarn warn -# define ullwarn llwarn -#else -# define uwarn (void) -# define ullwarn (void) -#endif - -#ifdef CONFIG_DEBUG_USB_INFO -# define uinfo info -# define ullinfo llinfo -#else -# define uinfo (void) -# define ullinfo (void) -#endif - #ifdef CONFIG_DEBUG_FS_ERROR # define ferr err # define fllerr llerr @@ -1378,6 +1378,54 @@ # define spillinfo (void) #endif +#ifdef CONFIG_DEBUG_USB_ERROR +# define uerr err +# define ullerr llerr +#else +# define uerr (void) +# define ullerr (void) +#endif + +#ifdef CONFIG_DEBUG_USB_WARN +# define uwarn warn +# define ullwarn llwarn +#else +# define uwarn (void) +# define ullwarn (void) +#endif + +#ifdef CONFIG_DEBUG_USB_INFO +# define uinfo info +# define ullinfo llinfo +#else +# define uinfo (void) +# define ullinfo (void) +#endif + +#ifdef CONFIG_DEBUG_WATCHDOG_ERROR +# define wderr err +# define wdllerr llerr +#else +# define wderr (void) +# define wdllerr (void) +#endif + +#ifdef CONFIG_DEBUG_WATCHDOG_WARN +# define wdwarn warn +# define wdllwarn llwarn +#else +# define wdwarn (void) +# define wdllwarn (void) +#endif + +#ifdef CONFIG_DEBUG_WATCHDOG_INFO +# define wdinfo info +# define wdllinfo llinfo +#else +# define wdinfo (void) +# define wdllinfo (void) +#endif + #endif /* CONFIG_CPP_HAVE_VARARGS */ /* Buffer dumping macros do not depend on varargs */ @@ -1428,14 +1476,6 @@ # define ninfodumpbuffer(m,b,n) #endif -#ifdef CONFIG_DEBUG_USB -# define uerrdumpbuffer(m,b,n) errdumpbuffer(m,b,n) -# define uinfodumpbuffer(m,b,n) infodumpbuffer(m,b,n) -#else -# define uerrdumpbuffer(m,b,n) -# define uinfodumpbuffer(m,b,n) -#endif - #ifdef CONFIG_DEBUG_FS # define ferrdumpbuffer(m,b,n) errdumpbuffer(m,b,n) # define finfodumpbuffer(m,b,n) infodumpbuffer(m,b,n) @@ -1572,6 +1612,22 @@ # define sninfodumpbuffer(m,b,n) #endif +#ifdef CONFIG_DEBUG_USB +# define uerrdumpbuffer(m,b,n) errdumpbuffer(m,b,n) +# define uinfodumpbuffer(m,b,n) infodumpbuffer(m,b,n) +#else +# define uerrdumpbuffer(m,b,n) +# define uinfodumpbuffer(m,b,n) +#endif + +#ifdef CONFIG_DEBUG_WATCHDOG +# define wderrdumpbuffer(m,b,n) errdumpbuffer(m,b,n) +# define wdinfodumpbuffer(m,b,n) infodumpbuffer(m,b,n) +#else +# define wderrdumpbuffer(m,b,n) +# define wdinfodumpbuffer(m,b,n) +#endif + /**************************************************************************** * Public Type Declarations ****************************************************************************/ From 37b9742189a974e188ee96bdbb798f9d2f68a1e9 Mon Sep 17 00:00:00 2001 From: Gregory Nutt Date: Thu, 16 Jun 2016 07:16:25 -0600 Subject: [PATCH 02/75] Centralize definitions associated with CONFIG_DEBUG_TIMER --- Kconfig | 30 +++++- arch/arm/src/efm32/efm32_timer.c | 103 +++++++------------- arch/arm/src/lpc11xx/lpc11_timer.c | 14 +-- arch/arm/src/lpc17xx/lpc17_timer.c | 14 +-- arch/arm/src/sam34/sam4cm_freerun.c | 20 ++-- arch/arm/src/sam34/sam4cm_oneshot.c | 32 +++--- arch/arm/src/sam34/sam4cm_tc.c | 28 +++--- arch/arm/src/sam34/sam4cm_tc.h | 17 +--- arch/arm/src/sam34/sam4cm_tickless.c | 8 +- arch/arm/src/sam34/sam_tc.c | 48 +++------ arch/arm/src/sama5/sam_freerun.c | 20 ++-- arch/arm/src/sama5/sam_oneshot.c | 32 +++--- arch/arm/src/sama5/sam_tc.c | 28 +++--- arch/arm/src/sama5/sam_tc.h | 17 +--- arch/arm/src/sama5/sam_tickless.c | 8 +- arch/arm/src/samv7/sam_freerun.c | 20 ++-- arch/arm/src/samv7/sam_oneshot.c | 32 +++--- arch/arm/src/samv7/sam_tc.c | 30 +++--- arch/arm/src/samv7/sam_tc.h | 17 +--- arch/arm/src/samv7/sam_tickless.c | 6 +- arch/arm/src/tiva/Kconfig | 6 +- arch/arm/src/tiva/tiva_timer.h | 14 --- arch/arm/src/tiva/tiva_timerlib.c | 62 ++++++------ arch/arm/src/tiva/tiva_timerlow32.c | 38 ++++---- configs/dk-tm4c129x/src/tm4c_timer.c | 4 +- configs/sam4s-xplained-pro/src/sam_tc.c | 74 +++++--------- configs/tm4c1294-launchpad/src/tm4c_timer.c | 4 +- drivers/timers/timer.c | 18 ---- include/debug.h | 64 ++++++++++++ 29 files changed, 368 insertions(+), 440 deletions(-) diff --git a/Kconfig b/Kconfig index 74de7c7db3..65a55a285d 100644 --- a/Kconfig +++ b/Kconfig @@ -1276,14 +1276,40 @@ config DEBUG_SPI_INFO endif # DEBUG_SPI config DEBUG_TIMER - bool "Timer Debug Output" + bool "Timer Debug Features" default n depends on TIMER ---help--- - Enable timer debug SYSLOG output (disabled by default). + Enable timer debug features. + Support for this debug option is architecture-specific and may not be available for some MCUs. +if DEBUG_TIMER + +config DEBUG_TIMER_ERROR + bool "Timer Error Output" + default n + depends on DEBUG_ERROR + ---help--- + Enable timer error output to SYSLOG. + +config DEBUG_TIMER_WARN + bool "Timer Warnings Output" + default n + depends on DEBUG_WARN + ---help--- + Enable timer warning output to SYSLOG. + +config DEBUG_TIMER_INFO + bool "Timer Informational Output" + default n + depends on DEBUG_INFO + ---help--- + Enable timer informational output to SYSLOG. + +endif # DEBUG_TIMER + config DEBUG_USB bool "USB Debug Features" default n diff --git a/arch/arm/src/efm32/efm32_timer.c b/arch/arm/src/efm32/efm32_timer.c index a1350a9154..6264c3a378 100644 --- a/arch/arm/src/efm32/efm32_timer.c +++ b/arch/arm/src/efm32/efm32_timer.c @@ -55,50 +55,18 @@ #include "efm32_config.h" #include "efm32_gpio.h" - /**************************************************************************** * Pre-processor Definitions ****************************************************************************/ /* Debug ********************************************************************/ -/* Non-standard debug that may be enabled just for testing TIMER */ -#ifndef CONFIG_DEBUG_FEATURES -# undef CONFIG_DEBUG_TIMER -#endif - -#ifdef CONFIG_DEBUG_TIMER -# define efm32_timererr err -# define efm32_timerllerr llerr -# ifdef CONFIG_DEBUG_INFO -# define efm32_timerinfo info -# define efm32_timerllinfo llinfo -# define efm32_timer_dumpgpio(p,m) efm32_dumpgpio(p,m) -# else -# define efm32_timerllerr(x...) -# define efm32_timerllinfo(x...) -# define efm32_timer_dumpgpio(p,m) -# endif +#ifdef CONFIG_DEBUG_TIMER_INFO +# define efm32_timer_dumpgpio(p,m) efm32_dumpgpio(p,m) #else -# define efm32_timererr(x...) -# define efm32_timerllerr(x...) -# define efm32_timerinfo(x...) -# define efm32_timerllinfo(x...) # define efm32_timer_dumpgpio(p,m) #endif -/**************************************************************************** - * Private Types - ****************************************************************************/ - -/**************************************************************************** - * Static Function Prototypes - ****************************************************************************/ - -/**************************************************************************** - * Private Data - ****************************************************************************/ - /**************************************************************************** * Private Functions ****************************************************************************/ @@ -119,48 +87,43 @@ void efm32_timer_dumpregs(uintptr_t base, FAR const char *msg) { +#ifdef CONFIG_DEBUG_TIMER_INFO int i; - efm32_timerinfo("%s:\n", msg); - efm32_timerinfo(" CTRL: %04x STATUS: %04x IEN: %04x IF: %04x\n", - getreg32(base + EFM32_TIMER_CTRL_OFFSET ), - getreg32(base + EFM32_TIMER_STATUS_OFFSET ), - getreg32(base + EFM32_TIMER_IEN_OFFSET ), - getreg32(base + EFM32_TIMER_IF_OFFSET ) - ); - efm32_timerinfo(" TOP: %04x TOPB: %04x CNT: %04x ROUTE: %04x\n", - getreg32(base + EFM32_TIMER_TOP_OFFSET ), - getreg32(base + EFM32_TIMER_TOPB_OFFSET ), - getreg32(base + EFM32_TIMER_CNT_OFFSET ), - getreg32(base + EFM32_TIMER_ROUTE_OFFSET ) - ); + tmrinfo("%s:\n", msg); + tmrinfo(" CTRL: %04x STATUS: %04x IEN: %04x IF: %04x\n", + getreg32(base + EFM32_TIMER_CTRL_OFFSET ), + getreg32(base + EFM32_TIMER_STATUS_OFFSET ), + getreg32(base + EFM32_TIMER_IEN_OFFSET ), + getreg32(base + EFM32_TIMER_IF_OFFSET )); + tmrinfo(" TOP: %04x TOPB: %04x CNT: %04x ROUTE: %04x\n", + getreg32(base + EFM32_TIMER_TOP_OFFSET ), + getreg32(base + EFM32_TIMER_TOPB_OFFSET ), + getreg32(base + EFM32_TIMER_CNT_OFFSET ), + getreg32(base + EFM32_TIMER_ROUTE_OFFSET )); for (i = 0; i < EFM32_TIMER_NCC; i++) { -#if defined(CONFIG_DEBUG_TIMER) && defined(CONFIG_DEBUG_INFO) uintptr_t base_cc = base + EFM32_TIMER_CC_OFFSET(i); -#endif - efm32_timerinfo("CC%d => CTRL: %04x CCV: %04x CCVP: %04x CCVB: %04x\n", - i - getreg32(base_cc + EFM32_TIMER_CC_CTRL_OFFSET ), - getreg32(base_cc + EFM32_TIMER_CC_CCV_OFFSET ), - getreg32(base_cc + EFM32_TIMER_CC_CCVP_OFFSET ), - getreg32(base_cc + EFM32_TIMER_CC_CCVB_OFFSET ) - ); + + tmrinfo("CC%d => CTRL: %04x CCV: %04x CCVP: %04x CCVB: %04x\n", + i + getreg32(base_cc + EFM32_TIMER_CC_CTRL_OFFSET ), + getreg32(base_cc + EFM32_TIMER_CC_CCV_OFFSET ), + getreg32(base_cc + EFM32_TIMER_CC_CCVP_OFFSET ), + getreg32(base_cc + EFM32_TIMER_CC_CCVB_OFFSET )); } - efm32_timerinfo("DTCTRL: %04x DTTIME: %04x DTFC: %04x DTOGEN: %04x\n", - getreg32(base + EFM32_TIMER_CTRL_OFFSET ), - getreg32(base + EFM32_TIMER_STATUS_OFFSET ), - getreg32(base + EFM32_TIMER_IEN_OFFSET ), - getreg32(base + EFM32_TIMER_IF_OFFSET ) - ); - efm32_timerinfo("DTFAULT: %04x DTFAULTC: %04x DTLOCK: %04x \n", - getreg32(base + EFM32_TIMER_CTRL_OFFSET ), - getreg32(base + EFM32_TIMER_STATUS_OFFSET ), - getreg32(base + EFM32_TIMER_IEN_OFFSET ), - getreg32(base + EFM32_TIMER_IF_OFFSET ) - ); + tmrinfo("DTCTRL: %04x DTTIME: %04x DTFC: %04x DTOGEN: %04x\n", + getreg32(base + EFM32_TIMER_CTRL_OFFSET ), + getreg32(base + EFM32_TIMER_STATUS_OFFSET ), + getreg32(base + EFM32_TIMER_IEN_OFFSET ), + getreg32(base + EFM32_TIMER_IF_OFFSET )); + tmrinfo("DTFAULT: %04x DTFAULTC: %04x DTLOCK: %04x \n", + getreg32(base + EFM32_TIMER_CTRL_OFFSET ), + getreg32(base + EFM32_TIMER_STATUS_OFFSET ), + getreg32(base + EFM32_TIMER_IEN_OFFSET ), +#endif } /**************************************************************************** @@ -238,6 +201,7 @@ void efm32_timer_reset(uintptr_t base) * prescaler setted, -1 in case of error. * ****************************************************************************/ + int efm32_timer_set_freq(uintptr_t base, uint32_t clk_freq, uint32_t freq) { int prescaler = 0; @@ -262,8 +226,7 @@ int efm32_timer_set_freq(uintptr_t base, uint32_t clk_freq, uint32_t freq) reload = (clk_freq / prescaler / freq); - efm32_timererr("Source: %4xHz Div: %4x Reload: %4x \n", - clk_freq, prescaler, reload); + tmrinfo("Source: %4xHz Div: %4x Reload: %4x \n", clk_freq, prescaler, reload); putreg32(reload, base + EFM32_TIMER_TOP_OFFSET); diff --git a/arch/arm/src/lpc11xx/lpc11_timer.c b/arch/arm/src/lpc11xx/lpc11_timer.c index 56e5f34471..e742dc2de0 100644 --- a/arch/arm/src/lpc11xx/lpc11_timer.c +++ b/arch/arm/src/lpc11xx/lpc11_timer.c @@ -449,7 +449,7 @@ static int timer_shutdown(FAR struct pwm_lowerhalf_s *dev) FAR struct lpc11_timer_s *priv = (FAR struct lpc11_timer_s *)dev; uint32_t pincfg; - pwmerr("TIM%d pincfg: %08x\n", priv->timid, priv->pincfg); + pwminfo("TIM%d pincfg: %08x\n", priv->timid, priv->pincfg); /* Make sure that the output has been stopped */ @@ -505,7 +505,7 @@ static int timer_stop(FAR struct pwm_lowerhalf_s *dev) uint32_t regval; irqstate_t flags; - pwmerr("TIM%d\n", priv->timid); + pwminfo("TIM%d\n", priv->timid); /* Disable interrupts momentary to stop any ongoing timer processing and * to prevent any concurrent access to the reset register. @@ -531,7 +531,7 @@ static int timer_stop(FAR struct pwm_lowerhalf_s *dev) leave_critical_section(flags); - pwmerr("regaddr: %08x resetbit: %08x\n", regaddr, resetbit); + pwminfo("regaddr: %08x resetbit: %08x\n", regaddr, resetbit); timer_dumpregs(priv, "After stop"); return OK; } @@ -555,12 +555,12 @@ static int timer_stop(FAR struct pwm_lowerhalf_s *dev) static int timer_ioctl(FAR struct pwm_lowerhalf_s *dev, int cmd, unsigned long arg) { -#ifdef CONFIG_DEBUG_TIMER +#ifdef CONFIG_DEBUG_PWM_INFO FAR struct lpc11_timer_s *priv = (FAR struct lpc11_timer_s *)dev; /* There are no platform-specific ioctl commands */ - pwmerr("TIM%d\n", priv->timid); + pwminfo("TIM%d\n", priv->timid); #endif return -ENOTTY; } @@ -590,7 +590,7 @@ FAR struct pwm_lowerhalf_s *lpc11_timerinitialize(int timer) { FAR struct lpc11_timer_s *lower; - pwmerr("TIM%d\n", timer); + pwminfo("TIM%d\n", timer); switch (timer) { @@ -604,7 +604,7 @@ FAR struct pwm_lowerhalf_s *lpc11_timerinitialize(int timer) #endif default: - pwmerr("No such timer configured\n"); + pwmerr("ERROR: No such timer configured\n"); return NULL; } diff --git a/arch/arm/src/lpc17xx/lpc17_timer.c b/arch/arm/src/lpc17xx/lpc17_timer.c index 6ce3c1f79e..9278578b67 100644 --- a/arch/arm/src/lpc17xx/lpc17_timer.c +++ b/arch/arm/src/lpc17xx/lpc17_timer.c @@ -450,7 +450,7 @@ static int timer_shutdown(FAR struct pwm_lowerhalf_s *dev) FAR struct lpc17_timer_s *priv = (FAR struct lpc17_timer_s *)dev; uint32_t pincfg; - pwmerr("TIM%d pincfg: %08x\n", priv->timid, priv->pincfg); + pwminfo("TIM%d pincfg: %08x\n", priv->timid, priv->pincfg); /* Make sure that the output has been stopped */ @@ -506,7 +506,7 @@ static int timer_stop(FAR struct pwm_lowerhalf_s *dev) uint32_t regval; irqstate_t flags; - pwmerr("TIM%d\n", priv->timid); + pwminfo("TIM%d\n", priv->timid); /* Disable interrupts momentary to stop any ongoing timer processing and * to prevent any concurrent access to the reset register. @@ -532,7 +532,7 @@ static int timer_stop(FAR struct pwm_lowerhalf_s *dev) leave_critical_section(flags); - pwmerr("regaddr: %08x resetbit: %08x\n", regaddr, resetbit); + pwminfo("regaddr: %08x resetbit: %08x\n", regaddr, resetbit); timer_dumpregs(priv, "After stop"); return OK; } @@ -555,12 +555,12 @@ static int timer_stop(FAR struct pwm_lowerhalf_s *dev) static int timer_ioctl(FAR struct pwm_lowerhalf_s *dev, int cmd, unsigned long arg) { -#ifdef CONFIG_DEBUG_TIMER +#ifdef CONFIG_DEBUG_PWM_INFO FAR struct lpc17_timer_s *priv = (FAR struct lpc17_timer_s *)dev; /* There are no platform-specific ioctl commands */ - pwmerr("TIM%d\n", priv->timid); + pwminfo("TIM%d\n", priv->timid); #endif return -ENOTTY; } @@ -590,7 +590,7 @@ FAR struct pwm_lowerhalf_s *lpc17_timerinitialize(int timer) { FAR struct lpc17_timer_s *lower; - pwmerr("TIM%d\n", timer); + pwminfo("TIM%d\n", timer); switch (timer) { @@ -604,7 +604,7 @@ FAR struct pwm_lowerhalf_s *lpc17_timerinitialize(int timer) #endif default: - pwmerr("No such timer configured\n"); + pwmerr("ERROR: No such timer configured\n"); return NULL; } diff --git a/arch/arm/src/sam34/sam4cm_freerun.c b/arch/arm/src/sam34/sam4cm_freerun.c index 1b74144713..a26578e99a 100644 --- a/arch/arm/src/sam34/sam4cm_freerun.c +++ b/arch/arm/src/sam34/sam4cm_freerun.c @@ -121,7 +121,7 @@ int sam_freerun_initialize(struct sam_freerun_s *freerun, int chan, uint32_t cmr; int ret; - tcinfo("chan=%d resolution=%d usec\n", chan, resolution); + tmrinfo("chan=%d resolution=%d usec\n", chan, resolution); DEBUGASSERT(freerun && resolution > 0); /* Get the TC frequency the corresponds to the requested resolution */ @@ -133,13 +133,13 @@ int sam_freerun_initialize(struct sam_freerun_s *freerun, int chan, ret = sam_tc_divisor(frequency, &divisor, &cmr); if (ret < 0) { - tcerr("ERROR: sam_tc_divisor failed: %d\n", ret); + tmrerr("ERROR: sam_tc_divisor failed: %d\n", ret); return ret; } - tcinfo("frequency=%lu, divisor=%u, cmr=%08lx\n", - (unsigned long)frequency, (unsigned long)divisor, - (unsigned long)cmr); + tmrinfo("frequency=%lu, divisor=%u, cmr=%08lx\n", + (unsigned long)frequency, (unsigned long)divisor, + (unsigned long)cmr); /* Allocate the timer/counter and select its mode of operation * @@ -172,7 +172,7 @@ int sam_freerun_initialize(struct sam_freerun_s *freerun, int chan, freerun->tch = sam_tc_allocate(chan, cmr); if (!freerun->tch) { - tcerr("ERROR: Failed to allocate timer channel %d\n", chan); + tmrerr("ERROR: Failed to allocate timer channel %d\n", chan); return -EBUSY; } @@ -257,9 +257,9 @@ int sam_freerun_counter(struct sam_freerun_s *freerun, struct timespec *ts) leave_critical_section(flags); - tcinfo("counter=%lu (%lu) overflow=%lu, sr=%08lx\n", - (unsigned long)counter, (unsigned long)verify, - (unsigned long)overflow, (unsigned long)sr); + tmrinfo("counter=%lu (%lu) overflow=%lu, sr=%08lx\n", + (unsigned long)counter, (unsigned long)verify, + (unsigned long)overflow, (unsigned long)sr); /* Convert the whole thing to units of microseconds. * @@ -277,7 +277,7 @@ int sam_freerun_counter(struct sam_freerun_s *freerun, struct timespec *ts) ts->tv_sec = sec; ts->tv_nsec = (usec - (sec * USEC_PER_SEC)) * NSEC_PER_USEC; - tcinfo("usec=%llu ts=(%lu, %lu)\n", + tmrinfo("usec=%llu ts=(%lu, %lu)\n", usec, (unsigned long)ts->tv_sec, (unsigned long)ts->tv_nsec); return OK; diff --git a/arch/arm/src/sam34/sam4cm_oneshot.c b/arch/arm/src/sam34/sam4cm_oneshot.c index 6ce9858d4c..402166b2f7 100644 --- a/arch/arm/src/sam34/sam4cm_oneshot.c +++ b/arch/arm/src/sam34/sam4cm_oneshot.c @@ -91,7 +91,7 @@ static void sam_oneshot_handler(TC_HANDLE tch, void *arg, uint32_t sr) oneshot_handler_t oneshot_handler; void *oneshot_arg; - tcllinfo("Expired...\n"); + tmrllinfo("Expired...\n"); DEBUGASSERT(oneshot && oneshot->handler); /* The clock was stopped, but not disabled when the RC match occurred. @@ -148,7 +148,7 @@ int sam_oneshot_initialize(struct sam_oneshot_s *oneshot, int chan, uint32_t cmr; int ret; - tcinfo("chan=%d resolution=%d usec\n", chan, resolution); + tmrinfo("chan=%d resolution=%d usec\n", chan, resolution); DEBUGASSERT(oneshot && resolution > 0); /* Get the TC frequency the corresponds to the requested resolution */ @@ -160,13 +160,13 @@ int sam_oneshot_initialize(struct sam_oneshot_s *oneshot, int chan, ret = sam_tc_divisor(frequency, &divisor, &cmr); if (ret < 0) { - tcerr("ERROR: sam_tc_divisor failed: %d\n", ret); + tmrerr("ERROR: sam_tc_divisor failed: %d\n", ret); return ret; } - tcinfo("frequency=%lu, divisor=%lu, cmr=%08lx\n", - (unsigned long)frequency, (unsigned long)divisor, - (unsigned long)cmr); + tmrinfo("frequency=%lu, divisor=%lu, cmr=%08lx\n", + (unsigned long)frequency, (unsigned long)divisor, + (unsigned long)cmr); /* Allocate the timer/counter and select its mode of operation * @@ -200,7 +200,7 @@ int sam_oneshot_initialize(struct sam_oneshot_s *oneshot, int chan, oneshot->tch = sam_tc_allocate(chan, cmr); if (!oneshot->tch) { - tcerr("ERROR: Failed to allocate timer channel %d\n", chan); + tmrerr("ERROR: Failed to allocate timer channel %d\n", chan); return -EBUSY; } @@ -258,8 +258,8 @@ int sam_oneshot_start(struct sam_oneshot_s *oneshot, struct sam_freerun_s *freer uint64_t regval; irqstate_t flags; - tcinfo("handler=%p arg=%p, ts=(%lu, %lu)\n", - handler, arg, (unsigned long)ts->tv_sec, (unsigned long)ts->tv_nsec); + tmrinfo("handler=%p arg=%p, ts=(%lu, %lu)\n", + handler, arg, (unsigned long)ts->tv_sec, (unsigned long)ts->tv_nsec); DEBUGASSERT(oneshot && handler && ts); /* Was the oneshot already running? */ @@ -269,7 +269,7 @@ int sam_oneshot_start(struct sam_oneshot_s *oneshot, struct sam_freerun_s *freer { /* Yes.. then cancel it */ - tcinfo("Already running... cancelling\n"); + tmrinfo("Already running... cancelling\n"); (void)sam_oneshot_cancel(oneshot, freerun, NULL); } @@ -291,7 +291,7 @@ int sam_oneshot_start(struct sam_oneshot_s *oneshot, struct sam_freerun_s *freer regval = (usec * (uint64_t)sam_tc_divfreq(oneshot->tch)) / USEC_PER_SEC; - tcinfo("usec=%llu regval=%08llx\n", usec, regval); + tmrinfo("usec=%llu regval=%08llx\n", usec, regval); DEBUGASSERT(regval <= UINT16_MAX); /* Set up to receive the callback when the interrupt occurs */ @@ -400,7 +400,7 @@ int sam_oneshot_cancel(struct sam_oneshot_s *oneshot, struct sam_freerun_s *free * REVISIT: This does not appear to be the case. */ - tcinfo("Cancelling...\n"); + tmrinfo("Cancelling...\n"); count = sam_tc_getcounter(oneshot->tch); rc = sam_tc_getregister(oneshot->tch, TC_REGC); @@ -436,8 +436,8 @@ int sam_oneshot_cancel(struct sam_oneshot_s *oneshot, struct sam_freerun_s *free * oneshot timer. */ - tcinfo("rc=%lu count=%lu usec=%lu\n", - (unsigned long)rc, (unsigned long)count, (unsigned long)usec); + tmrinfo("rc=%lu count=%lu usec=%lu\n", + (unsigned long)rc, (unsigned long)count, (unsigned long)usec); /* REVISIT: I am not certain why the timer counter value sometimes * exceeds RC. Might be a bug, or perhaps the counter does not stop @@ -481,8 +481,8 @@ int sam_oneshot_cancel(struct sam_oneshot_s *oneshot, struct sam_freerun_s *free ts->tv_nsec = (unsigned long)nsec; } - tcinfo("remaining (%lu, %lu)\n", - (unsigned long)ts->tv_sec, (unsigned long)ts->tv_nsec); + tmrinfo("remaining (%lu, %lu)\n", + (unsigned long)ts->tv_sec, (unsigned long)ts->tv_nsec); } return OK; diff --git a/arch/arm/src/sam34/sam4cm_tc.c b/arch/arm/src/sam34/sam4cm_tc.c index 5a7be95409..2ffe713072 100644 --- a/arch/arm/src/sam34/sam4cm_tc.c +++ b/arch/arm/src/sam34/sam4cm_tc.c @@ -757,7 +757,7 @@ static inline struct sam_chan_s *sam_tc_initialize(int channel) { /* Timer/counter is not invalid or not enabled */ - tcerr("ERROR: Bad channel number: %d\n", channel); + tmrerr("ERROR: Bad channel number: %d\n", channel); return NULL; } @@ -770,7 +770,7 @@ static inline struct sam_chan_s *sam_tc_initialize(int channel) { /* Initialize the channel. */ - tcerr("Initializing TC%d\n", chconfig->chan); + tmrerr("ERROR: Initializing TC%d\n", chconfig->chan); memset(chan, 0, sizeof(struct sam_chan_s)); sem_init(&chan->exclsem, 0, 1); @@ -831,7 +831,7 @@ static inline struct sam_chan_s *sam_tc_initialize(int channel) { /* No.. return a failure */ - tcerr("Channel %d is in-used\n", channel); + tmrerr("ERROR: Channel %d is in-use\n", channel); sam_givesem(chan); return NULL; } @@ -876,7 +876,7 @@ TC_HANDLE sam_tc_allocate(int channel, int mode) * access to the requested channel. */ - tcinfo("channel=%d mode=%08x\n", channel, mode); + tmrinfo("channel=%d mode=%08x\n", channel, mode); chan = sam_tc_initialize(channel); if (chan) @@ -902,7 +902,7 @@ TC_HANDLE sam_tc_allocate(int channel, int mode) /* Return an opaque reference to the channel */ - tcinfo("Returning %p\n", chan); + tmrinfo("Returning %p\n", chan); return (TC_HANDLE)chan; } @@ -924,7 +924,7 @@ void sam_tc_free(TC_HANDLE handle) { struct sam_chan_s *chan = (struct sam_chan_s *)handle; - tcinfo("Freeing %p channel=%d inuse=%d\n", chan, chan->chan, chan->inuse); + tmrinfo("Freeing %p channel=%d inuse=%d\n", chan, chan->chan, chan->inuse); DEBUGASSERT(chan && chan->inuse); /* Make sure that interrupts are detached and disabled and that the channel @@ -957,7 +957,7 @@ void sam_tc_start(TC_HANDLE handle) { struct sam_chan_s *chan = (struct sam_chan_s *)handle; - tcinfo("Starting channel %d inuse=%d\n", chan->chan, chan->inuse); + tmrinfo("Starting channel %d inuse=%d\n", chan->chan, chan->inuse); DEBUGASSERT(chan && chan->inuse); /* Read the SR to clear any pending interrupts on this channel */ @@ -989,7 +989,7 @@ void sam_tc_stop(TC_HANDLE handle) { struct sam_chan_s *chan = (struct sam_chan_s *)handle; - tcinfo("Stopping channel %d inuse=%d\n", chan->chan, chan->inuse); + tmrinfo("Stopping channel %d inuse=%d\n", chan->chan, chan->inuse); DEBUGASSERT(chan && chan->inuse); sam_chan_putreg(chan, SAM_TC_CCR_OFFSET, TC_CCR_CLKDIS); @@ -1096,8 +1096,8 @@ void sam_tc_setregister(TC_HANDLE handle, int regid, uint32_t regval) DEBUGASSERT(chan && regid < TC_NREGISTERS); - tcinfo("Channel %d: Set register RC%d to %08lx\n", - chan->chan, regid, (unsigned long)regval); + tmrinfo("Channel %d: Set register RC%d to %08lx\n", + chan->chan, regid, (unsigned long)regval); sam_chan_putreg(chan, g_regoffset[regid], regval); sam_regdump(chan, "Set register"); @@ -1233,7 +1233,7 @@ int sam_tc_divisor(uint32_t frequency, uint32_t *div, uint32_t *tcclks) uint32_t ftcin = sam_tc_infreq(); int ndx = 0; - tcinfo("frequency=%d\n", frequency); + tmrinfo("frequency=%d\n", frequency); /* Satisfy lower bound. That is, the value of the divider such that: * @@ -1246,7 +1246,7 @@ int sam_tc_divisor(uint32_t frequency, uint32_t *div, uint32_t *tcclks) { /* If no divisor can be found, return -ERANGE */ - tcerr("Lower bound search failed\n"); + tmrerr("ERROR: Lower bound search failed\n"); return -ERANGE; } } @@ -1270,7 +1270,7 @@ int sam_tc_divisor(uint32_t frequency, uint32_t *div, uint32_t *tcclks) if (div) { uint32_t value = sam_tc_freqdiv_lookup(ftcin, ndx); - tcinfo("return div=%lu\n", (unsigned long)value); + tmrinfo("return div=%lu\n", (unsigned long)value); *div = value; } @@ -1278,7 +1278,7 @@ int sam_tc_divisor(uint32_t frequency, uint32_t *div, uint32_t *tcclks) if (tcclks) { - tcinfo("return tcclks=%08lx\n", (unsigned long)TC_CMR_TCCLKS(ndx)); + tmrinfo("return tcclks=%08lx\n", (unsigned long)TC_CMR_TCCLKS(ndx)); *tcclks = TC_CMR_TCCLKS(ndx); } diff --git a/arch/arm/src/sam34/sam4cm_tc.h b/arch/arm/src/sam34/sam4cm_tc.h index f3b32a1a6f..e474f2bc66 100644 --- a/arch/arm/src/sam34/sam4cm_tc.h +++ b/arch/arm/src/sam34/sam4cm_tc.h @@ -71,8 +71,7 @@ /* Timer debug is enabled if any timer client is enabled */ -#ifndef CONFIG_DEBUG_FEATURES -# undef CONFIG_DEBUG_ANALOG +#ifndef CONFIG_DEBUG_TIMER_INFO # undef CONFIG_SAMA5_TC_REGDEBUG #endif @@ -80,20 +79,6 @@ # define CONFIG_SAM34_TC_DEBUG 1 #endif -/* Timer/counter debug output */ - -#ifdef CONFIG_SAM34_TC_DEBUG -# define tcerr err -# define tcinfo info -# define tcllerr llerr -# define tcllinfo llinfo -#else -# define tcerr(x...) -# define tcinfo(x...) -# define tcllerr(x...) -# define tcllinfo(x...) -#endif - /**************************************************************************** * Public Types ****************************************************************************/ diff --git a/arch/arm/src/sam34/sam4cm_tickless.c b/arch/arm/src/sam34/sam4cm_tickless.c index 048c42ffab..ed6b56dccd 100644 --- a/arch/arm/src/sam34/sam4cm_tickless.c +++ b/arch/arm/src/sam34/sam4cm_tickless.c @@ -197,7 +197,7 @@ static struct sam_tickless_s g_tickless; static void sam_oneshot_handler(void *arg) { - tcllinfo("Expired...\n"); + tmrllinfo("Expired...\n"); sched_timer_expiration(); } @@ -244,7 +244,7 @@ void up_timer_initialize(void) CONFIG_USEC_PER_TICK); if (ret < 0) { - tcllerr("ERROR: sam_oneshot_initialize failed\n"); + tmrllerr("ERROR: sam_oneshot_initialize failed\n"); PANIC(); } @@ -256,7 +256,7 @@ void up_timer_initialize(void) ret = sam_oneshot_max_delay(&g_tickless.oneshot, &max_delay); if (ret < 0) { - tcllerr("ERROR: sam_oneshot_max_delay failed\n"); + tmrllerr("ERROR: sam_oneshot_max_delay failed\n"); PANIC(); } @@ -280,7 +280,7 @@ void up_timer_initialize(void) CONFIG_USEC_PER_TICK); if (ret < 0) { - tcllerr("ERROR: sam_freerun_initialize failed\n"); + tmrllerr("ERROR: sam_freerun_initialize failed\n"); PANIC(); } diff --git a/arch/arm/src/sam34/sam_tc.c b/arch/arm/src/sam34/sam_tc.c index d18da143a3..8feea0a727 100644 --- a/arch/arm/src/sam34/sam_tc.c +++ b/arch/arm/src/sam34/sam_tc.c @@ -70,22 +70,6 @@ #define TC_FCLK (BOARD_SCLK_FREQUENCY) #define TC_MAXTIMEOUT ((1000000ULL * (1ULL + TC_RVALUE_MASK)) / TC_FCLK) -/* Configuration ************************************************************/ - -/* Debug ********************************************************************/ -/* Non-standard debug that may be enabled just for testing the timer - * driver. NOTE: that only llerr types are used so that the output is - * immediately available. - */ - -#ifdef CONFIG_DEBUG_TIMER -# define tcerr llerr -# define tcinfo llinfo -#else -# define tcerr(x...) -# define tcinfo(x...) -#endif - /**************************************************************************** * Private Types ****************************************************************************/ @@ -268,7 +252,7 @@ static int sam34_interrupt(int irq, FAR void *context) { FAR struct sam34_lowerhalf_s *priv = &g_tcdevs[irq-SAM_IRQ_TC0]; - tcinfo("Entry\n"); + tmrinfo("Entry\n"); DEBUGASSERT((irq >= SAM_IRQ_TC0) && (irq <= SAM_IRQ_TC5)); /* Check if the interrupt is really pending */ @@ -299,7 +283,7 @@ static int sam34_interrupt(int irq, FAR void *context) /* No handler or the handler returned false.. stop the timer */ sam34_stop((FAR struct timer_lowerhalf_s *)priv); - tcinfo("Stopped\n"); + tmrinfo("Stopped\n"); } /* TC_INT_CPCS is cleared by reading SAM_TCx_SR */ @@ -328,7 +312,7 @@ static int sam34_start(FAR struct timer_lowerhalf_s *lower) FAR struct sam34_lowerhalf_s *priv = (FAR struct sam34_lowerhalf_s *)lower; uint32_t mr_val; - tcinfo("Entry\n"); + tmrinfo("Entry\n"); DEBUGASSERT(priv); if (priv->started) @@ -382,7 +366,7 @@ static int sam34_start(FAR struct timer_lowerhalf_s *lower) static int sam34_stop(FAR struct timer_lowerhalf_s *lower) { FAR struct sam34_lowerhalf_s *priv = (FAR struct sam34_lowerhalf_s *)lower; - tcinfo("Entry\n"); + tmrinfo("Entry\n"); DEBUGASSERT(priv); if (!priv->started) @@ -421,7 +405,7 @@ static int sam34_getstatus(FAR struct timer_lowerhalf_s *lower, FAR struct sam34_lowerhalf_s *priv = (FAR struct sam34_lowerhalf_s *)lower; uint32_t elapsed; - tcinfo("Entry\n"); + tmrinfo("Entry\n"); DEBUGASSERT(priv); /* Return the status bit */ @@ -446,9 +430,9 @@ static int sam34_getstatus(FAR struct timer_lowerhalf_s *lower, elapsed = sam34_getreg(priv->base + SAM_TC_CV_OFFSET); status->timeleft = ((uint64_t)priv->timeout * elapsed) / (priv->clkticks + 1); /* TODO - check on this +1 */ - tcinfo(" flags : %08x\n", status->flags); - tcinfo(" timeout : %d\n", status->timeout); - tcinfo(" timeleft : %d\n", status->timeleft); + tmrinfo(" flags : %08x\n", status->flags); + tmrinfo(" timeout : %d\n", status->timeout); + tmrinfo(" timeleft : %d\n", status->timeleft); return OK; } @@ -480,14 +464,14 @@ static int sam34_settimeout(FAR struct timer_lowerhalf_s *lower, return -EPERM; } - tcinfo("Entry: timeout=%d\n", timeout); + tmrinfo("Entry: timeout=%d\n", timeout); /* Can this timeout be represented? */ if (timeout < 1 || timeout > TC_MAXTIMEOUT) { - tcerr("Cannot represent timeout=%lu > %lu\n", - timeout, TC_MAXTIMEOUT); + tmrerr("ERROR: Cannot represent timeout=%lu > %lu\n", + timeout, TC_MAXTIMEOUT); return -ERANGE; } @@ -496,8 +480,8 @@ static int sam34_settimeout(FAR struct timer_lowerhalf_s *lower, timeout = (1000000ULL * priv->clkticks) / TC_FCLK; /* Truncated timeout */ priv->adjustment = priv->timeout - timeout; /* Truncated time to be added to next interval (dither) */ - tcinfo("fclk=%d clkticks=%d timout=%d, adjustment=%d\n", - TC_FCLK, priv->clkticks, priv->timeout, priv->adjustment); + tmrinfo("fclk=%d clkticks=%d timout=%d, adjustment=%d\n", + TC_FCLK, priv->clkticks, priv->timeout, priv->adjustment); return OK; } @@ -531,7 +515,7 @@ static tccb_t sam34_sethandler(FAR struct timer_lowerhalf_s *lower, flags = enter_critical_section(); DEBUGASSERT(priv); - tcinfo("Entry: handler=%p\n", handler); + tmrinfo("Entry: handler=%p\n", handler); /* Get the old handler return value */ @@ -572,7 +556,7 @@ static int sam34_ioctl(FAR struct timer_lowerhalf_s *lower, int cmd, int ret = -ENOTTY; DEBUGASSERT(priv); - tcinfo("Entry: cmd=%d arg=%ld\n", cmd, arg); + tmrinfo("Entry: cmd=%d arg=%ld\n", cmd, arg); UNUSED(priv); return ret; @@ -602,7 +586,7 @@ void sam_tcinitialize(FAR const char *devpath, int irq) { FAR struct sam34_lowerhalf_s *priv = &g_tcdevs[irq-SAM_IRQ_TC0]; - tcinfo("Entry: devpath=%s\n", devpath); + tmrinfo("Entry: devpath=%s\n", devpath); DEBUGASSERT((irq >= SAM_IRQ_TC0) && (irq <= SAM_IRQ_TC5)); /* Initialize the driver state structure. Here we assume: (1) the state diff --git a/arch/arm/src/sama5/sam_freerun.c b/arch/arm/src/sama5/sam_freerun.c index dfc5f7a62b..8870988ce6 100644 --- a/arch/arm/src/sama5/sam_freerun.c +++ b/arch/arm/src/sama5/sam_freerun.c @@ -138,7 +138,7 @@ int sam_freerun_initialize(struct sam_freerun_s *freerun, int chan, uint32_t cmr; int ret; - tcinfo("chan=%d resolution=%d usec\n", chan, resolution); + tmrinfo("chan=%d resolution=%d usec\n", chan, resolution); DEBUGASSERT(freerun && resolution > 0); /* Get the TC frequency the corresponds to the requested resolution */ @@ -150,13 +150,13 @@ int sam_freerun_initialize(struct sam_freerun_s *freerun, int chan, ret = sam_tc_divisor(frequency, &divisor, &cmr); if (ret < 0) { - tcerr("ERROR: sam_tc_divisor failed: %d\n", ret); + tmrerr("ERROR: sam_tc_divisor failed: %d\n", ret); return ret; } - tcinfo("frequency=%lu, divisor=%u, cmr=%08lx\n", - (unsigned long)frequency, (unsigned long)divisor, - (unsigned long)cmr); + tmrinfo("frequency=%lu, divisor=%u, cmr=%08lx\n", + (unsigned long)frequency, (unsigned long)divisor, + (unsigned long)cmr); /* Allocate the timer/counter and select its mode of operation * @@ -189,7 +189,7 @@ int sam_freerun_initialize(struct sam_freerun_s *freerun, int chan, freerun->tch = sam_tc_allocate(chan, cmr); if (!freerun->tch) { - tcerr("ERROR: Failed to allocate timer channel %d\n", chan); + tmrerr("ERROR: Failed to allocate timer channel %d\n", chan); return -EBUSY; } @@ -274,9 +274,9 @@ int sam_freerun_counter(struct sam_freerun_s *freerun, struct timespec *ts) leave_critical_section(flags); - tcinfo("counter=%lu (%lu) overflow=%lu, sr=%08lx\n", - (unsigned long)counter, (unsigned long)verify, - (unsigned long)overflow, (unsigned long)sr); + tmrinfo("counter=%lu (%lu) overflow=%lu, sr=%08lx\n", + (unsigned long)counter, (unsigned long)verify, + (unsigned long)overflow, (unsigned long)sr); /* Convert the whole thing to units of microseconds. * @@ -294,7 +294,7 @@ int sam_freerun_counter(struct sam_freerun_s *freerun, struct timespec *ts) ts->tv_sec = sec; ts->tv_nsec = (usec - (sec * USEC_PER_SEC)) * NSEC_PER_USEC; - tcinfo("usec=%llu ts=(%lu, %lu)\n", + tmrinfo("usec=%llu ts=(%lu, %lu)\n", usec, (unsigned long)ts->tv_sec, (unsigned long)ts->tv_nsec); return OK; diff --git a/arch/arm/src/sama5/sam_oneshot.c b/arch/arm/src/sama5/sam_oneshot.c index 62872ea4dd..fc1985a45c 100644 --- a/arch/arm/src/sama5/sam_oneshot.c +++ b/arch/arm/src/sama5/sam_oneshot.c @@ -108,7 +108,7 @@ static void sam_oneshot_handler(TC_HANDLE tch, void *arg, uint32_t sr) oneshot_handler_t oneshot_handler; void *oneshot_arg; - tcllinfo("Expired...\n"); + tmrllinfo("Expired...\n"); DEBUGASSERT(oneshot && oneshot->handler); /* The clock was stopped, but not disabled when the RC match occurred. @@ -165,7 +165,7 @@ int sam_oneshot_initialize(struct sam_oneshot_s *oneshot, int chan, uint32_t cmr; int ret; - tcinfo("chan=%d resolution=%d usec\n", chan, resolution); + tmrinfo("chan=%d resolution=%d usec\n", chan, resolution); DEBUGASSERT(oneshot && resolution > 0); /* Get the TC frequency the corresponds to the requested resolution */ @@ -177,13 +177,13 @@ int sam_oneshot_initialize(struct sam_oneshot_s *oneshot, int chan, ret = sam_tc_divisor(frequency, &divisor, &cmr); if (ret < 0) { - tcerr("ERROR: sam_tc_divisor failed: %d\n", ret); + tmrerr("ERROR: sam_tc_divisor failed: %d\n", ret); return ret; } - tcinfo("frequency=%lu, divisor=%lu, cmr=%08lx\n", - (unsigned long)frequency, (unsigned long)divisor, - (unsigned long)cmr); + tmrinfo("frequency=%lu, divisor=%lu, cmr=%08lx\n", + (unsigned long)frequency, (unsigned long)divisor, + (unsigned long)cmr); /* Allocate the timer/counter and select its mode of operation * @@ -217,7 +217,7 @@ int sam_oneshot_initialize(struct sam_oneshot_s *oneshot, int chan, oneshot->tch = sam_tc_allocate(chan, cmr); if (!oneshot->tch) { - tcerr("ERROR: Failed to allocate timer channel %d\n", chan); + tmrerr("ERROR: Failed to allocate timer channel %d\n", chan); return -EBUSY; } @@ -260,8 +260,8 @@ int sam_oneshot_start(struct sam_oneshot_s *oneshot, struct sam_freerun_s *freer uint64_t regval; irqstate_t flags; - tcinfo("handler=%p arg=%p, ts=(%lu, %lu)\n", - handler, arg, (unsigned long)ts->tv_sec, (unsigned long)ts->tv_nsec); + tmrinfo("handler=%p arg=%p, ts=(%lu, %lu)\n", + handler, arg, (unsigned long)ts->tv_sec, (unsigned long)ts->tv_nsec); DEBUGASSERT(oneshot && handler && ts); /* Was the oneshot already running? */ @@ -271,7 +271,7 @@ int sam_oneshot_start(struct sam_oneshot_s *oneshot, struct sam_freerun_s *freer { /* Yes.. then cancel it */ - tcinfo("Already running... cancelling\n"); + tmrinfo("Already running... cancelling\n"); (void)sam_oneshot_cancel(oneshot, freerun, NULL); } @@ -293,7 +293,7 @@ int sam_oneshot_start(struct sam_oneshot_s *oneshot, struct sam_freerun_s *freer regval = (usec * (uint64_t)sam_tc_divfreq(oneshot->tch)) / USEC_PER_SEC; - tcinfo("usec=%llu regval=%08llx\n", usec, regval); + tmrinfo("usec=%llu regval=%08llx\n", usec, regval); DEBUGASSERT(regval <= UINT32_MAX); /* Set up to receive the callback when the interrupt occurs */ @@ -402,7 +402,7 @@ int sam_oneshot_cancel(struct sam_oneshot_s *oneshot, struct sam_freerun_s *free * REVISIT: This does not appear to be the case. */ - tcinfo("Cancelling...\n"); + tmrinfo("Cancelling...\n"); count = sam_tc_getcounter(oneshot->tch); rc = sam_tc_getregister(oneshot->tch, TC_REGC); @@ -438,8 +438,8 @@ int sam_oneshot_cancel(struct sam_oneshot_s *oneshot, struct sam_freerun_s *free * oneshot timer. */ - tcinfo("rc=%lu count=%lu usec=%lu\n", - (unsigned long)rc, (unsigned long)count, (unsigned long)usec); + tmrinfo("rc=%lu count=%lu usec=%lu\n", + (unsigned long)rc, (unsigned long)count, (unsigned long)usec); /* REVISIT: I am not certain why the timer counter value sometimes * exceeds RC. Might be a bug, or perhaps the counter does not stop @@ -483,8 +483,8 @@ int sam_oneshot_cancel(struct sam_oneshot_s *oneshot, struct sam_freerun_s *free ts->tv_nsec = (unsigned long)nsec; } - tcinfo("remaining (%lu, %lu)\n", - (unsigned long)ts->tv_sec, (unsigned long)ts->tv_nsec); + tmrinfo("remaining (%lu, %lu)\n", + (unsigned long)ts->tv_sec, (unsigned long)ts->tv_nsec); } return OK; diff --git a/arch/arm/src/sama5/sam_tc.c b/arch/arm/src/sama5/sam_tc.c index 6ce38f0ee2..5d51f82047 100644 --- a/arch/arm/src/sama5/sam_tc.c +++ b/arch/arm/src/sama5/sam_tc.c @@ -953,7 +953,7 @@ static inline struct sam_chan_s *sam_tc_initialize(int channel) { /* Timer/counter is not invalid or not enabled */ - tcerr("ERROR: Bad channel number: %d\n", channel); + tmrerr("ERROR: Bad channel number: %d\n", channel); return NULL; } @@ -976,7 +976,7 @@ static inline struct sam_chan_s *sam_tc_initialize(int channel) for (i = 0, ch = tcconfig->chfirst; i < SAM_TC_NCHANNELS; i++) { - tcerr("Initializing TC%d channel %d\n", tcconfig->tc, ch); + tmrerr("ERROR: Initializing TC%d channel %d\n", tcconfig->tc, ch); /* Initialize the channel data structure */ @@ -1057,7 +1057,7 @@ static inline struct sam_chan_s *sam_tc_initialize(int channel) { /* No.. return a failure */ - tcerr("Channel %d is in-used\n", channel); + tmrerr("ERROR: Channel %d is in-use\n", channel); sam_givesem(tc); return NULL; } @@ -1102,7 +1102,7 @@ TC_HANDLE sam_tc_allocate(int channel, int mode) * access to the requested channel. */ - tcinfo("channel=%d mode=%08x\n", channel, mode); + tmrinfo("channel=%d mode=%08x\n", channel, mode); chan = sam_tc_initialize(channel); if (chan) @@ -1128,7 +1128,7 @@ TC_HANDLE sam_tc_allocate(int channel, int mode) /* Return an opaque reference to the channel */ - tcinfo("Returning %p\n", chan); + tmrinfo("Returning %p\n", chan); return (TC_HANDLE)chan; } @@ -1150,7 +1150,7 @@ void sam_tc_free(TC_HANDLE handle) { struct sam_chan_s *chan = (struct sam_chan_s *)handle; - tcinfo("Freeing %p channel=%d inuse=%d\n", chan, chan->chan, chan->inuse); + tmrinfo("Freeing %p channel=%d inuse=%d\n", chan, chan->chan, chan->inuse); DEBUGASSERT(chan && chan->inuse); /* Make sure that interrupts are detached and disabled and that the channel @@ -1183,7 +1183,7 @@ void sam_tc_start(TC_HANDLE handle) { struct sam_chan_s *chan = (struct sam_chan_s *)handle; - tcinfo("Starting channel %d inuse=%d\n", chan->chan, chan->inuse); + tmrinfo("Starting channel %d inuse=%d\n", chan->chan, chan->inuse); DEBUGASSERT(chan && chan->inuse); /* Read the SR to clear any pending interrupts on this channel */ @@ -1215,7 +1215,7 @@ void sam_tc_stop(TC_HANDLE handle) { struct sam_chan_s *chan = (struct sam_chan_s *)handle; - tcinfo("Stopping channel %d inuse=%d\n", chan->chan, chan->inuse); + tmrinfo("Stopping channel %d inuse=%d\n", chan->chan, chan->inuse); DEBUGASSERT(chan && chan->inuse); sam_chan_putreg(chan, SAM_TC_CCR_OFFSET, TC_CCR_CLKDIS); @@ -1322,8 +1322,8 @@ void sam_tc_setregister(TC_HANDLE handle, int regid, uint32_t regval) DEBUGASSERT(chan && regid < TC_NREGISTERS); - tcinfo("Channel %d: Set register RC%d to %08lx\n", - chan->chan, regid, (unsigned long)regval); + tmrinfo("Channel %d: Set register RC%d to %08lx\n", + chan->chan, regid, (unsigned long)regval); sam_chan_putreg(chan, g_regoffset[regid], regval); sam_regdump(chan, "Set register"); @@ -1465,7 +1465,7 @@ int sam_tc_divisor(uint32_t frequency, uint32_t *div, uint32_t *tcclks) uint32_t ftcin = sam_tc_infreq(); int ndx = 0; - tcinfo("frequency=%d\n", frequency); + tmrinfo("frequency=%d\n", frequency); /* Satisfy lower bound. That is, the value of the divider such that: * @@ -1478,7 +1478,7 @@ int sam_tc_divisor(uint32_t frequency, uint32_t *div, uint32_t *tcclks) { /* If no divisor can be found, return -ERANGE */ - tcerr("Lower bound search failed\n"); + tmrerr("ERROR: Lower bound search failed\n"); return -ERANGE; } } @@ -1502,7 +1502,7 @@ int sam_tc_divisor(uint32_t frequency, uint32_t *div, uint32_t *tcclks) if (div) { uint32_t value = sam_tc_freqdiv_lookup(ftcin, ndx); - tcinfo("return div=%lu\n", (unsigned long)value); + tmrinfo("return div=%lu\n", (unsigned long)value); *div = value; } @@ -1510,7 +1510,7 @@ int sam_tc_divisor(uint32_t frequency, uint32_t *div, uint32_t *tcclks) if (tcclks) { - tcinfo("return tcclks=%08lx\n", (unsigned long)TC_CMR_TCCLKS(ndx)); + tmrinfo("return tcclks=%08lx\n", (unsigned long)TC_CMR_TCCLKS(ndx)); *tcclks = TC_CMR_TCCLKS(ndx); } diff --git a/arch/arm/src/sama5/sam_tc.h b/arch/arm/src/sama5/sam_tc.h index dec7b783e4..4cf53f9cc8 100644 --- a/arch/arm/src/sama5/sam_tc.h +++ b/arch/arm/src/sama5/sam_tc.h @@ -74,8 +74,7 @@ /* Timer debug is enabled if any timer client is enabled */ -#ifndef CONFIG_DEBUG_FEATURES -# undef CONFIG_DEBUG_ANALOG +#ifndef CONFIG_DEBUG_TIMER_INFO # undef CONFIG_SAMA5_TC_REGDEBUG #endif @@ -83,20 +82,6 @@ # define CONFIG_SAMA5_TC_DEBUG 1 #endif -/* Timer/counter debug output */ - -#ifdef CONFIG_SAMA5_TC_DEBUG -# define tcerr err -# define tcinfo info -# define tcllerr llerr -# define tcllinfo llinfo -#else -# define tcerr(x...) -# define tcinfo(x...) -# define tcllerr(x...) -# define tcllinfo(x...) -#endif - /**************************************************************************** * Public Types ****************************************************************************/ diff --git a/arch/arm/src/sama5/sam_tickless.c b/arch/arm/src/sama5/sam_tickless.c index 42eeabf809..d3a1d34e01 100644 --- a/arch/arm/src/sama5/sam_tickless.c +++ b/arch/arm/src/sama5/sam_tickless.c @@ -209,7 +209,7 @@ static struct sam_tickless_s g_tickless; static void sam_oneshot_handler(void *arg) { - tcllinfo("Expired...\n"); + tmrllinfo("Expired...\n"); sched_timer_expiration(); } @@ -256,7 +256,7 @@ void up_timer_initialize(void) CONFIG_USEC_PER_TICK); if (ret < 0) { - tcllerr("ERROR: sam_oneshot_initialize failed\n"); + tmrllerr("ERROR: sam_oneshot_initialize failed\n"); PANIC(); } @@ -268,7 +268,7 @@ void up_timer_initialize(void) ret = sam_oneshot_max_delay(&g_tickless.oneshot, &max_delay); if (ret < 0) { - tcllerr("ERROR: sam_oneshot_max_delay failed\n"); + tmrllerr("ERROR: sam_oneshot_max_delay failed\n"); PANIC(); } @@ -292,7 +292,7 @@ void up_timer_initialize(void) CONFIG_USEC_PER_TICK); if (ret < 0) { - tcllerr("ERROR: sam_freerun_initialize failed\n"); + tmrllerr("ERROR: sam_freerun_initialize failed\n"); PANIC(); } diff --git a/arch/arm/src/samv7/sam_freerun.c b/arch/arm/src/samv7/sam_freerun.c index 70747f867a..b3fbfbf6df 100644 --- a/arch/arm/src/samv7/sam_freerun.c +++ b/arch/arm/src/samv7/sam_freerun.c @@ -124,7 +124,7 @@ int sam_freerun_initialize(struct sam_freerun_s *freerun, int chan, uint32_t cmr; int ret; - tcinfo("chan=%d resolution=%d usec\n", chan, resolution); + tmrinfo("chan=%d resolution=%d usec\n", chan, resolution); DEBUGASSERT(freerun && resolution > 0); /* Get the TC frequency the corresponds to the requested resolution */ @@ -136,13 +136,13 @@ int sam_freerun_initialize(struct sam_freerun_s *freerun, int chan, ret = sam_tc_clockselect(frequency, &cmr, &actual); if (ret < 0) { - tcerr("ERROR: sam_tc_clockselect failed: %d\n", ret); + tmrerr("ERROR: sam_tc_clockselect failed: %d\n", ret); return ret; } - tcinfo("frequency=%lu, actual=%lu, cmr=%08lx\n", - (unsigned long)frequency, (unsigned long)actual, - (unsigned long)cmr); + tmrinfo("frequency=%lu, actual=%lu, cmr=%08lx\n", + (unsigned long)frequency, (unsigned long)actual, + (unsigned long)cmr); /* Allocate the timer/counter and select its mode of operation * @@ -175,7 +175,7 @@ int sam_freerun_initialize(struct sam_freerun_s *freerun, int chan, freerun->tch = sam_tc_allocate(chan, cmr); if (!freerun->tch) { - tcerr("ERROR: Failed to allocate timer channel %d\n", chan); + tmrerr("ERROR: Failed to allocate timer channel %d\n", chan); return -EBUSY; } @@ -260,9 +260,9 @@ int sam_freerun_counter(struct sam_freerun_s *freerun, struct timespec *ts) leave_critical_section(flags); - tcinfo("counter=%lu (%lu) overflow=%lu, sr=%08lx\n", - (unsigned long)counter, (unsigned long)verify, - (unsigned long)overflow, (unsigned long)sr); + tmrinfo("counter=%lu (%lu) overflow=%lu, sr=%08lx\n", + (unsigned long)counter, (unsigned long)verify, + (unsigned long)overflow, (unsigned long)sr); /* Convert the whole thing to units of microseconds. * @@ -280,7 +280,7 @@ int sam_freerun_counter(struct sam_freerun_s *freerun, struct timespec *ts) ts->tv_sec = sec; ts->tv_nsec = (usec - (sec * USEC_PER_SEC)) * NSEC_PER_USEC; - tcinfo("usec=%llu ts=(%lu, %lu)\n", + tmrinfo("usec=%llu ts=(%lu, %lu)\n", usec, (unsigned long)ts->tv_sec, (unsigned long)ts->tv_nsec); return OK; diff --git a/arch/arm/src/samv7/sam_oneshot.c b/arch/arm/src/samv7/sam_oneshot.c index 4400c57d93..bb5555a7bb 100644 --- a/arch/arm/src/samv7/sam_oneshot.c +++ b/arch/arm/src/samv7/sam_oneshot.c @@ -109,7 +109,7 @@ static void sam_oneshot_handler(TC_HANDLE tch, void *arg, uint32_t sr) oneshot_handler_t oneshot_handler; void *oneshot_arg; - tcllinfo("Expired...\n"); + tmrllinfo("Expired...\n"); DEBUGASSERT(oneshot && oneshot->handler); /* The clock was stopped, but not disabled when the RC match occurred. @@ -166,7 +166,7 @@ int sam_oneshot_initialize(struct sam_oneshot_s *oneshot, int chan, uint32_t cmr; int ret; - tcinfo("chan=%d resolution=%d usec\n", chan, resolution); + tmrinfo("chan=%d resolution=%d usec\n", chan, resolution); DEBUGASSERT(oneshot && resolution > 0); /* Get the TC frequency the corresponds to the requested resolution */ @@ -178,13 +178,13 @@ int sam_oneshot_initialize(struct sam_oneshot_s *oneshot, int chan, ret = sam_tc_clockselect(frequency, &cmr, &actual); if (ret < 0) { - tcerr("ERROR: sam_tc_clockselect failed: %d\n", ret); + tmrerr("ERROR: sam_tc_clockselect failed: %d\n", ret); return ret; } - tcinfo("frequency=%lu, actual=%lu, cmr=%08lx\n", - (unsigned long)frequency, (unsigned long)actual, - (unsigned long)cmr); + tmrinfo("frequency=%lu, actual=%lu, cmr=%08lx\n", + (unsigned long)frequency, (unsigned long)actual, + (unsigned long)cmr); /* Allocate the timer/counter and select its mode of operation * @@ -218,7 +218,7 @@ int sam_oneshot_initialize(struct sam_oneshot_s *oneshot, int chan, oneshot->tch = sam_tc_allocate(chan, cmr); if (!oneshot->tch) { - tcerr("ERROR: Failed to allocate timer channel %d\n", chan); + tmrerr("ERROR: Failed to allocate timer channel %d\n", chan); return -EBUSY; } @@ -261,8 +261,8 @@ int sam_oneshot_start(struct sam_oneshot_s *oneshot, struct sam_freerun_s *freer uint64_t regval; irqstate_t flags; - tcinfo("handler=%p arg=%p, ts=(%lu, %lu)\n", - handler, arg, (unsigned long)ts->tv_sec, (unsigned long)ts->tv_nsec); + tmrinfo("handler=%p arg=%p, ts=(%lu, %lu)\n", + handler, arg, (unsigned long)ts->tv_sec, (unsigned long)ts->tv_nsec); DEBUGASSERT(oneshot && handler && ts); /* Was the oneshot already running? */ @@ -272,7 +272,7 @@ int sam_oneshot_start(struct sam_oneshot_s *oneshot, struct sam_freerun_s *freer { /* Yes.. then cancel it */ - tcinfo("Already running... cancelling\n"); + tmrinfo("Already running... cancelling\n"); (void)sam_oneshot_cancel(oneshot, freerun, NULL); } @@ -294,7 +294,7 @@ int sam_oneshot_start(struct sam_oneshot_s *oneshot, struct sam_freerun_s *freer regval = (usec * (uint64_t)sam_tc_divfreq(oneshot->tch)) / USEC_PER_SEC; - tcinfo("usec=%llu regval=%08llx\n", usec, regval); + tmrinfo("usec=%llu regval=%08llx\n", usec, regval); DEBUGASSERT(regval <= UINT16_MAX); /* Set up to receive the callback when the interrupt occurs */ @@ -403,7 +403,7 @@ int sam_oneshot_cancel(struct sam_oneshot_s *oneshot, struct sam_freerun_s *free * REVISIT: This does not appear to be the case. */ - tcinfo("Cancelling...\n"); + tmrinfo("Cancelling...\n"); count = sam_tc_getcounter(oneshot->tch); rc = sam_tc_getregister(oneshot->tch, TC_REGC); @@ -439,8 +439,8 @@ int sam_oneshot_cancel(struct sam_oneshot_s *oneshot, struct sam_freerun_s *free * oneshot timer. */ - tcinfo("rc=%lu count=%lu usec=%lu\n", - (unsigned long)rc, (unsigned long)count, (unsigned long)usec); + tmrinfo("rc=%lu count=%lu usec=%lu\n", + (unsigned long)rc, (unsigned long)count, (unsigned long)usec); /* REVISIT: I am not certain why the timer counter value sometimes * exceeds RC. Might be a bug, or perhaps the counter does not stop @@ -484,8 +484,8 @@ int sam_oneshot_cancel(struct sam_oneshot_s *oneshot, struct sam_freerun_s *free ts->tv_nsec = (unsigned long)nsec; } - tcinfo("remaining (%lu, %lu)\n", - (unsigned long)ts->tv_sec, (unsigned long)ts->tv_nsec); + tmrinfo("remaining (%lu, %lu)\n", + (unsigned long)ts->tv_sec, (unsigned long)ts->tv_nsec); } return OK; diff --git a/arch/arm/src/samv7/sam_tc.c b/arch/arm/src/samv7/sam_tc.c index 50f2bad062..968c5528d0 100644 --- a/arch/arm/src/samv7/sam_tc.c +++ b/arch/arm/src/samv7/sam_tc.c @@ -1046,7 +1046,7 @@ static int sam_tc_mcksrc(uint32_t frequency, uint32_t *tcclks, uint32_t fnext; int ndx = 0; - tcinfo("frequency=%d\n", frequency); + tmrinfo("frequency=%d\n", frequency); /* Satisfy lower bound. That is, the value of the divider such that: * @@ -1066,7 +1066,7 @@ static int sam_tc_mcksrc(uint32_t frequency, uint32_t *tcclks, { /* If no divisor can be found, return -ERANGE */ - tcerr("Lower bound search failed\n"); + tmrerr("Lower bound search failed\n"); return -ERANGE; } @@ -1169,7 +1169,7 @@ static inline struct sam_chan_s *sam_tc_initialize(int channel) { /* Timer/counter is not invalid or not enabled */ - tcerr("ERROR: Bad channel number: %d\n", channel); + tmrerr("ERROR: Bad channel number: %d\n", channel); return NULL; } @@ -1225,7 +1225,7 @@ static inline struct sam_chan_s *sam_tc_initialize(int channel) { /* Yes.. return a failure */ - tcerr("Channel %d is in-use\n", channel); + tmrerr("Channel %d is in-use\n", channel); sam_givesem(tc); return NULL; } @@ -1318,7 +1318,7 @@ TC_HANDLE sam_tc_allocate(int channel, int mode) * access to the requested channel. */ - tcinfo("channel=%d mode=%08x\n", channel, mode); + tmrinfo("channel=%d mode=%08x\n", channel, mode); chan = sam_tc_initialize(channel); if (chan) @@ -1344,7 +1344,7 @@ TC_HANDLE sam_tc_allocate(int channel, int mode) /* Return an opaque reference to the channel */ - tcinfo("Returning %p\n", chan); + tmrinfo("Returning %p\n", chan); return (TC_HANDLE)chan; } @@ -1366,7 +1366,7 @@ void sam_tc_free(TC_HANDLE handle) { struct sam_chan_s *chan = (struct sam_chan_s *)handle; - tcinfo("Freeing %p channel=%d inuse=%d\n", chan, chan->chan, chan->inuse); + tmrinfo("Freeing %p channel=%d inuse=%d\n", chan, chan->chan, chan->inuse); DEBUGASSERT(chan && chan->inuse); /* Make sure that interrupts are detached and disabled and that the channel @@ -1399,7 +1399,7 @@ void sam_tc_start(TC_HANDLE handle) { struct sam_chan_s *chan = (struct sam_chan_s *)handle; - tcinfo("Starting channel %d inuse=%d\n", chan->chan, chan->inuse); + tmrinfo("Starting channel %d inuse=%d\n", chan->chan, chan->inuse); DEBUGASSERT(chan && chan->inuse); /* Read the SR to clear any pending interrupts on this channel */ @@ -1431,7 +1431,7 @@ void sam_tc_stop(TC_HANDLE handle) { struct sam_chan_s *chan = (struct sam_chan_s *)handle; - tcinfo("Stopping channel %d inuse=%d\n", chan->chan, chan->inuse); + tmrinfo("Stopping channel %d inuse=%d\n", chan->chan, chan->inuse); DEBUGASSERT(chan && chan->inuse); sam_chan_putreg(chan, SAM_TC_CCR_OFFSET, TC_CCR_CLKDIS); @@ -1538,8 +1538,8 @@ void sam_tc_setregister(TC_HANDLE handle, int regid, uint32_t regval) DEBUGASSERT(chan && regid < TC_NREGISTERS); - tcinfo("Channel %d: Set register RC%d to %08lx\n", - chan->chan, regid, (unsigned long)regval); + tmrinfo("Channel %d: Set register RC%d to %08lx\n", + chan->chan, regid, (unsigned long)regval); sam_chan_putreg(chan, g_regoffset[regid], regval); sam_regdump(chan, "Set register"); @@ -1717,7 +1717,7 @@ int sam_tc_clockselect(uint32_t frequency, uint32_t *tcclks, if (actual) { - tcinfo("return actual=%lu\n", (unsigned long)fselect); + tmrinfo("return actual=%lu\n", (unsigned long)fselect); *actual = pck6_actual; } @@ -1725,7 +1725,7 @@ int sam_tc_clockselect(uint32_t frequency, uint32_t *tcclks, if (tcclks) { - tcinfo("return tcclks=%08lx\n", (unsigned long)TC_CMR_TCCLKS_PCK6); + tmrinfo("return tcclks=%08lx\n", (unsigned long)TC_CMR_TCCLKS_PCK6); *tcclks = TC_CMR_TCCLKS_PCK6; } @@ -1739,7 +1739,7 @@ int sam_tc_clockselect(uint32_t frequency, uint32_t *tcclks, if (actual) { - tcinfo("return actual=%lu\n", (unsigned long)mck_actual); + tmrinfo("return actual=%lu\n", (unsigned long)mck_actual); *actual = mck_actual; } @@ -1747,7 +1747,7 @@ int sam_tc_clockselect(uint32_t frequency, uint32_t *tcclks, if (tcclks) { - tcinfo("return tcclks=%08lx\n", (unsigned long)mck_tcclks); + tmrinfo("return tcclks=%08lx\n", (unsigned long)mck_tcclks); *tcclks = mck_tcclks; } diff --git a/arch/arm/src/samv7/sam_tc.h b/arch/arm/src/samv7/sam_tc.h index 508b297f09..d62ac21252 100644 --- a/arch/arm/src/samv7/sam_tc.h +++ b/arch/arm/src/samv7/sam_tc.h @@ -75,8 +75,7 @@ /* Timer debug is enabled if any timer client is enabled */ -#ifndef CONFIG_DEBUG_FEATURES -# undef CONFIG_DEBUG_ANALOG +#ifndef CONFIG_DEBUG_TIMER_INFO # undef CONFIG_SAMV7_TC_REGDEBUG #endif @@ -84,20 +83,6 @@ # define CONFIG_SAMV7_TC_DEBUG 1 #endif -/* Timer/counter debug output */ - -#ifdef CONFIG_SAMV7_TC_DEBUG -# define tcerr err -# define tcinfo info -# define tcllerr llerr -# define tcllinfo llinfo -#else -# define tcerr(x...) -# define tcinfo(x...) -# define tcllerr(x...) -# define tcllinfo(x...) -#endif - /**************************************************************************** * Public Types ****************************************************************************/ diff --git a/arch/arm/src/samv7/sam_tickless.c b/arch/arm/src/samv7/sam_tickless.c index 6b610642ea..4a547a60e9 100644 --- a/arch/arm/src/samv7/sam_tickless.c +++ b/arch/arm/src/samv7/sam_tickless.c @@ -221,7 +221,7 @@ static struct sam_tickless_s g_tickless; static void sam_oneshot_handler(void *arg) { - tcllinfo("Expired...\n"); + tmrllinfo("Expired...\n"); sched_timer_expiration(); } @@ -265,7 +265,7 @@ void up_timer_initialize(void) CONFIG_USEC_PER_TICK); if (ret < 0) { - tcllerr("ERROR: sam_oneshot_initialize failed\n"); + tmrllerr("ERROR: sam_oneshot_initialize failed\n"); PANIC(); } @@ -278,7 +278,7 @@ void up_timer_initialize(void) CONFIG_USEC_PER_TICK); if (ret < 0) { - tcllerr("ERROR: sam_freerun_initialize failed\n"); + tmrllerr("ERROR: sam_freerun_initialize failed\n"); PANIC(); } diff --git a/arch/arm/src/tiva/Kconfig b/arch/arm/src/tiva/Kconfig index fc61ea26c3..174252528b 100644 --- a/arch/arm/src/tiva/Kconfig +++ b/arch/arm/src/tiva/Kconfig @@ -840,7 +840,7 @@ endif # TIVA_TIMER_16BIT config TIVA_TIMER_REGDEBUG bool "Register level debug" default n - depends on DEBUG_INFO + depends on DEBUG_TIMER_INFO ---help--- Enables extremely detailed register access debug output. @@ -853,7 +853,7 @@ menu "ADC Configuration" config TIVA_ADC_REGDEBUG bool "Register level debug" default n - depends on DEBUG_INFO + depends on DEBUG_ANALOG_INFO ---help--- Enables extremely detailed register access debug output. @@ -1103,7 +1103,7 @@ config TIVA_EMAC_HWCHECKSUM config TIVA_ETHERNET_REGDEBUG bool "Register-Level Debug" default n - depends on DEBUG_INFO + depends on DEBUG_NET_INFO ---help--- Enable very low-level register access debug. Depends on CONFIG_DEBUG_FEATURES. diff --git a/arch/arm/src/tiva/tiva_timer.h b/arch/arm/src/tiva/tiva_timer.h index 16dacb92bd..2f498581d2 100644 --- a/arch/arm/src/tiva/tiva_timer.h +++ b/arch/arm/src/tiva/tiva_timer.h @@ -127,20 +127,6 @@ #define TIMER_ISDMARTCM(c) ((((c)->flags) & TIMER_FLAG_DMARTCM) != 0) #define TIMER_ISDMAMATCH(c) ((((c)->flags) & TIMER_FLAG_DMAMATCH) != 0) -/* Debug ********************************************************************/ -/* Non-standard debug that may be enabled just for testing the timer - * driver. NOTE: that only llerr types are used so that the output is - * immediately available. - */ - -#ifdef CONFIG_DEBUG_TIMER -# define timerr llerr -# define timinfo llinfo -#else -# define timerr(x...) -# define timinfo(x...) -#endif - /**************************************************************************** * Public Types ****************************************************************************/ diff --git a/arch/arm/src/tiva/tiva_timerlib.c b/arch/arm/src/tiva/tiva_timerlib.c index 9aaac03fbe..f04dd26026 100644 --- a/arch/arm/src/tiva/tiva_timerlib.c +++ b/arch/arm/src/tiva/tiva_timerlib.c @@ -63,7 +63,7 @@ * Pre-processor Definitions ****************************************************************************/ -#ifndef CONFIG_DEBUG_INFO +#ifndef CONFIG_DEBUG_TIMER_INFO # undef CONFIG_TIVA_TIMER_REGDEBUG #endif @@ -397,7 +397,7 @@ static bool tiva_timer_checkreg(struct tiva_gptmstate_s *priv, bool wr, { /* Yes... show how many times we did it */ - llinfo("...[Repeats %d times]...\n", priv->ntimes); + tmrinfo("...[Repeats %d times]...\n", priv->ntimes); } /* Save information about the new access */ @@ -430,7 +430,7 @@ static uint32_t tiva_getreg(struct tiva_gptmstate_s *priv, unsigned int offset) #ifdef CONFIG_TIVA_TIMER_REGDEBUG if (tiva_timer_checkreg(priv, false, regval, regaddr)) { - llinfo("%08x->%08x\n", regaddr, regval); + tmrinfo("%08x->%08x\n", regaddr, regval); } #endif @@ -453,7 +453,7 @@ static void tiva_putreg(struct tiva_gptmstate_s *priv, unsigned int offset, #ifdef CONFIG_TIVA_TIMER_REGDEBUG if (tiva_timer_checkreg(priv, true, regval, regaddr)) { - llinfo("%08x<-%08x\n", regaddr, regval); + tmrinfo("%08x<-%08x\n", regaddr, regval); } #endif @@ -1780,7 +1780,7 @@ TIMER_HANDLE tiva_gptm_configure(const struct tiva_gptmconfig_s *config) priv->clkin = ALTCLK_FREQUENCY; #else - timinfo("tiva_gptm_configure: Error: alternate clock only available on TM4C129 devices\n"); + tmrinfo("tiva_gptm_configure: Error: alternate clock only available on TM4C129 devices\n"); return (TIMER_HANDLE)NULL; #endif /* CONFIG_ARCH_CHIP_TM4C129 */ } @@ -2382,14 +2382,14 @@ void tiva_timer32_setinterval(TIMER_HANDLE handle, uint32_t interval) #ifdef CONFIG_TIVA_TIMER_REGDEBUG /* Generate low-level debug output outside of the critical section */ - llinfo("%08x<-%08x\n", loadr, interval); + tmrinfo("%08x<-%08x\n", loadr, interval); if (toints) { # ifdef CONFIG_ARCH_CHIP_TM4C129 - llinfo("%08x->%08x\n", moder, modev1); - llinfo("%08x<-%08x\n", moder, modev2); + tmrinfo("%08x->%08x\n", moder, modev1); + tmrinfo("%08x<-%08x\n", moder, modev2); # endif /* CONFIG_ARCH_CHIP_TM4C129 */ - llinfo("%08x<-%08x\n", imrr, priv->imr); + tmrinfo("%08x<-%08x\n", imrr, priv->imr); } #endif } @@ -2529,14 +2529,14 @@ void tiva_timer16_setinterval(TIMER_HANDLE handle, uint16_t interval, int tmndx) #ifdef CONFIG_TIVA_TIMER_REGDEBUG /* Generate low-level debug output outside of the critical section */ - llinfo("%08x<-%08x\n", loadr, interval); + tmrinfo("%08x<-%08x\n", loadr, interval); if (toints) { #ifdef CONFIG_ARCH_CHIP_TM4C129 - llinfo("%08x->%08x\n", moder, modev1); - llinfo("%08x<-%08x\n", moder, modev2); + tmrinfo("%08x->%08x\n", moder, modev1); + tmrinfo("%08x<-%08x\n", moder, modev2); #endif - llinfo("%08x<-%08x\n", imrr, priv->imr); + tmrinfo("%08x<-%08x\n", imrr, priv->imr); } #endif } @@ -2568,7 +2568,7 @@ uint32_t tiva_timer32_remaining(TIMER_HANDLE handle) uint32_t interval; uint32_t remaining; - timinfo("Entry\n"); + tmrinfo("Entry\n"); DEBUGASSERT(priv && priv->attr && priv->config && priv->config->mode != TIMER16_MODE); @@ -2734,13 +2734,13 @@ void tiva_rtc_setalarm(TIMER_HANDLE handle, uint32_t delay) #ifdef CONFIG_TIVA_TIMER_REGDEBUG /* Generate low-level debug output outside of the critical section */ - llinfo("%08x->%08x\n", base + TIVA_TIMER_TAR_OFFSET, counter); - llinfo("%08x<-%08x\n", base + TIVA_TIMER_TAMATCHR_OFFSET, match); + tmrinfo("%08x->%08x\n", base + TIVA_TIMER_TAR_OFFSET, counter); + tmrinfo("%08x<-%08x\n", base + TIVA_TIMER_TAMATCHR_OFFSET, match); #ifdef CONFIG_ARCH_CHIP_TM4C129 - llinfo("%08x->%08x\n", base + TIVA_TIMER_ADCEV_OFFSET, adcev); - llinfo("%08x<-%08x\n", base + TIVA_TIMER_ADCEV_OFFSET, adcev | adcbits); + tmrinfo("%08x->%08x\n", base + TIVA_TIMER_ADCEV_OFFSET, adcev); + tmrinfo("%08x<-%08x\n", base + TIVA_TIMER_ADCEV_OFFSET, adcev | adcbits); #endif /* CONFIG_ARCH_CHIP_TM4C129 */ - llinfo("%08x<-%08x\n", base + TIVA_TIMER_IMR_OFFSET, priv->imr); + tmrinfo("%08x<-%08x\n", base + TIVA_TIMER_IMR_OFFSET, priv->imr); #endif } #endif @@ -2838,13 +2838,13 @@ void tiva_timer32_relmatch(TIMER_HANDLE handle, uint32_t relmatch) #ifdef CONFIG_TIVA_TIMER_REGDEBUG /* Generate low-level debug output outside of the critical section */ - llinfo("%08x->%08x\n", base + TIVA_TIMER_TAR_OFFSET, counter); - llinfo("%08x<-%08x\n", base + TIVA_TIMER_TAMATCHR_OFFSET, match); + tmrinfo("%08x->%08x\n", base + TIVA_TIMER_TAR_OFFSET, counter); + tmrinfo("%08x<-%08x\n", base + TIVA_TIMER_TAMATCHR_OFFSET, match); #ifdef CONFIG_ARCH_CHIP_TM4C129 - llinfo("%08x->%08x\n", base + TIVA_TIMER_ADCEV_OFFSET, adcev); - llinfo("%08x<-%08x\n", base + TIVA_TIMER_ADCEV_OFFSET, adcev | adcbits); + tmrinfo("%08x->%08x\n", base + TIVA_TIMER_ADCEV_OFFSET, adcev); + tmrinfo("%08x<-%08x\n", base + TIVA_TIMER_ADCEV_OFFSET, adcev | adcbits); #endif /* CONFIG_ARCH_CHIP_TM4C129 */ - llinfo("%08x<-%08x\n", base + TIVA_TIMER_IMR_OFFSET, priv->imr); + tmrinfo("%08x<-%08x\n", base + TIVA_TIMER_IMR_OFFSET, priv->imr); #endif /* CONFIG_TIVA_TIMER_REGDEBUG */ } @@ -3040,15 +3040,15 @@ void tiva_timer16_relmatch(TIMER_HANDLE handle, uint32_t relmatch, int tmndx) #ifdef CONFIG_TIVA_TIMER_REGDEBUG /* Generate low-level debug output outside of the critical section */ - llinfo("%08x->%08x\n", timerr, timerv); - llinfo("%08x->%08x\n", prescr, prescv); - llinfo("%08x<-%08x\n", matchr, matchv); - llinfo("%08x<-%08x\n", prematchr, prematchv); + tmrinfo("%08x->%08x\n", timerr, timerv); + tmrinfo("%08x->%08x\n", prescr, prescv); + tmrinfo("%08x<-%08x\n", matchr, matchv); + tmrinfo("%08x<-%08x\n", prematchr, prematchv); #ifdef CONFIG_ARCH_CHIP_TM4C129 - llinfo("%08x->%08x\n", adcevr, adcevv); - llinfo("%08x<-%08x\n", adcevr, adcevv | adcbits); + tmrinfo("%08x->%08x\n", adcevr, adcevv); + tmrinfo("%08x<-%08x\n", adcevr, adcevv | adcbits); #endif - llinfo("%08x<-%08x\n", imr, priv->imr); + tmrinfo("%08x<-%08x\n", imr, priv->imr); #endif } #endif diff --git a/arch/arm/src/tiva/tiva_timerlow32.c b/arch/arm/src/tiva/tiva_timerlow32.c index c96b8a4570..2491e01f63 100644 --- a/arch/arm/src/tiva/tiva_timerlow32.c +++ b/arch/arm/src/tiva/tiva_timerlow32.c @@ -57,10 +57,6 @@ #if defined(CONFIG_TIMER) && defined(CONFIG_TIVA_TIMER) -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - /**************************************************************************** * Private Types ****************************************************************************/ @@ -200,7 +196,7 @@ static uint32_t tiva_ticks2usec(struct tiva_lowerhalf_s *priv, uint32_t ticks) static void tiva_timeout(struct tiva_lowerhalf_s *priv, uint32_t timeout) { - timinfo("Entry: timeout=%d\n", timeout); + tmrinfo("Entry: timeout=%d\n", timeout); /* Save the desired timeout value */ @@ -215,7 +211,7 @@ static void tiva_timeout(struct tiva_lowerhalf_s *priv, uint32_t timeout) timeout = tiva_ticks2usec(priv, priv->clkticks); priv->adjustment = priv->timeout - timeout; - timinfo("clkin=%d clkticks=%d timeout=%d, adjustment=%d\n", + tmrinfo("clkin=%d clkticks=%d timeout=%d, adjustment=%d\n", priv->clkin, priv->clkticks, priv->timeout, priv->adjustment); } @@ -237,7 +233,7 @@ static void tiva_timer_handler(TIMER_HANDLE handle, void *arg, uint32_t status) { struct tiva_lowerhalf_s *priv = (struct tiva_lowerhalf_s *)arg; - timinfo("Entry: status=%08x\n", status); + tmrinfo("Entry: status=%08x\n", status); DEBUGASSERT(arg && status); /* Check if the timeout interrupt is pending */ @@ -276,7 +272,7 @@ static void tiva_timer_handler(TIMER_HANDLE handle, void *arg, uint32_t status) /* No handler or the handler returned false.. stop the timer */ tiva_timer32_stop(priv->handle); - timinfo("Stopped\n"); + tmrinfo("Stopped\n"); } } } @@ -300,7 +296,7 @@ static int tiva_start(struct timer_lowerhalf_s *lower) { struct tiva_lowerhalf_s *priv = (struct tiva_lowerhalf_s *)lower; - timinfo("Entry: started %d\n", priv->started); + tmrinfo("Entry: started %d\n", priv->started); /* Has the timer already been started? */ @@ -337,7 +333,7 @@ static int tiva_stop(struct timer_lowerhalf_s *lower) { struct tiva_lowerhalf_s *priv = (struct tiva_lowerhalf_s *)lower; - timinfo("Entry: started %d\n", priv->started); + tmrinfo("Entry: started %d\n", priv->started); /* Has the timer already been started? */ @@ -377,7 +373,7 @@ static int tiva_getstatus(struct timer_lowerhalf_s *lower, struct tiva_lowerhalf_s *priv = (struct tiva_lowerhalf_s *)lower; uint32_t remaining; - timinfo("Entry\n"); + tmrinfo("Entry\n"); DEBUGASSERT(priv); /* Return the status bit */ @@ -402,9 +398,9 @@ static int tiva_getstatus(struct timer_lowerhalf_s *lower, remaining = tiva_timer32_remaining(priv->handle); status->timeleft = tiva_ticks2usec(priv, remaining); - timinfo(" flags : %08x\n", status->flags); - timinfo(" timeout : %d\n", status->timeout); - timinfo(" timeleft : %d\n", status->timeleft); + tmrinfo(" flags : %08x\n", status->flags); + tmrinfo(" timeout : %d\n", status->timeout); + tmrinfo(" timeleft : %d\n", status->timeleft); return OK; } @@ -435,7 +431,7 @@ static int tiva_settimeout(struct timer_lowerhalf_s *lower, uint32_t timeout) return -EPERM; } - timinfo("Entry: timeout=%d\n", timeout); + tmrinfo("Entry: timeout=%d\n", timeout); /* Calculate the the new time settings */ @@ -476,7 +472,7 @@ static tccb_t tiva_sethandler(struct timer_lowerhalf_s *lower, flags = enter_critical_section(); DEBUGASSERT(priv); - timinfo("Entry: handler=%p\n", handler); + tmrinfo("Entry: handler=%p\n", handler); /* Get the old handler return value */ @@ -516,7 +512,7 @@ static int tiva_ioctl(struct timer_lowerhalf_s *lower, int cmd, int ret = -ENOTTY; DEBUGASSERT(priv); - timinfo("Entry: cmd=%d arg=%ld\n", cmd, arg); + tmrinfo("Entry: cmd=%d arg=%ld\n", cmd, arg); return ret; } @@ -557,7 +553,7 @@ int tiva_timer_initialize(FAR const char *devpath, void *drvr; int ret; - timinfo("\n"); + tmrinfo("\n"); DEBUGASSERT(devpath); /* Allocate an instance of the lower half state structure */ @@ -565,7 +561,7 @@ int tiva_timer_initialize(FAR const char *devpath, priv = (struct tiva_lowerhalf_s *)kmm_zalloc(sizeof(struct tiva_lowerhalf_s)); if (!priv) { - timerr("ERROR: Failed to allocate driver structure\n"); + tmrerr("ERROR: Failed to allocate driver structure\n"); return -ENOMEM; } @@ -577,7 +573,7 @@ int tiva_timer_initialize(FAR const char *devpath, #else if (config->cmn.alternate) { - timerr("ERROR: Alternate clock unsupported on TM4C123 architecture\n"); + tmrerr("ERROR: Alternate clock unsupported on TM4C123 architecture\n"); return -ENOMEM; } else @@ -599,7 +595,7 @@ int tiva_timer_initialize(FAR const char *devpath, priv->handle = tiva_gptm_configure((const struct tiva_gptmconfig_s *)&priv->config); if (!priv->handle) { - timerr("ERROR: Failed to create timer handle\n"); + tmrerr("ERROR: Failed to create timer handle\n"); ret = -EINVAL; goto errout_with_alloc; } diff --git a/configs/dk-tm4c129x/src/tm4c_timer.c b/configs/dk-tm4c129x/src/tm4c_timer.c index 1690fd0ba6..f331781088 100644 --- a/configs/dk-tm4c129x/src/tm4c_timer.c +++ b/configs/dk-tm4c129x/src/tm4c_timer.c @@ -102,12 +102,12 @@ int tiva_timer_configure(void) { int ret; - timinfo("Registering TIMER%d at %s\n", GPTM, CONFIG_DK_TM4C129X_TIMER_DEVNAME); + tmrinfo("Registering TIMER%d at %s\n", GPTM, CONFIG_DK_TM4C129X_TIMER_DEVNAME); ret = tiva_timer_register(CONFIG_DK_TM4C129X_TIMER_DEVNAME, GPTM, ALTCLK); if (ret < 0) { - timerr("ERROR: Failed to register timer driver: %d\n", ret); + tmrerr("ERROR: Failed to register timer driver: %d\n", ret); } return ret; diff --git a/configs/sam4s-xplained-pro/src/sam_tc.c b/configs/sam4s-xplained-pro/src/sam_tc.c index 12b374a738..f00fd42c04 100644 --- a/configs/sam4s-xplained-pro/src/sam_tc.c +++ b/configs/sam4s-xplained-pro/src/sam_tc.c @@ -95,34 +95,6 @@ # define CONFIG_RTT_DEVPATH "/dev/rtt0" #endif -/* Timer Definitions ********************************************************/ - -/* Debug ********************************************************************/ -/* Non-standard debug that may be enabled just for testing the watchdog - * timer - */ - -#ifndef CONFIG_DEBUG_FEATURES -# undef CONFIG_DEBUG_TIMER -#endif - -#ifdef CONFIG_DEBUG_TIMER -# define tcerr err -# define tcllerr llerr -# ifdef CONFIG_DEBUG_INFO -# define tcinfo info -# define tcllinfo llinfo -# else -# define tcinfo(x...) -# define tcllinfo(x...) -# endif -#else -# define tcerr(x...) -# define tcllerr(x...) -# define tcinfo(x...) -# define tcllinfo(x...) -#endif - /**************************************************************************** * Private Functions ****************************************************************************/ @@ -168,37 +140,37 @@ int sam_timerinitialize(void) /* Initialize and register the timer devices */ #if defined(CONFIG_SAM34_TC0) - tcinfo("Initializing %s...\n", CONFIG_TIMER0_DEVPATH); + tmrinfo("Initializing %s...\n", CONFIG_TIMER0_DEVPATH); sam_tcinitialize(CONFIG_TIMER0_DEVPATH, SAM_IRQ_TC0); #endif #if defined(CONFIG_SAM34_TC1) - tcinfo("Initializing %s...\n", CONFIG_TIMER1_DEVPATH); + tmrinfo("Initializing %s...\n", CONFIG_TIMER1_DEVPATH); sam_tcinitialize(CONFIG_TIMER1_DEVPATH, SAM_IRQ_TC1); #endif #if defined(CONFIG_SAM34_TC2) - tcinfo("Initializing %s...\n", CONFIG_TIMER2_DEVPATH); + tmrinfo("Initializing %s...\n", CONFIG_TIMER2_DEVPATH); sam_tcinitialize(CONFIG_TIMER2_DEVPATH, SAM_IRQ_TC2); #endif #if defined(CONFIG_SAM34_TC3) - tcinfo("Initializing %s...\n", CONFIG_TIMER3_DEVPATH); + tmrinfo("Initializing %s...\n", CONFIG_TIMER3_DEVPATH); sam_tcinitialize(CONFIG_TIMER3_DEVPATH, SAM_IRQ_TC3); #endif #if defined(CONFIG_SAM34_TC4) - tcinfo("Initializing %s...\n", CONFIG_TIMER4_DEVPATH); + tmrinfo("Initializing %s...\n", CONFIG_TIMER4_DEVPATH); sam_tcinitialize(CONFIG_TIMER4_DEVPATH, SAM_IRQ_TC4); #endif #if defined(CONFIG_SAM34_TC5) - tcinfo("Initializing %s...\n", CONFIG_TIMER5_DEVPATH); + tmrinfo("Initializing %s...\n", CONFIG_TIMER5_DEVPATH); sam_tcinitialize(CONFIG_TIMER5_DEVPATH, SAM_IRQ_TC5); #endif #if defined(CONFIG_SAM34_RTT) - tcinfo("Initializing %s...\n", CONFIG_RTT_DEVPATH); + tmrinfo("Initializing %s...\n", CONFIG_RTT_DEVPATH); sam_rttinitialize(CONFIG_RTT_DEVPATH); #endif @@ -206,23 +178,23 @@ int sam_timerinitialize(void) !defined(CONFIG_SUPPRESS_TIMER_INTS) /* System Timer Initialization */ - tcinfo("Opening %s\n", CONFIG_SAM4S_XPLAINED_PRO_SCHED_TIMER_DEVPATH); + tmrinfo("Opening %s\n", CONFIG_SAM4S_XPLAINED_PRO_SCHED_TIMER_DEVPATH); fd = open(CONFIG_SAM4S_XPLAINED_PRO_SCHED_TIMER_DEVPATH, O_RDONLY); if (fd < 0) { - tcerr("ERROR: open %s failed: %d\n", - CONFIG_SAM4S_XPLAINED_PRO_SCHED_TIMER_DEVPATH, errno); + tmrerr("ERROR: open %s failed: %d\n", + CONFIG_SAM4S_XPLAINED_PRO_SCHED_TIMER_DEVPATH, errno); goto errout; } /* Set the timeout */ - tcinfo("Interval = %d us.\n", (unsigned long)USEC_PER_TICK); + tmrinfo("Interval = %d us.\n", (unsigned long)USEC_PER_TICK); ret = ioctl(fd, TCIOC_SETTIMEOUT, (unsigned long)USEC_PER_TICK); if (ret < 0) { - tcerr("ERROR: ioctl(TCIOC_SETTIMEOUT) failed: %d\n", errno); + tmrerr("ERROR: ioctl(TCIOC_SETTIMEOUT) failed: %d\n", errno); goto errout_with_dev; } @@ -235,18 +207,18 @@ int sam_timerinitialize(void) ret = ioctl(fd, TCIOC_SETHANDLER, (unsigned long)&tccb); if (ret < 0) { - tcerr("ERROR: ioctl(TCIOC_SETHANDLER) failed: %d\n", errno); + tmrerr("ERROR: ioctl(TCIOC_SETHANDLER) failed: %d\n", errno); goto errout_with_dev; } } /* Start the timer */ - tcinfo("Starting.\n"); + tmrinfo("Starting.\n"); ret = ioctl(fd, TCIOC_START, 0); if (ret < 0) { - tcerr("ERROR: ioctl(TCIOC_START) failed: %d\n", errno); + tmrerr("ERROR: ioctl(TCIOC_START) failed: %d\n", errno); goto errout_with_dev; } #endif @@ -254,25 +226,25 @@ int sam_timerinitialize(void) #if defined(CONFIG_SCHED_CPULOAD) && defined(CONFIG_SCHED_CPULOAD_EXTCLK) /* CPU Load initialization */ - tcinfo("Opening %s\n", CONFIG_SAM4S_XPLAINED_PRO_CPULOAD_TIMER_DEVPATH); + tmrinfo("Opening %s\n", CONFIG_SAM4S_XPLAINED_PRO_CPULOAD_TIMER_DEVPATH); fd = open(CONFIG_SAM4S_XPLAINED_PRO_CPULOAD_TIMER_DEVPATH, O_RDONLY); if (fd < 0) { - tcerr("ERROR: open %s failed: %d\n", - CONFIG_SAM4S_XPLAINED_PRO_CPULOAD_TIMER_DEVPATH, errno); + tmrerr("ERROR: open %s failed: %d\n", + CONFIG_SAM4S_XPLAINED_PRO_CPULOAD_TIMER_DEVPATH, errno); goto errout; } /* Set the timeout */ - tcinfo("Interval = %d us.\n", (unsigned long)1000000 / CONFIG_SCHED_CPULOAD_TICKSPERSEC); + tmrinfo("Interval = %d us.\n", (unsigned long)1000000 / CONFIG_SCHED_CPULOAD_TICKSPERSEC); ret = ioctl(fd, TCIOC_SETTIMEOUT, (unsigned long)1000000 / CONFIG_SCHED_CPULOAD_TICKSPERSEC); if (ret < 0) { - tcerr("ERROR: ioctl(TCIOC_SETTIMEOUT) failed: %d\n", errno); + tmrerr("ERROR: ioctl(TCIOC_SETTIMEOUT) failed: %d\n", errno); goto errout_with_dev; } @@ -286,18 +258,18 @@ int sam_timerinitialize(void) ret = ioctl(fd, TCIOC_SETHANDLER, (unsigned long)&tccb); if (ret < 0) { - tcerr("ERROR: ioctl(TCIOC_SETHANDLER) failed: %d\n", errno); + tmrerr("ERROR: ioctl(TCIOC_SETHANDLER) failed: %d\n", errno); goto errout_with_dev; } } /* Start the timer */ - tcinfo("Starting.\n"); + tmrinfo("Starting.\n"); ret = ioctl(fd, TCIOC_START, 0); if (ret < 0) { - tcerr("ERROR: ioctl(TCIOC_START) failed: %d\n", errno); + tmrerr("ERROR: ioctl(TCIOC_START) failed: %d\n", errno); goto errout_with_dev; } #endif diff --git a/configs/tm4c1294-launchpad/src/tm4c_timer.c b/configs/tm4c1294-launchpad/src/tm4c_timer.c index d3957309be..7405bcc06d 100644 --- a/configs/tm4c1294-launchpad/src/tm4c_timer.c +++ b/configs/tm4c1294-launchpad/src/tm4c_timer.c @@ -101,14 +101,14 @@ int tiva_timer_configure(void) { int ret; - timinfo("Registering TIMER%d at %s\n", + tmrinfo("Registering TIMER%d at %s\n", GPTM, CONFIG_TM4C1294_LAUNCHPAD_TIMER_DEVNAME); ret = tiva_timer_register(CONFIG_TM4C1294_LAUNCHPAD_TIMER_DEVNAME, GPTM, ALTCLK); if (ret < 0) { - timerr("ERROR: Failed to register timer driver: %d\n", ret); + tmrerr("ERROR: Failed to register timer driver: %d\n", ret); } return ret; diff --git a/drivers/timers/timer.c b/drivers/timers/timer.c index 1a5c485a84..6bcbc3b634 100644 --- a/drivers/timers/timer.c +++ b/drivers/timers/timer.c @@ -57,24 +57,6 @@ #ifdef CONFIG_TIMER -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ -/* Debug ********************************************************************/ -/* Non-standard debug that may be enabled just for testing the timer driver */ - -#ifdef CONFIG_DEBUG_TIMER -# define tmrerr err -# define tmrinfo info -# define tmrllerr llerr -# define tmrllinfo llinfo -#else -# define tmrerr(x...) -# define tmrinfo(x...) -# define tmrllerr(x...) -# define tmrllinfo(x...) -#endif - /**************************************************************************** * Private Type Definitions ****************************************************************************/ diff --git a/include/debug.h b/include/debug.h index e6c835e552..735efb048e 100644 --- a/include/debug.h +++ b/include/debug.h @@ -741,6 +741,30 @@ # define spillinfo(x...) #endif +#ifdef CONFIG_DEBUG_TIMER_ERROR +# define tmrerr(format, ...) err(format, ##__VA_ARGS__) +# define tmrllerr(format, ...) llerr(format, ##__VA_ARGS__) +#else +# define tmrerr(x...) +# define tmrllerr(x...) +#endif + +#ifdef CONFIG_DEBUG_TIMER_WARN +# define tmrwarn(format, ...) warn(format, ##__VA_ARGS__) +# define tmrllwarn(format, ...) llwarn(format, ##__VA_ARGS__) +#else +# define tmrwarn(x...) +# define tmrllwarn(x...) +#endif + +#ifdef CONFIG_DEBUG_TIMER_INFO +# define tmrinfo(format, ...) info(format, ##__VA_ARGS__) +# define tmrllinfo(format, ...) llinfo(format, ##__VA_ARGS__) +#else +# define tmrinfo(x...) +# define tmrllinfo(x...) +#endif + #ifdef CONFIG_DEBUG_USB_ERROR # define uerr(format, ...) err(format, ##__VA_ARGS__) # define ullerr(format, ...) llerr(format, ##__VA_ARGS__) @@ -1378,6 +1402,30 @@ # define spillinfo (void) #endif +#ifdef CONFIG_DEBUG_TIMER_ERROR +# define tmrerr err +# define tmrllerr llerr +#else +# define tmrerr (void) +# define tmrllerr (void) +#endif + +#ifdef CONFIG_DEBUG_TIMER_WARN +# define tmrwarn warn +# define tmrllwarn llwarn +#else +# define tmrwarn (void) +# define tmrllwarn (void) +#endif + +#ifdef CONFIG_DEBUG_TIMER_INFO +# define tmrinfo info +# define tmrllinfo llinfo +#else +# define tmrinfo (void) +# define tmrllinfo (void) +#endif + #ifdef CONFIG_DEBUG_USB_ERROR # define uerr err # define ullerr llerr @@ -1612,6 +1660,22 @@ # define sninfodumpbuffer(m,b,n) #endif +#ifdef CONFIG_DEBUG_SPI +# define spierrdumpbuffer(m,b,n) errdumpbuffer(m,b,n) +# define spiinfodumpbuffer(m,b,n) infodumpbuffer(m,b,n) +#else +# define spierrdumpbuffer(m,b,n) +# define spiinfodumpbuffer(m,b,n) +#endif + +#ifdef CONFIG_DEBUG_TIMER +# define tmrerrdumpbuffer(m,b,n) errdumpbuffer(m,b,n) +# define tmrinfodumpbuffer(m,b,n) infodumpbuffer(m,b,n) +#else +# define tmrerrdumpbuffer(m,b,n) +# define tmrinfodumpbuffer(m,b,n) +#endif + #ifdef CONFIG_DEBUG_USB # define uerrdumpbuffer(m,b,n) errdumpbuffer(m,b,n) # define uinfodumpbuffer(m,b,n) infodumpbuffer(m,b,n) From b7f0fbc07345adee56541e60a8bd52c3908f2551 Mon Sep 17 00:00:00 2001 From: Gregory Nutt Date: Thu, 16 Jun 2016 07:39:23 -0600 Subject: [PATCH 03/75] Centralize definitions associated with CONFIG_DEBUG_RTC --- Kconfig | 33 +++++++++++- arch/arm/src/efm32/efm32_rtc_burtc.c | 24 +++------ arch/arm/src/lpc17xx/lpc176x_rtc.c | 48 +++++------------ arch/arm/src/sam34/sam_rtc.c | 62 +++++++-------------- arch/arm/src/sama5/sam_rtc.c | 62 +++++++-------------- arch/arm/src/stm32/stm32_rtcc.c | 78 ++++++++++----------------- arch/arm/src/stm32/stm32f40xxx_rtcc.c | 74 ++++++++++--------------- arch/arm/src/stm32l4/stm32l4_rtcc.c | 76 ++++++++++---------------- drivers/timers/ds3231.c | 40 ++++---------- drivers/timers/pcf85263.c | 40 ++++---------- include/debug.h | 56 +++++++++++++++++++ 11 files changed, 251 insertions(+), 342 deletions(-) diff --git a/Kconfig b/Kconfig index 65a55a285d..70c8cec584 100644 --- a/Kconfig +++ b/Kconfig @@ -1188,14 +1188,43 @@ config DEBUG_PWM_INFO endif # DEBUG_PWM config DEBUG_RTC - bool "RTC Debug Output" + bool "RTC Debug Features" default n depends on RTC ---help--- - Enable RTC driver debug SYSLOG output (disabled by default). + Enable RTC debug features. + Support for this debug option is architecture-specific and may not be available for some MCUs. +if DEBUG_RTC + +config DEBUG_RTC_ERROR + bool "RTC Error Output" + default n + depends on DEBUG_ERROR + ---help--- + Enable RTC driver error output to SYSLOG. + + Support for this debug option is architecture-specific and may not + be available for some MCUs. + +config DEBUG_RTC_WARN + bool "RTC Warnings Output" + default n + depends on DEBUG_WARN + ---help--- + Enable RTC driver warning output to SYSLOG. + +config DEBUG_RTC_INFO + bool "RTC Informational Output" + default n + depends on DEBUG_INFO + ---help--- + Enable RTC driver informational output to SYSLOG. + +endif # DEBUG_RTC + config DEBUG_SDIO bool "SDIO Debug Output" default n diff --git a/arch/arm/src/efm32/efm32_rtc_burtc.c b/arch/arm/src/efm32/efm32_rtc_burtc.c index 779c922e59..52c8811ae5 100644 --- a/arch/arm/src/efm32/efm32_rtc_burtc.c +++ b/arch/arm/src/efm32/efm32_rtc_burtc.c @@ -130,16 +130,6 @@ #define __CNT_CARRY_REG EFM32_BURTC_RET_REG(0) #define __CNT_ZERO_REG EFM32_BURTC_RET_REG(1) -#if defined CONFIG_DEBUG_FEATURES && defined CONFIG_RTC_DEBUG -# define burtcerr llerr -#else -# define burtcerr(x...) -#endif - -/************************************************************************************ - * Private Types - ************************************************************************************/ - /************************************************************************************ * Private Data ************************************************************************************/ @@ -191,7 +181,7 @@ static int efm32_rtc_burtc_interrupt(int irq, void *context) if (source & BURTC_IF_LFXOFAIL) { - burtcerr("BURTC_IF_LFXOFAIL"); + rtcerr("ERROR: BURTC_IF_LFXOFAIL"); } #ifdef CONFIG_RTC_HIRES @@ -245,7 +235,7 @@ static void efm32_rtc_burtc_init(void) regval = g_efm32_rstcause; regval2 = getreg32(EFM32_BURTC_CTRL); - burtcerr("BURTC RESETCAUSE=0x%08X BURTC_CTRL=0x%08X\n", regval, regval2); + rtcinfo("BURTC RESETCAUSE=0x%08X BURTC_CTRL=0x%08X\n", regval, regval2); if (!(regval2 & BURTC_CTRL_RSTEN) && !(regval & RMU_RSTCAUSE_BUBODREG) && @@ -262,11 +252,11 @@ static void efm32_rtc_burtc_init(void) /* restore saved base time */ - burtcerr("BURTC OK\n"); + rtcinfo("BURTC OK\n"); return; } - burtcerr("BURTC RESETED\n"); + rtcinfo("BURTC RESET\n"); /* Disable reset of BackupDomain */ @@ -358,7 +348,7 @@ static uint64_t efm32_get_burtc_tick(void) val = (uint64_t)cnt_carry*__CNT_TOP + cnt + cnt_zero; - burtcerr("Get Tick carry %u zero %u reg %u\n", cnt_carry, cnt_carry,cnt); + rtcinfo("Get Tick carry %u zero %u reg %u\n", cnt_carry, cnt_carry,cnt); return val; } @@ -449,7 +439,7 @@ int up_rtc_gettime(FAR struct timespec *tp) tp->tv_sec = val / CONFIG_RTC_FREQUENCY; tp->tv_nsec = (val % CONFIG_RTC_FREQUENCY)*(NSEC_PER_SEC/CONFIG_RTC_FREQUENCY); - burtcerr("Get RTC %u.%09u\n", tp->tv_sec, tp->tv_nsec); + rtcinfo("Get RTC %u.%09u\n", tp->tv_sec, tp->tv_nsec); return OK; } @@ -499,7 +489,7 @@ int up_rtc_settime(FAR const struct timespec *tp) cnt_carry = val / __CNT_TOP; cnt = val % __CNT_TOP; - burtcerr("Set RTC %u.%09u carry %u zero %u reg %u\n", + rtcinfo("Set RTC %u.%09u carry %u zero %u reg %u\n", tp->tv_sec, tp->tv_nsec, cnt_carry, cnt, cnt_reg); putreg32(cnt_carry, __CNT_CARRY_REG); diff --git a/arch/arm/src/lpc17xx/lpc176x_rtc.c b/arch/arm/src/lpc17xx/lpc176x_rtc.c index 1ffbbf93f4..8e04d2f2eb 100644 --- a/arch/arm/src/lpc17xx/lpc176x_rtc.c +++ b/arch/arm/src/lpc17xx/lpc176x_rtc.c @@ -72,30 +72,6 @@ # error "CONFIG_RTC_HIRES must NOT be set with this driver" #endif -#ifndef CONFIG_DEBUG_FEATURES -# undef CONFIG_DEBUG_RTC -#endif - -/* Constants ************************************************************************/ - -/* Debug ****************************************************************************/ - -#ifdef CONFIG_DEBUG_RTC -# define rtcerr err -# define rtcinfo info -# define rtcllerr llerr -# define rtcllinfo llinfo -#else -# define rtcerr(x...) -# define rtcinfo(x...) -# define rtcllerr(x...) -# define rtcllinfo(x...) -#endif - -/************************************************************************************ - * Private Types - ************************************************************************************/ - /************************************************************************************ * Private Data ************************************************************************************/ @@ -131,12 +107,12 @@ volatile bool g_rtc_enabled = false; * ************************************************************************************/ -#ifdef CONFIG_DEBUG_RTC +#ifdef CONFIG_DEBUG_RTC_INFO static void rtc_dumpregs(FAR const char *msg) { - rtcllerr("%s:\n", msg); - rtcllerr(" DOM : %08x\n", (getreg32(LPC17_RTC_DOM) & RTC_DOM_MASK)); - rtcllerr(" DOW : %08x\n", (getreg32(LPC17_RTC_DOW) & RTC_DOW_MASK)); + rtcinfo("%s:\n", msg); + rtcinfo(" DOM : %08x\n", (getreg32(LPC17_RTC_DOM) & RTC_DOM_MASK)); + rtcinfo(" DOW : %08x\n", (getreg32(LPC17_RTC_DOW) & RTC_DOW_MASK)); } #else # define rtc_dumpregs(msg) @@ -156,16 +132,16 @@ static void rtc_dumpregs(FAR const char *msg) * ************************************************************************************/ -#ifdef CONFIG_DEBUG_RTC +#ifdef CONFIG_DEBUG_RTC_INFO static void rtc_dumptime(FAR struct tm *tp, FAR const char *msg) { - rtcllerr("%s:\n", msg); - rtcllerr(" tm_sec: %08x\n", tp->tm_sec); - rtcllerr(" tm_min: %08x\n", tp->tm_min); - rtcllerr(" tm_hour: %08x\n", tp->tm_hour); - rtcllerr(" tm_mday: %08x\n", tp->tm_mday); - rtcllerr(" tm_mon: %08x\n", tp->tm_mon); - rtcllerr(" tm_year: %08x\n", tp->tm_year); + rtcinfo("%s:\n", msg); + rtcinfo(" tm_sec: %08x\n", tp->tm_sec); + rtcinfo(" tm_min: %08x\n", tp->tm_min); + rtcinfo(" tm_hour: %08x\n", tp->tm_hour); + rtcinfo(" tm_mday: %08x\n", tp->tm_mday); + rtcinfo(" tm_mon: %08x\n", tp->tm_mon); + rtcinfo(" tm_year: %08x\n", tp->tm_year); } #else # define rtc_dumptime(tp, msg) diff --git a/arch/arm/src/sam34/sam_rtc.c b/arch/arm/src/sam34/sam_rtc.c index 698a9df295..540fe3e44f 100644 --- a/arch/arm/src/sam34/sam_rtc.c +++ b/arch/arm/src/sam34/sam_rtc.c @@ -80,30 +80,6 @@ #define RTC_MAGIC 0xdeadbeef -#ifndef CONFIG_DEBUG_FEATURES -# undef CONFIG_DEBUG_RTC -#endif - -/* Constants ************************************************************************/ - -/* Debug ****************************************************************************/ - -#ifdef CONFIG_DEBUG_RTC -# define rtcerr err -# define rtcinfo info -# define rtcllerr llerr -# define rtcllinfo llinfo -#else -# define rtcerr(x...) -# define rtcinfo(x...) -# define rtcllerr(x...) -# define rtcllinfo(x...) -#endif - -/************************************************************************************ - * Private Types - ************************************************************************************/ - /************************************************************************************ * Private Data ************************************************************************************/ @@ -146,19 +122,19 @@ uint32_t g_rtt_offset = 0; * ************************************************************************************/ -#ifdef CONFIG_DEBUG_RTC +#ifdef CONFIG_DEBUG_RTC_INFO static void rtc_dumpregs(FAR const char *msg) { - rtcllerr("%s:\n", msg); - rtcllerr(" CR: %08x\n", getreg32(SAM_RTC_CR)); - rtcllerr(" MR: %08x\n", getreg32(SAM_RTC_MR)); - rtcllerr(" TIMR: %08x\n", getreg32(SAM_RTC_TIMR)); - rtcllerr(" CALR: %08x\n", getreg32(SAM_RTC_CALR)); - rtcllerr(" TIMALR: %08x\n", getreg32(SAM_RTC_TIMALR)); - rtcllerr(" CALALR: %08x\n", getreg32(SAM_RTC_CALALR)); - rtcllerr(" SR: %08x\n", getreg32(SAM_RTC_SR)); - rtcllerr(" IMR: %08x\n", getreg32(SAM_RTC_IMR)); - rtcllerr(" VER: %08x\n", getreg32(SAM_RTC_VER)); + rtcinfo("%s:\n", msg); + rtcinfo(" CR: %08x\n", getreg32(SAM_RTC_CR)); + rtcinfo(" MR: %08x\n", getreg32(SAM_RTC_MR)); + rtcinfo(" TIMR: %08x\n", getreg32(SAM_RTC_TIMR)); + rtcinfo(" CALR: %08x\n", getreg32(SAM_RTC_CALR)); + rtcinfo(" TIMALR: %08x\n", getreg32(SAM_RTC_TIMALR)); + rtcinfo(" CALALR: %08x\n", getreg32(SAM_RTC_CALALR)); + rtcinfo(" SR: %08x\n", getreg32(SAM_RTC_SR)); + rtcinfo(" IMR: %08x\n", getreg32(SAM_RTC_IMR)); + rtcinfo(" VER: %08x\n", getreg32(SAM_RTC_VER)); } #else # define rtc_dumpregs(msg) @@ -178,16 +154,16 @@ static void rtc_dumpregs(FAR const char *msg) * ************************************************************************************/ -#ifdef CONFIG_DEBUG_RTC +#ifdef CONFIG_DEBUG_RTC_INFO static void rtc_dumptime(FAR struct tm *tp, FAR const char *msg) { - rtcllerr("%s:\n", msg); - rtcllerr(" tm_sec: %08x\n", tp->tm_sec); - rtcllerr(" tm_min: %08x\n", tp->tm_min); - rtcllerr(" tm_hour: %08x\n", tp->tm_hour); - rtcllerr(" tm_mday: %08x\n", tp->tm_mday); - rtcllerr(" tm_mon: %08x\n", tp->tm_mon); - rtcllerr(" tm_year: %08x\n", tp->tm_year); + rtcinfo("%s:\n", msg); + rtcinfo(" tm_sec: %08x\n", tp->tm_sec); + rtcinfo(" tm_min: %08x\n", tp->tm_min); + rtcinfo(" tm_hour: %08x\n", tp->tm_hour); + rtcinfo(" tm_mday: %08x\n", tp->tm_mday); + rtcinfo(" tm_mon: %08x\n", tp->tm_mon); + rtcinfo(" tm_year: %08x\n", tp->tm_year); } #else # define rtc_dumptime(tp, msg) diff --git a/arch/arm/src/sama5/sam_rtc.c b/arch/arm/src/sama5/sam_rtc.c index 06fe78d4b1..16c4a4f295 100644 --- a/arch/arm/src/sama5/sam_rtc.c +++ b/arch/arm/src/sama5/sam_rtc.c @@ -77,30 +77,6 @@ #define RTC_MAGIC 0xdeadbeef -#ifndef CONFIG_DEBUG_FEATURES -# undef CONFIG_DEBUG_RTC -#endif - -/* Constants ************************************************************************/ - -/* Debug ****************************************************************************/ - -#ifdef CONFIG_DEBUG_RTC -# define rtcerr err -# define rtcinfo info -# define rtcllerr llerr -# define rtcllinfo llinfo -#else -# define rtcerr(x...) -# define rtcinfo(x...) -# define rtcllerr(x...) -# define rtcllinfo(x...) -#endif - -/************************************************************************************ - * Private Types - ************************************************************************************/ - /************************************************************************************ * Private Data ************************************************************************************/ @@ -137,19 +113,19 @@ volatile bool g_rtc_enabled = false; * ************************************************************************************/ -#ifdef CONFIG_DEBUG_RTC +#ifdef CONFIG_DEBUG_RTC_INFO static void rtc_dumpregs(FAR const char *msg) { - rtcllerr("%s:\n", msg); - rtcllerr(" CR: %08x\n", getreg32(SAM_RTC_CR)); - rtcllerr(" MR: %08x\n", getreg32(SAM_RTC_MR)); - rtcllerr(" TIMR: %08x\n", getreg32(SAM_RTC_TIMR)); - rtcllerr(" CALR: %08x\n", getreg32(SAM_RTC_CALR)); - rtcllerr(" TIMALR: %08x\n", getreg32(SAM_RTC_TIMALR)); - rtcllerr(" CALALR: %08x\n", getreg32(SAM_RTC_CALALR)); - rtcllerr(" SR: %08x\n", getreg32(SAM_RTC_SR)); - rtcllerr(" IMR: %08x\n", getreg32(SAM_RTC_IMR)); - rtcllerr(" VER: %08x\n", getreg32(SAM_RTC_VER)); + rtcinfo("%s:\n", msg); + rtcinfo(" CR: %08x\n", getreg32(SAM_RTC_CR)); + rtcinfo(" MR: %08x\n", getreg32(SAM_RTC_MR)); + rtcinfo(" TIMR: %08x\n", getreg32(SAM_RTC_TIMR)); + rtcinfo(" CALR: %08x\n", getreg32(SAM_RTC_CALR)); + rtcinfo(" TIMALR: %08x\n", getreg32(SAM_RTC_TIMALR)); + rtcinfo(" CALALR: %08x\n", getreg32(SAM_RTC_CALALR)); + rtcinfo(" SR: %08x\n", getreg32(SAM_RTC_SR)); + rtcinfo(" IMR: %08x\n", getreg32(SAM_RTC_IMR)); + rtcinfo(" VER: %08x\n", getreg32(SAM_RTC_VER)); } #else # define rtc_dumpregs(msg) @@ -169,16 +145,16 @@ static void rtc_dumpregs(FAR const char *msg) * ************************************************************************************/ -#ifdef CONFIG_DEBUG_RTC +#ifdef CONFIG_DEBUG_RTC_INFO static void rtc_dumptime(FAR struct tm *tp, FAR const char *msg) { - rtcllerr("%s:\n", msg); - rtcllerr(" tm_sec: %08x\n", tp->tm_sec); - rtcllerr(" tm_min: %08x\n", tp->tm_min); - rtcllerr(" tm_hour: %08x\n", tp->tm_hour); - rtcllerr(" tm_mday: %08x\n", tp->tm_mday); - rtcllerr(" tm_mon: %08x\n", tp->tm_mon); - rtcllerr(" tm_year: %08x\n", tp->tm_year); + rtcinfo("%s:\n", msg); + rtcinfo(" tm_sec: %08x\n", tp->tm_sec); + rtcinfo(" tm_min: %08x\n", tp->tm_min); + rtcinfo(" tm_hour: %08x\n", tp->tm_hour); + rtcinfo(" tm_mday: %08x\n", tp->tm_mday); + rtcinfo(" tm_mon: %08x\n", tp->tm_mon); + rtcinfo(" tm_year: %08x\n", tp->tm_year); } #else # define rtc_dumptime(tp, msg) diff --git a/arch/arm/src/stm32/stm32_rtcc.c b/arch/arm/src/stm32/stm32_rtcc.c index 7a55f9c46e..602ff7099d 100644 --- a/arch/arm/src/stm32/stm32_rtcc.c +++ b/arch/arm/src/stm32/stm32_rtcc.c @@ -76,10 +76,6 @@ # error "CONFIG_STM32_PWR must selected to use this driver" #endif -#ifndef CONFIG_DEBUG_FEATURES -# undef CONFIG_DEBUG_RTC -#endif - #ifdef CONFIG_STM32_STM32L15XX # if defined(CONFIG_RTC_HSECLOCK) # error "RTC with HSE clock not yet implemented for STM32L15XXX" @@ -123,24 +119,6 @@ # define RCC_XXX_RTCSEL_HSE RCC_BDCR_RTCSEL_HSE #endif -/* Debug ****************************************************************************/ - -#ifdef CONFIG_DEBUG_RTC -# define rtcerr err -# define rtcinfo info -# define rtcllerr llerr -# define rtcllinfo llinfo -#else -# define rtcerr(x...) -# define rtcinfo(x...) -# define rtcllerr(x...) -# define rtcllinfo(x...) -#endif - -/************************************************************************************ - * Private Types - ************************************************************************************/ - /************************************************************************************ * Private Data ************************************************************************************/ @@ -176,30 +154,30 @@ volatile bool g_rtc_enabled = false; * ************************************************************************************/ -#ifdef CONFIG_DEBUG_RTC +#ifdef CONFIG_DEBUG_RTC_INFO static void rtc_dumpregs(FAR const char *msg) { - rtcllerr("%s:\n", msg); - rtcllerr(" TR: %08x\n", getreg32(STM32_RTC_TR)); - rtcllerr(" DR: %08x\n", getreg32(STM32_RTC_DR)); - rtcllerr(" CR: %08x\n", getreg32(STM32_RTC_CR)); - rtcllerr(" ISR: %08x\n", getreg32(STM32_RTC_ISR)); - rtcllerr(" PRER: %08x\n", getreg32(STM32_RTC_PRER)); - rtcllerr(" WUTR: %08x\n", getreg32(STM32_RTC_WUTR)); + rtcinfo("%s:\n", msg); + rtcinfo(" TR: %08x\n", getreg32(STM32_RTC_TR)); + rtcinfo(" DR: %08x\n", getreg32(STM32_RTC_DR)); + rtcinfo(" CR: %08x\n", getreg32(STM32_RTC_CR)); + rtcinfo(" ISR: %08x\n", getreg32(STM32_RTC_ISR)); + rtcinfo(" PRER: %08x\n", getreg32(STM32_RTC_PRER)); + rtcinfo(" WUTR: %08x\n", getreg32(STM32_RTC_WUTR)); #ifndef CONFIG_STM32_STM32F30XX - rtcllerr(" CALIBR: %08x\n", getreg32(STM32_RTC_CALIBR)); + rtcinfo(" CALIBR: %08x\n", getreg32(STM32_RTC_CALIBR)); #endif - rtcllerr(" ALRMAR: %08x\n", getreg32(STM32_RTC_ALRMAR)); - rtcllerr(" ALRMBR: %08x\n", getreg32(STM32_RTC_ALRMBR)); - rtcllerr(" SHIFTR: %08x\n", getreg32(STM32_RTC_SHIFTR)); - rtcllerr(" TSTR: %08x\n", getreg32(STM32_RTC_TSTR)); - rtcllerr(" TSDR: %08x\n", getreg32(STM32_RTC_TSDR)); - rtcllerr(" TSSSR: %08x\n", getreg32(STM32_RTC_TSSSR)); - rtcllerr(" CALR: %08x\n", getreg32(STM32_RTC_CALR)); - rtcllerr(" TAFCR: %08x\n", getreg32(STM32_RTC_TAFCR)); - rtcllerr("ALRMASSR: %08x\n", getreg32(STM32_RTC_ALRMASSR)); - rtcllerr("ALRMBSSR: %08x\n", getreg32(STM32_RTC_ALRMBSSR)); - rtcllerr("MAGICREG: %08x\n", getreg32(RTC_MAGIC_REG)); + rtcinfo(" ALRMAR: %08x\n", getreg32(STM32_RTC_ALRMAR)); + rtcinfo(" ALRMBR: %08x\n", getreg32(STM32_RTC_ALRMBR)); + rtcinfo(" SHIFTR: %08x\n", getreg32(STM32_RTC_SHIFTR)); + rtcinfo(" TSTR: %08x\n", getreg32(STM32_RTC_TSTR)); + rtcinfo(" TSDR: %08x\n", getreg32(STM32_RTC_TSDR)); + rtcinfo(" TSSSR: %08x\n", getreg32(STM32_RTC_TSSSR)); + rtcinfo(" CALR: %08x\n", getreg32(STM32_RTC_CALR)); + rtcinfo(" TAFCR: %08x\n", getreg32(STM32_RTC_TAFCR)); + rtcinfo("ALRMASSR: %08x\n", getreg32(STM32_RTC_ALRMASSR)); + rtcinfo("ALRMBSSR: %08x\n", getreg32(STM32_RTC_ALRMBSSR)); + rtcinfo("MAGICREG: %08x\n", getreg32(RTC_MAGIC_REG)); } #else # define rtc_dumpregs(msg) @@ -219,16 +197,16 @@ static void rtc_dumpregs(FAR const char *msg) * ************************************************************************************/ -#ifdef CONFIG_DEBUG_RTC +#ifdef CONFIG_DEBUG_RTC_INFO static void rtc_dumptime(FAR struct tm *tp, FAR const char *msg) { - rtcllerr("%s:\n", msg); - rtcllerr(" tm_sec: %08x\n", tp->tm_sec); - rtcllerr(" tm_min: %08x\n", tp->tm_min); - rtcllerr(" tm_hour: %08x\n", tp->tm_hour); - rtcllerr(" tm_mday: %08x\n", tp->tm_mday); - rtcllerr(" tm_mon: %08x\n", tp->tm_mon); - rtcllerr(" tm_year: %08x\n", tp->tm_year); + rtcinfo("%s:\n", msg); + rtcinfo(" tm_sec: %08x\n", tp->tm_sec); + rtcinfo(" tm_min: %08x\n", tp->tm_min); + rtcinfo(" tm_hour: %08x\n", tp->tm_hour); + rtcinfo(" tm_mday: %08x\n", tp->tm_mday); + rtcinfo(" tm_mon: %08x\n", tp->tm_mon); + rtcinfo(" tm_year: %08x\n", tp->tm_year); } #else # define rtc_dumptime(tp, msg) diff --git a/arch/arm/src/stm32/stm32f40xxx_rtcc.c b/arch/arm/src/stm32/stm32f40xxx_rtcc.c index 4600ce97fa..bd0b6e45c8 100644 --- a/arch/arm/src/stm32/stm32f40xxx_rtcc.c +++ b/arch/arm/src/stm32/stm32f40xxx_rtcc.c @@ -81,10 +81,6 @@ # error "CONFIG_STM32_PWR must selected to use this driver" #endif -#ifndef CONFIG_DEBUG_FEATURES -# undef CONFIG_DEBUG_RTC -#endif - #if !defined(CONFIG_RTC_MAGIC) # define CONFIG_RTC_MAGIC (0xfacefeee) #endif @@ -131,20 +127,6 @@ #define RTC_ALRMR_DIS_DATE_MASK (RTC_ALRMR_MSK4) #define RTC_ALRMR_ENABLE (0) -/* Debug ****************************************************************************/ - -#ifdef CONFIG_DEBUG_RTC -# define rtcerr err -# define rtcinfo info -# define rtcllerr llerr -# define rtcllinfo llinfo -#else -# define rtcerr(x...) -# define rtcinfo(x...) -# define rtcllerr(x...) -# define rtcllinfo(x...) -#endif - /************************************************************************************ * Private Types ************************************************************************************/ @@ -208,36 +190,36 @@ static int rtchw_set_alrmbr(rtc_alarmreg_t alarmreg); * ************************************************************************************/ -#ifdef CONFIG_DEBUG_RTC +#ifdef CONFIG_DEBUG_RTC_INFO static void rtc_dumpregs(FAR const char *msg) { int rtc_state; - rtcllerr("%s:\n", msg); - rtcllerr(" TR: %08x\n", getreg32(STM32_RTC_TR)); - rtcllerr(" DR: %08x\n", getreg32(STM32_RTC_DR)); - rtcllerr(" CR: %08x\n", getreg32(STM32_RTC_CR)); - rtcllerr(" ISR: %08x\n", getreg32(STM32_RTC_ISR)); - rtcllerr(" PRER: %08x\n", getreg32(STM32_RTC_PRER)); - rtcllerr(" WUTR: %08x\n", getreg32(STM32_RTC_WUTR)); - rtcllerr(" ALRMAR: %08x\n", getreg32(STM32_RTC_ALRMAR)); - rtcllerr(" ALRMBR: %08x\n", getreg32(STM32_RTC_ALRMBR)); - rtcllerr(" SHIFTR: %08x\n", getreg32(STM32_RTC_SHIFTR)); - rtcllerr(" TSTR: %08x\n", getreg32(STM32_RTC_TSTR)); - rtcllerr(" TSDR: %08x\n", getreg32(STM32_RTC_TSDR)); - rtcllerr(" TSSSR: %08x\n", getreg32(STM32_RTC_TSSSR)); - rtcllerr(" CALR: %08x\n", getreg32(STM32_RTC_CALR)); - rtcllerr(" TAFCR: %08x\n", getreg32(STM32_RTC_TAFCR)); - rtcllerr("ALRMASSR: %08x\n", getreg32(STM32_RTC_ALRMASSR)); - rtcllerr("ALRMBSSR: %08x\n", getreg32(STM32_RTC_ALRMBSSR)); - rtcllerr("MAGICREG: %08x\n", getreg32(RTC_MAGIC_REG)); + rtcinfo("%s:\n", msg); + rtcinfo(" TR: %08x\n", getreg32(STM32_RTC_TR)); + rtcinfo(" DR: %08x\n", getreg32(STM32_RTC_DR)); + rtcinfo(" CR: %08x\n", getreg32(STM32_RTC_CR)); + rtcinfo(" ISR: %08x\n", getreg32(STM32_RTC_ISR)); + rtcinfo(" PRER: %08x\n", getreg32(STM32_RTC_PRER)); + rtcinfo(" WUTR: %08x\n", getreg32(STM32_RTC_WUTR)); + rtcinfo(" ALRMAR: %08x\n", getreg32(STM32_RTC_ALRMAR)); + rtcinfo(" ALRMBR: %08x\n", getreg32(STM32_RTC_ALRMBR)); + rtcinfo(" SHIFTR: %08x\n", getreg32(STM32_RTC_SHIFTR)); + rtcinfo(" TSTR: %08x\n", getreg32(STM32_RTC_TSTR)); + rtcinfo(" TSDR: %08x\n", getreg32(STM32_RTC_TSDR)); + rtcinfo(" TSSSR: %08x\n", getreg32(STM32_RTC_TSSSR)); + rtcinfo(" CALR: %08x\n", getreg32(STM32_RTC_CALR)); + rtcinfo(" TAFCR: %08x\n", getreg32(STM32_RTC_TAFCR)); + rtcinfo("ALRMASSR: %08x\n", getreg32(STM32_RTC_ALRMASSR)); + rtcinfo("ALRMBSSR: %08x\n", getreg32(STM32_RTC_ALRMBSSR)); + rtcinfo("MAGICREG: %08x\n", getreg32(RTC_MAGIC_REG)); rtc_state = ((getreg32(STM32_EXTI_RTSR) & EXTI_RTC_ALARM) ? 0x1000 : 0) | ((getreg32(STM32_EXTI_FTSR) & EXTI_RTC_ALARM) ? 0x0100 : 0) | ((getreg32(STM32_EXTI_IMR) & EXTI_RTC_ALARM) ? 0x0010 : 0) | ((getreg32(STM32_EXTI_EMR) & EXTI_RTC_ALARM) ? 0x0001 : 0); - rtcllerr("EXTI (RTSR FTSR ISR EVT): %01x\n",rtc_state); + rtcinfo("EXTI (RTSR FTSR ISR EVT): %01x\n",rtc_state); } #else # define rtc_dumpregs(msg) @@ -257,16 +239,16 @@ static void rtc_dumpregs(FAR const char *msg) * ************************************************************************************/ -#ifdef CONFIG_DEBUG_RTC +#ifdef CONFIG_DEBUG_RTC_INFO static void rtc_dumptime(FAR const struct tm *tp, FAR const char *msg) { - rtcllerr("%s:\n", msg); - rtcllerr(" tm_sec: %08x\n", tp->tm_sec); - rtcllerr(" tm_min: %08x\n", tp->tm_min); - rtcllerr(" tm_hour: %08x\n", tp->tm_hour); - rtcllerr(" tm_mday: %08x\n", tp->tm_mday); - rtcllerr(" tm_mon: %08x\n", tp->tm_mon); - rtcllerr(" tm_year: %08x\n", tp->tm_year); + rtcinfo("%s:\n", msg); + rtcinfo(" tm_sec: %08x\n", tp->tm_sec); + rtcinfo(" tm_min: %08x\n", tp->tm_min); + rtcinfo(" tm_hour: %08x\n", tp->tm_hour); + rtcinfo(" tm_mday: %08x\n", tp->tm_mday); + rtcinfo(" tm_mon: %08x\n", tp->tm_mon); + rtcinfo(" tm_year: %08x\n", tp->tm_year); } #else # define rtc_dumptime(tp, msg) diff --git a/arch/arm/src/stm32l4/stm32l4_rtcc.c b/arch/arm/src/stm32l4/stm32l4_rtcc.c index d2d055fcbd..c894fb54d8 100644 --- a/arch/arm/src/stm32l4/stm32l4_rtcc.c +++ b/arch/arm/src/stm32l4/stm32l4_rtcc.c @@ -83,10 +83,6 @@ # error "CONFIG_STM32L4_PWR must selected to use this driver" #endif -#ifndef CONFIG_DEBUG_FEATURES -# undef CONFIG_DEBUG_RTC -#endif - #if !defined(CONFIG_RTC_MAGIC) # define CONFIG_RTC_MAGIC (0xfacefeee) #endif @@ -116,20 +112,6 @@ #define RTC_ALRMR_ENABLE (0x80000000) -/* Debug ****************************************************************************/ - -#ifdef CONFIG_DEBUG_RTC -# define rtcerr err -# define rtcinfo info -# define rtcllerr llerr -# define rtcllinfo llinfo -#else -# define rtcerr(x...) -# define rtcinfo(x...) -# define rtcllerr(x...) -# define rtcllinfo(x...) -#endif - /************************************************************************************ * Private Types ************************************************************************************/ @@ -191,27 +173,27 @@ static int rtchw_set_alrmbr(rtc_alarmreg_t alarmreg); * ************************************************************************************/ -#ifdef CONFIG_DEBUG_RTC +#ifdef CONFIG_DEBUG_RTC_INFO static void rtc_dumpregs(FAR const char *msg) { - rtcllerr("%s:\n", msg); - rtcllerr(" TR: %08x\n", getreg32(STM32L4_RTC_TR)); - rtcllerr(" DR: %08x\n", getreg32(STM32L4_RTC_DR)); - rtcllerr(" CR: %08x\n", getreg32(STM32L4_RTC_CR)); - rtcllerr(" ISR: %08x\n", getreg32(STM32L4_RTC_ISR)); - rtcllerr(" PRER: %08x\n", getreg32(STM32L4_RTC_PRER)); - rtcllerr(" WUTR: %08x\n", getreg32(STM32L4_RTC_WUTR)); + rtcinfo("%s:\n", msg); + rtcinfo(" TR: %08x\n", getreg32(STM32L4_RTC_TR)); + rtcinfo(" DR: %08x\n", getreg32(STM32L4_RTC_DR)); + rtcinfo(" CR: %08x\n", getreg32(STM32L4_RTC_CR)); + rtcinfo(" ISR: %08x\n", getreg32(STM32L4_RTC_ISR)); + rtcinfo(" PRER: %08x\n", getreg32(STM32L4_RTC_PRER)); + rtcinfo(" WUTR: %08x\n", getreg32(STM32L4_RTC_WUTR)); - rtcllerr(" ALRMAR: %08x\n", getreg32(STM32L4_RTC_ALRMAR)); - rtcllerr(" ALRMBR: %08x\n", getreg32(STM32L4_RTC_ALRMBR)); - rtcllerr(" SHIFTR: %08x\n", getreg32(STM32L4_RTC_SHIFTR)); - rtcllerr(" TSTR: %08x\n", getreg32(STM32L4_RTC_TSTR)); - rtcllerr(" TSDR: %08x\n", getreg32(STM32L4_RTC_TSDR)); - rtcllerr(" TSSSR: %08x\n", getreg32(STM32L4_RTC_TSSSR)); - rtcllerr(" CALR: %08x\n", getreg32(STM32L4_RTC_CALR)); - rtcllerr(" TAMPCR: %08x\n", getreg32(STM32L4_RTC_TAMPCR)); - rtcllerr("ALRMASSR: %08x\n", getreg32(STM32L4_RTC_ALRMASSR)); - rtcllerr("ALRMBSSR: %08x\n", getreg32(STM32L4_RTC_ALRMBSSR)); + rtcinfo(" ALRMAR: %08x\n", getreg32(STM32L4_RTC_ALRMAR)); + rtcinfo(" ALRMBR: %08x\n", getreg32(STM32L4_RTC_ALRMBR)); + rtcinfo(" SHIFTR: %08x\n", getreg32(STM32L4_RTC_SHIFTR)); + rtcinfo(" TSTR: %08x\n", getreg32(STM32L4_RTC_TSTR)); + rtcinfo(" TSDR: %08x\n", getreg32(STM32L4_RTC_TSDR)); + rtcinfo(" TSSSR: %08x\n", getreg32(STM32L4_RTC_TSSSR)); + rtcinfo(" CALR: %08x\n", getreg32(STM32L4_RTC_CALR)); + rtcinfo(" TAMPCR: %08x\n", getreg32(STM32L4_RTC_TAMPCR)); + rtcinfo("ALRMASSR: %08x\n", getreg32(STM32L4_RTC_ALRMASSR)); + rtcinfo("ALRMBSSR: %08x\n", getreg32(STM32L4_RTC_ALRMBSSR)); } #else # define rtc_dumpregs(msg) @@ -231,21 +213,21 @@ static void rtc_dumpregs(FAR const char *msg) * ************************************************************************************/ -#ifdef CONFIG_DEBUG_RTC +#ifdef CONFIG_DEBUG_RTC_INFO static void rtc_dumptime(FAR const struct tm *tp, FAR const char *msg) { - rtcllerr("%s:\n", msg); + rtcinfo("%s:\n", msg); #if 0 - rtcllerr(" tm_sec: %08x\n", tp->tm_sec); - rtcllerr(" tm_min: %08x\n", tp->tm_min); - rtcllerr(" tm_hour: %08x\n", tp->tm_hour); - rtcllerr(" tm_mday: %08x\n", tp->tm_mday); - rtcllerr(" tm_mon: %08x\n", tp->tm_mon); - rtcllerr(" tm_year: %08x\n", tp->tm_year); + rtcinfo(" tm_sec: %08x\n", tp->tm_sec); + rtcinfo(" tm_min: %08x\n", tp->tm_min); + rtcinfo(" tm_hour: %08x\n", tp->tm_hour); + rtcinfo(" tm_mday: %08x\n", tp->tm_mday); + rtcinfo(" tm_mon: %08x\n", tp->tm_mon); + rtcinfo(" tm_year: %08x\n", tp->tm_year); #else - rtcllerr(" tm: %04d-%02d-%02d %02d:%02d:%02d\n", - tp->tm_year+1900, tp->tm_mon+1, tp->tm_mday, - tp->tm_hour, tp->tm_min, tp->tm_sec); + rtcinfo(" tm: %04d-%02d-%02d %02d:%02d:%02d\n", + tp->tm_year+1900, tp->tm_mon+1, tp->tm_mday, + tp->tm_hour, tp->tm_min, tp->tm_sec); #endif } #else diff --git a/drivers/timers/ds3231.c b/drivers/timers/ds3231.c index aa35fe7363..4f1e2a1c9f 100644 --- a/drivers/timers/ds3231.c +++ b/drivers/timers/ds3231.c @@ -77,24 +77,6 @@ #define DS3231_I2C_ADDRESS 0x68 -#ifndef CONFIG_DEBUG_FEATURES -# undef CONFIG_DEBUG_RTC -#endif - -/* Debug ****************************************************************************/ - -#ifdef CONFIG_DEBUG_RTC -# define rtcerr err -# define rtcinfo info -# define rtcllerr llerr -# define rtcllinfo llinfo -#else -# define rtcerr(x...) -# define rtcinfo(x...) -# define rtcllerr(x...) -# define rtcllinfo(x...) -#endif - /************************************************************************************ * Priviate Types ************************************************************************************/ @@ -140,20 +122,20 @@ static struct ds3231_dev_s g_ds3231; * ************************************************************************************/ -#if defined(CONFIG_DEBUG_RTC) && defined(CONFIG_DEBUG_INFO) +#ifdef CONFIG_DEBUG_RTC_INFO static void rtc_dumptime(FAR struct tm *tp, FAR const char *msg) { - rtcllinfo("%s:\n", msg); - rtcllinfo(" tm_sec: %08x\n", tp->tm_sec); - rtcllinfo(" tm_min: %08x\n", tp->tm_min); - rtcllinfo(" tm_hour: %08x\n", tp->tm_hour); - rtcllinfo(" tm_mday: %08x\n", tp->tm_mday); - rtcllinfo(" tm_mon: %08x\n", tp->tm_mon); - rtcllinfo(" tm_year: %08x\n", tp->tm_year); + rtcinfo("%s:\n", msg); + rtcinfo(" tm_sec: %08x\n", tp->tm_sec); + rtcinfo(" tm_min: %08x\n", tp->tm_min); + rtcinfo(" tm_hour: %08x\n", tp->tm_hour); + rtcinfo(" tm_mday: %08x\n", tp->tm_mday); + rtcinfo(" tm_mon: %08x\n", tp->tm_mon); + rtcinfo(" tm_year: %08x\n", tp->tm_year); #if defined(CONFIG_LIBC_LOCALTIME) || defined(CONFIG_TIME_EXTENDED) - rtcllinfo(" tm_wday: %08x\n", tp->tm_wday); - rtcllinfo(" tm_yday: %08x\n", tp->tm_yday); - rtcllinfo(" tm_isdst: %08x\n", tp->tm_isdst); + rtcinfo(" tm_wday: %08x\n", tp->tm_wday); + rtcinfo(" tm_yday: %08x\n", tp->tm_yday); + rtcinfo(" tm_isdst: %08x\n", tp->tm_isdst); #endif } #else diff --git a/drivers/timers/pcf85263.c b/drivers/timers/pcf85263.c index cc5ec728df..f162699f20 100644 --- a/drivers/timers/pcf85263.c +++ b/drivers/timers/pcf85263.c @@ -77,24 +77,6 @@ #define PCF85263_I2C_ADDRESS 0x51 -#ifndef CONFIG_DEBUG_FEATURES -# undef CONFIG_DEBUG_RTC -#endif - -/* Debug ****************************************************************************/ - -#ifdef CONFIG_DEBUG_RTC -# define rtcerr err -# define rtcinfo info -# define rtcllerr llerr -# define rtcllinfo llinfo -#else -# define rtcerr(x...) -# define rtcinfo(x...) -# define rtcllerr(x...) -# define rtcllinfo(x...) -#endif - /************************************************************************************ * Priviate Types ************************************************************************************/ @@ -140,20 +122,20 @@ static struct pcf85263_dev_s g_pcf85263; * ************************************************************************************/ -#if defined(CONFIG_DEBUG_RTC) && defined(CONFIG_DEBUG_INFO) +#ifdef CONFIG_DEBUG_RTC_INFO static void rtc_dumptime(FAR struct tm *tp, FAR const char *msg) { - rtcllinfo("%s:\n", msg); - rtcllinfo(" tm_sec: %08x\n", tp->tm_sec); - rtcllinfo(" tm_min: %08x\n", tp->tm_min); - rtcllinfo(" tm_hour: %08x\n", tp->tm_hour); - rtcllinfo(" tm_mday: %08x\n", tp->tm_mday); - rtcllinfo(" tm_mon: %08x\n", tp->tm_mon); - rtcllinfo(" tm_year: %08x\n", tp->tm_year); + rtcinfo("%s:\n", msg); + rtcinfo(" tm_sec: %08x\n", tp->tm_sec); + rtcinfo(" tm_min: %08x\n", tp->tm_min); + rtcinfo(" tm_hour: %08x\n", tp->tm_hour); + rtcinfo(" tm_mday: %08x\n", tp->tm_mday); + rtcinfo(" tm_mon: %08x\n", tp->tm_mon); + rtcinfo(" tm_year: %08x\n", tp->tm_year); #if defined(CONFIG_LIBC_LOCALTIME) || defined(CONFIG_TIME_EXTENDED) - rtcllinfo(" tm_wday: %08x\n", tp->tm_wday); - rtcllinfo(" tm_yday: %08x\n", tp->tm_yday); - rtcllinfo(" tm_isdst: %08x\n", tp->tm_isdst); + rtcinfo(" tm_wday: %08x\n", tp->tm_wday); + rtcinfo(" tm_yday: %08x\n", tp->tm_yday); + rtcinfo(" tm_isdst: %08x\n", tp->tm_isdst); #endif } #else diff --git a/include/debug.h b/include/debug.h index 735efb048e..9409b3b3c9 100644 --- a/include/debug.h +++ b/include/debug.h @@ -693,6 +693,30 @@ # define pwmllinfo(x...) #endif +#ifdef CONFIG_DEBUG_RTC_ERROR +# define rtcerr(format, ...) err(format, ##__VA_ARGS__) +# define rtcllerr(format, ...) llerr(format, ##__VA_ARGS__) +#else +# define rtcerr(x...) +# define rtcllerr(x...) +#endif + +#ifdef CONFIG_DEBUG_RTC_WARN +# define rtcwarn(format, ...) warn(format, ##__VA_ARGS__) +# define rtcllwarn(format, ...) llwarn(format, ##__VA_ARGS__) +#else +# define rtcwarn(x...) +# define rtcllwarn(x...) +#endif + +#ifdef CONFIG_DEBUG_RTC_INFO +# define rtcinfo(format, ...) info(format, ##__VA_ARGS__) +# define rtcllinfo(format, ...) llinfo(format, ##__VA_ARGS__) +#else +# define rtcinfo(x...) +# define rtcllinfo(x...) +#endif + #ifdef CONFIG_DEBUG_SENSORS_ERROR # define snerr(format, ...) err(format, ##__VA_ARGS__) # define snllerr(format, ...) llerr(format, ##__VA_ARGS__) @@ -1354,6 +1378,30 @@ # define pwmllinfo (void) #endif +#ifdef CONFIG_DEBUG_RTC_ERROR +# define rtcerr err +# define rtcllerr llerr +#else +# define rtcerr (void) +# define rtcllerr (void) +#endif + +#ifdef CONFIG_DEBUG_RTC_WARN +# define rtcwarn warn +# define rtcllwarn llwarn +#else +# define rtcwarn (void) +# define rtcllwarn (void) +#endif + +#ifdef CONFIG_DEBUG_RTC_INFO +# define rtcinfo info +# define rtcllinfo llinfo +#else +# define rtcinfo (void) +# define rtcllinfo (void) +#endif + #ifdef CONFIG_DEBUG_SENSORS_ERROR # define snerr err # define snllerr llerr @@ -1652,6 +1700,14 @@ # define pwminfodumpbuffer(m,b,n) #endif +#ifdef CONFIG_DEBUG_RTC +# define rtcerrdumpbuffer(m,b,n) errdumpbuffer(m,b,n) +# define rtcinfodumpbuffer(m,b,n) infodumpbuffer(m,b,n) +#else +# define rtcerrdumpbuffer(m,b,n) +# define rtcinfodumpbuffer(m,b,n) +#endif + #ifdef CONFIG_DEBUG_SENSORS # define snerrdumpbuffer(m,b,n) errdumpbuffer(m,b,n) # define sninfodumpbuffer(m,b,n) infodumpbuffer(m,b,n) From 7a9f1814a2637d197fed358d43ff51d62d24abcf Mon Sep 17 00:00:00 2001 From: Gregory Nutt Date: Thu, 16 Jun 2016 07:50:54 -0600 Subject: [PATCH 04/75] Centralize definitions associated with CONFIG_DEBUG_SDIO/MEMCARD --- Kconfig | 35 ++++++++++- arch/arm/src/lpc17xx/lpc17_sdcard.c | 98 ++++++++++++++--------------- include/debug.h | 56 +++++++++++++++++ 3 files changed, 136 insertions(+), 53 deletions(-) diff --git a/Kconfig b/Kconfig index 70c8cec584..f1fec3a7a4 100644 --- a/Kconfig +++ b/Kconfig @@ -1225,15 +1225,44 @@ config DEBUG_RTC_INFO endif # DEBUG_RTC -config DEBUG_SDIO - bool "SDIO Debug Output" +config DEBUG_MEMCARD + bool "Memory Card Driver Debug Features" default n depends on MMCSD_SDIO ---help--- - Enable SDIO driver debug SYSLOG output (disabled by default). + Enable MMC/SD memory card Driver debug features. + Support for this debug option is architecture-specific and may not be available for some MCUs. +if DEBUG_MEMCARD + +config DEBUG_MEMCARD_ERROR + bool "Memory Card Driver Error Output" + default n + depends on DEBUG_ERROR + ---help--- + Enable MMC/SD memory card driver error output to SYSLOG. + + Support for this debug option is architecture-specific and may not + be available for some MCUs. + +config DEBUG_MEMCARD_WARN + bool "Memory Card Driver Warnings Output" + default n + depends on DEBUG_WARN + ---help--- + Enable MMC/SD memory card driver warning output to SYSLOG. + +config DEBUG_MEMCARD_INFO + bool "Memory Card Driver Informational Output" + default n + depends on DEBUG_INFO + ---help--- + Enable MMC/SD memory card driver informational output to SYSLOG. + +endif # DEBUG_MEMCARD + config DEBUG_SENSORS bool "Sensor Debug Features" default n diff --git a/arch/arm/src/lpc17xx/lpc17_sdcard.c b/arch/arm/src/lpc17xx/lpc17_sdcard.c index 1143d4ca1f..6fb077c10b 100644 --- a/arch/arm/src/lpc17xx/lpc17_sdcard.c +++ b/arch/arm/src/lpc17xx/lpc17_sdcard.c @@ -93,7 +93,7 @@ * CONFIG_SDIO_WIDTH_D1_ONLY - This may be selected to force the driver * operate with only a single data line (the default is to use all * 4 SD data lines). - * CONFIG_DEBUG_SDIO - Enables some very low-level debug output + * CONFIG_DEBUG_MEMCARD_* - Enables some very low-level debug output * This also requires CONFIG_DEBUG_FS and CONFIG_DEBUG_INFO */ @@ -109,10 +109,6 @@ # error "Callback support requires CONFIG_SCHED_WORKQUEUE" #endif -#if !defined(CONFIG_DEBUG_FS) || !defined(CONFIG_DEBUG_FEATURES) -# undef CONFIG_DEBUG_SDIO -#endif - /* Friendly CLKCR bit re-definitions ****************************************/ /* Mode dependent settings. These depend on clock devisor settings that must @@ -213,7 +209,7 @@ /* Register logging support */ -#ifdef CONFIG_DEBUG_SDIO +#ifdef CONFIG_DEBUG_MEMCARD_INFO # ifdef CONFIG_SDIO_DMA # define SAMPLENDX_BEFORE_SETUP 0 # define SAMPLENDX_BEFORE_ENABLE 1 @@ -274,7 +270,7 @@ struct lpc17_dev_s /* Register logging support */ -#ifdef CONFIG_DEBUG_SDIO +#ifdef CONFIG_DEBUG_MEMCARD_INFO struct lpc17_sdcard_regs_s { uint8_t pwr; @@ -314,7 +310,7 @@ static inline uint32_t lpc17_getpwrctrl(void); /* DMA Helpers **************************************************************/ -#ifdef CONFIG_DEBUG_SDIO +#ifdef CONFIG_DEBUG_MEMCARD_INFO static void lpc17_sampleinit(void); static void lpc17_sdcard_sample(struct lpc17_sdcard_regs_s *regs); static void lpc17_sample(struct lpc17_dev_s *priv, int index); @@ -452,7 +448,7 @@ struct lpc17_dev_s g_scard_dev = /* Register logging support */ -#ifdef CONFIG_DEBUG_SDIO +#ifdef CONFIG_DEBUG_MEMCARD_INFO static struct lpc17_sampleregs_s g_sampleregs[DEBUG_NSAMPLES]; #endif @@ -529,8 +525,8 @@ static inline void lpc17_setclock(uint32_t clkcr) regval |= clkcr; putreg32(regval, LPC17_SDCARD_CLOCK); - finfo("CLKCR: %08x PWR: %08x\n", - getreg32(LPC17_SDCARD_CLOCK), getreg32(LPC17_SDCARD_PWR)); + mcinfo("CLKCR: %08x PWR: %08x\n", + getreg32(LPC17_SDCARD_CLOCK), getreg32(LPC17_SDCARD_PWR)); } /**************************************************************************** @@ -659,7 +655,7 @@ static inline uint32_t lpc17_getpwrctrl(void) * ****************************************************************************/ -#ifdef CONFIG_DEBUG_SDIO +#ifdef CONFIG_DEBUG_MEMCARD_INFO static void lpc17_sampleinit(void) { memset(g_sampleregs, 0xff, DEBUG_NSAMPLES * sizeof(struct lpc17_sampleregs_s)); @@ -674,7 +670,7 @@ static void lpc17_sampleinit(void) * ****************************************************************************/ -#ifdef CONFIG_DEBUG_SDIO +#ifdef CONFIG_DEBUG_MEMCARD_INFO static void lpc17_sdcard_sample(struct lpc17_sdcard_regs_s *regs) { regs->pwr = (uint8_t)getreg32(LPC17_SDCARD_PWR); @@ -697,7 +693,7 @@ static void lpc17_sdcard_sample(struct lpc17_sdcard_regs_s *regs) * ****************************************************************************/ -#ifdef CONFIG_DEBUG_SDIO +#ifdef CONFIG_DEBUG_MEMCARD_INFO static void lpc17_sample(struct lpc17_dev_s *priv, int index) { struct lpc17_sampleregs_s *regs = &g_sampleregs[index]; @@ -707,6 +703,7 @@ static void lpc17_sample(struct lpc17_dev_s *priv, int index) lpc17_dmasample(priv->dma, ®s->dma); } #endif + lpc17_sdcard_sample(®s->sdcard); } #endif @@ -719,19 +716,19 @@ static void lpc17_sample(struct lpc17_dev_s *priv, int index) * ****************************************************************************/ -#ifdef CONFIG_DEBUG_SDIO +#ifdef CONFIG_DEBUG_MEMCARD_INFO static void lpc17_sdcard_dump(struct lpc17_sdcard_regs_s *regs, const char *msg) { - ferr("SD Card Registers: %s\n", msg); - ferr(" POWER[%08x]: %08x\n", LPC17_SDCARD_PWR, regs->pwr); - ferr(" CLKCR[%08x]: %08x\n", LPC17_SDCARD_CLOCK, regs->clkcr); - ferr(" DCTRL[%08x]: %08x\n", LPC17_SDCARD_DCTRL, regs->dctrl); - ferr(" DTIMER[%08x]: %08x\n", LPC17_SDCARD_DTIMER, regs->dtimer); - ferr(" DLEN[%08x]: %08x\n", LPC17_SDCARD_DLEN, regs->dlen); - ferr(" DCOUNT[%08x]: %08x\n", LPC17_SDCARD_DCOUNT, regs->dcount); - ferr(" STA[%08x]: %08x\n", LPC17_SDCARD_STATUS, regs->sta); - ferr(" MASK[%08x]: %08x\n", LPC17_SDCARD_MASK0, regs->mask); - ferr("FIFOCNT[%08x]: %08x\n", LPC17_SDCARD_FIFOCNT, regs->fifocnt); + mcinfo("SD Card Registers: %s\n", msg); + mcinfo(" POWER[%08x]: %08x\n", LPC17_SDCARD_PWR, regs->pwr); + mcinfo(" CLKCR[%08x]: %08x\n", LPC17_SDCARD_CLOCK, regs->clkcr); + mcinfo(" DCTRL[%08x]: %08x\n", LPC17_SDCARD_DCTRL, regs->dctrl); + mcinfo(" DTIMER[%08x]: %08x\n", LPC17_SDCARD_DTIMER, regs->dtimer); + mcinfo(" DLEN[%08x]: %08x\n", LPC17_SDCARD_DLEN, regs->dlen); + mcinfo(" DCOUNT[%08x]: %08x\n", LPC17_SDCARD_DCOUNT, regs->dcount); + mcinfo(" STA[%08x]: %08x\n", LPC17_SDCARD_STATUS, regs->sta); + mcinfo(" MASK[%08x]: %08x\n", LPC17_SDCARD_MASK0, regs->mask); + mcinfo("FIFOCNT[%08x]: %08x\n", LPC17_SDCARD_FIFOCNT, regs->fifocnt); } #endif @@ -743,7 +740,7 @@ static void lpc17_sdcard_dump(struct lpc17_sdcard_regs_s *regs, const char *msg) * ****************************************************************************/ -#ifdef CONFIG_DEBUG_SDIO +#ifdef CONFIG_DEBUG_MEMCARD_INFO static void lpc17_dumpsample(struct lpc17_dev_s *priv, struct lpc17_sampleregs_s *regs, const char *msg) { @@ -765,7 +762,7 @@ static void lpc17_dumpsample(struct lpc17_dev_s *priv, * ****************************************************************************/ -#ifdef CONFIG_DEBUG_SDIO +#ifdef CONFIG_DEBUG_MEMCARD_INFO static void lpc17_dumpsamples(struct lpc17_dev_s *priv) { lpc17_dumpsample(priv, &g_sampleregs[SAMPLENDX_BEFORE_SETUP], "Before setup"); @@ -1480,8 +1477,8 @@ static void lpc17_reset(FAR struct sdio_dev_s *dev) lpc17_setpwrctrl(SDCARD_PWR_CTRL_ON); leave_critical_section(flags); - finfo("CLCKR: %08x POWER: %08x\n", - getreg32(LPC17_SDCARD_CLOCK), getreg32(LPC17_SDCARD_PWR)); + mcinfo("CLCKR: %08x POWER: %08x\n", + getreg32(LPC17_SDCARD_CLOCK), getreg32(LPC17_SDCARD_PWR)); } /**************************************************************************** @@ -1689,7 +1686,7 @@ static int lpc17_sendcmd(FAR struct sdio_dev_s *dev, uint32_t cmd, uint32_t arg) cmdidx = (cmd & MMCSD_CMDIDX_MASK) >> MMCSD_CMDIDX_SHIFT; regval |= cmdidx | SDCARD_CMD_CPSMEN; - finfo("cmd: %08x arg: %08x regval: %08x\n", cmd, arg, regval); + mcinfo("cmd: %08x arg: %08x regval: %08x\n", cmd, arg, regval); /* Write the SD card CMD */ @@ -1920,7 +1917,7 @@ static int lpc17_waitresponse(FAR struct sdio_dev_s *dev, uint32_t cmd) { if (--timeout <= 0) { - ferr("ERROR: Timeout cmd: %08x events: %08x STA: %08x\n", + mcerr("ERROR: Timeout cmd: %08x events: %08x STA: %08x\n", cmd, events, getreg32(LPC17_SDCARD_STATUS)); return -ETIMEDOUT; @@ -1987,7 +1984,7 @@ static int lpc17_recvshortcrc(FAR struct sdio_dev_s *dev, uint32_t cmd, uint32_t #ifdef CONFIG_DEBUG_FEATURES if (!rshort) { - ferr("ERROR: rshort=NULL\n"); + mcerr("ERROR: rshort=NULL\n"); ret = -EINVAL; } @@ -1997,7 +1994,7 @@ static int lpc17_recvshortcrc(FAR struct sdio_dev_s *dev, uint32_t cmd, uint32_t (cmd & MMCSD_RESPONSE_MASK) != MMCSD_R1B_RESPONSE && (cmd & MMCSD_RESPONSE_MASK) != MMCSD_R6_RESPONSE) { - ferr("ERROR: Wrong response CMD=%08x\n", cmd); + mcerr("ERROR: Wrong response CMD=%08x\n", cmd); ret = -EINVAL; } else @@ -2008,12 +2005,12 @@ static int lpc17_recvshortcrc(FAR struct sdio_dev_s *dev, uint32_t cmd, uint32_t regval = getreg32(LPC17_SDCARD_STATUS); if ((regval & SDCARD_STATUS_CTIMEOUT) != 0) { - ferr("ERROR: Command timeout: %08x\n", regval); + mcerr("ERROR: Command timeout: %08x\n", regval); ret = -ETIMEDOUT; } else if ((regval & SDCARD_STATUS_CCRCFAIL) != 0) { - ferr("ERROR: CRC failure: %08x\n", regval); + mcerr("ERROR: CRC failure: %08x\n", regval); ret = -EIO; } #ifdef CONFIG_DEBUG_FEATURES @@ -2024,7 +2021,7 @@ static int lpc17_recvshortcrc(FAR struct sdio_dev_s *dev, uint32_t cmd, uint32_t respcmd = getreg32(LPC17_SDCARD_RESPCMD); if ((uint8_t)(respcmd & SDCARD_RESPCMD_MASK) != (cmd & MMCSD_CMDIDX_MASK)) { - ferr("ERROR: RESCMD=%02x CMD=%08x\n", respcmd, cmd); + mcerr("ERROR: RESCMD=%02x CMD=%08x\n", respcmd, cmd); ret = -EINVAL; } } @@ -2057,7 +2054,7 @@ static int lpc17_recvlong(FAR struct sdio_dev_s *dev, uint32_t cmd, uint32_t rlo if ((cmd & MMCSD_RESPONSE_MASK) != MMCSD_R2_RESPONSE) { - ferr("ERROR: Wrong response CMD=%08x\n", cmd); + mcerr("ERROR: Wrong response CMD=%08x\n", cmd); ret = -EINVAL; } else @@ -2068,12 +2065,12 @@ static int lpc17_recvlong(FAR struct sdio_dev_s *dev, uint32_t cmd, uint32_t rlo regval = getreg32(LPC17_SDCARD_STATUS); if (regval & SDCARD_STATUS_CTIMEOUT) { - ferr("ERROR: Timeout STA: %08x\n", regval); + mcerr("ERROR: Timeout STA: %08x\n", regval); ret = -ETIMEDOUT; } else if (regval & SDCARD_STATUS_CCRCFAIL) { - ferr("ERROR: CRC fail STA: %08x\n", regval); + mcerr("ERROR: CRC fail STA: %08x\n", regval); ret = -EIO; } } @@ -2111,7 +2108,7 @@ static int lpc17_recvshort(FAR struct sdio_dev_s *dev, uint32_t cmd, uint32_t *r if ((cmd & MMCSD_RESPONSE_MASK) != MMCSD_R3_RESPONSE && (cmd & MMCSD_RESPONSE_MASK) != MMCSD_R7_RESPONSE) { - ferr("ERROR: Wrong response CMD=%08x\n", cmd); + mcerr("ERROR: Wrong response CMD=%08x\n", cmd); ret = -EINVAL; } else @@ -2124,7 +2121,7 @@ static int lpc17_recvshort(FAR struct sdio_dev_s *dev, uint32_t cmd, uint32_t *r regval = getreg32(LPC17_SDCARD_STATUS); if (regval & SDCARD_STATUS_CTIMEOUT) { - ferr("ERROR: Timeout STA: %08x\n", regval); + mcerr("ERROR: Timeout STA: %08x\n", regval); ret = -ETIMEDOUT; } } @@ -2269,7 +2266,7 @@ static sdio_eventset_t lpc17_eventwait(FAR struct sdio_dev_s *dev, 1, (uint32_t)priv); if (ret != OK) { - ferr("ERROR: wd_start failed: %d\n", ret); + mcerr("ERROR: wd_start failed: %d\n", ret); } } @@ -2341,7 +2338,7 @@ static void lpc17_callbackenable(FAR struct sdio_dev_s *dev, { struct lpc17_dev_s *priv = (struct lpc17_dev_s *)dev; - finfo("eventset: %02x\n", eventset); + mcinfo("eventset: %02x\n", eventset); DEBUGASSERT(priv != NULL); priv->cbevents = eventset; @@ -2377,7 +2374,7 @@ static int lpc17_registercallback(FAR struct sdio_dev_s *dev, /* Disable callbacks and register this callback and is argument */ - finfo("Register %p(%p)\n", callback, arg); + mcinfo("Register %p(%p)\n", callback, arg); DEBUGASSERT(priv != NULL); priv->cbevents = 0; @@ -2590,8 +2587,8 @@ static void lpc17_callback(void *arg) /* Is a callback registered? */ DEBUGASSERT(priv != NULL); - finfo("Callback %p(%p) cbevents: %02x cdstatus: %02x\n", - priv->callback, priv->cbarg, priv->cbevents, priv->cdstatus); + mcinfo("Callback %p(%p) cbevents: %02x cdstatus: %02x\n", + priv->callback, priv->cbarg, priv->cbevents, priv->cdstatus); if (priv->callback) { @@ -2635,14 +2632,14 @@ static void lpc17_callback(void *arg) { /* Yes.. queue it */ - finfo("Queuing callback to %p(%p)\n", priv->callback, priv->cbarg); + mcinfo("Queuing callback to %p(%p)\n", priv->callback, priv->cbarg); (void)work_queue(HPWORK, &priv->cbwork, (worker_t)priv->callback, priv->cbarg, 0); } else { /* No.. then just call the callback here */ - finfo("Callback to %p(%p)\n", priv->callback, priv->cbarg); + mcinfo("Callback to %p(%p)\n", priv->callback, priv->cbarg); priv->callback(priv->cbarg); } } @@ -2781,7 +2778,7 @@ void sdio_mediachange(FAR struct sdio_dev_s *dev, bool cardinslot) { priv->cdstatus &= ~SDIO_STATUS_PRESENT; } - finfo("cdstatus OLD: %02x NEW: %02x\n", cdstatus, priv->cdstatus); + mcinfo("cdstatus OLD: %02x NEW: %02x\n", cdstatus, priv->cdstatus); /* Perform any requested callback if the status has changed */ @@ -2824,7 +2821,8 @@ void sdio_wrprotect(FAR struct sdio_dev_s *dev, bool wrprotect) { priv->cdstatus &= ~SDIO_STATUS_WRPROTECTED; } - finfo("cdstatus: %02x\n", priv->cdstatus); + + mcinfo("cdstatus: %02x\n", priv->cdstatus); leave_critical_section(flags); } #endif /* CONFIG_LPC17_SDCARD */ diff --git a/include/debug.h b/include/debug.h index 9409b3b3c9..0659179eda 100644 --- a/include/debug.h +++ b/include/debug.h @@ -717,6 +717,30 @@ # define rtcllinfo(x...) #endif +#ifdef CONFIG_DEBUG_MEMCARD_ERROR +# define mcerr(format, ...) err(format, ##__VA_ARGS__) +# define mcllerr(format, ...) llerr(format, ##__VA_ARGS__) +#else +# define mcerr(x...) +# define mcllerr(x...) +#endif + +#ifdef CONFIG_DEBUG_MEMCARD_WARN +# define mcwarn(format, ...) warn(format, ##__VA_ARGS__) +# define mcllwarn(format, ...) llwarn(format, ##__VA_ARGS__) +#else +# define mcwarn(x...) +# define mcllwarn(x...) +#endif + +#ifdef CONFIG_DEBUG_MEMCARD_INFO +# define mcinfo(format, ...) info(format, ##__VA_ARGS__) +# define mcllinfo(format, ...) llinfo(format, ##__VA_ARGS__) +#else +# define mcinfo(x...) +# define mcllinfo(x...) +#endif + #ifdef CONFIG_DEBUG_SENSORS_ERROR # define snerr(format, ...) err(format, ##__VA_ARGS__) # define snllerr(format, ...) llerr(format, ##__VA_ARGS__) @@ -1402,6 +1426,30 @@ # define rtcllinfo (void) #endif +#ifdef CONFIG_DEBUG_MEMCARD_ERROR +# define mcerr err +# define mcllerr llerr +#else +# define mcerr (void) +# define mcllerr (void) +#endif + +#ifdef CONFIG_DEBUG_MEMCARD_WARN +# define mcwarn warn +# define mcllwarn llwarn +#else +# define mcwarn (void) +# define mcllwarn (void) +#endif + +#ifdef CONFIG_DEBUG_MEMCARD_INFO +# define mcinfo info +# define mcllinfo llinfo +#else +# define mcinfo (void) +# define mcllinfo (void) +#endif + #ifdef CONFIG_DEBUG_SENSORS_ERROR # define snerr err # define snllerr llerr @@ -1708,6 +1756,14 @@ # define rtcinfodumpbuffer(m,b,n) #endif +#ifdef CONFIG_DEBUG_MEMCARD +# define mcerrdumpbuffer(m,b,n) errdumpbuffer(m,b,n) +# define mcinfodumpbuffer(m,b,n) infodumpbuffer(m,b,n) +#else +# define mcerrdumpbuffer(m,b,n) +# define mcinfodumpbuffer(m,b,n) +#endif + #ifdef CONFIG_DEBUG_SENSORS # define snerrdumpbuffer(m,b,n) errdumpbuffer(m,b,n) # define sninfodumpbuffer(m,b,n) infodumpbuffer(m,b,n) From 6f08216621b0623ef6ebf7d9742fa6c0605e8e81 Mon Sep 17 00:00:00 2001 From: Gregory Nutt Date: Thu, 16 Jun 2016 08:12:38 -0600 Subject: [PATCH 05/75] Centralize definitions associated with CONFIG_DEBUG_SYSCALL --- Kconfig | 32 ++++++++++- arch/arm/src/armv6-m/up_svcall.c | 89 +++++++++++------------------- arch/arm/src/armv7-a/arm_syscall.c | 53 ++++++------------ arch/arm/src/armv7-m/up_svcall.c | 83 ++++++++++------------------ arch/arm/src/armv7-r/arm_syscall.c | 54 ++++++------------ arch/mips/src/mips32/up_swint0.c | 70 ++++++++--------------- include/debug.h | 56 +++++++++++++++++++ 7 files changed, 202 insertions(+), 235 deletions(-) diff --git a/Kconfig b/Kconfig index f1fec3a7a4..e14a7387cd 100644 --- a/Kconfig +++ b/Kconfig @@ -741,12 +741,38 @@ config DEBUG_SCHED_INFO endif # DEBUG_SCHED config DEBUG_SYSCALL - bool "SYSCALL Debug Output" + bool "SYSCALL Debug Features" default n depends on LIB_SYSCALL ---help--- - Enable very low level output related to system calls. This gives - you basically a poor man's version of strace. + Enable very low level features related to system calls. If SYSCAL + output is enabled, this gives you basically a poor man's version of + strace. + +if DEBUG_SYSCALL + +config DEBUG_SYSCALL_ERROR + bool "SYSCALL Error Output" + default n + depends on DEBUG_ERROR + ---help--- + Enable OS SYSCALL error output to SYSLOG. + +config DEBUG_SYSCALL_WARN + bool "SYSCALL Warnings Output" + default n + depends on DEBUG_WARN + ---help--- + Enable OS SYSCALL warning output to SYSLOG. + +config DEBUG_SYSCALL_INFO + bool "SYSCALL Informational Output" + default n + depends on DEBUG_INFO + ---help--- + Enable OS SYSCALL informational output to SYSLOG. + +endif # DEBUG_SYSCALL config DEBUG_WIRELESS bool "Wireless Device Debug Output" diff --git a/arch/arm/src/armv6-m/up_svcall.c b/arch/arm/src/armv6-m/up_svcall.c index a24fc12f2f..971b6d2c1e 100644 --- a/arch/arm/src/armv6-m/up_svcall.c +++ b/arch/arm/src/armv6-m/up_svcall.c @@ -55,33 +55,6 @@ #include "exc_return.h" #include "up_internal.h" -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ -/* Configuration ************************************************************/ - -/* Debug ********************************************************************/ -/* Debug output from this file may interfere with context switching! To get - * debug output you must enabled the following in your NuttX configuration: - * - * - CONFIG_DEBUG_FEATURES and CONFIG_DEBUG_SYSCALL (shows only syscalls) - * - CONFIG_DEBUG_FEATURES and CONFIG_DEBUG_SVCALL (shows everything) - */ - -#if defined(CONFIG_DEBUG_SYSCALL) || defined(CONFIG_DEBUG_SVCALL) -# define svcerr(format, ...) llerr(format, ##__VA_ARGS__) -#else -# define svcerr(x...) -#endif - -/**************************************************************************** - * Private Data - ****************************************************************************/ - -/**************************************************************************** - * Public Data - ****************************************************************************/ - /**************************************************************************** * Private Functions ****************************************************************************/ @@ -169,24 +142,24 @@ int up_svcall(int irq, FAR void *context) * and R1..R7 = variable number of arguments depending on the system call. */ -#if defined(CONFIG_DEBUG_SYSCALL) || defined(CONFIG_DEBUG_SVCALL) +#ifdef CONFIG_DEBUG_SYSCALL_INFO # ifndef CONFIG_DEBUG_SVCALL if (cmd > SYS_switch_context) # endif { - svcerr("SVCALL Entry: regs: %p cmd: %d\n", regs, cmd); - svcerr(" R0: %08x %08x %08x %08x %08x %08x %08x %08x\n", - regs[REG_R0], regs[REG_R1], regs[REG_R2], regs[REG_R3], - regs[REG_R4], regs[REG_R5], regs[REG_R6], regs[REG_R7]); - svcerr(" R8: %08x %08x %08x %08x %08x %08x %08x %08x\n", - regs[REG_R8], regs[REG_R9], regs[REG_R10], regs[REG_R11], - regs[REG_R12], regs[REG_R13], regs[REG_R14], regs[REG_R15]); + svcllinfo("SVCALL Entry: regs: %p cmd: %d\n", regs, cmd); + svcllinfo(" R0: %08x %08x %08x %08x %08x %08x %08x %08x\n", + regs[REG_R0], regs[REG_R1], regs[REG_R2], regs[REG_R3], + regs[REG_R4], regs[REG_R5], regs[REG_R6], regs[REG_R7]); + svcllinfo(" R8: %08x %08x %08x %08x %08x %08x %08x %08x\n", + regs[REG_R8], regs[REG_R9], regs[REG_R10], regs[REG_R11], + regs[REG_R12], regs[REG_R13], regs[REG_R14], regs[REG_R15]); # ifdef CONFIG_BUILD_PROTECTED - svcerr(" PSR: %08x PRIMASK: %08x EXC_RETURN: %08x\n", - regs[REG_XPSR], regs[REG_PRIMASK], regs[REG_EXC_RETURN]); + svcllinfo(" PSR: %08x PRIMASK: %08x EXC_RETURN: %08x\n", + regs[REG_XPSR], regs[REG_PRIMASK], regs[REG_EXC_RETURN]); # else - svcerr(" PSR: %08x PRIMASK: %08x\n", - regs[REG_XPSR], regs[REG_PRIMASK]); + svcllinfo(" PSR: %08x PRIMASK: %08x\n", + regs[REG_XPSR], regs[REG_PRIMASK]); # endif } #endif @@ -471,7 +444,7 @@ int up_svcall(int irq, FAR void *context) regs[REG_R0] -= CONFIG_SYS_RESERVED; #else - sllerr("ERROR: Bad SYS call: %d\n", regs[REG_R0]); + svcllerr("ERROR: Bad SYS call: %d\n", regs[REG_R0]); #endif } break; @@ -479,37 +452,37 @@ int up_svcall(int irq, FAR void *context) /* Report what happened. That might difficult in the case of a context switch */ -#if defined(CONFIG_DEBUG_SYSCALL) || defined(CONFIG_DEBUG_SVCALL) +#ifdef CONFIG_DEBUG_SYSCALL_INFO # ifndef CONFIG_DEBUG_SVCALL if (cmd > SYS_switch_context) # else if (regs != CURRENT_REGS) # endif { - svcerr("SVCall Return:\n"); - svcerr(" R0: %08x %08x %08x %08x %08x %08x %08x %08x\n", - CURRENT_REGS[REG_R0], CURRENT_REGS[REG_R1], - CURRENT_REGS[REG_R2], CURRENT_REGS[REG_R3], - CURRENT_REGS[REG_R4], CURRENT_REGS[REG_R5], - CURRENT_REGS[REG_R6], CURRENT_REGS[REG_R7]); - svcerr(" R8: %08x %08x %08x %08x %08x %08x %08x %08x\n", - CURRENT_REGS[REG_R8], CURRENT_REGS[REG_R9], - CURRENT_REGS[REG_R10], CURRENT_REGS[REG_R11], - CURRENT_REGS[REG_R12], CURRENT_REGS[REG_R13], - CURRENT_REGS[REG_R14], CURRENT_REGS[REG_R15]); + svcllinfo("SVCall Return:\n"); + svcllinfo(" R0: %08x %08x %08x %08x %08x %08x %08x %08x\n", + CURRENT_REGS[REG_R0], CURRENT_REGS[REG_R1], + CURRENT_REGS[REG_R2], CURRENT_REGS[REG_R3], + CURRENT_REGS[REG_R4], CURRENT_REGS[REG_R5], + CURRENT_REGS[REG_R6], CURRENT_REGS[REG_R7]); + svcllinfo(" R8: %08x %08x %08x %08x %08x %08x %08x %08x\n", + CURRENT_REGS[REG_R8], CURRENT_REGS[REG_R9], + CURRENT_REGS[REG_R10], CURRENT_REGS[REG_R11], + CURRENT_REGS[REG_R12], CURRENT_REGS[REG_R13], + CURRENT_REGS[REG_R14], CURRENT_REGS[REG_R15]); #ifdef CONFIG_BUILD_PROTECTED - svcerr(" PSR: %08x PRIMASK: %08x EXC_RETURN: %08x\n", - CURRENT_REGS[REG_XPSR], CURRENT_REGS[REG_PRIMASK], - CURRENT_REGS[REG_EXC_RETURN]); + svcllinfo(" PSR: %08x PRIMASK: %08x EXC_RETURN: %08x\n", + CURRENT_REGS[REG_XPSR], CURRENT_REGS[REG_PRIMASK], + CURRENT_REGS[REG_EXC_RETURN]); #else - svcerr(" PSR: %08x PRIMASK: %08x\n", - CURRENT_REGS[REG_XPSR], CURRENT_REGS[REG_PRIMASK]); + svcllinfo(" PSR: %08x PRIMASK: %08x\n", + CURRENT_REGS[REG_XPSR], CURRENT_REGS[REG_PRIMASK]); #endif } # ifdef CONFIG_DEBUG_SVCALL else { - svcerr("SVCall Return: %d\n", regs[REG_R0]); + svcllinfo("SVCall Return: %d\n", regs[REG_R0]); } # endif #endif diff --git a/arch/arm/src/armv7-a/arm_syscall.c b/arch/arm/src/armv7-a/arm_syscall.c index c9505aaadf..482345c417 100644 --- a/arch/arm/src/armv7-a/arm_syscall.c +++ b/arch/arm/src/armv7-a/arm_syscall.c @@ -54,21 +54,6 @@ #include "addrenv.h" #include "up_internal.h" -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ -/* Debug ********************************************************************/ - -#if defined(CONFIG_DEBUG_SYSCALL) -# define svcerr(format, ...) llerr(format, ##__VA_ARGS__) -# define svcwarn(format, ...) llwarn(format, ##__VA_ARGS__) -# define svcinfo(format, ...) llinfo(format, ##__VA_ARGS__) -#else -# define svcerr(x...) -# define svcwarn(x...) -# define svcinfo(x...) -#endif - /**************************************************************************** * Private Functions ****************************************************************************/ @@ -171,16 +156,14 @@ uint32_t *arm_syscall(uint32_t *regs) * and R1..R7 = variable number of arguments depending on the system call. */ -#if defined(CONFIG_DEBUG_SYSCALL) - svcinfo("SYSCALL Entry: regs: %p cmd: %d\n", regs, cmd); - svcinfo(" R0: %08x %08x %08x %08x %08x %08x %08x %08x\n", - regs[REG_R0], regs[REG_R1], regs[REG_R2], regs[REG_R3], - regs[REG_R4], regs[REG_R5], regs[REG_R6], regs[REG_R7]); - svcinfo(" R8: %08x %08x %08x %08x %08x %08x %08x %08x\n", - regs[REG_R8], regs[REG_R9], regs[REG_R10], regs[REG_R11], - regs[REG_R12], regs[REG_R13], regs[REG_R14], regs[REG_R15]); - svcinfo("CPSR: %08x\n", regs[REG_CPSR]); -#endif + svcllinfo("SYSCALL Entry: regs: %p cmd: %d\n", regs, cmd); + svcllinfo(" R0: %08x %08x %08x %08x %08x %08x %08x %08x\n", + regs[REG_R0], regs[REG_R1], regs[REG_R2], regs[REG_R3], + regs[REG_R4], regs[REG_R5], regs[REG_R6], regs[REG_R7]); + svcllinfo(" R8: %08x %08x %08x %08x %08x %08x %08x %08x\n", + regs[REG_R8], regs[REG_R9], regs[REG_R10], regs[REG_R11], + regs[REG_R12], regs[REG_R13], regs[REG_R14], regs[REG_R15]); + svcllinfo("CPSR: %08x\n", regs[REG_CPSR]); /* Handle the SVCall according to the command in R0 */ @@ -473,7 +456,7 @@ uint32_t *arm_syscall(uint32_t *regs) regs[REG_R0] -= CONFIG_SYS_RESERVED; #else - svcerr("ERROR: Bad SYS call: %d\n", regs[REG_R0]); + svcllerr("ERROR: Bad SYS call: %d\n", regs[REG_R0]); #endif #ifdef CONFIG_ARCH_KERNEL_STACK @@ -494,18 +477,16 @@ uint32_t *arm_syscall(uint32_t *regs) break; } -#if defined(CONFIG_DEBUG_SYSCALL) /* Report what happened */ - svcinfo("SYSCALL Exit: regs: %p\n", regs); - svcinfo(" R0: %08x %08x %08x %08x %08x %08x %08x %08x\n", - regs[REG_R0], regs[REG_R1], regs[REG_R2], regs[REG_R3], - regs[REG_R4], regs[REG_R5], regs[REG_R6], regs[REG_R7]); - svcinfo(" R8: %08x %08x %08x %08x %08x %08x %08x %08x\n", - regs[REG_R8], regs[REG_R9], regs[REG_R10], regs[REG_R11], - regs[REG_R12], regs[REG_R13], regs[REG_R14], regs[REG_R15]); - svcinfo("CPSR: %08x\n", regs[REG_CPSR]); -#endif + svcllinfo("SYSCALL Exit: regs: %p\n", regs); + svcllinfo(" R0: %08x %08x %08x %08x %08x %08x %08x %08x\n", + regs[REG_R0], regs[REG_R1], regs[REG_R2], regs[REG_R3], + regs[REG_R4], regs[REG_R5], regs[REG_R6], regs[REG_R7]); + svcllinfo(" R8: %08x %08x %08x %08x %08x %08x %08x %08x\n", + regs[REG_R8], regs[REG_R9], regs[REG_R10], regs[REG_R11], + regs[REG_R12], regs[REG_R13], regs[REG_R14], regs[REG_R15]); + svcllinfo("CPSR: %08x\n", regs[REG_CPSR]); /* Return the last value of curent_regs. This supports context switches * on return from the exception. That capability is only used with the diff --git a/arch/arm/src/armv7-m/up_svcall.c b/arch/arm/src/armv7-m/up_svcall.c index 70eef08054..63f229a048 100644 --- a/arch/arm/src/armv7-m/up_svcall.c +++ b/arch/arm/src/armv7-m/up_svcall.c @@ -56,33 +56,6 @@ #include "exc_return.h" #include "up_internal.h" -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ -/* Configuration ************************************************************/ - -/* Debug ********************************************************************/ -/* Debug output from this file may interfere with context switching! To get - * debug output you must enabled the following in your NuttX configuration: - * - * - CONFIG_DEBUG_FEATURES and CONFIG_DEBUG_SYSCALL (shows only syscalls) - * - CONFIG_DEBUG_FEATURES and CONFIG_DEBUG_SVCALL (shows everything) - */ - -#if defined(CONFIG_DEBUG_SYSCALL) || defined(CONFIG_DEBUG_SVCALL) -# define svcerr(format, ...) llerr(format, ##__VA_ARGS__) -#else -# define svcerr(x...) -#endif - -/**************************************************************************** - * Private Data - ****************************************************************************/ - -/**************************************************************************** - * Public Data - ****************************************************************************/ - /**************************************************************************** * Private Functions ****************************************************************************/ @@ -164,23 +137,23 @@ int up_svcall(int irq, FAR void *context) * and R1..R7 = variable number of arguments depending on the system call. */ -#if defined(CONFIG_DEBUG_SYSCALL) || defined(CONFIG_DEBUG_SVCALL) +#ifdef CONFIG_DEBUG_SYSCALL_INFO # ifndef CONFIG_DEBUG_SVCALL if (cmd > SYS_switch_context) # endif { - svcerr("SVCALL Entry: regs: %p cmd: %d\n", regs, cmd); - svcerr(" R0: %08x %08x %08x %08x %08x %08x %08x %08x\n", - regs[REG_R0], regs[REG_R1], regs[REG_R2], regs[REG_R3], - regs[REG_R4], regs[REG_R5], regs[REG_R6], regs[REG_R7]); - svcerr(" R8: %08x %08x %08x %08x %08x %08x %08x %08x\n", - regs[REG_R8], regs[REG_R9], regs[REG_R10], regs[REG_R11], - regs[REG_R12], regs[REG_R13], regs[REG_R14], regs[REG_R15]); + svcllinfo("SVCALL Entry: regs: %p cmd: %d\n", regs, cmd); + svcllinfo(" R0: %08x %08x %08x %08x %08x %08x %08x %08x\n", + regs[REG_R0], regs[REG_R1], regs[REG_R2], regs[REG_R3], + regs[REG_R4], regs[REG_R5], regs[REG_R6], regs[REG_R7]); + svcllinfo(" R8: %08x %08x %08x %08x %08x %08x %08x %08x\n", + regs[REG_R8], regs[REG_R9], regs[REG_R10], regs[REG_R11], + regs[REG_R12], regs[REG_R13], regs[REG_R14], regs[REG_R15]); # ifdef REG_EXC_RETURN - svcerr(" PSR: %08x EXC_RETURN: %08x\n", - regs[REG_XPSR], regs[REG_EXC_RETURN]); + svcllinfo(" PSR: %08x EXC_RETURN: %08x\n", + regs[REG_XPSR], regs[REG_EXC_RETURN]); # else - svcerr(" PSR: %08x\n", regs[REG_XPSR]); + svcllinfo(" PSR: %08x\n", regs[REG_XPSR]); # endif } #endif @@ -473,7 +446,7 @@ int up_svcall(int irq, FAR void *context) regs[REG_R0] -= CONFIG_SYS_RESERVED; #else - sllerr("ERROR: Bad SYS call: %d\n", regs[REG_R0]); + svcllerr("ERROR: Bad SYS call: %d\n", regs[REG_R0]); #endif } break; @@ -481,35 +454,35 @@ int up_svcall(int irq, FAR void *context) /* Report what happened. That might difficult in the case of a context switch */ -#if defined(CONFIG_DEBUG_SYSCALL) || defined(CONFIG_DEBUG_SVCALL) +#ifdef CONFIG_DEBUG_SYSCALL_INFO # ifndef CONFIG_DEBUG_SVCALL if (cmd > SYS_switch_context) # else if (regs != CURRENT_REGS) # endif { - svcerr("SVCall Return:\n"); - svcerr(" R0: %08x %08x %08x %08x %08x %08x %08x %08x\n", - CURRENT_REGS[REG_R0], CURRENT_REGS[REG_R1], - CURRENT_REGS[REG_R2], CURRENT_REGS[REG_R3], - CURRENT_REGS[REG_R4], CURRENT_REGS[REG_R5], - CURRENT_REGS[REG_R6], CURRENT_REGS[REG_R7]); - svcerr(" R8: %08x %08x %08x %08x %08x %08x %08x %08x\n", - CURRENT_REGS[REG_R8], CURRENT_REGS[REG_R9], - CURRENT_REGS[REG_R10], CURRENT_REGS[REG_R11], - CURRENT_REGS[REG_R12], CURRENT_REGS[REG_R13], - CURRENT_REGS[REG_R14], CURRENT_REGS[REG_R15]); + svcllinfo("SVCall Return:\n"); + svcllinfo(" R0: %08x %08x %08x %08x %08x %08x %08x %08x\n", + CURRENT_REGS[REG_R0], CURRENT_REGS[REG_R1], + CURRENT_REGS[REG_R2], CURRENT_REGS[REG_R3], + CURRENT_REGS[REG_R4], CURRENT_REGS[REG_R5], + CURRENT_REGS[REG_R6], CURRENT_REGS[REG_R7]); + svcllinfo(" R8: %08x %08x %08x %08x %08x %08x %08x %08x\n", + CURRENT_REGS[REG_R8], CURRENT_REGS[REG_R9], + CURRENT_REGS[REG_R10], CURRENT_REGS[REG_R11], + CURRENT_REGS[REG_R12], CURRENT_REGS[REG_R13], + CURRENT_REGS[REG_R14], CURRENT_REGS[REG_R15]); # ifdef REG_EXC_RETURN - svcerr(" PSR: %08x EXC_RETURN: %08x\n", - CURRENT_REGS[REG_XPSR], CURRENT_REGS[REG_EXC_RETURN]); + svcllinfo(" PSR: %08x EXC_RETURN: %08x\n", + CURRENT_REGS[REG_XPSR], CURRENT_REGS[REG_EXC_RETURN]); # else - svcerr(" PSR: %08x\n", CURRENT_REGS[REG_XPSR]); + svcllinfo(" PSR: %08x\n", CURRENT_REGS[REG_XPSR]); # endif } # ifdef CONFIG_DEBUG_SVCALL else { - svcerr("SVCall Return: %d\n", regs[REG_R0]); + svcllinfo("SVCall Return: %d\n", regs[REG_R0]); } # endif #endif diff --git a/arch/arm/src/armv7-r/arm_syscall.c b/arch/arm/src/armv7-r/arm_syscall.c index 28fad77f4e..c8a33f36c3 100644 --- a/arch/arm/src/armv7-r/arm_syscall.c +++ b/arch/arm/src/armv7-r/arm_syscall.c @@ -52,22 +52,6 @@ #include "svcall.h" #include "up_internal.h" -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/* Debug ********************************************************************/ - -#if defined(CONFIG_DEBUG_SYSCALL) -# define svcerr(format, ...) llerr(format, ##__VA_ARGS__) -# define svcwarn(format, ...) llwarn(format, ##__VA_ARGS__) -# define svcinfo(format, ...) llinfo(format, ##__VA_ARGS__) -#else -# define svcerr(x...) -# define svcwarn(x...) -# define svcinfo(x...) -#endif - /**************************************************************************** * Private Functions ****************************************************************************/ @@ -170,16 +154,14 @@ uint32_t *arm_syscall(uint32_t *regs) * and R1..R7 = variable number of arguments depending on the system call. */ -#if defined(CONFIG_DEBUG_SYSCALL) - svcinfo("SYSCALL Entry: regs: %p cmd: %d\n", regs, cmd); - svcinfo(" R0: %08x %08x %08x %08x %08x %08x %08x %08x\n", - regs[REG_R0], regs[REG_R1], regs[REG_R2], regs[REG_R3], - regs[REG_R4], regs[REG_R5], regs[REG_R6], regs[REG_R7]); - svcinfo(" R8: %08x %08x %08x %08x %08x %08x %08x %08x\n", - regs[REG_R8], regs[REG_R9], regs[REG_R10], regs[REG_R11], - regs[REG_R12], regs[REG_R13], regs[REG_R14], regs[REG_R15]); - svcinfo("CPSR: %08x\n", regs[REG_CPSR]); -#endif + svcllinfo("SYSCALL Entry: regs: %p cmd: %d\n", regs, cmd); + svcllinfo(" R0: %08x %08x %08x %08x %08x %08x %08x %08x\n", + regs[REG_R0], regs[REG_R1], regs[REG_R2], regs[REG_R3], + regs[REG_R4], regs[REG_R5], regs[REG_R6], regs[REG_R7]); + svcllinfo(" R8: %08x %08x %08x %08x %08x %08x %08x %08x\n", + regs[REG_R8], regs[REG_R9], regs[REG_R10], regs[REG_R11], + regs[REG_R12], regs[REG_R13], regs[REG_R14], regs[REG_R15]); + svcllinfo("CPSR: %08x\n", regs[REG_CPSR]); /* Handle the SVCall according to the command in R0 */ @@ -472,7 +454,7 @@ uint32_t *arm_syscall(uint32_t *regs) regs[REG_R0] -= CONFIG_SYS_RESERVED; #else - svcerr("ERROR: Bad SYS call: %d\n", regs[REG_R0]); + svcllerr("ERROR: Bad SYS call: %d\n", regs[REG_R0]); #endif #ifdef CONFIG_ARCH_KERNEL_STACK @@ -493,18 +475,16 @@ uint32_t *arm_syscall(uint32_t *regs) break; } -#if defined(CONFIG_DEBUG_SYSCALL) /* Report what happened */ - svcinfo("SYSCALL Exit: regs: %p\n", regs); - svcinfo(" R0: %08x %08x %08x %08x %08x %08x %08x %08x\n", - regs[REG_R0], regs[REG_R1], regs[REG_R2], regs[REG_R3], - regs[REG_R4], regs[REG_R5], regs[REG_R6], regs[REG_R7]); - svcinfo(" R8: %08x %08x %08x %08x %08x %08x %08x %08x\n", - regs[REG_R8], regs[REG_R9], regs[REG_R10], regs[REG_R11], - regs[REG_R12], regs[REG_R13], regs[REG_R14], regs[REG_R15]); - svcinfo("CPSR: %08x\n", regs[REG_CPSR]); -#endif + svcllinfo("SYSCALL Exit: regs: %p\n", regs); + svcllinfo(" R0: %08x %08x %08x %08x %08x %08x %08x %08x\n", + regs[REG_R0], regs[REG_R1], regs[REG_R2], regs[REG_R3], + regs[REG_R4], regs[REG_R5], regs[REG_R6], regs[REG_R7]); + svcllinfo(" R8: %08x %08x %08x %08x %08x %08x %08x %08x\n", + regs[REG_R8], regs[REG_R9], regs[REG_R10], regs[REG_R11], + regs[REG_R12], regs[REG_R13], regs[REG_R14], regs[REG_R15]); + svcllinfo("CPSR: %08x\n", regs[REG_CPSR]); /* Return the last value of curent_regs. This supports context switches * on return from the exception. That capability is only used with the diff --git a/arch/mips/src/mips32/up_swint0.c b/arch/mips/src/mips32/up_swint0.c index 720aaa3bce..e7e5f21d85 100644 --- a/arch/mips/src/mips32/up_swint0.c +++ b/arch/mips/src/mips32/up_swint0.c @@ -52,28 +52,6 @@ #include "up_internal.h" -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ -/* Configuration ************************************************************/ - -/* Debug ********************************************************************/ -/* Debug output from this file may interfere with context switching! To get - * debug output you must enabled the following in your NuttX configuration: - * - * CONFIG_DEBUG_FEATURES and CONFIG_DEBUG_SYSCALL - */ - -#ifdef CONFIG_DEBUG_SYSCALL -# define swierr(format, ...) llerr(format, ##__VA_ARGS__) -# define swiwarn(format, ...) llwarn(format, ##__VA_ARGS__) -# define swiinfo(format, ...) llinfo(format, ##__VA_ARGS__) -#else -# define swierr(x...) -# define swiwarn(x...) -# define swiinfo(x...) -#endif - /**************************************************************************** * Private Functions ****************************************************************************/ @@ -82,28 +60,28 @@ * Name: up_registerdump ****************************************************************************/ -#ifdef CONFIG_DEBUG_SYSCALL +#ifdef CONFIG_DEBUG_SYSCALL_INFO static void up_registerdump(const uint32_t *regs) { - swiinfo("MFLO:%08x MFHI:%08x EPC:%08x STATUS:%08x\n", - regs[REG_MFLO], regs[REG_MFHI], regs[REG_EPC], regs[REG_STATUS]); - swiinfo("AT:%08x V0:%08x V1:%08x A0:%08x A1:%08x A2:%08x A3:%08x\n", - regs[REG_AT], regs[REG_V0], regs[REG_V1], regs[REG_A0], - regs[REG_A1], regs[REG_A2], regs[REG_A3]); - swiinfo("T0:%08x T1:%08x T2:%08x T3:%08x T4:%08x T5:%08x T6:%08x T7:%08x\n", - regs[REG_T0], regs[REG_T1], regs[REG_T2], regs[REG_T3], - regs[REG_T4], regs[REG_T5], regs[REG_T6], regs[REG_T7]); - swiinfo("S0:%08x S1:%08x S2:%08x S3:%08x S4:%08x S5:%08x S6:%08x S7:%08x\n", - regs[REG_S0], regs[REG_S1], regs[REG_S2], regs[REG_S3], - regs[REG_S4], regs[REG_S5], regs[REG_S6], regs[REG_S7]); + svcllinfo("MFLO:%08x MFHI:%08x EPC:%08x STATUS:%08x\n", + regs[REG_MFLO], regs[REG_MFHI], regs[REG_EPC], regs[REG_STATUS]); + svcllinfo("AT:%08x V0:%08x V1:%08x A0:%08x A1:%08x A2:%08x A3:%08x\n", + regs[REG_AT], regs[REG_V0], regs[REG_V1], regs[REG_A0], + regs[REG_A1], regs[REG_A2], regs[REG_A3]); + svcllinfo("T0:%08x T1:%08x T2:%08x T3:%08x T4:%08x T5:%08x T6:%08x T7:%08x\n", + regs[REG_T0], regs[REG_T1], regs[REG_T2], regs[REG_T3], + regs[REG_T4], regs[REG_T5], regs[REG_T6], regs[REG_T7]); + svcllinfo("S0:%08x S1:%08x S2:%08x S3:%08x S4:%08x S5:%08x S6:%08x S7:%08x\n", + regs[REG_S0], regs[REG_S1], regs[REG_S2], regs[REG_S3], + regs[REG_S4], regs[REG_S5], regs[REG_S6], regs[REG_S7]); #ifdef MIPS32_SAVE_GP - swiinfo("T8:%08x T9:%08x GP:%08x SP:%08x FP:%08x RA:%08x\n", - regs[REG_T8], regs[REG_T9], regs[REG_GP], regs[REG_SP], - regs[REG_FP], regs[REG_RA]); + svcllinfo("T8:%08x T9:%08x GP:%08x SP:%08x FP:%08x RA:%08x\n", + regs[REG_T8], regs[REG_T9], regs[REG_GP], regs[REG_SP], + regs[REG_FP], regs[REG_RA]); #else - swiinfo("T8:%08x T9:%08x SP:%08x FP:%08x RA:%08x\n", - regs[REG_T8], regs[REG_T9], regs[REG_SP], regs[REG_FP], - regs[REG_RA]); + svcllinfo("T8:%08x T9:%08x SP:%08x FP:%08x RA:%08x\n", + regs[REG_T8], regs[REG_T9], regs[REG_SP], regs[REG_FP], + regs[REG_RA]); #endif } #else @@ -163,8 +141,8 @@ int up_swint0(int irq, FAR void *context) * arguments depending on the system call. */ -#ifdef CONFIG_DEBUG_SYSCALL - swiinfo("Entry: regs: %p cmd: %d\n", regs, regs[REG_R4]); +#ifdef CONFIG_DEBUG_SYSCALL_INFO + svcllinfo("Entry: regs: %p cmd: %d\n", regs, regs[REG_R4]); up_registerdump(regs); #endif @@ -285,7 +263,7 @@ int up_swint0(int irq, FAR void *context) g_current_regs[REG_R0] -= CONFIG_SYS_RESERVED; #else - sllerr("ERROR: Bad SYS call: %d\n", regs[REG_A0]); + svcllerr("ERROR: Bad SYS call: %d\n", regs[REG_A0]); #endif } break; @@ -293,15 +271,15 @@ int up_swint0(int irq, FAR void *context) /* Report what happened. That might difficult in the case of a context switch */ -#ifdef CONFIG_DEBUG_SYSCALL +#ifdef CONFIG_DEBUG_SYSCALL_INFO if (regs != g_current_regs) { - swiinfo("SWInt Return: Context switch!\n"); + svcllinfo("SWInt Return: Context switch!\n"); up_registerdump((const uint32_t *)g_current_regs); } else { - swiinfo("SWInt Return: %d\n", regs[REG_V0]); + svcllinfo("SWInt Return: %d\n", regs[REG_V0]); } #endif diff --git a/include/debug.h b/include/debug.h index 0659179eda..5479cd45e1 100644 --- a/include/debug.h +++ b/include/debug.h @@ -237,6 +237,30 @@ # define sllinfo(x...) #endif +#ifdef CONFIG_DEBUG_SYSCALL_ERROR +# define svcerr(format, ...) err(format, ##__VA_ARGS__) +# define svcllerr(format, ...) llerr(format, ##__VA_ARGS__) +#else +# define svcerr(x...) +# define svcllerr(x...) +#endif + +#ifdef CONFIG_DEBUG_SYSCALL_WARN +# define svcwarn(format, ...) warn(format, ##__VA_ARGS__) +# define svcllwarn(format, ...) llwarn(format, ##__VA_ARGS__) +#else +# define svcwarn(x...) +# define svcllwarn(x...) +#endif + +#ifdef CONFIG_DEBUG_SYSCALL_INFO +# define svcinfo(format, ...) info(format, ##__VA_ARGS__) +# define svcllinfo(format, ...) llinfo(format, ##__VA_ARGS__) +#else +# define svcinfo(x...) +# define svcllinfo(x...) +#endif + #ifdef CONFIG_DEBUG_PAGING_ERROR # define pgerr(format, ...) err(format, ##__VA_ARGS__) # define pgllerr(format, ...) llerr(format, ##__VA_ARGS__) @@ -946,6 +970,30 @@ # define sllinfo (void) #endif +#ifdef CONFIG_DEBUG_SYSCALL_ERROR +# define svcerr err +# define svcllerr llerr +#else +# define svcerr (void) +# define svcllerr (void) +#endif + +#ifdef CONFIG_DEBUG_SYSCALL_WARN +# define svcwarn warn +# define svcllwarn llwarn +#else +# define svcwarn (void) +# define svcllwarn (void) +#endif + +#ifdef CONFIG_DEBUG_SYSCALL_INFO +# define svcinfo info +# define svcllinfo llinfo +#else +# define svcinfo (void) +# define svcllinfo (void) +#endif + #ifdef CONFIG_DEBUG_PAGING_ERROR # define pgerr err # define pgllerr llerr @@ -1604,6 +1652,14 @@ # define sinfodumpbuffer(m,b,n) #endif +#ifdef CONFIG_DEBUG_SYSCALL +# define svcerrdumpbuffer(m,b,n) errdumpbuffer(m,b,n) +# define svcinfodumpbuffer(m,b,n) infodumpbuffer(m,b,n) +#else +# define svcerrdumpbuffer(m,b,n) +# define svcinfodumpbuffer(m,b,n) +#endif + #ifdef CONFIG_DEBUG_PAGING # define pgerrdumpbuffer(m,b,n) errdumpbuffer(m,b,n) # define pginfodumpbuffer(m,b,n) infodumpbuffer(m,b,n) From 8c76779bc0847fbed7d159e0808640a73acb5434 Mon Sep 17 00:00:00 2001 From: Gregory Nutt Date: Thu, 16 Jun 2016 08:41:21 -0600 Subject: [PATCH 06/75] Change *err() to either info() or err(ERROR:..), depending upon if an error has occurred. --- arch/arm/src/stm32f7/Kconfig | 2 +- arch/arm/src/stm32f7/stm32_dma.c | 24 +++++++------- arch/arm/src/stm32f7/stm32_dma.h | 4 +-- arch/arm/src/stm32f7/stm32_dumpgpio.c | 36 ++++++++++----------- arch/arm/src/stm32f7/stm32_ethernet.c | 30 +++++++++--------- arch/arm/src/stm32f7/stm32_i2c.c | 44 +++++++++++++------------- arch/arm/src/stm32l4/Kconfig | 6 ++-- arch/arm/src/stm32l4/stm32l4_dma.h | 6 ++-- arch/arm/src/stm32l4/stm32l4_i2c.c | 6 ++-- arch/arm/src/stm32l4/stm32l4_qspi.c | 6 ++-- arch/arm/src/stm32l4/stm32l4x6xx_dma.c | 19 ++++++----- arch/arm/src/tiva/lm3s_ethernet.c | 25 ++++++++------- arch/arm/src/tiva/tiva_adclow.c | 10 +++--- arch/arm/src/tiva/tiva_i2c.c | 12 +++---- 14 files changed, 114 insertions(+), 116 deletions(-) diff --git a/arch/arm/src/stm32f7/Kconfig b/arch/arm/src/stm32f7/Kconfig index 07ced000a6..b43c48a9dd 100644 --- a/arch/arm/src/stm32f7/Kconfig +++ b/arch/arm/src/stm32f7/Kconfig @@ -1866,7 +1866,7 @@ endchoice config STM32F7_ETHMAC_REGDEBUG bool "Register-Level Debug" default n - depends on DEBUG_FEATURES + depends on DEBUG_NET_INFO ---help--- Enable very low-level register access debug. Depends on CONFIG_DEBUG_FEATURES. diff --git a/arch/arm/src/stm32f7/stm32_dma.c b/arch/arm/src/stm32f7/stm32_dma.c index cddacbc115..7b03377bcc 100644 --- a/arch/arm/src/stm32f7/stm32_dma.c +++ b/arch/arm/src/stm32f7/stm32_dma.c @@ -606,8 +606,8 @@ void stm32_dmasetup(DMA_HANDLE handle, uint32_t paddr, uint32_t maddr, uint32_t regoffset; uint32_t regval; - dmaerr("paddr: %08x maddr: %08x ntransfers: %d scr: %08x\n", - paddr, maddr, ntransfers, scr); + dmainfo("paddr: %08x maddr: %08x ntransfers: %d scr: %08x\n", + paddr, maddr, ntransfers, scr); #ifdef CONFIG_STM32_DMACAPABLE DEBUGASSERT(stm32_dmacapable(maddr, ntransfers, scr)); @@ -1033,22 +1033,22 @@ void stm32_dmasample(DMA_HANDLE handle, struct stm32_dmaregs_s *regs) * ****************************************************************************/ -#ifdef CONFIG_DEBUG_DMA +#ifdef CONFIG_DEBUG_DMA_INFO void stm32_dmadump(DMA_HANDLE handle, const struct stm32_dmaregs_s *regs, const char *msg) { struct stm32_dma_s *dmast = (struct stm32_dma_s *)handle; uint32_t dmabase = DMA_BASE(dmast->base); - dmaerr("DMA Registers: %s\n", msg); - dmaerr(" LISR[%08x]: %08x\n", dmabase + STM32_DMA_LISR_OFFSET, regs->lisr); - dmaerr(" HISR[%08x]: %08x\n", dmabase + STM32_DMA_HISR_OFFSET, regs->hisr); - dmaerr(" SCR[%08x]: %08x\n", dmast->base + STM32_DMA_SCR_OFFSET, regs->scr); - dmaerr(" SNDTR[%08x]: %08x\n", dmast->base + STM32_DMA_SNDTR_OFFSET, regs->sndtr); - dmaerr(" SPAR[%08x]: %08x\n", dmast->base + STM32_DMA_SPAR_OFFSET, regs->spar); - dmaerr(" SM0AR[%08x]: %08x\n", dmast->base + STM32_DMA_SM0AR_OFFSET, regs->sm0ar); - dmaerr(" SM1AR[%08x]: %08x\n", dmast->base + STM32_DMA_SM1AR_OFFSET, regs->sm1ar); - dmaerr(" SFCR[%08x]: %08x\n", dmast->base + STM32_DMA_SFCR_OFFSET, regs->sfcr); + dmainfo("DMA Registers: %s\n", msg); + dmainfo(" LISR[%08x]: %08x\n", dmabase + STM32_DMA_LISR_OFFSET, regs->lisr); + dmainfo(" HISR[%08x]: %08x\n", dmabase + STM32_DMA_HISR_OFFSET, regs->hisr); + dmainfo(" SCR[%08x]: %08x\n", dmast->base + STM32_DMA_SCR_OFFSET, regs->scr); + dmainfo(" SNDTR[%08x]: %08x\n", dmast->base + STM32_DMA_SNDTR_OFFSET, regs->sndtr); + dmainfo(" SPAR[%08x]: %08x\n", dmast->base + STM32_DMA_SPAR_OFFSET, regs->spar); + dmainfo(" SM0AR[%08x]: %08x\n", dmast->base + STM32_DMA_SM0AR_OFFSET, regs->sm0ar); + dmainfo(" SM1AR[%08x]: %08x\n", dmast->base + STM32_DMA_SM1AR_OFFSET, regs->sm1ar); + dmainfo(" SFCR[%08x]: %08x\n", dmast->base + STM32_DMA_SFCR_OFFSET, regs->sfcr); } #endif diff --git a/arch/arm/src/stm32f7/stm32_dma.h b/arch/arm/src/stm32f7/stm32_dma.h index 67c9cbf4c8..f78221c949 100644 --- a/arch/arm/src/stm32f7/stm32_dma.h +++ b/arch/arm/src/stm32f7/stm32_dma.h @@ -265,7 +265,7 @@ bool stm32_dmacapable(uintptr_t maddr, uint32_t count, uint32_t ccr); * ****************************************************************************/ -#ifdef CONFIG_DEBUG_DMA +#ifdef CONFIG_DEBUG_DMA_INFO void stm32_dmasample(DMA_HANDLE handle, struct stm32_dmaregs_s *regs); #else # define stm32_dmasample(handle,regs) @@ -282,7 +282,7 @@ void stm32_dmasample(DMA_HANDLE handle, struct stm32_dmaregs_s *regs); * ****************************************************************************/ -#ifdef CONFIG_DEBUG_DMA +#ifdef CONFIG_DEBUG_DMA_INFO void stm32_dmadump(DMA_HANDLE handle, const struct stm32_dmaregs_s *regs, const char *msg); #else diff --git a/arch/arm/src/stm32f7/stm32_dumpgpio.c b/arch/arm/src/stm32f7/stm32_dumpgpio.c index a826720bbc..79210b4e8e 100644 --- a/arch/arm/src/stm32f7/stm32_dumpgpio.c +++ b/arch/arm/src/stm32f7/stm32_dumpgpio.c @@ -51,7 +51,7 @@ #include "stm32_gpio.h" #include "stm32_rcc.h" -#ifdef CONFIG_DEBUG_FEATURES +#ifdef CONFIG_DEBUG_GPIO_INFO /* Content of this file requires verification before it is used with other * families @@ -65,7 +65,6 @@ ****************************************************************************/ /* Port letters for prettier debug output */ -#ifdef CONFIG_DEBUG_FEATURES static const char g_portchar[STM32F7_NGPIO] = { #if STM32F7_NGPIO > 11 @@ -96,7 +95,6 @@ static const char g_portchar[STM32F7_NGPIO] = # error "Bad number of GPIOs" #endif }; -#endif /**************************************************************************** * Public Functions @@ -127,28 +125,28 @@ int stm32_dumpgpio(uint32_t pinset, const char *msg) DEBUGASSERT(port < STM32F7_NGPIO); - llerr("GPIO%c pinset: %08x base: %08x -- %s\n", + gpioinfo("GPIO%c pinset: %08x base: %08x -- %s\n", g_portchar[port], pinset, base, msg); if ((getreg32(STM32_RCC_AHB1ENR) & RCC_AHB1ENR_GPIOEN(port)) != 0) { - llerr(" MODE: %08x OTYPE: %04x OSPEED: %08x PUPDR: %08x\n", - getreg32(base + STM32_GPIO_MODER_OFFSET), - getreg32(base + STM32_GPIO_OTYPER_OFFSET), - getreg32(base + STM32_GPIO_OSPEED_OFFSET), - getreg32(base + STM32_GPIO_PUPDR_OFFSET)); - llerr(" IDR: %04x ODR: %04x LCKR: %05x\n", - getreg32(base + STM32_GPIO_IDR_OFFSET), - getreg32(base + STM32_GPIO_ODR_OFFSET), - getreg32(base + STM32_GPIO_LCKR_OFFSET)); - llerr(" AFRH: %08x AFRL: %08x\n", - getreg32(base + STM32_GPIO_AFRH_OFFSET), - getreg32(base + STM32_GPIO_AFRL_OFFSET)); + gpioinfo(" MODE: %08x OTYPE: %04x OSPEED: %08x PUPDR: %08x\n", + getreg32(base + STM32_GPIO_MODER_OFFSET), + getreg32(base + STM32_GPIO_OTYPER_OFFSET), + getreg32(base + STM32_GPIO_OSPEED_OFFSET), + getreg32(base + STM32_GPIO_PUPDR_OFFSET)); + gpioinfo(" IDR: %04x ODR: %04x LCKR: %05x\n", + getreg32(base + STM32_GPIO_IDR_OFFSET), + getreg32(base + STM32_GPIO_ODR_OFFSET), + getreg32(base + STM32_GPIO_LCKR_OFFSET)); + gpioinfo(" AFRH: %08x AFRL: %08x\n", + getreg32(base + STM32_GPIO_AFRH_OFFSET), + getreg32(base + STM32_GPIO_AFRL_OFFSET)); } else { - llerr(" GPIO%c not enabled: AHB1ENR: %08x\n", - g_portchar[port], getreg32(STM32_RCC_AHB1ENR)); + gpioinfo(" GPIO%c not enabled: AHB1ENR: %08x\n", + g_portchar[port], getreg32(STM32_RCC_AHB1ENR)); } leave_critical_section(flags); @@ -156,4 +154,4 @@ int stm32_dumpgpio(uint32_t pinset, const char *msg) } #endif /* CONFIG_STM32F7_STM32F74XX || CONFIG_STM32F7_STM32F75XX */ -#endif /* CONFIG_DEBUG_FEATURES */ +#endif /* CONFIG_DEBUG_GPIO_INFO */ diff --git a/arch/arm/src/stm32f7/stm32_ethernet.c b/arch/arm/src/stm32f7/stm32_ethernet.c index 4845e564d5..6129d3e75f 100644 --- a/arch/arm/src/stm32f7/stm32_ethernet.c +++ b/arch/arm/src/stm32f7/stm32_ethernet.c @@ -263,7 +263,7 @@ * enabled. */ -#ifndef CONFIG_DEBUG_FEATURES +#ifndef CONFIG_DEBUG_NET_INFO # undef CONFIG_STM32F7_ETHMAC_REGDEBUG #endif @@ -664,7 +664,7 @@ static struct stm32_ethmac_s g_stm32ethmac[STM32F7_NETHERNET]; ****************************************************************************/ /* Register operations ******************************************************/ -#if defined(CONFIG_STM32F7_ETHMAC_REGDEBUG) && defined(CONFIG_DEBUG_FEATURES) +#ifdef CONFIG_STM32F7_ETHMAC_REGDEBUG static uint32_t stm32_getreg(uint32_t addr); static void stm32_putreg(uint32_t val, uint32_t addr); static void stm32_checksetup(void); @@ -795,7 +795,7 @@ static int stm32_ethconfig(struct stm32_ethmac_s *priv); * ****************************************************************************/ -#if defined(CONFIG_STM32F7_ETHMAC_REGDEBUG) && defined(CONFIG_DEBUG_FEATURES) +#ifdef CONFIG_STM32F7_ETHMAC_REGDEBUG static uint32_t stm32_getreg(uint32_t addr) { static uint32_t prevaddr = 0; @@ -816,7 +816,7 @@ static uint32_t stm32_getreg(uint32_t addr) { if (count == 4) { - llerr("...\n"); + ninfo("...\n"); } return val; @@ -833,7 +833,7 @@ static uint32_t stm32_getreg(uint32_t addr) { /* Yes.. then show how many times the value repeated */ - llerr("[repeats %d more times]\n", count-3); + ninfo("[repeats %d more times]\n", count-3); } /* Save the new address, value, and count */ @@ -845,7 +845,7 @@ static uint32_t stm32_getreg(uint32_t addr) /* Show the register value read */ - llerr("%08x->%08x\n", addr, val); + ninfo("%08x->%08x\n", addr, val); return val; } #endif @@ -867,12 +867,12 @@ static uint32_t stm32_getreg(uint32_t addr) * ****************************************************************************/ -#if defined(CONFIG_STM32F7_ETHMAC_REGDEBUG) && defined(CONFIG_DEBUG_FEATURES) +#ifdef CONFIG_STM32F7_ETHMAC_REGDEBUG static void stm32_putreg(uint32_t val, uint32_t addr) { /* Show the register value being written */ - llerr("%08x<-%08x\n", addr, val); + ninfo("%08x<-%08x\n", addr, val); /* Write the value */ @@ -894,7 +894,7 @@ static void stm32_putreg(uint32_t val, uint32_t addr) * ****************************************************************************/ -#if defined(CONFIG_STM32F7_ETHMAC_REGDEBUG) && defined(CONFIG_DEBUG_FEATURES) +#ifdef CONFIG_STM32F7_ETHMAC_REGDEBUG static void stm32_checksetup(void) { } @@ -1589,7 +1589,7 @@ static int stm32_recvframe(struct stm32_ethmac_s *priv) if (!stm32_isfreebuffer(priv)) { - nllerr("No free buffers\n"); + nllerr("ERROR: No free buffers\n"); return -ENOMEM; } @@ -1718,7 +1718,7 @@ static int stm32_recvframe(struct stm32_ethmac_s *priv) * scanning logic, and continue scanning with the next frame. */ - nllerr("DROPPED: RX descriptor errors: %08x\n", rxdesc->rdes0); + nllwarn("WARNING: DROPPED RX descriptor errors: %08x\n", rxdesc->rdes0); stm32_freesegment(priv, rxcurr, priv->segments); } } @@ -1784,7 +1784,7 @@ static void stm32_receive(struct stm32_ethmac_s *priv) if (dev->d_len > CONFIG_NET_ETH_MTU) { - nllerr("DROPPED: Too big: %d\n", dev->d_len); + nllwarn("WARNING: DROPPED Too big: %d\n", dev->d_len); continue; } @@ -1894,7 +1894,7 @@ static void stm32_receive(struct stm32_ethmac_s *priv) else #endif { - nllerr("DROPPED: Unknown type: %04x\n", BUF->type); + nllwarn("WARNING: DROPPED Unknown type: %04x\n", BUF->type); } /* We are finished with the RX buffer. NOTE: If the buffer is @@ -2158,7 +2158,7 @@ static inline void stm32_interrupt_process(struct stm32_ethmac_s *priv) { /* Just let the user know what happened */ - nllerr("Abormal event(s): %08x\n", dmasr); + nllerr("ERROR: Abormal event(s): %08x\n", dmasr); /* Clear all pending abnormal events */ @@ -2362,7 +2362,7 @@ static void stm32_txtimeout_expiry(int argc, uint32_t arg, ...) { struct stm32_ethmac_s *priv = (struct stm32_ethmac_s *)arg; - nllerr("Timeout!\n"); + nllerr("ERROR: Timeout!\n"); #ifdef CONFIG_NET_NOINTS /* Disable further Ethernet interrupts. This will prevent some race diff --git a/arch/arm/src/stm32f7/stm32_i2c.c b/arch/arm/src/stm32f7/stm32_i2c.c index bc34aa25aa..e6fa309cd7 100644 --- a/arch/arm/src/stm32f7/stm32_i2c.c +++ b/arch/arm/src/stm32f7/stm32_i2c.c @@ -1093,7 +1093,7 @@ static void stm32_i2c_tracenew(FAR struct stm32_i2c_priv_s *priv, if (priv->tndx >= (CONFIG_I2C_NTRACE-1)) { - i2cerr("Trace table overflow\n"); + i2cerr("ERROR: Trace table overflow\n"); return; } @@ -1134,7 +1134,7 @@ static void stm32_i2c_traceevent(FAR struct stm32_i2c_priv_s *priv, if (priv->tndx >= (CONFIG_I2C_NTRACE-1)) { - i2cerr("Trace table overflow\n"); + i2cerr("ERROR: Trace table overflow\n"); return; } @@ -1362,13 +1362,13 @@ static inline void stm32_i2c_sendstart(FAR struct stm32_i2c_priv_s *priv) if ((priv->flags & I2C_M_NORESTART) || priv->dcnt > 255) { - i2cerr("RELOAD enabled: dcnt = %i msgc = %i\n", + i2cinfo("RELOAD enabled: dcnt = %i msgc = %i\n", priv->dcnt, priv->msgc); stm32_i2c_enable_reload(priv); } else { - i2cerr("RELOAD disable: dcnt = %i msgc = %i\n", + i2cinfo("RELOAD disable: dcnt = %i msgc = %i\n", priv->dcnt, priv->msgc); stm32_i2c_disable_reload(priv); } @@ -1407,7 +1407,7 @@ static inline void stm32_i2c_sendstart(FAR struct stm32_i2c_priv_s *priv) * START condition using the address and transfer direction data entered. */ - i2cerr("Sending START: dcnt=%i msgc=%i flags=0x%04x\n", + i2cinfo("Sending START: dcnt=%i msgc=%i flags=0x%04x\n", priv->dcnt, priv->msgc, priv->flags); stm32_i2c_modifyreg32(priv, STM32F7_I2C_CR2_OFFSET, 0, I2C_CR2_START); @@ -1427,7 +1427,7 @@ static inline void stm32_i2c_sendstart(FAR struct stm32_i2c_priv_s *priv) static inline void stm32_i2c_sendstop(FAR struct stm32_i2c_priv_s *priv) { - i2cerr("Sending STOP\n"); + i2cinfo("Sending STOP\n"); stm32_i2c_traceevent(priv, I2CEVENT_WRITE_STOP, 0); stm32_i2c_modifyreg32(priv, STM32F7_I2C_CR2_OFFSET, 0, I2C_CR2_STOP); @@ -1655,7 +1655,7 @@ static int stm32_i2c_isr(struct stm32_i2c_priv_s *priv) { /* Unsupported state */ - i2cerr("TXIS: UNSUPPORTED STATE DETECTED, dcnt=%i, status 0x%08x\n", + i2cerr("ERROR: TXIS Unsupported state detected, dcnt=%i, status 0x%08x\n", priv->dcnt, status); stm32_i2c_traceevent(priv, I2CEVENT_WRITE_ERROR, 0); } @@ -1741,7 +1741,7 @@ static int stm32_i2c_isr(struct stm32_i2c_priv_s *priv) stm32_i2c_traceevent(priv, I2CEVENT_READ_ERROR, 0); status = stm32_i2c_getreg(priv, STM32F7_I2C_ISR_OFFSET); - i2cerr("RXNE: UNSUPPORTED STATE DETECTED, dcnt=%i, status 0x%08x\n", + i2cerr("ERROR: RXNE Unsupported state detected, dcnt=%i, status 0x%08x\n", priv->dcnt, status); /* Set signals that will terminate ISR and wake waiting thread */ @@ -1976,7 +1976,7 @@ static int stm32_i2c_isr(struct stm32_i2c_priv_s *priv) else if (priv->dcnt == -1 && priv->msgc == 0) { status = stm32_i2c_getreg(priv, STM32F7_I2C_ISR_OFFSET); - i2cerr("EMPTY CALL: Stopping ISR: status 0x%08x\n", status); + i2cwarn("WARNING: EMPTY CALL: Stopping ISR: status 0x%08x\n", status); stm32_i2c_traceevent(priv, I2CEVENT_ISR_EMPTY_CALL, 0); } @@ -1999,7 +1999,7 @@ static int stm32_i2c_isr(struct stm32_i2c_priv_s *priv) status = stm32_i2c_getreg(priv, STM32F7_I2C_ISR_OFFSET); - i2cerr("INVALID STATE DETECTED, status 0x%08x\n", status); + i2cerr("ERROR: Invalid state detected, status 0x%08x\n", status); /* set condition to terminate ISR and wake waiting thread */ @@ -2303,16 +2303,16 @@ static int stm32_i2c_process(FAR struct i2c_master_s *dev, FAR struct i2c_msg_s /* Connection timed out */ errval = ETIMEDOUT; - i2cerr("Waitdone timed out: CR1: 0x%08x CR2: 0x%08x status: 0x%08x\n", + i2cerr("ERROR: Waitdone timed out CR1: 0x%08x CR2: 0x%08x status: 0x%08x\n", cr1, cr2,status); } else { - i2cerr("Waitdone success: CR1: 0x%08x CR2: 0x%08x status: 0x%08x\n", + i2cinfo("Waitdone success: CR1: 0x%08x CR2: 0x%08x status: 0x%08x\n", cr1, cr2,status ); } - i2cerr("priv->status: 0x%08x\n", priv->status); + i2cinfo("priv->status: 0x%08x\n", priv->status); /* Check for error status conditions */ @@ -2330,7 +2330,7 @@ static int stm32_i2c_process(FAR struct i2c_master_s *dev, FAR struct i2c_msg_s { /* Bus Error, ignore it because of errata (revision A,Z) */ - i2cerr("I2C: Bus Error\n"); + i2cerr("ERROR: I2C Bus Error\n"); /* errval = EIO; */ } @@ -2338,7 +2338,7 @@ static int stm32_i2c_process(FAR struct i2c_master_s *dev, FAR struct i2c_msg_s { /* Arbitration Lost (master mode) */ - i2cerr("I2C: Arbitration Lost\n"); + i2cerr("ERROR: I2C Arbitration Lost\n"); errval = EAGAIN; } @@ -2346,21 +2346,21 @@ static int stm32_i2c_process(FAR struct i2c_master_s *dev, FAR struct i2c_msg_s { /* Overrun/Underrun */ - i2cerr("I2C: Overrun/Underrun\n"); + i2cerr("ERROR: I2C Overrun/Underrun\n"); errval = EIO; } else if (status & I2C_INT_PECERR) { /* PEC Error in reception (SMBus Only) */ - i2cerr("I2C: PEC Error\n"); + i2cerr("ERROR: I2C PEC Error\n"); errval = EPROTO; } else if (status & I2C_INT_TIMEOUT) { /* Timeout or Tlow Error (SMBus Only) */ - i2cerr("I2C: Timeout / Tlow Error\n"); + i2cerr("ERROR: I2C Timeout / Tlow Error\n"); errval = ETIME; } else if (status & I2C_INT_NACK) @@ -2369,12 +2369,12 @@ static int stm32_i2c_process(FAR struct i2c_master_s *dev, FAR struct i2c_msg_s if (priv->astart == TRUE) { - i2cerr("I2C: Address NACK\n"); + i2cwarn("WARNING: I2C Address NACK\n"); errval = EADDRNOTAVAIL; } else { - i2cerr("I2C: Data NACK\n"); + i2cwarn("WARNING: I2C Data NACK\n"); errval = ECOMM; } } @@ -2382,7 +2382,7 @@ static int stm32_i2c_process(FAR struct i2c_master_s *dev, FAR struct i2c_msg_s { /* Unrecognized error */ - i2cerr("I2C: Unrecognized Error"); + i2cerr("ERROR: I2C Unrecognized Error"); errval = EINTR; } } @@ -2413,7 +2413,7 @@ static int stm32_i2c_process(FAR struct i2c_master_s *dev, FAR struct i2c_msg_s { if((clock_systimer() - start) > timeout) { - i2cerr("I2C: Bus busy"); + i2cerr("ERROR: I2C Bus busy"); errval = EBUSY; break; } diff --git a/arch/arm/src/stm32l4/Kconfig b/arch/arm/src/stm32l4/Kconfig index 6bc1cc9920..1724fe8124 100644 --- a/arch/arm/src/stm32l4/Kconfig +++ b/arch/arm/src/stm32l4/Kconfig @@ -333,7 +333,7 @@ config STM32L4_QSPI_DMATHRESHOLD config STM32L4_QSPI_DMADEBUG bool "QSPI DMA transfer debug" - depends on STM32L4_QSPI_DMA && DEBUG_FEATURES && DEBUG_DMA + depends on STM32L4_QSPI_DMA && DEBUG_SPI && DEBUG_DMA default n ---help--- Enable special debug instrumentation to analyze QSPI DMA data transfers. @@ -343,11 +343,11 @@ config STM32L4_QSPI_DMADEBUG config STM32L4_QSPI_REGDEBUG bool "QSPI Register level debug" - depends on DEBUG_FEATURES + depends on DEBUG_SPI_INFO default n ---help--- Output detailed register-level QSPI device debug information. - Requires also CONFIG_DEBUG_FEATURES. + Requires also CONFIG_DEBUG_SPI_INFO. endif diff --git a/arch/arm/src/stm32l4/stm32l4_dma.h b/arch/arm/src/stm32l4/stm32l4_dma.h index ee11f8655c..c5ccf60b29 100644 --- a/arch/arm/src/stm32l4/stm32l4_dma.h +++ b/arch/arm/src/stm32l4/stm32l4_dma.h @@ -90,7 +90,7 @@ typedef FAR void *DMA_HANDLE; typedef void (*dma_callback_t)(DMA_HANDLE handle, uint8_t status, void *arg); -#ifdef CONFIG_DEBUG_DMA +#ifdef CONFIG_DEBUG_DMA_INFO struct stm32l4_dmaregs_s { uint32_t isr; /* Interrupt Status Register; each channel gets 4 bits */ @@ -267,7 +267,7 @@ bool stm32l4_dmacapable(uintptr_t maddr, uint32_t count, uint32_t ccr); * ****************************************************************************/ -#ifdef CONFIG_DEBUG_DMA +#ifdef CONFIG_DEBUG_DMA_INFO void stm32l4_dmasample(DMA_HANDLE handle, struct stm32l4_dmaregs_s *regs); #else # define stm32l4_dmasample(handle,regs) @@ -284,7 +284,7 @@ void stm32l4_dmasample(DMA_HANDLE handle, struct stm32l4_dmaregs_s *regs); * ****************************************************************************/ -#ifdef CONFIG_DEBUG_DMA +#ifdef CONFIG_DEBUG_DMA_INFO void stm32l4_dmadump(DMA_HANDLE handle, const struct stm32l4_dmaregs_s *regs, const char *msg); #else diff --git a/arch/arm/src/stm32l4/stm32l4_i2c.c b/arch/arm/src/stm32l4/stm32l4_i2c.c index 63b0f5b048..ce6c91b677 100644 --- a/arch/arm/src/stm32l4/stm32l4_i2c.c +++ b/arch/arm/src/stm32l4/stm32l4_i2c.c @@ -910,7 +910,7 @@ static void stm32l4_i2c_tracenew(FAR struct stm32l4_i2c_priv_s *priv, if (priv->tndx >= (CONFIG_I2C_NTRACE-1)) { - i2cerr("Trace table overflow\n"); + i2cerr("ERROR: Trace table overflow\n"); return; } @@ -951,7 +951,7 @@ static void stm32l4_i2c_traceevent(FAR struct stm32l4_i2c_priv_s *priv, if (priv->tndx >= (CONFIG_I2C_NTRACE-1)) { - i2cerr("Trace table overflow\n"); + i2cerr("ERROR: Trace table overflow\n"); return; } @@ -1722,7 +1722,7 @@ static int stm32l4_i2c_transfer(FAR struct i2c_master_s *dev, FAR struct i2c_msg status = stm32l4_i2c_getstatus(priv); ret = -ETIMEDOUT; - i2cerr("Timed out: CR1: %08x status: %08x\n", + i2cerr("ERROR: Timed out: CR1: %08x status: %08x\n", stm32l4_i2c_getreg32(priv, STM32L4_I2C_CR1_OFFSET), status); /* "Note: When the STOP, START or PEC bit is set, the software must diff --git a/arch/arm/src/stm32l4/stm32l4_qspi.c b/arch/arm/src/stm32l4/stm32l4_qspi.c index 14053a598f..1fe106a083 100644 --- a/arch/arm/src/stm32l4/stm32l4_qspi.c +++ b/arch/arm/src/stm32l4/stm32l4_qspi.c @@ -405,7 +405,7 @@ static bool qspi_checkreg(struct stm32l4_qspidev_s *priv, bool wr, uint32_t valu { /* Yes... show how many times we did it */ - llerr("...[Repeats %d times]...\n", priv->ntimes); + spillinfo("...[Repeats %d times]...\n", priv->ntimes); } /* Save information about the new access */ @@ -439,7 +439,7 @@ static inline uint32_t qspi_getreg(struct stm32l4_qspidev_s *priv, #ifdef CONFIG_STM32L4_QSPI_REGDEBUG if (qspi_checkreg(priv, false, value, address)) { - llerr("%08x->%08x\n", address, value); + spillinfo("%08x->%08x\n", address, value); } #endif @@ -462,7 +462,7 @@ static inline void qspi_putreg(struct stm32l4_qspidev_s *priv, uint32_t value, #ifdef CONFIG_STM32L4_QSPI_REGDEBUG if (qspi_checkreg(priv, true, value, address)) { - llerr("%08x<-%08x\n", address, value); + spillinfo("%08x<-%08x\n", address, value); } #endif diff --git a/arch/arm/src/stm32l4/stm32l4x6xx_dma.c b/arch/arm/src/stm32l4/stm32l4x6xx_dma.c index e854d32261..e05173d82c 100644 --- a/arch/arm/src/stm32l4/stm32l4x6xx_dma.c +++ b/arch/arm/src/stm32l4/stm32l4x6xx_dma.c @@ -727,7 +727,7 @@ bool stm32l4_dmacapable(uint32_t maddr, uint32_t count, uint32_t ccr) * ****************************************************************************/ -#ifdef CONFIG_DEBUG_DMA +#ifdef CONFIG_DEBUG_DMA_INFO void stm32l4_dmasample(DMA_HANDLE handle, struct stm32l4_dmaregs_s *regs) { struct stm32l4_dma_s *dmach = (struct stm32l4_dma_s *)handle; @@ -755,20 +755,19 @@ void stm32l4_dmasample(DMA_HANDLE handle, struct stm32l4_dmaregs_s *regs) * ****************************************************************************/ -#ifdef CONFIG_DEBUG_DMA +#ifdef CONFIG_DEBUG_DMA_INFO void stm32l4_dmadump(DMA_HANDLE handle, const struct stm32l4_dmaregs_s *regs, const char *msg) { struct stm32l4_dma_s *dmach = (struct stm32l4_dma_s *)handle; uint32_t dmabase = DMA_BASE(dmach->base); - dmaerr("DMA Registers: %s\n", msg); - dmaerr(" ISR[%08x]: %08x\n", dmabase + STM32L4_DMA_ISR_OFFSET, regs->isr); - dmaerr(" CSELR[%08x]: %08x\n", dmabase + STM32L4_DMA_CSELR_OFFSET, regs->cselr); - dmaerr(" CCR[%08x]: %08x\n", dmach->base + STM32L4_DMACHAN_CCR_OFFSET, regs->ccr); - dmaerr(" CNDTR[%08x]: %08x\n", dmach->base + STM32L4_DMACHAN_CNDTR_OFFSET, regs->cndtr); - dmaerr(" CPAR[%08x]: %08x\n", dmach->base + STM32L4_DMACHAN_CPAR_OFFSET, regs->cpar); - dmaerr(" CMAR[%08x]: %08x\n", dmach->base + STM32L4_DMACHAN_CMAR_OFFSET, regs->cmar); + dmainfo("DMA Registers: %s\n", msg); + dmainfo(" ISR[%08x]: %08x\n", dmabase + STM32L4_DMA_ISR_OFFSET, regs->isr); + dmainfo(" CSELR[%08x]: %08x\n", dmabase + STM32L4_DMA_CSELR_OFFSET, regs->cselr); + dmainfo(" CCR[%08x]: %08x\n", dmach->base + STM32L4_DMACHAN_CCR_OFFSET, regs->ccr); + dmainfo(" CNDTR[%08x]: %08x\n", dmach->base + STM32L4_DMACHAN_CNDTR_OFFSET, regs->cndtr); + dmainfo(" CPAR[%08x]: %08x\n", dmach->base + STM32L4_DMACHAN_CPAR_OFFSET, regs->cpar); + dmainfo(" CMAR[%08x]: %08x\n", dmach->base + STM32L4_DMACHAN_CMAR_OFFSET, regs->cmar); } #endif - diff --git a/arch/arm/src/tiva/lm3s_ethernet.c b/arch/arm/src/tiva/lm3s_ethernet.c index bc22d7439d..e5e242c624 100644 --- a/arch/arm/src/tiva/lm3s_ethernet.c +++ b/arch/arm/src/tiva/lm3s_ethernet.c @@ -686,7 +686,7 @@ static void tiva_receive(struct tiva_driver_s *priv) /* We will have to drop this packet */ - nllerr("Bad packet size dropped (%d)\n", pktlen); + nllwarn("WARNING: "Bad packet size dropped (%d)\n", pktlen); NETDEV_RXERRORS(&priv->ld_dev); /* The number of bytes and words left to read is pktlen - 4 (including, @@ -867,7 +867,8 @@ static void tiva_receive(struct tiva_driver_s *priv) else #endif { - nllerr("Unsupported packet type dropped (%02x)\n", htons(ETHBUF->type)); + nllwarn("WARNING: Unsupported packet type dropped (%02x)\n", + htons(ETHBUF->type)); NETDEV_RXDROPPED(&priv->ld_dev); } } @@ -1024,7 +1025,7 @@ static void tiva_txtimeout(int argc, uint32_t arg, ...) /* Increment statistics */ - nllerr("Tx timeout\n"); + nllerr("ERROR: Tx timeout\n"); NETDEV_TXTIMEOUTS(&priv->ld_dev); /* Then reset the hardware */ @@ -1104,9 +1105,9 @@ static int tiva_ifup(struct net_driver_s *dev) uint32_t div; uint16_t phyreg; - nllerr("Bringing up: %d.%d.%d.%d\n", - dev->d_ipaddr & 0xff, (dev->d_ipaddr >> 8) & 0xff, - (dev->d_ipaddr >> 16) & 0xff, dev->d_ipaddr >> 24); + nllinfo("Bringing up: %d.%d.%d.%d\n", + dev->d_ipaddr & 0xff, (dev->d_ipaddr >> 8) & 0xff, + (dev->d_ipaddr >> 16) & 0xff, dev->d_ipaddr >> 24); /* Enable and reset the Ethernet controller */ @@ -1168,13 +1169,13 @@ static int tiva_ifup(struct net_driver_s *dev) * set */ - nllerr("Waiting for link\n"); + nllinfo("Waiting for link\n"); do { phyreg = tiva_phyread(priv, MII_MSR); } while ((phyreg & MII_MSR_LINKSTATUS) == 0); - nllerr("Link established\n"); + nllinfo("Link established\n"); /* Reset the receive FIFO */ @@ -1258,9 +1259,9 @@ static int tiva_ifdown(struct net_driver_s *dev) irqstate_t flags; uint32_t regval; - nllerr("Taking down: %d.%d.%d.%d\n", - dev->d_ipaddr & 0xff, (dev->d_ipaddr >> 8) & 0xff, - (dev->d_ipaddr >> 16) & 0xff, dev->d_ipaddr >> 24); + nllinfo("Taking down: %d.%d.%d.%d\n", + dev->d_ipaddr & 0xff, (dev->d_ipaddr >> 8) & 0xff, + (dev->d_ipaddr >> 16) & 0xff, dev->d_ipaddr >> 24); /* Cancel the TX poll timer and TX timeout timers */ @@ -1455,7 +1456,7 @@ static inline int tiva_ethinitialize(int intf) /* Check if the Ethernet module is present */ - nerr("Setting up eth%d\n", intf); + ninfo("Setting up eth%d\n", intf); #if TIVA_NETHCONTROLLERS > 1 # error "This debug check only works with one interface" diff --git a/arch/arm/src/tiva/tiva_adclow.c b/arch/arm/src/tiva/tiva_adclow.c index 809cb65b3b..e2e20b9196 100644 --- a/arch/arm/src/tiva/tiva_adclow.c +++ b/arch/arm/src/tiva/tiva_adclow.c @@ -686,7 +686,7 @@ static void tiva_adc_read(void *arg) * and should cause a full system stop. */ - allerr("PANIC!!! Invalid ADC device number given %d\n", sse->adc); + allerr("ERROR: Invalid ADC device number given %d\n", sse->adc); PANIC(); return; } @@ -879,8 +879,8 @@ int tiva_adc_initialize(const char *devpath, struct tiva_adc_cfg_s *cfg, adc = tiva_adc_struct_init(cfg); if (adc == NULL) { - aerr("Invalid ADC device number: expected=%d actual=%d\n", - 0, cfg->adc); + aerr("ERROR: Invalid ADC device number: expected=%d actual=%d\n", + 0, cfg->adc); return -ENODEV; } @@ -889,7 +889,7 @@ int tiva_adc_initialize(const char *devpath, struct tiva_adc_cfg_s *cfg, if (tiva_adc_enable(adc->devno, true) < 0) { aerr("ERROR: failure to power ADC peripheral (devno=%d)\n", - cfg->adc); + cfg->adc); return ret; } @@ -926,7 +926,7 @@ int tiva_adc_initialize(const char *devpath, struct tiva_adc_cfg_s *cfg, if (ret < 0) { aerr("ERROR: Failed to register %s to character driver: %d\n", - devpath, ret); + devpath, ret); return ret; } diff --git a/arch/arm/src/tiva/tiva_i2c.c b/arch/arm/src/tiva/tiva_i2c.c index f3e47ac795..1d0127aa04 100644 --- a/arch/arm/src/tiva/tiva_i2c.c +++ b/arch/arm/src/tiva/tiva_i2c.c @@ -959,7 +959,7 @@ static void tiva_i2c_tracenew(struct tiva_i2c_priv_s *priv, uint32_t status) if (priv->tndx >= (CONFIG_I2C_NTRACE-1)) { - i2cerr("I2C%d: ERROR: Trace table overflow\n", priv->config->devno); + i2cerr("ERROR: I2C%d trace table overflow\n", priv->config->devno); return; } @@ -1008,7 +1008,7 @@ static void tiva_i2c_traceevent(struct tiva_i2c_priv_s *priv, if (priv->tndx >= (CONFIG_I2C_NTRACE-1)) { - i2cerr("I2C%d: ERROR: Trace table overflow\n", priv->config->devno); + i2cerr("ERROR: I2C%d trace table overflow\n", priv->config->devno); return; } @@ -1907,7 +1907,7 @@ static int tiva_i2c_transfer(struct i2c_master_s *dev, struct i2c_msg_s *msgv, if (tiva_i2c_sem_waitdone(priv) < 0) { - i2cerr("I2C%d: ERROR: Timed out\n", priv->config->devno); + i2cerr("ERROR: I2C%d timed out\n", priv->config->devno); ret = -ETIMEDOUT; } #if 0 /* I2CM_CS_CLKTO */ @@ -1916,7 +1916,7 @@ static int tiva_i2c_transfer(struct i2c_master_s *dev, struct i2c_msg_s *msgv, else if ((priv->mstatus & (I2CM_CS_ERROR | I2CM_CS_ARBLST)) != 0) #endif { - i2cerr("I2C%d: ERROR: I2C error status: %08x\n", + i2cerr("ERROR: I2C%d I2C error status: %08x\n", priv->config->devno, priv->mstatus); if ((priv->mstatus & I2CM_CS_ARBLST) != 0) @@ -1963,7 +1963,7 @@ static int tiva_i2c_transfer(struct i2c_master_s *dev, struct i2c_msg_s *msgv, * other bits are valid. */ - i2cerr("I2C%d: ERROR: I2C still busy: %08x\n", + i2cerr("ERROR: I2C%d I2C still busy: %08x\n", priv->config->devno, regval); /* Reset and reinitialize the I2C hardware */ @@ -2212,7 +2212,7 @@ struct i2c_master_s *tiva_i2cbus_initialize(int port) #endif default: - i2cerr("I2C%d: ERROR: Not supported\n", port); + i2cerr("ERROR: I2C%d not supported\n", port); return NULL; } From f9652812e261f729f9fe7fbcff91da0a05d1920b Mon Sep 17 00:00:00 2001 From: Gregory Nutt Date: Thu, 16 Jun 2016 09:38:16 -0600 Subject: [PATCH 07/75] Change *err() to either info() or err(ERROR:..), depending upon if an error has occurred. --- arch/arm/src/stm32/Kconfig | 6 +- arch/arm/src/stm32/stm32_adc.c | 18 +-- arch/arm/src/stm32/stm32_bbsram.c | 22 +-- arch/arm/src/stm32/stm32_dac.c | 12 +- arch/arm/src/stm32/stm32_dma2d.c | 136 ++++++++--------- arch/arm/src/stm32/stm32_eth.c | 74 ++++----- arch/arm/src/stm32/stm32_i2c.c | 6 +- arch/arm/src/stm32/stm32_i2c_alt.c | 25 ++-- arch/arm/src/stm32/stm32_iwdg.c | 22 +-- arch/arm/src/stm32/stm32_ltdc.c | 206 ++++++++++++++------------ arch/arm/src/stm32/stm32_otgfsdev.c | 30 ++-- arch/arm/src/stm32/stm32_otgfshost.c | 6 +- arch/arm/src/stm32/stm32_otghsdev.c | 28 ++-- arch/arm/src/stm32/stm32_otghshost.c | 6 +- arch/arm/src/stm32/stm32_pwm.c | 12 +- arch/arm/src/stm32/stm32_qencoder.c | 6 +- arch/arm/src/stm32/stm32_rtcc.c | 10 +- arch/arm/src/stm32/stm32_sdio.c | 95 ++++++------ arch/arm/src/stm32/stm32_usbdev.c | 75 +++++----- arch/arm/src/stm32/stm32_wwdg.c | 20 ++- arch/arm/src/stm32/stm32f20xxx_dma.c | 4 +- arch/arm/src/stm32/stm32f30xxx_i2c.c | 6 +- arch/arm/src/stm32/stm32f40xxx_dma.c | 4 +- arch/arm/src/stm32/stm32f40xxx_rtcc.c | 10 +- arch/arm/src/stm32f7/stm32_gpio.h | 2 +- 25 files changed, 439 insertions(+), 402 deletions(-) diff --git a/arch/arm/src/stm32/Kconfig b/arch/arm/src/stm32/Kconfig index c1e277fc2b..13d8af2384 100644 --- a/arch/arm/src/stm32/Kconfig +++ b/arch/arm/src/stm32/Kconfig @@ -6215,7 +6215,7 @@ endchoice config STM32_ETHMAC_REGDEBUG bool "Register-Level Debug" default n - depends on DEBUG_FEATURES + depends on DEBUG_NET_INFO ---help--- Enable very low-level register access debug. Depends on CONFIG_DEBUG_FEATURES. @@ -6305,14 +6305,14 @@ menu "USB Host Debug Configuration" config STM32_USBHOST_REGDEBUG bool "Register-Level Debug" default n - depends on USBHOST && (STM32_OTGFS || STM32_OTGHS) + depends on USBHOST && DEBUG_USB_INFO && (STM32_OTGFS || STM32_OTGHS) ---help--- Enable very low-level register access debug. config STM32_USBHOST_PKTDUMP bool "Packet Dump Debug" default n - depends on USBHOST && (STM32_OTGFS || STM32_OTGHS) + depends on USBHOST && DEBUG_USB_INFO && (STM32_OTGFS || STM32_OTGHS) ---help--- Dump all incoming and outgoing USB packets. diff --git a/arch/arm/src/stm32/stm32_adc.c b/arch/arm/src/stm32/stm32_adc.c index d730923a22..3b541dde8a 100644 --- a/arch/arm/src/stm32/stm32_adc.c +++ b/arch/arm/src/stm32/stm32_adc.c @@ -906,7 +906,7 @@ static int adc_timinit(FAR struct stm32_dev_s *priv) if (prescaler < 1) { - aerr("WARNING: Prescaler underflowed.\n"); + awarn("WARNING: Prescaler underflowed.\n"); prescaler = 1; } @@ -914,7 +914,7 @@ static int adc_timinit(FAR struct stm32_dev_s *priv) else if (prescaler > 65536) { - aerr("WARNING: Prescaler overflowed.\n"); + awarn("WARNING: Prescaler overflowed.\n"); prescaler = 65536; } @@ -923,12 +923,12 @@ static int adc_timinit(FAR struct stm32_dev_s *priv) reload = timclk / priv->freq; if (reload < 1) { - aerr("WARNING: Reload value underflowed.\n"); + awarn("WARNING: Reload value underflowed.\n"); reload = 1; } else if (reload > 65535) { - aerr("WARNING: Reload value overflowed.\n"); + awarn("WARNING: Reload value overflowed.\n"); reload = 65535; } @@ -1070,7 +1070,7 @@ static int adc_timinit(FAR struct stm32_dev_s *priv) break; default: - aerr("No such trigger: %d\n", priv->trigger); + aerr("ERROR: No such trigger: %d\n", priv->trigger); return -EINVAL; } @@ -2002,7 +2002,7 @@ static void adc_reset(FAR struct adc_dev_s *dev) ret = adc_timinit(priv); if (ret < 0) { - aerr("adc_timinit failed: %d\n", ret); + aerr("ERROR: adc_timinit failed: %d\n", ret); } } #ifndef CONFIG_ADC_NO_STARTUP_CONV @@ -2718,12 +2718,12 @@ static int adc_interrupt(FAR struct adc_dev_s *dev) if ((regval & ADC_ISR_AWD) != 0) { - allerr("WARNING: Analog Watchdog, Value converted out of range!\n"); + allwarn("WARNING: Analog Watchdog, Value converted out of range!\n"); } if ((regval & ADC_ISR_OVR) != 0) { - allerr("WARNING: Overrun has occurred!\n"); + allwarn("WARNING: Overrun has occurred!\n"); } /* EOC: End of conversion */ @@ -3012,7 +3012,7 @@ struct adc_dev_s *stm32_adcinitialize(int intf, FAR const uint8_t *chanlist, break; #endif default: - aerr("No ADC interface defined\n"); + aerr("ERROR: No ADC interface defined\n"); return NULL; } diff --git a/arch/arm/src/stm32/stm32_bbsram.c b/arch/arm/src/stm32/stm32_bbsram.c index 0266f6bedd..e2ca52eee4 100644 --- a/arch/arm/src/stm32/stm32_bbsram.c +++ b/arch/arm/src/stm32/stm32_bbsram.c @@ -75,6 +75,10 @@ #define MAX_OPENCNT (255) /* Limit of uint8_t */ +#ifndef CONFIG_DEBUG_INFO +# undef CONFIG_BBSRAM_DEBUG +#endif + #if defined(CONFIG_BBSRAM_DEBUG) # define BBSRAM_DEBUG_READ() stm32_bbsram_rd() # define BBSRAM_DUMP(p,s) stm32_bbsram_dump(p,s) @@ -183,15 +187,15 @@ static void stm32_bbsram_rd(void) static void stm32_bbsram_dump(FAR struct bbsramfh_s *bbf, char *op) { BBSRAM_DEBUG_READ(); - llerr("%s:\n", op); - llerr(" File Address:0x%8x\n", bbf); - llerr(" crc:0x%8x\n", bbf->crc); - llerr(" fileno:%d\n", (int) bbf->fileno); - llerr(" dirty:%d\n", (int) bbf->dirty); - llerr(" length:%d\n", (int) bbf->len); - llerr(" time:%ld:%ld\n", bbf->lastwrite.tv_sec, bbf->lastwrite.tv_nsec); - llerr(" data: 0x%2x 0x%2x 0x%2x 0x%2x 0x%2x\n", - bbf->data[0], bbf->data[1], bbf->data[2], bbf->data[3], bbf->data[4]); + info("%s:\n", op); + info(" File Address:0x%8x\n", bbf); + info(" crc:0x%8x\n", bbf->crc); + info(" fileno:%d\n", (int) bbf->fileno); + info(" dirty:%d\n", (int) bbf->dirty); + info(" length:%d\n", (int) bbf->len); + info(" time:%ld:%ld\n", bbf->lastwrite.tv_sec, bbf->lastwrite.tv_nsec); + info(" data: 0x%2x 0x%2x 0x%2x 0x%2x 0x%2x\n", + bbf->data[0], bbf->data[1], bbf->data[2], bbf->data[3], bbf->data[4]); } #endif diff --git a/arch/arm/src/stm32/stm32_dac.c b/arch/arm/src/stm32/stm32_dac.c index a2cfcea92f..528faf1786 100644 --- a/arch/arm/src/stm32/stm32_dac.c +++ b/arch/arm/src/stm32/stm32_dac.c @@ -852,7 +852,7 @@ static int dac_timinit(FAR struct stm32_chan_s *chan) break; #endif default: - aerr("Could not enable timer\n"); + aerr("ERROR: Could not enable timer\n"); break; } @@ -1016,7 +1016,7 @@ static int dac_chaninit(FAR struct stm32_chan_s *chan) chan->dma = stm32_dmachannel(chan->dmachan); if (!chan->dma) { - aerr("Failed to allocate a DMA channel\n"); + aerr("ERROR: Failed to allocate a DMA channel\n"); return -EBUSY; } @@ -1025,7 +1025,7 @@ static int dac_chaninit(FAR struct stm32_chan_s *chan) ret = dac_timinit(chan); if (ret < 0) { - aerr("Failed to initialize the DMA timer: %d\n", ret); + aerr("ERROR: Failed to initialize the DMA timer: %d\n", ret); return ret; } } @@ -1128,7 +1128,7 @@ FAR struct dac_dev_s *stm32_dacinitialize(int intf) else #endif { - aerr("No such DAC interface: %d\n", intf); + aerr("ERROR: No such DAC interface: %d\n", intf); errno = ENODEV; return NULL; } @@ -1138,7 +1138,7 @@ FAR struct dac_dev_s *stm32_dacinitialize(int intf) ret = dac_blockinit(); if (ret < 0) { - aerr("Failed to initialize the DAC block: %d\n", ret); + aerr("ERROR: Failed to initialize the DAC block: %d\n", ret); errno = -ret; return NULL; } @@ -1149,7 +1149,7 @@ FAR struct dac_dev_s *stm32_dacinitialize(int intf) ret = dac_chaninit(chan); if (ret < 0) { - aerr("Failed to initialize DAC channel %d: %d\n", intf, ret); + aerr("ERROR: Failed to initialize DAC channel %d: %d\n", intf, ret); errno = -ret; return NULL; } diff --git a/arch/arm/src/stm32/stm32_dma2d.c b/arch/arm/src/stm32/stm32_dma2d.c index 06325fe28d..5e5740e27b 100644 --- a/arch/arm/src/stm32/stm32_dma2d.c +++ b/arch/arm/src/stm32/stm32_dma2d.c @@ -137,8 +137,8 @@ /* Debug option */ #ifdef CONFIG_STM32_DMA2D_REGDEBUG -# define regerr err -# define reginfo info +# define regerr lcderr +# define reginfo lcdinfo #else # define regerr(x...) # define reginfo(x...) @@ -408,7 +408,7 @@ static void stm32_dma2d_control(uint32_t setbits, uint32_t clrbits) { uint32_t cr; - ginfo("setbits=%08x, clrbits=%08x\n", setbits, clrbits); + lcdinfo("setbits=%08x, clrbits=%08x\n", setbits, clrbits); cr = getreg32(STM32_DMA2D_CR); cr &= ~clrbits; @@ -469,7 +469,7 @@ static int stm32_dma2dirq(int irq, void *context) if (ret != OK) { - err("sem_post() failed\n"); + lcderr("ERROR: sem_post() failed\n"); return ret; } } @@ -512,7 +512,7 @@ static int stm32_dma2d_waitforirq(void) if (ret != OK) { - err("sem_wait() failed\n"); + lcderr("ERROR: sem_wait() failed\n"); return ret; } } @@ -632,7 +632,7 @@ static uint32_t stm32_dma2d_memaddress(FAR const struct stm32_dma2d_s *layer, offset = xpos * DMA2D_PF_BYPP(layer->pinfo.bpp) + layer->pinfo.stride * ypos; - ginfo("%p\n", ((uint32_t) pinfo->fbmem) + offset); + lcdinfo("%p\n", ((uint32_t) pinfo->fbmem) + offset); return ((uint32_t) pinfo->fbmem) + offset; } @@ -655,7 +655,7 @@ static fb_coord_t stm32_dma2d_lineoffset(FAR const struct stm32_dma2d_s *layer, { /* offset at the end of each line in the context to the area layer */ - ginfo("%d\n", layer->vinfo.xres - area->xres); + lcdinfo("%d\n", layer->vinfo.xres - area->xres); return layer->vinfo.xres - area->xres; } @@ -677,7 +677,7 @@ static fb_coord_t stm32_dma2d_lineoffset(FAR const struct stm32_dma2d_s *layer, static int stm32_dma2d_pixelformat(uint8_t fmt, uint8_t *fmtmap) { - ginfo("fmt=%d, fmtmap=%p\n", fmt, fmtmap); + lcdinfo("fmt=%d, fmtmap=%p\n", fmt, fmtmap); /* Map to the controller known format * @@ -711,7 +711,7 @@ static int stm32_dma2d_pixelformat(uint8_t fmt, uint8_t *fmtmap) break; #endif default: - gerr("ERROR: Returning EINVAL\n"); + lcderr("ERROR: Returning EINVAL\n"); return -EINVAL; } @@ -736,7 +736,7 @@ static int stm32_dma2d_pixelformat(uint8_t fmt, uint8_t *fmtmap) static int stm32_dma2d_bpp(uint8_t fmt, uint8_t *bpp) { - ginfo("fmt=%d, bpp=%p\n", fmt, bpp); + lcdinfo("fmt=%d, bpp=%p\n", fmt, bpp); switch (fmt) { @@ -756,7 +756,7 @@ static int stm32_dma2d_bpp(uint8_t fmt, uint8_t *bpp) break; #endif default: - gerr("ERROR: Returning EINVAL\n"); + lcderr("ERROR: Returning EINVAL\n"); return -EINVAL; } @@ -937,7 +937,7 @@ static void stm32_dma2d_linit(FAR struct stm32_dma2d_s *layer, { FAR struct dma2d_layer_s *priv = &layer->dma2d; - ginfo("layer=%p, lid=%d, fmt=%02x\n", layer, lid, fmt); + lcdinfo("layer=%p, lid=%d, fmt=%02x\n", layer, lid, fmt); /* initialize the layer interface */ @@ -985,8 +985,8 @@ static void stm32_dma2d_lfifo(FAR const struct stm32_dma2d_s *layer, int lid, fb_coord_t xpos, fb_coord_t ypos, FAR const struct ltdc_area_s *area) { - ginfo("layer=%p, lid=%d, xpos=%d, ypos=%d, area=%p\n", - layer, lid, xpos, ypos, area); + lcdinfo("layer=%p, lid=%d, xpos=%d, ypos=%d, area=%p\n", + layer, lid, xpos, ypos, area); putreg32(stm32_dma2d_memaddress(layer, xpos, ypos), stm32_mar_layer_t[lid]); putreg32(stm32_dma2d_lineoffset(layer, area), stm32_or_layer_t[lid]); @@ -1006,7 +1006,7 @@ static void stm32_dma2d_lfifo(FAR const struct stm32_dma2d_s *layer, int lid, static void stm32_dma2d_lcolor(FAR const struct stm32_dma2d_s *layer, int lid, uint32_t color) { - ginfo("layer=%p, lid=%d, color=%08x\n", layer, lid, color); + lcdinfo("layer=%p, lid=%d, color=%08x\n", layer, lid, color); putreg32(color, stm32_color_layer_t[lid]); } @@ -1027,7 +1027,7 @@ static void stm32_dma2d_llnr(FAR struct stm32_dma2d_s *layer, { uint32_t nlrreg; - ginfo("pixel per line: %d, number of lines: %d\n", area->xres, area->yres); + lcdinfo("pixel per line: %d, number of lines: %d\n", area->xres, area->yres); nlrreg = getreg32(STM32_DMA2D_NLR); nlrreg = (DMA2D_NLR_PL(area->xres) | DMA2D_NLR_NL(area->yres)); @@ -1047,7 +1047,7 @@ static void stm32_dma2d_llnr(FAR struct stm32_dma2d_s *layer, static int stm32_dma2d_loutpfc(FAR const struct stm32_dma2d_s *layer) { - ginfo("layer=%p\n", layer); + lcdinfo("layer=%p\n", layer); /* CLUT format isn't supported by the dma2d controller */ @@ -1055,8 +1055,8 @@ static int stm32_dma2d_loutpfc(FAR const struct stm32_dma2d_s *layer) { /* Destination layer doesn't support CLUT output */ - gerr("ERROR: Returning ENOSYS, " - "output to layer with CLUT format not supported.\n"); + lcderr("ERROR: Returning ENOSYS, " + "output to layer with CLUT format not supported.\n"); return -ENOSYS; } @@ -1083,7 +1083,7 @@ static void stm32_dma2d_lpfc(FAR const struct stm32_dma2d_s *layer, { uint32_t pfccrreg; - ginfo("layer=%p, lid=%d, blendmode=%08x\n", layer, lid, blendmode); + lcdinfo("layer=%p, lid=%d, blendmode=%08x\n", layer, lid, blendmode); /* Set color format */ @@ -1172,7 +1172,7 @@ static int stm32_dma2dgetvideoinfo(FAR struct dma2d_layer_s *layer, { FAR struct stm32_dma2d_s *priv = (FAR struct stm32_dma2d_s *)layer; - ginfo("layer=%p, vinfo=%p\n", layer, vinfo); + lcdinfo("layer=%p, vinfo=%p\n", layer, vinfo); if (stm32_dma2d_lvalidate(priv) && vinfo) { @@ -1183,7 +1183,7 @@ static int stm32_dma2dgetvideoinfo(FAR struct dma2d_layer_s *layer, return OK; } - gerr("ERROR: Returning EINVAL\n"); + lcderr("ERROR: Returning EINVAL\n"); return -ENOSYS; } @@ -1209,7 +1209,7 @@ static int stm32_dma2dgetplaneinfo(FAR struct dma2d_layer_s *layer, int planeno, { FAR struct stm32_dma2d_s *priv = (FAR struct stm32_dma2d_s *)layer; - ginfo("layer=%p, planeno=%d, pinfo=%p\n", layer, planeno, pinfo); + lcdinfo("layer=%p, planeno=%d, pinfo=%p\n", layer, planeno, pinfo); if (stm32_dma2d_lvalidate(priv) && pinfo && planeno == 0) { @@ -1220,7 +1220,7 @@ static int stm32_dma2dgetplaneinfo(FAR struct dma2d_layer_s *layer, int planeno, return OK; } - gerr("ERROR: Returning EINVAL\n"); + lcderr("ERROR: Returning EINVAL\n"); return -EINVAL; } @@ -1244,7 +1244,7 @@ static int stm32_dma2dgetlid(FAR struct dma2d_layer_s *layer, int *lid) { FAR struct stm32_dma2d_s *priv = (FAR struct stm32_dma2d_s *)layer; - ginfo("layer=%p, lid=%p\n", layer, lid); + lcdinfo("layer=%p, lid=%p\n", layer, lid); if (stm32_dma2d_lvalidate(priv) && lid) { @@ -1254,7 +1254,7 @@ static int stm32_dma2dgetlid(FAR struct dma2d_layer_s *layer, int *lid) return OK; } - gerr("ERROR: Returning EINVAL\n"); + lcderr("ERROR: Returning EINVAL\n"); return -EINVAL; } @@ -1282,7 +1282,7 @@ static int stm32_dma2dsetclut(FAR struct dma2d_layer_s *layer, int ret; FAR struct stm32_dma2d_s *priv = (FAR struct stm32_dma2d_s *)layer; - ginfo("layer=%p, cmap=%p\n", layer, cmap); + lcdinfo("layer=%p, cmap=%p\n", layer, cmap); if (stm32_dma2d_lvalidate(priv) && cmap) { @@ -1320,14 +1320,14 @@ static int stm32_dma2dsetclut(FAR struct dma2d_layer_s *layer, if (priv->fmt != DMA2D_PF_L8) { - gerr("Error: CLUT is not supported for the pixel format: %d\n", - priv->vinfo.fmt); + lcderr("ERROR: CLUT is not supported for the pixel format: %d\n", + priv->vinfo.fmt); ret = -EINVAL; } else if (cmap->first >= STM32_DMA2D_NCLUT) { - gerr("Error: only %d color table entries supported\n", - STM32_DMA2D_NCLUT); + lcderr("ERROR: only %d color table entries supported\n", + STM32_DMA2D_NCLUT); ret = -EINVAL; } else @@ -1374,7 +1374,7 @@ static int stm32_dma2dsetclut(FAR struct dma2d_layer_s *layer, return ret; } - gerr("ERROR: Returning EINVAL\n"); + lcderr("ERROR: Returning EINVAL\n"); return -EINVAL; } @@ -1401,7 +1401,7 @@ static int stm32_dma2dgetclut(FAR struct dma2d_layer_s *layer, int ret; FAR struct stm32_dma2d_s *priv = (FAR struct stm32_dma2d_s *)layer; - ginfo("layer=%p, cmap=%p\n", layer, cmap); + lcdinfo("layer=%p, cmap=%p\n", layer, cmap); if (stm32_dma2d_lvalidate(priv) && cmap) { @@ -1409,14 +1409,14 @@ static int stm32_dma2dgetclut(FAR struct dma2d_layer_s *layer, if (priv->fmt != DMA2D_PF_L8) { - gerr("Error: CLUT is not supported for the pixel format: %d\n", - priv->vinfo.fmt); + lcderr("ERROR: CLUT is not supported for the pixel format: %d\n", + priv->vinfo.fmt); ret = -EINVAL; } else if (cmap->first >= STM32_DMA2D_NCLUT) { - gerr("Error: only %d color table entries supported\n", - STM32_DMA2D_NCLUT); + lcderr("ERROR: only %d color table entries supported\n", + STM32_DMA2D_NCLUT); ret = -EINVAL; } else @@ -1461,7 +1461,7 @@ static int stm32_dma2dgetclut(FAR struct dma2d_layer_s *layer, return ret; } - gerr("ERROR: Returning EINVAL\n"); + lcderr("ERROR: Returning EINVAL\n"); return -EINVAL; } #endif @@ -1491,7 +1491,7 @@ static int stm32_dma2dsetalpha(FAR struct dma2d_layer_s *layer, uint8_t alpha) { FAR struct stm32_dma2d_s *priv = (FAR struct stm32_dma2d_s *)layer; - ginfo("layer=%p, alpha=%02x\n", layer, alpha); + lcdinfo("layer=%p, alpha=%02x\n", layer, alpha); if (stm32_dma2d_lvalidate(priv)) { @@ -1502,7 +1502,7 @@ static int stm32_dma2dsetalpha(FAR struct dma2d_layer_s *layer, uint8_t alpha) return OK; } - gerr("ERROR: Returning EINVAL\n"); + lcderr("ERROR: Returning EINVAL\n"); return -EINVAL; } @@ -1526,7 +1526,7 @@ static int stm32_dma2dgetalpha(FAR struct dma2d_layer_s *layer, uint8_t *alpha) { FAR struct stm32_dma2d_s *priv = (FAR struct stm32_dma2d_s *)layer; - ginfo("layer=%p, alpha=%p\n", layer, alpha); + lcdinfo("layer=%p, alpha=%p\n", layer, alpha); if (stm32_dma2d_lvalidate(priv)) { @@ -1537,7 +1537,7 @@ static int stm32_dma2dgetalpha(FAR struct dma2d_layer_s *layer, uint8_t *alpha) return OK; } - gerr("ERROR: Returning EINVAL\n"); + lcderr("ERROR: Returning EINVAL\n"); return -EINVAL; } @@ -1577,7 +1577,7 @@ static int stm32_dma2dsetblendmode(FAR struct dma2d_layer_s *layer, { FAR struct stm32_dma2d_s *priv = (FAR struct stm32_dma2d_s *)layer; - ginfo("layer=%p, mode=%08x\n", layer, mode); + lcdinfo("layer=%p, mode=%08x\n", layer, mode); if (stm32_dma2d_lvalidate(priv)) { @@ -1588,7 +1588,7 @@ static int stm32_dma2dsetblendmode(FAR struct dma2d_layer_s *layer, return OK; } - gerr("ERROR: Returning EINVAL\n"); + lcderr("ERROR: Returning EINVAL\n"); return -EINVAL; } @@ -1613,7 +1613,7 @@ static int stm32_dma2dgetblendmode(FAR struct dma2d_layer_s *layer, { FAR struct stm32_dma2d_s *priv = (FAR struct stm32_dma2d_s *)layer; - ginfo("layer=%p, mode=%p\n", layer, mode); + lcdinfo("layer=%p, mode=%p\n", layer, mode); if (stm32_dma2d_lvalidate(priv) && mode) { @@ -1624,7 +1624,7 @@ static int stm32_dma2dgetblendmode(FAR struct dma2d_layer_s *layer, return OK; } - gerr("ERROR: Returning EINVAL\n"); + lcderr("ERROR: Returning EINVAL\n"); return -EINVAL; } @@ -1661,8 +1661,8 @@ static int stm32_dma2dblit(FAR struct dma2d_layer_s *dest, FAR struct stm32_dma2d_s * destlayer = (FAR struct stm32_dma2d_s *)dest; FAR struct stm32_dma2d_s * srclayer = (FAR struct stm32_dma2d_s *)src; - ginfo("dest=%p, destxpos=%d, destypos=%d, src=%p, srcarea=%p\n", - dest, destxpos, destypos, src, srcarea); + lcdinfo("dest=%p, destxpos=%d, destypos=%d, src=%p, srcarea=%p\n", + dest, destxpos, destypos, src, srcarea); if (stm32_dma2d_lvalidatesize(destlayer, destxpos, destypos, srcarea) && stm32_dma2d_lvalidatesize(srclayer, srcarea->xpos, @@ -1718,7 +1718,7 @@ static int stm32_dma2dblit(FAR struct dma2d_layer_s *dest, if (ret != OK) { ret = -ECANCELED; - gerr("ERROR: Returning ECANCELED\n"); + lcderr("ERROR: Returning ECANCELED\n"); } } @@ -1727,7 +1727,7 @@ static int stm32_dma2dblit(FAR struct dma2d_layer_s *dest, else { ret = -EINVAL; - gerr("ERROR: Returning EINVAL\n"); + lcderr("ERROR: Returning EINVAL\n"); } return ret; @@ -1772,10 +1772,10 @@ static int stm32_dma2dblend(FAR struct dma2d_layer_s *dest, FAR struct stm32_dma2d_s * forelayer = (FAR struct stm32_dma2d_s *)fore; FAR struct stm32_dma2d_s * backlayer = (FAR struct stm32_dma2d_s *)back; - ginfo("dest=%p, destxpos=%d, destypos=%d, " - "fore=%p, forexpos=%d, foreypos=%d, " - "back=%p, backarea=%p\n", - dest, destxpos, destypos, fore, forexpos, foreypos, back, backarea); + lcdinfo("dest=%p, destxpos=%d, destypos=%d, " + "fore=%p, forexpos=%d, foreypos=%d, " + "back=%p, backarea=%p\n", + dest, destxpos, destypos, fore, forexpos, foreypos, back, backarea); if (stm32_dma2d_lvalidatesize(destlayer, destxpos, destypos, backarea) && stm32_dma2d_lvalidatesize(forelayer, forexpos, foreypos, backarea) && @@ -1832,7 +1832,7 @@ static int stm32_dma2dblend(FAR struct dma2d_layer_s *dest, if (ret != OK) { ret = -ECANCELED; - gerr("ERROR: Returning ECANCELED\n"); + lcderr("ERROR: Returning ECANCELED\n"); } } @@ -1841,7 +1841,7 @@ static int stm32_dma2dblend(FAR struct dma2d_layer_s *dest, else { ret = -EINVAL; - gerr("ERROR: Returning EINVAL\n"); + lcderr("ERROR: Returning EINVAL\n"); } return ret; @@ -1874,7 +1874,7 @@ static int stm32_dma2dfillarea(FAR struct dma2d_layer_s *layer, int ret; FAR struct stm32_dma2d_s *priv = (FAR struct stm32_dma2d_s *)layer; - ginfo("layer=%p, area=%p, color=%08x\n", layer, area, color); + lcdinfo("layer=%p, area=%p, color=%08x\n", layer, area, color); if (stm32_dma2d_lvalidatesize(priv, area->xpos, area->ypos, area)) { @@ -1912,7 +1912,7 @@ static int stm32_dma2dfillarea(FAR struct dma2d_layer_s *layer, if (ret != OK) { ret = -ECANCELED; - gerr("ERROR: Returning ECANCELED\n"); + lcderr("ERROR: Returning ECANCELED\n"); } } @@ -1921,7 +1921,7 @@ static int stm32_dma2dfillarea(FAR struct dma2d_layer_s *layer, else { ret = -EINVAL; - gerr("ERROR: Returning EINVAL\n"); + lcderr("ERROR: Returning EINVAL\n"); } return ret; @@ -1954,7 +1954,7 @@ FAR struct dma2d_layer_s * up_dma2dgetlayer(int lid) return &priv->dma2d; } - gerr("ERROR: EINVAL, Unknown layer identifier\n"); + lcderr("ERROR: EINVAL, Unknown layer identifier\n"); errno = EINVAL; return NULL; } @@ -1989,7 +1989,7 @@ FAR struct dma2d_layer_s *up_dma2dcreatelayer(fb_coord_t width, uint8_t bpp = 0; FAR struct stm32_dma2d_s *layer = NULL; - ginfo("width=%d, height=%d, fmt=%02x \n", width, height, fmt); + lcdinfo("width=%d, height=%d, fmt=%02x \n", width, height, fmt); /* Validate if pixel format supported */ @@ -2069,19 +2069,19 @@ FAR struct dma2d_layer_s *up_dma2dcreatelayer(fb_coord_t width, /* free the layer struture */ kmm_free(layer); - gerr("ERROR: ENOMEM, Unable to allocate layer buffer\n"); + lcderr("ERROR: ENOMEM, Unable to allocate layer buffer\n"); errno = ENOMEM; } } else { - gerr("ERROR: ENOMEM, unable to allocate layer structure\n"); + lcderr("ERROR: ENOMEM, unable to allocate layer structure\n"); errno = ENOMEM; } } else { - gerr("ERROR: EINVAL, no free layer available\n"); + lcderr("ERROR: EINVAL, no free layer available\n"); errno = EINVAL; } @@ -2148,7 +2148,7 @@ int up_dma2dremovelayer(FAR struct dma2d_layer_s *layer) int up_dma2dinitialize(void) { - err("Initialize DMA2D driver\n"); + lcdinfo("Initialize DMA2D driver\n"); if (g_initialized == false) { @@ -2265,15 +2265,15 @@ FAR struct dma2d_layer_s * stm32_dma2dinitltdc(FAR struct stm32_ltdc_s *layer) uint8_t fmt = 0; FAR struct stm32_ltdc_dma2d_s *priv; - ginfo("layer=%p\n", layer); + lcdinfo("layer=%p\n", layer); DEBUGASSERT(layer && layer->lid >= 0 && layer->lid < DMA2D_SHADOW_LAYER); ret = stm32_dma2d_pixelformat(layer->vinfo.fmt, &fmt); if (ret != OK) { - err("Returning -EINVAL, unsupported pixel format: %d\n", - layer->vinfo.fmt); + lcderr("ERROR: Returning -EINVAL, unsupported pixel format: %d\n", + layer->vinfo.fmt); errno = -EINVAL; return NULL; } diff --git a/arch/arm/src/stm32/stm32_eth.c b/arch/arm/src/stm32/stm32_eth.c index e2708372ba..df02c0a857 100644 --- a/arch/arm/src/stm32/stm32_eth.c +++ b/arch/arm/src/stm32/stm32_eth.c @@ -240,7 +240,7 @@ * enabled. */ -#ifndef CONFIG_DEBUG_FEATURES +#ifndef CONFIG_DEBUG_NET_INFO # undef CONFIG_STM32_ETHMAC_REGDEBUG #endif @@ -748,7 +748,7 @@ static int stm32_ethconfig(FAR struct stm32_ethmac_s *priv); * ****************************************************************************/ -#if defined(CONFIG_STM32_ETHMAC_REGDEBUG) && defined(CONFIG_DEBUG_FEATURES) +#ifdef CONFIG_STM32_ETHMAC_REGDEBUG static uint32_t stm32_getreg(uint32_t addr) { static uint32_t prevaddr = 0; @@ -769,7 +769,7 @@ static uint32_t stm32_getreg(uint32_t addr) { if (count == 4) { - llerr("...\n"); + ninfo("...\n"); } return val; @@ -786,7 +786,7 @@ static uint32_t stm32_getreg(uint32_t addr) { /* Yes.. then show how many times the value repeated */ - llerr("[repeats %d more times]\n", count-3); + ninfo("[repeats %d more times]\n", count-3); } /* Save the new address, value, and count */ @@ -798,7 +798,7 @@ static uint32_t stm32_getreg(uint32_t addr) /* Show the register value read */ - llerr("%08x->%08x\n", addr, val); + ninfo("%08x->%08x\n", addr, val); return val; } #endif @@ -820,12 +820,12 @@ static uint32_t stm32_getreg(uint32_t addr) * ****************************************************************************/ -#if defined(CONFIG_STM32_ETHMAC_REGDEBUG) && defined(CONFIG_DEBUG_FEATURES) +#ifdef CONFIG_STM32_ETHMAC_REGDEBUG static void stm32_putreg(uint32_t val, uint32_t addr) { /* Show the register value being written */ - llerr("%08x<-%08x\n", addr, val); + ninfo("%08x<-%08x\n", addr, val); /* Write the value */ @@ -847,7 +847,7 @@ static void stm32_putreg(uint32_t val, uint32_t addr) * ****************************************************************************/ -#if defined(CONFIG_STM32_ETHMAC_REGDEBUG) && defined(CONFIG_DEBUG_FEATURES) +#ifdef CONFIG_STM32_ETHMAC_REGDEBUG static void stm32_checksetup(void) { } @@ -1505,7 +1505,7 @@ static int stm32_recvframe(FAR struct stm32_ethmac_s *priv) if (!stm32_isfreebuffer(priv)) { - nllerr("No free buffers\n"); + nllerr("ERROR: No free buffers\n"); return -ENOMEM; } @@ -1612,7 +1612,7 @@ static int stm32_recvframe(FAR struct stm32_ethmac_s *priv) * scanning logic, and continue scanning with the next frame. */ - nllerr("DROPPED: RX descriptor errors: %08x\n", rxdesc->rdes0); + nllerr("ERROR: Dropped, RX descriptor errors: %08x\n", rxdesc->rdes0); stm32_freesegment(priv, rxcurr, priv->segments); } } @@ -1673,7 +1673,7 @@ static void stm32_receive(FAR struct stm32_ethmac_s *priv) if (dev->d_len > CONFIG_NET_ETH_MTU) { - nllerr("DROPPED: Too big: %d\n", dev->d_len); + nllerr("ERROR: Dropped, Too big: %d\n", dev->d_len); /* Free dropped packet buffer */ @@ -1793,7 +1793,7 @@ static void stm32_receive(FAR struct stm32_ethmac_s *priv) else #endif { - nllerr("DROPPED: Unknown type: %04x\n", BUF->type); + nllerr("ERROR: Dropped, Unknown type: %04x\n", BUF->type); } /* We are finished with the RX buffer. NOTE: If the buffer is @@ -2042,7 +2042,7 @@ static inline void stm32_interrupt_process(FAR struct stm32_ethmac_s *priv) { /* Just let the user know what happened */ - nllerr("Abormal event(s): %08x\n", dmasr); + nllninfoAbormal event(s): %08x\n", dmasr); /* Clear all pending abnormal events */ @@ -2246,7 +2246,7 @@ static void stm32_txtimeout_expiry(int argc, uint32_t arg, ...) { FAR struct stm32_ethmac_s *priv = (FAR struct stm32_ethmac_s *)arg; - nllerr("Timeout!\n"); + nllninfoTimeout!\n"); #ifdef CONFIG_NET_NOINTS /* Disable further Ethernet interrupts. This will prevent some race @@ -2447,15 +2447,15 @@ static int stm32_ifup(struct net_driver_s *dev) int ret; #ifdef CONFIG_NET_IPv4 - nerr("Bringing up: %d.%d.%d.%d\n", - dev->d_ipaddr & 0xff, (dev->d_ipaddr >> 8) & 0xff, + ninfo("Bringing up: %d.%d.%d.%d\n", + dev->d_ipaddr & 0xff, (dev->d_ipaddr >> 8) & 0xff, (dev->d_ipaddr >> 16) & 0xff, dev->d_ipaddr >> 24); #endif #ifdef CONFIG_NET_IPv6 - nerr("Bringing up: %04x:%04x:%04x:%04x:%04x:%04x:%04x:%04x\n", - dev->d_ipv6addr[0], dev->d_ipv6addr[1], dev->d_ipv6addr[2], - dev->d_ipv6addr[3], dev->d_ipv6addr[4], dev->d_ipv6addr[5], - dev->d_ipv6addr[6], dev->d_ipv6addr[7]); + ninfo("Bringing up: %04x:%04x:%04x:%04x:%04x:%04x:%04x:%04x\n", + dev->d_ipv6addr[0], dev->d_ipv6addr[1], dev->d_ipv6addr[2], + dev->d_ipv6addr[3], dev->d_ipv6addr[4], dev->d_ipv6addr[5], + dev->d_ipv6addr[6], dev->d_ipv6addr[7]); #endif /* Configure the Ethernet interface for DMA operation. */ @@ -2500,7 +2500,7 @@ static int stm32_ifdown(struct net_driver_s *dev) FAR struct stm32_ethmac_s *priv = (FAR struct stm32_ethmac_s *)dev->d_private; irqstate_t flags; - nerr("Taking the network down\n"); + ninfo("Taking the network down\n"); /* Disable the Ethernet interrupt */ @@ -3129,7 +3129,7 @@ static int stm32_phyread(uint16_t phydevaddr, uint16_t phyregaddr, uint16_t *val } } - nerr("MII transfer timed out: phydevaddr: %04x phyregaddr: %04x\n", + nerr("ERROR: MII transfer timed out: phydevaddr: %04x phyregaddr: %04x\n", phydevaddr, phyregaddr); return -ETIMEDOUT; @@ -3188,7 +3188,7 @@ static int stm32_phywrite(uint16_t phydevaddr, uint16_t phyregaddr, uint16_t val } } - nerr("MII transfer timed out: phydevaddr: %04x phyregaddr: %04x value: %04x\n", + nerr("ERROR: MII transfer timed out: phydevaddr: %04x phyregaddr: %04x value: %04x\n", phydevaddr, phyregaddr, value); return -ETIMEDOUT; @@ -3225,7 +3225,7 @@ static inline int stm32_dm9161(FAR struct stm32_ethmac_s *priv) ret = stm32_phyread(CONFIG_STM32_PHYADDR, MII_PHYID1, &phyval); if (ret < 0) { - nerr("Failed to read the PHY ID1: %d\n", ret); + nerr("ERROR: Failed to read the PHY ID1: %d\n", ret); return ret; } @@ -3243,7 +3243,7 @@ static inline int stm32_dm9161(FAR struct stm32_ethmac_s *priv) ret = stm32_phyread(CONFIG_STM32_PHYADDR, 16, &phyval); if (ret < 0) { - nerr("Failed to read the PHY Register 0x10: %d\n", ret); + nerr("ERROR: Failed to read the PHY Register 0x10: %d\n", ret); return ret; } @@ -3300,7 +3300,7 @@ static int stm32_phyinit(FAR struct stm32_ethmac_s *priv) ret = stm32_phywrite(CONFIG_STM32_PHYADDR, MII_MCR, MII_MCR_RESET); if (ret < 0) { - nerr("Failed to reset the PHY: %d\n", ret); + nerr("ERROR: Failed to reset the PHY: %d\n", ret); return ret; } up_mdelay(PHY_RESET_DELAY); @@ -3311,7 +3311,7 @@ static int stm32_phyinit(FAR struct stm32_ethmac_s *priv) ret = stm32_phy_boardinitialize(0); if (ret < 0) { - nerr("Failed to initialize the PHY: %d\n", ret); + nerr("ERROR: Failed to initialize the PHY: %d\n", ret); return ret; } #endif @@ -3336,7 +3336,7 @@ static int stm32_phyinit(FAR struct stm32_ethmac_s *priv) ret = stm32_phyread(CONFIG_STM32_PHYADDR, MII_MSR, &phyval); if (ret < 0) { - nerr("Failed to read the PHY MSR: %d\n", ret); + nerr("ERROR: Failed to read the PHY MSR: %d\n", ret); return ret; } else if ((phyval & MII_MSR_LINKSTATUS) != 0) @@ -3347,7 +3347,7 @@ static int stm32_phyinit(FAR struct stm32_ethmac_s *priv) if (timeout >= PHY_RETRY_TIMEOUT) { - nerr("Timed out waiting for link status: %04x\n", phyval); + nerr("ERROR: Timed out waiting for link status: %04x\n", phyval); return -ETIMEDOUT; } @@ -3356,7 +3356,7 @@ static int stm32_phyinit(FAR struct stm32_ethmac_s *priv) ret = stm32_phywrite(CONFIG_STM32_PHYADDR, MII_MCR, MII_MCR_ANENABLE); if (ret < 0) { - nerr("Failed to enable auto-negotiation: %d\n", ret); + nerr("ERROR: Failed to enable auto-negotiation: %d\n", ret); return ret; } @@ -3367,7 +3367,7 @@ static int stm32_phyinit(FAR struct stm32_ethmac_s *priv) ret = stm32_phyread(CONFIG_STM32_PHYADDR, MII_MSR, &phyval); if (ret < 0) { - nerr("Failed to read the PHY MSR: %d\n", ret); + nerr("ERROR: Failed to read the PHY MSR: %d\n", ret); return ret; } else if ((phyval & MII_MSR_ANEGCOMPLETE) != 0) @@ -3378,7 +3378,7 @@ static int stm32_phyinit(FAR struct stm32_ethmac_s *priv) if (timeout >= PHY_RETRY_TIMEOUT) { - nerr("Timed out waiting for auto-negotiation\n"); + nerr("ERROR: Timed out waiting for auto-negotiation\n"); return -ETIMEDOUT; } @@ -3387,7 +3387,7 @@ static int stm32_phyinit(FAR struct stm32_ethmac_s *priv) ret = stm32_phyread(CONFIG_STM32_PHYADDR, CONFIG_STM32_PHYSR, &phyval); if (ret < 0) { - nerr("Failed to read PHY status register\n"); + nerr("ERROR: Failed to read PHY status register\n"); return ret; } @@ -3457,7 +3457,7 @@ static int stm32_phyinit(FAR struct stm32_ethmac_s *priv) ret = stm32_phywrite(CONFIG_STM32_PHYADDR, MII_MCR, phyval); if (ret < 0) { - nerr("Failed to write the PHY MCR: %d\n", ret); + nerr("ERROR: Failed to write the PHY MCR: %d\n", ret); return ret; } up_mdelay(PHY_CONFIG_DELAY); @@ -3472,9 +3472,9 @@ static int stm32_phyinit(FAR struct stm32_ethmac_s *priv) #endif #endif - nerr("Duplex: %s Speed: %d MBps\n", - priv->fduplex ? "FULL" : "HALF", - priv->mbps100 ? 100 : 10); + ninfo("Duplex: %s Speed: %d MBps\n", + priv->fduplex ? "FULL" : "HALF", + priv->mbps100 ? 100 : 10); return OK; } diff --git a/arch/arm/src/stm32/stm32_i2c.c b/arch/arm/src/stm32/stm32_i2c.c index 97e6ccc682..9f41597f04 100644 --- a/arch/arm/src/stm32/stm32_i2c.c +++ b/arch/arm/src/stm32/stm32_i2c.c @@ -850,7 +850,7 @@ static void stm32_i2c_tracenew(FAR struct stm32_i2c_priv_s *priv, uint32_t statu if (priv->tndx >= (CONFIG_I2C_NTRACE-1)) { - i2cerr("Trace table overflow\n"); + i2cerr("ERROR: Trace table overflow\n"); return; } @@ -891,7 +891,7 @@ static void stm32_i2c_traceevent(FAR struct stm32_i2c_priv_s *priv, if (priv->tndx >= (CONFIG_I2C_NTRACE-1)) { - i2cerr("Trace table overflow\n"); + i2cerr("ERROR: Trace table overflow\n"); return; } @@ -1686,7 +1686,7 @@ static int stm32_i2c_transfer(FAR struct i2c_master_s *dev, FAR struct i2c_msg_s status = stm32_i2c_getstatus(priv); ret = -ETIMEDOUT; - i2cerr("Timed out: CR1: 0x%04x status: 0x%08x\n", + i2cerr("ERROR: Timed out: CR1: 0x%04x status: 0x%08x\n", stm32_i2c_getreg(priv, STM32_I2C_CR1_OFFSET), status); /* "Note: When the STOP, START or PEC bit is set, the software must diff --git a/arch/arm/src/stm32/stm32_i2c_alt.c b/arch/arm/src/stm32/stm32_i2c_alt.c index 1419bfc81f..ac2ea5f607 100644 --- a/arch/arm/src/stm32/stm32_i2c_alt.c +++ b/arch/arm/src/stm32/stm32_i2c_alt.c @@ -858,7 +858,7 @@ static void stm32_i2c_tracenew(FAR struct stm32_i2c_priv_s *priv, uint16_t statu if (priv->tndx >= (CONFIG_I2C_NTRACE-1)) { - i2cerr("Trace table overflow\n"); + i2cerr("ERROR: Trace table overflow\n"); return; } @@ -899,7 +899,7 @@ static void stm32_i2c_traceevent(FAR struct stm32_i2c_priv_s *priv, if (priv->tndx >= (CONFIG_I2C_NTRACE-1)) { - i2cerr("Trace table overflow\n"); + i2cerr("ERROR: Trace table overflow\n"); return; } @@ -1373,7 +1373,7 @@ static int stm32_i2c_isr(struct stm32_i2c_priv_s *priv) { /* TODO: untested!! */ - i2cerr(" An empty message has been detected, ignoring and passing to next message.\n"); + i2cwarn("WARNING: An empty message has been detected, ignoring and passing to next message.\n"); /* Trace event */ @@ -1600,14 +1600,14 @@ static int stm32_i2c_isr(struct stm32_i2c_priv_s *priv) } else { - i2cerr("Write mode: next message has an unrecognized flag.\n"); + i2cerr("ERROR: Write mode: next message has an unrecognized flag.\n"); stm32_i2c_traceevent(priv, I2CEVENT_WRITE_FLAG_ERROR, priv->msgv->flags); } } else { - i2cerr("Write mode error.\n"); + i2cerr("ERROR: Write mode error.\n"); stm32_i2c_traceevent(priv, I2CEVENT_WRITE_ERROR, 0); } } @@ -1774,8 +1774,8 @@ static int stm32_i2c_isr(struct stm32_i2c_priv_s *priv) else { - i2cerr("I2C read mode no correct state detected\n"); - i2cerr(" state %i, dcnt=%i\n", status, priv->dcnt); + i2cerr("ERROR: I2C read mode no correct state detected\n"); + i2cerr(" state %i, dcnt=%i\n", status, priv->dcnt); /* set condition to terminate ISR and wake waiting thread */ @@ -1800,7 +1800,7 @@ static int stm32_i2c_isr(struct stm32_i2c_priv_s *priv) /* Read rest of the state */ status |= (stm32_i2c_getreg(priv, STM32_I2C_SR2_OFFSET) << 16); - i2cerr("Empty call to ISR: Stopping ISR\n"); + i2cwarn("WARNING: Empty call to ISR: Stopping ISR\n"); stm32_i2c_traceevent(priv, I2CEVENT_ISR_EMPTY_CALL, 0); } @@ -1824,8 +1824,8 @@ static int stm32_i2c_isr(struct stm32_i2c_priv_s *priv) status |= (stm32_i2c_getreg(priv, STM32_I2C_SR2_OFFSET) << 16); - i2cerr(" No correct state detected(start bit, read or write) \n"); - i2cerr(" state %i\n", status); + i2cerr("ERROR: No correct state detected(start bit, read or write) \n"); + i2cerr(" state %i\n", status); /* set condition to terminate ISR and wake waiting thread */ @@ -2117,7 +2117,7 @@ static int stm32_i2c_transfer(FAR struct i2c_master_s *dev, FAR struct i2c_msg_s status = stm32_i2c_getstatus(priv); ret = -ETIMEDOUT; - i2cerr("Timed out: CR1: 0x%04x status: 0x%08x\n", + i2cerr("ERROR: Timed out: CR1: 0x%04x status: 0x%08x\n", stm32_i2c_getreg(priv, STM32_I2C_CR1_OFFSET), status); /* "Note: When the STOP, START or PEC bit is set, the software must @@ -2147,7 +2147,8 @@ static int stm32_i2c_transfer(FAR struct i2c_master_s *dev, FAR struct i2c_msg_s * Note: this commentary is found in both places. * */ - i2cerr("Check if the address was valid\n"); + + i2cinfo("Check if the address was valid\n"); stm32_i2c_sendstop(priv); #endif /* Clear busy flag in case of timeout */ diff --git a/arch/arm/src/stm32/stm32_iwdg.c b/arch/arm/src/stm32/stm32_iwdg.c index ab6b052714..1cdf8e47bc 100644 --- a/arch/arm/src/stm32/stm32_iwdg.c +++ b/arch/arm/src/stm32/stm32_iwdg.c @@ -84,6 +84,10 @@ # define CONFIG_STM32_IWDG_DEFTIMOUT IWDG_MAXTIMEOUT #endif +#ifndef CONFIG_DEBUG_WATCHDOG_INFO +# undef CONFIG_STM32_IWDG_REGDEBUG +#endif + /* REVISIT: It appears that you can only setup the prescaler and reload * registers once. After that, the SR register's PVU and RVU bits never go * to zero. So we defer setting up these registers until the watchdog @@ -129,7 +133,7 @@ struct stm32_lowerhalf_s ****************************************************************************/ /* Register operations ******************************************************/ -#if defined(CONFIG_STM32_IWDG_REGDEBUG) && defined(CONFIG_DEBUG_FEATURES) +#ifdef CONFIG_STM32_IWDG_REGDEBUG static uint16_t stm32_getreg(uint32_t addr); static void stm32_putreg(uint16_t val, uint32_t addr); #else @@ -181,7 +185,7 @@ static struct stm32_lowerhalf_s g_wdgdev; * ****************************************************************************/ -#if defined(CONFIG_STM32_IWDG_REGDEBUG) && defined(CONFIG_DEBUG_FEATURES) +#ifdef CONFIG_STM32_IWDG_REGDEBUG static uint16_t stm32_getreg(uint32_t addr) { static uint32_t prevaddr = 0; @@ -202,7 +206,7 @@ static uint16_t stm32_getreg(uint32_t addr) { if (count == 4) { - llerr("...\n"); + wdinfo("...\n"); } return val; @@ -219,7 +223,7 @@ static uint16_t stm32_getreg(uint32_t addr) { /* Yes.. then show how many times the value repeated */ - llerr("[repeats %d more times]\n", count-3); + wdinfo("[repeats %d more times]\n", count-3); } /* Save the new address, value, and count */ @@ -231,7 +235,7 @@ static uint16_t stm32_getreg(uint32_t addr) /* Show the register value read */ - llerr("%08x->%04x\n", addr, val); + wdinfo("%08x->%04x\n", addr, val); return val; } #endif @@ -244,12 +248,12 @@ static uint16_t stm32_getreg(uint32_t addr) * ****************************************************************************/ -#if defined(CONFIG_STM32_IWDG_REGDEBUG) && defined(CONFIG_DEBUG_FEATURES) +#ifdef CONFIG_STM32_IWDG_REGDEBUG static void stm32_putreg(uint16_t val, uint32_t addr) { /* Show the register value being written */ - llerr("%08x<-%04x\n", addr, val); + wdinfo("%08x<-%04x\n", addr, val); /* Write the value */ @@ -509,7 +513,7 @@ static int stm32_settimeout(FAR struct watchdog_lowerhalf_s *lower, if (timeout < 1 || timeout > IWDG_MAXTIMEOUT) { - wderr("Cannot represent timeout=%d > %d\n", + wderr("ERROR: Cannot represent timeout=%d > %d\n", timeout, IWDG_MAXTIMEOUT); return -ERANGE; } @@ -522,7 +526,7 @@ static int stm32_settimeout(FAR struct watchdog_lowerhalf_s *lower, #ifdef CONFIG_STM32_IWDG_ONETIMESETUP if (priv->started) { - wderr("Timer is already started\n"); + wdwarn("WARNING: Timer is already started\n"); return -EBUSY; } #endif diff --git a/arch/arm/src/stm32/stm32_ltdc.c b/arch/arm/src/stm32/stm32_ltdc.c index 9ad25dfeed..442af257dd 100644 --- a/arch/arm/src/stm32/stm32_ltdc.c +++ b/arch/arm/src/stm32/stm32_ltdc.c @@ -283,8 +283,8 @@ /* Debug option */ #ifdef CONFIG_STM32_LTDC_REGDEBUG -# define regerr err -# define reginfo info +# define regerr lcderr +# define reginfo lcdinfo #else # define regerr(x...) # define reginfo(x...) @@ -942,7 +942,7 @@ static void stm32_ltdc_gpioconfig(void) { int i; - ginfo("Configuring pins\n"); + lcdinfo("Configuring pins\n"); /* Configure each pin */ @@ -1155,7 +1155,7 @@ static int stm32_ltdcirq(int irq, void *context) if (ret != OK) { - err("sem_post() failed\n"); + lcderr("ERROR: sem_post() failed\n"); return ret; } } @@ -1202,7 +1202,7 @@ static int stm32_ltdc_waitforirq(void) if (ret != OK) { - err("sem_wait() failed\n"); + lcderr("ERROR: sem_wait() failed\n"); } } @@ -1519,17 +1519,17 @@ static int stm32_ltdc_lvalidatearea(FAR struct stm32_layer_s *layer, (srcypos > ypos + yres - 1)) { - gerr("layer coordinates out of valid area: xpos = %d > %d, \ - ypos = %d > %d, width = %d > %d, height = %d > %d, \ - srcxpos = %d > %d, srcypos = %d > %d", - xpos, vinfo->xres - 1, - ypos, vinfo->yres - 1, - xres, vinfo->xres - xpos, - yres, vinfo->yres - ypos, - srcxpos, xpos + xres - 1, - srcypos, ypos + yres - 1); + lcderr("ERROR: layer coordinates out of valid area: xpos = %d > %d, \ + ypos = %d > %d, width = %d > %d, height = %d > %d, \ + srcxpos = %d > %d, srcypos = %d > %d", + xpos, vinfo->xres - 1, + ypos, vinfo->yres - 1, + xres, vinfo->xres - xpos, + yres, vinfo->yres - ypos, + srcxpos, xpos + xres - 1, + srcypos, ypos + yres - 1); - gerr("Returning EINVAL\n"); + lcderr(" Returning EINVAL\n"); return -EINVAL; } @@ -1985,8 +1985,8 @@ static void stm32_ltdc_lclear(FAR struct stm32_layer_s *layer, uint8_t *dest = (uint8_t *)priv->pinfo.fbmem; int i; - ginfo("Clearing display: BPP=%d color=%04x framebuffer=%08x size=%d\n", - priv->pinfo.bpp, color, dest, priv->pinfo.fblen); + lcdinfo("Clearing display: BPP=%d color=%04x framebuffer=%08x size=%d\n", + priv->pinfo.bpp, color, dest, priv->pinfo.fblen); for (i = 0; i < priv->pinfo.fblen; i += sizeof(uint8_t)) { @@ -2003,8 +2003,8 @@ static void stm32_ltdc_lclear(FAR struct stm32_layer_s *layer, uint16_t *dest = (uint16_t *)priv->pinfo.fbmem; int i; - ginfo("Clearing display: BPP=%d color=%04x framebuffer=%08x size=%d\n", - priv->pinfo.bpp, color, dest, priv->pinfo.fblen); + lcdinfo("Clearing display: BPP=%d color=%04x framebuffer=%08x size=%d\n", + priv->pinfo.bpp, color, dest, priv->pinfo.fblen); for (i = 0; i < priv->pinfo.fblen; i += sizeof(uint16_t)) { @@ -2024,8 +2024,8 @@ static void stm32_ltdc_lclear(FAR struct stm32_layer_s *layer, uint8_t b; int i; - ginfo("Clearing display: BPP=%d color=%04x framebuffer=%08x size=%d\n", - priv->pinfo.bpp, color, dest, priv->pinfo.fblen); + lcdinfo("Clearing display: BPP=%d color=%04x framebuffer=%08x size=%d\n", + priv->pinfo.bpp, color, dest, priv->pinfo.fblen); r = (uint8_t) color; g = (uint8_t) (color >> 8); @@ -2048,8 +2048,8 @@ static void stm32_ltdc_lclear(FAR struct stm32_layer_s *layer, uint32_t *dest = (uint32_t *)priv->pinfo.fbmem; int i; - ginfo("Clearing display: BPP=%d color=%04x framebuffer=%08x size=%d\n", - priv->pinfo.bpp, color, dest, priv->pinfo.fblen); + lcdinfo("Clearing display: BPP=%d color=%04x framebuffer=%08x size=%d\n", + priv->pinfo.bpp, color, dest, priv->pinfo.fblen); for (i = 0; i < priv->pinfo.fblen; i += sizeof(uint32_t)) { @@ -2191,7 +2191,7 @@ static void stm32_ltdc_linit(int lid) static int stm32_getvideoinfo(struct fb_vtable_s *vtable, struct fb_videoinfo_s *vinfo) { - ginfo("vtable=%p vinfo=%p\n", vtable, vinfo); + lcdinfo("vtable=%p vinfo=%p\n", vtable, vinfo); if (vtable) { FAR struct ltdc_layer_s *ltdc; @@ -2203,7 +2203,7 @@ static int stm32_getvideoinfo(struct fb_vtable_s *vtable, return stm32_lgetvideoinfo(ltdc, vinfo); } - gerr("ERROR: Returning EINVAL\n"); + lcderr("ERROR: Returning EINVAL\n"); return -EINVAL; } @@ -2226,7 +2226,7 @@ static int stm32_getvideoinfo(struct fb_vtable_s *vtable, static int stm32_getplaneinfo(struct fb_vtable_s *vtable, int planeno, struct fb_planeinfo_s *pinfo) { - ginfo("vtable=%p planeno=%d pinfo=%p\n", vtable, planeno, pinfo); + lcdinfo("vtable=%p planeno=%d pinfo=%p\n", vtable, planeno, pinfo); if (vtable) { FAR struct ltdc_layer_s *ltdc; @@ -2238,7 +2238,7 @@ static int stm32_getplaneinfo(struct fb_vtable_s *vtable, int planeno, return stm32_lgetplaneinfo(ltdc, planeno, pinfo); } - gerr("Returning EINVAL\n"); + lcderr("ERROR: Returning EINVAL\n"); return -EINVAL; } @@ -2315,7 +2315,7 @@ static int stm32_putcmap(struct fb_vtable_s *vtable, static int stm32_lgetvideoinfo(struct ltdc_layer_s *layer, struct fb_videoinfo_s *vinfo) { - ginfo("layer=%p vinfo=%p\n", layer, vinfo); + lcdinfo("layer=%p vinfo=%p\n", layer, vinfo); FAR struct stm32_layer_s *priv = (FAR struct stm32_layer_s *)layer; if (stm32_ltdc_lvalidate(priv)) @@ -2325,7 +2325,7 @@ static int stm32_lgetvideoinfo(struct ltdc_layer_s *layer, return OK; } - gerr("Returning EINVAL\n"); + lcderr("ERROR: Returning EINVAL\n"); return -EINVAL; } @@ -2349,16 +2349,16 @@ static int stm32_lgetvideoinfo(struct ltdc_layer_s *layer, static int stm32_lgetplaneinfo(struct ltdc_layer_s *layer, int planeno, struct fb_planeinfo_s *pinfo) { - ginfo("layer=%p planeno=%d pinfo=%p\n", layer, planeno, pinfo); FAR struct stm32_layer_s *priv = (FAR struct stm32_layer_s *)layer; + lcdinfo("layer=%p planeno=%d pinfo=%p\n", layer, planeno, pinfo); if (stm32_ltdc_lvalidate(priv) && planeno == 0) { memcpy(pinfo, &priv->state.pinfo, sizeof(struct fb_planeinfo_s)); return OK; } - gerr("Returning EINVAL\n"); + lcderr("ERROR: Returning EINVAL\n"); return -EINVAL; } @@ -2384,9 +2384,10 @@ static int stm32_lgetplaneinfo(struct ltdc_layer_s *layer, int planeno, static int stm32_setclut(struct ltdc_layer_s *layer, const struct fb_cmap_s *cmap) { - int ret; FAR struct stm32_layer_s *priv = (FAR struct stm32_layer_s *)layer; - ginfo("layer=%p cmap=%p\n", layer, cmap); + int ret; + + lcdinfo("layer=%p cmap=%p\n", layer, cmap); if (stm32_ltdc_lvalidate(priv) && cmap) { @@ -2394,14 +2395,14 @@ static int stm32_setclut(struct ltdc_layer_s *layer, if (priv->state.vinfo.fmt != FB_FMT_RGB8) { - gerr("Error: CLUT is not supported for the pixel format: %d\n", - priv->state.vinfo.fmt); + lcderr("ERROR: CLUT is not supported for the pixel format: %d\n", + priv->state.vinfo.fmt); ret = -EINVAL; } else if (cmap->first >= STM32_LTDC_NCLUT) { - gerr("Error: only %d color table entries supported\n", - STM32_LTDC_NCLUT); + lcderr("ERROR: only %d color table entries supported\n", + STM32_LTDC_NCLUT); ret = -EINVAL; } else @@ -2418,7 +2419,7 @@ static int stm32_setclut(struct ltdc_layer_s *layer, return ret; } - gerr("Returning EINVAL\n"); + lcderr("ERROR: Returning EINVAL\n"); return -EINVAL; } @@ -2442,9 +2443,10 @@ static int stm32_setclut(struct ltdc_layer_s *layer, static int stm32_getclut(struct ltdc_layer_s *layer, struct fb_cmap_s *cmap) { - int ret; FAR struct stm32_layer_s *priv = (FAR struct stm32_layer_s *)layer; - ginfo("layer=%p cmap=%p\n", layer, cmap); + int ret; + + lcdinfo("layer=%p cmap=%p\n", layer, cmap); if (priv == &LAYER_L1 || priv == &LAYER_L2) { @@ -2460,14 +2462,14 @@ static int stm32_getclut(struct ltdc_layer_s *layer, #else if (priv->state.vinfo.fmt != FB_FMT_RGB8) { - gerr("Error: CLUT is not supported for the pixel format: %d\n", - priv->state.vinfo.fmt); + lcderr("ERROR: CLUT is not supported for the pixel format: %d\n", + priv->state.vinfo.fmt); ret = -EINVAL; } else if (cmap->first >= STM32_LTDC_NCLUT) { - gerr("Error: only %d color table entries supported\n", - STM32_LTDC_NCLUT); + lcderr("ERROR: only %d color table entries supported\n", + STM32_LTDC_NCLUT); ret = -EINVAL; } else @@ -2512,7 +2514,7 @@ static int stm32_getclut(struct ltdc_layer_s *layer, return ret; } - gerr("Returning EINVAL\n"); + lcderr("ERROR: Returning EINVAL\n"); return -EINVAL; } #endif /* STM32_LAYER_CLUT_SIZE */ @@ -2542,7 +2544,7 @@ static int stm32_getlid(FAR struct ltdc_layer_s *layer, int *lid, { FAR struct stm32_layer_s *priv = (FAR struct stm32_layer_s *)layer; - ginfo("flag = %08x\n", flag); + lcdinfo("flag = %08x\n", flag); if (stm32_ltdc_lvalidate(priv)) { @@ -2583,7 +2585,7 @@ static int stm32_getlid(FAR struct ltdc_layer_s *layer, int *lid, #endif default: ret = EINVAL; - gerr("Returning EINVAL\n"); + lcderr("ERROR: Returning EINVAL\n"); break; } @@ -2592,7 +2594,7 @@ static int stm32_getlid(FAR struct ltdc_layer_s *layer, int *lid, return ret; } - gerr("Returning EINVAL\n"); + lcderr("ERROR: Returning EINVAL\n"); return -EINVAL; } @@ -2617,7 +2619,8 @@ static int stm32_getlid(FAR struct ltdc_layer_s *layer, int *lid, static int stm32_setcolor(FAR struct ltdc_layer_s *layer, uint32_t argb) { FAR struct stm32_layer_s *priv = (FAR struct stm32_layer_s *)layer; - ginfo("layer = %p, argb = %08x\n", layer, argb); + + lcdinfo("layer = %p, argb = %08x\n", layer, argb); if (stm32_ltdc_lvalidate(priv)) { @@ -2629,7 +2632,7 @@ static int stm32_setcolor(FAR struct ltdc_layer_s *layer, uint32_t argb) return OK; } - gerr("Returning EINVAL\n"); + lcderr("ERROR: Returning EINVAL\n"); return -EINVAL; } @@ -2652,7 +2655,8 @@ static int stm32_setcolor(FAR struct ltdc_layer_s *layer, uint32_t argb) static int stm32_getcolor(FAR struct ltdc_layer_s *layer, uint32_t *argb) { FAR struct stm32_layer_s *priv = (FAR struct stm32_layer_s *)layer; - ginfo("layer = %p, argb = %p\n", layer, argb); + + lcdinfo("layer = %p, argb = %p\n", layer, argb); if (stm32_ltdc_lvalidate(priv)) { @@ -2663,7 +2667,7 @@ static int stm32_getcolor(FAR struct ltdc_layer_s *layer, uint32_t *argb) return OK; } - gerr("Returning EINVAL\n"); + lcderr("ERROR: Returning EINVAL\n"); return -EINVAL; } @@ -2688,7 +2692,8 @@ static int stm32_getcolor(FAR struct ltdc_layer_s *layer, uint32_t *argb) static int stm32_setcolorkey(FAR struct ltdc_layer_s *layer, uint32_t rgb) { FAR struct stm32_layer_s *priv = (FAR struct stm32_layer_s *)layer; - ginfo("layer = %p, argb = %08x\n", layer, rgb); + + lcdinfo("layer = %p, argb = %08x\n", layer, rgb); if (stm32_ltdc_lvalidate(priv)) { @@ -2700,7 +2705,7 @@ static int stm32_setcolorkey(FAR struct ltdc_layer_s *layer, uint32_t rgb) return OK; } - gerr("Returning EINVAL\n"); + lcderr("ERROR: Returning EINVAL\n"); return -EINVAL; } @@ -2723,7 +2728,8 @@ static int stm32_setcolorkey(FAR struct ltdc_layer_s *layer, uint32_t rgb) static int stm32_getcolorkey(FAR struct ltdc_layer_s *layer, uint32_t *rgb) { FAR struct stm32_layer_s *priv = (FAR struct stm32_layer_s *)layer; - ginfo("layer = %p, argb = %p\n", layer, rgb); + + lcdinfo("layer = %p, argb = %p\n", layer, rgb); if (stm32_ltdc_lvalidate(priv)) { @@ -2734,7 +2740,7 @@ static int stm32_getcolorkey(FAR struct ltdc_layer_s *layer, uint32_t *rgb) return OK; } - gerr("Returning EINVAL\n"); + lcderr("ERROR: Returning EINVAL\n"); return -EINVAL; } @@ -2763,7 +2769,8 @@ static int stm32_getcolorkey(FAR struct ltdc_layer_s *layer, uint32_t *rgb) static int stm32_setalpha(FAR struct ltdc_layer_s *layer, uint8_t alpha) { FAR struct stm32_layer_s *priv = (FAR struct stm32_layer_s *)layer; - ginfo("layer = %p, alpha = %02x\n", layer, alpha); + + lcdinfo("layer = %p, alpha = %02x\n", layer, alpha); if (stm32_ltdc_lvalidate(priv)) { @@ -2775,7 +2782,7 @@ static int stm32_setalpha(FAR struct ltdc_layer_s *layer, uint8_t alpha) return OK; } - gerr("Returning EINVAL\n"); + lcderr("ERROR: Returning EINVAL\n"); return -EINVAL; } @@ -2798,7 +2805,8 @@ static int stm32_setalpha(FAR struct ltdc_layer_s *layer, uint8_t alpha) static int stm32_getalpha(FAR struct ltdc_layer_s *layer, uint8_t *alpha) { FAR struct stm32_layer_s *priv = (FAR struct stm32_layer_s *)layer; - ginfo("layer = %p, alpha = %p\n", layer, alpha); + + lcdinfo("layer = %p, alpha = %p\n", layer, alpha); if (stm32_ltdc_lvalidate(priv)) { @@ -2809,7 +2817,7 @@ static int stm32_getalpha(FAR struct ltdc_layer_s *layer, uint8_t *alpha) return OK; } - gerr("Returning EINVAL\n"); + lcderr("ERROR: Returning EINVAL\n"); return -EINVAL; } @@ -2856,8 +2864,9 @@ static int stm32_getalpha(FAR struct ltdc_layer_s *layer, uint8_t *alpha) static int stm32_setblendmode(FAR struct ltdc_layer_s *layer, uint32_t mode) { FAR struct stm32_layer_s *priv = (FAR struct stm32_layer_s *)layer; - uint32_t blendmode = mode; - ginfo("layer = %p, mode = %08x\n", layer, mode); + uint32_t blendmode = mode; + + lcdinfo("layer = %p, mode = %08x\n", layer, mode); if (stm32_ltdc_lvalidate(priv)) { @@ -2926,7 +2935,7 @@ static int stm32_setblendmode(FAR struct ltdc_layer_s *layer, uint32_t mode) } if (blendmode) { - gerr("Unknown blendmode %02x\n", blendmode); + lcderr("ERROR: Unknown blendmode %02x\n", blendmode); ret = -EINVAL; } @@ -2942,7 +2951,7 @@ static int stm32_setblendmode(FAR struct ltdc_layer_s *layer, uint32_t mode) return ret; } - gerr("Returning EINVAL\n"); + lcderr("ERROR: Returning EINVAL\n"); return -EINVAL; } @@ -2964,7 +2973,8 @@ static int stm32_setblendmode(FAR struct ltdc_layer_s *layer, uint32_t mode) static int stm32_getblendmode(FAR struct ltdc_layer_s *layer, uint32_t *mode) { FAR struct stm32_layer_s *priv = (FAR struct stm32_layer_s *)layer; - ginfo("layer = %p, mode = %p\n", layer, mode); + + lcdinfo("layer = %p, mode = %p\n", layer, mode); if (stm32_ltdc_lvalidate(priv)) { @@ -2975,7 +2985,7 @@ static int stm32_getblendmode(FAR struct ltdc_layer_s *layer, uint32_t *mode) return OK; } - gerr("Returning EINVAL\n"); + lcderr("ERROR: Returning EINVAL\n"); return -EINVAL; } @@ -3011,8 +3021,9 @@ static int stm32_setarea(FAR struct ltdc_layer_s *layer, fb_coord_t srcypos) { FAR struct stm32_layer_s *priv = (FAR struct stm32_layer_s *)layer; - ginfo("layer = %p, area = %p, srcxpos = %d, srcypos = %d\n", - layer, area, srcxpos, srcypos); + + lcdinfo("layer = %p, area = %p, srcxpos = %d, srcypos = %d\n", + layer, area, srcxpos, srcypos); if (stm32_ltdc_lvalidate(priv)) { @@ -3039,7 +3050,7 @@ static int stm32_setarea(FAR struct ltdc_layer_s *layer, return ret; } - gerr("Returning EINVAL\n"); + lcderr("ERROR: Returning EINVAL\n"); return -EINVAL; } @@ -3066,8 +3077,9 @@ static int stm32_getarea(FAR struct ltdc_layer_s *layer, fb_coord_t *srcxpos, fb_coord_t *srcypos) { FAR struct stm32_layer_s *priv = (FAR struct stm32_layer_s *)layer; - ginfo("layer = %p, area = %p, srcxpos = %p, srcypos = %p\n", - layer, area, srcxpos, srcypos); + + lcdinfo("layer = %p, area = %p, srcxpos = %p, srcypos = %p\n", + layer, area, srcxpos, srcypos); if (stm32_ltdc_lvalidate(priv)) { @@ -3080,7 +3092,7 @@ static int stm32_getarea(FAR struct ltdc_layer_s *layer, return OK; } - gerr("Returning EINVAL\n"); + lcderr("ERROR: Returning EINVAL\n"); return -EINVAL; } @@ -3131,7 +3143,7 @@ static int stm32_update(FAR struct ltdc_layer_s *layer, uint32_t mode) FAR struct stm32_layer_s *inactive = &LAYER(!g_lactive); #endif - ginfo("layer = %p, mode = %08x\n", layer, mode); + lcdinfo("layer = %p, mode = %08x\n", layer, mode); if (stm32_ltdc_lvalidate(priv)) { @@ -3156,7 +3168,7 @@ static int stm32_update(FAR struct ltdc_layer_s *layer, uint32_t mode) if (stm32_ltdc_waitforirq() != OK) { - gerr("Returning ECANCELED\n"); + lcderr("ERROR: Returning ECANCELED\n"); return -ECANCELED; } @@ -3238,7 +3250,7 @@ static int stm32_update(FAR struct ltdc_layer_s *layer, uint32_t mode) return OK; } - gerr("Returning EINVAL\n"); + lcderr("ERROR: Returning EINVAL\n"); return -EINVAL; } @@ -3272,8 +3284,8 @@ static int stm32_blit(FAR struct ltdc_layer_s *dest, { FAR struct stm32_layer_s *priv = (FAR struct stm32_layer_s *)dest; - ginfo("dest = %p, destxpos = %d, destypos = %d, src = %p, srcarea = %p\n", - dest, destxpos, destypos, src, srcarea); + lcdinfo("dest = %p, destxpos = %d, destypos = %d, src = %p, srcarea = %p\n", + dest, destxpos, destypos, src, srcarea); if (stm32_ltdc_lvalidate(priv)) { @@ -3286,7 +3298,7 @@ static int stm32_blit(FAR struct ltdc_layer_s *dest, return ret; } - gerr("Returning EINVAL\n"); + lcderr("ERROR: Returning EINVAL\n"); return -EINVAL; } @@ -3325,10 +3337,10 @@ static int stm32_blend(FAR struct ltdc_layer_s *dest, { FAR struct stm32_layer_s *priv = (FAR struct stm32_layer_s *)dest; - ginfo("dest=%p, destxpos=%d, destypos=%d, " - "fore=%p, forexpos=%d foreypos=%d, " - "back=%p, backarea=%p\n", - dest, destxpos, destypos, fore, forexpos, foreypos, back, backarea); + lcdinfo("dest=%p, destxpos=%d, destypos=%d, " + "fore=%p, forexpos=%d foreypos=%d, " + "back=%p, backarea=%p\n", + dest, destxpos, destypos, fore, forexpos, foreypos, back, backarea); if (stm32_ltdc_lvalidate(priv)) { @@ -3342,7 +3354,7 @@ static int stm32_blend(FAR struct ltdc_layer_s *dest, return ret; } - gerr("Returning EINVAL\n"); + lcderr("ERROR: Returning EINVAL\n"); return -EINVAL; } @@ -3370,7 +3382,8 @@ static int stm32_fillarea(FAR struct ltdc_layer_s *layer, uint32_t color) { FAR struct stm32_layer_s *priv = (FAR struct stm32_layer_s *)layer; - ginfo("layer = %p, area = %p, color = %08x\n", layer, area, color); + + lcdinfo("layer = %p, area = %p, color = %08x\n", layer, area, color); if (stm32_ltdc_lvalidate(priv)) { @@ -3383,7 +3396,7 @@ static int stm32_fillarea(FAR struct ltdc_layer_s *layer, return ret; } - gerr("Returning EINVAL\n"); + lcderr("ERROR: Returning EINVAL\n"); return -EINVAL; } #endif @@ -3407,13 +3420,14 @@ static int stm32_fillarea(FAR struct ltdc_layer_s *layer, FAR struct ltdc_layer_s *stm32_ltdcgetlayer(int lid) { - ginfo("lid: %d\n", lid); + lcdinfo("lid: %d\n", lid); + if (lid == LTDC_LAYER_L1 || lid == LTDC_LAYER_L2) { return (FAR struct ltdc_layer_s *) &LAYER(lid); } - gerr("EINVAL\n"); + lcderr("ERROR: Returning EINVAL\n"); errno = EINVAL; return NULL; } @@ -3436,7 +3450,7 @@ int stm32_ltdcinitialize(void) int ret; #endif - err("Initialize LTDC driver\n"); + lcdinfo("Initialize LTDC driver\n"); if (g_initialized == true) { @@ -3447,16 +3461,16 @@ int stm32_ltdcinitialize(void) stm32_lcd_enable(false); - ginfo("Configuring the LCD controller\n"); + lcdinfo("Configuring the LCD controller\n"); /* Configure LCD periphery */ - ginfo("Configure lcd periphery\n"); + lcdinfo("Configure lcd periphery\n"); stm32_ltdc_periphconfig(); /* Configure global ltdc register */ - ginfo("Configure global register\n"); + lcdinfo("Configure global register\n"); stm32_global_configure(); #ifdef CONFIG_STM32_DMA2D @@ -3472,7 +3486,7 @@ int stm32_ltdcinitialize(void) /* Initialize ltdc layer */ - ginfo("Initialize ltdc layer\n"); + lcdinfo("Initialize ltdc layer\n"); stm32_ltdc_linit(LTDC_LAYER_L1); #ifdef CONFIG_STM32_LTDC_L2 stm32_ltdc_linit(LTDC_LAYER_L2); @@ -3493,12 +3507,12 @@ int stm32_ltdcinitialize(void) /* Reload shadow register */ - ginfo("Reload shadow register\n"); + lcdinfo("Reload shadow register\n"); stm32_ltdc_reload(LTDC_SRCR_IMR, false); /* Turn the LCD on */ - ginfo("Enabling the display\n"); + lcdinfo("Enabling the display\n"); stm32_lcd_enable(true); /* Set initialized state */ @@ -3524,7 +3538,7 @@ int stm32_ltdcinitialize(void) struct fb_vtable_s *stm32_ltdcgetvplane(int vplane) { - ginfo("vplane: %d\n", vplane); + lcdinfo("vplane: %d\n", vplane); if (vplane == 0) { @@ -3600,6 +3614,6 @@ void stm32_backlight(bool blon) { /* Set default backlight level CONFIG_STM32_LTDC_DEFBACKLIGHT */ - gerr("Not supported\n"); + lcderr("ERROR: Not supported\n"); } #endif diff --git a/arch/arm/src/stm32/stm32_otgfsdev.c b/arch/arm/src/stm32/stm32_otgfsdev.c index 8481142f88..2d7912ac7b 100644 --- a/arch/arm/src/stm32/stm32_otgfsdev.c +++ b/arch/arm/src/stm32/stm32_otgfsdev.c @@ -81,6 +81,10 @@ # define CONFIG_USBDEV_MAXPOWER 100 /* mA */ #endif +#ifndef CONFIG_DEBUG_USB_INFO +# undef CONFIG_STM32_USBDEV_REGDEBUG +#endif + /* There is 1.25Kb of FIFO memory. The default partitions this memory * so that there is a TxFIFO allocated for each endpoint and with more * memory provided for the common RxFIFO. A more knowledge-able @@ -472,7 +476,7 @@ struct stm32_usbdev_s /* Register operations ********************************************************/ -#if defined(CONFIG_STM32_USBDEV_REGDEBUG) && defined(CONFIG_DEBUG_FEATURES) +#ifdef CONFIG_STM32_USBDEV_REGDEBUG static uint32_t stm32_getreg(uint32_t addr); static void stm32_putreg(uint32_t val, uint32_t addr); #else @@ -792,7 +796,7 @@ const struct trace_msg_t g_usb_trace_strings_intdecode[] = * ****************************************************************************/ -#if defined(CONFIG_STM32_USBDEV_REGDEBUG) && defined(CONFIG_DEBUG_FEATURES) +#ifdef CONFIG_STM32_USBDEV_REGDEBUG static uint32_t stm32_getreg(uint32_t addr) { static uint32_t prevaddr = 0; @@ -813,7 +817,7 @@ static uint32_t stm32_getreg(uint32_t addr) { if (count == 4) { - llerr("...\n"); + usbinfo("...\n"); } return val; @@ -830,7 +834,7 @@ static uint32_t stm32_getreg(uint32_t addr) { /* Yes.. then show how many times the value repeated */ - llerr("[repeats %d more times]\n", count-3); + usbinfo("[repeats %d more times]\n", count-3); } /* Save the new address, value, and count */ @@ -842,7 +846,7 @@ static uint32_t stm32_getreg(uint32_t addr) /* Show the register value read */ - llerr("%08x->%08x\n", addr, val); + usbinfo("%08x->%08x\n", addr, val); return val; } #endif @@ -855,12 +859,12 @@ static uint32_t stm32_getreg(uint32_t addr) * ****************************************************************************/ -#if defined(CONFIG_STM32_USBDEV_REGDEBUG) && defined(CONFIG_DEBUG_FEATURES) +#ifdef CONFIG_STM32_USBDEV_REGDEBUG static void stm32_putreg(uint32_t val, uint32_t addr) { /* Show the register value being written */ - llerr("%08x<-%08x\n", addr, val); + usbinfo("%08x<-%08x\n", addr, val); /* Write the value */ @@ -2625,7 +2629,7 @@ static inline void stm32_epout_interrupt(FAR struct stm32_usbdev_s *priv) if ((daint & 1) != 0) { regval = stm32_getreg(STM32_OTGFS_DOEPINT(epno)); - ullerr("DOEPINT(%d) = %08x\n", epno, regval); + ullinfo("DOEPINT(%d) = %08x\n", epno, regval); stm32_putreg(0xFF, STM32_OTGFS_DOEPINT(epno)); } @@ -2855,8 +2859,8 @@ static inline void stm32_epin_interrupt(FAR struct stm32_usbdev_s *priv) { if ((daint & 1) != 0) { - ullerr("DIEPINT(%d) = %08x\n", - epno, stm32_getreg(STM32_OTGFS_DIEPINT(epno))); + ullinfo("DIEPINT(%d) = %08x\n", + epno, stm32_getreg(STM32_OTGFS_DIEPINT(epno))); stm32_putreg(0xFF, STM32_OTGFS_DIEPINT(epno)); } @@ -3801,7 +3805,7 @@ static int stm32_epout_configure(FAR struct stm32_ep_s *privep, uint8_t eptype, break; default: - uerr("Unsupported maxpacket: %d\n", maxpacket); + uerr("ERROR: Unsupported maxpacket: %d\n", maxpacket); return -EINVAL; } } @@ -3896,7 +3900,7 @@ static int stm32_epin_configure(FAR struct stm32_ep_s *privep, uint8_t eptype, break; default: - uerr("Unsupported maxpacket: %d\n", maxpacket); + uerr("ERROR: Unsupported maxpacket: %d\n", maxpacket); return -EINVAL; } } @@ -5447,7 +5451,7 @@ void up_usbinitialize(void) ret = irq_attach(STM32_IRQ_OTGFS, stm32_usbinterrupt); if (ret < 0) { - uerr("irq_attach failed\n", ret); + uerr("ERROR: irq_attach failed\n", ret); goto errout; } diff --git a/arch/arm/src/stm32/stm32_otgfshost.c b/arch/arm/src/stm32/stm32_otgfshost.c index 912919a940..632ba36287 100644 --- a/arch/arm/src/stm32/stm32_otgfshost.c +++ b/arch/arm/src/stm32/stm32_otgfshost.c @@ -130,7 +130,7 @@ /* Register/packet debug depends on CONFIG_DEBUG_FEATURES */ -#ifndef CONFIG_DEBUG_FEATURES +#ifndef CONFIG_DEBUG_USB_INFO # undef CONFIG_STM32_USBHOST_REGDEBUG # undef CONFIG_STM32_USBHOST_PKTDUMP #endif @@ -506,7 +506,7 @@ static struct usbhost_connection_s g_usbconn = #ifdef CONFIG_STM32_USBHOST_REGDEBUG static void stm32_printreg(uint32_t addr, uint32_t val, bool iswrite) { - llerr("%08x%s%08x\n", addr, iswrite ? "<-" : "->", val); + usbinfo("%08x%s%08x\n", addr, iswrite ? "<-" : "->", val); } #endif @@ -556,7 +556,7 @@ static void stm32_checkreg(uint32_t addr, uint32_t val, bool iswrite) { /* No.. More than one. */ - llerr("[repeats %d more times]\n", count); + usbinfo("[repeats %d more times]\n", count); } } diff --git a/arch/arm/src/stm32/stm32_otghsdev.c b/arch/arm/src/stm32/stm32_otghsdev.c index 64b53eec4c..c8d146373a 100644 --- a/arch/arm/src/stm32/stm32_otghsdev.c +++ b/arch/arm/src/stm32/stm32_otghsdev.c @@ -81,6 +81,10 @@ # define CONFIG_USBDEV_MAXPOWER 100 /* mA */ #endif +#ifndef CONFIG_DEBUG_USB_INFO +# undef CONFIG_STM32_USBDEV_REGDEBUG +#endif + /* There is 1.25Kb of FIFO memory. The default partitions this memory * so that there is a TxFIFO allocated for each endpoint and with more * memory provided for the common RxFIFO. A more knowledge-able @@ -472,7 +476,7 @@ struct stm32_usbdev_s /* Register operations ********************************************************/ -#if defined(CONFIG_STM32_USBDEV_REGDEBUG) && defined(CONFIG_DEBUG_FEATURES) +#ifdef CONFIG_STM32_USBDEV_REGDEBUG static uint32_t stm32_getreg(uint32_t addr); static void stm32_putreg(uint32_t val, uint32_t addr); #else @@ -792,7 +796,7 @@ const struct trace_msg_t g_usb_trace_strings_intdecode[] = * ****************************************************************************/ -#if defined(CONFIG_STM32_USBDEV_REGDEBUG) && defined(CONFIG_DEBUG_FEATURES) +#ifdef CONFIG_STM32_USBDEV_REGDEBUG static uint32_t stm32_getreg(uint32_t addr) { static uint32_t prevaddr = 0; @@ -813,7 +817,7 @@ static uint32_t stm32_getreg(uint32_t addr) { if (count == 4) { - llerr("...\n"); + usbinfo("...\n"); } return val; @@ -830,7 +834,7 @@ static uint32_t stm32_getreg(uint32_t addr) { /* Yes.. then show how many times the value repeated */ - llerr("[repeats %d more times]\n", count-3); + usbinfo("[repeats %d more times]\n", count-3); } /* Save the new address, value, and count */ @@ -842,7 +846,7 @@ static uint32_t stm32_getreg(uint32_t addr) /* Show the register value read */ - llerr("%08x->%08x\n", addr, val); + usbinfo("%08x->%08x\n", addr, val); return val; } #endif @@ -855,12 +859,12 @@ static uint32_t stm32_getreg(uint32_t addr) * ****************************************************************************/ -#if defined(CONFIG_STM32_USBDEV_REGDEBUG) && defined(CONFIG_DEBUG_FEATURES) +#ifdef CONFIG_STM32_USBDEV_REGDEBUG static void stm32_putreg(uint32_t val, uint32_t addr) { /* Show the register value being written */ - llerr("%08x<-%08x\n", addr, val); + usbinfo("%08x<-%08x\n", addr, val); /* Write the value */ @@ -2625,7 +2629,7 @@ static inline void stm32_epout_interrupt(FAR struct stm32_usbdev_s *priv) if ((daint & 1) != 0) { regval = stm32_getreg(STM32_OTGHS_DOEPINT(epno)); - ullerr("DOEPINT(%d) = %08x\n", epno, regval); + ulinfo("("DOEPINT(%d) = %08x\n", epno, regval); stm32_putreg(0xFF, STM32_OTGHS_DOEPINT(epno)); } @@ -2855,7 +2859,7 @@ static inline void stm32_epin_interrupt(FAR struct stm32_usbdev_s *priv) { if ((daint & 1) != 0) { - ullerr("DIEPINT(%d) = %08x\n", + ulinfo("("DIEPINT(%d) = %08x\n", epno, stm32_getreg(STM32_OTGHS_DIEPINT(epno))); stm32_putreg(0xFF, STM32_OTGHS_DIEPINT(epno)); } @@ -3801,7 +3805,7 @@ static int stm32_epout_configure(FAR struct stm32_ep_s *privep, uint8_t eptype, break; default: - uerr("Unsupported maxpacket: %d\n", maxpacket); + uerr("ERROR: Unsupported maxpacket: %d\n", maxpacket); return -EINVAL; } } @@ -3896,7 +3900,7 @@ static int stm32_epin_configure(FAR struct stm32_ep_s *privep, uint8_t eptype, break; default: - uerr("Unsupported maxpacket: %d\n", maxpacket); + uerr("ERROR: Unsupported maxpacket: %d\n", maxpacket); return -EINVAL; } } @@ -5436,7 +5440,7 @@ void up_usbinitialize(void) ret = irq_attach(STM32_IRQ_OTGHS, stm32_usbinterrupt); if (ret < 0) { - uerr("irq_attach failed\n", ret); + uerr("ERROR: irq_attach failed\n", ret); goto errout; } diff --git a/arch/arm/src/stm32/stm32_otghshost.c b/arch/arm/src/stm32/stm32_otghshost.c index b93e185c96..42a68f6533 100644 --- a/arch/arm/src/stm32/stm32_otghshost.c +++ b/arch/arm/src/stm32/stm32_otghshost.c @@ -130,7 +130,7 @@ /* Register/packet debug depends on CONFIG_DEBUG_FEATURES */ -#ifndef CONFIG_DEBUG_FEATURES +#ifndef CONFIG_DEBUG_USB_INFO # undef CONFIG_STM32_USBHOST_REGDEBUG # undef CONFIG_STM32_USBHOST_PKTDUMP #endif @@ -506,7 +506,7 @@ static struct usbhost_connection_s g_usbconn = #ifdef CONFIG_STM32_USBHOST_REGDEBUG static void stm32_printreg(uint32_t addr, uint32_t val, bool iswrite) { - llerr("%08x%s%08x\n", addr, iswrite ? "<-" : "->", val); + usbinfo("%08x%s%08x\n", addr, iswrite ? "<-" : "->", val); } #endif @@ -556,7 +556,7 @@ static void stm32_checkreg(uint32_t addr, uint32_t val, bool iswrite) { /* No.. More than one. */ - llerr("[repeats %d more times]\n", count); + usbinfo("[repeats %d more times]\n", count); } } diff --git a/arch/arm/src/stm32/stm32_pwm.c b/arch/arm/src/stm32/stm32_pwm.c index 77534effa8..36f4aa4c13 100644 --- a/arch/arm/src/stm32/stm32_pwm.c +++ b/arch/arm/src/stm32/stm32_pwm.c @@ -1190,7 +1190,7 @@ static int pwm_timer(FAR struct stm32_pwmtimer_s *priv, break; default: - pwmerr("No such timer mode: %u\n", (unsigned int)priv->mode); + pwmerr("ERROR: No such timer mode: %u\n", (unsigned int)priv->mode); return -EINVAL; } } @@ -1317,7 +1317,7 @@ static int pwm_timer(FAR struct stm32_pwmtimer_s *priv, if (j >= PWM_NCHANNELS) { - pwmerr("No such channel: %u\n", channel); + pwmerr("ERROR: No such channel: %u\n", channel); return -EINVAL; } #else @@ -1368,7 +1368,7 @@ static int pwm_timer(FAR struct stm32_pwmtimer_s *priv, #endif default: - pwmerr("No such mode: %u\n", (unsigned int)mode); + pwmerr("ERROR: No such mode: %u\n", (unsigned int)mode); return -EINVAL; } @@ -1475,7 +1475,7 @@ static int pwm_timer(FAR struct stm32_pwmtimer_s *priv, break; default: - pwmerr("No such channel: %u\n", channel); + pwmerr("ERROR: No such channel: %u\n", channel); return -EINVAL; } } @@ -1688,7 +1688,7 @@ static int pwm_update_duty(FAR struct stm32_pwmtimer_s *priv, uint8_t channel, break; default: - pwmerr("No such channel: %u\n", channel); + pwmerr("ERROR: No such channel: %u\n", channel); return -EINVAL; } @@ -2508,7 +2508,7 @@ FAR struct pwm_lowerhalf_s *stm32_pwminitialize(int timer) #endif default: - pwmerr("No such timer configured\n"); + pwmerr("ERROR: No such timer configured\n"); return NULL; } diff --git a/arch/arm/src/stm32/stm32_qencoder.c b/arch/arm/src/stm32/stm32_qencoder.c index 584ea46a47..7d87debe33 100644 --- a/arch/arm/src/stm32/stm32_qencoder.c +++ b/arch/arm/src/stm32/stm32_qencoder.c @@ -1270,7 +1270,7 @@ int stm32_qeinitialize(FAR const char *devpath, int tim) priv = stm32_tim2lower(tim); if (!priv) { - snerr("TIM%d support not configured\n", tim); + snerr("ERROR: TIM%d support not configured\n", tim); return -ENXIO; } @@ -1278,7 +1278,7 @@ int stm32_qeinitialize(FAR const char *devpath, int tim) if (priv->inuse) { - snerr("TIM%d is in-used\n", tim); + snerr("ERROR: TIM%d is in-use\n", tim); return -EBUSY; } @@ -1287,7 +1287,7 @@ int stm32_qeinitialize(FAR const char *devpath, int tim) ret = qe_register(devpath, (FAR struct qe_lowerhalf_s *)priv); if (ret < 0) { - snerr("qe_register failed: %d\n", ret); + snerr("ERROR: qe_register failed: %d\n", ret); return ret; } diff --git a/arch/arm/src/stm32/stm32_rtcc.c b/arch/arm/src/stm32/stm32_rtcc.c index 602ff7099d..bbb2137ab7 100644 --- a/arch/arm/src/stm32/stm32_rtcc.c +++ b/arch/arm/src/stm32/stm32_rtcc.c @@ -711,13 +711,13 @@ int up_rtc_initialize(void) { case OK: { - rtcllerr("rtc_syncwait() okay\n"); + rtcllinfo("rtc_syncwait() okay\n"); break; } default: { - rtcllerr("rtc_syncwait() failed (%d)\n", ret); + rtcllerr("ERROR: rtc_syncwait() failed (%d)\n", ret); break; } } @@ -731,7 +731,7 @@ int up_rtc_initialize(void) if (regval != RTC_MAGIC) { - rtcllerr("Do setup\n"); + rtcllinfo("Do setup\n"); /* Perform the one-time setup of the LSE clocking to the RTC */ @@ -749,7 +749,7 @@ int up_rtc_initialize(void) } else { - rtcllerr("Do resume\n"); + rtcllinfo("Do resume\n"); /* RTC already set-up, just resume normal operation */ @@ -765,7 +765,7 @@ int up_rtc_initialize(void) if (ret != OK && nretry > 0) { - rtcllerr("setup/resume ran %d times and failed with %d\n", + rtcllinfo("setup/resume ran %d times and failed with %d\n", nretry, ret); return -ETIMEDOUT; } diff --git a/arch/arm/src/stm32/stm32_sdio.c b/arch/arm/src/stm32/stm32_sdio.c index 7fdf1c6cae..d1317e611e 100644 --- a/arch/arm/src/stm32/stm32_sdio.c +++ b/arch/arm/src/stm32/stm32_sdio.c @@ -139,7 +139,7 @@ # undef CONFIG_SDIO_DMAPRIO #endif -#if !defined(CONFIG_DEBUG_FS) || !defined(CONFIG_DEBUG_FEATURES) +#ifndef CONFIG_DEBUG_MEMCARD_INFO # undef CONFIG_SDIO_XFRDEBUG #endif @@ -596,7 +596,7 @@ static inline void stm32_setclkcr(uint32_t clkcr) regval |= clkcr; putreg32(regval, STM32_SDIO_CLKCR); - finfo("CLKCR: %08x PWR: %08x\n", + mcinfo("CLKCR: %08x PWR: %08x\n", getreg32(STM32_SDIO_CLKCR), getreg32(STM32_SDIO_POWER)); } @@ -812,16 +812,16 @@ static void stm32_sample(struct stm32_dev_s *priv, int index) #ifdef CONFIG_SDIO_XFRDEBUG static void stm32_sdiodump(struct stm32_sdioregs_s *regs, const char *msg) { - ferr("SDIO Registers: %s\n", msg); - ferr(" POWER[%08x]: %08x\n", STM32_SDIO_POWER, regs->power); - ferr(" CLKCR[%08x]: %08x\n", STM32_SDIO_CLKCR, regs->clkcr); - ferr(" DCTRL[%08x]: %08x\n", STM32_SDIO_DCTRL, regs->dctrl); - ferr(" DTIMER[%08x]: %08x\n", STM32_SDIO_DTIMER, regs->dtimer); - ferr(" DLEN[%08x]: %08x\n", STM32_SDIO_DLEN, regs->dlen); - ferr(" DCOUNT[%08x]: %08x\n", STM32_SDIO_DCOUNT, regs->dcount); - ferr(" STA[%08x]: %08x\n", STM32_SDIO_STA, regs->sta); - ferr(" MASK[%08x]: %08x\n", STM32_SDIO_MASK, regs->mask); - ferr("FIFOCNT[%08x]: %08x\n", STM32_SDIO_FIFOCNT, regs->fifocnt); + mcinfo("SDIO Registers: %s\n", msg); + mcinfo(" POWER[%08x]: %08x\n", STM32_SDIO_POWER, regs->power); + mcinfo(" CLKCR[%08x]: %08x\n", STM32_SDIO_CLKCR, regs->clkcr); + mcinfo(" DCTRL[%08x]: %08x\n", STM32_SDIO_DCTRL, regs->dctrl); + mcinfo(" DTIMER[%08x]: %08x\n", STM32_SDIO_DTIMER, regs->dtimer); + mcinfo(" DLEN[%08x]: %08x\n", STM32_SDIO_DLEN, regs->dlen); + mcinfo(" DCOUNT[%08x]: %08x\n", STM32_SDIO_DCOUNT, regs->dcount); + mcinfo(" STA[%08x]: %08x\n", STM32_SDIO_STA, regs->sta); + mcinfo(" MASK[%08x]: %08x\n", STM32_SDIO_MASK, regs->mask); + mcinfo("FIFOCNT[%08x]: %08x\n", STM32_SDIO_FIFOCNT, regs->fifocnt); } #endif @@ -907,7 +907,7 @@ static void stm32_dmacallback(DMA_HANDLE handle, uint8_t status, void *arg) if ((status & DMA_STATUS_ERROR) != 0) { - fllerr("DMA error %02x, remaining: %d\n", status, priv->remaining); + mcllerr("ERROR: DMA error %02x, remaining: %d\n", status, priv->remaining); result = SDIOWAIT_ERROR; } else @@ -1172,7 +1172,7 @@ static void stm32_eventtimeout(int argc, uint32_t arg) /* Yes.. wake up any waiting threads */ stm32_endwait(priv, SDIOWAIT_TIMEOUT); - fllerr("Timeout: remaining: %d\n", priv->remaining); + mcllerr("ERROR: Timeout, remaining: %d\n", priv->remaining); } } @@ -1412,7 +1412,7 @@ static int stm32_interrupt(int irq, void *context) { /* Terminate the transfer with an error */ - fllerr("ERROR: Data block CRC failure, remaining: %d\n", priv->remaining); + mcllerr("ERROR: Data block CRC failure, remaining: %d\n", priv->remaining); stm32_endtransfer(priv, SDIOWAIT_TRANSFERDONE | SDIOWAIT_ERROR); } @@ -1422,7 +1422,7 @@ static int stm32_interrupt(int irq, void *context) { /* Terminate the transfer with an error */ - fllerr("ERROR: Data timeout, remaining: %d\n", priv->remaining); + mcllerr("ERROR: Data timeout, remaining: %d\n", priv->remaining); stm32_endtransfer(priv, SDIOWAIT_TRANSFERDONE | SDIOWAIT_TIMEOUT); } @@ -1432,7 +1432,7 @@ static int stm32_interrupt(int irq, void *context) { /* Terminate the transfer with an error */ - fllerr("ERROR: RX FIFO overrun, remaining: %d\n", priv->remaining); + mcllerr("ERROR: RX FIFO overrun, remaining: %d\n", priv->remaining); stm32_endtransfer(priv, SDIOWAIT_TRANSFERDONE | SDIOWAIT_ERROR); } @@ -1442,7 +1442,7 @@ static int stm32_interrupt(int irq, void *context) { /* Terminate the transfer with an error */ - fllerr("ERROR: TX FIFO underrun, remaining: %d\n", priv->remaining); + mcllerr("ERROR: TX FIFO underrun, remaining: %d\n", priv->remaining); stm32_endtransfer(priv, SDIOWAIT_TRANSFERDONE | SDIOWAIT_ERROR); } @@ -1452,7 +1452,7 @@ static int stm32_interrupt(int irq, void *context) { /* Terminate the transfer with an error */ - fllerr("ERROR: Start bit, remaining: %d\n", priv->remaining); + mcllerr("ERROR: Start bit, remaining: %d\n", priv->remaining); stm32_endtransfer(priv, SDIOWAIT_TRANSFERDONE | SDIOWAIT_ERROR); } } @@ -1588,8 +1588,8 @@ static void stm32_reset(FAR struct sdio_dev_s *dev) stm32_setpwrctrl(SDIO_POWER_PWRCTRL_ON); leave_critical_section(flags); - finfo("CLCKR: %08x POWER: %08x\n", - getreg32(STM32_SDIO_CLKCR), getreg32(STM32_SDIO_POWER)); + mcinfo("CLCKR: %08x POWER: %08x\n", + getreg32(STM32_SDIO_CLKCR), getreg32(STM32_SDIO_POWER)); } /**************************************************************************** @@ -1801,7 +1801,7 @@ static int stm32_sendcmd(FAR struct sdio_dev_s *dev, uint32_t cmd, uint32_t arg) cmdidx = (cmd & MMCSD_CMDIDX_MASK) >> MMCSD_CMDIDX_SHIFT; regval |= cmdidx | SDIO_CMD_CPSMEN; - finfo("cmd: %08x arg: %08x regval: %08x\n", cmd, arg, regval); + mcinfo("cmd: %08x arg: %08x regval: %08x\n", cmd, arg, regval); /* Write the SDIO CMD */ @@ -2031,7 +2031,7 @@ static int stm32_waitresponse(FAR struct sdio_dev_s *dev, uint32_t cmd) { if (--timeout <= 0) { - ferr("ERROR: Timeout cmd: %08x events: %08x STA: %08x\n", + mcerr("ERROR: Timeout cmd: %08x events: %08x STA: %08x\n", cmd, events, getreg32(STM32_SDIO_STA)); return -ETIMEDOUT; @@ -2066,7 +2066,7 @@ static int stm32_waitresponse(FAR struct sdio_dev_s *dev, uint32_t cmd) static int stm32_recvshortcrc(FAR struct sdio_dev_s *dev, uint32_t cmd, uint32_t *rshort) { -#ifdef CONFIG_DEBUG_FEATURES +#ifdef CONFIG_DEBUG_MEMCARD_INFO uint32_t respcmd; #endif uint32_t regval; @@ -2095,10 +2095,10 @@ static int stm32_recvshortcrc(FAR struct sdio_dev_s *dev, uint32_t cmd, uint32_t */ -#ifdef CONFIG_DEBUG_FEATURES +#ifdef CONFIG_DEBUG_MEMCARD_INFO if (!rshort) { - ferr("ERROR: rshort=NULL\n"); + mcerr("ERROR: rshort=NULL\n"); ret = -EINVAL; } @@ -2108,7 +2108,7 @@ static int stm32_recvshortcrc(FAR struct sdio_dev_s *dev, uint32_t cmd, uint32_t (cmd & MMCSD_RESPONSE_MASK) != MMCSD_R1B_RESPONSE && (cmd & MMCSD_RESPONSE_MASK) != MMCSD_R6_RESPONSE) { - ferr("ERROR: Wrong response CMD=%08x\n", cmd); + mcerr("ERROR: Wrong response CMD=%08x\n", cmd); ret = -EINVAL; } else @@ -2119,15 +2119,15 @@ static int stm32_recvshortcrc(FAR struct sdio_dev_s *dev, uint32_t cmd, uint32_t regval = getreg32(STM32_SDIO_STA); if ((regval & SDIO_STA_CTIMEOUT) != 0) { - ferr("ERROR: Command timeout: %08x\n", regval); + mcerr("ERROR: Command timeout: %08x\n", regval); ret = -ETIMEDOUT; } else if ((regval & SDIO_STA_CCRCFAIL) != 0) { - ferr("ERROR: CRC failure: %08x\n", regval); + mcerr("ERROR: CRC failure: %08x\n", regval); ret = -EIO; } -#ifdef CONFIG_DEBUG_FEATURES +#ifdef CONFIG_DEBUG_MEMCARD_INFO else { /* Check response received is of desired command */ @@ -2135,7 +2135,7 @@ static int stm32_recvshortcrc(FAR struct sdio_dev_s *dev, uint32_t cmd, uint32_t respcmd = getreg32(STM32_SDIO_RESPCMD); if ((uint8_t)(respcmd & SDIO_RESPCMD_MASK) != (cmd & MMCSD_CMDIDX_MASK)) { - ferr("ERROR: RESCMD=%02x CMD=%08x\n", respcmd, cmd); + mcerr("ERROR: RESCMD=%02x CMD=%08x\n", respcmd, cmd); ret = -EINVAL; } } @@ -2163,12 +2163,12 @@ static int stm32_recvlong(FAR struct sdio_dev_s *dev, uint32_t cmd, uint32_t rlo * 0 1 End bit */ -#ifdef CONFIG_DEBUG_FEATURES +#ifdef CONFIG_DEBUG_MEMCARD_INFO /* Check that R1 is the correct response to this command */ if ((cmd & MMCSD_RESPONSE_MASK) != MMCSD_R2_RESPONSE) { - ferr("ERROR: Wrong response CMD=%08x\n", cmd); + mcerr("ERROR: Wrong response CMD=%08x\n", cmd); ret = -EINVAL; } else @@ -2179,12 +2179,12 @@ static int stm32_recvlong(FAR struct sdio_dev_s *dev, uint32_t cmd, uint32_t rlo regval = getreg32(STM32_SDIO_STA); if (regval & SDIO_STA_CTIMEOUT) { - ferr("ERROR: Timeout STA: %08x\n", regval); + mcerr("ERROR: Timeout STA: %08x\n", regval); ret = -ETIMEDOUT; } else if (regval & SDIO_STA_CCRCFAIL) { - ferr("ERROR: CRC fail STA: %08x\n", regval); + mcerr("ERROR: CRC fail STA: %08x\n", regval); ret = -EIO; } } @@ -2218,11 +2218,11 @@ static int stm32_recvshort(FAR struct sdio_dev_s *dev, uint32_t cmd, uint32_t *r /* Check that this is the correct response to this command */ -#ifdef CONFIG_DEBUG_FEATURES +#ifdef CONFIG_DEBUG_MEMCARD_INFO if ((cmd & MMCSD_RESPONSE_MASK) != MMCSD_R3_RESPONSE && (cmd & MMCSD_RESPONSE_MASK) != MMCSD_R7_RESPONSE) { - ferr("ERROR: Wrong response CMD=%08x\n", cmd); + mcerr("ERROR: Wrong response CMD=%08x\n", cmd); ret = -EINVAL; } else @@ -2235,7 +2235,7 @@ static int stm32_recvshort(FAR struct sdio_dev_s *dev, uint32_t cmd, uint32_t *r regval = getreg32(STM32_SDIO_STA); if (regval & SDIO_STA_CTIMEOUT) { - ferr("ERROR: Timeout STA: %08x\n", regval); + mcerr("ERROR: Timeout STA: %08x\n", regval); ret = -ETIMEDOUT; } } @@ -2390,7 +2390,7 @@ static sdio_eventset_t stm32_eventwait(FAR struct sdio_dev_s *dev, 1, (uint32_t)priv); if (ret != OK) { - ferr("ERROR: wd_start failed: %d\n", ret); + mcerr("ERROR: wd_start failed: %d\n", ret); } } @@ -2477,7 +2477,7 @@ static void stm32_callbackenable(FAR struct sdio_dev_s *dev, { struct stm32_dev_s *priv = (struct stm32_dev_s *)dev; - finfo("eventset: %02x\n", eventset); + mcinfo("eventset: %02x\n", eventset); DEBUGASSERT(priv != NULL); priv->cbevents = eventset; @@ -2513,7 +2513,7 @@ static int stm32_registercallback(FAR struct sdio_dev_s *dev, /* Disable callbacks and register this callback and is argument */ - finfo("Register %p(%p)\n", callback, arg); + mcinfo("Register %p(%p)\n", callback, arg); DEBUGASSERT(priv != NULL); priv->cbevents = 0; @@ -2749,8 +2749,8 @@ static void stm32_callback(void *arg) /* Is a callback registered? */ DEBUGASSERT(priv != NULL); - finfo("Callback %p(%p) cbevents: %02x cdstatus: %02x\n", - priv->callback, priv->cbarg, priv->cbevents, priv->cdstatus); + mcinfo("Callback %p(%p) cbevents: %02x cdstatus: %02x\n", + priv->callback, priv->cbarg, priv->cbevents, priv->cdstatus); if (priv->callback) { @@ -2794,14 +2794,14 @@ static void stm32_callback(void *arg) { /* Yes.. queue it */ - finfo("Queuing callback to %p(%p)\n", priv->callback, priv->cbarg); + mcinfo("Queuing callback to %p(%p)\n", priv->callback, priv->cbarg); (void)work_queue(HPWORK, &priv->cbwork, (worker_t)priv->callback, priv->cbarg, 0); } else { /* No.. then just call the callback here */ - finfo("Callback to %p(%p)\n", priv->callback, priv->cbarg); + mcinfo("Callback to %p(%p)\n", priv->callback, priv->cbarg); priv->callback(priv->cbarg); } } @@ -2931,7 +2931,7 @@ void sdio_mediachange(FAR struct sdio_dev_s *dev, bool cardinslot) leave_critical_section(flags); - finfo("cdstatus OLD: %02x NEW: %02x\n", cdstatus, priv->cdstatus); + mcinfo("cdstatus OLD: %02x NEW: %02x\n", cdstatus, priv->cdstatus); /* Perform any requested callback if the status has changed */ @@ -2973,7 +2973,8 @@ void sdio_wrprotect(FAR struct sdio_dev_s *dev, bool wrprotect) { priv->cdstatus &= ~SDIO_STATUS_WRPROTECTED; } - finfo("cdstatus: %02x\n", priv->cdstatus); + + mcinfo("cdstatus: %02x\n", priv->cdstatus); leave_critical_section(flags); } #endif /* CONFIG_STM32_SDIO */ diff --git a/arch/arm/src/stm32/stm32_usbdev.c b/arch/arm/src/stm32/stm32_usbdev.c index b219a93e6c..ec8be78bcc 100644 --- a/arch/arm/src/stm32/stm32_usbdev.c +++ b/arch/arm/src/stm32/stm32_usbdev.c @@ -103,7 +103,7 @@ * enabled. */ -#ifndef CONFIG_DEBUG_FEATURES +#ifndef CONFIG_DEBUG_USB_INFO # undef CONFIG_STM32_USBDEV_REGDEBUG #endif @@ -388,7 +388,7 @@ struct stm32_usbdev_s /* Register operations ******************************************************/ -#if defined(CONFIG_STM32_USBDEV_REGDEBUG) && defined(CONFIG_DEBUG_FEATURES) +#ifdef CONFIG_STM32_USBDEV_REGDEBUG static uint16_t stm32_getreg(uint32_t addr); static void stm32_putreg(uint16_t val, uint32_t addr); static void stm32_checksetup(void); @@ -648,11 +648,12 @@ const struct trace_msg_t g_usb_trace_strings_deverror[] = /**************************************************************************** * Register Operations ****************************************************************************/ + /**************************************************************************** * Name: stm32_getreg ****************************************************************************/ -#if defined(CONFIG_STM32_USBDEV_REGDEBUG) && defined(CONFIG_DEBUG_FEATURES) +#ifdef CONFIG_STM32_USBDEV_REGDEBUG static uint16_t stm32_getreg(uint32_t addr) { static uint32_t prevaddr = 0; @@ -673,7 +674,7 @@ static uint16_t stm32_getreg(uint32_t addr) { if (count == 4) { - llerr("...\n"); + usbinfo("...\n"); } return val; } @@ -689,7 +690,7 @@ static uint16_t stm32_getreg(uint32_t addr) { /* Yes.. then show how many times the value repeated */ - llerr("[repeats %d more times]\n", count-3); + usbinfo("[repeats %d more times]\n", count-3); } /* Save the new address, value, and count */ @@ -701,7 +702,7 @@ static uint16_t stm32_getreg(uint32_t addr) /* Show the register value read */ - llerr("%08x->%04x\n", addr, val); + usbinfo("%08x->%04x\n", addr, val); return val; } #endif @@ -710,12 +711,12 @@ static uint16_t stm32_getreg(uint32_t addr) * Name: stm32_putreg ****************************************************************************/ -#if defined(CONFIG_STM32_USBDEV_REGDEBUG) && defined(CONFIG_DEBUG_FEATURES) +#ifdef CONFIG_STM32_USBDEV_REGDEBUG static void stm32_putreg(uint16_t val, uint32_t addr) { /* Show the register value being written */ - llerr("%08x<-%04x\n", addr, val); + usbinfo("%08x<-%04x\n", addr, val); /* Write the value */ @@ -727,42 +728,42 @@ static void stm32_putreg(uint16_t val, uint32_t addr) * Name: stm32_dumpep ****************************************************************************/ -#if defined(CONFIG_STM32_USBDEV_REGDEBUG) && defined(CONFIG_DEBUG_FEATURES) +#ifdef CONFIG_STM32_USBDEV_REGDEBUG static void stm32_dumpep(int epno) { uint32_t addr; /* Common registers */ - llerr("CNTR: %04x\n", getreg16(STM32_USB_CNTR)); - llerr("ISTR: %04x\n", getreg16(STM32_USB_ISTR)); - llerr("FNR: %04x\n", getreg16(STM32_USB_FNR)); - llerr("DADDR: %04x\n", getreg16(STM32_USB_DADDR)); - llerr("BTABLE: %04x\n", getreg16(STM32_USB_BTABLE)); + usbinfo("CNTR: %04x\n", getreg16(STM32_USB_CNTR)); + usbinfo("ISTR: %04x\n", getreg16(STM32_USB_ISTR)); + usbinfo("FNR: %04x\n", getreg16(STM32_USB_FNR)); + usbinfo("DADDR: %04x\n", getreg16(STM32_USB_DADDR)); + usbinfo("BTABLE: %04x\n", getreg16(STM32_USB_BTABLE)); /* Endpoint register */ addr = STM32_USB_EPR(epno); - llerr("EPR%d: [%08x] %04x\n", epno, addr, getreg16(addr)); + usbinfo("EPR%d: [%08x] %04x\n", epno, addr, getreg16(addr)); /* Endpoint descriptor */ addr = STM32_USB_BTABLE_ADDR(epno, 0); - llerr("DESC: %08x\n", addr); + usbinfo("DESC: %08x\n", addr); /* Endpoint buffer descriptor */ addr = STM32_USB_ADDR_TX(epno); - llerr(" TX ADDR: [%08x] %04x\n", addr, getreg16(addr)); + usbinfo(" TX ADDR: [%08x] %04x\n", addr, getreg16(addr)); addr = STM32_USB_COUNT_TX(epno); - llerr(" COUNT: [%08x] %04x\n", addr, getreg16(addr)); + usbinfo(" COUNT: [%08x] %04x\n", addr, getreg16(addr)); addr = STM32_USB_ADDR_RX(epno); - llerr(" RX ADDR: [%08x] %04x\n", addr, getreg16(addr)); + usbinfo(" RX ADDR: [%08x] %04x\n", addr, getreg16(addr)); addr = STM32_USB_COUNT_RX(epno); - llerr(" COUNT: [%08x] %04x\n", addr, getreg16(addr)); + usbinfo(" COUNT: [%08x] %04x\n", addr, getreg16(addr)); } #endif @@ -770,19 +771,19 @@ static void stm32_dumpep(int epno) * Name: stm32_checksetup ****************************************************************************/ -#if defined(CONFIG_STM32_USBDEV_REGDEBUG) && defined(CONFIG_DEBUG_FEATURES) +#ifdef CONFIG_STM32_USBDEV_REGDEBUG static void stm32_checksetup(void) { uint32_t cfgr = getreg32(STM32_RCC_CFGR); uint32_t apb1rstr = getreg32(STM32_RCC_APB1RSTR); uint32_t apb1enr = getreg32(STM32_RCC_APB1ENR); - llerr("CFGR: %08x APB1RSTR: %08x APB1ENR: %08x\n", cfgr, apb1rstr, apb1enr); + usbinfo("CFGR: %08x APB1RSTR: %08x APB1ENR: %08x\n", cfgr, apb1rstr, apb1enr); if ((apb1rstr & RCC_APB1RSTR_USBRST) != 0 || (apb1enr & RCC_APB1ENR_USBEN) == 0) { - llerr("ERROR: USB is NOT setup correctly\n"); + usbinfo("ERROR: USB is NOT setup correctly\n"); } } #endif @@ -2844,7 +2845,7 @@ static int stm32_epconfigure(struct usbdev_ep_s *ep, if (!ep || !desc) { usbtrace(TRACE_DEVERROR(STM32_TRACEERR_INVALIDPARMS), 0); - ullerr("ERROR: ep=%p desc=%p\n"); + uusbinfo("ERROR: ep=%p desc=%p\n"); return -EINVAL; } #endif @@ -2940,7 +2941,7 @@ static int stm32_epdisable(struct usbdev_ep_s *ep) if (!ep) { usbtrace(TRACE_DEVERROR(STM32_TRACEERR_INVALIDPARMS), 0); - ullerr("ERROR: ep=%p\n", ep); + uusbinfo("ERROR: ep=%p\n", ep); return -EINVAL; } #endif @@ -3028,7 +3029,7 @@ static int stm32_epsubmit(struct usbdev_ep_s *ep, struct usbdev_req_s *req) if (!req || !req->callback || !req->buf || !ep) { usbtrace(TRACE_DEVERROR(STM32_TRACEERR_INVALIDPARMS), 0); - ullerr("ERROR: req=%p callback=%p buf=%p ep=%p\n", req, req->callback, req->buf, ep); + uusbinfo("ERROR: req=%p callback=%p buf=%p ep=%p\n", req, req->callback, req->buf, ep); return -EINVAL; } #endif @@ -3040,7 +3041,7 @@ static int stm32_epsubmit(struct usbdev_ep_s *ep, struct usbdev_req_s *req) if (!priv->driver) { usbtrace(TRACE_DEVERROR(STM32_TRACEERR_NOTCONFIGURED), priv->usbdev.speed); - ullerr("ERROR: driver=%p\n", priv->driver); + uusbinfo("ERROR: driver=%p\n", priv->driver); return -ESHUTDOWN; } #endif @@ -3057,7 +3058,7 @@ static int stm32_epsubmit(struct usbdev_ep_s *ep, struct usbdev_req_s *req) if (privep->stalled) { stm32_abortrequest(privep, privreq, -EBUSY); - ullerr("ERROR: stalled\n"); + uusbinfo("ERROR: stalled\n"); ret = -EBUSY; } @@ -3136,7 +3137,7 @@ static int stm32_epcancel(struct usbdev_ep_s *ep, struct usbdev_req_s *req) struct stm32_ep_s *privep = (struct stm32_ep_s *)ep; irqstate_t flags; -#ifdef CONFIG_DEBUG_FEATURES +#ifdef CONFIG_DEBUG_USB if (!ep || !req) { usbtrace(TRACE_DEVERROR(STM32_TRACEERR_INVALIDPARMS), 0); @@ -3163,7 +3164,7 @@ static int stm32_epstall(struct usbdev_ep_s *ep, bool resume) uint16_t status; irqstate_t flags; -#ifdef CONFIG_DEBUG_FEATURES +#ifdef CONFIG_DEBUG_USB if (!ep) { usbtrace(TRACE_DEVERROR(STM32_TRACEERR_INVALIDPARMS), 0); @@ -3305,7 +3306,7 @@ static struct usbdev_ep_s *stm32_allocep(struct usbdev_s *dev, uint8_t epno, int bufno; usbtrace(TRACE_DEVALLOCEP, (uint16_t)epno); -#ifdef CONFIG_DEBUG_FEATURES +#ifdef CONFIG_DEBUG_USB if (!dev) { usbtrace(TRACE_DEVERROR(STM32_TRACEERR_INVALIDPARMS), 0); @@ -3379,7 +3380,7 @@ static void stm32_freeep(struct usbdev_s *dev, struct usbdev_ep_s *ep) struct stm32_usbdev_s *priv; struct stm32_ep_s *privep; -#ifdef CONFIG_DEBUG_FEATURES +#ifdef CONFIG_DEBUG_USB if (!dev || !ep) { usbtrace(TRACE_DEVERROR(STM32_TRACEERR_INVALIDPARMS), 0); @@ -3410,7 +3411,7 @@ static int stm32_getframe(struct usbdev_s *dev) { uint16_t fnr; -#ifdef CONFIG_DEBUG_FEATURES +#ifdef CONFIG_DEBUG_USB if (!dev) { usbtrace(TRACE_DEVERROR(STM32_TRACEERR_INVALIDPARMS), 0); @@ -3435,7 +3436,7 @@ static int stm32_wakeup(struct usbdev_s *dev) irqstate_t flags; usbtrace(TRACE_DEVWAKEUP, 0); -#ifdef CONFIG_DEBUG_FEATURES +#ifdef CONFIG_DEBUG_USB if (!dev) { usbtrace(TRACE_DEVERROR(STM32_TRACEERR_INVALIDPARMS), 0); @@ -3473,7 +3474,7 @@ static int stm32_selfpowered(struct usbdev_s *dev, bool selfpowered) usbtrace(TRACE_DEVSELFPOWERED, (uint16_t)selfpowered); -#ifdef CONFIG_DEBUG_FEATURES +#ifdef CONFIG_DEBUG_USB if (!dev) { usbtrace(TRACE_DEVERROR(STM32_TRACEERR_INVALIDPARMS), 0); @@ -3834,7 +3835,7 @@ int usbdev_register(struct usbdevclass_driver_s *driver) usbtrace(TRACE_DEVREGISTER, 0); -#ifdef CONFIG_DEBUG_FEATURES +#ifdef CONFIG_DEBUG_USB if (!driver || !driver->ops->bind || !driver->ops->unbind || !driver->ops->disconnect || !driver->ops->setup) { @@ -3912,7 +3913,7 @@ int usbdev_unregister(struct usbdevclass_driver_s *driver) usbtrace(TRACE_DEVUNREGISTER, 0); -#ifdef CONFIG_DEBUG_FEATURES +#ifdef CONFIG_DEBUG_USB if (driver != priv->driver) { usbtrace(TRACE_DEVERROR(STM32_TRACEERR_INVALIDPARMS), 0); diff --git a/arch/arm/src/stm32/stm32_wwdg.c b/arch/arm/src/stm32/stm32_wwdg.c index 116d8d56ac..6c98299743 100644 --- a/arch/arm/src/stm32/stm32_wwdg.c +++ b/arch/arm/src/stm32/stm32_wwdg.c @@ -81,6 +81,10 @@ # define CONFIG_STM32_WWDG_DEFTIMOUT WWDG_MAXTIMEOUT #endif +#ifndef CONFIG_DEBUG_WATCHDOG_INFO +# undef CONFIG_STM32_WWDG_REGDEBUG +#endif + /**************************************************************************** * Private Types ****************************************************************************/ @@ -105,7 +109,7 @@ struct stm32_lowerhalf_s ****************************************************************************/ /* Register operations ******************************************************/ -#if defined(CONFIG_STM32_WWDG_REGDEBUG) && defined(CONFIG_DEBUG_FEATURES) +#ifdef CONFIG_STM32_WWDG_REGDEBUG static uint16_t stm32_getreg(uint32_t addr); static void stm32_putreg(uint16_t val, uint32_t addr); #else @@ -165,7 +169,7 @@ static struct stm32_lowerhalf_s g_wdgdev; * ****************************************************************************/ -#if defined(CONFIG_STM32_WWDG_REGDEBUG) && defined(CONFIG_DEBUG_FEATURES) +#ifdef CONFIG_STM32_WWDG_REGDEBUG static uint16_t stm32_getreg(uint32_t addr) { static uint32_t prevaddr = 0; @@ -186,7 +190,7 @@ static uint16_t stm32_getreg(uint32_t addr) { if (count == 4) { - llerr("...\n"); + wdinfo("...\n"); } return val; @@ -203,7 +207,7 @@ static uint16_t stm32_getreg(uint32_t addr) { /* Yes.. then show how many times the value repeated */ - llerr("[repeats %d more times]\n", count-3); + wdinfo("[repeats %d more times]\n", count-3); } /* Save the new address, value, and count */ @@ -215,7 +219,7 @@ static uint16_t stm32_getreg(uint32_t addr) /* Show the register value read */ - llerr("%08x->%04x\n", addr, val); + wdinfo("%08x->%04x\n", addr, val); return val; } #endif @@ -228,12 +232,12 @@ static uint16_t stm32_getreg(uint32_t addr) * ****************************************************************************/ -#if defined(CONFIG_STM32_WWDG_REGDEBUG) && defined(CONFIG_DEBUG_FEATURES) +#ifdef CONFIG_STM32_WWDG_REGDEBUG static void stm32_putreg(uint16_t val, uint32_t addr) { /* Show the register value being written */ - llerr("%08x<-%04x\n", addr, val); + wdinfo("%08x<-%04x\n", addr, val); /* Write the value */ @@ -499,7 +503,7 @@ static int stm32_settimeout(FAR struct watchdog_lowerhalf_s *lower, if (timeout < 1 || timeout > WWDG_MAXTIMEOUT) { - wderr("Cannot represent timeout=%d > %d\n", + wderr("ERROR: Cannot represent timeout=%d > %d\n", timeout, WWDG_MAXTIMEOUT); return -ERANGE; } diff --git a/arch/arm/src/stm32/stm32f20xxx_dma.c b/arch/arm/src/stm32/stm32f20xxx_dma.c index 335a9cd009..8edd31db2c 100644 --- a/arch/arm/src/stm32/stm32f20xxx_dma.c +++ b/arch/arm/src/stm32/stm32f20xxx_dma.c @@ -606,8 +606,8 @@ void stm32_dmasetup(DMA_HANDLE handle, uint32_t paddr, uint32_t maddr, uint32_t regoffset; uint32_t regval; - dmaerr("paddr: %08x maddr: %08x ntransfers: %d scr: %08x\n", - paddr, maddr, ntransfers, scr); + dmainfo("paddr: %08x maddr: %08x ntransfers: %d scr: %08x\n", + paddr, maddr, ntransfers, scr); /* "If the stream is enabled, disable it by resetting the EN bit in the * DMA_SxCR register, then read this bit in order to confirm that there is no diff --git a/arch/arm/src/stm32/stm32f30xxx_i2c.c b/arch/arm/src/stm32/stm32f30xxx_i2c.c index de9d9241cb..141b0deb75 100644 --- a/arch/arm/src/stm32/stm32f30xxx_i2c.c +++ b/arch/arm/src/stm32/stm32f30xxx_i2c.c @@ -966,7 +966,7 @@ static void stm32_i2c_tracenew(FAR struct stm32_i2c_priv_s *priv, if (priv->tndx >= (CONFIG_I2C_NTRACE-1)) { - i2cerr("Trace table overflow\n"); + i2cerr("ERROR: Trace table overflow\n"); return; } @@ -1007,7 +1007,7 @@ static void stm32_i2c_traceevent(FAR struct stm32_i2c_priv_s *priv, if (priv->tndx >= (CONFIG_I2C_NTRACE-1)) { - i2cerr("Trace table overflow\n"); + i2cerr("ERROR: Trace table overflow\n"); return; } @@ -1700,7 +1700,7 @@ static int stm32_i2c_transfer(FAR struct i2c_master_s *dev, FAR struct i2c_msg_s status = stm32_i2c_getstatus(priv); ret = -ETIMEDOUT; - i2cerr("Timed out: CR1: %04x status: %08x\n", + i2cerr("ERROR: Timed out: CR1: %04x status: %08x\n", stm32_i2c_getreg(priv, STM32_I2C_CR1_OFFSET), status); /* "Note: When the STOP, START or PEC bit is set, the software must diff --git a/arch/arm/src/stm32/stm32f40xxx_dma.c b/arch/arm/src/stm32/stm32f40xxx_dma.c index 8aae23d833..f631c6ea4a 100644 --- a/arch/arm/src/stm32/stm32f40xxx_dma.c +++ b/arch/arm/src/stm32/stm32f40xxx_dma.c @@ -605,8 +605,8 @@ void stm32_dmasetup(DMA_HANDLE handle, uint32_t paddr, uint32_t maddr, uint32_t regoffset; uint32_t regval; - dmaerr("paddr: %08x maddr: %08x ntransfers: %d scr: %08x\n", - paddr, maddr, ntransfers, scr); + dmainfo("paddr: %08x maddr: %08x ntransfers: %d scr: %08x\n", + paddr, maddr, ntransfers, scr); #ifdef CONFIG_STM32_DMACAPABLE DEBUGASSERT(stm32_dmacapable(maddr, ntransfers, scr)); diff --git a/arch/arm/src/stm32/stm32f40xxx_rtcc.c b/arch/arm/src/stm32/stm32f40xxx_rtcc.c index bd0b6e45c8..5017658cfe 100644 --- a/arch/arm/src/stm32/stm32f40xxx_rtcc.c +++ b/arch/arm/src/stm32/stm32f40xxx_rtcc.c @@ -971,13 +971,13 @@ int up_rtc_initialize(void) { case OK: { - rtcllerr("rtc_syncwait() okay\n"); + rtcllinfo("rtc_syncwait() okay\n"); break; } default: { - rtcllerr("rtc_syncwait() failed (%d)\n", ret); + rtcllerr("ERROR: rtc_syncwait() failed (%d)\n", ret); break; } } @@ -991,7 +991,7 @@ int up_rtc_initialize(void) if (regval != RTC_MAGIC) { - rtcllerr("Do setup\n"); + rtcllinfo("Do setup\n"); /* Perform the one-time setup of the LSE clocking to the RTC */ @@ -1009,7 +1009,7 @@ int up_rtc_initialize(void) } else { - rtcllerr("Do resume\n"); + rtcllinfo("Do resume\n"); /* RTC already set-up, just resume normal operation */ @@ -1025,7 +1025,7 @@ int up_rtc_initialize(void) if (ret != OK && nretry > 0) { - rtcllerr("setup/resume ran %d times and failed with %d\n", + rtcllinfo("setup/resume ran %d times and failed with %d\n", nretry, ret); return -ETIMEDOUT; } diff --git a/arch/arm/src/stm32f7/stm32_gpio.h b/arch/arm/src/stm32f7/stm32_gpio.h index e08aac39f7..f79b398b7a 100644 --- a/arch/arm/src/stm32f7/stm32_gpio.h +++ b/arch/arm/src/stm32f7/stm32_gpio.h @@ -345,7 +345,7 @@ xcpt_t stm32_gpiosetevent(uint32_t pinset, bool risingedge, bool fallingedge, * ************************************************************************************/ -#ifdef CONFIG_DEBUG_FEATURES +#ifdef CONFIG_DEBUG_GPIO_INFO int stm32_dumpgpio(uint32_t pinset, const char *msg); #else # define stm32_dumpgpio(p,m) From fdaf3d7268fbd4fd53b74de80670bfb3aa9abd9a Mon Sep 17 00:00:00 2001 From: Gregory Nutt Date: Thu, 16 Jun 2016 09:52:15 -0600 Subject: [PATCH 08/75] STM32: Move backup domain reset to stm32_rcc.c in order to avoid disabling LSE during RTC initialiation. --- arch/arm/src/stm32/stm32_rcc.c | 34 +++++++++++++++++++++++++++ arch/arm/src/stm32/stm32_rtc.h | 11 +++++++++ arch/arm/src/stm32/stm32_rtcc.c | 17 -------------- arch/arm/src/stm32/stm32f40xxx_rtcc.c | 17 -------------- 4 files changed, 45 insertions(+), 34 deletions(-) diff --git a/arch/arm/src/stm32/stm32_rcc.c b/arch/arm/src/stm32/stm32_rcc.c index 8040af9e1e..87afb59d3a 100644 --- a/arch/arm/src/stm32/stm32_rcc.c +++ b/arch/arm/src/stm32/stm32_rcc.c @@ -51,6 +51,7 @@ #include "chip.h" #include "stm32_rcc.h" +#include "stm32_rtc.h" #include "stm32_flash.h" #include "stm32.h" #include "stm32_waste.h" @@ -92,6 +93,14 @@ # error "Unsupported STM32 chip" #endif +#if defined(CONFIG_STM32_STM32L15XX) +# define STM32_RCC_XXX STM32_RCC_CSR +# define RCC_XXX_YYYRST RCC_CSR_RTCRST +#else +# define STM32_RCC_XXX STM32_RCC_BDCR +# define RCC_XXX_YYYRST RCC_BDCR_BDRST +#endif + /**************************************************************************** * Public Functions ****************************************************************************/ @@ -119,10 +128,35 @@ void stm32_clockconfig(void) { + uint32_t regval; + /* Make sure that we are starting in the reset state */ rcc_reset(); + /* The RTC needs to reset the Backup Domain to change RTCSEL and resetting the + * Backup Domain renders to disabling the LSE as consequence. In order to avoid + * resetting the Backup Domain when we already configured LSE we will reset the + * Backup Domain early (here). + */ + + /* Check if the RTC is already configured */ + + regval = getreg32(RTC_MAGIC_REG); + if (regval != RTC_MAGIC) + { + (void)stm32_pwr_enablebkp(true); + + /* We might be changing RTCSEL - to ensure such changes work, we must + * reset the backup domain (having backed up the RTC_MAGIC token) + */ + + modifyreg32(STM32_RCC_XXX, 0, RCC_XXX_YYYRST); + modifyreg32(STM32_RCC_XXX, RCC_XXX_YYYRST, 0); + + (void)stm32_pwr_enablebkp(false); + } + #if defined(CONFIG_ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG) /* Invoke Board Custom Clock Configuration */ diff --git a/arch/arm/src/stm32/stm32_rtc.h b/arch/arm/src/stm32/stm32_rtc.h index 731cc2d3b8..119e5e54df 100644 --- a/arch/arm/src/stm32/stm32_rtc.h +++ b/arch/arm/src/stm32/stm32_rtc.h @@ -79,6 +79,17 @@ #define STM32_RTC_PRESCALER_SECOND 32767 /* Default prescaler to get a second base */ #define STM32_RTC_PRESCALER_MIN 1 /* Maximum speed of 16384 Hz */ +#if !defined(CONFIG_RTC_MAGIC) +# define CONFIG_RTC_MAGIC (0xfacefeee) +#endif + +#if !defined(CONFIG_RTC_MAGIC_REG) +# define CONFIG_RTC_MAGIC_REG (0) +#endif + +#define RTC_MAGIC CONFIG_RTC_MAGIC +#define RTC_MAGIC_REG STM32_RTC_BKR(CONFIG_RTC_MAGIC_REG) + /**************************************************************************** * Public Types ****************************************************************************/ diff --git a/arch/arm/src/stm32/stm32_rtcc.c b/arch/arm/src/stm32/stm32_rtcc.c index bbb2137ab7..89d97dc46b 100644 --- a/arch/arm/src/stm32/stm32_rtcc.c +++ b/arch/arm/src/stm32/stm32_rtcc.c @@ -84,20 +84,10 @@ # endif #endif -#if !defined(CONFIG_RTC_MAGIC) -# define CONFIG_RTC_MAGIC (0xfacefeee) -#endif - -#if !defined(CONFIG_RTC_MAGIC_REG) -# define CONFIG_RTC_MAGIC_REG (0) -#endif - /* Constants ************************************************************************/ #define SYNCHRO_TIMEOUT (0x00020000) #define INITMODE_TIMEOUT (0x00010000) -#define RTC_MAGIC CONFIG_RTC_MAGIC -#define RTC_MAGIC_REG STM32_RTC_BKR(CONFIG_RTC_MAGIC_REG) /* Proxy definitions to make the same code work for all the STM32 series ************/ @@ -612,13 +602,6 @@ int up_rtc_initialize(void) if (regval != RTC_MAGIC) { - /* We might be changing RTCSEL - to ensure such changes work, we must reset the - * backup domain (having backed up the RTC_MAGIC token) - */ - - modifyreg32(STM32_RCC_XXX, 0, RCC_XXX_YYYRST); - modifyreg32(STM32_RCC_XXX, RCC_XXX_YYYRST, 0); - /* Some boards do not have the external 32khz oscillator installed, for those * boards we must fallback to the crummy internal RC clock or the external high * rate clock diff --git a/arch/arm/src/stm32/stm32f40xxx_rtcc.c b/arch/arm/src/stm32/stm32f40xxx_rtcc.c index 5017658cfe..5274687963 100644 --- a/arch/arm/src/stm32/stm32f40xxx_rtcc.c +++ b/arch/arm/src/stm32/stm32f40xxx_rtcc.c @@ -81,20 +81,10 @@ # error "CONFIG_STM32_PWR must selected to use this driver" #endif -#if !defined(CONFIG_RTC_MAGIC) -# define CONFIG_RTC_MAGIC (0xfacefeee) -#endif - -#if !defined(CONFIG_RTC_MAGIC_REG) -# define CONFIG_RTC_MAGIC_REG (0) -#endif - /* Constants ************************************************************************/ #define SYNCHRO_TIMEOUT (0x00020000) #define INITMODE_TIMEOUT (0x00010000) -#define RTC_MAGIC CONFIG_RTC_MAGIC -#define RTC_MAGIC_REG STM32_RTC_BKR(CONFIG_RTC_MAGIC_REG) /* Proxy definitions to make the same code work for all the STM32 series ************/ @@ -867,13 +857,6 @@ int up_rtc_initialize(void) if (regval != RTC_MAGIC) { - /* We might be changing RTCSEL - to ensure such changes work, we must reset the - * backup domain (having backed up the RTC_MAGIC token) - */ - - modifyreg32(STM32_RCC_XXX, 0, RCC_XXX_YYYRST); - modifyreg32(STM32_RCC_XXX, RCC_XXX_YYYRST, 0); - /* Some boards do not have the external 32khz oscillator installed, for those * boards we must fallback to the crummy internal RC clock or the external high * rate clock From 0c8c7fecf089481b6f982ff83cab8c15d198853a Mon Sep 17 00:00:00 2001 From: Gregory Nutt Date: Thu, 16 Jun 2016 12:33:32 -0600 Subject: [PATCH 09/75] Add _ to the beginning of all debug macros to avoid name collisions --- Kconfig | 4 +- arch/arm/src/a1x/a1x_serial.c | 6 +- arch/arm/src/armv6-m/up_dumpnvic.c | 12 +- arch/arm/src/armv6-m/up_hardfault.c | 16 +- arch/arm/src/armv7-a/arm_cpustart.c | 6 +- arch/arm/src/armv7-a/arm_l2cc_pl310.c | 2 +- arch/arm/src/armv7-m/mpu.h | 2 +- arch/arm/src/armv7-m/up_hardfault.c | 4 +- arch/arm/src/armv7-m/up_memfault.c | 6 +- arch/arm/src/armv7-r/arm_assert.c | 46 +- arch/arm/src/armv7-r/arm_l2cc_pl310.c | 2 +- arch/arm/src/armv7-r/mpu.h | 2 +- arch/arm/src/c5471/c5471_watchdog.c | 36 +- arch/arm/src/calypso/calypso_spi.c | 10 +- arch/arm/src/calypso/calypso_uwire.c | 8 +- arch/arm/src/common/up_initialize.c | 4 +- arch/arm/src/dm320/dm320_usbdev.c | 24 +- arch/arm/src/efm32/efm32_idle.c | 2 +- arch/arm/src/efm32/efm32_irq.c | 12 +- arch/arm/src/efm32/efm32_leserial.c | 4 +- arch/arm/src/efm32/efm32_rmu.h | 4 +- arch/arm/src/efm32/efm32_serial.c | 4 +- arch/arm/src/efm32/efm32_usbdev.c | 8 +- arch/arm/src/efm32/efm32_usbhost.c | 4 +- arch/arm/src/kinetis/kinetis_irq.c | 12 +- arch/arm/src/kinetis/kinetis_serial.c | 2 +- arch/arm/src/kinetis/kinetis_start.c | 2 +- arch/arm/src/kinetis/kinetis_usbdev.c | 16 +- arch/arm/src/kl/kl_dumpgpio.c | 4 +- arch/arm/src/kl/kl_idle.c | 2 +- arch/arm/src/kl/kl_irq.c | 6 +- arch/arm/src/lpc11xx/lpc11_i2c.c | 2 +- arch/arm/src/lpc11xx/lpc11_irq.c | 6 +- arch/arm/src/lpc11xx/lpc11_serial.c | 4 +- arch/arm/src/lpc17xx/lpc17_can.c | 14 +- arch/arm/src/lpc17xx/lpc17_dac.c | 2 +- arch/arm/src/lpc17xx/lpc17_ethernet.c | 18 +- arch/arm/src/lpc17xx/lpc17_i2c.c | 2 +- arch/arm/src/lpc17xx/lpc17_irq.c | 12 +- arch/arm/src/lpc17xx/lpc17_serial.c | 6 +- arch/arm/src/lpc17xx/lpc17_usbdev.c | 4 +- arch/arm/src/lpc17xx/lpc17_usbhost.c | 4 +- arch/arm/src/lpc214x/lpc214x_serial.c | 6 +- arch/arm/src/lpc214x/lpc214x_usbdev.c | 8 +- arch/arm/src/lpc2378/lpc23xx_i2c.c | 2 +- arch/arm/src/lpc2378/lpc23xx_serial.c | 6 +- arch/arm/src/lpc31xx/lpc31_ehci.c | 4 +- arch/arm/src/lpc31xx/lpc31_serial.c | 2 +- arch/arm/src/lpc31xx/lpc31_spi.c | 8 +- arch/arm/src/lpc31xx/lpc31_usbdev.c | 8 +- arch/arm/src/lpc43xx/lpc43_dac.c | 2 +- arch/arm/src/lpc43xx/lpc43_ehci.c | 4 +- arch/arm/src/lpc43xx/lpc43_ethernet.c | 8 +- arch/arm/src/lpc43xx/lpc43_i2c.c | 2 +- arch/arm/src/lpc43xx/lpc43_idle.c | 2 +- arch/arm/src/lpc43xx/lpc43_irq.c | 12 +- arch/arm/src/lpc43xx/lpc43_rit.c | 2 +- arch/arm/src/lpc43xx/lpc43_serial.c | 6 +- arch/arm/src/lpc43xx/lpc43_usb0dev.c | 8 +- arch/arm/src/moxart/moxart_irq.c | 10 +- arch/arm/src/nuc1xx/nuc_dumpgpio.c | 8 +- arch/arm/src/nuc1xx/nuc_idle.c | 2 +- arch/arm/src/nuc1xx/nuc_irq.c | 6 +- arch/arm/src/sam34/sam4cm_tc.c | 18 +- arch/arm/src/sam34/sam_emac.c | 6 +- arch/arm/src/sam34/sam_irq.c | 12 +- arch/arm/src/sam34/sam_rtt.c | 12 +- arch/arm/src/sam34/sam_spi.c | 6 +- arch/arm/src/sam34/sam_tc.c | 8 +- arch/arm/src/sam34/sam_twi.c | 6 +- arch/arm/src/sam34/sam_udp.c | 22 +- arch/arm/src/sam34/sam_wdt.c | 8 +- arch/arm/src/sama5/sam_adc.c | 6 +- arch/arm/src/sama5/sam_allocateheap.c | 24 +- arch/arm/src/sama5/sam_can.c | 20 +- arch/arm/src/sama5/sam_ehci.c | 4 +- arch/arm/src/sama5/sam_emaca.c | 6 +- arch/arm/src/sama5/sam_emacb.c | 6 +- arch/arm/src/sama5/sam_gmac.c | 6 +- arch/arm/src/sama5/sam_hsmci.c | 6 +- arch/arm/src/sama5/sam_lcd.c | 6 +- arch/arm/src/sama5/sam_memories.c | 6 +- arch/arm/src/sama5/sam_nand.c | 4 +- arch/arm/src/sama5/sam_nand.h | 4 +- arch/arm/src/sama5/sam_ohci.c | 4 +- arch/arm/src/sama5/sam_pck.c | 2 +- arch/arm/src/sama5/sam_pwm.c | 14 +- arch/arm/src/sama5/sam_spi.c | 6 +- arch/arm/src/sama5/sam_ssc.c | 10 +- arch/arm/src/sama5/sam_tc.c | 22 +- arch/arm/src/sama5/sam_twi.c | 6 +- arch/arm/src/sama5/sam_udphs.c | 36 +- arch/arm/src/sama5/sam_wdt.c | 8 +- arch/arm/src/samdl/sam_idle.c | 2 +- arch/arm/src/samdl/sam_irq.c | 6 +- arch/arm/src/samdl/sam_port.c | 8 +- arch/arm/src/samdl/sam_spi.c | 14 +- arch/arm/src/samv7/sam_emac.c | 6 +- arch/arm/src/samv7/sam_hsmci.c | 6 +- arch/arm/src/samv7/sam_irq.c | 12 +- arch/arm/src/samv7/sam_mcan.c | 34 +- arch/arm/src/samv7/sam_pck.c | 4 +- arch/arm/src/samv7/sam_qspi.c | 6 +- arch/arm/src/samv7/sam_rswdt.c | 8 +- arch/arm/src/samv7/sam_spi.c | 6 +- arch/arm/src/samv7/sam_spi_slave.c | 6 +- arch/arm/src/samv7/sam_ssc.c | 10 +- arch/arm/src/samv7/sam_tc.c | 20 +- arch/arm/src/samv7/sam_twihs.c | 6 +- arch/arm/src/samv7/sam_usbdevhs.c | 36 +- arch/arm/src/samv7/sam_wdt.c | 8 +- arch/arm/src/stm32/stm32_bbsram.c | 16 +- arch/arm/src/stm32/stm32_dumpgpio.c | 36 +- arch/arm/src/stm32/stm32_idle.c | 2 +- arch/arm/src/stm32/stm32_irq.c | 12 +- arch/arm/src/stm32/stm32_rng.c | 4 +- arch/arm/src/stm32f7/stm32_irq.c | 12 +- arch/arm/src/stm32l4/stm32l4_idle.c | 2 +- arch/arm/src/stm32l4/stm32l4_irq.c | 12 +- arch/arm/src/stm32l4/stm32l4_rng.c | 4 +- arch/arm/src/tiva/tiva_irq.c | 12 +- arch/arm/src/tiva/tm4c_ethernet.c | 8 +- arch/arm/src/tms570/tms570_esm.c | 2 +- arch/arm/src/tms570/tms570_gio.c | 10 +- arch/avr/src/at32uc3/at32uc3_gpioirq.c | 4 +- arch/avr/src/at32uc3/at32uc3_irq.c | 4 +- arch/avr/src/common/up_initialize.c | 4 +- arch/hc/src/common/up_initialize.c | 4 +- arch/mips/src/common/up_initialize.c | 4 +- arch/mips/src/pic32mx/pic32mx-serial.c | 2 +- arch/mips/src/pic32mx/pic32mx-spi.c | 8 +- arch/mips/src/pic32mx/pic32mx-usbdev.c | 12 +- arch/mips/src/pic32mz/pic32mz-serial.c | 2 +- arch/mips/src/pic32mz/pic32mz-spi.c | 6 +- arch/rgmp/src/bridge.c | 8 +- arch/rgmp/src/nuttx.c | 10 +- arch/rgmp/src/x86/com.c | 18 +- arch/sh/src/m16c/m16c_serial.c | 10 +- arch/sh/src/sh1/sh1_irq.c | 4 +- arch/sim/src/up_framebuffer.c | 36 +- arch/x86/src/common/up_initialize.c | 4 +- arch/z16/src/common/up_initialize.c | 4 +- arch/z16/src/common/up_stackdump.c | 2 +- arch/z80/src/common/up_blocktask.c | 2 +- arch/z80/src/common/up_exit.c | 12 +- arch/z80/src/common/up_initialize.c | 4 +- arch/z80/src/common/up_unblocktask.c | 2 +- arch/z80/src/ez80/ez80_i2c.c | 18 +- arch/z80/src/z180/z180_schedulesigaction.c | 2 +- arch/z80/src/z8/z8_i2c.c | 2 +- arch/z80/src/z8/z8_schedulesigaction.c | 2 +- arch/z80/src/z80/z80_schedulesigaction.c | 2 +- audio/pcm_decode.c | 34 +- binfmt/pcode.c | 2 +- configs/compal_e99/src/ssd1783.c | 2 +- configs/dk-tm4c129x/src/tm4c_bringup.c | 8 +- configs/fire-stm32v2/src/stm32_appinit.c | 4 +- configs/freedom-kl25z/src/kl_appinit.c | 2 +- configs/hymini-stm32v/src/stm32_appinit.c | 2 +- configs/lm3s6965-ek/src/lm_oled.c | 2 +- configs/lm3s8962-ek/src/lm_oled.c | 2 +- configs/lpc4337-ws/src/lpc43_appinit.c | 4 +- configs/lpc4370-link2/src/lpc43_appinit.c | 4 +- configs/mikroe-stm32f4/src/stm32_idle.c | 2 +- configs/mikroe-stm32f4/src/stm32_pwm.c | 2 +- configs/mirtoo/README.txt | 6 +- configs/ne64badge/src/m9s12_buttons.c | 4 +- configs/sabre-6quad/src/imx_bringup.c | 4 +- configs/sam4e-ek/src/sam_ethernet.c | 12 +- configs/sama5d2-xult/src/sam_bringup.c | 4 +- configs/sama5d3-xplained/src/sam_ethernet.c | 12 +- configs/sama5d3-xplained/src/sam_i2schar.c | 2 +- configs/sama5d3-xplained/src/sam_pwm.c | 2 +- configs/sama5d3x-ek/src/sam_ethernet.c | 12 +- configs/sama5d3x-ek/src/sam_i2schar.c | 2 +- configs/sama5d3x-ek/src/sam_pwm.c | 2 +- configs/sama5d4-ek/src/sam_bringup.c | 8 +- configs/sama5d4-ek/src/sam_ethernet.c | 12 +- configs/sama5d4-ek/src/sam_pmic.c | 2 +- configs/sama5d4-ek/src/sam_pwm.c | 2 +- configs/same70-xplained/src/sam_bringup.c | 8 +- configs/same70-xplained/src/sam_ethernet.c | 12 +- configs/samv71-xult/src/sam_bringup.c | 8 +- configs/samv71-xult/src/sam_ethernet.c | 12 +- configs/shenzhou/src/stm32_ili93xx.c | 10 +- configs/shenzhou/src/stm32_ssd1289.c | 10 +- configs/sim/src/sim_bringup.c | 4 +- configs/stm3210e-eval/src/stm32_appinit.c | 4 +- configs/stm3210e-eval/src/stm32_idle.c | 2 +- configs/stm3220g-eval/src/stm32_appinit.c | 4 +- configs/stm3240g-eval/src/stm32_appinit.c | 4 +- configs/stm32_tiny/src/stm32_wireless.c | 8 +- configs/stm32f4discovery/src/stm32_ethernet.c | 12 +- configs/stm32f4discovery/src/stm32_pca9635.c | 2 +- configs/stm32l476vg-disco/src/stm32_appinit.c | 12 +- configs/stm32ldiscovery/src/stm32_pwm.c | 2 +- configs/tm4c1294-launchpad/src/tm4c_bringup.c | 6 +- configs/u-blox-c027/src/lpc17_ubxmdm.c | 8 +- configs/us7032evb1/shterm/shterm.c | 4 +- configs/zkit-arm-1769/src/lpc17_appinit.c | 4 +- drivers/analog/ad5410.c | 2 +- drivers/analog/ads1242.c | 14 +- drivers/analog/ads1255.c | 2 +- drivers/bch/bchdev_unregister.c | 4 +- drivers/input/stmpe811_base.c | 6 +- drivers/lcd/p14201.c | 6 +- drivers/lcd/skeleton.c | 6 +- drivers/lcd/ssd1306_i2c.c | 2 +- drivers/lcd/ssd1306_spi.c | 2 +- drivers/loop/losetup.c | 18 +- drivers/modem/u-blox.c | 8 +- drivers/mtd/filemtd.c | 4 +- drivers/mtd/rammtd.c | 2 +- drivers/mtd/smart.c | 6 +- drivers/mtd/sst26.c | 10 +- drivers/net/phy_notify.c | 8 +- drivers/pipes/pipe_common.c | 4 +- drivers/power/battery_charger.c | 4 +- drivers/power/battery_gauge.c | 4 +- drivers/power/bq2425x.c | 4 +- drivers/power/max1704x.c | 2 +- drivers/sensors/adxl345_i2c.c | 6 +- drivers/sensors/adxl345_spi.c | 6 +- drivers/sensors/mpl115a.c | 2 +- drivers/sensors/ms58xx.c | 8 +- drivers/sercomm/console.c | 2 +- drivers/serial/serial.c | 2 +- drivers/serial/uart_16550.c | 6 +- drivers/timers/cs2100-cp.c | 18 +- drivers/video/ov2640.c | 4 +- drivers/wireless/cc3000/cc3000.c | 4 +- drivers/wireless/cc3000/socket.c | 4 +- drivers/wireless/ieee802154/mrf24j40.c | 2 +- drivers/wireless/pn532.c | 4 +- graphics/vnc/server/vnc_server.h | 24 +- include/debug.h | 790 +++++++++--------- include/nuttx/mm/shm.h | 8 +- include/nuttx/wireless/nrf24l01.h | 8 +- include/sys/wait.h | 2 +- libc/libc.csv | 12 +- libc/misc/lib_debug.c | 16 +- libc/spawn/lib_psa_dump.c | 30 +- libc/spawn/lib_psfa_dump.c | 12 +- libxx/libxx_new.cxx | 2 +- libxx/libxx_newa.cxx | 2 +- libxx/libxx_stdthrow.cxx | 8 +- mm/mm_gran/mm_gran.h | 12 +- mm/mm_gran/mm_pgalloc.c | 12 +- mm/mm_heap/mm_sem.c | 8 +- sched/group/group_childstatus.c | 4 +- sched/irq/irq_unexpectedisr.c | 2 +- sched/semaphore/sem_holder.c | 4 +- 252 files changed, 1348 insertions(+), 1374 deletions(-) diff --git a/Kconfig b/Kconfig index e14a7387cd..7e9ae4eed3 100644 --- a/Kconfig +++ b/Kconfig @@ -413,7 +413,7 @@ config DEBUG_ERROR bool "Enable Error Output" default n ---help--- - Enables output from err() statements. Errors are significant system + Enables output from [a-z]err() statements. Errors are significant system exceptions that require immediate attention. config DEBUG_WARN @@ -421,7 +421,7 @@ config DEBUG_WARN default n depends on DEBUG_ERROR ---help--- - Enables output from warn() statements. Warnings are considered to + Enables output from [a-z]warn() statements. Warnings are considered to be various unexpected conditions, potential errors or errors that will not have serious consequences. diff --git a/arch/arm/src/a1x/a1x_serial.c b/arch/arm/src/a1x/a1x_serial.c index 3ae955a99d..8c28eabb37 100644 --- a/arch/arm/src/a1x/a1x_serial.c +++ b/arch/arm/src/a1x/a1x_serial.c @@ -1156,7 +1156,7 @@ static int uart_interrupt(struct uart_dev_s *dev) /* Read the modem status register (MSR) to clear */ status = up_serialin(priv, A1X_UART_MSR_OFFSET); - info("MSR: %02x\n", status); + _info("MSR: %02x\n", status); break; } @@ -1167,7 +1167,7 @@ static int uart_interrupt(struct uart_dev_s *dev) /* Read the line status register (LSR) to clear */ status = up_serialin(priv, A1X_UART_LSR_OFFSET); - info("LSR: %02x\n", status); + _info("LSR: %02x\n", status); break; } @@ -1192,7 +1192,7 @@ static int uart_interrupt(struct uart_dev_s *dev) default: { - llerr("Unexpected IIR: %02x\n", status); + _llerr("Unexpected IIR: %02x\n", status); break; } } diff --git a/arch/arm/src/armv6-m/up_dumpnvic.c b/arch/arm/src/armv6-m/up_dumpnvic.c index a50d91aac0..ba4974a0ac 100644 --- a/arch/arm/src/armv6-m/up_dumpnvic.c +++ b/arch/arm/src/armv6-m/up_dumpnvic.c @@ -72,25 +72,25 @@ void up_dumpnvic(FAR const char *msg) flags = enter_critical_section(); - llinfo("NVIC: %s\n", msg); - llinfo(" ISER: %08x ICER: %08x ISPR: %08x ICPR: %08x\n", + _llinfo("NVIC: %s\n", msg); + _llinfo(" ISER: %08x ICER: %08x ISPR: %08x ICPR: %08x\n", getreg32(ARMV6M_NVIC_ISER), getreg32(ARMV6M_NVIC_ICER), getreg32(ARMV6M_NVIC_ISPR), getreg32(ARMV6M_NVIC_ICPR)); for (i = 0 ; i < 8; i += 4) { - llinfo(" IPR%d: %08x IPR%d: %08x IPR%d: %08x IPR%d: %08x\n", + _llinfo(" IPR%d: %08x IPR%d: %08x IPR%d: %08x IPR%d: %08x\n", i, getreg32(ARMV6M_NVIC_IPR(i)), i+1, getreg32(ARMV6M_NVIC_IPR(i+1)), i+2, getreg32(ARMV6M_NVIC_IPR(i+2)), i+3, getreg32(ARMV6M_NVIC_IPR(i+3))); } - llinfo("SYSCON:\n"); - llinfo(" CPUID: %08x ICSR: %08x AIRCR: %08x SCR: %08x\n", + _llinfo("SYSCON:\n"); + _llinfo(" CPUID: %08x ICSR: %08x AIRCR: %08x SCR: %08x\n", getreg32(ARMV6M_SYSCON_CPUID), getreg32(ARMV6M_SYSCON_ICSR), getreg32(ARMV6M_SYSCON_AIRCR), getreg32(ARMV6M_SYSCON_SCR)); - llinfo(" CCR: %08x SHPR2: %08x SHPR3: %08x\n", + _llinfo(" CCR: %08x SHPR2: %08x SHPR3: %08x\n", getreg32(ARMV6M_SYSCON_CCR), getreg32(ARMV6M_SYSCON_SHPR2), getreg32(ARMV6M_SYSCON_SHPR3)); diff --git a/arch/arm/src/armv6-m/up_hardfault.c b/arch/arm/src/armv6-m/up_hardfault.c index 873a76d972..ef5c59ba2e 100644 --- a/arch/arm/src/armv6-m/up_hardfault.c +++ b/arch/arm/src/armv6-m/up_hardfault.c @@ -55,25 +55,13 @@ ****************************************************************************/ #ifdef CONFIG_DEBUG_HARDFAULT -# define hferr(format, ...) llerr(format, ##__VA_ARGS__) +# define hferr(format, ...) _llerr(format, ##__VA_ARGS__) #else # define hferr(x...) #endif #define INSN_SVC0 0xdf00 /* insn: svc 0 */ -/**************************************************************************** - * Private Data - ****************************************************************************/ - -/**************************************************************************** - * Public Data - ****************************************************************************/ - -/**************************************************************************** - * Private Functions - ****************************************************************************/ - /**************************************************************************** * Public Functions ****************************************************************************/ @@ -149,7 +137,7 @@ int up_hardfault(int irq, FAR void *context) #endif (void)up_irq_save(); - llerr("PANIC!!! Hard fault\n"); + _llerr("PANIC!!! Hard fault\n"); PANIC(); return OK; /* Won't get here */ } diff --git a/arch/arm/src/armv7-a/arm_cpustart.c b/arch/arm/src/armv7-a/arm_cpustart.c index 30653ed197..98aee251ab 100644 --- a/arch/arm/src/armv7-a/arm_cpustart.c +++ b/arch/arm/src/armv7-a/arm_cpustart.c @@ -64,19 +64,19 @@ static inline void arm_registerdump(FAR struct tcb_s *tcb) { int regndx; - llerr("CPU%d:\n", up_cpu_index()); + _llerr("CPU%d:\n", up_cpu_index()); /* Dump the startup registers */ for (regndx = REG_R0; regndx <= REG_R15; regndx += 8) { uint32_t *ptr = (uint32_t *)&tcb->xcp.regs[regndx]; - llerr("R%d: %08x %08x %08x %08x %08x %08x %08x %08x\n", + _llerr("R%d: %08x %08x %08x %08x %08x %08x %08x %08x\n", regndx, ptr[0], ptr[1], ptr[2], ptr[3], ptr[4], ptr[5], ptr[6], ptr[7]); } - llerr("CPSR: %08x\n", tcb->xcp.regs[REG_CPSR]); + _llerr("CPSR: %08x\n", tcb->xcp.regs[REG_CPSR]); } #else # define arm_registerdump(tcb) diff --git a/arch/arm/src/armv7-a/arm_l2cc_pl310.c b/arch/arm/src/armv7-a/arm_l2cc_pl310.c index 1b88cca350..94a1a343dc 100644 --- a/arch/arm/src/armv7-a/arm_l2cc_pl310.c +++ b/arch/arm/src/armv7-a/arm_l2cc_pl310.c @@ -411,7 +411,7 @@ void up_l2ccinitialize(void) putreg32(L2CC_CR_L2CEN, L2CC_CR); } - llerr("(%d ways) * (%d bytes/way) = %d bytes\n", + _llerr("(%d ways) * (%d bytes/way) = %d bytes\n", PL310_NWAYS, PL310_WAYSIZE, PL310_CACHE_SIZE); } diff --git a/arch/arm/src/armv7-m/mpu.h b/arch/arm/src/armv7-m/mpu.h index 6f4617a670..3ff96371cb 100644 --- a/arch/arm/src/armv7-m/mpu.h +++ b/arch/arm/src/armv7-m/mpu.h @@ -222,7 +222,7 @@ static inline void mpu_showtype(void) #ifdef CONFIG_DEBUG_ERROR uint32_t regval = getreg32(MPU_TYPE); - err("%s MPU Regions: data=%d instr=%d\n", + _err("%s MPU Regions: data=%d instr=%d\n", (regval & MPU_TYPE_SEPARATE) != 0 ? "Separate" : "Unified", (regval & MPU_TYPE_DREGION_MASK) >> MPU_TYPE_DREGION_SHIFT, (regval & MPU_TYPE_IREGION_MASK) >> MPU_TYPE_IREGION_SHIFT); diff --git a/arch/arm/src/armv7-m/up_hardfault.c b/arch/arm/src/armv7-m/up_hardfault.c index b08466258f..225ca8337e 100644 --- a/arch/arm/src/armv7-m/up_hardfault.c +++ b/arch/arm/src/armv7-m/up_hardfault.c @@ -60,7 +60,7 @@ */ #ifdef CONFIG_DEBUG_HARDFAULT -# define hferr(format, ...) llerr(format, ##__VA_ARGS__) +# define hferr(format, ...) _llerr(format, ##__VA_ARGS__) #else # define hferr(x...) #endif @@ -179,7 +179,7 @@ int up_hardfault(int irq, FAR void *context) #endif (void)up_irq_save(); - llerr("PANIC!!! Hard fault: %08x\n", getreg32(NVIC_HFAULTS)); + _llerr("PANIC!!! Hard fault: %08x\n", getreg32(NVIC_HFAULTS)); PANIC(); return OK; } diff --git a/arch/arm/src/armv7-m/up_memfault.c b/arch/arm/src/armv7-m/up_memfault.c index 629304d6d2..4359072e65 100644 --- a/arch/arm/src/armv7-m/up_memfault.c +++ b/arch/arm/src/armv7-m/up_memfault.c @@ -55,7 +55,7 @@ #undef DEBUG_MEMFAULTS /* Define to debug memory management faults */ #ifdef DEBUG_MEMFAULTS -# define mferr(format, ...) llerr(format, ##__VA_ARGS__) +# define mferr(format, ...) _llerr(format, ##__VA_ARGS__) #else # define mferr(x...) #endif @@ -92,9 +92,9 @@ int up_memfault(int irq, FAR void *context) /* Dump some memory management fault info */ (void)up_irq_save(); - llerr("PANIC!!! Memory Management Fault:\n"); + _llerr("PANIC!!! Memory Management Fault:\n"); mferr(" IRQ: %d context: %p\n", irq, regs); - llerr(" CFAULTS: %08x MMFAR: %08x\n", + _llerr(" CFAULTS: %08x MMFAR: %08x\n", getreg32(NVIC_CFAULTS), getreg32(NVIC_MEMMANAGE_ADDR)); mferr(" BASEPRI: %08x PRIMASK: %08x IPSR: %08x CONTROL: %08x\n", getbasepri(), getprimask(), getipsr(), getcontrol()); diff --git a/arch/arm/src/armv7-r/arm_assert.c b/arch/arm/src/armv7-r/arm_assert.c index 9218e4da8a..b6f6b23546 100644 --- a/arch/arm/src/armv7-r/arm_assert.c +++ b/arch/arm/src/armv7-r/arm_assert.c @@ -98,7 +98,7 @@ static void up_stackdump(uint32_t sp, uint32_t stack_base) for (stack = sp & ~0x1f; stack < stack_base; stack += 32) { uint32_t *ptr = (uint32_t *)stack; - llerr("%08x: %08x %08x %08x %08x %08x %08x %08x %08x\n", + _llerr("%08x: %08x %08x %08x %08x %08x %08x %08x %08x\n", stack, ptr[0], ptr[1], ptr[2], ptr[3], ptr[4], ptr[5], ptr[6], ptr[7]); } @@ -117,11 +117,11 @@ static void up_taskdump(FAR struct tcb_s *tcb, FAR void *arg) /* Dump interesting properties of this task */ #if CONFIG_TASK_NAME_SIZE > 0 - llerr("%s: PID=%d Stack Used=%lu of %lu\n", + _llerr("%s: PID=%d Stack Used=%lu of %lu\n", tcb->name, tcb->pid, (unsigned long)up_check_tcbstack(tcb), (unsigned long)tcb->adj_stack_size); #else - llerr("PID: %d Stack Used=%lu of %lu\n", + _llerr("PID: %d Stack Used=%lu of %lu\n", tcb->pid, (unsigned long)up_check_tcbstack(tcb), (unsigned long)tcb->adj_stack_size); #endif @@ -161,12 +161,12 @@ static inline void up_registerdump(void) for (regs = REG_R0; regs <= REG_R15; regs += 8) { uint32_t *ptr = (uint32_t *)&CURRENT_REGS[regs]; - llerr("R%d: %08x %08x %08x %08x %08x %08x %08x %08x\n", + _llerr("R%d: %08x %08x %08x %08x %08x %08x %08x %08x\n", regs, ptr[0], ptr[1], ptr[2], ptr[3], ptr[4], ptr[5], ptr[6], ptr[7]); } - llerr("CPSR: %08x\n", CURRENT_REGS[REG_CPSR]); + _llerr("CPSR: %08x\n", CURRENT_REGS[REG_CPSR]); } } #else @@ -230,7 +230,7 @@ static void up_dumpstate(void) ustacksize = (uint32_t)rtcb->adj_stack_size; } - llerr("Current sp: %08x\n", sp); + _llerr("Current sp: %08x\n", sp); #if CONFIG_ARCH_INTERRUPTSTACK > 3 /* Get the limits on the interrupt stack memory */ @@ -240,21 +240,21 @@ static void up_dumpstate(void) /* Show interrupt stack info */ - llerr("Interrupt stack:\n"); - llerr(" base: %08x\n", istackbase); - llerr(" size: %08x\n", istacksize); + _llerr("Interrupt stack:\n"); + _llerr(" base: %08x\n", istackbase); + _llerr(" size: %08x\n", istacksize); #ifdef CONFIG_STACK_COLORATION - llerr(" used: %08x\n", up_check_intstack()); + _llerr(" used: %08x\n", up_check_intstack()); #endif #endif /* Show user stack info */ - llerr("User stack:\n"); - llerr(" base: %08x\n", ustackbase); - llerr(" size: %08x\n", ustacksize); + _llerr("User stack:\n"); + _llerr(" base: %08x\n", ustackbase); + _llerr(" size: %08x\n", ustacksize); #ifdef CONFIG_STACK_COLORATION - llerr(" used: %08x\n", up_check_tcbstack(rtcb)); + _llerr(" used: %08x\n", up_check_tcbstack(rtcb)); #endif #ifdef CONFIG_ARCH_KERNEL_STACK @@ -264,9 +264,9 @@ static void up_dumpstate(void) { kstackbase = (uint32_t)rtcb->xcp.kstack + CONFIG_ARCH_KERNEL_STACKSIZE - 4; - llerr("Kernel stack:\n"); - llerr(" base: %08x\n", kstackbase); - llerr(" size: %08x\n", CONFIG_ARCH_KERNEL_STACKSIZE); + _llerr("Kernel stack:\n"); + _llerr(" base: %08x\n", kstackbase); + _llerr(" size: %08x\n", CONFIG_ARCH_KERNEL_STACKSIZE); } #endif @@ -277,7 +277,7 @@ static void up_dumpstate(void) { /* Yes.. dump the interrupt stack */ - llerr("Interrupt Stack\n", sp); + _llerr("Interrupt Stack\n", sp); up_stackdump(sp, istackbase); /* Extract the user stack pointer which should lie @@ -285,7 +285,7 @@ static void up_dumpstate(void) */ sp = g_intstackbase; - llerr("User sp: %08x\n", sp); + _llerr("User sp: %08x\n", sp); } #endif @@ -295,7 +295,7 @@ static void up_dumpstate(void) if (sp > ustackbase - ustacksize && sp < ustackbase) { - llerr("User Stack\n", sp); + _llerr("User Stack\n", sp); up_stackdump(sp, ustackbase); } @@ -306,7 +306,7 @@ static void up_dumpstate(void) if (sp >= (uint32_t)rtcb->xcp.kstack && sp < kstackbase) { - llerr("Kernel Stack\n", sp); + _llerr("Kernel Stack\n", sp); up_stackdump(sp, kstackbase); } #endif @@ -373,10 +373,10 @@ void up_assert(const uint8_t *filename, int lineno) board_autoled_on(LED_ASSERTION); #if CONFIG_TASK_NAME_SIZE > 0 - llerr("Assertion failed at file:%s line: %d task: %s\n", + _llerr("Assertion failed at file:%s line: %d task: %s\n", filename, lineno, rtcb->name); #else - llerr("Assertion failed at file:%s line: %d\n", + _llerr("Assertion failed at file:%s line: %d\n", filename, lineno); #endif up_dumpstate(); diff --git a/arch/arm/src/armv7-r/arm_l2cc_pl310.c b/arch/arm/src/armv7-r/arm_l2cc_pl310.c index e389c87e59..f606dadc8a 100644 --- a/arch/arm/src/armv7-r/arm_l2cc_pl310.c +++ b/arch/arm/src/armv7-r/arm_l2cc_pl310.c @@ -411,7 +411,7 @@ void up_l2ccinitialize(void) putreg32(L2CC_CR_L2CEN, L2CC_CR); } - llerr("(%d ways) * (%d bytes/way) = %d bytes\n", + _llerr("(%d ways) * (%d bytes/way) = %d bytes\n", PL310_NWAYS, PL310_WAYSIZE, PL310_CACHE_SIZE); } diff --git a/arch/arm/src/armv7-r/mpu.h b/arch/arm/src/armv7-r/mpu.h index 7428e9cac2..07b1969760 100644 --- a/arch/arm/src/armv7-r/mpu.h +++ b/arch/arm/src/armv7-r/mpu.h @@ -361,7 +361,7 @@ static inline void mpu_showtype(void) { #ifdef CONFIG_DEBUG_FEATURES uint32_t regval = mpu_get_mpuir(); - err("%s MPU Regions: data=%d instr=%d\n", + _err("%s MPU Regions: data=%d instr=%d\n", (regval & MPUIR_SEPARATE) != 0 ? "Separate" : "Unified", (regval & MPUIR_DREGION_MASK) >> MPUIR_DREGION_SHIFT, (regval & MPUIR_IREGION_MASK) >> MPUIR_IREGION_SHIFT); diff --git a/arch/arm/src/c5471/c5471_watchdog.c b/arch/arm/src/c5471/c5471_watchdog.c index 011357fb5c..51363ec8df 100644 --- a/arch/arm/src/c5471/c5471_watchdog.c +++ b/arch/arm/src/c5471/c5471_watchdog.c @@ -155,7 +155,7 @@ static inline unsigned int wdt_prescaletoptv(unsigned int prescale) } } - err("prescale=%d -> ptv=%d\n", prescale, ptv); + _err("prescale=%d -> ptv=%d\n", prescale, ptv); return ptv; } @@ -173,7 +173,7 @@ static int wdt_setusec(uint32_t usec) uint32_t divisor = 1; uint32_t mode; - err("usec=%d\n", usec); + _err("usec=%d\n", usec); /* Calculate a value of prescaler and divisor that will be able * to count to the usec. It may not be exact or the best @@ -186,7 +186,7 @@ static int wdt_setusec(uint32_t usec) do { divisor = (CLOCK_MHZx2 * usec) / (prescaler * 2); - err("divisor=0x%x prescaler=0x%x\n", divisor, prescaler); + _err("divisor=0x%x prescaler=0x%x\n", divisor, prescaler); if (divisor >= 0x10000) { @@ -194,7 +194,7 @@ static int wdt_setusec(uint32_t usec) { /* This is the max possible ~2.5 seconds. */ - err("prescaler=0x%x too big!\n", prescaler); + _err("prescaler=0x%x too big!\n", prescaler); return ERROR; } @@ -207,19 +207,19 @@ static int wdt_setusec(uint32_t usec) } while (divisor >= 0x10000); - err("prescaler=0x%x divisor=0x%x\n", prescaler, divisor); + _err("prescaler=0x%x divisor=0x%x\n", prescaler, divisor); mode = wdt_prescaletoptv(prescaler); mode &= ~C5471_TIMER_AUTORELOAD; /* One shot mode. */ mode |= divisor << 5; - err("mode=0x%x\n", mode); + _err("mode=0x%x\n", mode); c5471_wdt_cntl = mode; /* Now start the watchdog */ c5471_wdt_cntl |= C5471_TIMER_STARTBIT; - err("cntl_timer=0x%x\n", c5471_wdt_cntl); + _err("cntl_timer=0x%x\n", c5471_wdt_cntl); return 0; } @@ -234,17 +234,17 @@ static int wdt_setusec(uint32_t usec) static int wdt_interrupt(int irq, void *context) { - err("expired\n"); + _err("expired\n"); #if defined(CONFIG_SOFTWARE_REBOOT) # if defined(CONFIG_SOFTWARE_TEST) - err(" Test only\n"); + _err(" Test only\n"); # else - err(" Re-booting\n"); + _err(" Re-booting\n"); # warning "Add logic to reset CPU here" # endif #else - err(" No reboot\n"); + _err(" No reboot\n"); #endif return OK; } @@ -259,7 +259,7 @@ static ssize_t wdt_read(struct file *filep, char *buffer, size_t buflen) * not work if the user provides a buffer smaller than 18 bytes. */ - err("buflen=%d\n", buflen); + _err("buflen=%d\n", buflen); if (buflen >= 18) { sprintf(buffer, "%08x %08x\n", c5471_wdt_cntl, c5471_wdt_count); @@ -274,7 +274,7 @@ static ssize_t wdt_read(struct file *filep, char *buffer, size_t buflen) static ssize_t wdt_write(struct file *filep, const char *buffer, size_t buflen) { - err("buflen=%d\n", buflen); + _err("buflen=%d\n", buflen); if (buflen) { /* Reset the timer to the maximum delay */ @@ -292,7 +292,7 @@ static ssize_t wdt_write(struct file *filep, const char *buffer, size_t buflen) static int wdt_ioctl(FAR struct file *filep, int cmd, unsigned long arg) { - err("ioctl Call: cmd=0x%x arg=0x%x", cmd, arg); + _err("ioctl Call: cmd=0x%x arg=0x%x", cmd, arg); /* Process the IOCTL command (see arch/watchdog.h) */ @@ -315,7 +315,7 @@ static int wdt_ioctl(FAR struct file *filep, int cmd, unsigned long arg) static int wdt_open(struct file *filep) { - err(""); + _err(""); if (g_wdtopen) { @@ -339,7 +339,7 @@ static int wdt_open(struct file *filep) static int wdt_close(struct file *filep) { - err(""); + _err(""); /* The task controlling the watchdog has terminated. Take the timer * the @@ -367,7 +367,7 @@ int up_wdtinit(void) { int ret; - err("C547x Watchdog Driver\n"); + _err("C547x Watchdog Driver\n"); /* Register as /dev/wdt */ @@ -379,7 +379,7 @@ int up_wdtinit(void) /* Register for an interrupt level callback through wdt_interrupt */ - err("Attach to IRQ=%d\n", C5471_IRQ_WATCHDOG); + _err("Attach to IRQ=%d\n", C5471_IRQ_WATCHDOG); /* Make sure that the timer is stopped */ diff --git a/arch/arm/src/calypso/calypso_spi.c b/arch/arm/src/calypso/calypso_spi.c index fb5f871dfb..6278c32707 100644 --- a/arch/arm/src/calypso/calypso_spi.c +++ b/arch/arm/src/calypso/calypso_spi.c @@ -216,7 +216,7 @@ int spi_xfer(uint8_t dev_idx, uint8_t bitlen, const void *dout, void *din) tmp <<= (32-bitlen); /* align to MSB */ } - err("spi_xfer(dev_idx=%u, bitlen=%u, data_out=0x%08x): ", + _err("spi_xfer(dev_idx=%u, bitlen=%u, data_out=0x%08x): ", dev_idx, bitlen, tmp); /* fill transmit registers */ @@ -236,14 +236,14 @@ int spi_xfer(uint8_t dev_idx, uint8_t bitlen, const void *dout, void *din) } putreg16(reg_ctrl, SPI_REG(REG_CTRL)); - err("reg_ctrl=0x%04x ", reg_ctrl); + _err("reg_ctrl=0x%04x ", reg_ctrl); /* wait until the transfer is complete */ while (1) { reg_status = getreg16(SPI_REG(REG_STATUS)); - err("status=0x%04x ", reg_status); + _err("status=0x%04x ", reg_status); if (din && (reg_status & SPI_STATUS_RE)) { break; @@ -262,7 +262,7 @@ int spi_xfer(uint8_t dev_idx, uint8_t bitlen, const void *dout, void *din) { tmp = getreg16(SPI_REG(REG_RX_MSB)) << 16; tmp |= getreg16(SPI_REG(REG_RX_LSB)); - err("data_in=0x%08x ", tmp); + _err("data_in=0x%08x ", tmp); if (bitlen <= 8) { @@ -278,7 +278,7 @@ int spi_xfer(uint8_t dev_idx, uint8_t bitlen, const void *dout, void *din) } } - err("\n"); + _err("\n"); return 0; } diff --git a/arch/arm/src/calypso/calypso_uwire.c b/arch/arm/src/calypso/calypso_uwire.c index ee932b2924..7ad9075b1e 100644 --- a/arch/arm/src/calypso/calypso_uwire.c +++ b/arch/arm/src/calypso/calypso_uwire.c @@ -112,7 +112,7 @@ int uwire_xfer(int cs, int bitlen, const void *dout, void *din) /* FIXME uwire_init always selects CS0 for now */ - err("uwire_xfer(dev_idx=%u, bitlen=%u\n", cs, bitlen); + _err("uwire_xfer(dev_idx=%u, bitlen=%u\n", cs, bitlen); /* select the chip */ @@ -128,7 +128,7 @@ int uwire_xfer(int cs, int bitlen, const void *dout, void *din) tmp <<= 16 - bitlen; /* align to MSB */ putreg16(tmp, UWIRE_REG(REG_DATA)); - err(", data_out=0x%04hx", tmp); + _err(", data_out=0x%04hx", tmp); } tmp = (dout ? UWIRE_CSR_BITS_WR(bitlen) : 0) | @@ -142,7 +142,7 @@ int uwire_xfer(int cs, int bitlen, const void *dout, void *din) _uwire_wait(UWIRE_CSR_RDRB, UWIRE_CSR_RDRB); tmp = getreg16(UWIRE_REG(REG_DATA)); - err(", data_in=0x%08x", tmp); + _err(", data_in=0x%08x", tmp); if (bitlen <= 8) *(uint8_t *)din = tmp & 0xff; @@ -155,7 +155,7 @@ int uwire_xfer(int cs, int bitlen, const void *dout, void *din) putreg16(UWIRE_CSR_IDX(0) | 0, UWIRE_REG(REG_CSR)); _uwire_wait(UWIRE_CSR_CSRB, 0); - err(")\n"); + _err(")\n"); return 0; } diff --git a/arch/arm/src/common/up_initialize.c b/arch/arm/src/common/up_initialize.c index 6482a5fce2..5316eacbb6 100644 --- a/arch/arm/src/common/up_initialize.c +++ b/arch/arm/src/common/up_initialize.c @@ -77,13 +77,13 @@ static void up_calibratedelay(void) { int i; - llerr("Beginning 100s delay\n"); + _llerr("Beginning 100s delay\n"); for (i = 0; i < 100; i++) { up_mdelay(1000); } - llerr("End 100s delay\n"); + _llerr("End 100s delay\n"); } #else # define up_calibratedelay() diff --git a/arch/arm/src/dm320/dm320_usbdev.c b/arch/arm/src/dm320/dm320_usbdev.c index 7f3229b7fc..ad1641db1f 100644 --- a/arch/arm/src/dm320/dm320_usbdev.c +++ b/arch/arm/src/dm320/dm320_usbdev.c @@ -443,7 +443,7 @@ static uint8_t dm320_getreg8(uint32_t addr) { if (count == 4) { - llerr("...\n"); + _llerr("...\n"); } return val; @@ -460,7 +460,7 @@ static uint8_t dm320_getreg8(uint32_t addr) { /* Yes.. then show how many times the value repeated */ - llerr("[repeats %d more times]\n", count-3); + _llerr("[repeats %d more times]\n", count-3); } /* Save the new address, value, and count */ @@ -472,7 +472,7 @@ static uint8_t dm320_getreg8(uint32_t addr) /* Show the register value read */ - llerr("%08x->%02x\n", addr, val); + _llerr("%08x->%02x\n", addr, val); return val; } #endif @@ -506,7 +506,7 @@ static uint32_t dm320_getreg16(uint32_t addr) { if (count == 4) { - llerr("...\n"); + _llerr("...\n"); } return val; @@ -523,7 +523,7 @@ static uint32_t dm320_getreg16(uint32_t addr) { /* Yes.. then show how many times the value repeated */ - llerr("[repeats %d more times]\n", count-3); + _llerr("[repeats %d more times]\n", count-3); } /* Save the new address, value, and count */ @@ -535,7 +535,7 @@ static uint32_t dm320_getreg16(uint32_t addr) /* Show the register value read */ - llerr("%08x->%04x\n", addr, val); + _llerr("%08x->%04x\n", addr, val); return val; } #endif @@ -569,7 +569,7 @@ static uint32_t dm320_getreg32(uint32_t addr) { if (count == 4) { - llerr("...\n"); + _llerr("...\n"); } return val; @@ -586,7 +586,7 @@ static uint32_t dm320_getreg32(uint32_t addr) { /* Yes.. then show how many times the value repeated */ - llerr("[repeats %d more times]\n", count-3); + _llerr("[repeats %d more times]\n", count-3); } /* Save the new address, value, and count */ @@ -598,7 +598,7 @@ static uint32_t dm320_getreg32(uint32_t addr) /* Show the register value read */ - llerr("%08x->%08x\n", addr, val); + _llerr("%08x->%08x\n", addr, val); return val; } #endif @@ -616,7 +616,7 @@ static void dm320_putreg8(uint8_t val, uint32_t addr) { /* Show the register value being written */ - llerr("%08x<-%02x\n", addr, val); + _llerr("%08x<-%02x\n", addr, val); /* Write the value */ @@ -637,7 +637,7 @@ static void dm320_putreg16(uint16_t val, uint32_t addr) { /* Show the register value being written */ - llerr("%08x<-%04x\n", addr, val); + _llerr("%08x<-%04x\n", addr, val); /* Write the value */ @@ -658,7 +658,7 @@ static void dm320_putreg32(uint32_t val, uint32_t addr) { /* Show the register value being written */ - llerr("%08x<-%08x\n", addr, val); + _llerr("%08x<-%08x\n", addr, val); /* Write the value */ diff --git a/arch/arm/src/efm32/efm32_idle.c b/arch/arm/src/efm32/efm32_idle.c index 5d42299d70..b5a2278a1a 100644 --- a/arch/arm/src/efm32/efm32_idle.c +++ b/arch/arm/src/efm32/efm32_idle.c @@ -110,7 +110,7 @@ static void up_idlepm(void) /* Perform board-specific, state-dependent logic here */ - llinfo("newstate= %d oldstate=%d\n", newstate, oldstate); + _llinfo("newstate= %d oldstate=%d\n", newstate, oldstate); /* Then force the global state change */ diff --git a/arch/arm/src/efm32/efm32_irq.c b/arch/arm/src/efm32/efm32_irq.c index 74a5385f47..05d28c74a4 100644 --- a/arch/arm/src/efm32/efm32_irq.c +++ b/arch/arm/src/efm32/efm32_irq.c @@ -170,7 +170,7 @@ static void efm32_dumpnvic(const char *msg, int irq) static int efm32_nmi(int irq, FAR void *context) { (void)up_irq_save(); - err("PANIC!!! NMI received\n"); + _err("PANIC!!! NMI received\n"); PANIC(); return 0; } @@ -178,7 +178,7 @@ static int efm32_nmi(int irq, FAR void *context) static int efm32_busfault(int irq, FAR void *context) { (void)up_irq_save(); - err("PANIC!!! Bus fault received: %08x\n", getreg32(NVIC_CFAULTS)); + _err("PANIC!!! Bus fault received: %08x\n", getreg32(NVIC_CFAULTS)); PANIC(); return 0; } @@ -186,7 +186,7 @@ static int efm32_busfault(int irq, FAR void *context) static int efm32_usagefault(int irq, FAR void *context) { (void)up_irq_save(); - err("PANIC!!! Usage fault received: %08x\n", getreg32(NVIC_CFAULTS)); + _err("PANIC!!! Usage fault received: %08x\n", getreg32(NVIC_CFAULTS)); PANIC(); return 0; } @@ -194,7 +194,7 @@ static int efm32_usagefault(int irq, FAR void *context) static int efm32_pendsv(int irq, FAR void *context) { (void)up_irq_save(); - err("PANIC!!! PendSV received\n"); + _err("PANIC!!! PendSV received\n"); PANIC(); return 0; } @@ -202,7 +202,7 @@ static int efm32_pendsv(int irq, FAR void *context) static int efm32_errmonitor(int irq, FAR void *context) { (void)up_irq_save(); - err("PANIC!!! Debug Monitor received\n"); + _err("PANIC!!! Debug Monitor received\n"); PANIC(); return 0; } @@ -210,7 +210,7 @@ static int efm32_errmonitor(int irq, FAR void *context) static int efm32_reserved(int irq, FAR void *context) { (void)up_irq_save(); - err("PANIC!!! Reserved interrupt\n"); + _err("PANIC!!! Reserved interrupt\n"); PANIC(); return 0; } diff --git a/arch/arm/src/efm32/efm32_leserial.c b/arch/arm/src/efm32/efm32_leserial.c index 63fbd5f8cd..02126a92f3 100644 --- a/arch/arm/src/efm32/efm32_leserial.c +++ b/arch/arm/src/efm32/efm32_leserial.c @@ -518,7 +518,7 @@ static int efm32_interrupt(struct uart_dev_s *dev) * FERR - Framing Error Interrupt Enable */ - llerr("RX ERROR: %08x\n", intflags); + _llerr("RX ERROR: %08x\n", intflags); } /* Check for transmit errors */ @@ -527,7 +527,7 @@ static int efm32_interrupt(struct uart_dev_s *dev) { /* TXOF - TX Overflow Interrupt Enable */ - llerr("RX ERROR: %08x\n", intflags); + _llerr("RX ERROR: %08x\n", intflags); } #endif diff --git a/arch/arm/src/efm32/efm32_rmu.h b/arch/arm/src/efm32/efm32_rmu.h index d633c9f73c..215f0c85e8 100644 --- a/arch/arm/src/efm32/efm32_rmu.h +++ b/arch/arm/src/efm32/efm32_rmu.h @@ -56,9 +56,9 @@ #endif #ifdef CONFIG_EFM32_RMU_DEBUG -# define rmuerr llerr +# define rmuerr _llerr # ifdef CONFIG_DEBUG_INFO -# define rmuinfo llerr +# define rmuinfo _llerr # else # define rmuinfo(x...) # endif diff --git a/arch/arm/src/efm32/efm32_serial.c b/arch/arm/src/efm32/efm32_serial.c index 762da175a9..ff8c0f7dac 100644 --- a/arch/arm/src/efm32/efm32_serial.c +++ b/arch/arm/src/efm32/efm32_serial.c @@ -780,7 +780,7 @@ static int efm32_rxinterrupt(struct uart_dev_s *dev) * FERR - Framing Error Interrupt Enable */ - llerr("RX ERROR: %08x\n", intflags); + _llerr("RX ERROR: %08x\n", intflags); } #endif @@ -863,7 +863,7 @@ static int efm32_txinterrupt(struct uart_dev_s *dev) { /* TXOF - TX Overflow Interrupt Enable */ - llerr("RX ERROR: %08x\n", intflags); + _llerr("RX ERROR: %08x\n", intflags); } #endif diff --git a/arch/arm/src/efm32/efm32_usbdev.c b/arch/arm/src/efm32/efm32_usbdev.c index a6f4c7362c..207cce2e94 100644 --- a/arch/arm/src/efm32/efm32_usbdev.c +++ b/arch/arm/src/efm32/efm32_usbdev.c @@ -815,7 +815,7 @@ static uint32_t efm32_getreg(uint32_t addr) { if (count == 4) { - llerr("...\n"); + _llerr("...\n"); } return val; @@ -832,7 +832,7 @@ static uint32_t efm32_getreg(uint32_t addr) { /* Yes.. then show how many times the value repeated */ - llerr("[repeats %d more times]\n", count-3); + _llerr("[repeats %d more times]\n", count-3); } /* Save the new address, value, and count */ @@ -844,7 +844,7 @@ static uint32_t efm32_getreg(uint32_t addr) /* Show the register value read */ - llerr("%08x->%08x\n", addr, val); + _llerr("%08x->%08x\n", addr, val); return val; } #endif @@ -862,7 +862,7 @@ static void efm32_putreg(uint32_t val, uint32_t addr) { /* Show the register value being written */ - llerr("%08x<-%08x\n", addr, val); + _llerr("%08x<-%08x\n", addr, val); /* Write the value */ diff --git a/arch/arm/src/efm32/efm32_usbhost.c b/arch/arm/src/efm32/efm32_usbhost.c index 55786d14e0..ccfd96e34b 100644 --- a/arch/arm/src/efm32/efm32_usbhost.c +++ b/arch/arm/src/efm32/efm32_usbhost.c @@ -582,7 +582,7 @@ static const struct efm32_usbhost_trace_s g_trace2[TRACE2_NSTRINGS] = #ifdef CONFIG_EFM32_USBHOST_REGDEBUG static void efm32_printreg(uint32_t addr, uint32_t val, bool iswrite) { - llerr("%08x%s%08x\n", addr, iswrite ? "<-" : "->", val); + _llerr("%08x%s%08x\n", addr, iswrite ? "<-" : "->", val); } #endif @@ -632,7 +632,7 @@ static void efm32_checkreg(uint32_t addr, uint32_t val, bool iswrite) { /* No.. More than one. */ - llerr("[repeats %d more times]\n", count); + _llerr("[repeats %d more times]\n", count); } } diff --git a/arch/arm/src/kinetis/kinetis_irq.c b/arch/arm/src/kinetis/kinetis_irq.c index a7a5cab620..2ce3d373a9 100644 --- a/arch/arm/src/kinetis/kinetis_irq.c +++ b/arch/arm/src/kinetis/kinetis_irq.c @@ -173,7 +173,7 @@ static void kinetis_dumpnvic(const char *msg, int irq) static int kinetis_nmi(int irq, FAR void *context) { (void)up_irq_save(); - err("PANIC!!! NMI received\n"); + _err("PANIC!!! NMI received\n"); PANIC(); return 0; } @@ -181,7 +181,7 @@ static int kinetis_nmi(int irq, FAR void *context) static int kinetis_busfault(int irq, FAR void *context) { (void)up_irq_save(); - err("PANIC!!! Bus fault recived\n"); + _err("PANIC!!! Bus fault recived\n"); PANIC(); return 0; } @@ -189,7 +189,7 @@ static int kinetis_busfault(int irq, FAR void *context) static int kinetis_usagefault(int irq, FAR void *context) { (void)up_irq_save(); - err("PANIC!!! Usage fault received\n"); + _err("PANIC!!! Usage fault received\n"); PANIC(); return 0; } @@ -197,7 +197,7 @@ static int kinetis_usagefault(int irq, FAR void *context) static int kinetis_pendsv(int irq, FAR void *context) { (void)up_irq_save(); - err("PANIC!!! PendSV received\n"); + _err("PANIC!!! PendSV received\n"); PANIC(); return 0; } @@ -205,7 +205,7 @@ static int kinetis_pendsv(int irq, FAR void *context) static int kinetis_errmonitor(int irq, FAR void *context) { (void)up_irq_save(); - err("PANIC!!! Debug Monitor received\n"); + _err("PANIC!!! Debug Monitor received\n"); PANIC(); return 0; } @@ -213,7 +213,7 @@ static int kinetis_errmonitor(int irq, FAR void *context) static int kinetis_reserved(int irq, FAR void *context) { (void)up_irq_save(); - err("PANIC!!! Reserved interrupt\n"); + _err("PANIC!!! Reserved interrupt\n"); PANIC(); return 0; } diff --git a/arch/arm/src/kinetis/kinetis_serial.c b/arch/arm/src/kinetis/kinetis_serial.c index 3b169232a9..084204daa9 100644 --- a/arch/arm/src/kinetis/kinetis_serial.c +++ b/arch/arm/src/kinetis/kinetis_serial.c @@ -805,7 +805,7 @@ static int up_interrupt(int irq, void *context) */ regval = up_serialin(priv, KINETIS_UART_S1_OFFSET); - llerr("S1: %02x\n", regval); + _llerr("S1: %02x\n", regval); UNUSED(regval); regval = up_serialin(priv, KINETIS_UART_D_OFFSET); diff --git a/arch/arm/src/kinetis/kinetis_start.c b/arch/arm/src/kinetis/kinetis_start.c index 4b0451acf8..6744012f07 100644 --- a/arch/arm/src/kinetis/kinetis_start.c +++ b/arch/arm/src/kinetis/kinetis_start.c @@ -156,7 +156,7 @@ void __start(void) /* Show reset status */ - err("Reset status: %02x:%02x\n", + _err("Reset status: %02x:%02x\n", getreg8(KINETIS_SMC_SRSH), getreg8(KINETIS_SMC_SRSL)); /* Then start NuttX */ diff --git a/arch/arm/src/kinetis/kinetis_usbdev.c b/arch/arm/src/kinetis/kinetis_usbdev.c index dee28aed0a..406880cb2a 100644 --- a/arch/arm/src/kinetis/kinetis_usbdev.c +++ b/arch/arm/src/kinetis/kinetis_usbdev.c @@ -369,9 +369,9 @@ const struct trace_msg_t g_usb_trace_strings_deverror[] = # undef CONFIG_KHCI_USBDEV_BDTDEBUG # define CONFIG_KHCI_USBDEV_BDTDEBUG 1 -# define regerr llerr +# define regerr _llerr # ifdef CONFIG_DEBUG_INFO -# define reginfo llerr +# define reginfo _llerr # else # define reginfo(x...) # endif @@ -389,9 +389,9 @@ const struct trace_msg_t g_usb_trace_strings_deverror[] = #ifdef CONFIG_KHCI_USBDEV_BDTDEBUG -# define bdterr llerr +# define bdterr _llerr # ifdef CONFIG_DEBUG_INFO -# define bdtinfo llerr +# define bdtinfo _llerr # else # define bdtinfo(x...) # endif @@ -714,7 +714,7 @@ static uint16_t khci_getreg(uint32_t addr) { if (count == 4) { - llerr("...\n"); + _llerr("...\n"); } return val; } @@ -730,7 +730,7 @@ static uint16_t khci_getreg(uint32_t addr) { /* Yes.. then show how many times the value repeated */ - llerr("[repeats %d more times]\n", count-3); + _llerr("[repeats %d more times]\n", count-3); } /* Save the new address, value, and count */ @@ -742,7 +742,7 @@ static uint16_t khci_getreg(uint32_t addr) /* Show the register value read */ - llerr("%08x->%04x\n", addr, val); + _llerr("%08x->%04x\n", addr, val); return val; } #endif @@ -756,7 +756,7 @@ static void khci_putreg(uint32_t val, uint32_t addr) { /* Show the register value being written */ - llerr("%08x<-%04x\n", addr, val); + _llerr("%08x<-%04x\n", addr, val); /* Write the value */ diff --git a/arch/arm/src/kl/kl_dumpgpio.c b/arch/arm/src/kl/kl_dumpgpio.c index 60eea46009..8ca8e15002 100644 --- a/arch/arm/src/kl/kl_dumpgpio.c +++ b/arch/arm/src/kl/kl_dumpgpio.c @@ -118,9 +118,9 @@ void kl_dumpgpio(gpio_cfgset_t pinset, const char *msg) flags = enter_critical_section(); - llinfo("GPIO%c pinset: %08x base: %08x -- %s\n", + _llinfo("GPIO%c pinset: %08x base: %08x -- %s\n", g_portchar[port], pinset, base, msg); - llinfo(" PDOR: %08x PDIR: %08x PDDR: %08x\n", + _llinfo(" PDOR: %08x PDIR: %08x PDDR: %08x\n", getreg32(base + KL_GPIO_PDOR_OFFSET), getreg32(base + KL_GPIO_PDIR_OFFSET), getreg32(base + KL_GPIO_PDDR_OFFSET)); diff --git a/arch/arm/src/kl/kl_idle.c b/arch/arm/src/kl/kl_idle.c index b8a51b04da..1122cf4391 100644 --- a/arch/arm/src/kl/kl_idle.c +++ b/arch/arm/src/kl/kl_idle.c @@ -103,7 +103,7 @@ static void up_idlepm(void) /* Perform board-specific, state-dependent logic here */ - llinfo("newstate= %d oldstate=%d\n", newstate, oldstate); + _llinfo("newstate= %d oldstate=%d\n", newstate, oldstate); /* Then force the global state change */ diff --git a/arch/arm/src/kl/kl_irq.c b/arch/arm/src/kl/kl_irq.c index 100b91edba..c76a07ed25 100644 --- a/arch/arm/src/kl/kl_irq.c +++ b/arch/arm/src/kl/kl_irq.c @@ -141,7 +141,7 @@ static void kl_dumpnvic(const char *msg, int irq) static int kl_nmi(int irq, FAR void *context) { (void)up_irq_save(); - err("PANIC!!! NMI received\n"); + _err("PANIC!!! NMI received\n"); PANIC(); return 0; } @@ -149,7 +149,7 @@ static int kl_nmi(int irq, FAR void *context) static int kl_pendsv(int irq, FAR void *context) { (void)up_irq_save(); - err("PANIC!!! PendSV received\n"); + _err("PANIC!!! PendSV received\n"); PANIC(); return 0; } @@ -157,7 +157,7 @@ static int kl_pendsv(int irq, FAR void *context) static int kl_reserved(int irq, FAR void *context) { (void)up_irq_save(); - err("PANIC!!! Reserved interrupt\n"); + _err("PANIC!!! Reserved interrupt\n"); PANIC(); return 0; } diff --git a/arch/arm/src/lpc11xx/lpc11_i2c.c b/arch/arm/src/lpc11xx/lpc11_i2c.c index 6d4c60f852..46011f7508 100644 --- a/arch/arm/src/lpc11xx/lpc11_i2c.c +++ b/arch/arm/src/lpc11xx/lpc11_i2c.c @@ -485,7 +485,7 @@ struct i2c_master_s *lpc11_i2cbus_initialize(int port) if (port > 1) { - err("lpc I2C Only support 0,1\n"); + _err("lpc I2C Only support 0,1\n"); return NULL; } diff --git a/arch/arm/src/lpc11xx/lpc11_irq.c b/arch/arm/src/lpc11xx/lpc11_irq.c index 793463eb5f..d907b7d4ae 100644 --- a/arch/arm/src/lpc11xx/lpc11_irq.c +++ b/arch/arm/src/lpc11xx/lpc11_irq.c @@ -137,7 +137,7 @@ static void lpc11_dumpnvic(const char *msg, int irq) static int lpc11_nmi(int irq, FAR void *context) { (void)up_irq_save(); - err("PANIC!!! NMI received\n"); + _err("PANIC!!! NMI received\n"); PANIC(); return 0; } @@ -145,7 +145,7 @@ static int lpc11_nmi(int irq, FAR void *context) static int lpc11_pendsv(int irq, FAR void *context) { (void)up_irq_save(); - err("PANIC!!! PendSV received\n"); + _err("PANIC!!! PendSV received\n"); PANIC(); return 0; } @@ -153,7 +153,7 @@ static int lpc11_pendsv(int irq, FAR void *context) static int lpc11_reserved(int irq, FAR void *context) { (void)up_irq_save(); - err("PANIC!!! Reserved interrupt\n"); + _err("PANIC!!! Reserved interrupt\n"); PANIC(); return 0; } diff --git a/arch/arm/src/lpc11xx/lpc11_serial.c b/arch/arm/src/lpc11xx/lpc11_serial.c index 331c4df7c2..b9365615da 100644 --- a/arch/arm/src/lpc11xx/lpc11_serial.c +++ b/arch/arm/src/lpc11xx/lpc11_serial.c @@ -630,7 +630,7 @@ static int up_interrupt(int irq, void *context) /* Read the line status register (LSR) to clear */ status = up_serialin(priv, LPC11_UART_LSR_OFFSET); - info("LSR: %02x\n", status); + _info("LSR: %02x\n", status); break; } @@ -638,7 +638,7 @@ static int up_interrupt(int irq, void *context) default: { - err("Unexpected IIR: %02x\n", status); + _err("Unexpected IIR: %02x\n", status); break; } } diff --git a/arch/arm/src/lpc17xx/lpc17_can.c b/arch/arm/src/lpc17xx/lpc17_can.c index d1b66ac3b6..802fe89ae9 100644 --- a/arch/arm/src/lpc17xx/lpc17_can.c +++ b/arch/arm/src/lpc17xx/lpc17_can.c @@ -308,7 +308,7 @@ static void can_printreg(uint32_t addr, uint32_t value) { if (count == 4) { - llerr("...\n"); + _llerr("...\n"); } return; @@ -325,7 +325,7 @@ static void can_printreg(uint32_t addr, uint32_t value) { /* Yes.. then show how many times the value repeated */ - llerr("[repeats %d more times]\n", count-3); + _llerr("[repeats %d more times]\n", count-3); } /* Save the new address, value, and count */ @@ -337,7 +337,7 @@ static void can_printreg(uint32_t addr, uint32_t value) /* Show the register value read */ - llerr("%08x->%08x\n", addr, value); + _llerr("%08x->%08x\n", addr, value); } #endif @@ -398,7 +398,7 @@ static void can_putreg(struct up_dev_s *priv, int offset, uint32_t value) /* Show the register value being written */ - llerr("%08x<-%08x\n", addr, value); + _llerr("%08x<-%08x\n", addr, value); /* Write the value */ @@ -458,7 +458,7 @@ static void can_putcommon(uint32_t addr, uint32_t value) { /* Show the register value being written */ - llerr("%08x<-%08x\n", addr, value); + _llerr("%08x<-%08x\n", addr, value); /* Write the value */ @@ -681,7 +681,7 @@ static void can_txint(FAR struct can_dev_s *dev, bool enable) static int can_ioctl(FAR struct can_dev_s *dev, int cmd, unsigned long arg) { - err("Fix me:Not Implemented\n"); + _err("Fix me:Not Implemented\n"); return 0; } @@ -701,7 +701,7 @@ static int can_ioctl(FAR struct can_dev_s *dev, int cmd, unsigned long arg) static int can_remoterequest(FAR struct can_dev_s *dev, uint16_t id) { - err("Fix me:Not Implemented\n"); + _err("Fix me:Not Implemented\n"); return 0; } diff --git a/arch/arm/src/lpc17xx/lpc17_dac.c b/arch/arm/src/lpc17xx/lpc17_dac.c index 6508b09683..d936aa0fc5 100644 --- a/arch/arm/src/lpc17xx/lpc17_dac.c +++ b/arch/arm/src/lpc17xx/lpc17_dac.c @@ -172,7 +172,7 @@ static int dac_send(FAR struct dac_dev_s *dev, FAR struct dac_msg_s *msg) static int dac_ioctl(FAR struct dac_dev_s *dev, int cmd, unsigned long arg) { - err("Fix me:Not Implemented\n"); + _err("Fix me:Not Implemented\n"); return 0; } diff --git a/arch/arm/src/lpc17xx/lpc17_ethernet.c b/arch/arm/src/lpc17xx/lpc17_ethernet.c index ef4957cba7..a7a28a2616 100644 --- a/arch/arm/src/lpc17xx/lpc17_ethernet.c +++ b/arch/arm/src/lpc17xx/lpc17_ethernet.c @@ -415,7 +415,7 @@ static void lpc17_ethreset(struct lpc17_driver_s *priv); #ifdef CONFIG_NET_REGDEBUG static void lpc17_printreg(uint32_t addr, uint32_t val, bool iswrite) { - err("%08x%s%08x\n", addr, iswrite ? "<-" : "->", val); + _err("%08x%s%08x\n", addr, iswrite ? "<-" : "->", val); } #endif @@ -465,7 +465,7 @@ static void lpc17_checkreg(uint32_t addr, uint32_t val, bool iswrite) { /* No.. More than one. */ - err("[repeats %d more times]\n", count); + _err("[repeats %d more times]\n", count); } } @@ -2319,14 +2319,14 @@ static void lpc17_showpins(void) #if defined(CONFIG_NET_REGDEBUG) && defined(LPC17_HAVE_PHY) static void lpc17_showmii(uint8_t phyaddr, const char *msg) { - err("PHY " LPC17_PHYNAME ": %s\n", msg); - err(" MCR: %04x\n", lpc17_phyread(phyaddr, MII_MCR)); - err(" MSR: %04x\n", lpc17_phyread(phyaddr, MII_MSR)); - err(" ADVERTISE: %04x\n", lpc17_phyread(phyaddr, MII_ADVERTISE)); - err(" LPA: %04x\n", lpc17_phyread(phyaddr, MII_LPA)); - err(" EXPANSION: %04x\n", lpc17_phyread(phyaddr, MII_EXPANSION)); + _err("PHY " LPC17_PHYNAME ": %s\n", msg); + _err(" MCR: %04x\n", lpc17_phyread(phyaddr, MII_MCR)); + _err(" MSR: %04x\n", lpc17_phyread(phyaddr, MII_MSR)); + _err(" ADVERTISE: %04x\n", lpc17_phyread(phyaddr, MII_ADVERTISE)); + _err(" LPA: %04x\n", lpc17_phyread(phyaddr, MII_LPA)); + _err(" EXPANSION: %04x\n", lpc17_phyread(phyaddr, MII_EXPANSION)); #ifdef CONFIG_ETH0_PHY_KS8721 - err(" 10BTCR: %04x\n", lpc17_phyread(phyaddr, MII_KS8721_10BTCR)); + _err(" 10BTCR: %04x\n", lpc17_phyread(phyaddr, MII_KS8721_10BTCR)); #endif } #endif diff --git a/arch/arm/src/lpc17xx/lpc17_i2c.c b/arch/arm/src/lpc17xx/lpc17_i2c.c index 7b5346e9f3..a4f817be33 100644 --- a/arch/arm/src/lpc17xx/lpc17_i2c.c +++ b/arch/arm/src/lpc17xx/lpc17_i2c.c @@ -485,7 +485,7 @@ struct i2c_master_s *lpc17_i2cbus_initialize(int port) if (port > 1) { - err("lpc I2C Only support 0,1\n"); + _err("lpc I2C Only support 0,1\n"); return NULL; } diff --git a/arch/arm/src/lpc17xx/lpc17_irq.c b/arch/arm/src/lpc17xx/lpc17_irq.c index 595e9cf594..a3ada9cbe8 100644 --- a/arch/arm/src/lpc17xx/lpc17_irq.c +++ b/arch/arm/src/lpc17xx/lpc17_irq.c @@ -152,7 +152,7 @@ static void lpc17_dumpnvic(const char *msg, int irq) static int lpc17_nmi(int irq, FAR void *context) { (void)up_irq_save(); - err("PANIC!!! NMI received\n"); + _err("PANIC!!! NMI received\n"); PANIC(); return 0; } @@ -160,7 +160,7 @@ static int lpc17_nmi(int irq, FAR void *context) static int lpc17_busfault(int irq, FAR void *context) { (void)up_irq_save(); - err("PANIC!!! Bus fault recived\n"); + _err("PANIC!!! Bus fault recived\n"); PANIC(); return 0; } @@ -168,7 +168,7 @@ static int lpc17_busfault(int irq, FAR void *context) static int lpc17_usagefault(int irq, FAR void *context) { (void)up_irq_save(); - err("PANIC!!! Usage fault received\n"); + _err("PANIC!!! Usage fault received\n"); PANIC(); return 0; } @@ -176,7 +176,7 @@ static int lpc17_usagefault(int irq, FAR void *context) static int lpc17_pendsv(int irq, FAR void *context) { (void)up_irq_save(); - err("PANIC!!! PendSV received\n"); + _err("PANIC!!! PendSV received\n"); PANIC(); return 0; } @@ -184,7 +184,7 @@ static int lpc17_pendsv(int irq, FAR void *context) static int lpc17_errmonitor(int irq, FAR void *context) { (void)up_irq_save(); - err("PANIC!!! Debug Monitor received\n"); + _err("PANIC!!! Debug Monitor received\n"); PANIC(); return 0; } @@ -192,7 +192,7 @@ static int lpc17_errmonitor(int irq, FAR void *context) static int lpc17_reserved(int irq, FAR void *context) { (void)up_irq_save(); - err("PANIC!!! Reserved interrupt\n"); + _err("PANIC!!! Reserved interrupt\n"); PANIC(); return 0; } diff --git a/arch/arm/src/lpc17xx/lpc17_serial.c b/arch/arm/src/lpc17xx/lpc17_serial.c index 94a92873d2..0ec62236a6 100644 --- a/arch/arm/src/lpc17xx/lpc17_serial.c +++ b/arch/arm/src/lpc17xx/lpc17_serial.c @@ -1134,7 +1134,7 @@ static int up_interrupt(int irq, void *context) /* Read the modem status register (MSR) to clear */ status = up_serialin(priv, LPC17_UART_MSR_OFFSET); - info("MSR: %02x\n", status); + _info("MSR: %02x\n", status); break; } @@ -1145,7 +1145,7 @@ static int up_interrupt(int irq, void *context) /* Read the line status register (LSR) to clear */ status = up_serialin(priv, LPC17_UART_LSR_OFFSET); - info("LSR: %02x\n", status); + _info("LSR: %02x\n", status); break; } @@ -1153,7 +1153,7 @@ static int up_interrupt(int irq, void *context) default: { - err("Unexpected IIR: %02x\n", status); + _err("Unexpected IIR: %02x\n", status); break; } } diff --git a/arch/arm/src/lpc17xx/lpc17_usbdev.c b/arch/arm/src/lpc17xx/lpc17_usbdev.c index f96e91f6aa..d2c4606283 100644 --- a/arch/arm/src/lpc17xx/lpc17_usbdev.c +++ b/arch/arm/src/lpc17xx/lpc17_usbdev.c @@ -531,7 +531,7 @@ static struct lpc17_dmadesc_s g_usbddesc[CONFIG_LPC17_USBDEV_NDMADESCRIPTORS]; #ifdef CONFIG_LPC17_USBDEV_REGDEBUG static void lpc17_printreg(uint32_t addr, uint32_t val, bool iswrite) { - llerr("%08x%s%08x\n", addr, iswrite ? "<-" : "->", val); + _llerr("%08x%s%08x\n", addr, iswrite ? "<-" : "->", val); } #endif @@ -581,7 +581,7 @@ static void lpc17_checkreg(uint32_t addr, uint32_t val, bool iswrite) { /* No.. More than one. */ - llerr("[repeats %d more times]\n", count); + _llerr("[repeats %d more times]\n", count); } } diff --git a/arch/arm/src/lpc17xx/lpc17_usbhost.c b/arch/arm/src/lpc17xx/lpc17_usbhost.c index 7825df9672..7d707daf79 100644 --- a/arch/arm/src/lpc17xx/lpc17_usbhost.c +++ b/arch/arm/src/lpc17xx/lpc17_usbhost.c @@ -456,7 +456,7 @@ static struct lpc17_xfrinfo_s g_xfrbuffers[CONFIG_LPC17_USBHOST_NPREALLOC]; #ifdef CONFIG_LPC17_USBHOST_REGDEBUG static void lpc17_printreg(uint32_t addr, uint32_t val, bool iswrite) { - llerr("%08x%s%08x\n", addr, iswrite ? "<-" : "->", val); + _llerr("%08x%s%08x\n", addr, iswrite ? "<-" : "->", val); } #endif @@ -506,7 +506,7 @@ static void lpc17_checkreg(uint32_t addr, uint32_t val, bool iswrite) { /* No.. More than one. */ - llerr("[repeats %d more times]\n", count); + _llerr("[repeats %d more times]\n", count); } } diff --git a/arch/arm/src/lpc214x/lpc214x_serial.c b/arch/arm/src/lpc214x/lpc214x_serial.c index b0bcafd44e..1f699f5129 100644 --- a/arch/arm/src/lpc214x/lpc214x_serial.c +++ b/arch/arm/src/lpc214x/lpc214x_serial.c @@ -530,7 +530,7 @@ static int up_interrupt(int irq, void *context) /* Read the modem status register (MSR) to clear */ status = up_serialin(priv, LPC214X_UART_MSR_OFFSET); - info("MSR: %02x\n", status); + _info("MSR: %02x\n", status); break; } @@ -541,7 +541,7 @@ static int up_interrupt(int irq, void *context) /* Read the line status register (LSR) to clear */ status = up_serialin(priv, LPC214X_UART_LSR_OFFSET); - info("LSR: %02x\n", status); + _info("LSR: %02x\n", status); break; } @@ -549,7 +549,7 @@ static int up_interrupt(int irq, void *context) default: { - err("Unexpected IIR: %02x\n", status); + _err("Unexpected IIR: %02x\n", status); break; } } diff --git a/arch/arm/src/lpc214x/lpc214x_usbdev.c b/arch/arm/src/lpc214x/lpc214x_usbdev.c index 431b71655e..e9ea74f088 100644 --- a/arch/arm/src/lpc214x/lpc214x_usbdev.c +++ b/arch/arm/src/lpc214x/lpc214x_usbdev.c @@ -539,7 +539,7 @@ static uint32_t lpc214x_getreg(uint32_t addr) { if (count == 4) { - llerr("...\n"); + _llerr("...\n"); } return val; @@ -556,7 +556,7 @@ static uint32_t lpc214x_getreg(uint32_t addr) { /* Yes.. then show how many times the value repeated */ - llerr("[repeats %d more times]\n", count-3); + _llerr("[repeats %d more times]\n", count-3); } /* Save the new address, value, and count */ @@ -568,7 +568,7 @@ static uint32_t lpc214x_getreg(uint32_t addr) /* Show the register value read */ - llerr("%08x->%08x\n", addr, val); + _llerr("%08x->%08x\n", addr, val); return val; } #endif @@ -586,7 +586,7 @@ static void lpc214x_putreg(uint32_t val, uint32_t addr) { /* Show the register value being written */ - llerr("%08x<-%08x\n", addr, val); + _llerr("%08x<-%08x\n", addr, val); /* Write the value */ diff --git a/arch/arm/src/lpc2378/lpc23xx_i2c.c b/arch/arm/src/lpc2378/lpc23xx_i2c.c index d3bec89884..6932e93210 100644 --- a/arch/arm/src/lpc2378/lpc23xx_i2c.c +++ b/arch/arm/src/lpc2378/lpc23xx_i2c.c @@ -490,7 +490,7 @@ struct i2c_master_s *lpc2378_i2cbus_initialize(int port) if (port > 1) { - err("lpc I2C Only support 0,1\n"); + _err("lpc I2C Only support 0,1\n"); return NULL; } diff --git a/arch/arm/src/lpc2378/lpc23xx_serial.c b/arch/arm/src/lpc2378/lpc23xx_serial.c index 9ea299783d..50aaa662a6 100644 --- a/arch/arm/src/lpc2378/lpc23xx_serial.c +++ b/arch/arm/src/lpc2378/lpc23xx_serial.c @@ -648,7 +648,7 @@ static int up_interrupt(int irq, void *context) /* Read the modem status register (MSR) to clear */ status = up_serialin(priv, UART_MSR_OFFSET); - info("MSR: %02x\n", status); + _info("MSR: %02x\n", status); break; } @@ -659,7 +659,7 @@ static int up_interrupt(int irq, void *context) /* Read the line status register (LSR) to clear */ status = up_serialin(priv, UART_LSR_OFFSET); - info("LSR: %02x\n", status); + _info("LSR: %02x\n", status); break; } @@ -667,7 +667,7 @@ static int up_interrupt(int irq, void *context) default: { - err("Unexpected IIR: %02x\n", status); + _err("Unexpected IIR: %02x\n", status); break; } } diff --git a/arch/arm/src/lpc31xx/lpc31_ehci.c b/arch/arm/src/lpc31xx/lpc31_ehci.c index 0734e85e51..1532feddbd 100644 --- a/arch/arm/src/lpc31xx/lpc31_ehci.c +++ b/arch/arm/src/lpc31xx/lpc31_ehci.c @@ -826,7 +826,7 @@ static uint32_t lpc31_swap32(uint32_t value) static void lpc31_printreg(volatile uint32_t *regaddr, uint32_t regval, bool iswrite) { - llerr("%08x%s%08x\n", (uintptr_t)regaddr, iswrite ? "<-" : "->", regval); + _llerr("%08x%s%08x\n", (uintptr_t)regaddr, iswrite ? "<-" : "->", regval); } #endif @@ -877,7 +877,7 @@ static void lpc31_checkreg(volatile uint32_t *regaddr, uint32_t regval, bool isw { /* No.. More than one. */ - llerr("[repeats %d more times]\n", count); + _llerr("[repeats %d more times]\n", count); } } diff --git a/arch/arm/src/lpc31xx/lpc31_serial.c b/arch/arm/src/lpc31xx/lpc31_serial.c index c3b9b3f509..b46c0598fc 100644 --- a/arch/arm/src/lpc31xx/lpc31_serial.c +++ b/arch/arm/src/lpc31xx/lpc31_serial.c @@ -560,7 +560,7 @@ static int up_interrupt(int irq, void *context) default: { - err("Unexpected IIR: %02x\n", status); + _err("Unexpected IIR: %02x\n", status); break; } } diff --git a/arch/arm/src/lpc31xx/lpc31_spi.c b/arch/arm/src/lpc31xx/lpc31_spi.c index c72a0221c0..074bbe2b7d 100644 --- a/arch/arm/src/lpc31xx/lpc31_spi.c +++ b/arch/arm/src/lpc31xx/lpc31_spi.c @@ -207,7 +207,7 @@ static bool spi_checkreg(bool wr, uint32_t value, uint32_t address) { if (g_ntimes > 0) { - llerr("...[Repeats %d times]...\n", g_ntimes); + _llerr("...[Repeats %d times]...\n", g_ntimes); } g_wrlast = wr; @@ -239,7 +239,7 @@ static void spi_putreg(uint32_t value, uint32_t address) { if (spi_checkreg(true, value, address)) { - llerr("%08x<-%08x\n", address, value); + _llerr("%08x<-%08x\n", address, value); } putreg32(value, address); } @@ -265,7 +265,7 @@ static uint32_t spi_getreg(uint32_t address) uint32_t value = getreg32(address); if (spi_checkreg(false, value, address)) { - llerr("%08x->%08x\n", address, value); + _llerr("%08x->%08x\n", address, value); } return value; } @@ -921,7 +921,7 @@ FAR struct spi_dev_s *lpc31_spibus_initialize(int port) */ #ifdef CONFIG_LPC31_SPI_REGDEBUG - llerr("PINS: %08x MODE0: %08x MODE1: %08x\n", + _llerr("PINS: %08x MODE0: %08x MODE1: %08x\n", spi_getreg(LPC31_IOCONFIG_SPI_PINS), spi_getreg(LPC31_IOCONFIG_SPI_MODE0), spi_getreg(LPC31_IOCONFIG_SPI_MODE1)); diff --git a/arch/arm/src/lpc31xx/lpc31_usbdev.c b/arch/arm/src/lpc31xx/lpc31_usbdev.c index 3d56725cea..f75eb1aa52 100644 --- a/arch/arm/src/lpc31xx/lpc31_usbdev.c +++ b/arch/arm/src/lpc31xx/lpc31_usbdev.c @@ -501,7 +501,7 @@ static uint32_t lpc31_getreg(uint32_t addr) { if (count == 4) { - llerr("...\n"); + _llerr("...\n"); } return val; @@ -518,7 +518,7 @@ static uint32_t lpc31_getreg(uint32_t addr) { /* Yes.. then show how many times the value repeated */ - llerr("[repeats %d more times]\n", count-3); + _llerr("[repeats %d more times]\n", count-3); } /* Save the new address, value, and count */ @@ -530,7 +530,7 @@ static uint32_t lpc31_getreg(uint32_t addr) /* Show the register value read */ - llerr("%08x->%08x\n", addr, val); + _llerr("%08x->%08x\n", addr, val); return val; } #endif @@ -548,7 +548,7 @@ static void lpc31_putreg(uint32_t val, uint32_t addr) { /* Show the register value being written */ - llerr("%08x<-%08x\n", addr, val); + _llerr("%08x<-%08x\n", addr, val); /* Write the value */ diff --git a/arch/arm/src/lpc43xx/lpc43_dac.c b/arch/arm/src/lpc43xx/lpc43_dac.c index b9ab14b874..f14186f7d1 100644 --- a/arch/arm/src/lpc43xx/lpc43_dac.c +++ b/arch/arm/src/lpc43xx/lpc43_dac.c @@ -173,7 +173,7 @@ static int dac_send(FAR struct dac_dev_s *dev, FAR struct dac_msg_s *msg) static int dac_ioctl(FAR struct dac_dev_s *dev, int cmd, unsigned long arg) { - err("Fix me:Not Implemented\n"); + _err("Fix me:Not Implemented\n"); return 0; } diff --git a/arch/arm/src/lpc43xx/lpc43_ehci.c b/arch/arm/src/lpc43xx/lpc43_ehci.c index a0d4d1160e..a0483accd4 100644 --- a/arch/arm/src/lpc43xx/lpc43_ehci.c +++ b/arch/arm/src/lpc43xx/lpc43_ehci.c @@ -817,7 +817,7 @@ static uint32_t lpc43_swap32(uint32_t value) static void lpc43_printreg(volatile uint32_t *regaddr, uint32_t regval, bool iswrite) { - llerr("%08x%s%08x\n", (uintptr_t)regaddr, iswrite ? "<-" : "->", regval); + _llerr("%08x%s%08x\n", (uintptr_t)regaddr, iswrite ? "<-" : "->", regval); } #endif @@ -868,7 +868,7 @@ static void lpc43_checkreg(volatile uint32_t *regaddr, uint32_t regval, bool isw { /* No.. More than one. */ - llerr("[repeats %d more times]\n", count); + _llerr("[repeats %d more times]\n", count); } } diff --git a/arch/arm/src/lpc43xx/lpc43_ethernet.c b/arch/arm/src/lpc43xx/lpc43_ethernet.c index 37e39dee6d..13b2983aaf 100644 --- a/arch/arm/src/lpc43xx/lpc43_ethernet.c +++ b/arch/arm/src/lpc43xx/lpc43_ethernet.c @@ -704,7 +704,7 @@ static uint32_t lpc43_getreg(uint32_t addr) { if (count == 4) { - llerr("...\n"); + _llerr("...\n"); } return val; @@ -721,7 +721,7 @@ static uint32_t lpc43_getreg(uint32_t addr) { /* Yes.. then show how many times the value repeated */ - llerr("[repeats %d more times]\n", count-3); + _llerr("[repeats %d more times]\n", count-3); } /* Save the new address, value, and count */ @@ -733,7 +733,7 @@ static uint32_t lpc43_getreg(uint32_t addr) /* Show the register value read */ - llerr("%08x->%08x\n", addr, val); + _llerr("%08x->%08x\n", addr, val); return val; } #endif @@ -760,7 +760,7 @@ static void lpc43_putreg(uint32_t val, uint32_t addr) { /* Show the register value being written */ - llerr("%08x<-%08x\n", addr, val); + _llerr("%08x<-%08x\n", addr, val); /* Write the value */ diff --git a/arch/arm/src/lpc43xx/lpc43_i2c.c b/arch/arm/src/lpc43xx/lpc43_i2c.c index 9bc4f4b6e0..4ec260760b 100644 --- a/arch/arm/src/lpc43xx/lpc43_i2c.c +++ b/arch/arm/src/lpc43xx/lpc43_i2c.c @@ -464,7 +464,7 @@ struct i2c_master_s *lpc43_i2cbus_initialize(int port) if (port > 1) { - err("lpc I2C Only support 0,1\n"); + _err("lpc I2C Only support 0,1\n"); return NULL; } diff --git a/arch/arm/src/lpc43xx/lpc43_idle.c b/arch/arm/src/lpc43xx/lpc43_idle.c index 4dc5a30209..89c9d98e83 100644 --- a/arch/arm/src/lpc43xx/lpc43_idle.c +++ b/arch/arm/src/lpc43xx/lpc43_idle.c @@ -98,7 +98,7 @@ static void up_idlepm(void) /* Perform board-specific, state-dependent logic here */ - llinfo("newstate= %d oldstate=%d\n", newstate, oldstate); + _llinfo("newstate= %d oldstate=%d\n", newstate, oldstate); /* Then force the global state change */ diff --git a/arch/arm/src/lpc43xx/lpc43_irq.c b/arch/arm/src/lpc43xx/lpc43_irq.c index 77189d2079..ea87cec8fe 100644 --- a/arch/arm/src/lpc43xx/lpc43_irq.c +++ b/arch/arm/src/lpc43xx/lpc43_irq.c @@ -161,7 +161,7 @@ static void lpc43_dumpnvic(const char *msg, int irq) static int lpc43_nmi(int irq, FAR void *context) { (void)up_irq_save(); - err("PANIC!!! NMI received\n"); + _err("PANIC!!! NMI received\n"); PANIC(); return 0; } @@ -169,7 +169,7 @@ static int lpc43_nmi(int irq, FAR void *context) static int lpc43_busfault(int irq, FAR void *context) { (void)up_irq_save(); - err("PANIC!!! Bus fault recived\n"); + _err("PANIC!!! Bus fault recived\n"); PANIC(); return 0; } @@ -177,7 +177,7 @@ static int lpc43_busfault(int irq, FAR void *context) static int lpc43_usagefault(int irq, FAR void *context) { (void)up_irq_save(); - err("PANIC!!! Usage fault received\n"); + _err("PANIC!!! Usage fault received\n"); PANIC(); return 0; } @@ -185,7 +185,7 @@ static int lpc43_usagefault(int irq, FAR void *context) static int lpc43_pendsv(int irq, FAR void *context) { (void)up_irq_save(); - err("PANIC!!! PendSV received\n"); + _err("PANIC!!! PendSV received\n"); PANIC(); return 0; } @@ -193,7 +193,7 @@ static int lpc43_pendsv(int irq, FAR void *context) static int lpc43_errmonitor(int irq, FAR void *context) { (void)up_irq_save(); - err("PANIC!!! Debug Monitor received\n"); + _err("PANIC!!! Debug Monitor received\n"); PANIC(); return 0; } @@ -201,7 +201,7 @@ static int lpc43_errmonitor(int irq, FAR void *context) static int lpc43_reserved(int irq, FAR void *context) { (void)up_irq_save(); - err("PANIC!!! Reserved interrupt\n"); + _err("PANIC!!! Reserved interrupt\n"); PANIC(); return 0; } diff --git a/arch/arm/src/lpc43xx/lpc43_rit.c b/arch/arm/src/lpc43xx/lpc43_rit.c index 2b153fb1b3..7d68c8f58b 100644 --- a/arch/arm/src/lpc43xx/lpc43_rit.c +++ b/arch/arm/src/lpc43xx/lpc43_rit.c @@ -201,7 +201,7 @@ void up_timer_initialize(void) mask_bits++; } - llerr("mask_bits = %d, mask = %X, ticks_per_int = %d\r\n", + _llerr("mask_bits = %d, mask = %X, ticks_per_int = %d\r\n", mask_bits, (0xffffffff << (32 - mask_bits)), ticks_per_int); /* Set the mask and compare value so we get interrupts every diff --git a/arch/arm/src/lpc43xx/lpc43_serial.c b/arch/arm/src/lpc43xx/lpc43_serial.c index 1e045e13d7..e423e2c0da 100644 --- a/arch/arm/src/lpc43xx/lpc43_serial.c +++ b/arch/arm/src/lpc43xx/lpc43_serial.c @@ -854,7 +854,7 @@ static int up_interrupt(int irq, void *context) /* Read the modem status register (MSR) to clear */ status = up_serialin(priv, LPC43_UART_MSR_OFFSET); - info("MSR: %02x\n", status); + _info("MSR: %02x\n", status); break; } @@ -865,7 +865,7 @@ static int up_interrupt(int irq, void *context) /* Read the line status register (LSR) to clear */ status = up_serialin(priv, LPC43_UART_LSR_OFFSET); - info("LSR: %02x\n", status); + _info("LSR: %02x\n", status); break; } @@ -873,7 +873,7 @@ static int up_interrupt(int irq, void *context) default: { - err("Unexpected IIR: %02x\n", status); + _err("Unexpected IIR: %02x\n", status); break; } } diff --git a/arch/arm/src/lpc43xx/lpc43_usb0dev.c b/arch/arm/src/lpc43xx/lpc43_usb0dev.c index 035b1827b9..af5337bda2 100644 --- a/arch/arm/src/lpc43xx/lpc43_usb0dev.c +++ b/arch/arm/src/lpc43xx/lpc43_usb0dev.c @@ -522,7 +522,7 @@ static uint32_t lpc43_getreg(uint32_t addr) { if (count == 4) { - llerr("...\n"); + _llerr("...\n"); } return val; @@ -539,7 +539,7 @@ static uint32_t lpc43_getreg(uint32_t addr) { /* Yes.. then show how many times the value repeated */ - llerr("[repeats %d more times]\n", count-3); + _llerr("[repeats %d more times]\n", count-3); } /* Save the new address, value, and count */ @@ -551,7 +551,7 @@ static uint32_t lpc43_getreg(uint32_t addr) /* Show the register value read */ - llerr("%08x->%08x\n", addr, val); + _llerr("%08x->%08x\n", addr, val); return val; } #endif @@ -569,7 +569,7 @@ static void lpc43_putreg(uint32_t val, uint32_t addr) { /* Show the register value being written */ - llerr("%08x<-%08x\n", addr, val); + _llerr("%08x<-%08x\n", addr, val); /* Write the value */ diff --git a/arch/arm/src/moxart/moxart_irq.c b/arch/arm/src/moxart/moxart_irq.c index 71d9e68629..0dfd4d92ea 100644 --- a/arch/arm/src/moxart/moxart_irq.c +++ b/arch/arm/src/moxart/moxart_irq.c @@ -145,15 +145,15 @@ void up_irqinitialize(void) #if 1 #define REG(x) (*(volatile uint32_t *)(x)) - llerr("\n=============================================================\n"); - llerr("TM CNTL=%08x INTRS=%08x MASK=%08x LOAD=%08x COUNT=%08x M1=%08x\n", + _llerr("\n=============================================================\n"); + _llerr("TM CNTL=%08x INTRS=%08x MASK=%08x LOAD=%08x COUNT=%08x M1=%08x\n", REG(0x98400030), REG(0x98400034), REG(0x98400038), REG(0x98400004), REG(0x98400000), REG(0x98400008)); - llerr("IRQ STATUS=%08x MASK=%08x MODE=%08x LEVEL=%08x\n", + _llerr("IRQ STATUS=%08x MASK=%08x MODE=%08x LEVEL=%08x\n", REG(0x98800014), REG(0x98800004), REG(0x9880000C), REG(0x98800010)); - llerr("FIQ STATUS=%08x MASK=%08x MODE=%08x LEVEL=%08x\n", + _llerr("FIQ STATUS=%08x MASK=%08x MODE=%08x LEVEL=%08x\n", REG(0x98800034), REG(0x98800024), REG(0x9880002C), REG(0x98800020)); - llerr("=============================================================\n"); + _llerr("=============================================================\n"); #endif #ifndef CONFIG_SUPPRESS_INTERRUPTS diff --git a/arch/arm/src/nuc1xx/nuc_dumpgpio.c b/arch/arm/src/nuc1xx/nuc_dumpgpio.c index 45db371a8b..780f8c61d4 100644 --- a/arch/arm/src/nuc1xx/nuc_dumpgpio.c +++ b/arch/arm/src/nuc1xx/nuc_dumpgpio.c @@ -124,19 +124,19 @@ void nuc_dumpgpio(gpio_cfgset_t pinset, const char *msg) flags = enter_critical_section(); - llerr("GPIO%c pinset: %08x base: %08x -- %s\n", + _llerr("GPIO%c pinset: %08x base: %08x -- %s\n", g_portchar[port], pinset, base, msg); - llerr(" PMD: %08x OFFD: %08x DOUT: %08x DMASK: %08x\n", + _llerr(" PMD: %08x OFFD: %08x DOUT: %08x DMASK: %08x\n", getreg32(base + NUC_GPIO_PMD_OFFSET), getreg32(base + NUC_GPIO_OFFD_OFFSET), getreg32(base + NUC_GPIO_DOUT_OFFSET), getreg32(base + NUC_GPIO_DMASK_OFFSET)); - llerr(" PIN: %08x DBEN: %08x IMD: %08x IEN: %08x\n", + _llerr(" PIN: %08x DBEN: %08x IMD: %08x IEN: %08x\n", getreg32(base + NUC_GPIO_PIN_OFFSET), getreg32(base + NUC_GPIO_DBEN_OFFSET), getreg32(base + NUC_GPIO_IMD_OFFSET), getreg32(base + NUC_GPIO_IEN_OFFSET)); - llerr(" ISRC: %08x\n", + _llerr(" ISRC: %08x\n", getreg32(base + NUC_GPIO_ISRC_OFFSET)); leave_critical_section(flags); diff --git a/arch/arm/src/nuc1xx/nuc_idle.c b/arch/arm/src/nuc1xx/nuc_idle.c index e0e0131059..7462aa24aa 100644 --- a/arch/arm/src/nuc1xx/nuc_idle.c +++ b/arch/arm/src/nuc1xx/nuc_idle.c @@ -99,7 +99,7 @@ static void up_idlepm(void) /* Perform board-specific, state-dependent logic here */ - llinfo("newstate= %d oldstate=%d\n", newstate, oldstate); + _llinfo("newstate= %d oldstate=%d\n", newstate, oldstate); /* Then force the global state change */ diff --git a/arch/arm/src/nuc1xx/nuc_irq.c b/arch/arm/src/nuc1xx/nuc_irq.c index 19da86459e..ec045c3734 100644 --- a/arch/arm/src/nuc1xx/nuc_irq.c +++ b/arch/arm/src/nuc1xx/nuc_irq.c @@ -141,7 +141,7 @@ static void nuc_dumpnvic(const char *msg, int irq) static int nuc_nmi(int irq, FAR void *context) { (void)up_irq_save(); - err("PANIC!!! NMI received\n"); + _err("PANIC!!! NMI received\n"); PANIC(); return 0; } @@ -149,7 +149,7 @@ static int nuc_nmi(int irq, FAR void *context) static int nuc_pendsv(int irq, FAR void *context) { (void)up_irq_save(); - err("PANIC!!! PendSV received\n"); + _err("PANIC!!! PendSV received\n"); PANIC(); return 0; } @@ -157,7 +157,7 @@ static int nuc_pendsv(int irq, FAR void *context) static int nuc_reserved(int irq, FAR void *context) { (void)up_irq_save(); - err("PANIC!!! Reserved interrupt\n"); + _err("PANIC!!! Reserved interrupt\n"); PANIC(); return 0; } diff --git a/arch/arm/src/sam34/sam4cm_tc.c b/arch/arm/src/sam34/sam4cm_tc.c index 2ffe713072..8766a88720 100644 --- a/arch/arm/src/sam34/sam4cm_tc.c +++ b/arch/arm/src/sam34/sam4cm_tc.c @@ -390,20 +390,20 @@ static void sam_regdump(struct sam_chan_s *chan, const char *msg) uintptr_t base; base = chan->base; - llerr("TC%d [%08x]: %s\n", chan->chan, (int)base, msg); - llerr(" BMR: %08x QIMR: %08x QISR: %08x WPMR: %08x\n", + _llerr("TC%d [%08x]: %s\n", chan->chan, (int)base, msg); + _llerr(" BMR: %08x QIMR: %08x QISR: %08x WPMR: %08x\n", getreg32(base+SAM_TC_BMR_OFFSET), getreg32(base+SAM_TC_QIMR_OFFSET), getreg32(base+SAM_TC_QISR_OFFSET), getreg32(base+SAM_TC_WPMR_OFFSET)); base = chan->base; - llerr("TC%d Channel %d [%08x]: %s\n", chan->chan, chan->chan, (int)base, msg); - llerr(" CMR: %08x SSMR: %08x RAB: %08x CV: %08x\n", + _llerr("TC%d Channel %d [%08x]: %s\n", chan->chan, chan->chan, (int)base, msg); + _llerr(" CMR: %08x SSMR: %08x RAB: %08x CV: %08x\n", getreg32(base+SAM_TC_CMR_OFFSET), getreg32(base+SAM_TC_SMMR_OFFSET), getreg32(base+SAM_TC_RAB_OFFSET), getreg32(base+SAM_TC_CV_OFFSET)); - llerr(" RA: %08x RB: %08x RC: %08x SR: %08x\n", + _llerr(" RA: %08x RB: %08x RC: %08x SR: %08x\n", getreg32(base+SAM_TC_RA_OFFSET), getreg32(base+SAM_TC_RB_OFFSET), getreg32(base+SAM_TC_RC_OFFSET), getreg32(base+SAM_TC_SR_OFFSET)); - llerr(" IMR: %08x\n", + _llerr(" IMR: %08x\n", getreg32(base+SAM_TC_IMR_OFFSET)); } #endif @@ -447,7 +447,7 @@ static bool sam_checkreg(struct sam_chan_s *chan, bool wr, uint32_t regaddr, { /* Yes... show how many times we did it */ - llerr("...[Repeats %d times]...\n", chan->ntimes); + _llerr("...[Repeats %d times]...\n", chan->ntimes); } /* Save information about the new access */ @@ -481,7 +481,7 @@ static inline uint32_t sam_chan_getreg(struct sam_chan_s *chan, #ifdef CONFIG_SAM34_TC_REGDEBUG if (sam_checkreg(chan, false, regaddr, regval)) { - llerr("%08x->%08x\n", regaddr, regval); + _llerr("%08x->%08x\n", regaddr, regval); } #endif @@ -504,7 +504,7 @@ static inline void sam_chan_putreg(struct sam_chan_s *chan, unsigned int offset, #ifdef CONFIG_SAM34_TC_REGDEBUG if (sam_checkreg(chan, true, regaddr, regval)) { - llerr("%08x<-%08x\n", regaddr, regval); + _llerr("%08x<-%08x\n", regaddr, regval); } #endif diff --git a/arch/arm/src/sam34/sam_emac.c b/arch/arm/src/sam34/sam_emac.c index 1c7d627677..5a8d2673b8 100644 --- a/arch/arm/src/sam34/sam_emac.c +++ b/arch/arm/src/sam34/sam_emac.c @@ -490,7 +490,7 @@ static bool sam_checkreg(struct sam_emac_s *priv, bool wr, uint32_t regval, { /* Yes... show how many times we did it */ - llerr("...[Repeats %d times]...\n", priv->ntimes); + _llerr("...[Repeats %d times]...\n", priv->ntimes); } /* Save information about the new access */ @@ -522,7 +522,7 @@ static uint32_t sam_getreg(struct sam_emac_s *priv, uintptr_t address) if (sam_checkreg(priv, false, regval, address)) { - llerr("%08x->%08x\n", address, regval); + _llerr("%08x->%08x\n", address, regval); } return regval; @@ -543,7 +543,7 @@ static void sam_putreg(struct sam_emac_s *priv, uintptr_t address, { if (sam_checkreg(priv, true, regval, address)) { - llerr("%08x<-%08x\n", address, regval); + _llerr("%08x<-%08x\n", address, regval); } putreg32(regval, address); diff --git a/arch/arm/src/sam34/sam_irq.c b/arch/arm/src/sam34/sam_irq.c index 7dc6371541..7e002224fb 100644 --- a/arch/arm/src/sam34/sam_irq.c +++ b/arch/arm/src/sam34/sam_irq.c @@ -177,7 +177,7 @@ static void sam_dumpnvic(const char *msg, int irq) static int sam_nmi(int irq, FAR void *context) { (void)up_irq_save(); - err("PANIC!!! NMI received\n"); + _err("PANIC!!! NMI received\n"); PANIC(); return 0; } @@ -185,7 +185,7 @@ static int sam_nmi(int irq, FAR void *context) static int sam_busfault(int irq, FAR void *context) { (void)up_irq_save(); - err("PANIC!!! Bus fault received: %08x\n", getreg32(NVIC_CFAULTS)); + _err("PANIC!!! Bus fault received: %08x\n", getreg32(NVIC_CFAULTS)); PANIC(); return 0; } @@ -193,7 +193,7 @@ static int sam_busfault(int irq, FAR void *context) static int sam_usagefault(int irq, FAR void *context) { (void)up_irq_save(); - err("PANIC!!! Usage fault received: %08x\n", getreg32(NVIC_CFAULTS)); + _err("PANIC!!! Usage fault received: %08x\n", getreg32(NVIC_CFAULTS)); PANIC(); return 0; } @@ -201,7 +201,7 @@ static int sam_usagefault(int irq, FAR void *context) static int sam_pendsv(int irq, FAR void *context) { (void)up_irq_save(); - err("PANIC!!! PendSV received\n"); + _err("PANIC!!! PendSV received\n"); PANIC(); return 0; } @@ -209,7 +209,7 @@ static int sam_pendsv(int irq, FAR void *context) static int sam_errmonitor(int irq, FAR void *context) { (void)up_irq_save(); - err("PANIC!!! Debug Monitor received\n"); + _err("PANIC!!! Debug Monitor received\n"); PANIC(); return 0; } @@ -217,7 +217,7 @@ static int sam_errmonitor(int irq, FAR void *context) static int sam_reserved(int irq, FAR void *context) { (void)up_irq_save(); - err("PANIC!!! Reserved interrupt\n"); + _err("PANIC!!! Reserved interrupt\n"); PANIC(); return 0; } diff --git a/arch/arm/src/sam34/sam_rtt.c b/arch/arm/src/sam34/sam_rtt.c index e2972e00ba..385aa37d01 100644 --- a/arch/arm/src/sam34/sam_rtt.c +++ b/arch/arm/src/sam34/sam_rtt.c @@ -81,8 +81,8 @@ */ #ifdef CONFIG_DEBUG_RTT -# define rtterr llerr -# define rttinfo llinfo +# define rtterr _llerr +# define rttinfo _llinfo #else # define rtterr(x...) # define rttinfo(x...) @@ -214,7 +214,7 @@ static uint32_t sam34_getreg(uint32_t addr) { if (count == 4) { - llerr("...\n"); + _llerr("...\n"); } return val; @@ -231,7 +231,7 @@ static uint32_t sam34_getreg(uint32_t addr) { /* Yes.. then show how many times the value repeated */ - llerr("[repeats %d more times]\n", count-3); + _llerr("[repeats %d more times]\n", count-3); } /* Save the new address, value, and count */ @@ -243,7 +243,7 @@ static uint32_t sam34_getreg(uint32_t addr) /* Show the register value read */ - llerr("%08lx->%08lx\n", addr, val); + _llerr("%08lx->%08lx\n", addr, val); return val; } #endif @@ -261,7 +261,7 @@ static void sam34_putreg(uint32_t val, uint32_t addr) { /* Show the register value being written */ - llerr("%08lx<-%08lx\n", addr, val); + _llerr("%08lx<-%08lx\n", addr, val); /* Write the value */ diff --git a/arch/arm/src/sam34/sam_spi.c b/arch/arm/src/sam34/sam_spi.c index 0c01cb7dad..488a0d8d1e 100644 --- a/arch/arm/src/sam34/sam_spi.c +++ b/arch/arm/src/sam34/sam_spi.c @@ -420,7 +420,7 @@ static bool spi_checkreg(struct sam_spidev_s *spi, bool wr, uint32_t value, { /* Yes... show how many times we did it */ - llerr("...[Repeats %d times]...\n", spi->ntimes); + _llerr("...[Repeats %d times]...\n", spi->ntimes); } /* Save information about the new access */ @@ -454,7 +454,7 @@ static inline uint32_t spi_getreg(struct sam_spidev_s *spi, #ifdef CONFIG_SAM34_SPI_REGDEBUG if (spi_checkreg(spi, false, value, address)) { - llerr("%08x->%08x\n", address, value); + _llerr("%08x->%08x\n", address, value); } #endif @@ -477,7 +477,7 @@ static inline void spi_putreg(struct sam_spidev_s *spi, uint32_t value, #ifdef CONFIG_SAM34_SPI_REGDEBUG if (spi_checkreg(spi, true, value, address)) { - llerr("%08x<-%08x\n", address, value); + _llerr("%08x<-%08x\n", address, value); } #endif diff --git a/arch/arm/src/sam34/sam_tc.c b/arch/arm/src/sam34/sam_tc.c index 8feea0a727..26a73eff82 100644 --- a/arch/arm/src/sam34/sam_tc.c +++ b/arch/arm/src/sam34/sam_tc.c @@ -179,7 +179,7 @@ static uint32_t sam34_getreg(uint32_t addr) { if (count == 4) { - llerr("...\n"); + _llerr("...\n"); } return val; @@ -196,7 +196,7 @@ static uint32_t sam34_getreg(uint32_t addr) { /* Yes.. then show how many times the value repeated */ - llerr("[repeats %d more times]\n", count-3); + _llerr("[repeats %d more times]\n", count-3); } /* Save the new address, value, and count */ @@ -208,7 +208,7 @@ static uint32_t sam34_getreg(uint32_t addr) /* Show the register value read */ - llerr("%08lx->%08lx\n", addr, val); + _llerr("%08lx->%08lx\n", addr, val); return val; } #endif @@ -226,7 +226,7 @@ static void sam34_putreg(uint32_t val, uint32_t addr) { /* Show the register value being written */ - llerr("%08lx<-%08lx\n", addr, val); + _llerr("%08lx<-%08lx\n", addr, val); /* Write the value */ diff --git a/arch/arm/src/sam34/sam_twi.c b/arch/arm/src/sam34/sam_twi.c index a91d9af815..bc13070664 100644 --- a/arch/arm/src/sam34/sam_twi.c +++ b/arch/arm/src/sam34/sam_twi.c @@ -273,7 +273,7 @@ static bool twi_checkreg(struct twi_dev_s *priv, bool wr, uint32_t value, { /* Yes... show how many times we did it */ - llerr("...[Repeats %d times]...\n", priv->ntimes); + _llerr("...[Repeats %d times]...\n", priv->ntimes); } /* Save information about the new access */ @@ -305,7 +305,7 @@ static uint32_t twi_getabs(struct twi_dev_s *priv, uintptr_t address) if (twi_checkreg(priv, false, value, address)) { - llerr("%08x->%08x\n", address, value); + _llerr("%08x->%08x\n", address, value); } return value; @@ -326,7 +326,7 @@ static void twi_putabs(struct twi_dev_s *priv, uintptr_t address, { if (twi_checkreg(priv, true, value, address)) { - llerr("%08x<-%08x\n", address, value); + _llerr("%08x<-%08x\n", address, value); } putreg32(value, address); diff --git a/arch/arm/src/sam34/sam_udp.c b/arch/arm/src/sam34/sam_udp.c index 851b61c741..4615cd01b0 100644 --- a/arch/arm/src/sam34/sam_udp.c +++ b/arch/arm/src/sam34/sam_udp.c @@ -606,7 +606,7 @@ const struct trace_msg_t g_usb_trace_strings_intdecode[] = #ifdef CONFIG_SAM34_UDP_REGDEBUG static void sam_printreg(uintptr_t regaddr, uint32_t regval, bool iswrite) { - llinfo("%p%s%08x\n", regaddr, iswrite ? "<-" : "->", regval); + _llinfo("%p%s%08x\n", regaddr, iswrite ? "<-" : "->", regval); } #endif @@ -657,7 +657,7 @@ static void sam_checkreg(uintptr_t regaddr, uint32_t regval, bool iswrite) { /* No.. More than one. */ - llinfo("[repeats %d more times]\n", count); + _llinfo("[repeats %d more times]\n", count); } } @@ -737,15 +737,15 @@ static void sam_dumpep(struct sam_usbdev_s *priv, uint8_t epno) { /* Global Registers */ - llinfo("Global Registers:\n"); - llinfo(" FRMNUM: %08x\n", sam_getreg(SAM_UDP_FRMNUM)); - llinfo("GLBSTAT: %08x\n", sam_getreg(SAM_UDP_GLBSTAT)); - llinfo(" FADDR: %08x\n", sam_getreg(SAM_UDP_FADDR)); - llinfo(" IMR: %08x\n", sam_getreg(SAM_UDP_IMR)); - llinfo(" ISR: %08x\n", sam_getreg(SAM_UDP_ISR)); - llinfo(" RSTEP: %08x\n", sam_getreg(SAM_UDP_RSTEP)); - llinfo(" TXVC: %08x\n", sam_getreg(SAM_UDP_TXVC)); - llinfo(" CSR[%d]: %08x\n", epno, sam_getreg(SAM_UDPEP_CSR(epno))); + _llinfo("Global Registers:\n"); + _llinfo(" FRMNUM: %08x\n", sam_getreg(SAM_UDP_FRMNUM)); + _llinfo("GLBSTAT: %08x\n", sam_getreg(SAM_UDP_GLBSTAT)); + _llinfo(" FADDR: %08x\n", sam_getreg(SAM_UDP_FADDR)); + _llinfo(" IMR: %08x\n", sam_getreg(SAM_UDP_IMR)); + _llinfo(" ISR: %08x\n", sam_getreg(SAM_UDP_ISR)); + _llinfo(" RSTEP: %08x\n", sam_getreg(SAM_UDP_RSTEP)); + _llinfo(" TXVC: %08x\n", sam_getreg(SAM_UDP_TXVC)); + _llinfo(" CSR[%d]: %08x\n", epno, sam_getreg(SAM_UDPEP_CSR(epno))); } #endif diff --git a/arch/arm/src/sam34/sam_wdt.c b/arch/arm/src/sam34/sam_wdt.c index d54297f5ab..aa033f4e87 100644 --- a/arch/arm/src/sam34/sam_wdt.c +++ b/arch/arm/src/sam34/sam_wdt.c @@ -183,7 +183,7 @@ static uint32_t sam34_getreg(uint32_t addr) { if (count == 4) { - llerr("...\n"); + _llerr("...\n"); } return val; @@ -200,7 +200,7 @@ static uint32_t sam34_getreg(uint32_t addr) { /* Yes.. then show how many times the value repeated */ - llerr("[repeats %d more times]\n", count-3); + _llerr("[repeats %d more times]\n", count-3); } /* Save the new address, value, and count */ @@ -212,7 +212,7 @@ static uint32_t sam34_getreg(uint32_t addr) /* Show the register value read */ - llerr("%08x->%08x\n", addr, val); + _llerr("%08x->%08x\n", addr, val); return val; } #endif @@ -230,7 +230,7 @@ static void sam34_putreg(uint32_t val, uint32_t addr) { /* Show the register value being written */ - llerr("%08x<-%08x\n", addr, val); + _llerr("%08x<-%08x\n", addr, val); /* Write the value */ diff --git a/arch/arm/src/sama5/sam_adc.c b/arch/arm/src/sama5/sam_adc.c index 35bb4ea9fe..24099c0d92 100644 --- a/arch/arm/src/sama5/sam_adc.c +++ b/arch/arm/src/sama5/sam_adc.c @@ -544,7 +544,7 @@ static bool sam_adc_checkreg(struct sam_adc_s *priv, bool wr, { /* Yes... show how many times we did it */ - llerr("...[Repeats %d times]...\n", priv->ntimes); + _llerr("...[Repeats %d times]...\n", priv->ntimes); } /* Save information about the new access */ @@ -2187,7 +2187,7 @@ uint32_t sam_adc_getreg(struct sam_adc_s *priv, uintptr_t address) if (sam_adc_checkreg(priv, false, regval, address)) { - llerr("%08x->%08x\n", address, regval); + _llerr("%08x->%08x\n", address, regval); } return regval; @@ -2207,7 +2207,7 @@ void sam_adc_putreg(struct sam_adc_s *priv, uintptr_t address, uint32_t regval) { if (sam_adc_checkreg(priv, true, regval, address)) { - llerr("%08x<-%08x\n", address, regval); + _llerr("%08x<-%08x\n", address, regval); } putreg32(regval, address); diff --git a/arch/arm/src/sama5/sam_allocateheap.c b/arch/arm/src/sama5/sam_allocateheap.c index c666b09ce6..f772735bae 100644 --- a/arch/arm/src/sama5/sam_allocateheap.c +++ b/arch/arm/src/sama5/sam_allocateheap.c @@ -312,9 +312,9 @@ void up_addregion(void) } else { - llerr("ERROR: SDRAM memory not added to heap. CONFIG_MM_NREGIONS=%d\n", + _llerr("ERROR: SDRAM memory not added to heap. CONFIG_MM_NREGIONS=%d\n", CONFIG_MM_REGIONS); - llerr(" Increase the size of CONFIG_MM_NREGIONS\n"); + _llerr(" Increase the size of CONFIG_MM_NREGIONS\n"); } #endif @@ -331,9 +331,9 @@ void up_addregion(void) } else { - llerr("ERROR: CS0 memory not added to heap. CONFIG_MM_NREGIONS=%d\n", + _llerr("ERROR: CS0 memory not added to heap. CONFIG_MM_NREGIONS=%d\n", CONFIG_MM_REGIONS); - llerr(" Increase the size of CONFIG_MM_NREGIONS\n"); + _llerr(" Increase the size of CONFIG_MM_NREGIONS\n"); } #endif @@ -350,9 +350,9 @@ void up_addregion(void) } else { - llerr("ERROR: CS1 memory not added to heap. CONFIG_MM_NREGIONS=%d\n", + _llerr("ERROR: CS1 memory not added to heap. CONFIG_MM_NREGIONS=%d\n", CONFIG_MM_REGIONS); - llerr(" Increase the size of CONFIG_MM_NREGIONS\n"); + _llerr(" Increase the size of CONFIG_MM_NREGIONS\n"); } #endif @@ -369,9 +369,9 @@ void up_addregion(void) } else { - llerr("ERROR: CS2 memory not added to heap. CONFIG_MM_NREGIONS=%d\n", + _llerr("ERROR: CS2 memory not added to heap. CONFIG_MM_NREGIONS=%d\n", CONFIG_MM_REGIONS); - llerr(" Increase the size of CONFIG_MM_NREGIONS\n"); + _llerr(" Increase the size of CONFIG_MM_NREGIONS\n"); } #endif @@ -388,9 +388,9 @@ void up_addregion(void) } else { - llerr("ERROR: CS3 memory not added to heap. CONFIG_MM_NREGIONS=%d\n", + _llerr("ERROR: CS3 memory not added to heap. CONFIG_MM_NREGIONS=%d\n", CONFIG_MM_REGIONS); - llerr(" Increase the size of CONFIG_MM_NREGIONS\n"); + _llerr(" Increase the size of CONFIG_MM_NREGIONS\n"); } #endif @@ -398,9 +398,9 @@ void up_addregion(void) if (nregions > 0) { - llerr("ERROR: Not all regions added to heap: %d added, but CONFIG_MM_NREGIONS=%d\n", + _llerr("ERROR: Not all regions added to heap: %d added, but CONFIG_MM_NREGIONS=%d\n", CONFIG_MM_REGIONS - nregions, CONFIG_MM_REGIONS); - llerr(" Decrease the size of CONFIG_MM_NREGIONS\n"); + _llerr(" Decrease the size of CONFIG_MM_NREGIONS\n"); } } #endif diff --git a/arch/arm/src/sama5/sam_can.c b/arch/arm/src/sama5/sam_can.c index c09c4fd610..bb580c9e14 100644 --- a/arch/arm/src/sama5/sam_can.c +++ b/arch/arm/src/sama5/sam_can.c @@ -371,7 +371,7 @@ static uint32_t can_getreg(FAR struct sam_can_s *priv, int offset) { if (priv->count == 4) { - llerr("...\n"); + _llerr("...\n"); } return regval; @@ -388,7 +388,7 @@ static uint32_t can_getreg(FAR struct sam_can_s *priv, int offset) { /* Yes.. then show how many times the value repeated */ - llerr("[repeats %d more times]\n", priv->count - 3); + _llerr("[repeats %d more times]\n", priv->count - 3); } /* Save the new address, value, and count */ @@ -400,7 +400,7 @@ static uint32_t can_getreg(FAR struct sam_can_s *priv, int offset) /* Show the register value read */ - llerr("%08x->%08x\n", regaddr, regval); + _llerr("%08x->%08x\n", regaddr, regval); return regval; } @@ -437,7 +437,7 @@ static void can_putreg(FAR struct sam_can_s *priv, int offset, uint32_t regval) /* Show the register value being written */ - llerr("%08x<-%08x\n", regaddr, regval); + _llerr("%08x<-%08x\n", regaddr, regval); /* Write the value */ @@ -483,17 +483,17 @@ static void can_dumpctrlregs(FAR struct sam_can_s *priv, FAR const char *msg) /* CAN control and status registers */ - llerr(" MR: %08x IMR: %08x SR: %08x\n", + _llerr(" MR: %08x IMR: %08x SR: %08x\n", getreg32(config->base + SAM_CAN_MR_OFFSET), getreg32(config->base + SAM_CAN_IMR_OFFSET), getreg32(config->base + SAM_CAN_SR_OFFSET)); - llerr(" BR: %08x TIM: %08x TIMESTP: %08x\n", + _llerr(" BR: %08x TIM: %08x TIMESTP: %08x\n", getreg32(config->base + SAM_CAN_BR_OFFSET), getreg32(config->base + SAM_CAN_TIM_OFFSET), getreg32(config->base + SAM_CAN_TIMESTP_OFFSET)); - llerr(" ECR: %08x WPMR: %08x WPSR: %08x\n", + _llerr(" ECR: %08x WPMR: %08x WPSR: %08x\n", getreg32(config->base + SAM_CAN_ECR_OFFSET), getreg32(config->base + SAM_CAN_TCR_OFFSET), getreg32(config->base + SAM_CAN_ACR_OFFSET)); @@ -533,17 +533,17 @@ static void can_dumpmbregs(FAR struct sam_can_s *priv, FAR const char *msg) for (i = 0; i < SAM_CAN_NMAILBOXES; i++) { mbbase = config->base + SAM_CAN_MBn_OFFSET(i); - llerr(" MB%d:\n", i); + _llerr(" MB%d:\n", i); /* CAN mailbox registers */ - llerr(" MMR: %08x MAM: %08x MID: %08x MFID: %08x\n", + _llerr(" MMR: %08x MAM: %08x MID: %08x MFID: %08x\n", getreg32(mbbase + SAM_CAN_MMR_OFFSET), getreg32(mbbase + SAM_CAN_MAM_OFFSET), getreg32(mbbase + SAM_CAN_MID_OFFSET), getreg32(mbbase + SAM_CAN_MFID_OFFSET)); - llerr(" MSR: %08x MDL: %08x MDH: %08x\n", + _llerr(" MSR: %08x MDL: %08x MDH: %08x\n", getreg32(mbbase + SAM_CAN_MSR_OFFSET), getreg32(mbbase + SAM_CAN_MDL_OFFSET), getreg32(mbbase + SAM_CAN_MDH_OFFSET)); diff --git a/arch/arm/src/sama5/sam_ehci.c b/arch/arm/src/sama5/sam_ehci.c index 731290b6ab..b39d925c8b 100644 --- a/arch/arm/src/sama5/sam_ehci.c +++ b/arch/arm/src/sama5/sam_ehci.c @@ -628,7 +628,7 @@ static uint32_t sam_swap32(uint32_t value) static void sam_printreg(volatile uint32_t *regaddr, uint32_t regval, bool iswrite) { - llerr("%08x%s%08x\n", (uintptr_t)regaddr, iswrite ? "<-" : "->", regval); + _llerr("%08x%s%08x\n", (uintptr_t)regaddr, iswrite ? "<-" : "->", regval); } #endif @@ -679,7 +679,7 @@ static void sam_checkreg(volatile uint32_t *regaddr, uint32_t regval, bool iswri { /* No.. More than one. */ - llerr("[repeats %d more times]\n", count); + _llerr("[repeats %d more times]\n", count); } } diff --git a/arch/arm/src/sama5/sam_emaca.c b/arch/arm/src/sama5/sam_emaca.c index 86d0b5ffa1..04267d09a8 100644 --- a/arch/arm/src/sama5/sam_emaca.c +++ b/arch/arm/src/sama5/sam_emaca.c @@ -461,7 +461,7 @@ static bool sam_checkreg(struct sam_emac_s *priv, bool wr, uint32_t regval, { /* Yes... show how many times we did it */ - llerr("...[Repeats %d times]...\n", priv->ntimes); + _llerr("...[Repeats %d times]...\n", priv->ntimes); } /* Save information about the new access */ @@ -493,7 +493,7 @@ static uint32_t sam_getreg(struct sam_emac_s *priv, uintptr_t address) if (sam_checkreg(priv, false, regval, address)) { - llerr("%08x->%08x\n", address, regval); + _llerr("%08x->%08x\n", address, regval); } return regval; @@ -514,7 +514,7 @@ static void sam_putreg(struct sam_emac_s *priv, uintptr_t address, { if (sam_checkreg(priv, true, regval, address)) { - llerr("%08x<-%08x\n", address, regval); + _llerr("%08x<-%08x\n", address, regval); } putreg32(regval, address); diff --git a/arch/arm/src/sama5/sam_emacb.c b/arch/arm/src/sama5/sam_emacb.c index f36722abb8..66155406e9 100644 --- a/arch/arm/src/sama5/sam_emacb.c +++ b/arch/arm/src/sama5/sam_emacb.c @@ -820,7 +820,7 @@ static bool sam_checkreg(struct sam_emac_s *priv, bool wr, uint32_t regval, { /* Yes... show how many times we did it */ - llerr("...[Repeats %d times]...\n", priv->ntimes); + _llerr("...[Repeats %d times]...\n", priv->ntimes); } /* Save information about the new access */ @@ -853,7 +853,7 @@ static uint32_t sam_getreg(struct sam_emac_s *priv, uint16_t offset) #ifdef CONFIG_SAMA5_EMACB_REGDEBUG if (sam_checkreg(priv, false, regval, regaddr)) { - llerr("%08x->%08x\n", regaddr, regval); + _llerr("%08x->%08x\n", regaddr, regval); } #endif @@ -877,7 +877,7 @@ static void sam_putreg(struct sam_emac_s *priv, uint16_t offset, #ifdef CONFIG_SAMA5_EMACB_REGDEBUG if (sam_checkreg(priv, true, regval, regaddr)) { - llerr("%08x<-%08x\n", regaddr, regval); + _llerr("%08x<-%08x\n", regaddr, regval); } #endif diff --git a/arch/arm/src/sama5/sam_gmac.c b/arch/arm/src/sama5/sam_gmac.c index 078841fbb1..3bf136c310 100644 --- a/arch/arm/src/sama5/sam_gmac.c +++ b/arch/arm/src/sama5/sam_gmac.c @@ -392,7 +392,7 @@ static bool sam_checkreg(struct sam_gmac_s *priv, bool wr, uint32_t regval, { /* Yes... show how many times we did it */ - llerr("...[Repeats %d times]...\n", priv->ntimes); + _llerr("...[Repeats %d times]...\n", priv->ntimes); } /* Save information about the new access */ @@ -424,7 +424,7 @@ static uint32_t sam_getreg(struct sam_gmac_s *priv, uintptr_t address) if (sam_checkreg(priv, false, regval, address)) { - llerr("%08x->%08x\n", address, regval); + _llerr("%08x->%08x\n", address, regval); } return regval; @@ -445,7 +445,7 @@ static void sam_putreg(struct sam_gmac_s *priv, uintptr_t address, { if (sam_checkreg(priv, true, regval, address)) { - llerr("%08x<-%08x\n", address, regval); + _llerr("%08x<-%08x\n", address, regval); } putreg32(regval, address); diff --git a/arch/arm/src/sama5/sam_hsmci.c b/arch/arm/src/sama5/sam_hsmci.c index 5bb44bec4d..026424fae7 100644 --- a/arch/arm/src/sama5/sam_hsmci.c +++ b/arch/arm/src/sama5/sam_hsmci.c @@ -725,7 +725,7 @@ static bool sam_checkreg(struct sam_dev_s *priv, bool wr, uint32_t value, { /* Yes... show how many times we did it */ - llerr("...[Repeats %d times]...\n", priv->ntimes); + _llerr("...[Repeats %d times]...\n", priv->ntimes); } /* Save information about the new access */ @@ -758,7 +758,7 @@ static inline uint32_t sam_getreg(struct sam_dev_s *priv, unsigned int offset) #ifdef CONFIG_SAMA5_HSMCI_REGDEBUG if (sam_checkreg(priv, false, value, address)) { - llerr("%08x->%08x\n", address, value); + _llerr("%08x->%08x\n", address, value); } #endif @@ -781,7 +781,7 @@ static inline void sam_putreg(struct sam_dev_s *priv, uint32_t value, #ifdef CONFIG_SAMA5_HSMCI_REGDEBUG if (sam_checkreg(priv, true, value, address)) { - llerr("%08x<-%08x\n", address, value); + _llerr("%08x<-%08x\n", address, value); } #endif diff --git a/arch/arm/src/sama5/sam_lcd.c b/arch/arm/src/sama5/sam_lcd.c index b1a0fd9760..eef9767adf 100644 --- a/arch/arm/src/sama5/sam_lcd.c +++ b/arch/arm/src/sama5/sam_lcd.c @@ -1021,7 +1021,7 @@ static bool sam_checkreg(bool wr, uint32_t regval, uintptr_t address) { /* Yes... show how many times we did it */ - llerr("...[Repeats %d times]...\n", g_lcdc.ntimes); + _llerr("...[Repeats %d times]...\n", g_lcdc.ntimes); } /* Save information about the new access */ @@ -1053,7 +1053,7 @@ static uint32_t sam_getreg(uintptr_t address) if (sam_checkreg(false, regval, address)) { - llerr("%08x->%08x\n", address, regval); + _llerr("%08x->%08x\n", address, regval); } return regval; @@ -1073,7 +1073,7 @@ static void sam_putreg(uintptr_t address, uint32_t regval) { if (sam_checkreg(true, regval, address)) { - llerr("%08x<-%08x\n", address, regval); + _llerr("%08x<-%08x\n", address, regval); } putreg32(regval, address); diff --git a/arch/arm/src/sama5/sam_memories.c b/arch/arm/src/sama5/sam_memories.c index d6b18aa792..6588309b88 100644 --- a/arch/arm/src/sama5/sam_memories.c +++ b/arch/arm/src/sama5/sam_memories.c @@ -766,7 +766,7 @@ uintptr_t sam_physregaddr(uintptr_t virtregaddr) * address */ - err("Bad virtual address: %08lx\n", virtregaddr); + _err("Bad virtual address: %08lx\n", virtregaddr); DEBUGPANIC(); return virtregaddr; } @@ -925,7 +925,7 @@ uintptr_t sam_physramaddr(uintptr_t virtramaddr) if (virtramaddr != 0) { - err("Bad virtual address: %08lx\n", virtramaddr); + _err("Bad virtual address: %08lx\n", virtramaddr); DEBUGPANIC(); } @@ -1058,7 +1058,7 @@ uintptr_t sam_virtramaddr(uintptr_t physramaddr) if (physramaddr != 0) { - err("Bad physical address: %08lx\n|", physramaddr); + _err("Bad physical address: %08lx\n|", physramaddr); DEBUGPANIC(); } diff --git a/arch/arm/src/sama5/sam_nand.c b/arch/arm/src/sama5/sam_nand.c index 425120b8d3..6cb56fea97 100644 --- a/arch/arm/src/sama5/sam_nand.c +++ b/arch/arm/src/sama5/sam_nand.c @@ -1163,7 +1163,7 @@ static void nand_dma_sampleinit(struct sam_nandcs_s *priv) #ifdef CONFIG_SAMA5_NAND_DMADEBUG static void nand_dma_sampledone(struct sam_nandcs_s *priv, int result) { - llerr("result: %d\n", result); + _llerr("result: %d\n", result); /* Sample the final registers */ @@ -3088,7 +3088,7 @@ bool nand_checkreg(bool wr, uintptr_t regaddr, uint32_t regval) { /* Yes... show how many times we did it */ - llerr("...[Repeats %d times]...\n", g_nand.ntimes); + _llerr("...[Repeats %d times]...\n", g_nand.ntimes); } /* Save information about the new access */ diff --git a/arch/arm/src/sama5/sam_nand.h b/arch/arm/src/sama5/sam_nand.h index 352b45b491..81e6cb8003 100644 --- a/arch/arm/src/sama5/sam_nand.h +++ b/arch/arm/src/sama5/sam_nand.h @@ -518,7 +518,7 @@ static inline uint32_t nand_getreg(uintptr_t regaddr) #ifdef CONFIG_SAMA5_NAND_REGDEBUG if (nand_checkreg(false, regaddr, regval)) { - llerr("%08x->%08x\n", regaddr, regval); + _llerr("%08x->%08x\n", regaddr, regval); } #endif @@ -538,7 +538,7 @@ static inline void nand_putreg(uintptr_t regaddr, uint32_t regval) #ifdef CONFIG_SAMA5_NAND_REGDEBUG if (nand_checkreg(true, regaddr, regval)) { - llerr("%08x<-%08x\n", regaddr, regval); + _llerr("%08x<-%08x\n", regaddr, regval); } #endif diff --git a/arch/arm/src/sama5/sam_ohci.c b/arch/arm/src/sama5/sam_ohci.c index e20a1adb24..76899223c6 100644 --- a/arch/arm/src/sama5/sam_ohci.c +++ b/arch/arm/src/sama5/sam_ohci.c @@ -524,7 +524,7 @@ static uint8_t g_bufalloc[SAM_BUFALLOC] #ifdef CONFIG_SAMA5_OHCI_REGDEBUG static void sam_printreg(uint32_t addr, uint32_t val, bool iswrite) { - llerr("%08x%s%08x\n", addr, iswrite ? "<-" : "->", val); + _llerr("%08x%s%08x\n", addr, iswrite ? "<-" : "->", val); } #endif @@ -574,7 +574,7 @@ static void sam_checkreg(uint32_t addr, uint32_t val, bool iswrite) { /* No.. More than one. */ - llerr("[repeats %d more times]\n", count); + _llerr("[repeats %d more times]\n", count); } } diff --git a/arch/arm/src/sama5/sam_pck.c b/arch/arm/src/sama5/sam_pck.c index 9b7e406a38..dc96ab678c 100644 --- a/arch/arm/src/sama5/sam_pck.c +++ b/arch/arm/src/sama5/sam_pck.c @@ -151,7 +151,7 @@ uint32_t sam_pck_configure(enum pckid_e pckid, enum pckid_clksrc_e clksrc, break; default: - err("ERROR: Unknown clock source\n"); + _err("ERROR: Unknown clock source\n"); return 0; } diff --git a/arch/arm/src/sama5/sam_pwm.c b/arch/arm/src/sama5/sam_pwm.c index 6fe331db44..4aac3affa8 100644 --- a/arch/arm/src/sama5/sam_pwm.c +++ b/arch/arm/src/sama5/sam_pwm.c @@ -689,7 +689,7 @@ static bool pwm_checkreg(FAR struct sam_pwm_s *pwm, bool wr, uint32_t regval, { /* Yes... show how many times we did it */ - llerr("...[Repeats %d times]...\n", pwm->count); + _llerr("...[Repeats %d times]...\n", pwm->count); } /* Save information about the new access */ @@ -733,7 +733,7 @@ static uint32_t pwm_getreg(struct sam_pwm_chan_s *chan, int offset) #ifdef CONFIG_SAMA5_PWM_REGDEBUG if (pwm_checkreg(&g_pwm, false, regval, regaddr)) { - llerr("%08x->%08x\n", regaddr, regval); + _llerr("%08x->%08x\n", regaddr, regval); } #endif @@ -750,7 +750,7 @@ static uint32_t pwm_getreg(struct sam_pwm_chan_s *chan, int offset) #ifdef CONFIG_SAMA5_PWM_REGDEBUG if (pwm_checkreg(pwm, false, regval, regaddr)) { - llerr("%08x->%08x\n", regaddr, regval); + _llerr("%08x->%08x\n", regaddr, regval); } #endif @@ -789,7 +789,7 @@ static uint32_t pwm_chan_getreg(struct sam_pwm_chan_s *chan, int offset) if (pwm_checkreg(chan->pwm, false, regval, regaddr)) #endif { - llerr("%08x->%08x\n", regaddr, regval); + _llerr("%08x->%08x\n", regaddr, regval); } #endif @@ -820,7 +820,7 @@ static void pwm_putreg(struct sam_pwm_chan_s *chan, int offset, #ifdef CONFIG_SAMA5_PWM_REGDEBUG if (pwm_checkreg(&g_pwm, true, regval, regaddr)) { - llerr("%08x<-%08x\n", regaddr, regval); + _llerr("%08x<-%08x\n", regaddr, regval); } #endif @@ -833,7 +833,7 @@ static void pwm_putreg(struct sam_pwm_chan_s *chan, int offset, #ifdef CONFIG_SAMA5_PWM_REGDEBUG if (pwm_checkreg(pwm, true, regval, regaddr)) { - llerr("%08x<-%08x\n", regaddr, regval); + _llerr("%08x<-%08x\n", regaddr, regval); } #endif @@ -869,7 +869,7 @@ static void pwm_chan_putreg(struct sam_pwm_chan_s *chan, int offset, if (pwm_checkreg(chan->pwm, true, regval, regaddr)) #endif { - llerr("%08x<-%08x\n", regaddr, regval); + _llerr("%08x<-%08x\n", regaddr, regval); } #endif diff --git a/arch/arm/src/sama5/sam_spi.c b/arch/arm/src/sama5/sam_spi.c index 0bc887534a..33cd3cb93e 100644 --- a/arch/arm/src/sama5/sam_spi.c +++ b/arch/arm/src/sama5/sam_spi.c @@ -409,7 +409,7 @@ static bool spi_checkreg(struct sam_spidev_s *spi, bool wr, uint32_t value, { /* Yes... show how many times we did it */ - llerr("...[Repeats %d times]...\n", spi->ntimes); + _llerr("...[Repeats %d times]...\n", spi->ntimes); } /* Save information about the new access */ @@ -443,7 +443,7 @@ static inline uint32_t spi_getreg(struct sam_spidev_s *spi, #ifdef CONFIG_SAMA5_SPI_REGDEBUG if (spi_checkreg(spi, false, value, address)) { - llerr("%08x->%08x\n", address, value); + _llerr("%08x->%08x\n", address, value); } #endif @@ -466,7 +466,7 @@ static inline void spi_putreg(struct sam_spidev_s *spi, uint32_t value, #ifdef CONFIG_SAMA5_SPI_REGDEBUG if (spi_checkreg(spi, true, value, address)) { - llerr("%08x<-%08x\n", address, value); + _llerr("%08x<-%08x\n", address, value); } #endif diff --git a/arch/arm/src/sama5/sam_ssc.c b/arch/arm/src/sama5/sam_ssc.c index d33b1588ff..46c564b66e 100644 --- a/arch/arm/src/sama5/sam_ssc.c +++ b/arch/arm/src/sama5/sam_ssc.c @@ -703,7 +703,7 @@ static bool ssc_checkreg(struct sam_ssc_s *priv, bool wr, uint32_t regval, { /* Yes... show how many times we did it */ - llerr("...[Repeats %d times]...\n", priv->count); + _llerr("...[Repeats %d times]...\n", priv->count); } /* Save information about the new access */ @@ -737,7 +737,7 @@ static inline uint32_t ssc_getreg(struct sam_ssc_s *priv, #ifdef CONFIG_SAMA5_SSC_REGDEBUG if (ssc_checkreg(priv, false, regval, regaddr)) { - llerr("%08x->%08x\n", regaddr, regval); + _llerr("%08x->%08x\n", regaddr, regval); } #endif @@ -760,7 +760,7 @@ static inline void ssc_putreg(struct sam_ssc_s *priv, unsigned int offset, #ifdef CONFIG_SAMA5_SSC_REGDEBUG if (ssc_checkreg(priv, true, regval, regaddr)) { - llerr("%08x<-%08x\n", regaddr, regval); + _llerr("%08x<-%08x\n", regaddr, regval); } #endif @@ -1090,7 +1090,7 @@ static void ssc_dma_sampleinit(struct sam_ssc_s *priv, #if defined(CONFIG_SAMA5_SSC_DMADEBUG) && defined(SSC_HAVE_RX) static void ssc_rxdma_sampledone(struct sam_ssc_s *priv, int result) { - llerr("result: %d\n", result); + _llerr("result: %d\n", result); /* Sample the final registers */ @@ -1155,7 +1155,7 @@ static void ssc_rxdma_sampledone(struct sam_ssc_s *priv, int result) #if defined(CONFIG_SAMA5_SSC_DMADEBUG) && defined(SSC_HAVE_TX) static void ssc_txdma_sampledone(struct sam_ssc_s *priv, int result) { - llerr("result: %d\n", result); + _llerr("result: %d\n", result); /* Sample the final registers */ diff --git a/arch/arm/src/sama5/sam_tc.c b/arch/arm/src/sama5/sam_tc.c index 5d51f82047..9ea38a333d 100644 --- a/arch/arm/src/sama5/sam_tc.c +++ b/arch/arm/src/sama5/sam_tc.c @@ -501,20 +501,20 @@ static void sam_regdump(struct sam_chan_s *chan, const char *msg) uintptr_t base; base = tc->base; - llerr("TC%d [%08x]: %s\n", tc->tc, (int)base, msg); - llerr(" BMR: %08x QIMR: %08x QISR: %08x WPMR: %08x\n", + _llerr("TC%d [%08x]: %s\n", tc->tc, (int)base, msg); + _llerr(" BMR: %08x QIMR: %08x QISR: %08x WPMR: %08x\n", getreg32(base+SAM_TC_BMR_OFFSET), getreg32(base+SAM_TC_QIMR_OFFSET), getreg32(base+SAM_TC_QISR_OFFSET), getreg32(base+SAM_TC_WPMR_OFFSET)); base = chan->base; - llerr("TC%d Channel %d [%08x]: %s\n", tc->tc, chan->chan, (int)base, msg); - llerr(" CMR: %08x SSMR: %08x RAB: %08x CV: %08x\n", + _llerr("TC%d Channel %d [%08x]: %s\n", tc->tc, chan->chan, (int)base, msg); + _llerr(" CMR: %08x SSMR: %08x RAB: %08x CV: %08x\n", getreg32(base+SAM_TC_CMR_OFFSET), getreg32(base+SAM_TC_SMMR_OFFSET), getreg32(base+SAM_TC_RAB_OFFSET), getreg32(base+SAM_TC_CV_OFFSET)); - llerr(" RA: %08x RB: %08x RC: %08x SR: %08x\n", + _llerr(" RA: %08x RB: %08x RC: %08x SR: %08x\n", getreg32(base+SAM_TC_RA_OFFSET), getreg32(base+SAM_TC_RB_OFFSET), getreg32(base+SAM_TC_RC_OFFSET), getreg32(base+SAM_TC_SR_OFFSET)); - llerr(" IMR: %08x\n", + _llerr(" IMR: %08x\n", getreg32(base+SAM_TC_IMR_OFFSET)); } #endif @@ -558,7 +558,7 @@ static bool sam_checkreg(struct sam_tc_s *tc, bool wr, uint32_t regaddr, { /* Yes... show how many times we did it */ - llerr("...[Repeats %d times]...\n", tc->ntimes); + _llerr("...[Repeats %d times]...\n", tc->ntimes); } /* Save information about the new access */ @@ -593,7 +593,7 @@ static inline uint32_t sam_tc_getreg(struct sam_chan_s *chan, #ifdef CONFIG_SAMA5_TC_REGDEBUG if (sam_checkreg(tc, false, regaddr, regval)) { - llerr("%08x->%08x\n", regaddr, regval); + _llerr("%08x->%08x\n", regaddr, regval); } #endif @@ -617,7 +617,7 @@ static inline void sam_tc_putreg(struct sam_chan_s *chan, uint32_t regval, #ifdef CONFIG_SAMA5_TC_REGDEBUG if (sam_checkreg(tc, true, regaddr, regval)) { - llerr("%08x<-%08x\n", regaddr, regval); + _llerr("%08x<-%08x\n", regaddr, regval); } #endif @@ -641,7 +641,7 @@ static inline uint32_t sam_chan_getreg(struct sam_chan_s *chan, #ifdef CONFIG_SAMA5_TC_REGDEBUG if (sam_checkreg(chan->tc, false, regaddr, regval)) { - llerr("%08x->%08x\n", regaddr, regval); + _llerr("%08x->%08x\n", regaddr, regval); } #endif @@ -664,7 +664,7 @@ static inline void sam_chan_putreg(struct sam_chan_s *chan, unsigned int offset, #ifdef CONFIG_SAMA5_TC_REGDEBUG if (sam_checkreg(chan->tc, true, regaddr, regval)) { - llerr("%08x<-%08x\n", regaddr, regval); + _llerr("%08x<-%08x\n", regaddr, regval); } #endif diff --git a/arch/arm/src/sama5/sam_twi.c b/arch/arm/src/sama5/sam_twi.c index aae56067bb..095fb7e895 100644 --- a/arch/arm/src/sama5/sam_twi.c +++ b/arch/arm/src/sama5/sam_twi.c @@ -369,7 +369,7 @@ static bool twi_checkreg(struct twi_dev_s *priv, bool wr, uint32_t value, { /* Yes... show how many times we did it */ - llerr("...[Repeats %d times]...\n", priv->ntimes); + _llerr("...[Repeats %d times]...\n", priv->ntimes); } /* Save information about the new access */ @@ -401,7 +401,7 @@ static uint32_t twi_getabs(struct twi_dev_s *priv, uintptr_t address) if (twi_checkreg(priv, false, value, address)) { - llerr("%08x->%08x\n", address, value); + _llerr("%08x->%08x\n", address, value); } return value; @@ -422,7 +422,7 @@ static void twi_putabs(struct twi_dev_s *priv, uintptr_t address, { if (twi_checkreg(priv, true, value, address)) { - llerr("%08x<-%08x\n", address, value); + _llerr("%08x<-%08x\n", address, value); } putreg32(value, address); diff --git a/arch/arm/src/sama5/sam_udphs.c b/arch/arm/src/sama5/sam_udphs.c index 00f85e6381..a5dba4368d 100644 --- a/arch/arm/src/sama5/sam_udphs.c +++ b/arch/arm/src/sama5/sam_udphs.c @@ -671,7 +671,7 @@ const struct trace_msg_t g_usb_trace_strings_intdecode[] = #ifdef CONFIG_SAMA5_UDPHS_REGDEBUG static void sam_printreg(uintptr_t regaddr, uint32_t regval, bool iswrite) { - llerr("%p%s%08x\n", regaddr, iswrite ? "<-" : "->", regval); + _llerr("%p%s%08x\n", regaddr, iswrite ? "<-" : "->", regval); } #endif @@ -722,7 +722,7 @@ static void sam_checkreg(uintptr_t regaddr, uint32_t regval, bool iswrite) { /* No.. More than one. */ - llerr("[repeats %d more times]\n", count); + _llerr("[repeats %d more times]\n", count); } } @@ -802,31 +802,31 @@ static void sam_dumpep(struct sam_usbdev_s *priv, int epno) { /* Global Registers */ - llerr("Global Register:\n"); - llerr(" CTRL: %04x\n", sam_getreg(SAM_UDPHS_CTRL)); - llerr(" FNUM: %04x\n", sam_getreg(SAM_UDPHS_FNUM)); - llerr(" IEN: %04x\n", sam_getreg(SAM_UDPHS_IEN)); - llerr(" INSTA: %04x\n", sam_getreg(SAM_UDPHS_INTSTA)); - llerr(" TST: %04x\n", sam_getreg(SAM_UDPHS_TST)); + _llerr("Global Register:\n"); + _llerr(" CTRL: %04x\n", sam_getreg(SAM_UDPHS_CTRL)); + _llerr(" FNUM: %04x\n", sam_getreg(SAM_UDPHS_FNUM)); + _llerr(" IEN: %04x\n", sam_getreg(SAM_UDPHS_IEN)); + _llerr(" INSTA: %04x\n", sam_getreg(SAM_UDPHS_INTSTA)); + _llerr(" TST: %04x\n", sam_getreg(SAM_UDPHS_TST)); /* Endpoint registers */ - llerr("Endpoint %d Register:\n", epno); - llerr(" CFG: %04x\n", sam_getreg(SAM_UDPHS_EPTCFG(epno))); - llerr(" CTL: %04x\n", sam_getreg(SAM_UDPHS_EPTCTL(epno))); - llerr(" STA: %04x\n", sam_getreg(SAM_UDPHS_EPTSTA(epno))); + _llerr("Endpoint %d Register:\n", epno); + _llerr(" CFG: %04x\n", sam_getreg(SAM_UDPHS_EPTCFG(epno))); + _llerr(" CTL: %04x\n", sam_getreg(SAM_UDPHS_EPTCTL(epno))); + _llerr(" STA: %04x\n", sam_getreg(SAM_UDPHS_EPTSTA(epno))); - llerr("DMA %d Register:\n", epno); + _llerr("DMA %d Register:\n", epno); if ((SAM_EPSET_DMA & SAM_EP_BIT(epno)) != 0) { - llerr(" NXTDSC: %04x\n", sam_getreg(SAM_UDPHS_DMANXTDSC(epno))); - llerr(" ADDRESS: %04x\n", sam_getreg(SAM_UDPHS_DMAADDRESS(epno))); - llerr(" CONTROL: %04x\n", sam_getreg(SAM_UDPHS_DMACONTROL(epno))); - llerr(" STATUS: %04x\n", sam_getreg(SAM_UDPHS_DMASTATUS(epno))); + _llerr(" NXTDSC: %04x\n", sam_getreg(SAM_UDPHS_DMANXTDSC(epno))); + _llerr(" ADDRESS: %04x\n", sam_getreg(SAM_UDPHS_DMAADDRESS(epno))); + _llerr(" CONTROL: %04x\n", sam_getreg(SAM_UDPHS_DMACONTROL(epno))); + _llerr(" STATUS: %04x\n", sam_getreg(SAM_UDPHS_DMASTATUS(epno))); } else { - llerr(" None\n"); + _llerr(" None\n"); } } #endif diff --git a/arch/arm/src/sama5/sam_wdt.c b/arch/arm/src/sama5/sam_wdt.c index be77357e97..aa16905888 100644 --- a/arch/arm/src/sama5/sam_wdt.c +++ b/arch/arm/src/sama5/sam_wdt.c @@ -185,7 +185,7 @@ static uint32_t sam_getreg(uintptr_t regaddr) { if (count == 4) { - llerr("...\n"); + _llerr("...\n"); } return regval; @@ -202,7 +202,7 @@ static uint32_t sam_getreg(uintptr_t regaddr) { /* Yes.. then show how many times the value repeated */ - llerr("[repeats %d more times]\n", count-3); + _llerr("[repeats %d more times]\n", count-3); } /* Save the new address, value, and count */ @@ -214,7 +214,7 @@ static uint32_t sam_getreg(uintptr_t regaddr) /* Show the register value read */ - llerr("%08x->%048\n", regaddr, regval); + _llerr("%08x->%048\n", regaddr, regval); return regval; } #endif @@ -232,7 +232,7 @@ static void sam_putreg(uint32_t regval, uintptr_t regaddr) { /* Show the register value being written */ - llerr("%08x<-%08x\n", regaddr, regval); + _llerr("%08x<-%08x\n", regaddr, regval); /* Write the value */ diff --git a/arch/arm/src/samdl/sam_idle.c b/arch/arm/src/samdl/sam_idle.c index b54d8d3a7d..a6fb024527 100644 --- a/arch/arm/src/samdl/sam_idle.c +++ b/arch/arm/src/samdl/sam_idle.c @@ -99,7 +99,7 @@ static void up_idlepm(void) /* Perform board-specific, state-dependent logic here */ - llinfo("newstate= %d oldstate=%d\n", newstate, oldstate); + _llinfo("newstate= %d oldstate=%d\n", newstate, oldstate); /* Then force the global state change */ diff --git a/arch/arm/src/samdl/sam_irq.c b/arch/arm/src/samdl/sam_irq.c index 0def4718bf..ea20c689bf 100644 --- a/arch/arm/src/samdl/sam_irq.c +++ b/arch/arm/src/samdl/sam_irq.c @@ -97,7 +97,7 @@ volatile uint32_t *g_current_regs[1]; static int sam_nmi(int irq, FAR void *context) { (void)up_irq_save(); - err("PANIC!!! NMI received\n"); + _err("PANIC!!! NMI received\n"); PANIC(); return 0; } @@ -105,7 +105,7 @@ static int sam_nmi(int irq, FAR void *context) static int sam_pendsv(int irq, FAR void *context) { (void)up_irq_save(); - err("PANIC!!! PendSV received\n"); + _err("PANIC!!! PendSV received\n"); PANIC(); return 0; } @@ -113,7 +113,7 @@ static int sam_pendsv(int irq, FAR void *context) static int sam_reserved(int irq, FAR void *context) { (void)up_irq_save(); - err("PANIC!!! Reserved interrupt\n"); + _err("PANIC!!! Reserved interrupt\n"); PANIC(); return 0; } diff --git a/arch/arm/src/samdl/sam_port.c b/arch/arm/src/samdl/sam_port.c index 58d0550df3..1b4cd115fb 100644 --- a/arch/arm/src/samdl/sam_port.c +++ b/arch/arm/src/samdl/sam_port.c @@ -538,16 +538,16 @@ int sam_dumpport(uint32_t pinset, const char *msg) /* The following requires exclusive access to the PORT registers */ flags = enter_critical_section(); - llerr("PORT%c pin: %d pinset: %08x base: %08x -- %s\n", + _llerr("PORT%c pin: %d pinset: %08x base: %08x -- %s\n", g_portchar[port], pin, pinset, base, msg); - llerr(" DIR: %08x OUT: %08x IN: %08x\n", + _llerr(" DIR: %08x OUT: %08x IN: %08x\n", getreg32(base + SAM_PORT_DIR_OFFSET), getreg32(base + SAM_PORT_OUT_OFFSET), getreg32(base + SAM_PORT_IN_OFFSET)); - llerr(" CTRL: %08x WRCONFIG: %08x\n", + _llerr(" CTRL: %08x WRCONFIG: %08x\n", getreg32(base + SAM_PORT_CTRL_OFFSET), getreg32(base + SAM_PORT_WRCONFIG_OFFSET)); - llerr(" PMUX[%08x]: %02x PINCFG[%08x]: %02x\n", + _llerr(" PMUX[%08x]: %02x PINCFG[%08x]: %02x\n", base + SAM_PORT_PMUX_OFFSET(pin), getreg8(base + SAM_PORT_PMUX_OFFSET(pin)), base + SAM_PORT_PINCFG_OFFSET(pin), diff --git a/arch/arm/src/samdl/sam_spi.c b/arch/arm/src/samdl/sam_spi.c index 6211147a85..1d8f2c4163 100644 --- a/arch/arm/src/samdl/sam_spi.c +++ b/arch/arm/src/samdl/sam_spi.c @@ -540,7 +540,7 @@ static bool spi_checkreg(struct sam_spidev_s *priv, bool wr, uint32_t regval, { /* Yes... show how many times we did it */ - llerr("...[Repeats %d times]...\n", priv->ntimes); + _llerr("...[Repeats %d times]...\n", priv->ntimes); } /* Save information about the new access */ @@ -573,7 +573,7 @@ static uint8_t spi_getreg8(struct sam_spidev_s *priv, unsigned int offset) #ifdef CONFIG_SAMDL_SPI_REGDEBUG if (spi_checkreg(priv, false, (uint32_t)regval, regaddr)) { - llerr("%08x->%02x\n", regaddr, regval); + _llerr("%08x->%02x\n", regaddr, regval); } #endif @@ -596,7 +596,7 @@ static void spi_putreg8(struct sam_spidev_s *priv, uint8_t regval, #ifdef CONFIG_SAMDL_SPI_REGDEBUG if (spi_checkreg(priv, true, (uint32_t)regval, regaddr)) { - llerr("%08x<-%02x\n", regaddr, regval); + _llerr("%08x<-%02x\n", regaddr, regval); } #endif @@ -619,7 +619,7 @@ static uint16_t spi_getreg16(struct sam_spidev_s *priv, unsigned int offset) #ifdef CONFIG_SAMDL_SPI_REGDEBUG if (spi_checkreg(priv, false, (uint32_t)regval, regaddr)) { - llerr("%08x->%04x\n", regaddr, regval); + _llerr("%08x->%04x\n", regaddr, regval); } #endif @@ -642,7 +642,7 @@ static void spi_putreg16(struct sam_spidev_s *priv, uint16_t regval, #ifdef CONFIG_SAMDL_SPI_REGDEBUG if (spi_checkreg(priv, true, (uint32_t)regval, regaddr)) { - llerr("%08x<-%04x\n", regaddr, regval); + _llerr("%08x<-%04x\n", regaddr, regval); } #endif @@ -665,7 +665,7 @@ static uint32_t spi_getreg32(struct sam_spidev_s *priv, unsigned int offset) #ifdef CONFIG_SAMDL_SPI_REGDEBUG if (spi_checkreg(priv, false, regval, regaddr)) { - llerr("%08x->%08x\n", regaddr, regval); + _llerr("%08x->%08x\n", regaddr, regval); } #endif @@ -688,7 +688,7 @@ static void spi_putreg32(struct sam_spidev_s *priv, uint32_t regval, #ifdef CONFIG_SAMDL_SPI_REGDEBUG if (spi_checkreg(priv, true, regval, regaddr)) { - llerr("%08x<-%08x\n", regaddr, regval); + _llerr("%08x<-%08x\n", regaddr, regval); } #endif diff --git a/arch/arm/src/samv7/sam_emac.c b/arch/arm/src/samv7/sam_emac.c index b11150ffaa..f43d432b68 100644 --- a/arch/arm/src/samv7/sam_emac.c +++ b/arch/arm/src/samv7/sam_emac.c @@ -966,7 +966,7 @@ static bool sam_checkreg(struct sam_emac_s *priv, bool wr, uint32_t regval, { /* Yes... show how many times we did it */ - llerr("...[Repeats %d times]...\n", priv->ntimes); + _llerr("...[Repeats %d times]...\n", priv->ntimes); } /* Save information about the new access */ @@ -999,7 +999,7 @@ static uint32_t sam_getreg(struct sam_emac_s *priv, uint16_t offset) #ifdef CONFIG_SAMV7_EMAC_REGDEBUG if (sam_checkreg(priv, false, regval, regaddr)) { - llerr("%08x->%08x\n", regaddr, regval); + _llerr("%08x->%08x\n", regaddr, regval); } #endif @@ -1023,7 +1023,7 @@ static void sam_putreg(struct sam_emac_s *priv, uint16_t offset, #ifdef CONFIG_SAMV7_EMAC_REGDEBUG if (sam_checkreg(priv, true, regval, regaddr)) { - llerr("%08x<-%08x\n", regaddr, regval); + _llerr("%08x<-%08x\n", regaddr, regval); } #endif diff --git a/arch/arm/src/samv7/sam_hsmci.c b/arch/arm/src/samv7/sam_hsmci.c index 8c487a75fd..ec664e0e93 100644 --- a/arch/arm/src/samv7/sam_hsmci.c +++ b/arch/arm/src/samv7/sam_hsmci.c @@ -653,7 +653,7 @@ static bool sam_checkreg(struct sam_dev_s *priv, bool wr, uint32_t value, { /* Yes... show how many times we did it */ - llerr("...[Repeats %d times]...\n", priv->ntimes); + _llerr("...[Repeats %d times]...\n", priv->ntimes); } /* Save information about the new access */ @@ -686,7 +686,7 @@ static inline uint32_t sam_getreg(struct sam_dev_s *priv, unsigned int offset) #ifdef CONFIG_SAMV7_HSMCI_REGDEBUG if (sam_checkreg(priv, false, value, address)) { - llerr("%08x->%08x\n", address, value); + _llerr("%08x->%08x\n", address, value); } #endif @@ -709,7 +709,7 @@ static inline void sam_putreg(struct sam_dev_s *priv, uint32_t value, #ifdef CONFIG_SAMV7_HSMCI_REGDEBUG if (sam_checkreg(priv, true, value, address)) { - llerr("%08x<-%08x\n", address, value); + _llerr("%08x<-%08x\n", address, value); } #endif diff --git a/arch/arm/src/samv7/sam_irq.c b/arch/arm/src/samv7/sam_irq.c index 4c729272e4..faf021fa47 100644 --- a/arch/arm/src/samv7/sam_irq.c +++ b/arch/arm/src/samv7/sam_irq.c @@ -177,7 +177,7 @@ static void sam_dumpnvic(const char *msg, int irq) static int sam_nmi(int irq, FAR void *context) { (void)up_irq_save(); - err("PANIC!!! NMI received\n"); + _err("PANIC!!! NMI received\n"); PANIC(); return 0; } @@ -185,7 +185,7 @@ static int sam_nmi(int irq, FAR void *context) static int sam_busfault(int irq, FAR void *context) { (void)up_irq_save(); - err("PANIC!!! Bus fault received: %08x\n", getreg32(NVIC_CFAULTS)); + _err("PANIC!!! Bus fault received: %08x\n", getreg32(NVIC_CFAULTS)); PANIC(); return 0; } @@ -193,7 +193,7 @@ static int sam_busfault(int irq, FAR void *context) static int sam_usagefault(int irq, FAR void *context) { (void)up_irq_save(); - err("PANIC!!! Usage fault received: %08x\n", getreg32(NVIC_CFAULTS)); + _err("PANIC!!! Usage fault received: %08x\n", getreg32(NVIC_CFAULTS)); PANIC(); return 0; } @@ -201,7 +201,7 @@ static int sam_usagefault(int irq, FAR void *context) static int sam_pendsv(int irq, FAR void *context) { (void)up_irq_save(); - err("PANIC!!! PendSV received\n"); + _err("PANIC!!! PendSV received\n"); PANIC(); return 0; } @@ -209,7 +209,7 @@ static int sam_pendsv(int irq, FAR void *context) static int sam_errmonitor(int irq, FAR void *context) { (void)up_irq_save(); - err("PANIC!!! Debug Monitor received\n"); + _err("PANIC!!! Debug Monitor received\n"); PANIC(); return 0; } @@ -217,7 +217,7 @@ static int sam_errmonitor(int irq, FAR void *context) static int sam_reserved(int irq, FAR void *context) { (void)up_irq_save(); - err("PANIC!!! Reserved interrupt\n"); + _err("PANIC!!! Reserved interrupt\n"); PANIC(); return 0; } diff --git a/arch/arm/src/samv7/sam_mcan.c b/arch/arm/src/samv7/sam_mcan.c index ab169b13af..1cf299e055 100644 --- a/arch/arm/src/samv7/sam_mcan.c +++ b/arch/arm/src/samv7/sam_mcan.c @@ -1195,7 +1195,7 @@ static uint32_t mcan_getreg(FAR struct sam_mcan_s *priv, int offset) { if (priv->count == 4) { - llerr("...\n"); + _llerr("...\n"); } return regval; @@ -1212,7 +1212,7 @@ static uint32_t mcan_getreg(FAR struct sam_mcan_s *priv, int offset) { /* Yes.. then show how many times the value repeated */ - llerr("[repeats %d more times]\n", priv->count - 3); + _llerr("[repeats %d more times]\n", priv->count - 3); } /* Save the new address, value, and count */ @@ -1224,7 +1224,7 @@ static uint32_t mcan_getreg(FAR struct sam_mcan_s *priv, int offset) /* Show the register value read */ - llerr("%08x->%08x\n", regaddr, regval); + _llerr("%08x->%08x\n", regaddr, regval); return regval; } @@ -1261,7 +1261,7 @@ static void mcan_putreg(FAR struct sam_mcan_s *priv, int offset, uint32_t regval /* Show the register value being written */ - llerr("%08x<-%08x\n", regaddr, regval); + _llerr("%08x<-%08x\n", regaddr, regval); /* Write the value */ @@ -1296,70 +1296,70 @@ static void mcan_dumpregs(FAR struct sam_mcan_s *priv, FAR const char *msg) { FAR const struct sam_config_s *config = priv->config; - llerr("MCAN%d Registers: %s\n", config->port, msg); - llerr(" Base: %08x\n", config->base); + _llerr("MCAN%d Registers: %s\n", config->port, msg); + _llerr(" Base: %08x\n", config->base); - llerr(" CUST: %08x FBTP: %08x TEST: %08x RWD: %08x\n", + _llerr(" CUST: %08x FBTP: %08x TEST: %08x RWD: %08x\n", getreg32(config->base + SAM_MCAN_CUST_OFFSET), getreg32(config->base + SAM_MCAN_FBTP_OFFSET), getreg32(config->base + SAM_MCAN_TEST_OFFSET), getreg32(config->base + SAM_MCAN_RWD_OFFSET)); - llerr(" CCCR: %08x BTP: %08x TSCC: %08x TSCV: %08x\n", + _llerr(" CCCR: %08x BTP: %08x TSCC: %08x TSCV: %08x\n", getreg32(config->base + SAM_MCAN_CCCR_OFFSET), getreg32(config->base + SAM_MCAN_BTP_OFFSET), getreg32(config->base + SAM_MCAN_TSCC_OFFSET), getreg32(config->base + SAM_MCAN_TSCV_OFFSET)); - llerr(" TOCC: %08x TOCV: %08x ECR: %08x PSR: %08x\n", + _llerr(" TOCC: %08x TOCV: %08x ECR: %08x PSR: %08x\n", getreg32(config->base + SAM_MCAN_TOCC_OFFSET), getreg32(config->base + SAM_MCAN_TOCV_OFFSET), getreg32(config->base + SAM_MCAN_ECR_OFFSET), getreg32(config->base + SAM_MCAN_PSR_OFFSET)); - llerr(" IR: %08x IE: %08x ILS: %08x ILE: %08x\n", + _llerr(" IR: %08x IE: %08x ILS: %08x ILE: %08x\n", getreg32(config->base + SAM_MCAN_IR_OFFSET), getreg32(config->base + SAM_MCAN_IE_OFFSET), getreg32(config->base + SAM_MCAN_ILS_OFFSET), getreg32(config->base + SAM_MCAN_ILE_OFFSET)); - llerr(" GFC: %08x SIDFC: %08x XIDFC: %08x XIDAM: %08x\n", + _llerr(" GFC: %08x SIDFC: %08x XIDFC: %08x XIDAM: %08x\n", getreg32(config->base + SAM_MCAN_GFC_OFFSET), getreg32(config->base + SAM_MCAN_SIDFC_OFFSET), getreg32(config->base + SAM_MCAN_XIDFC_OFFSET), getreg32(config->base + SAM_MCAN_XIDAM_OFFSET)); - llerr(" HPMS: %08x NDAT1: %08x NDAT2: %08x RXF0C: %08x\n", + _llerr(" HPMS: %08x NDAT1: %08x NDAT2: %08x RXF0C: %08x\n", getreg32(config->base + SAM_MCAN_HPMS_OFFSET), getreg32(config->base + SAM_MCAN_NDAT1_OFFSET), getreg32(config->base + SAM_MCAN_NDAT2_OFFSET), getreg32(config->base + SAM_MCAN_RXF0C_OFFSET)); - llerr(" RXF0S: %08x FXF0A: %08x RXBC: %08x RXF1C: %08x\n", + _llerr(" RXF0S: %08x FXF0A: %08x RXBC: %08x RXF1C: %08x\n", getreg32(config->base + SAM_MCAN_RXF0S_OFFSET), getreg32(config->base + SAM_MCAN_RXF0A_OFFSET), getreg32(config->base + SAM_MCAN_RXBC_OFFSET), getreg32(config->base + SAM_MCAN_RXF1C_OFFSET)); - llerr(" RXF1S: %08x FXF1A: %08x RXESC: %08x TXBC: %08x\n", + _llerr(" RXF1S: %08x FXF1A: %08x RXESC: %08x TXBC: %08x\n", getreg32(config->base + SAM_MCAN_RXF1S_OFFSET), getreg32(config->base + SAM_MCAN_RXF1A_OFFSET), getreg32(config->base + SAM_MCAN_RXESC_OFFSET), getreg32(config->base + SAM_MCAN_TXBC_OFFSET)); - llerr(" TXFQS: %08x TXESC: %08x TXBRP: %08x TXBAR: %08x\n", + _llerr(" TXFQS: %08x TXESC: %08x TXBRP: %08x TXBAR: %08x\n", getreg32(config->base + SAM_MCAN_TXFQS_OFFSET), getreg32(config->base + SAM_MCAN_TXESC_OFFSET), getreg32(config->base + SAM_MCAN_TXBRP_OFFSET), getreg32(config->base + SAM_MCAN_TXBAR_OFFSET)); - llerr(" TXBCR: %08x TXBTO: %08x TXBCF: %08x TXBTIE: %08x\n", + _llerr(" TXBCR: %08x TXBTO: %08x TXBCF: %08x TXBTIE: %08x\n", getreg32(config->base + SAM_MCAN_TXBCR_OFFSET), getreg32(config->base + SAM_MCAN_TXBTO_OFFSET), getreg32(config->base + SAM_MCAN_TXBCF_OFFSET), getreg32(config->base + SAM_MCAN_TXBTIE_OFFSET)); - llerr("TXBCIE: %08x TXEFC: %08x TXEFS: %08x TXEFA: %08x\n", + _llerr("TXBCIE: %08x TXEFC: %08x TXEFS: %08x TXEFA: %08x\n", getreg32(config->base + SAM_MCAN_TXBCIE_OFFSET), getreg32(config->base + SAM_MCAN_TXEFC_OFFSET), getreg32(config->base + SAM_MCAN_TXEFS_OFFSET), diff --git a/arch/arm/src/samv7/sam_pck.c b/arch/arm/src/samv7/sam_pck.c index ddfc7371fa..3511d0d9ce 100644 --- a/arch/arm/src/samv7/sam_pck.c +++ b/arch/arm/src/samv7/sam_pck.c @@ -128,7 +128,7 @@ uint32_t sam_pck_configure(enum pckid_e pckid, enum pckid_clksrc_e clksrc, break; default: - err("ERROR: Unknown clock source\n"); + _err("ERROR: Unknown clock source\n"); return 0; } @@ -272,7 +272,7 @@ uint32_t sam_pck_frequency(enum pckid_e pckid) break; default: - err("ERROR: Unknown clock source\n"); + _err("ERROR: Unknown clock source\n"); return 0; } diff --git a/arch/arm/src/samv7/sam_qspi.c b/arch/arm/src/samv7/sam_qspi.c index 3418d183a6..569f374702 100644 --- a/arch/arm/src/samv7/sam_qspi.c +++ b/arch/arm/src/samv7/sam_qspi.c @@ -374,7 +374,7 @@ static bool qspi_checkreg(struct sam_qspidev_s *priv, bool wr, uint32_t value, { /* Yes... show how many times we did it */ - llerr("...[Repeats %d times]...\n", priv->ntimes); + _llerr("...[Repeats %d times]...\n", priv->ntimes); } /* Save information about the new access */ @@ -408,7 +408,7 @@ static inline uint32_t qspi_getreg(struct sam_qspidev_s *priv, #ifdef CONFIG_SAMV7_QSPI_REGDEBUG if (qspi_checkreg(priv, false, value, address)) { - llerr("%08x->%08x\n", address, value); + _llerr("%08x->%08x\n", address, value); } #endif @@ -431,7 +431,7 @@ static inline void qspi_putreg(struct sam_qspidev_s *priv, uint32_t value, #ifdef CONFIG_SAMV7_QSPI_REGDEBUG if (qspi_checkreg(priv, true, value, address)) { - llerr("%08x<-%08x\n", address, value); + _llerr("%08x<-%08x\n", address, value); } #endif diff --git a/arch/arm/src/samv7/sam_rswdt.c b/arch/arm/src/samv7/sam_rswdt.c index a097a7056f..3723a0bc83 100644 --- a/arch/arm/src/samv7/sam_rswdt.c +++ b/arch/arm/src/samv7/sam_rswdt.c @@ -185,7 +185,7 @@ static uint32_t sam_getreg(uintptr_t regaddr) { if (count == 4) { - llerr("...\n"); + _llerr("...\n"); } return regval; @@ -202,7 +202,7 @@ static uint32_t sam_getreg(uintptr_t regaddr) { /* Yes.. then show how many times the value repeated */ - llerr("[repeats %d more times]\n", count-3); + _llerr("[repeats %d more times]\n", count-3); } /* Save the new address, value, and count */ @@ -214,7 +214,7 @@ static uint32_t sam_getreg(uintptr_t regaddr) /* Show the register value read */ - llerr("%08x->%048\n", regaddr, regval); + _llerr("%08x->%048\n", regaddr, regval); return regval; } #endif @@ -232,7 +232,7 @@ static void sam_putreg(uint32_t regval, uintptr_t regaddr) { /* Show the register value being written */ - llerr("%08x<-%08x\n", regaddr, regval); + _llerr("%08x<-%08x\n", regaddr, regval); /* Write the value */ diff --git a/arch/arm/src/samv7/sam_spi.c b/arch/arm/src/samv7/sam_spi.c index 7f200b0422..7af29d3a70 100644 --- a/arch/arm/src/samv7/sam_spi.c +++ b/arch/arm/src/samv7/sam_spi.c @@ -428,7 +428,7 @@ static bool spi_checkreg(struct sam_spidev_s *spi, bool wr, uint32_t value, { /* Yes... show how many times we did it */ - llerr("...[Repeats %d times]...\n", spi->ntimes); + _llerr("...[Repeats %d times]...\n", spi->ntimes); } /* Save information about the new access */ @@ -462,7 +462,7 @@ static inline uint32_t spi_getreg(struct sam_spidev_s *spi, #ifdef CONFIG_SAMV7_SPI_REGDEBUG if (spi_checkreg(spi, false, value, address)) { - llerr("%08x->%08x\n", address, value); + _llerr("%08x->%08x\n", address, value); } #endif @@ -485,7 +485,7 @@ static inline void spi_putreg(struct sam_spidev_s *spi, uint32_t value, #ifdef CONFIG_SAMV7_SPI_REGDEBUG if (spi_checkreg(spi, true, value, address)) { - llerr("%08x<-%08x\n", address, value); + _llerr("%08x<-%08x\n", address, value); } #endif diff --git a/arch/arm/src/samv7/sam_spi_slave.c b/arch/arm/src/samv7/sam_spi_slave.c index 80d6f436e0..574b5ab0bf 100644 --- a/arch/arm/src/samv7/sam_spi_slave.c +++ b/arch/arm/src/samv7/sam_spi_slave.c @@ -248,7 +248,7 @@ static bool spi_checkreg(struct sam_spidev_s *priv, bool wr, uint32_t value, { /* Yes... show how many times we did it */ - llerr("...[Repeats %d times]...\n", priv->ntimes); + _llerr("...[Repeats %d times]...\n", priv->ntimes); } /* Save information about the new access */ @@ -281,7 +281,7 @@ static uint32_t spi_getreg(struct sam_spidev_s *priv, unsigned int offset) #ifdef CONFIG_SAMV7_SPI_REGDEBUG if (spi_checkreg(priv, false, value, address)) { - llerr("%08x->%08x\n", address, value); + _llerr("%08x->%08x\n", address, value); } #endif @@ -304,7 +304,7 @@ static void spi_putreg(struct sam_spidev_s *priv, uint32_t value, #ifdef CONFIG_SAMV7_SPI_REGDEBUG if (spi_checkreg(priv, true, value, address)) { - llerr("%08x<-%08x\n", address, value); + _llerr("%08x<-%08x\n", address, value); } #endif diff --git a/arch/arm/src/samv7/sam_ssc.c b/arch/arm/src/samv7/sam_ssc.c index c9204f093f..eb21113bd3 100644 --- a/arch/arm/src/samv7/sam_ssc.c +++ b/arch/arm/src/samv7/sam_ssc.c @@ -674,7 +674,7 @@ static bool ssc_checkreg(struct sam_ssc_s *priv, bool wr, uint32_t regval, { /* Yes... show how many times we did it */ - llerr("...[Repeats %d times]...\n", priv->count); + _llerr("...[Repeats %d times]...\n", priv->count); } /* Save information about the new access */ @@ -708,7 +708,7 @@ static inline uint32_t ssc_getreg(struct sam_ssc_s *priv, #ifdef CONFIG_SAMV7_SSC_REGDEBUG if (ssc_checkreg(priv, false, regval, regaddr)) { - llerr("%08x->%08x\n", regaddr, regval); + _llerr("%08x->%08x\n", regaddr, regval); } #endif @@ -731,7 +731,7 @@ static inline void ssc_putreg(struct sam_ssc_s *priv, unsigned int offset, #ifdef CONFIG_SAMV7_SSC_REGDEBUG if (ssc_checkreg(priv, true, regval, regaddr)) { - llerr("%08x<-%08x\n", regaddr, regval); + _llerr("%08x<-%08x\n", regaddr, regval); } #endif @@ -1060,7 +1060,7 @@ static void ssc_dma_sampleinit(struct sam_ssc_s *priv, #if defined(CONFIG_SAMV7_SSC_DMADEBUG) && defined(SSC_HAVE_RX) static void ssc_rxdma_sampledone(struct sam_ssc_s *priv, int result) { - llerr("result: %d\n", result); + _llerr("result: %d\n", result); /* Sample the final registers */ @@ -1125,7 +1125,7 @@ static void ssc_rxdma_sampledone(struct sam_ssc_s *priv, int result) #if defined(CONFIG_SAMV7_SSC_DMADEBUG) && defined(SSC_HAVE_TX) static void ssc_txdma_sampledone(struct sam_ssc_s *priv, int result) { - llerr("result: %d\n", result); + _llerr("result: %d\n", result); /* Sample the final registers */ diff --git a/arch/arm/src/samv7/sam_tc.c b/arch/arm/src/samv7/sam_tc.c index 968c5528d0..4eba2f077b 100644 --- a/arch/arm/src/samv7/sam_tc.c +++ b/arch/arm/src/samv7/sam_tc.c @@ -643,17 +643,17 @@ static void sam_regdump(struct sam_chan_s *chan, const char *msg) uintptr_t base; base = tc->base; - llerr("TC%d [%08x]: %s\n", tc->tc, (int)base, msg); - llerr(" BMR: %08x QIMR: %08x QISR: %08x WPMR: %08x\n", + _llerr("TC%d [%08x]: %s\n", tc->tc, (int)base, msg); + _llerr(" BMR: %08x QIMR: %08x QISR: %08x WPMR: %08x\n", getreg32(base+SAM_TC_BMR_OFFSET), getreg32(base+SAM_TC_QIMR_OFFSET), getreg32(base+SAM_TC_QISR_OFFSET), getreg32(base+SAM_TC_WPMR_OFFSET)); base = chan->base; - llerr("TC%d Channel %d [%08x]: %s\n", tc->tc, chan->chan, (int)base, msg); - llerr(" CMR: %08x SSMR: %08x RAB: %08x CV: %08x\n", + _llerr("TC%d Channel %d [%08x]: %s\n", tc->tc, chan->chan, (int)base, msg); + _llerr(" CMR: %08x SSMR: %08x RAB: %08x CV: %08x\n", getreg32(base+SAM_TC_CMR_OFFSET), getreg32(base+SAM_TC_SMMR_OFFSET), getreg32(base+SAM_TC_RAB_OFFSET), getreg32(base+SAM_TC_CV_OFFSET)); - llerr(" RA: %08x RB: %08x RC: %08x IMR: %08x\n", + _llerr(" RA: %08x RB: %08x RC: %08x IMR: %08x\n", getreg32(base+SAM_TC_RA_OFFSET), getreg32(base+SAM_TC_RB_OFFSET), getreg32(base+SAM_TC_RC_OFFSET), getreg32(base+SAM_TC_IMR_OFFSET)); } @@ -698,7 +698,7 @@ static bool sam_checkreg(struct sam_tc_s *tc, bool wr, uint32_t regaddr, { /* Yes... show how many times we did it */ - llerr("...[Repeats %d times]...\n", tc->ntimes); + _llerr("...[Repeats %d times]...\n", tc->ntimes); } /* Save information about the new access */ @@ -733,7 +733,7 @@ static inline uint32_t sam_tc_getreg(struct sam_chan_s *chan, #ifdef CONFIG_SAMV7_TC_REGDEBUG if (sam_checkreg(tc, false, regaddr, regval)) { - llerr("%08x->%08x\n", regaddr, regval); + _llerr("%08x->%08x\n", regaddr, regval); } #endif @@ -757,7 +757,7 @@ static inline void sam_tc_putreg(struct sam_chan_s *chan, uint32_t regval, #ifdef CONFIG_SAMV7_TC_REGDEBUG if (sam_checkreg(tc, true, regaddr, regval)) { - llerr("%08x<-%08x\n", regaddr, regval); + _llerr("%08x<-%08x\n", regaddr, regval); } #endif @@ -781,7 +781,7 @@ static inline uint32_t sam_chan_getreg(struct sam_chan_s *chan, #ifdef CONFIG_SAMV7_TC_REGDEBUG if (sam_checkreg(chan->tc, false, regaddr, regval)) { - llerr("%08x->%08x\n", regaddr, regval); + _llerr("%08x->%08x\n", regaddr, regval); } #endif @@ -804,7 +804,7 @@ static inline void sam_chan_putreg(struct sam_chan_s *chan, unsigned int offset, #ifdef CONFIG_SAMV7_TC_REGDEBUG if (sam_checkreg(chan->tc, true, regaddr, regval)) { - llerr("%08x<-%08x\n", regaddr, regval); + _llerr("%08x<-%08x\n", regaddr, regval); } #endif diff --git a/arch/arm/src/samv7/sam_twihs.c b/arch/arm/src/samv7/sam_twihs.c index b57662cc18..4dc6fcae9b 100644 --- a/arch/arm/src/samv7/sam_twihs.c +++ b/arch/arm/src/samv7/sam_twihs.c @@ -349,7 +349,7 @@ static bool twi_checkreg(struct twi_dev_s *priv, bool wr, uint32_t value, { /* Yes... show how many times we did it */ - llerr("...[Repeats %d times]...\n", priv->ntimes); + _llerr("...[Repeats %d times]...\n", priv->ntimes); } /* Save information about the new access */ @@ -381,7 +381,7 @@ static uint32_t twi_getabs(struct twi_dev_s *priv, uintptr_t address) if (twi_checkreg(priv, false, value, address)) { - llerr("%08x->%08x\n", address, value); + _llerr("%08x->%08x\n", address, value); } return value; @@ -402,7 +402,7 @@ static void twi_putabs(struct twi_dev_s *priv, uintptr_t address, { if (twi_checkreg(priv, true, value, address)) { - llerr("%08x<-%08x\n", address, value); + _llerr("%08x<-%08x\n", address, value); } putreg32(value, address); diff --git a/arch/arm/src/samv7/sam_usbdevhs.c b/arch/arm/src/samv7/sam_usbdevhs.c index 8c8cde272a..43a86c0e79 100644 --- a/arch/arm/src/samv7/sam_usbdevhs.c +++ b/arch/arm/src/samv7/sam_usbdevhs.c @@ -743,7 +743,7 @@ const struct trace_msg_t g_usb_trace_strings_intdecode[] = #ifdef CONFIG_SAMV7_USBHS_REGDEBUG static void sam_printreg(uintptr_t regaddr, uint32_t regval, bool iswrite) { - llerr("%p%s%08x\n", regaddr, iswrite ? "<-" : "->", regval); + _llerr("%p%s%08x\n", regaddr, iswrite ? "<-" : "->", regval); } #endif @@ -794,7 +794,7 @@ static void sam_checkreg(uintptr_t regaddr, uint32_t regval, bool iswrite) { /* No.. More than one. */ - llerr("[repeats %d more times]\n", count); + _llerr("[repeats %d more times]\n", count); } } @@ -874,31 +874,31 @@ static void sam_dumpep(struct sam_usbdev_s *priv, int epno) { /* Global Registers */ - llerr("Global Register:\n"); - llerr(" CTRL: %08x\n", sam_getreg(SAM_USBHS_DEVCTRL)); - llerr(" ISR: %08x\n", sam_getreg(SAM_USBHS_DEVISR)); - llerr(" IMR: %08x\n", sam_getreg(SAM_USBHS_DEVIMR)); - llerr(" EPT: %08x\n", sam_getreg(SAM_USBHS_DEVEPT)); - llerr(" FNUM: %08x\n", sam_getreg(SAM_USBHS_DEVFNUM)); + _llerr("Global Register:\n"); + _llerr(" CTRL: %08x\n", sam_getreg(SAM_USBHS_DEVCTRL)); + _llerr(" ISR: %08x\n", sam_getreg(SAM_USBHS_DEVISR)); + _llerr(" IMR: %08x\n", sam_getreg(SAM_USBHS_DEVIMR)); + _llerr(" EPT: %08x\n", sam_getreg(SAM_USBHS_DEVEPT)); + _llerr(" FNUM: %08x\n", sam_getreg(SAM_USBHS_DEVFNUM)); /* Endpoint registers */ - llerr("Endpoint %d Register:\n", epno); - llerr(" CFG: %08x\n", sam_getreg(SAM_USBHS_DEVEPTCFG(epno))); - llerr(" ISR: %08x\n", sam_getreg(SAM_USBHS_DEVEPTISR(epno))); - llerr(" IMR: %08x\n", sam_getreg(SAM_USBHS_DEVEPTIMR(epno))); + _llerr("Endpoint %d Register:\n", epno); + _llerr(" CFG: %08x\n", sam_getreg(SAM_USBHS_DEVEPTCFG(epno))); + _llerr(" ISR: %08x\n", sam_getreg(SAM_USBHS_DEVEPTISR(epno))); + _llerr(" IMR: %08x\n", sam_getreg(SAM_USBHS_DEVEPTIMR(epno))); - llerr("DMA %d Register:\n", epno); + _llerr("DMA %d Register:\n", epno); if ((SAM_EPSET_DMA & SAM_EP_BIT(epno)) != 0) { - llerr(" NXTDSC: %08x\n", sam_getreg(SAM_USBHS_DEVDMANXTDSC(epno))); - llerr(" ADDRESS: %08x\n", sam_getreg(SAM_USBHS_DEVDMAADDR(epno))); - llerr(" CONTROL: %08x\n", sam_getreg(SAM_USBHS_DEVDMACTRL(epno))); - llerr(" STATUS: %08x\n", sam_getreg(SAM_USBHS_DEVDMASTA(epno))); + _llerr(" NXTDSC: %08x\n", sam_getreg(SAM_USBHS_DEVDMANXTDSC(epno))); + _llerr(" ADDRESS: %08x\n", sam_getreg(SAM_USBHS_DEVDMAADDR(epno))); + _llerr(" CONTROL: %08x\n", sam_getreg(SAM_USBHS_DEVDMACTRL(epno))); + _llerr(" STATUS: %08x\n", sam_getreg(SAM_USBHS_DEVDMASTA(epno))); } else { - llerr(" None\n"); + _llerr(" None\n"); } } #endif diff --git a/arch/arm/src/samv7/sam_wdt.c b/arch/arm/src/samv7/sam_wdt.c index 1c2d81cd9b..d8c870b1f6 100644 --- a/arch/arm/src/samv7/sam_wdt.c +++ b/arch/arm/src/samv7/sam_wdt.c @@ -185,7 +185,7 @@ static uint32_t sam_getreg(uintptr_t regaddr) { if (count == 4) { - llerr("...\n"); + _llerr("...\n"); } return regval; @@ -202,7 +202,7 @@ static uint32_t sam_getreg(uintptr_t regaddr) { /* Yes.. then show how many times the value repeated */ - llerr("[repeats %d more times]\n", count-3); + _llerr("[repeats %d more times]\n", count-3); } /* Save the new address, value, and count */ @@ -214,7 +214,7 @@ static uint32_t sam_getreg(uintptr_t regaddr) /* Show the register value read */ - llerr("%08x->%048\n", regaddr, regval); + _llerr("%08x->%048\n", regaddr, regval); return regval; } #endif @@ -232,7 +232,7 @@ static void sam_putreg(uint32_t regval, uintptr_t regaddr) { /* Show the register value being written */ - llerr("%08x<-%08x\n", regaddr, regval); + _llerr("%08x<-%08x\n", regaddr, regval); /* Write the value */ diff --git a/arch/arm/src/stm32/stm32_bbsram.c b/arch/arm/src/stm32/stm32_bbsram.c index e2ca52eee4..e35f5e05a7 100644 --- a/arch/arm/src/stm32/stm32_bbsram.c +++ b/arch/arm/src/stm32/stm32_bbsram.c @@ -187,14 +187,14 @@ static void stm32_bbsram_rd(void) static void stm32_bbsram_dump(FAR struct bbsramfh_s *bbf, char *op) { BBSRAM_DEBUG_READ(); - info("%s:\n", op); - info(" File Address:0x%8x\n", bbf); - info(" crc:0x%8x\n", bbf->crc); - info(" fileno:%d\n", (int) bbf->fileno); - info(" dirty:%d\n", (int) bbf->dirty); - info(" length:%d\n", (int) bbf->len); - info(" time:%ld:%ld\n", bbf->lastwrite.tv_sec, bbf->lastwrite.tv_nsec); - info(" data: 0x%2x 0x%2x 0x%2x 0x%2x 0x%2x\n", + _info("%s:\n", op); + _info(" File Address:0x%8x\n", bbf); + _info(" crc:0x%8x\n", bbf->crc); + _info(" fileno:%d\n", (int) bbf->fileno); + _info(" dirty:%d\n", (int) bbf->dirty); + _info(" length:%d\n", (int) bbf->len); + _info(" time:%ld:%ld\n", bbf->lastwrite.tv_sec, bbf->lastwrite.tv_nsec); + _info(" data: 0x%2x 0x%2x 0x%2x 0x%2x 0x%2x\n", bbf->data[0], bbf->data[1], bbf->data[2], bbf->data[3], bbf->data[4]); } #endif diff --git a/arch/arm/src/stm32/stm32_dumpgpio.c b/arch/arm/src/stm32/stm32_dumpgpio.c index 5de501f033..b50f8b84cc 100644 --- a/arch/arm/src/stm32/stm32_dumpgpio.c +++ b/arch/arm/src/stm32/stm32_dumpgpio.c @@ -120,18 +120,18 @@ int stm32_dumpgpio(uint32_t pinset, const char *msg) flags = enter_critical_section(); #if defined(CONFIG_STM32_STM32F10XX) - llinfo("GPIO%c pinset: %08x base: %08x -- %s\n", + _llinfo("GPIO%c pinset: %08x base: %08x -- %s\n", g_portchar[port], pinset, base, msg); if ((getreg32(STM32_RCC_APB2ENR) & RCC_APB2ENR_IOPEN(port)) != 0) { - llinfo(" CR: %08x %08x IDR: %04x ODR: %04x LCKR: %04x\n", + _llinfo(" CR: %08x %08x IDR: %04x ODR: %04x LCKR: %04x\n", getreg32(base + STM32_GPIO_CRH_OFFSET), getreg32(base + STM32_GPIO_CRL_OFFSET), getreg32(base + STM32_GPIO_IDR_OFFSET), getreg32(base + STM32_GPIO_ODR_OFFSET), getreg32(base + STM32_GPIO_LCKR_OFFSET)); - llinfo(" EVCR: %02x MAPR: %08x CR: %04x %04x %04x %04x\n", + _llinfo(" EVCR: %02x MAPR: %08x CR: %04x %04x %04x %04x\n", getreg32(STM32_AFIO_EVCR), getreg32(STM32_AFIO_MAPR), getreg32(STM32_AFIO_EXTICR1), getreg32(STM32_AFIO_EXTICR2), @@ -140,57 +140,57 @@ int stm32_dumpgpio(uint32_t pinset, const char *msg) } else { - llinfo(" GPIO%c not enabled: APB2ENR: %08x\n", + _llinfo(" GPIO%c not enabled: APB2ENR: %08x\n", g_portchar[port], getreg32(STM32_RCC_APB2ENR)); } #elif defined(CONFIG_STM32_STM32L15XX) DEBUGASSERT(port < STM32_NGPIO_PORTS); - llinfo("GPIO%c pinset: %08x base: %08x -- %s\n", + _llinfo("GPIO%c pinset: %08x base: %08x -- %s\n", g_portchar[port], pinset, base, msg); if ((getreg32(STM32_RCC_AHBENR) & RCC_AHBENR_GPIOEN(port)) != 0) { - llinfo(" MODE: %08x OTYPE: %04x OSPEED: %08x PUPDR: %08x\n", + _llinfo(" MODE: %08x OTYPE: %04x OSPEED: %08x PUPDR: %08x\n", getreg32(base + STM32_GPIO_MODER_OFFSET), getreg32(base + STM32_GPIO_OTYPER_OFFSET), getreg32(base + STM32_GPIO_OSPEED_OFFSET), getreg32(base + STM32_GPIO_PUPDR_OFFSET)); - llinfo(" IDR: %04x ODR: %04x BSRR: %08x LCKR: %04x\n", + _llinfo(" IDR: %04x ODR: %04x BSRR: %08x LCKR: %04x\n", getreg32(base + STM32_GPIO_IDR_OFFSET), getreg32(base + STM32_GPIO_ODR_OFFSET), getreg32(base + STM32_GPIO_BSRR_OFFSET), getreg32(base + STM32_GPIO_LCKR_OFFSET)); - llinfo(" AFRH: %08x AFRL: %08x\n", + _llinfo(" AFRH: %08x AFRL: %08x\n", getreg32(base + STM32_GPIO_AFRH_OFFSET), getreg32(base + STM32_GPIO_AFRL_OFFSET)); } else { - llinfo(" GPIO%c not enabled: AHBENR: %08x\n", + _llinfo(" GPIO%c not enabled: AHBENR: %08x\n", g_portchar[port], getreg32(STM32_RCC_AHBENR)); } #elif defined(CONFIG_STM32_STM32F30XX) || defined(CONFIG_STM32_STM32F37XX) DEBUGASSERT(port < STM32_NGPIO_PORTS); - llinfo("GPIO%c pinset: %08x base: %08x -- %s\n", + _llinfo("GPIO%c pinset: %08x base: %08x -- %s\n", g_portchar[port], pinset, base, msg); /* GPIOs are always enabled */ - llinfo(" MODE: %08x OTYPE: %04x OSPEED: %08x PUPDR: %08x\n", + _llinfo(" MODE: %08x OTYPE: %04x OSPEED: %08x PUPDR: %08x\n", getreg32(base + STM32_GPIO_MODER_OFFSET), getreg32(base + STM32_GPIO_OTYPER_OFFSET), getreg32(base + STM32_GPIO_OSPEED_OFFSET), getreg32(base + STM32_GPIO_PUPDR_OFFSET)); - llinfo(" IDR: %04x ODR: %04x BSRR: %08x LCKR: %04x\n", + _llinfo(" IDR: %04x ODR: %04x BSRR: %08x LCKR: %04x\n", getreg32(base + STM32_GPIO_IDR_OFFSET), getreg32(base + STM32_GPIO_ODR_OFFSET), getreg32(base + STM32_GPIO_BSRR_OFFSET), getreg32(base + STM32_GPIO_LCKR_OFFSET)); - llinfo(" AFRH: %08x AFRL: %08x BRR: %04x\n", + _llinfo(" AFRH: %08x AFRL: %08x BRR: %04x\n", getreg32(base + STM32_GPIO_AFRH_OFFSET), getreg32(base + STM32_GPIO_AFRL_OFFSET), getreg32(base + STM32_GPIO_BRR_OFFSET)); @@ -198,28 +198,28 @@ int stm32_dumpgpio(uint32_t pinset, const char *msg) #elif defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F40XX) DEBUGASSERT(port < STM32_NGPIO_PORTS); - llinfo("GPIO%c pinset: %08x base: %08x -- %s\n", + _llinfo("GPIO%c pinset: %08x base: %08x -- %s\n", g_portchar[port], pinset, base, msg); if ((getreg32(STM32_RCC_AHB1ENR) & RCC_AHB1ENR_GPIOEN(port)) != 0) { - llinfo(" MODE: %08x OTYPE: %04x OSPEED: %08x PUPDR: %08x\n", + _llinfo(" MODE: %08x OTYPE: %04x OSPEED: %08x PUPDR: %08x\n", getreg32(base + STM32_GPIO_MODER_OFFSET), getreg32(base + STM32_GPIO_OTYPER_OFFSET), getreg32(base + STM32_GPIO_OSPEED_OFFSET), getreg32(base + STM32_GPIO_PUPDR_OFFSET)); - llinfo(" IDR: %04x ODR: %04x BSRR: %08x LCKR: %04x\n", + _llinfo(" IDR: %04x ODR: %04x BSRR: %08x LCKR: %04x\n", getreg32(base + STM32_GPIO_IDR_OFFSET), getreg32(base + STM32_GPIO_ODR_OFFSET), getreg32(base + STM32_GPIO_BSRR_OFFSET), getreg32(base + STM32_GPIO_LCKR_OFFSET)); - llinfo(" AFRH: %08x AFRL: %08x\n", + _llinfo(" AFRH: %08x AFRL: %08x\n", getreg32(base + STM32_GPIO_AFRH_OFFSET), getreg32(base + STM32_GPIO_AFRL_OFFSET)); } else { - llinfo(" GPIO%c not enabled: AHB1ENR: %08x\n", + _llinfo(" GPIO%c not enabled: AHB1ENR: %08x\n", g_portchar[port], getreg32(STM32_RCC_AHB1ENR)); } #else diff --git a/arch/arm/src/stm32/stm32_idle.c b/arch/arm/src/stm32/stm32_idle.c index 64e08a1b04..888ed17ed7 100644 --- a/arch/arm/src/stm32/stm32_idle.c +++ b/arch/arm/src/stm32/stm32_idle.c @@ -101,7 +101,7 @@ static void up_idlepm(void) /* Perform board-specific, state-dependent logic here */ - llinfo("newstate= %d oldstate=%d\n", newstate, oldstate); + _llinfo("newstate= %d oldstate=%d\n", newstate, oldstate); /* Then force the global state change */ diff --git a/arch/arm/src/stm32/stm32_irq.c b/arch/arm/src/stm32/stm32_irq.c index 810c4a8f5b..1e9570cc90 100644 --- a/arch/arm/src/stm32/stm32_irq.c +++ b/arch/arm/src/stm32/stm32_irq.c @@ -164,7 +164,7 @@ static void stm32_dumpnvic(const char *msg, int irq) static int stm32_nmi(int irq, FAR void *context) { (void)up_irq_save(); - err("PANIC!!! NMI received\n"); + _err("PANIC!!! NMI received\n"); PANIC(); return 0; } @@ -172,7 +172,7 @@ static int stm32_nmi(int irq, FAR void *context) static int stm32_busfault(int irq, FAR void *context) { (void)up_irq_save(); - err("PANIC!!! Bus fault received: %08x\n", getreg32(NVIC_CFAULTS)); + _err("PANIC!!! Bus fault received: %08x\n", getreg32(NVIC_CFAULTS)); PANIC(); return 0; } @@ -180,7 +180,7 @@ static int stm32_busfault(int irq, FAR void *context) static int stm32_usagefault(int irq, FAR void *context) { (void)up_irq_save(); - err("PANIC!!! Usage fault received: %08x\n", getreg32(NVIC_CFAULTS)); + _err("PANIC!!! Usage fault received: %08x\n", getreg32(NVIC_CFAULTS)); PANIC(); return 0; } @@ -188,7 +188,7 @@ static int stm32_usagefault(int irq, FAR void *context) static int stm32_pendsv(int irq, FAR void *context) { (void)up_irq_save(); - err("PANIC!!! PendSV received\n"); + _err("PANIC!!! PendSV received\n"); PANIC(); return 0; } @@ -196,7 +196,7 @@ static int stm32_pendsv(int irq, FAR void *context) static int stm32_errmonitor(int irq, FAR void *context) { (void)up_irq_save(); - err("PANIC!!! Debug Monitor received\n"); + _err("PANIC!!! Debug Monitor received\n"); PANIC(); return 0; } @@ -204,7 +204,7 @@ static int stm32_errmonitor(int irq, FAR void *context) static int stm32_reserved(int irq, FAR void *context) { (void)up_irq_save(); - err("PANIC!!! Reserved interrupt\n"); + _err("PANIC!!! Reserved interrupt\n"); PANIC(); return 0; } diff --git a/arch/arm/src/stm32/stm32_rng.c b/arch/arm/src/stm32/stm32_rng.c index 11477eb893..fce55ebf0a 100644 --- a/arch/arm/src/stm32/stm32_rng.c +++ b/arch/arm/src/stm32/stm32_rng.c @@ -102,7 +102,7 @@ static int stm32_rnginitialize() { uint32_t regval; - info("Initializing RNG\n"); + _info("Initializing RNG\n"); memset(&g_rngdev, 0, sizeof(struct rng_dev_s)); @@ -112,7 +112,7 @@ static int stm32_rnginitialize() { /* We could not attach the ISR to the interrupt */ - info("Could not attach IRQ.\n"); + _info("Could not attach IRQ.\n"); return -EAGAIN; } diff --git a/arch/arm/src/stm32f7/stm32_irq.c b/arch/arm/src/stm32f7/stm32_irq.c index 407e756e98..62c4aee7aa 100644 --- a/arch/arm/src/stm32f7/stm32_irq.c +++ b/arch/arm/src/stm32f7/stm32_irq.c @@ -189,7 +189,7 @@ static void stm32_dumpnvic(const char *msg, int irq) static int stm32_nmi(int irq, FAR void *context) { (void)up_irq_save(); - err("PANIC!!! NMI received\n"); + _err("PANIC!!! NMI received\n"); PANIC(); return 0; } @@ -197,7 +197,7 @@ static int stm32_nmi(int irq, FAR void *context) static int stm32_busfault(int irq, FAR void *context) { (void)up_irq_save(); - err("PANIC!!! Bus fault received: %08x\n", getreg32(NVIC_CFAULTS)); + _err("PANIC!!! Bus fault received: %08x\n", getreg32(NVIC_CFAULTS)); PANIC(); return 0; } @@ -205,7 +205,7 @@ static int stm32_busfault(int irq, FAR void *context) static int stm32_usagefault(int irq, FAR void *context) { (void)up_irq_save(); - err("PANIC!!! Usage fault received: %08x\n", getreg32(NVIC_CFAULTS)); + _err("PANIC!!! Usage fault received: %08x\n", getreg32(NVIC_CFAULTS)); PANIC(); return 0; } @@ -213,7 +213,7 @@ static int stm32_usagefault(int irq, FAR void *context) static int stm32_pendsv(int irq, FAR void *context) { (void)up_irq_save(); - err("PANIC!!! PendSV received\n"); + _err("PANIC!!! PendSV received\n"); PANIC(); return 0; } @@ -221,7 +221,7 @@ static int stm32_pendsv(int irq, FAR void *context) static int stm32_errmonitor(int irq, FAR void *context) { (void)up_irq_save(); - err("PANIC!!! Debug Monitor received\n"); + _err("PANIC!!! Debug Monitor received\n"); PANIC(); return 0; } @@ -229,7 +229,7 @@ static int stm32_errmonitor(int irq, FAR void *context) static int stm32_reserved(int irq, FAR void *context) { (void)up_irq_save(); - err("PANIC!!! Reserved interrupt\n"); + _err("PANIC!!! Reserved interrupt\n"); PANIC(); return 0; } diff --git a/arch/arm/src/stm32l4/stm32l4_idle.c b/arch/arm/src/stm32l4/stm32l4_idle.c index 00cceb1470..f17bd4d75e 100644 --- a/arch/arm/src/stm32l4/stm32l4_idle.c +++ b/arch/arm/src/stm32l4/stm32l4_idle.c @@ -101,7 +101,7 @@ static void up_idlepm(void) /* Perform board-specific, state-dependent logic here */ - llinfo("newstate= %d oldstate=%d\n", newstate, oldstate); + _llinfo("newstate= %d oldstate=%d\n", newstate, oldstate); /* Then force the global state change */ diff --git a/arch/arm/src/stm32l4/stm32l4_irq.c b/arch/arm/src/stm32l4/stm32l4_irq.c index 75fec84dfd..7d5f948c81 100644 --- a/arch/arm/src/stm32l4/stm32l4_irq.c +++ b/arch/arm/src/stm32l4/stm32l4_irq.c @@ -163,7 +163,7 @@ static void stm32l4_dumpnvic(const char *msg, int irq) static int stm32l4_nmi(int irq, FAR void *context) { (void)up_irq_save(); - err("PANIC!!! NMI received\n"); + _err("PANIC!!! NMI received\n"); PANIC(); return 0; } @@ -171,7 +171,7 @@ static int stm32l4_nmi(int irq, FAR void *context) static int stm32l4_busfault(int irq, FAR void *context) { (void)up_irq_save(); - err("PANIC!!! Bus fault received: %08x\n", getreg32(NVIC_CFAULTS)); + _err("PANIC!!! Bus fault received: %08x\n", getreg32(NVIC_CFAULTS)); PANIC(); return 0; } @@ -179,7 +179,7 @@ static int stm32l4_busfault(int irq, FAR void *context) static int stm32l4_usagefault(int irq, FAR void *context) { (void)up_irq_save(); - err("PANIC!!! Usage fault received: %08x\n", getreg32(NVIC_CFAULTS)); + _err("PANIC!!! Usage fault received: %08x\n", getreg32(NVIC_CFAULTS)); PANIC(); return 0; } @@ -187,7 +187,7 @@ static int stm32l4_usagefault(int irq, FAR void *context) static int stm32l4_pendsv(int irq, FAR void *context) { (void)up_irq_save(); - err("PANIC!!! PendSV received\n"); + _err("PANIC!!! PendSV received\n"); PANIC(); return 0; } @@ -195,7 +195,7 @@ static int stm32l4_pendsv(int irq, FAR void *context) static int stm32l4_errmonitor(int irq, FAR void *context) { (void)up_irq_save(); - err("PANIC!!! Debug Monitor received\n"); + _err("PANIC!!! Debug Monitor received\n"); PANIC(); return 0; } @@ -203,7 +203,7 @@ static int stm32l4_errmonitor(int irq, FAR void *context) static int stm32l4_reserved(int irq, FAR void *context) { (void)up_irq_save(); - err("PANIC!!! Reserved interrupt\n"); + _err("PANIC!!! Reserved interrupt\n"); PANIC(); return 0; } diff --git a/arch/arm/src/stm32l4/stm32l4_rng.c b/arch/arm/src/stm32l4/stm32l4_rng.c index 2a27348bee..f9324fb6f1 100644 --- a/arch/arm/src/stm32l4/stm32l4_rng.c +++ b/arch/arm/src/stm32l4/stm32l4_rng.c @@ -107,7 +107,7 @@ static const struct file_operations g_rngops = static int stm32l4_rnginitialize(void) { - info("Initializing RNG\n"); + _info("Initializing RNG\n"); memset(&g_rngdev, 0, sizeof(struct rng_dev_s)); @@ -117,7 +117,7 @@ static int stm32l4_rnginitialize(void) { /* We could not attach the ISR to the interrupt */ - info("Could not attach IRQ.\n"); + _info("Could not attach IRQ.\n"); return -EAGAIN; } diff --git a/arch/arm/src/tiva/tiva_irq.c b/arch/arm/src/tiva/tiva_irq.c index d7152a3eed..8f95e071d9 100644 --- a/arch/arm/src/tiva/tiva_irq.c +++ b/arch/arm/src/tiva/tiva_irq.c @@ -199,7 +199,7 @@ static void tiva_dumpnvic(const char *msg, int irq) static int tiva_nmi(int irq, FAR void *context) { (void)up_irq_save(); - err("PANIC!!! NMI received\n"); + _err("PANIC!!! NMI received\n"); PANIC(); return 0; } @@ -207,7 +207,7 @@ static int tiva_nmi(int irq, FAR void *context) static int tiva_busfault(int irq, FAR void *context) { (void)up_irq_save(); - err("PANIC!!! Bus fault recived\n"); + _err("PANIC!!! Bus fault recived\n"); PANIC(); return 0; } @@ -215,7 +215,7 @@ static int tiva_busfault(int irq, FAR void *context) static int tiva_usagefault(int irq, FAR void *context) { (void)up_irq_save(); - err("PANIC!!! Usage fault received\n"); + _err("PANIC!!! Usage fault received\n"); PANIC(); return 0; } @@ -223,7 +223,7 @@ static int tiva_usagefault(int irq, FAR void *context) static int tiva_pendsv(int irq, FAR void *context) { (void)up_irq_save(); - err("PANIC!!! PendSV received\n"); + _err("PANIC!!! PendSV received\n"); PANIC(); return 0; } @@ -231,7 +231,7 @@ static int tiva_pendsv(int irq, FAR void *context) static int tiva_errmonitor(int irq, FAR void *context) { (void)up_irq_save(); - err("PANIC!!! Debug Monitor received\n"); + _err("PANIC!!! Debug Monitor received\n"); PANIC(); return 0; } @@ -239,7 +239,7 @@ static int tiva_errmonitor(int irq, FAR void *context) static int tiva_reserved(int irq, FAR void *context) { (void)up_irq_save(); - err("PANIC!!! Reserved interrupt\n"); + _err("PANIC!!! Reserved interrupt\n"); PANIC(); return 0; } diff --git a/arch/arm/src/tiva/tm4c_ethernet.c b/arch/arm/src/tiva/tm4c_ethernet.c index 5860a55b87..575f6b2edc 100644 --- a/arch/arm/src/tiva/tm4c_ethernet.c +++ b/arch/arm/src/tiva/tm4c_ethernet.c @@ -808,7 +808,7 @@ static uint32_t tiva_getreg(uint32_t addr) { if (count == 4) { - llinfo("...\n"); + _llinfo("...\n"); } return val; @@ -825,7 +825,7 @@ static uint32_t tiva_getreg(uint32_t addr) { /* Yes.. then show how many times the value repeated */ - llinfo("[repeats %d more times]\n", count-3); + _llinfo("[repeats %d more times]\n", count-3); } /* Save the new address, value, and count */ @@ -837,7 +837,7 @@ static uint32_t tiva_getreg(uint32_t addr) /* Show the register value read */ - llinfo("%08x->%08x\n", addr, val); + _llinfo("%08x->%08x\n", addr, val); return val; } #endif @@ -864,7 +864,7 @@ static void tiva_putreg(uint32_t val, uint32_t addr) { /* Show the register value being written */ - llinfo("%08x<-%08x\n", addr, val); + _llinfo("%08x<-%08x\n", addr, val); /* Write the value */ diff --git a/arch/arm/src/tms570/tms570_esm.c b/arch/arm/src/tms570/tms570_esm.c index 601fefa86d..e6eec90c5f 100644 --- a/arch/arm/src/tms570/tms570_esm.c +++ b/arch/arm/src/tms570/tms570_esm.c @@ -155,7 +155,7 @@ int tms570_esm_interrupt(int irq, void *context) /* Crash -- possibly showing diagnostic debug information. */ - llerr("ERROR: ESM Interrupt. PC: %08x\n", CURRENT_REGS[REG_PC]); + _llerr("ERROR: ESM Interrupt. PC: %08x\n", CURRENT_REGS[REG_PC]); PANIC(); return OK; /* To keep the compiler happy */ } diff --git a/arch/arm/src/tms570/tms570_gio.c b/arch/arm/src/tms570/tms570_gio.c index 1e4b156c10..3a771ff1d8 100644 --- a/arch/arm/src/tms570/tms570_gio.c +++ b/arch/arm/src/tms570/tms570_gio.c @@ -296,7 +296,7 @@ int tms570_dumpgio(uint32_t pinset, const char *msg) uintptr_t base; unsigned int port; - llinfo("GIO%c pinset: %08x base: %08x -- %s\n", + _llinfo("GIO%c pinset: %08x base: %08x -- %s\n", g_portchar[port], pinset, base, msg); /* Get the base address associated with the GIO port */ @@ -310,19 +310,19 @@ int tms570_dumpgio(uint32_t pinset, const char *msg) /* Show global GIO registers */ - llinfo(" GCR0: %08x INTDET: %08x POL: %08x ENA: %08x\n", + _llinfo(" GCR0: %08x INTDET: %08x POL: %08x ENA: %08x\n", getreg32(TMS570_GIO_GCR0), getreg32(TMS570_GIO_INTDET), getreg32(TMS570_GIO_POL), getreg32(TMS570_GIO_ENASET)); - llinfo(" LVL: %08x FLG: %08x EMU1: %08x EMU2: %08x\n", + _llinfo(" LVL: %08x FLG: %08x EMU1: %08x EMU2: %08x\n", getreg32(TMS570_GIO_LVLSET), getreg32(TMS570_GIO_FLG), getreg32(TMS570_GIO_EMU1), getreg32(TMS570_GIO_EMU2)); /* Port specific registers */ - llinfo(" DIR: %08x DIN: %08x DOUT: %08x PDR: %08x\n", + _llinfo(" DIR: %08x DIN: %08x DOUT: %08x PDR: %08x\n", getreg32(base + TMS570_GIO_DIR_OFFSET), getreg32(base + TMS570_GIO_DIN_OFFSET), getreg32(base + TMS570_GIO_DOUT_OFFSET), getreg32(base + TMS570_GIO_PDR_OFFSET)); - llinfo(" PULDIS: %08x PSL: %08x\n", + _llinfo(" PULDIS: %08x PSL: %08x\n", getreg32(base + TMS570_GIO_PULDIS_OFFSET), getreg32(base + TMS570_GIO_PSL_OFFSET)); leave_critical_section(flags); diff --git a/arch/avr/src/at32uc3/at32uc3_gpioirq.c b/arch/avr/src/at32uc3/at32uc3_gpioirq.c index 0972429bae..a62dc41aa6 100644 --- a/arch/avr/src/at32uc3/at32uc3_gpioirq.c +++ b/arch/avr/src/at32uc3/at32uc3_gpioirq.c @@ -228,7 +228,7 @@ static void gpio_porthandler(uint32_t regbase, int irqbase, uint32_t irqset, voi } else { - llerr("ERROR: No handler: pin=%d ifr=%08x irqset=%08x", + _llerr("ERROR: No handler: pin=%d ifr=%08x irqset=%08x", pin, ifr, irqset); } } @@ -247,7 +247,7 @@ static void gpio_porthandler(uint32_t regbase, int irqbase, uint32_t irqset, voi putreg32(bit, regbase + AVR32_GPIO_IFRC_OFFSET); ifr &= ~bit; - llwarn("WARNING: IRQ on unconfigured pin: pin=%d ifr=%08x irqset=%08x", + _llwarn("WARNING: IRQ on unconfigured pin: pin=%d ifr=%08x irqset=%08x", pin, ifr, irqset); } } diff --git a/arch/avr/src/at32uc3/at32uc3_irq.c b/arch/avr/src/at32uc3/at32uc3_irq.c index f6964b7404..c552f462a9 100644 --- a/arch/avr/src/at32uc3/at32uc3_irq.c +++ b/arch/avr/src/at32uc3/at32uc3_irq.c @@ -321,11 +321,11 @@ unsigned int avr32_intirqno(unsigned int level) mask <<= 1; } - llerr("ERROR: Spurious interrupt: group=%d IRR=%08x\n", group, irr); + _llerr("ERROR: Spurious interrupt: group=%d IRR=%08x\n", group, irr); return -ENODEV; } - llerr("ERROR: Bad group: %d\n", group); + _llerr("ERROR: Bad group: %d\n", group); return AVR32_IRQ_BADVECTOR; } diff --git a/arch/avr/src/common/up_initialize.c b/arch/avr/src/common/up_initialize.c index 8f58cdcf6e..b79f95876c 100644 --- a/arch/avr/src/common/up_initialize.c +++ b/arch/avr/src/common/up_initialize.c @@ -125,13 +125,13 @@ static void up_calibratedelay(void) { int i; - llwarn("Beginning 100s delay\n"); + _llwarn("Beginning 100s delay\n"); for (i = 0; i < 100; i++) { up_mdelay(1000); } - llwarn("End 100s delay\n"); + _llwarn("End 100s delay\n"); } #else # define up_calibratedelay() diff --git a/arch/hc/src/common/up_initialize.c b/arch/hc/src/common/up_initialize.c index a358d29e9b..47c8abfe94 100644 --- a/arch/hc/src/common/up_initialize.c +++ b/arch/hc/src/common/up_initialize.c @@ -74,13 +74,13 @@ static void up_calibratedelay(void) { int i; - llwarn("Beginning 100s delay\n"); + _llwarn("Beginning 100s delay\n"); for (i = 0; i < 100; i++) { up_mdelay(1000); } - llwarn("End 100s delay\n"); + _llwarn("End 100s delay\n"); } #else # define up_calibratedelay() diff --git a/arch/mips/src/common/up_initialize.c b/arch/mips/src/common/up_initialize.c index 2529020267..dbb950424b 100644 --- a/arch/mips/src/common/up_initialize.c +++ b/arch/mips/src/common/up_initialize.c @@ -76,13 +76,13 @@ static void up_calibratedelay(void) { int i; - llwarn("Beginning 100s delay\n"); + _llwarn("Beginning 100s delay\n"); for (i = 0; i < 100; i++) { up_mdelay(1000); } - llwarn("End 100s delay\n"); + _llwarn("End 100s delay\n"); } #else # define up_calibratedelay() diff --git a/arch/mips/src/pic32mx/pic32mx-serial.c b/arch/mips/src/pic32mx/pic32mx-serial.c index 20a50bf2bb..7617a8f3a0 100644 --- a/arch/mips/src/pic32mx/pic32mx-serial.c +++ b/arch/mips/src/pic32mx/pic32mx-serial.c @@ -500,7 +500,7 @@ static int up_interrupt(int irq, void *context) /* Clear the pending error interrupt */ up_clrpend_irq(priv->irqe); - llerr("ERROR: interrupt STA: %08x\n", + _llerr("ERROR: interrupt STA: %08x\n", up_serialin(priv, PIC32MX_UART_STA_OFFSET)); handled = true; } diff --git a/arch/mips/src/pic32mx/pic32mx-spi.c b/arch/mips/src/pic32mx/pic32mx-spi.c index dddadf2c02..c56ff271c3 100644 --- a/arch/mips/src/pic32mx/pic32mx-spi.c +++ b/arch/mips/src/pic32mx/pic32mx-spi.c @@ -315,7 +315,7 @@ static uint32_t spi_getreg(FAR struct pic32mx_dev_s *priv, unsigned int offset) { if (count == 4) { - llinfo("...\n"); + _llinfo("...\n"); } return value; } @@ -331,7 +331,7 @@ static uint32_t spi_getreg(FAR struct pic32mx_dev_s *priv, unsigned int offset) { /* Yes.. then show how many times the value repeated */ - llinfo("[repeats %d more times]\n", count-3); + _llinfo("[repeats %d more times]\n", count-3); } /* Save the new address, value, and count */ @@ -343,7 +343,7 @@ static uint32_t spi_getreg(FAR struct pic32mx_dev_s *priv, unsigned int offset) /* Show the register value read */ - llinfo("%08x->%08x\n", addr, value); + _llinfo("%08x->%08x\n", addr, value); return value; } #else @@ -381,7 +381,7 @@ static void spi_putreg(FAR struct pic32mx_dev_s *priv, unsigned int offset, /* Show the register value being written */ - llinfo("%08x<-%08x\n", addr, value); + _llinfo("%08x<-%08x\n", addr, value); /* Then do the write */ diff --git a/arch/mips/src/pic32mx/pic32mx-usbdev.c b/arch/mips/src/pic32mx/pic32mx-usbdev.c index 0c43382e1c..85d2705c70 100644 --- a/arch/mips/src/pic32mx/pic32mx-usbdev.c +++ b/arch/mips/src/pic32mx/pic32mx-usbdev.c @@ -280,9 +280,9 @@ # undef CONFIG_PIC32MX_USBDEV_BDTDEBUG # define CONFIG_PIC32MX_USBDEV_BDTDEBUG 1 -# define regerr llerr -# define regwarn llwarn -# define reginfo llinfo +# define regerr _llerr +# define regwarn _llwarn +# define reginfo _llinfo #else @@ -298,9 +298,9 @@ #ifdef CONFIG_PIC32MX_USBDEV_BDTDEBUG -# define bdterr llerr -# define bdtwarn llwarn -# define bdtinfo llinfo +# define bdterr _llerr +# define bdtwarn _llwarn +# define bdtinfo _llinfo #else diff --git a/arch/mips/src/pic32mz/pic32mz-serial.c b/arch/mips/src/pic32mz/pic32mz-serial.c index c9b56f3ff4..e14ab4472f 100644 --- a/arch/mips/src/pic32mz/pic32mz-serial.c +++ b/arch/mips/src/pic32mz/pic32mz-serial.c @@ -758,7 +758,7 @@ static int up_interrupt(struct uart_dev_s *dev) /* Clear the pending error interrupt */ up_clrpend_irq(priv->irqe); - llerr("ERROR: interrupt STA: %08x\n", + _llerr("ERROR: interrupt STA: %08x\n", up_serialin(priv, PIC32MZ_UART_STA_OFFSET)); handled = true; } diff --git a/arch/mips/src/pic32mz/pic32mz-spi.c b/arch/mips/src/pic32mz/pic32mz-spi.c index 5297a370b8..b2ddd66d7c 100644 --- a/arch/mips/src/pic32mz/pic32mz-spi.c +++ b/arch/mips/src/pic32mz/pic32mz-spi.c @@ -482,7 +482,7 @@ static bool spi_checkreg(struct pic32mz_dev_s *priv, uintptr_t regaddr, { /* Yes... show how many times we did it */ - llinfo("...[Repeats %d times]...\n", priv->ntimes); + _llinfo("...[Repeats %d times]...\n", priv->ntimes); } /* Save information about the new access */ @@ -532,7 +532,7 @@ static uint32_t spi_getreg(FAR struct pic32mz_dev_s *priv, { /* Yes.. */ - llinfo("%08lx->%08lx\n", + _llinfo("%08lx->%08lx\n", (unsigned long)regaddr, (unsigned long)regval); } @@ -574,7 +574,7 @@ static void spi_putaddr(FAR struct pic32mz_dev_s *priv, uintptr_t regaddr, { /* Yes.. */ - llinfo("%08lx<-%08lx\n", + _llinfo("%08lx<-%08lx\n", (unsigned long)regaddr, (unsigned long)regval); } diff --git a/arch/rgmp/src/bridge.c b/arch/rgmp/src/bridge.c index 46f45a8f59..320019ba9f 100644 --- a/arch/rgmp/src/bridge.c +++ b/arch/rgmp/src/bridge.c @@ -98,7 +98,7 @@ static const struct file_operations up_bridge_fops = int rtos_bridge_init(struct rgmp_bridge *b) { - int err; + int errcode; struct bridge *bridge; char path[30] = {'/', 'd', 'e', 'v', '/'}; @@ -106,10 +106,10 @@ int rtos_bridge_init(struct rgmp_bridge *b) goto err0; bridge->b = b; - if ((err = sem_init(&bridge->rd_lock, 0, 1)) == ERROR) + if ((errcode = sem_init(&bridge->rd_lock, 0, 1)) == ERROR) goto err1; - if ((err = sem_init(&bridge->wr_lock, 0, 1)) == ERROR) + if ((errcode = sem_init(&bridge->wr_lock, 0, 1)) == ERROR) goto err1; // make rgmp_bridge0 to be the console @@ -119,7 +119,7 @@ int rtos_bridge_init(struct rgmp_bridge *b) else strlcpy(path + 5, b->vdev->name, 25); - if ((err = register_driver(path, &up_bridge_fops, 0666, bridge)) == ERROR) + if ((errcode = register_driver(path, &up_bridge_fops, 0666, bridge)) == ERROR) { cprintf("NuttX: register bridge %s fail\n", b->vdev->name); goto err1; diff --git a/arch/rgmp/src/nuttx.c b/arch/rgmp/src/nuttx.c index 0832e8f9ec..4a274264d7 100644 --- a/arch/rgmp/src/nuttx.c +++ b/arch/rgmp/src/nuttx.c @@ -258,7 +258,7 @@ void up_block_task(struct tcb_s *tcb, tstate_t task_state) if ((tcb->task_state < FIRST_READY_TO_RUN_STATE) || (tcb->task_state > LAST_READY_TO_RUN_STATE)) { - warn("%s: task sched error\n", __func__); + _warn("%s: task sched error\n", __func__); return; } else @@ -304,7 +304,7 @@ void up_block_task(struct tcb_s *tcb, tstate_t task_state) if (g_pendingtasks.head) { - warn("Disable preemption failed for task block itself\n"); + _warn("Disable preemption failed for task block itself\n"); sched_mergepending(); } @@ -353,7 +353,7 @@ void up_unblock_task(struct tcb_s *tcb) if ((tcb->task_state < FIRST_BLOCKED_STATE) || (tcb->task_state > LAST_BLOCKED_STATE)) { - warn("%s: task sched error\n", __func__); + _warn("%s: task sched error\n", __func__); return; } else @@ -453,7 +453,7 @@ void up_reprioritize_rtr(struct tcb_s *tcb, uint8_t priority) #endif ) { - warn("%s: task sched error\n", __func__); + _warn("%s: task sched error\n", __func__); return; } else @@ -496,7 +496,7 @@ void up_reprioritize_rtr(struct tcb_s *tcb, uint8_t priority) if (g_pendingtasks.head) { - warn("Disable preemption failed for reprioritize task\n"); + _warn("Disable preemption failed for reprioritize task\n"); sched_mergepending(); } diff --git a/arch/rgmp/src/x86/com.c b/arch/rgmp/src/x86/com.c index 495aa4b692..8c8d076cc0 100644 --- a/arch/rgmp/src/x86/com.c +++ b/arch/rgmp/src/x86/com.c @@ -258,7 +258,7 @@ static int up_setup(struct uart_dev_s *dev) inb(base+COM_RX); if (inb(base+COM_LSR) == 0xff) { - err("ERROR: COM %d does not exist\n", base); + _err("ERROR: COM %d does not exist\n", base); return -1; } @@ -591,14 +591,14 @@ void up_serialinit(void) dev = up_alloc_com(COM1, 4); if (dev == NULL) { - err("ERROR: alloc com1 fail\n"); + _err("ERROR: alloc com1 fail\n"); } else { errcode = uart_register("/dev/ttyS0", dev); if (errcode) { - err("ERROR: register com1 fail\n"); + _err("ERROR: register com1 fail\n"); } } #endif @@ -606,14 +606,14 @@ void up_serialinit(void) dev = up_alloc_com(COM2, 3); if (dev == NULL) { - err("ERROR: alloc com2 fail\n"); + _err("ERROR: alloc com2 fail\n"); } else { errcode = uart_register("/dev/ttyS1", dev); if (errcode) { - err("ERROR: register com2 fail\n"); + _err("ERROR: register com2 fail\n"); } } #endif @@ -621,14 +621,14 @@ void up_serialinit(void) dev = up_alloc_com(COM3, 4); if (dev == NULL) { - err("ERROR: alloc com3 fail\n"); + _err("ERROR: alloc com3 fail\n"); } else { errcode = uart_register("/dev/ttyS2", dev); if (errcode) { - err("ERROR: register com3 fail\n"); + _err("ERROR: register com3 fail\n"); } } #endif @@ -636,14 +636,14 @@ void up_serialinit(void) dev = up_alloc_com(COM4, 3); if (dev == NULL) { - err("ERROR: alloc com4 fail\n"); + _err("ERROR: alloc com4 fail\n"); } else { errcode = uart_register("/dev/ttyS3", dev); if (errcode) { - err("ERROR: register com4 fail\n"); + _err("ERROR: register com4 fail\n"); } } #endif diff --git a/arch/sh/src/m16c/m16c_serial.c b/arch/sh/src/m16c/m16c_serial.c index 34c3d9019a..4bc1f969ce 100644 --- a/arch/sh/src/m16c/m16c_serial.c +++ b/arch/sh/src/m16c/m16c_serial.c @@ -588,7 +588,7 @@ static int up_setup(struct uart_dev_s *dev) else #endif { - err("ERROR: Invalid UART #\n"); + _err("ERROR: Invalid UART #\n"); } /* Set UART transmit/receive control register 1 to enable transmit and receive */ @@ -613,7 +613,7 @@ static int up_setup(struct uart_dev_s *dev) } else { - err("ERROR: Invalid bits=%d\n", priv->bits); + _err("ERROR: Invalid bits=%d\n", priv->bits); } if (priv->parity != 0) @@ -665,7 +665,7 @@ static int up_setup(struct uart_dev_s *dev) else #endif { - err("ERROR: Invalid UART #\n"); + _err("ERROR: Invalid UART #\n"); } /* Read any data left in the RX fifo */ @@ -872,7 +872,7 @@ static void m16c_rxint(struct up_dev_s *dev, bool enable) else #endif { - err("ERROR: Invalid UART #\n"); + _err("ERROR: Invalid UART #\n"); return; } @@ -1027,7 +1027,7 @@ static void m16c_txint(struct up_dev_s *dev, bool enable) else #endif { - err("ERROR: Invalid UART #\n"); + _err("ERROR: Invalid UART #\n"); return; } diff --git a/arch/sh/src/sh1/sh1_irq.c b/arch/sh/src/sh1/sh1_irq.c index 36164ae9d1..bb59877340 100644 --- a/arch/sh/src/sh1/sh1_irq.c +++ b/arch/sh/src/sh1/sh1_irq.c @@ -95,7 +95,7 @@ void up_prioritize_irq(int irq, int priority) #ifdef CONFIG_DEBUG_FEATURES if ((unsigned) irq > NR_IRQS || (unsigned)priority > 15) { - err("ERROR: Invalid parameters\n"); + _err("ERROR: Invalid parameters\n"); return; } #endif @@ -260,7 +260,7 @@ void up_prioritize_irq(int irq, int priority) #endif default: - err("ERROR: Invalid irq=%d\n", irq); + _err("ERROR: Invalid irq=%d\n", irq); return; } diff --git a/arch/sim/src/up_framebuffer.c b/arch/sim/src/up_framebuffer.c index ff1e3629bc..1de73fd514 100644 --- a/arch/sim/src/up_framebuffer.c +++ b/arch/sim/src/up_framebuffer.c @@ -191,14 +191,14 @@ struct fb_vtable_s g_fbobject = static int up_getvideoinfo(FAR struct fb_vtable_s *vtable, FAR struct fb_videoinfo_s *vinfo) { - info("vtable=%p vinfo=%p\n", vtable, vinfo); + _info("vtable=%p vinfo=%p\n", vtable, vinfo); if (vtable && vinfo) { memcpy(vinfo, &g_videoinfo, sizeof(struct fb_videoinfo_s)); return OK; } - err("ERROR: Returning EINVAL\n"); + _err("ERROR: Returning EINVAL\n"); return -EINVAL; } @@ -209,14 +209,14 @@ static int up_getvideoinfo(FAR struct fb_vtable_s *vtable, static int up_getplaneinfo(FAR struct fb_vtable_s *vtable, int planeno, FAR struct fb_planeinfo_s *pinfo) { - info("vtable=%p planeno=%d pinfo=%p\n", vtable, planeno, pinfo); + _info("vtable=%p planeno=%d pinfo=%p\n", vtable, planeno, pinfo); if (vtable && planeno == 0 && pinfo) { memcpy(pinfo, &g_planeinfo, sizeof(struct fb_planeinfo_s)); return OK; } - err("ERROR: Returning EINVAL\n"); + _err("ERROR: Returning EINVAL\n"); return -EINVAL; } @@ -230,7 +230,7 @@ static int up_getcmap(FAR struct fb_vtable_s *vtable, FAR struct fb_cmap_s *cmap int len; int i; - info("vtable=%p cmap=%p len=%d\n", vtable, cmap, cmap->len); + _info("vtable=%p cmap=%p len=%d\n", vtable, cmap, cmap->len); if (vtable && cmap) { for (i = cmap->first, len = 0; i < 256 && len < cmap->len; i++, len++) @@ -247,7 +247,7 @@ static int up_getcmap(FAR struct fb_vtable_s *vtable, FAR struct fb_cmap_s *cmap return OK; } - err("ERROR: Returning EINVAL\n"); + _err("ERROR: Returning EINVAL\n"); return -EINVAL; } #endif @@ -262,13 +262,13 @@ static int up_putcmap(FAR struct fb_vtable_s *vtable, FAR const struct fb_cmap_s #ifdef CONFIG_SIM_X11FB return up_x11cmap(cmap->first, cmap->len, cmap->red, cmap->green, cmap->blue, NULL); #else - info("vtable=%p cmap=%p len=%d\n", vtable, cmap, cmap->len); + _info("vtable=%p cmap=%p len=%d\n", vtable, cmap, cmap->len); if (vtable && cmap) { return OK; } - err("ERROR: Returning EINVAL\n"); + _err("ERROR: Returning EINVAL\n"); return -EINVAL; #endif } @@ -282,24 +282,24 @@ static int up_putcmap(FAR struct fb_vtable_s *vtable, FAR const struct fb_cmap_s static int up_getcursor(FAR struct fb_vtable_s *vtable, FAR struct fb_cursorattrib_s *attrib) { - info("vtable=%p attrib=%p\n", vtable, attrib); + _info("vtable=%p attrib=%p\n", vtable, attrib); if (vtable && attrib) { #ifdef CONFIG_FB_HWCURSORIMAGE attrib->fmt = FB_FMT; #endif - info("pos: (x=%d, y=%d)\n", g_cpos.x, g_cpos.y); + _info("pos: (x=%d, y=%d)\n", g_cpos.x, g_cpos.y); attrib->pos = g_cpos; #ifdef CONFIG_FB_HWCURSORSIZE attrib->mxsize.h = CONFIG_SIM_FBHEIGHT; attrib->mxsize.w = CONFIG_SIM_FBWIDTH; - info("size: (h=%d, w=%d)\n", g_csize.h, g_csize.w); + _info("size: (h=%d, w=%d)\n", g_csize.h, g_csize.w); attrib->size = g_csize; #endif return OK; } - err("ERROR: Returning EINVAL\n"); + _err("ERROR: Returning EINVAL\n"); return -EINVAL; } #endif @@ -312,33 +312,33 @@ static int up_getcursor(FAR struct fb_vtable_s *vtable, static int up_setcursor(FAR struct fb_vtable_s *vtable, FAR struct fb_setcursor_s *setttings) { - info("vtable=%p setttings=%p\n", vtable, setttings); + _info("vtable=%p setttings=%p\n", vtable, setttings); if (vtable && setttings) { - info("flags: %02x\n", settings->flags); + _info("flags: %02x\n", settings->flags); if ((flags & FB_CUR_SETPOSITION) != 0) { g_cpos = settings->pos; - info("pos: (h:%d, w:%d)\n", g_cpos.x, g_cpos.y); + _info("pos: (h:%d, w:%d)\n", g_cpos.x, g_cpos.y); } #ifdef CONFIG_FB_HWCURSORSIZE if ((flags & FB_CUR_SETSIZE) != 0) { g_csize = settings->size; - info("size: (h:%d, w:%d)\n", g_csize.h, g_csize.w); + _info("size: (h:%d, w:%d)\n", g_csize.h, g_csize.w); } #endif #ifdef CONFIG_FB_HWCURSORIMAGE if ((flags & FB_CUR_SETIMAGE) != 0) { - info("image: (h:%d, w:%d) @ %p\n", + _info("image: (h:%d, w:%d) @ %p\n", settings->img.height, settings->img.width, settings->img.image); } #endif return OK; } - err("ERROR: Returning EINVAL\n"); + _err("ERROR: Returning EINVAL\n"); return -EINVAL; } #endif diff --git a/arch/x86/src/common/up_initialize.c b/arch/x86/src/common/up_initialize.c index ff68a14fc2..15197e93a5 100644 --- a/arch/x86/src/common/up_initialize.c +++ b/arch/x86/src/common/up_initialize.c @@ -76,13 +76,13 @@ static void up_calibratedelay(void) { int i; - llwarn("Beginning 100s delay\n"); + _llwarn("Beginning 100s delay\n"); for (i = 0; i < 100; i++) { up_mdelay(1000); } - llwarn("End 100s delay\n"); + _llwarn("End 100s delay\n"); } #else # define up_calibratedelay() diff --git a/arch/z16/src/common/up_initialize.c b/arch/z16/src/common/up_initialize.c index a832942f19..853ae0ce7a 100644 --- a/arch/z16/src/common/up_initialize.c +++ b/arch/z16/src/common/up_initialize.c @@ -87,13 +87,13 @@ static void up_calibratedelay(void) { int i; - llwarn("Beginning 100s delay\n"); + _llwarn("Beginning 100s delay\n"); for (i = 0; i < 100; i++) { up_mdelay(1000); } - llwarn("End 100s delay\n"); + _llwarn("End 100s delay\n"); } #else # define up_calibratedelay() diff --git a/arch/z16/src/common/up_stackdump.c b/arch/z16/src/common/up_stackdump.c index 4b439b8d87..35bc6d4979 100644 --- a/arch/z16/src/common/up_stackdump.c +++ b/arch/z16/src/common/up_stackdump.c @@ -73,7 +73,7 @@ static void up_stackdump(void) if (sp >= stack_base || sp < stack_base - stack_size) { - llerr("ERROR: Stack pointer is not within allocated stack\n"); + _llerr("ERROR: Stack pointer is not within allocated stack\n"); return; } else diff --git a/arch/z80/src/common/up_blocktask.c b/arch/z80/src/common/up_blocktask.c index 3ce49030af..a4aa7b8ed5 100644 --- a/arch/z80/src/common/up_blocktask.c +++ b/arch/z80/src/common/up_blocktask.c @@ -85,7 +85,7 @@ void up_block_task(FAR struct tcb_s *tcb, tstate_t task_state) ASSERT((tcb->task_state >= FIRST_READY_TO_RUN_STATE) && (tcb->task_state <= LAST_READY_TO_RUN_STATE)); - /* info("Blocking TCB=%p\n", tcb); */ + /* _info("Blocking TCB=%p\n", tcb); */ /* Remove the tcb task from the ready-to-run list. If we * are blocking the task at the head of the task list (the diff --git a/arch/z80/src/common/up_exit.c b/arch/z80/src/common/up_exit.c index ac534d7222..a5e9832133 100644 --- a/arch/z80/src/common/up_exit.c +++ b/arch/z80/src/common/up_exit.c @@ -88,8 +88,8 @@ static void _up_dumponexit(FAR struct tcb_s *tcb, FAR void *arg) int i; #endif - llinfo(" TCB=%p name=%s\n", tcb, tcb->argv[0]); - llinfo(" priority=%d state=%d\n", tcb->sched_priority, tcb->task_state); + _llinfo(" TCB=%p name=%s\n", tcb, tcb->argv[0]); + _llinfo(" priority=%d state=%d\n", tcb->sched_priority, tcb->task_state); #if CONFIG_NFILE_DESCRIPTORS > 0 filelist = tcb->group->tg_filelist; @@ -98,7 +98,7 @@ static void _up_dumponexit(FAR struct tcb_s *tcb, FAR void *arg) struct inode *inode = filelist->fl_files[i].f_inode; if (inode) { - llinfo(" fd=%d refcount=%d\n", + _llinfo(" fd=%d refcount=%d\n", i, inode->i_crefs); } } @@ -112,11 +112,11 @@ static void _up_dumponexit(FAR struct tcb_s *tcb, FAR void *arg) if (filep->fs_fd >= 0) { #if CONFIG_STDIO_BUFFER_SIZE > 0 - llinfo(" fd=%d nbytes=%d\n", + _llinfo(" fd=%d nbytes=%d\n", filep->fs_fd, filep->fs_bufpos - filep->fs_bufstart); #else - llinfo(" fd=%d\n", filep->fs_fd); + _llinfo(" fd=%d\n", filep->fs_fd); #endif } } @@ -152,7 +152,7 @@ void _exit(int status) sllinfo("TCB=%p exiting\n", tcb); #if defined(CONFIG_DUMP_ON_EXIT) && defined(CONFIG_DEBUG_FEATURES) - llinfo("Other tasks:\n"); + _llinfo("Other tasks:\n"); sched_foreach(_up_dumponexit, NULL); #endif diff --git a/arch/z80/src/common/up_initialize.c b/arch/z80/src/common/up_initialize.c index f631238c46..b773d95892 100644 --- a/arch/z80/src/common/up_initialize.c +++ b/arch/z80/src/common/up_initialize.c @@ -75,13 +75,13 @@ static void up_calibratedelay(void) { int i; - llwarn("Beginning 100s delay\n"); + _llwarn("Beginning 100s delay\n"); for (i = 0; i < 100; i++) { up_mdelay(1000); } - llwarn("End 100s delay\n"); + _llwarn("End 100s delay\n"); } #else # define up_calibratedelay() diff --git a/arch/z80/src/common/up_unblocktask.c b/arch/z80/src/common/up_unblocktask.c index 123881386e..3539ef404d 100644 --- a/arch/z80/src/common/up_unblocktask.c +++ b/arch/z80/src/common/up_unblocktask.c @@ -81,7 +81,7 @@ void up_unblock_task(FAR struct tcb_s *tcb) ASSERT((tcb->task_state >= FIRST_BLOCKED_STATE) && (tcb->task_state <= LAST_BLOCKED_STATE)); - /* info("Unblocking TCB=%p\n", tcb); */ + /* _info("Unblocking TCB=%p\n", tcb); */ /* Remove the task from the blocked task list */ diff --git a/arch/z80/src/ez80/ez80_i2c.c b/arch/z80/src/ez80/ez80_i2c.c index 04c45c3c4c..0e4bdb1b28 100644 --- a/arch/z80/src/ez80/ez80_i2c.c +++ b/arch/z80/src/ez80/ez80_i2c.c @@ -404,7 +404,7 @@ static int ez80_i2c_sendaddr(struct ez80_i2cdev_s *priv, uint8_t readbit) { /* This error should never occur */ - err("ERROR: Bad START status: %02x\n", sr); + _err("ERROR: Bad START status: %02x\n", sr); ez80_i2c_clriflg(); return -EIO; } @@ -426,7 +426,7 @@ static int ez80_i2c_sendaddr(struct ez80_i2cdev_s *priv, uint8_t readbit) sr = ez80_i2c_waitiflg(); if (sr != I2C_SR_MADDRWRACK && sr != I2C_SR_MADDRWR) { - err("ERROR: Bad ADDR8 status: %02x\n", sr); + _err("ERROR: Bad ADDR8 status: %02x\n", sr); goto failure; } } @@ -445,7 +445,7 @@ static int ez80_i2c_sendaddr(struct ez80_i2cdev_s *priv, uint8_t readbit) sr = ez80_i2c_waitiflg(); if (sr != I2C_SR_MADDRWRACK && sr != I2C_SR_MADDRWR) { - err("ERROR: Bad ADDR10H status: %02x\n", sr); + _err("ERROR: Bad ADDR10H status: %02x\n", sr); goto failure; } @@ -459,7 +459,7 @@ static int ez80_i2c_sendaddr(struct ez80_i2cdev_s *priv, uint8_t readbit) sr = ez80_i2c_waitiflg(); if (sr != I2C_SR_MADDR2WRACK && sr != I2C_SR_MADDR2WR) { - err("ERROR: Bad ADDR10L status: %02x\n", sr); + _err("ERROR: Bad ADDR10L status: %02x\n", sr); goto failure; } } @@ -479,12 +479,12 @@ failure: * Call address received, ACK transmitted */ case I2C_SR_ARBLOST4: /* Arbitration lost in address as master, slave * address and Read bit received, ACK transmitted */ - err("ERROR: Arbitration lost: %02x\n", sr); + _err("ERROR: Arbitration lost: %02x\n", sr); ez80_i2c_clriflg(); return -EAGAIN; default: - err("ERROR: Unexpected status: %02x\n", sr); + _err("ERROR: Unexpected status: %02x\n", sr); ez80_i2c_clriflg(); return -EIO; } @@ -634,7 +634,7 @@ static int ez80_i2c_read_transfer(FAR struct ez80_i2cdev_s *priv, * this will cause the whole transfer to start over */ - err("ERROR: Arbitration lost: %02x\n", regval); + _err("ERROR: Arbitration lost: %02x\n", regval); ez80_i2c_clriflg(); break; } @@ -643,7 +643,7 @@ static int ez80_i2c_read_transfer(FAR struct ez80_i2cdev_s *priv, else { - err("ERROR: Unexpected status: %02x\n", regval); + _err("ERROR: Unexpected status: %02x\n", regval); ez80_i2c_clriflg(); return-EIO; } @@ -731,7 +731,7 @@ static int ez80_i2c_write_transfer(FAR struct ez80_i2cdev_s *priv, sr = ez80_i2c_waitiflg(); if (sr != I2C_SR_MDATAWRACK && sr != I2C_SR_MDATAWR) { - err("ERROR: Bad DATA status: %02x\n", sr); + _err("ERROR: Bad DATA status: %02x\n", sr); ez80_i2c_clriflg(); if (sr == I2C_SR_ARBLOST1) { diff --git a/arch/z80/src/z180/z180_schedulesigaction.c b/arch/z80/src/z180/z180_schedulesigaction.c index ade86734e9..c53663f783 100644 --- a/arch/z80/src/z180/z180_schedulesigaction.c +++ b/arch/z80/src/z180/z180_schedulesigaction.c @@ -125,7 +125,7 @@ void up_schedule_sigaction(FAR struct tcb_s *tcb, sig_deliver_t sigdeliver) { irqstate_t flags; - info("tcb=0x%p sigdeliver=0x%04x\n", tcb, (uint16_t)sigdeliver); + _info("tcb=0x%p sigdeliver=0x%04x\n", tcb, (uint16_t)sigdeliver); /* Make sure that interrupts are disabled */ diff --git a/arch/z80/src/z8/z8_i2c.c b/arch/z80/src/z8/z8_i2c.c index a5c597cba9..e8c2a0e046 100644 --- a/arch/z80/src/z8/z8_i2c.c +++ b/arch/z80/src/z8/z8_i2c.c @@ -236,7 +236,7 @@ static uint16_t z8_i2c_getbrg(uint32_t frequency) if (frequency > 400*1000) { - err("ERROR: Invalid inputs\n"); + _err("ERROR: Invalid inputs\n"); frequency = 400*1000; } diff --git a/arch/z80/src/z8/z8_schedulesigaction.c b/arch/z80/src/z8/z8_schedulesigaction.c index 679bccd617..338bf3096a 100644 --- a/arch/z80/src/z8/z8_schedulesigaction.c +++ b/arch/z80/src/z8/z8_schedulesigaction.c @@ -125,7 +125,7 @@ void up_schedule_sigaction(FAR struct tcb_s *tcb, sig_deliver_t sigdeliver) { irqstate_t flags; - info("tcb=0x%p sigdeliver=0x%04x\n", tcb, (uint16_t)sigdeliver); + _info("tcb=0x%p sigdeliver=0x%04x\n", tcb, (uint16_t)sigdeliver); /* Make sure that interrupts are disabled */ diff --git a/arch/z80/src/z80/z80_schedulesigaction.c b/arch/z80/src/z80/z80_schedulesigaction.c index dbb3cb5537..439808b0ca 100644 --- a/arch/z80/src/z80/z80_schedulesigaction.c +++ b/arch/z80/src/z80/z80_schedulesigaction.c @@ -125,7 +125,7 @@ void up_schedule_sigaction(FAR struct tcb_s *tcb, sig_deliver_t sigdeliver) { irqstate_t flags; - info("tcb=0x%p sigdeliver=0x%04x\n", tcb, (uint16_t)sigdeliver); + _info("tcb=0x%p sigdeliver=0x%04x\n", tcb, (uint16_t)sigdeliver); /* Make sure that interrupts are disabled */ diff --git a/audio/pcm_decode.c b/audio/pcm_decode.c index a9d739dd44..383d8ef261 100644 --- a/audio/pcm_decode.c +++ b/audio/pcm_decode.c @@ -259,23 +259,23 @@ static void pcm_callback(FAR void *arg, uint16_t reason, #ifdef CONFIG_PCM_DEBUG static void pcm_dump(FAR const struct wav_header_s *wav) { - info("Wave file header\n"); - info(" Header Chunk:\n"); - info(" Chunk ID: 0x%08x\n", wav->hdr.chunkid); - info(" Chunk Size: %u\n", wav->hdr.chunklen); - info(" Format: 0x%08x\n", wav->hdr.format); - info(" Format Chunk:\n"); - info(" Chunk ID: 0x%08x\n", wav->fmt.chunkid); - info(" Chunk Size: %u\n", wav->fmt.chunklen); - info(" Audio Format: 0x%04x\n", wav->fmt.format); - info(" Num. Channels: %d\n", wav->fmt.nchannels); - info(" Sample Rate: %u\n", wav->fmt.samprate); - info(" Byte Rate: %u\n", wav->fmt.byterate); - info(" Block Align: %d\n", wav->fmt.align); - info(" Bits Per Sample: %d\n", wav->fmt.bpsamp); - info(" Data Chunk:\n"); - info(" Chunk ID: 0x%08x\n", wav->data.chunkid); - info(" Chunk Size: %u\n", wav->data.chunklen); + _info("Wave file header\n"); + _info(" Header Chunk:\n"); + _info(" Chunk ID: 0x%08x\n", wav->hdr.chunkid); + _info(" Chunk Size: %u\n", wav->hdr.chunklen); + _info(" Format: 0x%08x\n", wav->hdr.format); + _info(" Format Chunk:\n"); + _info(" Chunk ID: 0x%08x\n", wav->fmt.chunkid); + _info(" Chunk Size: %u\n", wav->fmt.chunklen); + _info(" Audio Format: 0x%04x\n", wav->fmt.format); + _info(" Num. Channels: %d\n", wav->fmt.nchannels); + _info(" Sample Rate: %u\n", wav->fmt.samprate); + _info(" Byte Rate: %u\n", wav->fmt.byterate); + _info(" Block Align: %d\n", wav->fmt.align); + _info(" Bits Per Sample: %d\n", wav->fmt.bpsamp); + _info(" Data Chunk:\n"); + _info(" Chunk ID: 0x%08x\n", wav->data.chunkid); + _info(" Chunk Size: %u\n", wav->data.chunklen); } #endif diff --git a/binfmt/pcode.c b/binfmt/pcode.c index 3913d38ed5..8e52b75aab 100644 --- a/binfmt/pcode.c +++ b/binfmt/pcode.c @@ -366,7 +366,7 @@ static int pcode_load(struct binary_s *binp) if (memcmp(&hdr.fh_ident, FHI_POFF_MAG, 4) != 0 || hdr.fh_type != FHT_EXEC) { - err("ERROR: File is not a P-code executable: %d\n"); + _err("ERROR: File is not a P-code executable: %d\n"); ret = -ENOEXEC; goto errout_with_fd; } diff --git a/configs/compal_e99/src/ssd1783.c b/configs/compal_e99/src/ssd1783.c index 1482bb85eb..75725fc920 100644 --- a/configs/compal_e99/src/ssd1783.c +++ b/configs/compal_e99/src/ssd1783.c @@ -244,7 +244,7 @@ static void lcd_write_prepare(unsigned int x1, unsigned int x2, unsigned int y1, { END, 0x00 } }; - info("x1:%d, x2:%d, y1:%d, y2:%d\n",x1, x2,y1, y2); + _info("x1:%d, x2:%d, y1:%d, y2:%d\n",x1, x2,y1, y2); fb_ssd1783_send_cmdlist(prepare_disp_write_cmds); } diff --git a/configs/dk-tm4c129x/src/tm4c_bringup.c b/configs/dk-tm4c129x/src/tm4c_bringup.c index b6ddd0be28..e2207559b7 100644 --- a/configs/dk-tm4c129x/src/tm4c_bringup.c +++ b/configs/dk-tm4c129x/src/tm4c_bringup.c @@ -86,14 +86,14 @@ static void tm4c_i2c_register(int bus) i2c = tiva_i2cbus_initialize(bus); if (i2c == NULL) { - err("ERROR: Failed to get I2C%d interface\n", bus); + _err("ERROR: Failed to get I2C%d interface\n", bus); } else { ret = i2c_register(i2c, bus); if (ret < 0) { - err("ERROR: Failed to register I2C%d driver: %d\n", bus, ret); + _err("ERROR: Failed to register I2C%d driver: %d\n", bus, ret); tiva_i2cbus_uninitialize(i2c); } } @@ -174,7 +174,7 @@ int tm4c_bringup(void) ret = tiva_tmp100_initialize(TMP100_DEVNAME); if (ret < 0) { - err("ERROR: Failed to initialize TMP100 driver: %d\n", ret); + _err("ERROR: Failed to initialize TMP100 driver: %d\n", ret); } #endif @@ -184,7 +184,7 @@ int tm4c_bringup(void) ret = tiva_timer_configure(); if (ret < 0) { - err("ERROR: Failed to initialize timer driver: %d\n", ret); + _err("ERROR: Failed to initialize timer driver: %d\n", ret); } #endif diff --git a/configs/fire-stm32v2/src/stm32_appinit.c b/configs/fire-stm32v2/src/stm32_appinit.c index 7e894cc4af..aa962b5b77 100644 --- a/configs/fire-stm32v2/src/stm32_appinit.c +++ b/configs/fire-stm32v2/src/stm32_appinit.c @@ -147,14 +147,14 @@ static void stm32_i2c_register(int bus) i2c = stm32_i2cbus_initialize(bus); if (i2c == NULL) { - err("ERROR: Failed to get I2C%d interface\n", bus); + _err("ERROR: Failed to get I2C%d interface\n", bus); } else { ret = i2c_register(i2c, bus); if (ret < 0) { - err("ERROR: Failed to register I2C%d driver: %d\n", bus, ret); + _err("ERROR: Failed to register I2C%d driver: %d\n", bus, ret); stm32_i2cbus_uninitialize(i2c); } } diff --git a/configs/freedom-kl25z/src/kl_appinit.c b/configs/freedom-kl25z/src/kl_appinit.c index f0126fdd31..1f0d218ece 100644 --- a/configs/freedom-kl25z/src/kl_appinit.c +++ b/configs/freedom-kl25z/src/kl_appinit.c @@ -86,7 +86,7 @@ int board_app_initialize(uintptr_t arg) ret = adxl345_archinitialize(0); if (ret < 0) { - err("ERROR: adxl345_archinitialize failed: %d\n", ret); + _err("ERROR: adxl345_archinitialize failed: %d\n", ret); } #endif return OK; diff --git a/configs/hymini-stm32v/src/stm32_appinit.c b/configs/hymini-stm32v/src/stm32_appinit.c index bff825036b..725a212619 100644 --- a/configs/hymini-stm32v/src/stm32_appinit.c +++ b/configs/hymini-stm32v/src/stm32_appinit.c @@ -216,7 +216,7 @@ int board_app_initialize(uintptr_t arg) /* Use SD card detect pin to check if a card is inserted */ cd_status = !stm32_gpioread(GPIO_SD_CD); - info("Card detect : %hhu\n", cd_status); + _info("Card detect : %hhu\n", cd_status); sdio_mediachange(g_sdiodev, cd_status); #endif diff --git a/configs/lm3s6965-ek/src/lm_oled.c b/configs/lm3s6965-ek/src/lm_oled.c index de1a4a23e2..bc28b2ac79 100644 --- a/configs/lm3s6965-ek/src/lm_oled.c +++ b/configs/lm3s6965-ek/src/lm_oled.c @@ -73,7 +73,7 @@ #endif #ifdef CONFIG_LCD_RITDEBUG -# define riterr(format, ...) info(format, ##__VA_ARGS__) +# define riterr(format, ...) _info(format, ##__VA_ARGS__) # define oleddc_dumpgpio(m) tiva_dumpgpio(OLEDDC_GPIO, m) # define oledcs_dumpgpio(m) tiva_dumpgpio(OLEDCS_GPIO, m) #else diff --git a/configs/lm3s8962-ek/src/lm_oled.c b/configs/lm3s8962-ek/src/lm_oled.c index d6298212e5..0be8eaf874 100644 --- a/configs/lm3s8962-ek/src/lm_oled.c +++ b/configs/lm3s8962-ek/src/lm_oled.c @@ -72,7 +72,7 @@ #endif #ifdef CONFIG_LCD_RITDEBUG -# define riterr(format, ...) info(format, ##__VA_ARGS__) +# define riterr(format, ...) _info(format, ##__VA_ARGS__) # define oleddc_dumpgpio(m) tiva_dumpgpio(OLEDDC_GPIO, m) # define oledcs_dumpgpio(m) tiva_dumpgpio(OLEDCS_GPIO, m) #else diff --git a/configs/lpc4337-ws/src/lpc43_appinit.c b/configs/lpc4337-ws/src/lpc43_appinit.c index b9dadd3090..3ae071fe12 100644 --- a/configs/lpc4337-ws/src/lpc43_appinit.c +++ b/configs/lpc4337-ws/src/lpc43_appinit.c @@ -70,14 +70,14 @@ static void lpc43_i2c_register(int bus) i2c = lpc43_i2cbus_initialize(bus); if (i2c == NULL) { - err("ERROR: Failed to get I2C%d interface\n", bus); + _err("ERROR: Failed to get I2C%d interface\n", bus); } else { ret = i2c_register(i2c, bus); if (ret < 0) { - err("ERROR: Failed to register I2C%d driver: %d\n", bus, ret); + _err("ERROR: Failed to register I2C%d driver: %d\n", bus, ret); lpc43_i2cbus_uninitialize(i2c); } } diff --git a/configs/lpc4370-link2/src/lpc43_appinit.c b/configs/lpc4370-link2/src/lpc43_appinit.c index a2f013613d..8493fb391d 100644 --- a/configs/lpc4370-link2/src/lpc43_appinit.c +++ b/configs/lpc4370-link2/src/lpc43_appinit.c @@ -70,14 +70,14 @@ static void lpc43_i2c_register(int bus) i2c = lpc43_i2cbus_initialize(bus); if (i2c == NULL) { - err("ERROR: Failed to get I2C%d interface\n", bus); + _err("ERROR: Failed to get I2C%d interface\n", bus); } else { ret = i2c_register(i2c, bus); if (ret < 0) { - err("ERROR: Failed to register I2C%d driver: %d\n", bus, ret); + _err("ERROR: Failed to register I2C%d driver: %d\n", bus, ret); lpc43_i2cbus_uninitialize(i2c); } } diff --git a/configs/mikroe-stm32f4/src/stm32_idle.c b/configs/mikroe-stm32f4/src/stm32_idle.c index bde6c70038..54265e8a47 100644 --- a/configs/mikroe-stm32f4/src/stm32_idle.c +++ b/configs/mikroe-stm32f4/src/stm32_idle.c @@ -125,7 +125,7 @@ static void up_idlepm(void) if (newstate != oldstate) { - llinfo("newstate= %d oldstate=%d\n", newstate, oldstate); + _llinfo("newstate= %d oldstate=%d\n", newstate, oldstate); flags = enter_critical_section(); diff --git a/configs/mikroe-stm32f4/src/stm32_pwm.c b/configs/mikroe-stm32f4/src/stm32_pwm.c index a7eda30906..0710d42f8b 100644 --- a/configs/mikroe-stm32f4/src/stm32_pwm.c +++ b/configs/mikroe-stm32f4/src/stm32_pwm.c @@ -119,7 +119,7 @@ int board_pwm_setup(void) pwm = stm32_pwminitialize(STM32F4DISCOVERY_PWMTIMER); if (!pwm) { - err("ERROR: Failed to get the STM32 PWM lower half\n"); + _err("ERROR: Failed to get the STM32 PWM lower half\n"); return -ENODEV; } diff --git a/configs/mirtoo/README.txt b/configs/mirtoo/README.txt index 35fbb83c6a..d97e6d198c 100644 --- a/configs/mirtoo/README.txt +++ b/configs/mirtoo/README.txt @@ -592,7 +592,7 @@ Analog Input spi = pic32mx_spibus_initialize(2); if (!spi) { - err("ERROR: Failed to initialize SPI port 2\n"); + _err("ERROR: Failed to initialize SPI port 2\n"); return -ENODEV; } @@ -601,7 +601,7 @@ Analog Input handle = pga11x_initialize(spi); if (!handle) { - err("ERROR: Failed to bind SPI port 2 to the PGA117 driver\n"); + _err("ERROR: Failed to bind SPI port 2 to the PGA117 driver\n"); return -ENODEV; } @@ -617,7 +617,7 @@ Analog Input ret = pga11x_select(handle, &settings); if (ret < 0) { - err("ERROR: Failed to select channel 2, gain 2\n"); + _err("ERROR: Failed to select channel 2, gain 2\n"); return -EIO; } diff --git a/configs/ne64badge/src/m9s12_buttons.c b/configs/ne64badge/src/m9s12_buttons.c index ecd4c6741b..dc67eeec6a 100644 --- a/configs/ne64badge/src/m9s12_buttons.c +++ b/configs/ne64badge/src/m9s12_buttons.c @@ -61,9 +61,9 @@ #undef BUTTON_VERBOSE /* Define to enable verbose debug */ #ifdef BUTTON_DEBUG -# define btnerr llerr +# define btnerr _llerr # ifdef BUTTON_VERBOSE -# define btninfo llerr +# define btninfo _llerr # else # define btninfo(x...) # endif diff --git a/configs/sabre-6quad/src/imx_bringup.c b/configs/sabre-6quad/src/imx_bringup.c index 051da9635f..5bb167a90b 100644 --- a/configs/sabre-6quad/src/imx_bringup.c +++ b/configs/sabre-6quad/src/imx_bringup.c @@ -51,9 +51,9 @@ /* Debug ********************************************************************/ #ifdef CONFIG_BOARD_INITIALIZE -# define SYSLOG llerr +# define SYSLOG _llerr #else -# define SYSLOG err +# define SYSLOG _err #endif /**************************************************************************** diff --git a/configs/sam4e-ek/src/sam_ethernet.c b/configs/sam4e-ek/src/sam_ethernet.c index b949658ada..1e2948da57 100644 --- a/configs/sam4e-ek/src/sam_ethernet.c +++ b/configs/sam4e-ek/src/sam_ethernet.c @@ -74,12 +74,12 @@ */ #ifdef CONFIG_NETDEV_PHY_DEBUG -# define phyerr err -# define phywarn warn -# define phyinfo info -# define phyllerr llerr -# define phyllwarn llwarn -# define phyllinfo llinfo +# define phyerr _err +# define phywarn _warn +# define phyinfo _info +# define phyllerr _llerr +# define phyllwarn _llwarn +# define phyllinfo _llinfo #else # define phyerr(x...) # define phywarn(x...) diff --git a/configs/sama5d2-xult/src/sam_bringup.c b/configs/sama5d2-xult/src/sam_bringup.c index 133e3f5199..eb02652441 100644 --- a/configs/sama5d2-xult/src/sam_bringup.c +++ b/configs/sama5d2-xult/src/sam_bringup.c @@ -50,9 +50,9 @@ ****************************************************************************/ #ifdef CONFIG_BOARD_INITIALIZE -# define SYSLOG llerr +# define SYSLOG _llerr #else -# define SYSLOG err +# define SYSLOG _err #endif /**************************************************************************** diff --git a/configs/sama5d3-xplained/src/sam_ethernet.c b/configs/sama5d3-xplained/src/sam_ethernet.c index c6ef0d3f53..5f38d395b1 100644 --- a/configs/sama5d3-xplained/src/sam_ethernet.c +++ b/configs/sama5d3-xplained/src/sam_ethernet.c @@ -84,12 +84,12 @@ */ #ifdef CONFIG_NETDEV_PHY_DEBUG -# define phyerr err -# define phywarn warn -# define phyinfo info -# define phyllerr llerr -# define phyllwarn llwarn -# define phyllinfo llinfo +# define phyerr _err +# define phywarn _warn +# define phyinfo _info +# define phyllerr _llerr +# define phyllwarn _llwarn +# define phyllinfo _llinfo #else # define phyerr(x...) # define phywarn(x...) diff --git a/configs/sama5d3-xplained/src/sam_i2schar.c b/configs/sama5d3-xplained/src/sam_i2schar.c index 67d271edc6..51510b4e6e 100644 --- a/configs/sama5d3-xplained/src/sam_i2schar.c +++ b/configs/sama5d3-xplained/src/sam_i2schar.c @@ -99,7 +99,7 @@ int i2schar_devinit(void) i2s = sam_ssc_initialize(CONFIG_SAMA5D3XPLAINED_SSC_PORT); if (!i2s) { - err("ERROR: Failed to get the SAMA5 SSC/I2S driver for SSC%d\n", + _err("ERROR: Failed to get the SAMA5 SSC/I2S driver for SSC%d\n", CONFIG_SAMA5D3XPLAINED_SSC_PORT); return -ENODEV; } diff --git a/configs/sama5d3-xplained/src/sam_pwm.c b/configs/sama5d3-xplained/src/sam_pwm.c index cd78ff2338..91664c1d21 100644 --- a/configs/sama5d3-xplained/src/sam_pwm.c +++ b/configs/sama5d3-xplained/src/sam_pwm.c @@ -139,7 +139,7 @@ int board_pwm_setup(void) pwm = sam_pwminitialize(CONFIG_SAMA5D3XPLAINED_CHANNEL); if (!pwm) { - err("ERROR: Failed to get the SAMA5 PWM lower half\n"); + _err("ERROR: Failed to get the SAMA5 PWM lower half\n"); return -ENODEV; } diff --git a/configs/sama5d3x-ek/src/sam_ethernet.c b/configs/sama5d3x-ek/src/sam_ethernet.c index ec7a9a21c6..b4d0d31c0b 100644 --- a/configs/sama5d3x-ek/src/sam_ethernet.c +++ b/configs/sama5d3x-ek/src/sam_ethernet.c @@ -84,12 +84,12 @@ */ #ifdef CONFIG_NETDEV_PHY_DEBUG -# define phyerr err -# define phywarn warn -# define phyinfo info -# define phyllerr llerr -# define phyllwarn llwarn -# define phyllinfo llinfo +# define phyerr _err +# define phywarn _warn +# define phyinfo _info +# define phyllerr _llerr +# define phyllwarn _llwarn +# define phyllinfo _llinfo #else # define phyerr(x...) # define phywarn(x...) diff --git a/configs/sama5d3x-ek/src/sam_i2schar.c b/configs/sama5d3x-ek/src/sam_i2schar.c index 21a88b3743..86c06aafa7 100644 --- a/configs/sama5d3x-ek/src/sam_i2schar.c +++ b/configs/sama5d3x-ek/src/sam_i2schar.c @@ -99,7 +99,7 @@ int i2schar_devinit(void) i2s = sam_ssc_initialize(CONFIG_SAMA5D3xEK_SSC_PORT); if (!i2s) { - err("ERROR: Failed to get the SAMA5 SSC/I2S driver for SSC%d\n", + _err("ERROR: Failed to get the SAMA5 SSC/I2S driver for SSC%d\n", CONFIG_SAMA5D3xEK_SSC_PORT); return -ENODEV; } diff --git a/configs/sama5d3x-ek/src/sam_pwm.c b/configs/sama5d3x-ek/src/sam_pwm.c index 26d14ce4dc..ef90855451 100644 --- a/configs/sama5d3x-ek/src/sam_pwm.c +++ b/configs/sama5d3x-ek/src/sam_pwm.c @@ -139,7 +139,7 @@ int board_pwm_setup(void) pwm = sam_pwminitialize(CONFIG_SAMA5D3xEK_CHANNEL); if (!pwm) { - err("ERROR: Failed to get the SAMA5 PWM lower half\n"); + _err("ERROR: Failed to get the SAMA5 PWM lower half\n"); return -ENODEV; } diff --git a/configs/sama5d4-ek/src/sam_bringup.c b/configs/sama5d4-ek/src/sam_bringup.c index 489249b04a..953a40b498 100644 --- a/configs/sama5d4-ek/src/sam_bringup.c +++ b/configs/sama5d4-ek/src/sam_bringup.c @@ -72,9 +72,9 @@ /* Debug ********************************************************************/ #ifdef CONFIG_BOARD_INITIALIZE -# define SYSLOG llerr +# define SYSLOG _llerr #else -# define SYSLOG err +# define SYSLOG _err #endif /**************************************************************************** @@ -98,14 +98,14 @@ static void sam_i2c_register(int bus) i2c = sam_i2cbus_initialize(bus); if (i2c == NULL) { - err("ERROR: Failed to get I2C%d interface\n", bus); + _err("ERROR: Failed to get I2C%d interface\n", bus); } else { ret = i2c_register(i2c, bus); if (ret < 0) { - err("ERROR: Failed to register I2C%d driver: %d\n", bus, ret); + _err("ERROR: Failed to register I2C%d driver: %d\n", bus, ret); sam_i2cbus_uninitialize(i2c); } } diff --git a/configs/sama5d4-ek/src/sam_ethernet.c b/configs/sama5d4-ek/src/sam_ethernet.c index 952d60771a..30fd1e6124 100644 --- a/configs/sama5d4-ek/src/sam_ethernet.c +++ b/configs/sama5d4-ek/src/sam_ethernet.c @@ -84,12 +84,12 @@ */ #ifdef CONFIG_NETDEV_PHY_DEBUG -# define phyerr err -# define phywarn warn -# define phyinfo info -# define phyllerr llerr -# define phyllwarn llwarn -# define phyllinfo llinfo +# define phyerr _err +# define phywarn _warn +# define phyinfo _info +# define phyllerr _llerr +# define phyllwarn _llwarn +# define phyllinfo _llinfo #else # define phyerr(x...) # define phywarn(x...) diff --git a/configs/sama5d4-ek/src/sam_pmic.c b/configs/sama5d4-ek/src/sam_pmic.c index ca4edf718e..63e6967141 100644 --- a/configs/sama5d4-ek/src/sam_pmic.c +++ b/configs/sama5d4-ek/src/sam_pmic.c @@ -80,7 +80,7 @@ void sam_pmic_initialize(void) i2c = sam_i2cbus_initialize(PMIC_TWI_BUS); if (!i2c) { - err("ERROR: Failed to initialize TWI%d\n", PMIC_TWI_BUS); + _err("ERROR: Failed to initialize TWI%d\n", PMIC_TWI_BUS); } else { diff --git a/configs/sama5d4-ek/src/sam_pwm.c b/configs/sama5d4-ek/src/sam_pwm.c index 5e74de17f1..b69d8f5e5a 100644 --- a/configs/sama5d4-ek/src/sam_pwm.c +++ b/configs/sama5d4-ek/src/sam_pwm.c @@ -139,7 +139,7 @@ int board_pwm_setup(void) pwm = sam_pwminitialize(CONFIG_SAMA5D4EK_CHANNEL); if (!pwm) { - err("ERROR: Failed to get the SAMA5 PWM lower half\n"); + _err("ERROR: Failed to get the SAMA5 PWM lower half\n"); return -ENODEV; } diff --git a/configs/same70-xplained/src/sam_bringup.c b/configs/same70-xplained/src/sam_bringup.c index 23600e6f5d..814953748e 100644 --- a/configs/same70-xplained/src/sam_bringup.c +++ b/configs/same70-xplained/src/sam_bringup.c @@ -79,9 +79,9 @@ /* Debug ********************************************************************/ #ifdef CONFIG_BOARD_INITIALIZE -# define SYSLOG llerr +# define SYSLOG _llerr #else -# define SYSLOG err +# define SYSLOG _err #endif /**************************************************************************** @@ -105,14 +105,14 @@ static void sam_i2c_register(int bus) i2c = sam_i2cbus_initialize(bus); if (i2c == NULL) { - err("ERROR: Failed to get I2C%d interface\n", bus); + _err("ERROR: Failed to get I2C%d interface\n", bus); } else { ret = i2c_register(i2c, bus); if (ret < 0) { - err("ERROR: Failed to register I2C%d driver: %d\n", bus, ret); + _err("ERROR: Failed to register I2C%d driver: %d\n", bus, ret); sam_i2cbus_uninitialize(i2c); } } diff --git a/configs/same70-xplained/src/sam_ethernet.c b/configs/same70-xplained/src/sam_ethernet.c index ca56f783d6..f7a2d9113c 100644 --- a/configs/same70-xplained/src/sam_ethernet.c +++ b/configs/same70-xplained/src/sam_ethernet.c @@ -80,12 +80,12 @@ */ #ifdef CONFIG_NETDEV_PHY_DEBUG -# define phyerr err -# define phywarn warn -# define phyinfo info -# define phyllerr llerr -# define phyllwarn llwarn -# define phyllinfo llinfo +# define phyerr _err +# define phywarn _warn +# define phyinfo _info +# define phyllerr _llerr +# define phyllwarn _llwarn +# define phyllinfo _llinfo #else # define phyerr(x...) # define phywarn(x...) diff --git a/configs/samv71-xult/src/sam_bringup.c b/configs/samv71-xult/src/sam_bringup.c index 6e00088027..85dca37057 100644 --- a/configs/samv71-xult/src/sam_bringup.c +++ b/configs/samv71-xult/src/sam_bringup.c @@ -102,9 +102,9 @@ /* Debug ********************************************************************/ #ifdef CONFIG_BOARD_INITIALIZE -# define SYSLOG llerr +# define SYSLOG _llerr #else -# define SYSLOG err +# define SYSLOG _err #endif /**************************************************************************** @@ -128,14 +128,14 @@ static void sam_i2c_register(int bus) i2c = sam_i2cbus_initialize(bus); if (i2c == NULL) { - err("ERROR: Failed to get I2C%d interface\n", bus); + _err("ERROR: Failed to get I2C%d interface\n", bus); } else { ret = i2c_register(i2c, bus); if (ret < 0) { - err("ERROR: Failed to register I2C%d driver: %d\n", bus, ret); + _err("ERROR: Failed to register I2C%d driver: %d\n", bus, ret); sam_i2cbus_uninitialize(i2c); } } diff --git a/configs/samv71-xult/src/sam_ethernet.c b/configs/samv71-xult/src/sam_ethernet.c index 119ada6455..00d91314a0 100644 --- a/configs/samv71-xult/src/sam_ethernet.c +++ b/configs/samv71-xult/src/sam_ethernet.c @@ -80,12 +80,12 @@ */ #ifdef CONFIG_NETDEV_PHY_DEBUG -# define phyerr err -# define phywarn warn -# define phyinfo info -# define phyllerr llerr -# define phyllwarn llwarn -# define phyllinfo llinfo +# define phyerr _err +# define phywarn _warn +# define phyinfo _info +# define phyllerr _llerr +# define phyllwarn _llwarn +# define phyllinfo _llinfo #else # define phyerr(x...) # define phywarn(x...) diff --git a/configs/shenzhou/src/stm32_ili93xx.c b/configs/shenzhou/src/stm32_ili93xx.c index 84646484fa..553e847bd3 100644 --- a/configs/shenzhou/src/stm32_ili93xx.c +++ b/configs/shenzhou/src/stm32_ili93xx.c @@ -569,18 +569,18 @@ static struct stm32_dev_s g_lcddev = #ifdef CONFIG_LCD_REGDEBUG static void stm32_lcdshow(FAR struct stm32_lower_s *priv, FAR const char *msg) { - info("%s:\n", msg); - info(" CRTL RS: %d CS: %d RD: %d WR: %d LE: %d\n", + _info("%s:\n", msg); + _info(" CRTL RS: %d CS: %d RD: %d WR: %d LE: %d\n", getreg32(LCD_RS_READ), getreg32(LCD_CS_READ), getreg32(LCD_RD_READ), getreg32(LCD_WR_READ), getreg32(LCD_LE_READ)); - info(" DATA CR: %08x %08x\n", getreg32(LCD_CRL), getreg32(LCD_CRH)); + _info(" DATA CR: %08x %08x\n", getreg32(LCD_CRL), getreg32(LCD_CRH)); if (priv->output) { - info(" OUTPUT: %08x\n", getreg32(LCD_ODR)); + _info(" OUTPUT: %08x\n", getreg32(LCD_ODR)); } else { - info(" INPUT: %08x\n", getreg32(LCD_IDR)); + _info(" INPUT: %08x\n", getreg32(LCD_IDR)); } } #endif diff --git a/configs/shenzhou/src/stm32_ssd1289.c b/configs/shenzhou/src/stm32_ssd1289.c index 65b7f70e20..413a49c9e4 100644 --- a/configs/shenzhou/src/stm32_ssd1289.c +++ b/configs/shenzhou/src/stm32_ssd1289.c @@ -252,18 +252,18 @@ static struct stm32_lower_s g_lcdlower = #ifdef CONFIG_LCD_REGDEBUG static void stm32_lcdshow(FAR struct stm32_lower_s *priv, FAR const char *msg) { - info("%s:\n", msg); - info(" CRTL RS: %d CS: %d RD: %d WR: %d LE: %d\n", + _info("%s:\n", msg); + _info(" CRTL RS: %d CS: %d RD: %d WR: %d LE: %d\n", getreg32(LCD_RS_READ), getreg32(LCD_CS_READ), getreg32(LCD_RD_READ), getreg32(LCD_WR_READ), getreg32(LCD_LE_READ)); - info(" DATA CR: %08x %08x\n", getreg32(LCD_CRL), getreg32(LCD_CRH)); + _info(" DATA CR: %08x %08x\n", getreg32(LCD_CRL), getreg32(LCD_CRH)); if (priv->output) { - info(" OUTPUT: %08x\n", getreg32(LCD_ODR)); + _info(" OUTPUT: %08x\n", getreg32(LCD_ODR)); } else { - info(" INPUT: %08x\n", getreg32(LCD_IDR)); + _info(" INPUT: %08x\n", getreg32(LCD_IDR)); } } #endif diff --git a/configs/sim/src/sim_bringup.c b/configs/sim/src/sim_bringup.c index 08b7e9f6ce..28b4c8fdcb 100644 --- a/configs/sim/src/sim_bringup.c +++ b/configs/sim/src/sim_bringup.c @@ -60,9 +60,9 @@ int trv_mount_world(int minor, FAR const char *mountpoint); /* Debug ********************************************************************/ #ifdef CONFIG_BOARD_INITIALIZE -# define SYSLOG llerr +# define SYSLOG _llerr #else -# define SYSLOG err +# define SYSLOG _err #endif /**************************************************************************** diff --git a/configs/stm3210e-eval/src/stm32_appinit.c b/configs/stm3210e-eval/src/stm32_appinit.c index 831a4f341e..10d617c0da 100644 --- a/configs/stm3210e-eval/src/stm32_appinit.c +++ b/configs/stm3210e-eval/src/stm32_appinit.c @@ -129,14 +129,14 @@ static void stm32_i2c_register(int bus) i2c = stm32_i2cbus_initialize(bus); if (i2c == NULL) { - err("ERROR: Failed to get I2C%d interface\n", bus); + _err("ERROR: Failed to get I2C%d interface\n", bus); } else { ret = i2c_register(i2c, bus); if (ret < 0) { - err("ERROR: Failed to register I2C%d driver: %d\n", bus, ret); + _err("ERROR: Failed to register I2C%d driver: %d\n", bus, ret); stm32_i2cbus_uninitialize(i2c); } } diff --git a/configs/stm3210e-eval/src/stm32_idle.c b/configs/stm3210e-eval/src/stm32_idle.c index cbe7e9f812..5dc94ece4e 100644 --- a/configs/stm3210e-eval/src/stm32_idle.c +++ b/configs/stm3210e-eval/src/stm32_idle.c @@ -290,7 +290,7 @@ static void stm32_idlepm(void) if (newstate != oldstate) { - llinfo("newstate= %d oldstate=%d\n", newstate, oldstate); + _llinfo("newstate= %d oldstate=%d\n", newstate, oldstate); sched_lock(); diff --git a/configs/stm3220g-eval/src/stm32_appinit.c b/configs/stm3220g-eval/src/stm32_appinit.c index e763f2fbe4..93ed87e3c4 100644 --- a/configs/stm3220g-eval/src/stm32_appinit.c +++ b/configs/stm3220g-eval/src/stm32_appinit.c @@ -142,14 +142,14 @@ static void stm32_i2c_register(int bus) i2c = stm32_i2cbus_initialize(bus); if (i2c == NULL) { - err("ERROR: Failed to get I2C%d interface\n", bus); + _err("ERROR: Failed to get I2C%d interface\n", bus); } else { ret = i2c_register(i2c, bus); if (ret < 0) { - err("ERROR: Failed to register I2C%d driver: %d\n", bus, ret); + _err("ERROR: Failed to register I2C%d driver: %d\n", bus, ret); stm32_i2cbus_uninitialize(i2c); } } diff --git a/configs/stm3240g-eval/src/stm32_appinit.c b/configs/stm3240g-eval/src/stm32_appinit.c index 144f237c1a..58938c9c2e 100644 --- a/configs/stm3240g-eval/src/stm32_appinit.c +++ b/configs/stm3240g-eval/src/stm32_appinit.c @@ -160,14 +160,14 @@ static void stm32_i2c_register(int bus) i2c = stm32_i2cbus_initialize(bus); if (i2c == NULL) { - err("ERROR: Failed to get I2C%d interface\n", bus); + _err("ERROR: Failed to get I2C%d interface\n", bus); } else { ret = i2c_register(i2c, bus); if (ret < 0) { - err("ERROR: Failed to register I2C%d driver: %d\n", bus, ret); + _err("ERROR: Failed to register I2C%d driver: %d\n", bus, ret); stm32_i2cbus_uninitialize(i2c); } } diff --git a/configs/stm32_tiny/src/stm32_wireless.c b/configs/stm32_tiny/src/stm32_wireless.c index e13bf24c97..bbfdedc13b 100644 --- a/configs/stm32_tiny/src/stm32_wireless.c +++ b/configs/stm32_tiny/src/stm32_wireless.c @@ -79,7 +79,7 @@ static xcpt_t g_isr; static int stm32tiny_wl_irq_attach(xcpt_t isr) { - info("Attach IRQ\n"); + _info("Attach IRQ\n"); g_isr = isr; stm32_gpiosetevent(GPIO_NRF24L01_IRQ, false, true, false, g_isr); return OK; @@ -87,7 +87,7 @@ static int stm32tiny_wl_irq_attach(xcpt_t isr) static void stm32tiny_wl_chip_enable(bool enable) { - info("CE:%d\n", enable); + _info("CE:%d\n", enable); stm32_gpiowrite(GPIO_NRF24L01_CE, enable); } @@ -114,14 +114,14 @@ void stm32_wlinitialize(void) spidev = stm32_spibus_initialize(2); if (!spidev) { - err("ERROR: Failed to initialize SPI bus\n"); + _err("ERROR: Failed to initialize SPI bus\n"); return; } result = nrf24l01_register(spidev, &nrf_cfg); if (result != OK) { - err("ERROR: Failed to register initialize SPI bus\n"); + _err("ERROR: Failed to register initialize SPI bus\n"); return; } } diff --git a/configs/stm32f4discovery/src/stm32_ethernet.c b/configs/stm32f4discovery/src/stm32_ethernet.c index 6c58def651..e8418d41f7 100644 --- a/configs/stm32f4discovery/src/stm32_ethernet.c +++ b/configs/stm32f4discovery/src/stm32_ethernet.c @@ -79,12 +79,12 @@ */ #ifdef CONFIG_NETDEV_PHY_DEBUG -# define phyerr err -# define phywarn warn -# define phyinfo info -# define phyllerr llerr -# define phyllwarn llwarn -# define phyllinfo llinfo +# define phyerr _err +# define phywarn _warn +# define phyinfo _info +# define phyllerr _llerr +# define phyllwarn _llwarn +# define phyllinfo _llinfo #else # define phyerr(x...) # define phywarn(x...) diff --git a/configs/stm32f4discovery/src/stm32_pca9635.c b/configs/stm32f4discovery/src/stm32_pca9635.c index 739b43e16a..dfea887d0e 100644 --- a/configs/stm32f4discovery/src/stm32_pca9635.c +++ b/configs/stm32f4discovery/src/stm32_pca9635.c @@ -86,7 +86,7 @@ int stm32_pca9635_initialize(void) i2c = stm32_i2cbus_initialize(PCA9635_I2CBUS); if (!i2c) { - err("ERROR: Failed to initialize I2C%d\n", PCA9635_I2CBUS); + _err("ERROR: Failed to initialize I2C%d\n", PCA9635_I2CBUS); return -1; } diff --git a/configs/stm32l476vg-disco/src/stm32_appinit.c b/configs/stm32l476vg-disco/src/stm32_appinit.c index fee33a2b3e..3d3cf8a76b 100644 --- a/configs/stm32l476vg-disco/src/stm32_appinit.c +++ b/configs/stm32l476vg-disco/src/stm32_appinit.c @@ -93,20 +93,12 @@ /* Debug ********************************************************************/ #ifdef CONFIG_BOARD_INITIALIZE -# define SYSLOG llerr +# define SYSLOG _llerr #else -# define SYSLOG err +# define SYSLOG _err #endif /**************************************************************************** - * Private Type Definitions - ****************************************************************************/ - -/**************************************************************************** - * Private Function Prototypes - ****************************************************************************/ - - /**************************************************************************** * Private Data ****************************************************************************/ diff --git a/configs/stm32ldiscovery/src/stm32_pwm.c b/configs/stm32ldiscovery/src/stm32_pwm.c index 9285c2a821..8da1601b71 100644 --- a/configs/stm32ldiscovery/src/stm32_pwm.c +++ b/configs/stm32ldiscovery/src/stm32_pwm.c @@ -120,7 +120,7 @@ int board_pwm_setup(void) pwm = stm32_pwminitialize(STM32F3DISCOVERY_PWMTIMER); if (!pwm) { - err("ERROR: Failed to get the STM32 PWM lower half\n"); + _err("ERROR: Failed to get the STM32 PWM lower half\n"); return -ENODEV; } diff --git a/configs/tm4c1294-launchpad/src/tm4c_bringup.c b/configs/tm4c1294-launchpad/src/tm4c_bringup.c index 53bd6a965b..9c8a60f2b4 100644 --- a/configs/tm4c1294-launchpad/src/tm4c_bringup.c +++ b/configs/tm4c1294-launchpad/src/tm4c_bringup.c @@ -76,14 +76,14 @@ static void tm4c_i2c_register(int bus) i2c = tiva_i2cbus_initialize(bus); if (i2c == NULL) { - err("ERROR: Failed to get I2C%d interface\n", bus); + _err("ERROR: Failed to get I2C%d interface\n", bus); } else { ret = i2c_register(i2c, bus); if (ret < 0) { - err("ERROR: Failed to register I2C%d driver: %d\n", bus, ret); + _err("ERROR: Failed to register I2C%d driver: %d\n", bus, ret); tiva_i2cbus_uninitialize(i2c); } } @@ -164,7 +164,7 @@ int tm4c_bringup(void) ret = tiva_timer_configure(); if (ret < 0) { - err("ERROR: Failed to initialize timer driver: %d\n", ret); + _err("ERROR: Failed to initialize timer driver: %d\n", ret); } #endif diff --git a/configs/u-blox-c027/src/lpc17_ubxmdm.c b/configs/u-blox-c027/src/lpc17_ubxmdm.c index 8f8e113297..f926026eba 100644 --- a/configs/u-blox-c027/src/lpc17_ubxmdm.c +++ b/configs/u-blox-c027/src/lpc17_ubxmdm.c @@ -62,10 +62,10 @@ /* Non-standard debug that may be enabled just for testing the modem driver */ #ifdef CONFIG_MODEM_U_BLOX_DEBUG -# define m_err err -# define m_info info -# define m_vllerr llerr -# define m_vllinfo llinfo +# define m_err _err +# define m_info _info +# define m_vllerr _llerr +# define m_vllinfo _llinfo #else # define m_err(x...) # define m_info(x...) diff --git a/configs/us7032evb1/shterm/shterm.c b/configs/us7032evb1/shterm/shterm.c index b9a1ff5b14..8b70d71301 100644 --- a/configs/us7032evb1/shterm/shterm.c +++ b/configs/us7032evb1/shterm/shterm.c @@ -62,8 +62,8 @@ #define DEFAULT_BAUD 9600 -#define err(format, ...) if (debug > 0) printconsole(format, ##__VA_ARGS__) -#define info(format, ...) if (debug > 1) printconsole(format, ##__VA_ARGS__) +#define _err(format, ...) if (debug > 0) printconsole(format, ##__VA_ARGS__) +#define _info(format, ...) if (debug > 1) printconsole(format, ##__VA_ARGS__) /**************************************************************************** * Private Types diff --git a/configs/zkit-arm-1769/src/lpc17_appinit.c b/configs/zkit-arm-1769/src/lpc17_appinit.c index 2eebdc5196..9cc219af0a 100644 --- a/configs/zkit-arm-1769/src/lpc17_appinit.c +++ b/configs/zkit-arm-1769/src/lpc17_appinit.c @@ -117,13 +117,13 @@ #ifdef CONFIG_CPP_HAVE_VARARGS # ifdef CONFIG_DEBUG_INFO -# define message(...) llinfo(__VA_ARGS__) +# define message(...) _llinfo(__VA_ARGS__) # else # define message(...) printf(__VA_ARGS__) # endif #else # ifdef CONFIG_DEBUG_FEATURES -# define message llinfo +# define message _llinfo # else # define message printf # endif diff --git a/drivers/analog/ad5410.c b/drivers/analog/ad5410.c index 15ceedf4a7..5aeede163c 100644 --- a/drivers/analog/ad5410.c +++ b/drivers/analog/ad5410.c @@ -256,7 +256,7 @@ static int dac_send(FAR struct dac_dev_s *dev, FAR struct dac_msg_s *msg) static int dac_ioctl(FAR struct dac_dev_s *dev, int cmd, unsigned long arg) { - err("ERROR: Fix me; Not Implemented\n"); + _err("ERROR: Fix me; Not Implemented\n"); return 0; } diff --git a/drivers/analog/ads1242.c b/drivers/analog/ads1242.c index d15f58e3b4..ee7c39582e 100644 --- a/drivers/analog/ads1242.c +++ b/drivers/analog/ads1242.c @@ -403,15 +403,15 @@ static void ads1242_print_regs(FAR struct ads1242_dev_s *dev, char const *msg) uint8_t mux_reg_value = 0; uint8_t acr_reg_value = 0; - info("%s\n", msg); + _info("%s\n", msg); ads1242_read_reg(dev, ADS1242_REG_SETUP, &setup_reg_value); ads1242_read_reg(dev, ADS1242_REG_MUX, &mux_reg_value); ads1242_read_reg(dev, ADS1242_REG_ACR, &acr_reg_value); - info("SETUP %02X\n", setup_reg_value); - info("MUX %02X\n", mux_reg_value); - info("ACR %02X\n", acr_reg_value); + _info("SETUP %02X\n", setup_reg_value); + _info("MUX %02X\n", mux_reg_value); + _info("ACR %02X\n", acr_reg_value); } #endif /* CONFIG_DEBUG_FEATURES && CONFIG_DEBUG_INFO */ @@ -552,7 +552,7 @@ static int ads1242_ioctl (FAR struct file *filep, int cmd, unsigned long arg) /* Command was not recognized */ default: - err ("Unrecognized cmd: %d\n", cmd); + _err("ERROR: Unrecognized cmd: %d\n", cmd); ret = -ENOTTY; break; } @@ -596,7 +596,7 @@ int ads1242_register(FAR const char *devpath, FAR struct spi_dev_s *spi, priv = (FAR struct ads1242_dev_s *)kmm_malloc(sizeof(struct ads1242_dev_s)); if (priv == NULL) { - err ("Failed to allocate instance\n"); + _err("ERROR: Failed to allocate instance\n"); return -ENOMEM; } @@ -610,7 +610,7 @@ int ads1242_register(FAR const char *devpath, FAR struct spi_dev_s *spi, ret = register_driver(devpath, &g_ads1242_fops, 0666, priv); if (ret < 0) { - err ("Failed to register driver: %d\n", ret); + _err("ERROR: Failed to register driver: %d\n", ret); kmm_free(priv); } diff --git a/drivers/analog/ads1255.c b/drivers/analog/ads1255.c index ea70d36174..75b256cf16 100644 --- a/drivers/analog/ads1255.c +++ b/drivers/analog/ads1255.c @@ -396,7 +396,7 @@ static void adc_rxint(FAR struct adc_dev_s *dev, bool enable) static int adc_ioctl(FAR struct adc_dev_s *dev, int cmd, unsigned long arg) { - err("ERROR: Fix me; Not Implemented\n"); + _err("ERROR: Fix me; Not Implemented\n"); return 0; } diff --git a/drivers/bch/bchdev_unregister.c b/drivers/bch/bchdev_unregister.c index 6c2e4dd506..cf7d681de8 100644 --- a/drivers/bch/bchdev_unregister.c +++ b/drivers/bch/bchdev_unregister.c @@ -103,7 +103,7 @@ int bchdev_unregister(FAR const char *chardev) fd = open(chardev, O_RDONLY); if (fd < 0) { - err("ERROR: Failed to open %s: %d\n", chardev, errno); + _err("ERROR: Failed to open %s: %d\n", chardev, errno); return -errno; } @@ -116,7 +116,7 @@ int bchdev_unregister(FAR const char *chardev) if (ret < 0) { - err("ERROR: ioctl failed: %d\n", errno); + _err("ERROR: ioctl failed: %d\n", errno); return -errno; } diff --git a/drivers/input/stmpe811_base.c b/drivers/input/stmpe811_base.c index 8aea42e09d..3cfb7ad099 100644 --- a/drivers/input/stmpe811_base.c +++ b/drivers/input/stmpe811_base.c @@ -427,7 +427,7 @@ uint8_t stmpe811_getreg8(FAR struct stmpe811_dev_s *priv, uint8_t regaddr) } #ifdef CONFIG_STMPE811_REGDEBUG - err("%02x->%02x\n", regaddr, regval); + _err("%02x->%02x\n", regaddr, regval); #endif return regval; } @@ -455,7 +455,7 @@ void stmpe811_putreg8(FAR struct stmpe811_dev_s *priv, int ret; #ifdef CONFIG_STMPE811_REGDEBUG - err("%02x<-%02x\n", regaddr, regval); + _err("%02x<-%02x\n", regaddr, regval); #endif /* Setup to the data to be transferred. Two bytes: The STMPE811 register @@ -535,7 +535,7 @@ uint16_t stmpe811_getreg16(FAR struct stmpe811_dev_s *priv, uint8_t regaddr) } #ifdef CONFIG_STMPE811_REGDEBUG - err("%02x->%02x%02x\n", regaddr, rxbuffer[0], rxbuffer[1]); + _err("%02x->%02x%02x\n", regaddr, rxbuffer[0], rxbuffer[1]); #endif return (uint16_t)rxbuffer[0] << 8 | (uint16_t)rxbuffer[1]; } diff --git a/drivers/lcd/p14201.c b/drivers/lcd/p14201.c index f7d2d91b97..147e6414ed 100644 --- a/drivers/lcd/p14201.c +++ b/drivers/lcd/p14201.c @@ -180,9 +180,9 @@ /* Debug ******************************************************************************/ #ifdef CONFIG_LCD_RITDEBUG -# define riterr(format, ...) err(format, ##__VA_ARGS__) -# define ritwarn(format, ...) warn(format, ##__VA_ARGS__) -# define ritinfo(format, ...) info(format, ##__VA_ARGS__) +# define riterr(format, ...) _err(format, ##__VA_ARGS__) +# define ritwarn(format, ...) _warn(format, ##__VA_ARGS__) +# define ritinfo(format, ...) _info(format, ##__VA_ARGS__) #else # define riterr(x...) # define ritwarn(x...) diff --git a/drivers/lcd/skeleton.c b/drivers/lcd/skeleton.c index 3bcfc9bcf1..96be4b2e2c 100644 --- a/drivers/lcd/skeleton.c +++ b/drivers/lcd/skeleton.c @@ -90,9 +90,9 @@ /* Debug ******************************************************************************/ #ifdef CONFIG_LCD_SKELDEBUG -# define skelerr(format, ...) err(format, ##__VA_ARGS__) -# define skelwarn(format, ...) warn(format, ##__VA_ARGS__) -# define skelinfo(format, ...) info(format, ##__VA_ARGS__) +# define skelerr(format, ...) _err(format, ##__VA_ARGS__) +# define skelwarn(format, ...) _warn(format, ##__VA_ARGS__) +# define skelinfo(format, ...) _info(format, ##__VA_ARGS__) #else # define skelerr(x...) # define skelwarn(x...) diff --git a/drivers/lcd/ssd1306_i2c.c b/drivers/lcd/ssd1306_i2c.c index 343a0e3199..969eec4769 100644 --- a/drivers/lcd/ssd1306_i2c.c +++ b/drivers/lcd/ssd1306_i2c.c @@ -71,7 +71,7 @@ void ssd1306_sendbyte(FAR struct ssd1306_dev_s *priv, uint8_t regval) int ret; #ifdef CONFIG_LCD_SSD1306_REGDEBUG - llerr("-> 0x%02x\n", regval); + _llerr("-> 0x%02x\n", regval); #endif /* Setup to the data to be transferred. Two bytes: The SSD1306 register diff --git a/drivers/lcd/ssd1306_spi.c b/drivers/lcd/ssd1306_spi.c index dfa7acfc02..c53faf15d4 100644 --- a/drivers/lcd/ssd1306_spi.c +++ b/drivers/lcd/ssd1306_spi.c @@ -89,7 +89,7 @@ static inline void ssd1306_configspi(FAR struct spi_dev_s *spi) void ssd1306_sendbyte(FAR struct ssd1306_dev_s *priv, uint8_t regval) { #ifdef CONFIG_LCD_SSD1306_REGDEBUG - llerr("->0x%02x\n", regval); + _llerr("->0x%02x\n", regval); #endif /* Send byte value to display */ diff --git a/drivers/loop/losetup.c b/drivers/loop/losetup.c index fe4a9b3792..65d9f9e9cd 100644 --- a/drivers/loop/losetup.c +++ b/drivers/loop/losetup.c @@ -246,7 +246,7 @@ static ssize_t loop_read(FAR struct inode *inode, FAR unsigned char *buffer, if (start_sector + nsectors > dev->nsectors) { - err("ERROR: Read past end of file\n"); + _err("ERROR: Read past end of file\n"); return -EIO; } @@ -256,7 +256,7 @@ static ssize_t loop_read(FAR struct inode *inode, FAR unsigned char *buffer, ret = lseek(dev->fd, offset, SEEK_SET); if (ret == (off_t)-1) { - err("ERROR: Seek failed for offset=%d: %d\n", (int)offset, get_errno()); + _err("ERROR: Seek failed for offset=%d: %d\n", (int)offset, get_errno()); return -EIO; } @@ -267,7 +267,7 @@ static ssize_t loop_read(FAR struct inode *inode, FAR unsigned char *buffer, nbytesread = read(dev->fd, buffer, nsectors * dev->sectsize); if (nbytesread < 0 && get_errno() != EINTR) { - err("ERROR: Read failed: %d\n", get_errno()); + _err("ERROR: Read failed: %d\n", get_errno()); return -get_errno(); } } @@ -304,7 +304,7 @@ static ssize_t loop_write(FAR struct inode *inode, ret = lseek(dev->fd, offset, SEEK_SET); if (ret == (off_t)-1) { - err("ERROR: Seek failed for offset=%d: %d\n", (int)offset, get_errno()); + _err("ERROR: Seek failed for offset=%d: %d\n", (int)offset, get_errno()); } /* Then write the requested number of sectors to that position */ @@ -314,7 +314,7 @@ static ssize_t loop_write(FAR struct inode *inode, nbyteswritten = write(dev->fd, buffer, nsectors * dev->sectsize); if (nbyteswritten < 0 && get_errno() != EINTR) { - err("ERROR: Write failed: %d\n", get_errno()); + _err("ERROR: Write failed: %d\n", get_errno()); return -get_errno(); } } @@ -391,7 +391,7 @@ int losetup(FAR const char *devname, FAR const char *filename, ret = stat(filename, &sb); if (ret < 0) { - err("ERROR: Failed to stat %s: %d\n", filename, get_errno()); + _err("ERROR: Failed to stat %s: %d\n", filename, get_errno()); return -get_errno(); } @@ -399,7 +399,7 @@ int losetup(FAR const char *devname, FAR const char *filename, if (sb.st_size - offset < sectsize) { - err("ERROR: File is too small for blocksize\n"); + _err("ERROR: File is too small for blocksize\n"); return -ERANGE; } @@ -445,7 +445,7 @@ int losetup(FAR const char *devname, FAR const char *filename, dev->fd = open(filename, O_RDWR); if (dev->fd < 0) { - err("ERROR: Failed to open %s: %d\n", filename, get_errno()); + _err("ERROR: Failed to open %s: %d\n", filename, get_errno()); ret = -get_errno(); goto errout_with_dev; } @@ -499,7 +499,7 @@ int loteardown(FAR const char *devname) ret = open_blockdriver(devname, MS_RDONLY, &inode); if (ret < 0) { - err("ERROR: Failed to open %s: %d\n", devname, -ret); + _err("ERROR: Failed to open %s: %d\n", devname, -ret); return ret; } diff --git a/drivers/modem/u-blox.c b/drivers/modem/u-blox.c index 5925d33bf4..f3cf094ebe 100644 --- a/drivers/modem/u-blox.c +++ b/drivers/modem/u-blox.c @@ -58,10 +58,10 @@ /* Non-standard debug that may be enabled just for testing the modem driver */ #ifdef CONFIG_MODEM_U_BLOX_DEBUG -# define m_err err -# define m_info info -# define m_vllerr llerr -# define m_vllinfo llinfo +# define m_err _err +# define m_info _info +# define m_vllerr _llerr +# define m_vllinfo _llinfo #else # define m_err(x...) # define m_info(x...) diff --git a/drivers/mtd/filemtd.c b/drivers/mtd/filemtd.c index 5eb2963eab..57c4f3d834 100644 --- a/drivers/mtd/filemtd.c +++ b/drivers/mtd/filemtd.c @@ -187,7 +187,7 @@ static ssize_t filemtd_write(FAR struct file_dev_s *priv, size_t offset, #ifdef CONFIG_DEBUG_FEATURES if (newvalue != srcvalue) { - err("ERROR: Bad write: source=%02x dest=%02x result=%02x\n", + _err("ERROR: Bad write: source=%02x dest=%02x result=%02x\n", srcvalue, oldvalue, newvalue); } #endif @@ -514,7 +514,7 @@ FAR struct mtd_dev_s *filemtd_initialize(FAR const char *path, size_t offset, ret = stat(path, &sb); if (ret < 0) { - err("ERROR: Failed to stat %s: %d\n", path, get_errno()); + _err("ERROR: Failed to stat %s: %d\n", path, get_errno()); return NULL; } diff --git a/drivers/mtd/rammtd.c b/drivers/mtd/rammtd.c index 46abf5fde2..66c350888c 100644 --- a/drivers/mtd/rammtd.c +++ b/drivers/mtd/rammtd.c @@ -172,7 +172,7 @@ static void *ram_write(FAR void *dest, FAR const void *src, size_t len) #ifdef CONFIG_DEBUG_FEATURES if (newvalue != srcvalue) { - err("ERROR: Bad write: source=%02x dest=%02x result=%02x\n", + _err("ERROR: Bad write: source=%02x dest=%02x result=%02x\n", srcvalue, oldvalue, newvalue); } #endif diff --git a/drivers/mtd/smart.c b/drivers/mtd/smart.c index 050b38a9fc..52676e7ea7 100644 --- a/drivers/mtd/smart.c +++ b/drivers/mtd/smart.c @@ -1387,7 +1387,7 @@ static int smart_add_sector_to_cache(FAR struct smart_struct_s *dev, if (dev->debuglevel > 1) { - err("Add Cache sector: Log=%d, Phys=%d at index %d from line %d\n", + _err("Add Cache sector: Log=%d, Phys=%d at index %d from line %d\n", logical, physical, index, line); } @@ -1575,7 +1575,7 @@ static void smart_update_cache(FAR struct smart_struct_s *dev, uint16_t if (dev->debuglevel > 1) { - err("Update Cache: Log=%d, Phys=%d at index %d\n", logical, physical, x); + _err("Update Cache: Log=%d, Phys=%d at index %d\n", logical, physical, x); } break; @@ -1712,7 +1712,7 @@ static int smart_set_wear_level(FAR struct smart_struct_s *dev, uint16_t block, if (level > 15) { - err("ERROR: Fatal Design Error! Wear level > 15, block=%d\n", block); + _err("ERROR: Fatal Design Error! Wear level > 15, block=%d\n", block); /* This is a design flaw, but we still allow processing, otherwise we * will corrupt the volume. It's better to have a few blocks that are diff --git a/drivers/mtd/sst26.c b/drivers/mtd/sst26.c index 4b70c0f285..016d72b5b4 100644 --- a/drivers/mtd/sst26.c +++ b/drivers/mtd/sst26.c @@ -208,10 +208,10 @@ /* Debug ****************************************************************************/ #ifdef CONFIG_SST26_DEBUG -# define ssterr(format, ...) err(format, ##__VA_ARGS__) -# define sstllerr(format, ...) llerr(format, ##__VA_ARGS__) -# define sstinfo(format, ...) info(format, ##__VA_ARGS__) -# define sstllinfo(format, ...) llinfo(format, ##__VA_ARGS__) +# define ssterr(format, ...) _err(format, ##__VA_ARGS__) +# define sstllerr(format, ...) _llerr(format, ##__VA_ARGS__) +# define sstinfo(format, ...) _info(format, ##__VA_ARGS__) +# define sstllinfo(format, ...) _llinfo(format, ##__VA_ARGS__) #else # define ssterr(x...) # define sstllerr(x...) @@ -340,7 +340,7 @@ static inline int sst26_readid(struct sst26_dev_s *priv) SPI_SELECT(priv->dev, SPIDEV_FLASH, false); sst26_unlock(priv->dev); - llinfo("manufacturer: %02x memory: %02x capacity: %02x\n", + _llinfo("manufacturer: %02x memory: %02x capacity: %02x\n", manufacturer, memory, capacity); /* Check for a valid manufacturer and memory type */ diff --git a/drivers/net/phy_notify.c b/drivers/net/phy_notify.c index d480a361a8..96b6109b67 100644 --- a/drivers/net/phy_notify.c +++ b/drivers/net/phy_notify.c @@ -82,10 +82,10 @@ */ #ifdef CONFIG_NETDEV_PHY_DEBUG -# define phyinfo info -# define phyllinfo llinfo -# define phyerr err -# define phyllerr llerr +# define phyinfo _info +# define phyllinfo _llinfo +# define phyerr _err +# define phyllerr _llerr #else # define phyinfo(x...) # define phyllinfo(x...) diff --git a/drivers/pipes/pipe_common.c b/drivers/pipes/pipe_common.c index 2b9eb67e3a..21fe124f16 100644 --- a/drivers/pipes/pipe_common.c +++ b/drivers/pipes/pipe_common.c @@ -519,9 +519,9 @@ ssize_t pipecommon_write(FAR struct file *filep, FAR const char *buffer, /* At present, this method cannot be called from interrupt handlers. That is * because it calls sem_wait (via pipecommon_semtake below) and sem_wait cannot * be called from interrupt level. This actually happens fairly commonly - * IF err() is called from interrupt handlers and stdout is being redirected + * IF [a-z]err() is called from interrupt handlers and stdout is being redirected * via a pipe. In that case, the debug output will try to go out the pipe - * (interrupt handlers should use the llerr() APIs). + * (interrupt handlers should use the _llerr() APIs). * * On the other hand, it would be very valuable to be able to feed the pipe * from an interrupt handler! TODO: Consider disabling interrupts instead diff --git a/drivers/power/battery_charger.c b/drivers/power/battery_charger.c index 514329f03e..0a573375dc 100644 --- a/drivers/power/battery_charger.c +++ b/drivers/power/battery_charger.c @@ -228,7 +228,7 @@ static int bat_charger_ioctl(FAR struct file *filep, int cmd, break; default: - err("ERROR: Unrecognized cmd: %d\n", cmd); + _err("ERROR: Unrecognized cmd: %d\n", cmd); ret = -ENOTTY; break; } @@ -268,7 +268,7 @@ int battery_charger_register(FAR const char *devpath, ret = register_driver(devpath, &g_batteryops, 0555, dev); if (ret < 0) { - err("ERROR: Failed to register driver: %d\n", ret); + _err("ERROR: Failed to register driver: %d\n", ret); } return ret; diff --git a/drivers/power/battery_gauge.c b/drivers/power/battery_gauge.c index 247d319180..f0b2f9f66c 100644 --- a/drivers/power/battery_gauge.c +++ b/drivers/power/battery_gauge.c @@ -213,7 +213,7 @@ static int bat_gauge_ioctl(FAR struct file *filep, int cmd, unsigned long arg) break; default: - err("ERROR: Unrecognized cmd: %d\n", cmd); + _err("ERROR: Unrecognized cmd: %d\n", cmd); ret = -ENOTTY; break; } @@ -253,7 +253,7 @@ int battery_gauge_register(FAR const char *devpath, ret = register_driver(devpath, &g_batteryops, 0555, dev); if (ret < 0) { - err("ERROR: Failed to register driver: %d\n", ret); + _err("ERROR: Failed to register driver: %d\n", ret); } return ret; diff --git a/drivers/power/bq2425x.c b/drivers/power/bq2425x.c index 04a864b775..661187cdee 100644 --- a/drivers/power/bq2425x.c +++ b/drivers/power/bq2425x.c @@ -78,8 +78,8 @@ /* Debug ********************************************************************/ #ifdef CONFIG_DEBUG_BQ2425X -# define baterr err -# define batreg err +# define baterr _err +# define batreg _err #else # ifdef CONFIG_CPP_HAVE_VARARGS # define baterr(x...) diff --git a/drivers/power/max1704x.c b/drivers/power/max1704x.c index ac1d7ef80f..00f98fc189 100644 --- a/drivers/power/max1704x.c +++ b/drivers/power/max1704x.c @@ -160,7 +160,7 @@ /* Debug ********************************************************************/ #ifdef CONFIG_DEBUG_MAX1704X -# define baterr err +# define baterr _err #else # ifdef CONFIG_CPP_HAVE_VARARGS # define baterr(x...) diff --git a/drivers/sensors/adxl345_i2c.c b/drivers/sensors/adxl345_i2c.c index a522c36fdf..96731bbe8a 100644 --- a/drivers/sensors/adxl345_i2c.c +++ b/drivers/sensors/adxl345_i2c.c @@ -102,7 +102,7 @@ uint8_t adxl345_getreg8(FAR struct adxl345_dev_s *priv, uint8_t regaddr) } #ifdef CONFIG_ADXL345_REGDEBUG - err("%02x->%02x\n", regaddr, regval); + _err("%02x->%02x\n", regaddr, regval); #endif return regval; } @@ -130,7 +130,7 @@ void adxl345_putreg8(FAR struct adxl345_dev_s *priv, int ret; #ifdef CONFIG_ADXL345_REGDEBUG - err("%02x<-%02x\n", regaddr, regval); + _err("%02x<-%02x\n", regaddr, regval); #endif /* Setup to the data to be transferred. Two bytes: The ADXL345 register @@ -209,7 +209,7 @@ uint16_t adxl345_getreg16(FAR struct adxl345_dev_s *priv, uint8_t regaddr) } #ifdef CONFIG_ADXL345_REGDEBUG - err("%02x->%02x%02x\n", regaddr, rxbuffer[0], rxbuffer[1]); + _err("%02x->%02x%02x\n", regaddr, rxbuffer[0], rxbuffer[1]); #endif return (uint16_t)rxbuffer[0] << 8 | (uint16_t)rxbuffer[1]; } diff --git a/drivers/sensors/adxl345_spi.c b/drivers/sensors/adxl345_spi.c index 38dd9179c2..a2d524bf50 100644 --- a/drivers/sensors/adxl345_spi.c +++ b/drivers/sensors/adxl345_spi.c @@ -113,7 +113,7 @@ uint8_t adxl345_getreg8(FAR struct adxl345_dev_s *priv, uint8_t regaddr) (void)SPI_LOCK(priv->spi, false); #ifdef CONFIG_ADXL345_REGDEBUG - err("%02x->%02x\n", regaddr, regval); + _err("%02x->%02x\n", regaddr, regval); #endif return regval; } @@ -130,7 +130,7 @@ void adxl345_putreg8(FAR struct adxl345_dev_s *priv, uint8_t regaddr, uint8_t regval) { #ifdef CONFIG_ADXL345_REGDEBUG - err("%02x<-%02x\n", regaddr, regval); + _err("%02x<-%02x\n", regaddr, regval); #endif /* If SPI bus is shared then lock and configure it */ @@ -191,7 +191,7 @@ uint16_t adxl345_getreg16(FAR struct adxl345_dev_s *priv, uint8_t regaddr) (void)SPI_LOCK(priv->spi, false); #ifdef CONFIG_ADXL345_REGDEBUG - err("%02x->%04x\n", regaddr, regval); + _err("%02x->%04x\n", regaddr, regval); #endif return regval; diff --git a/drivers/sensors/mpl115a.c b/drivers/sensors/mpl115a.c index 5631bd7073..38763f5c71 100644 --- a/drivers/sensors/mpl115a.c +++ b/drivers/sensors/mpl115a.c @@ -157,7 +157,7 @@ static uint8_t mpl115a_getreg8(FAR struct mpl115a_dev_s *priv, uint8_t regaddr) (void)SPI_LOCK(priv->spi, false); #ifdef CONFIG_MPL115A_REGDEBUG - err("%02x->%02x\n", regaddr, regval); + _err("%02x->%02x\n", regaddr, regval); #endif return regval; } diff --git a/drivers/sensors/ms58xx.c b/drivers/sensors/ms58xx.c index 4c948714b0..47f04e57ca 100644 --- a/drivers/sensors/ms58xx.c +++ b/drivers/sensors/ms58xx.c @@ -1178,14 +1178,14 @@ int ms58xx_register(FAR const char *devpath, FAR struct i2c_master_s *i2c, if (ret < 0) { snerr("ERROR: ms58xx_setosr failed: %d\n", ret); - goto err; + goto errout; } ret = ms58xx_reset(priv); if (ret < 0) { snerr("ERROR: ms58xx_reset failed: %d\n", ret); - goto err; + goto errout; } /* Register the character driver */ @@ -1194,12 +1194,12 @@ int ms58xx_register(FAR const char *devpath, FAR struct i2c_master_s *i2c, if (ret < 0) { snerr("ERROR: Failed to register driver: %d\n", ret); - goto err; + goto errout; } return ret; -err: +errout: kmm_free(priv); return ret; } diff --git a/drivers/sercomm/console.c b/drivers/sercomm/console.c index 579a3f605a..c12c35af5f 100644 --- a/drivers/sercomm/console.c +++ b/drivers/sercomm/console.c @@ -187,7 +187,7 @@ int sercomm_register(FAR const char *path, FAR uart_dev_t *dev) sem_init(&dev->pollsem, 0, 1); #endif - info("Registering %s\n", path); + _info("Registering %s\n", path); return register_driver(path, &g_sercom_console_ops, 0666, NULL); } diff --git a/drivers/serial/serial.c b/drivers/serial/serial.c index ca695afb76..c98867d6ff 100644 --- a/drivers/serial/serial.c +++ b/drivers/serial/serial.c @@ -1369,7 +1369,7 @@ int uart_register(FAR const char *path, FAR uart_dev_t *dev) sem_init(&dev->pollsem, 0, 1); #endif - info("Registering %s\n", path); + _info("Registering %s\n", path); return register_driver(path, &g_serialops, 0666, dev); } diff --git a/drivers/serial/uart_16550.c b/drivers/serial/uart_16550.c index 59ebdbfa9a..022adf3abe 100644 --- a/drivers/serial/uart_16550.c +++ b/drivers/serial/uart_16550.c @@ -829,7 +829,7 @@ static int u16550_interrupt(int irq, void *context) /* Read the modem status register (MSR) to clear */ status = u16550_serialin(priv, UART_MSR_OFFSET); - info("MSR: %02x\n", status); + _info("MSR: %02x\n", status); break; } @@ -840,7 +840,7 @@ static int u16550_interrupt(int irq, void *context) /* Read the line status register (LSR) to clear */ status = u16550_serialin(priv, UART_LSR_OFFSET); - info("LSR: %02x\n", status); + _info("LSR: %02x\n", status); break; } @@ -848,7 +848,7 @@ static int u16550_interrupt(int irq, void *context) default: { - err("ERROR: Unexpected IIR: %02x\n", status); + _err("ERROR: Unexpected IIR: %02x\n", status); break; } } diff --git a/drivers/timers/cs2100-cp.c b/drivers/timers/cs2100-cp.c index dfd1c58ba8..82c80bf403 100644 --- a/drivers/timers/cs2100-cp.c +++ b/drivers/timers/cs2100-cp.c @@ -69,24 +69,24 @@ #undef cserr #ifdef CONFIG_CS2100CP_DEBUG # ifdef CONFIG_CPP_HAVE_VARARGS -# define cserr(format, ...) err(format, ##__VA_ARGS__) +# define cserr(format, ...) _err(format, ##__VA_ARGS__) # else -# define cserr err +# define cserr _err # endif #else # ifdef CONFIG_CPP_HAVE_VARARGS # define cserr(x...) # else -# define cserr (void) +# define cserr (void) # endif #endif #undef reginfo #ifdef CONFIG_CS2100CP_REGDEBUG # ifdef CONFIG_CPP_HAVE_VARARGS -# define reginfo(format, ...) err(format, ##__VA_ARGS__) +# define reginfo(format, ...) _err(format, ##__VA_ARGS__) # else -# define reginfo err +# define reginfo _err # endif #else # ifdef CONFIG_CPP_HAVE_VARARGS @@ -96,14 +96,6 @@ # endif #endif -/**************************************************************************** - * Public Types - ****************************************************************************/ - -/**************************************************************************** - * Public Data - ****************************************************************************/ - /**************************************************************************** * Private Functions ****************************************************************************/ diff --git a/drivers/video/ov2640.c b/drivers/video/ov2640.c index 28b3c4ebc7..06f88d1bf4 100644 --- a/drivers/video/ov2640.c +++ b/drivers/video/ov2640.c @@ -696,7 +696,7 @@ static int ov2640_putreg(FAR struct i2c_master_s *i2c, uint8_t regaddr, int ret; #ifdef CONFIG_OV2640_REGDEBUG - err("%02x <- %02x\n", regaddr, regval); + _err("%02x <- %02x\n", regaddr, regval); #endif /* Set up for the transfer */ @@ -771,7 +771,7 @@ static uint8_t ov2640_getreg(FAR struct i2c_master_s *i2c, uint8_t regaddr) #ifdef CONFIG_OV2640_REGDEBUG else { - err("%02x -> %02x\n", regaddr, regval); + _err("%02x -> %02x\n", regaddr, regval); } #endif diff --git a/drivers/wireless/cc3000/cc3000.c b/drivers/wireless/cc3000/cc3000.c index 1e14d98fdf..4d08431d9e 100644 --- a/drivers/wireless/cc3000/cc3000.c +++ b/drivers/wireless/cc3000/cc3000.c @@ -124,8 +124,8 @@ CCASSERT(sizeof(cc3000_buffer_desc) <= CONFIG_MQ_MAXMSGSIZE); # define PROBE(pin,state) #endif -#define waitllerr(x,...) // llerr -#define waitllinfo(x,...) // llinfo +#define waitllerr(x,...) // _llerr +#define waitllinfo(x,...) // _llinfo /**************************************************************************** * Private Function Prototypes diff --git a/drivers/wireless/cc3000/socket.c b/drivers/wireless/cc3000/socket.c index 255ce62b2f..d8eea4ebd3 100644 --- a/drivers/wireless/cc3000/socket.c +++ b/drivers/wireless/cc3000/socket.c @@ -62,8 +62,8 @@ # define ARRAY_SIZE(x) (sizeof(x) / sizeof((x)[0])) #endif -#define waitllerr(x,...) // llerr -#define waitllinfo(x,...) // llinfo +#define waitllerr(x,...) // _llerr +#define waitllinfo(x,...) // _llinfo /**************************************************************************** * Private Types diff --git a/drivers/wireless/ieee802154/mrf24j40.c b/drivers/wireless/ieee802154/mrf24j40.c index c49713cd3e..efbbb8c7b2 100644 --- a/drivers/wireless/ieee802154/mrf24j40.c +++ b/drivers/wireless/ieee802154/mrf24j40.c @@ -779,7 +779,7 @@ static int mrf24j40_settxpower(FAR struct ieee802154_dev_s *ieee, return -EINVAL; } - llinfo("remaining attenuation: %d mBm\n",txpwr); + _llinfo("remaining attenuation: %d mBm\n",txpwr); switch(txpwr/100) { diff --git a/drivers/wireless/pn532.c b/drivers/wireless/pn532.c index afb575e7b1..e9bf42737c 100644 --- a/drivers/wireless/pn532.c +++ b/drivers/wireless/pn532.c @@ -57,8 +57,8 @@ ****************************************************************************/ #ifdef CONFIG_WL_PN532_DEBUG -# define pn532err err -# define pn532info info +# define pn532err _err +# define pn532info _info #else # ifdef CONFIG_CPP_HAVE_VARARGS # define pn532err(x...) diff --git a/graphics/vnc/server/vnc_server.h b/graphics/vnc/server/vnc_server.h index 9b9406038b..fc1e398fc4 100644 --- a/graphics/vnc/server/vnc_server.h +++ b/graphics/vnc/server/vnc_server.h @@ -186,19 +186,19 @@ #ifdef CONFIG_VNCSERVER_UPDATE_DEBUG # ifdef CONFIG_CPP_HAVE_VARARGS -# define upderr(format, ...) err(format, ##__VA_ARGS__) -# define updllerr(format, ...) llerr(format, ##__VA_ARGS__) -# define updinfo(format, ...) info(format, ##__VA_ARGS__) -# define updllinfo(format, ...) llinfo(format, ##__VA_ARGS__) -# define updinfo(format, ...) info(format, ##__VA_ARGS__) -# define updllinfo(format, ...) llinfo(format, ##__VA_ARGS__) +# define upderr(format, ...) _err(format, ##__VA_ARGS__) +# define updllerr(format, ...) _llerr(format, ##__VA_ARGS__) +# define updinfo(format, ...) _info(format, ##__VA_ARGS__) +# define updllinfo(format, ...) _llinfo(format, ##__VA_ARGS__) +# define updinfo(format, ...) _info(format, ##__VA_ARGS__) +# define updllinfo(format, ...) _llinfo(format, ##__VA_ARGS__) # else -# define upderr err -# define updllerr llerr -# define updwarn warn -# define updllwarn llwarn -# define updinfo info -# define updllinfo llinfo +# define upderr _err +# define updllerr _llerr +# define updwarn _warn +# define updllwarn _llwarn +# define updinfo _info +# define updllinfo _llinfo # endif #else # ifdef CONFIG_CPP_HAVE_VARARGS diff --git a/include/debug.h b/include/debug.h index 5479cd45e1..7251839ea6 100644 --- a/include/debug.h +++ b/include/debug.h @@ -64,7 +64,7 @@ * * The first character of the macro name indicates the system system * (e.g., n=network, f=filesystm, etc.). If the first character is - * missing (i.e., info()), then it is common. The common info() macro + * missing (i.e., _info()), then it is common. The common _info() macro * is enabled simply with CONFIG_DEBUG_INFO. Subsystem debug requires an * additional configuration setting to enable it (e.g., CONFIG_DEBUG_NET * for the network, CONFIG_DEBUG_FS for the file system, etc). @@ -118,15 +118,6 @@ # define EXTRA_ARG #endif -/* The actual logger function may be overridden in arch/debug.h if needed. */ - -#ifndef __arch_syslog -# define __arch_syslog syslog -#endif -#ifndef __arch_lowsyslog -# define __arch_lowsyslog lowsyslog -#endif - /* Debug macros will differ depending upon if the toolchain supports * macros with a variable number of arguments or not. */ @@ -135,6 +126,17 @@ /* C-99 style variadic macros are supported */ +/* The actual logger function may be overridden in arch/debug.h if needed. + * (Currently only if the pre-processor supports variadic macros) + */ + +#ifndef __arch_syslog +# define __arch_syslog syslog +#endif +#ifndef __arch_lowsyslog +# define __arch_lowsyslog lowsyslog +#endif + #ifdef CONFIG_ARCH_LOWPUTC # define alert(format, ...) \ __arch_lowsyslog(LOG_EMERG, EXTRA_FMT format EXTRA_ARG, ##__VA_ARGS__) @@ -143,743 +145,743 @@ # endif #ifdef CONFIG_DEBUG_ERROR -# define err(format, ...) \ +# define _err(format, ...) \ __arch_syslog(LOG_ERR, EXTRA_FMT format EXTRA_ARG, ##__VA_ARGS__) # ifdef CONFIG_ARCH_LOWPUTC -# define llerr(format, ...) \ +# define _llerr(format, ...) \ __arch_lowsyslog(LOG_ERR, EXTRA_FMT format EXTRA_ARG, ##__VA_ARGS__) # else -# define llerr(x...) +# define _llerr(x...) # endif #else /* CONFIG_DEBUG_ERROR */ -# define err(x...) -# define llerr(x...) +# define _err(x...) +# define _llerr(x...) #endif #ifdef CONFIG_DEBUG_WARN -# define warn(format, ...) \ +# define _warn(format, ...) \ __arch_syslog(LOG_WARNING, EXTRA_FMT format EXTRA_ARG, ##__VA_ARGS__) # ifdef CONFIG_ARCH_LOWPUTC -# define llwarn(format, ...) \ +# define _llwarn(format, ...) \ __arch_lowsyslog(LOG_WARNING, EXTRA_FMT format EXTRA_ARG, ##__VA_ARGS__) # else -# define llwarn(x...) +# define _llwarn(x...) # endif #else /* CONFIG_DEBUG_INFO */ -# define warn(x...) -# define llwarn(x...) +# define _warn(x...) +# define _llwarn(x...) #endif /* CONFIG_DEBUG_INFO */ #ifdef CONFIG_DEBUG_INFO -# define info(format, ...) \ +# define _info(format, ...) \ __arch_syslog(LOG_INFO, EXTRA_FMT format EXTRA_ARG, ##__VA_ARGS__) # ifdef CONFIG_ARCH_LOWPUTC -# define llinfo(format, ...) \ +# define _llinfo(format, ...) \ __arch_lowsyslog(LOG_INFO, EXTRA_FMT format EXTRA_ARG, ##__VA_ARGS__) # else -# define llinfo(x...) +# define _llinfo(x...) # endif #else /* CONFIG_DEBUG_INFO */ -# define info(x...) -# define llinfo(x...) +# define _info(x...) +# define _llinfo(x...) #endif /* CONFIG_DEBUG_INFO */ /* Subsystem specific debug */ #ifdef CONFIG_DEBUG_MM_ERROR -# define merr(format, ...) err(format, ##__VA_ARGS__) -# define mllerr(format, ...) llerr(format, ##__VA_ARGS__) +# define merr(format, ...) _err(format, ##__VA_ARGS__) +# define mllerr(format, ...) _llerr(format, ##__VA_ARGS__) #else # define merr(x...) # define mllerr(x...) #endif #ifdef CONFIG_DEBUG_MM_WARN -# define mwarn(format, ...) warn(format, ##__VA_ARGS__) -# define mllwarn(format, ...) llwarn(format, ##__VA_ARGS__) +# define mwarn(format, ...) _warn(format, ##__VA_ARGS__) +# define mllwarn(format, ...) _llwarn(format, ##__VA_ARGS__) #else # define mwarn(x...) # define mllwarn(x...) #endif #ifdef CONFIG_DEBUG_MM_INFO -# define minfo(format, ...) info(format, ##__VA_ARGS__) -# define mllinfo(format, ...) llinfo(format, ##__VA_ARGS__) +# define minfo(format, ...) _info(format, ##__VA_ARGS__) +# define mllinfo(format, ...) _llinfo(format, ##__VA_ARGS__) #else # define minfo(x...) # define mllinfo(x...) #endif #ifdef CONFIG_DEBUG_SCHED_ERROR -# define serr(format, ...) err(format, ##__VA_ARGS__) -# define sllerr(format, ...) llerr(format, ##__VA_ARGS__) +# define serr(format, ...) _err(format, ##__VA_ARGS__) +# define sllerr(format, ...) _llerr(format, ##__VA_ARGS__) #else # define serr(x...) # define sllerr(x...) #endif #ifdef CONFIG_DEBUG_SCHED_WARN -# define swarn(format, ...) warn(format, ##__VA_ARGS__) -# define sllwarn(format, ...) llwarn(format, ##__VA_ARGS__) +# define swarn(format, ...) _warn(format, ##__VA_ARGS__) +# define sllwarn(format, ...) _llwarn(format, ##__VA_ARGS__) #else # define swarn(x...) # define sllwarn(x...) #endif #ifdef CONFIG_DEBUG_SCHED_INFO -# define sinfo(format, ...) info(format, ##__VA_ARGS__) -# define sllinfo(format, ...) llinfo(format, ##__VA_ARGS__) +# define sinfo(format, ...) _info(format, ##__VA_ARGS__) +# define sllinfo(format, ...) _llinfo(format, ##__VA_ARGS__) #else # define sinfo(x...) # define sllinfo(x...) #endif #ifdef CONFIG_DEBUG_SYSCALL_ERROR -# define svcerr(format, ...) err(format, ##__VA_ARGS__) -# define svcllerr(format, ...) llerr(format, ##__VA_ARGS__) +# define svcerr(format, ...) _err(format, ##__VA_ARGS__) +# define svcllerr(format, ...) _llerr(format, ##__VA_ARGS__) #else # define svcerr(x...) # define svcllerr(x...) #endif #ifdef CONFIG_DEBUG_SYSCALL_WARN -# define svcwarn(format, ...) warn(format, ##__VA_ARGS__) -# define svcllwarn(format, ...) llwarn(format, ##__VA_ARGS__) +# define svcwarn(format, ...) _warn(format, ##__VA_ARGS__) +# define svcllwarn(format, ...) _llwarn(format, ##__VA_ARGS__) #else # define svcwarn(x...) # define svcllwarn(x...) #endif #ifdef CONFIG_DEBUG_SYSCALL_INFO -# define svcinfo(format, ...) info(format, ##__VA_ARGS__) -# define svcllinfo(format, ...) llinfo(format, ##__VA_ARGS__) +# define svcinfo(format, ...) _info(format, ##__VA_ARGS__) +# define svcllinfo(format, ...) _llinfo(format, ##__VA_ARGS__) #else # define svcinfo(x...) # define svcllinfo(x...) #endif #ifdef CONFIG_DEBUG_PAGING_ERROR -# define pgerr(format, ...) err(format, ##__VA_ARGS__) -# define pgllerr(format, ...) llerr(format, ##__VA_ARGS__) +# define pgerr(format, ...) _err(format, ##__VA_ARGS__) +# define pgllerr(format, ...) _llerr(format, ##__VA_ARGS__) #else # define pgerr(x...) # define pgllerr(x...) #endif #ifdef CONFIG_DEBUG_PAGING_WARN -# define pgwarn(format, ...) warn(format, ##__VA_ARGS__) -# define pgllwarn(format, ...) llwarn(format, ##__VA_ARGS__) +# define pgwarn(format, ...) _warn(format, ##__VA_ARGS__) +# define pgllwarn(format, ...) _llwarn(format, ##__VA_ARGS__) #else # define pgwarn(x...) # define pgllwarn(x...) #endif #ifdef CONFIG_DEBUG_PAGING_INFO -# define pginfo(format, ...) info(format, ##__VA_ARGS__) -# define pgllinfo(format, ...) llinfo(format, ##__VA_ARGS__) +# define pginfo(format, ...) _info(format, ##__VA_ARGS__) +# define pgllinfo(format, ...) _llinfo(format, ##__VA_ARGS__) #else # define pgerr(x...) # define pgllerr(x...) #endif #ifdef CONFIG_DEBUG_NET_ERROR -# define nerr(format, ...) err(format, ##__VA_ARGS__) -# define nllerr(format, ...) llerr(format, ##__VA_ARGS__) +# define nerr(format, ...) _err(format, ##__VA_ARGS__) +# define nllerr(format, ...) _llerr(format, ##__VA_ARGS__) #else # define nerr(x...) # define nllerr(x...) #endif #ifdef CONFIG_DEBUG_NET_WARN -# define nwarn(format, ...) warn(format, ##__VA_ARGS__) -# define nllwarn(format, ...) llwarn(format, ##__VA_ARGS__) +# define nwarn(format, ...) _warn(format, ##__VA_ARGS__) +# define nllwarn(format, ...) _llwarn(format, ##__VA_ARGS__) #else # define nwarn(x...) # define nllwarn(x...) #endif #ifdef CONFIG_DEBUG_NET_INFO -# define ninfo(format, ...) info(format, ##__VA_ARGS__) -# define nllinfo(format, ...) llinfo(format, ##__VA_ARGS__) +# define ninfo(format, ...) _info(format, ##__VA_ARGS__) +# define nllinfo(format, ...) _llinfo(format, ##__VA_ARGS__) #else # define ninfo(x...) # define nllinfo(x...) #endif #ifdef CONFIG_DEBUG_FS_ERROR -# define ferr(format, ...) err(format, ##__VA_ARGS__) -# define fllerr(format, ...) llerr(format, ##__VA_ARGS__) +# define ferr(format, ...) _err(format, ##__VA_ARGS__) +# define fllerr(format, ...) _llerr(format, ##__VA_ARGS__) #else # define ferr(x...) # define fllerr(x...) #endif #ifdef CONFIG_DEBUG_FS_WARN -# define fwarn(format, ...) warn(format, ##__VA_ARGS__) -# define fllwarn(format, ...) llwarn(format, ##__VA_ARGS__) +# define fwarn(format, ...) _warn(format, ##__VA_ARGS__) +# define fllwarn(format, ...) _llwarn(format, ##__VA_ARGS__) #else # define fwarn(x...) # define fllwarn(x...) #endif #ifdef CONFIG_DEBUG_FS_INFO -# define finfo(format, ...) info(format, ##__VA_ARGS__) -# define fllinfo(format, ...) llinfo(format, ##__VA_ARGS__) +# define finfo(format, ...) _info(format, ##__VA_ARGS__) +# define fllinfo(format, ...) _llinfo(format, ##__VA_ARGS__) #else # define finfo(x...) # define fllinfo(x...) #endif #ifdef CONFIG_DEBUG_CRYPTO_ERROR -# define crypterr(format, ...) err(format, ##__VA_ARGS__) -# define cryptllerr(format, ...) llerr(format, ##__VA_ARGS__) +# define crypterr(format, ...) _err(format, ##__VA_ARGS__) +# define cryptllerr(format, ...) _llerr(format, ##__VA_ARGS__) #else # define crypterr(x...) # define cryptllerr(x...) #endif #ifdef CONFIG_DEBUG_CRYPTO_WARN -# define cryptwarn(format, ...) warn(format, ##__VA_ARGS__) -# define cryptllwarn(format, ...) llwarn(format, ##__VA_ARGS__) +# define cryptwarn(format, ...) _warn(format, ##__VA_ARGS__) +# define cryptllwarn(format, ...) _llwarn(format, ##__VA_ARGS__) #else # define cryptwarn(x...) # define cryptllwarn(x...) #endif #ifdef CONFIG_DEBUG_CRYPTO_INFO -# define cryptinfo(format, ...) info(format, ##__VA_ARGS__) -# define cryptllinfo(format, ...) llinfo(format, ##__VA_ARGS__) +# define cryptinfo(format, ...) _info(format, ##__VA_ARGS__) +# define cryptllinfo(format, ...) _llinfo(format, ##__VA_ARGS__) #else # define cryptinfo(x...) # define cryptllinfo(x...) #endif #ifdef CONFIG_DEBUG_INPUT_ERROR -# define ierr(format, ...) err(format, ##__VA_ARGS__) -# define illerr(format, ...) llerr(format, ##__VA_ARGS__) +# define ierr(format, ...) _err(format, ##__VA_ARGS__) +# define illerr(format, ...) _llerr(format, ##__VA_ARGS__) #else # define ierr(x...) # define illerr(x...) #endif #ifdef CONFIG_DEBUG_INPUT_WARN -# define iwarn(format, ...) warn(format, ##__VA_ARGS__) -# define illwarn(format, ...) llwarn(format, ##__VA_ARGS__) +# define iwarn(format, ...) _warn(format, ##__VA_ARGS__) +# define illwarn(format, ...) _llwarn(format, ##__VA_ARGS__) #else # define iwarn(x...) # define illwarn(x...) #endif #ifdef CONFIG_DEBUG_INPUT_INFO -# define iinfo(format, ...) info(format, ##__VA_ARGS__) -# define illinfo(format, ...) llinfo(format, ##__VA_ARGS__) +# define iinfo(format, ...) _info(format, ##__VA_ARGS__) +# define illinfo(format, ...) _llinfo(format, ##__VA_ARGS__) #else # define iinfo(x...) # define illinfo(x...) #endif #ifdef CONFIG_DEBUG_ANALOG_ERROR -# define aerr(format, ...) err(format, ##__VA_ARGS__) -# define allerr(format, ...) llerr(format, ##__VA_ARGS__) +# define aerr(format, ...) _err(format, ##__VA_ARGS__) +# define allerr(format, ...) _llerr(format, ##__VA_ARGS__) #else # define aerr(x...) # define allerr(x...) #endif #ifdef CONFIG_DEBUG_ANALOG_WARN -# define awarn(format, ...) warn(format, ##__VA_ARGS__) -# define allwarn(format, ...) llwarn(format, ##__VA_ARGS__) +# define awarn(format, ...) _warn(format, ##__VA_ARGS__) +# define allwarn(format, ...) _llwarn(format, ##__VA_ARGS__) #else # define awarn(x...) # define allwarn(x...) #endif #ifdef CONFIG_DEBUG_ANALOG_INFO -# define ainfo(format, ...) info(format, ##__VA_ARGS__) -# define allinfo(format, ...) llinfo(format, ##__VA_ARGS__) +# define ainfo(format, ...) _info(format, ##__VA_ARGS__) +# define allinfo(format, ...) _llinfo(format, ##__VA_ARGS__) #else # define ainfo(x...) # define allinfo(x...) #endif #ifdef CONFIG_DEBUG_CAN_ERROR -# define canerr(format, ...) err(format, ##__VA_ARGS__) -# define canllerr(format, ...) llerr(format, ##__VA_ARGS__) +# define canerr(format, ...) _err(format, ##__VA_ARGS__) +# define canllerr(format, ...) _llerr(format, ##__VA_ARGS__) #else # define canerr(x...) # define canllerr(x...) #endif #ifdef CONFIG_DEBUG_CAN_WARN -# define canwarn(format, ...) warn(format, ##__VA_ARGS__) -# define canllwarn(format, ...) llwarn(format, ##__VA_ARGS__) +# define canwarn(format, ...) _warn(format, ##__VA_ARGS__) +# define canllwarn(format, ...) _llwarn(format, ##__VA_ARGS__) #else # define canwarn(x...) # define canllwarn(x...) #endif #ifdef CONFIG_DEBUG_CAN_INFO -# define caninfo(format, ...) info(format, ##__VA_ARGS__) -# define canllinfo(format, ...) llinfo(format, ##__VA_ARGS__) +# define caninfo(format, ...) _info(format, ##__VA_ARGS__) +# define canllinfo(format, ...) _llinfo(format, ##__VA_ARGS__) #else # define caninfo(x...) # define canllinfo(x...) #endif #ifdef CONFIG_DEBUG_GRAPHICS_ERROR -# define gerr(format, ...) err(format, ##__VA_ARGS__) -# define gllerr(format, ...) llerr(format, ##__VA_ARGS__) +# define gerr(format, ...) _err(format, ##__VA_ARGS__) +# define gllerr(format, ...) _llerr(format, ##__VA_ARGS__) #else # define gerr(x...) # define gllerr(x...) #endif #ifdef CONFIG_DEBUG_GRAPHICS_WARN -# define gwarn(format, ...) warn(format, ##__VA_ARGS__) -# define gllwarn(format, ...) llwarn(format, ##__VA_ARGS__) +# define gwarn(format, ...) _warn(format, ##__VA_ARGS__) +# define gllwarn(format, ...) _llwarn(format, ##__VA_ARGS__) #else # define gwarn(x...) # define gllwarn(x...) #endif #ifdef CONFIG_DEBUG_GRAPHICS_INFO -# define ginfo(format, ...) info(format, ##__VA_ARGS__) -# define gllinfo(format, ...) llinfo(format, ##__VA_ARGS__) +# define ginfo(format, ...) _info(format, ##__VA_ARGS__) +# define gllinfo(format, ...) _llinfo(format, ##__VA_ARGS__) #else # define ginfo(x...) # define gllinfo(x...) #endif #ifdef CONFIG_DEBUG_BINFMT_ERROR -# define berr(format, ...) err(format, ##__VA_ARGS__) -# define bllerr(format, ...) llerr(format, ##__VA_ARGS__) +# define berr(format, ...) _err(format, ##__VA_ARGS__) +# define bllerr(format, ...) _llerr(format, ##__VA_ARGS__) #else # define berr(x...) # define bllerr(x...) #endif #ifdef CONFIG_DEBUG_BINFMT_WARN -# define bwarn(format, ...) warn(format, ##__VA_ARGS__) -# define bllwarn(format, ...) llwarn(format, ##__VA_ARGS__) +# define bwarn(format, ...) _warn(format, ##__VA_ARGS__) +# define bllwarn(format, ...) _llwarn(format, ##__VA_ARGS__) #else # define bwarn(x...) # define bllwarn(x...) #endif #ifdef CONFIG_DEBUG_BINFMT_INFO -# define binfo(format, ...) info(format, ##__VA_ARGS__) -# define bllinfo(format, ...) llinfo(format, ##__VA_ARGS__) +# define binfo(format, ...) _info(format, ##__VA_ARGS__) +# define bllinfo(format, ...) _llinfo(format, ##__VA_ARGS__) #else # define binfo(x...) # define bllinfo(x...) #endif #ifdef CONFIG_DEBUG_LIB_ERROR -# define lerr(format, ...) err(format, ##__VA_ARGS__) -# define lllerr(format, ...) llerr(format, ##__VA_ARGS__) +# define lerr(format, ...) _err(format, ##__VA_ARGS__) +# define lllerr(format, ...) _llerr(format, ##__VA_ARGS__) #else # define lerr(x...) # define lllerr(x...) #endif #ifdef CONFIG_DEBUG_LIB_WARN -# define lwarn(format, ...) warn(format, ##__VA_ARGS__) -# define lllwarn(format, ...) llwarn(format, ##__VA_ARGS__) +# define lwarn(format, ...) _warn(format, ##__VA_ARGS__) +# define lllwarn(format, ...) _llwarn(format, ##__VA_ARGS__) #else # define lwarn(x...) # define lllwarn(x...) #endif #ifdef CONFIG_DEBUG_LIB_INFO -# define linfo(format, ...) info(format, ##__VA_ARGS__) -# define lllinfo(format, ...) llinfo(format, ##__VA_ARGS__) +# define linfo(format, ...) _info(format, ##__VA_ARGS__) +# define lllinfo(format, ...) _llinfo(format, ##__VA_ARGS__) #else # define linfo(x...) # define lllinfo(x...) #endif #ifdef CONFIG_DEBUG_AUDIO_ERROR -# define auderr(format, ...) err(format, ##__VA_ARGS__) -# define audllerr(format, ...) llerr(format, ##__VA_ARGS__) +# define auderr(format, ...) _err(format, ##__VA_ARGS__) +# define audllerr(format, ...) _llerr(format, ##__VA_ARGS__) #else # define auderr(x...) # define audllerr(x...) #endif #ifdef CONFIG_DEBUG_AUDIO_WARN -# define audwarn(format, ...) warn(format, ##__VA_ARGS__) -# define audllwarn(format, ...) llwarn(format, ##__VA_ARGS__) +# define audwarn(format, ...) _warn(format, ##__VA_ARGS__) +# define audllwarn(format, ...) _llwarn(format, ##__VA_ARGS__) #else # define audwarn(x...) # define audllwarn(x...) #endif #ifdef CONFIG_DEBUG_AUDIO_INFO -# define audinfo(format, ...) info(format, ##__VA_ARGS__) -# define audllinfo(format, ...) llinfo(format, ##__VA_ARGS__) +# define audinfo(format, ...) _info(format, ##__VA_ARGS__) +# define audllinfo(format, ...) _llinfo(format, ##__VA_ARGS__) #else # define audinfo(x...) # define audllinfo(x...) #endif #ifdef CONFIG_DEBUG_DMA_ERROR -# define dmaerr(format, ...) err(format, ##__VA_ARGS__) -# define dmallerr(format, ...) llerr(format, ##__VA_ARGS__) +# define dmaerr(format, ...) _err(format, ##__VA_ARGS__) +# define dmallerr(format, ...) _llerr(format, ##__VA_ARGS__) #else # define dmaerr(x...) # define dmallerr(x...) #endif #ifdef CONFIG_DEBUG_DMA_WARN -# define dmawarn(format, ...) warn(format, ##__VA_ARGS__) -# define dmallwarn(format, ...) llwarn(format, ##__VA_ARGS__) +# define dmawarn(format, ...) _warn(format, ##__VA_ARGS__) +# define dmallwarn(format, ...) _llwarn(format, ##__VA_ARGS__) #else # define dmawarn(x...) # define dmallwarn(x...) #endif #ifdef CONFIG_DEBUG_DMA_INFO -# define dmainfo(format, ...) info(format, ##__VA_ARGS__) -# define dmallinfo(format, ...) llinfo(format, ##__VA_ARGS__) +# define dmainfo(format, ...) _info(format, ##__VA_ARGS__) +# define dmallinfo(format, ...) _llinfo(format, ##__VA_ARGS__) #else # define dmainfo(x...) # define dmallinfo(x...) #endif #ifdef CONFIG_DEBUG_IRQ_ERROR -# define irqerr(format, ...) err(format, ##__VA_ARGS__) -# define irqllerr(format, ...) llerr(format, ##__VA_ARGS__) +# define irqerr(format, ...) _err(format, ##__VA_ARGS__) +# define irqllerr(format, ...) _llerr(format, ##__VA_ARGS__) #else # define irqerr(x...) # define irqllerr(x...) #endif #ifdef CONFIG_DEBUG_IRQ_WARN -# define irqwarn(format, ...) warn(format, ##__VA_ARGS__) -# define irqllwarn(format, ...) llwarn(format, ##__VA_ARGS__) +# define irqwarn(format, ...) _warn(format, ##__VA_ARGS__) +# define irqllwarn(format, ...) _llwarn(format, ##__VA_ARGS__) #else # define irqwarn(x...) # define irqllwarn(x...) #endif #ifdef CONFIG_DEBUG_IRQ_INFO -# define irqinfo(format, ...) info(format, ##__VA_ARGS__) -# define irqllinfo(format, ...) llinfo(format, ##__VA_ARGS__) +# define irqinfo(format, ...) _info(format, ##__VA_ARGS__) +# define irqllinfo(format, ...) _llinfo(format, ##__VA_ARGS__) #else # define irqinfo(x...) # define irqllinfo(x...) #endif #ifdef CONFIG_DEBUG_LCD_ERROR -# define lcderr(format, ...) err(format, ##__VA_ARGS__) -# define lcdllerr(format, ...) llerr(format, ##__VA_ARGS__) +# define lcderr(format, ...) _err(format, ##__VA_ARGS__) +# define lcdllerr(format, ...) _llerr(format, ##__VA_ARGS__) #else # define lcderr(x...) # define lcdllerr(x...) #endif #ifdef CONFIG_DEBUG_LCD_WARN -# define lcdwarn(format, ...) warn(format, ##__VA_ARGS__) -# define lcdllwarn(format, ...) llwarn(format, ##__VA_ARGS__) +# define lcdwarn(format, ...) _warn(format, ##__VA_ARGS__) +# define lcdllwarn(format, ...) _llwarn(format, ##__VA_ARGS__) #else # define lcdwarn(x...) # define lcdllwarn(x...) #endif #ifdef CONFIG_DEBUG_LCD_INFO -# define lcdinfo(format, ...) info(format, ##__VA_ARGS__) -# define lcdllinfo(format, ...) llinfo(format, ##__VA_ARGS__) +# define lcdinfo(format, ...) _info(format, ##__VA_ARGS__) +# define lcdllinfo(format, ...) _llinfo(format, ##__VA_ARGS__) #else # define lcdinfo(x...) # define lcdllinfo(x...) #endif #ifdef CONFIG_DEBUG_LEDS_ERROR -# define lederr(format, ...) err(format, ##__VA_ARGS__) -# define ledllerr(format, ...) llerr(format, ##__VA_ARGS__) +# define lederr(format, ...) _err(format, ##__VA_ARGS__) +# define ledllerr(format, ...) _llerr(format, ##__VA_ARGS__) #else # define lederr(x...) # define ledllerr(x...) #endif #ifdef CONFIG_DEBUG_LEDS_WARN -# define ledwarn(format, ...) warn(format, ##__VA_ARGS__) -# define ledllwarn(format, ...) llwarn(format, ##__VA_ARGS__) +# define ledwarn(format, ...) _warn(format, ##__VA_ARGS__) +# define ledllwarn(format, ...) _llwarn(format, ##__VA_ARGS__) #else # define ledwarn(x...) # define ledllwarn(x...) #endif #ifdef CONFIG_DEBUG_LEDS_INFO -# define ledinfo(format, ...) info(format, ##__VA_ARGS__) -# define ledllinfo(format, ...) llinfo(format, ##__VA_ARGS__) +# define ledinfo(format, ...) _info(format, ##__VA_ARGS__) +# define ledllinfo(format, ...) _llinfo(format, ##__VA_ARGS__) #else # define ledinfo(x...) # define ledllinfo(x...) #endif #ifdef CONFIG_DEBUG_GPIO_ERROR -# define gpioerr(format, ...) err(format, ##__VA_ARGS__) -# define gpiollerr(format, ...) llerr(format, ##__VA_ARGS__) +# define gpioerr(format, ...) _err(format, ##__VA_ARGS__) +# define gpiollerr(format, ...) _llerr(format, ##__VA_ARGS__) #else # define gpioerr(x...) # define gpiollerr(x...) #endif #ifdef CONFIG_DEBUG_GPIO_WARN -# define gpiowarn(format, ...) warn(format, ##__VA_ARGS__) -# define gpiollwarn(format, ...) llwarn(format, ##__VA_ARGS__) +# define gpiowarn(format, ...) _warn(format, ##__VA_ARGS__) +# define gpiollwarn(format, ...) _llwarn(format, ##__VA_ARGS__) #else # define gpiowarn(x...) # define gpiollwarn(x...) #endif #ifdef CONFIG_DEBUG_GPIO_INFO -# define gpioinfo(format, ...) info(format, ##__VA_ARGS__) -# define gpiollinfo(format, ...) llinfo(format, ##__VA_ARGS__) +# define gpioinfo(format, ...) _info(format, ##__VA_ARGS__) +# define gpiollinfo(format, ...) _llinfo(format, ##__VA_ARGS__) #else # define gpioinfo(x...) # define gpiollinfo(x...) #endif #ifdef CONFIG_DEBUG_I2C_ERROR -# define i2cerr(format, ...) err(format, ##__VA_ARGS__) -# define i2cllerr(format, ...) llerr(format, ##__VA_ARGS__) +# define i2cerr(format, ...) _err(format, ##__VA_ARGS__) +# define i2cllerr(format, ...) _llerr(format, ##__VA_ARGS__) #else # define i2cerr(x...) # define i2cllerr(x...) #endif #ifdef CONFIG_DEBUG_I2C_WARN -# define i2cwarn(format, ...) warn(format, ##__VA_ARGS__) -# define i2cllwarn(format, ...) llwarn(format, ##__VA_ARGS__) +# define i2cwarn(format, ...) _warn(format, ##__VA_ARGS__) +# define i2cllwarn(format, ...) _llwarn(format, ##__VA_ARGS__) #else # define i2cwarn(x...) # define i2cllwarn(x...) #endif #ifdef CONFIG_DEBUG_I2C_INFO -# define i2cinfo(format, ...) info(format, ##__VA_ARGS__) -# define i2cllinfo(format, ...) llinfo(format, ##__VA_ARGS__) +# define i2cinfo(format, ...) _info(format, ##__VA_ARGS__) +# define i2cllinfo(format, ...) _llinfo(format, ##__VA_ARGS__) #else # define i2cinfo(x...) # define i2cllinfo(x...) #endif #ifdef CONFIG_DEBUG_I2S_ERROR -# define i2serr(format, ...) err(format, ##__VA_ARGS__) -# define i2sllerr(format, ...) llerr(format, ##__VA_ARGS__) +# define i2serr(format, ...) _err(format, ##__VA_ARGS__) +# define i2sllerr(format, ...) _llerr(format, ##__VA_ARGS__) #else # define i2serr(x...) # define i2sllerr(x...) #endif #ifdef CONFIG_DEBUG_I2S_WARN -# define i2swarn(format, ...) warn(format, ##__VA_ARGS__) -# define i2sllwarn(format, ...) llwarn(format, ##__VA_ARGS__) +# define i2swarn(format, ...) _warn(format, ##__VA_ARGS__) +# define i2sllwarn(format, ...) _llwarn(format, ##__VA_ARGS__) #else # define i2swarn(x...) # define i2sllwarn(x...) #endif #ifdef CONFIG_DEBUG_I2S_INFO -# define i2sinfo(format, ...) info(format, ##__VA_ARGS__) -# define i2sllinfo(format, ...) llinfo(format, ##__VA_ARGS__) +# define i2sinfo(format, ...) _info(format, ##__VA_ARGS__) +# define i2sllinfo(format, ...) _llinfo(format, ##__VA_ARGS__) #else # define i2sinfo(x...) # define i2sllinfo(x...) #endif #ifdef CONFIG_DEBUG_PWM_ERROR -# define pwmerr(format, ...) err(format, ##__VA_ARGS__) -# define pwmllerr(format, ...) llerr(format, ##__VA_ARGS__) +# define pwmerr(format, ...) _err(format, ##__VA_ARGS__) +# define pwmllerr(format, ...) _llerr(format, ##__VA_ARGS__) #else # define pwmerr(x...) # define pwmllerr(x...) #endif #ifdef CONFIG_DEBUG_PWM_WARN -# define pwmwarn(format, ...) warn(format, ##__VA_ARGS__) -# define pwmllwarn(format, ...) llwarn(format, ##__VA_ARGS__) +# define pwmwarn(format, ...) _warn(format, ##__VA_ARGS__) +# define pwmllwarn(format, ...) _llwarn(format, ##__VA_ARGS__) #else # define pwmwarn(x...) # define pwmllwarn(x...) #endif #ifdef CONFIG_DEBUG_PWM_INFO -# define pwminfo(format, ...) info(format, ##__VA_ARGS__) -# define pwmllinfo(format, ...) llinfo(format, ##__VA_ARGS__) +# define pwminfo(format, ...) _info(format, ##__VA_ARGS__) +# define pwmllinfo(format, ...) _llinfo(format, ##__VA_ARGS__) #else # define pwminfo(x...) # define pwmllinfo(x...) #endif #ifdef CONFIG_DEBUG_RTC_ERROR -# define rtcerr(format, ...) err(format, ##__VA_ARGS__) -# define rtcllerr(format, ...) llerr(format, ##__VA_ARGS__) +# define rtcerr(format, ...) _err(format, ##__VA_ARGS__) +# define rtcllerr(format, ...) _llerr(format, ##__VA_ARGS__) #else # define rtcerr(x...) # define rtcllerr(x...) #endif #ifdef CONFIG_DEBUG_RTC_WARN -# define rtcwarn(format, ...) warn(format, ##__VA_ARGS__) -# define rtcllwarn(format, ...) llwarn(format, ##__VA_ARGS__) +# define rtcwarn(format, ...) _warn(format, ##__VA_ARGS__) +# define rtcllwarn(format, ...) _llwarn(format, ##__VA_ARGS__) #else # define rtcwarn(x...) # define rtcllwarn(x...) #endif #ifdef CONFIG_DEBUG_RTC_INFO -# define rtcinfo(format, ...) info(format, ##__VA_ARGS__) -# define rtcllinfo(format, ...) llinfo(format, ##__VA_ARGS__) +# define rtcinfo(format, ...) _info(format, ##__VA_ARGS__) +# define rtcllinfo(format, ...) _llinfo(format, ##__VA_ARGS__) #else # define rtcinfo(x...) # define rtcllinfo(x...) #endif #ifdef CONFIG_DEBUG_MEMCARD_ERROR -# define mcerr(format, ...) err(format, ##__VA_ARGS__) -# define mcllerr(format, ...) llerr(format, ##__VA_ARGS__) +# define mcerr(format, ...) _err(format, ##__VA_ARGS__) +# define mcllerr(format, ...) _llerr(format, ##__VA_ARGS__) #else # define mcerr(x...) # define mcllerr(x...) #endif #ifdef CONFIG_DEBUG_MEMCARD_WARN -# define mcwarn(format, ...) warn(format, ##__VA_ARGS__) -# define mcllwarn(format, ...) llwarn(format, ##__VA_ARGS__) +# define mcwarn(format, ...) _warn(format, ##__VA_ARGS__) +# define mcllwarn(format, ...) _llwarn(format, ##__VA_ARGS__) #else # define mcwarn(x...) # define mcllwarn(x...) #endif #ifdef CONFIG_DEBUG_MEMCARD_INFO -# define mcinfo(format, ...) info(format, ##__VA_ARGS__) -# define mcllinfo(format, ...) llinfo(format, ##__VA_ARGS__) +# define mcinfo(format, ...) _info(format, ##__VA_ARGS__) +# define mcllinfo(format, ...) _llinfo(format, ##__VA_ARGS__) #else # define mcinfo(x...) # define mcllinfo(x...) #endif #ifdef CONFIG_DEBUG_SENSORS_ERROR -# define snerr(format, ...) err(format, ##__VA_ARGS__) -# define snllerr(format, ...) llerr(format, ##__VA_ARGS__) +# define snerr(format, ...) _err(format, ##__VA_ARGS__) +# define snllerr(format, ...) _llerr(format, ##__VA_ARGS__) #else # define snerr(x...) # define snllerr(x...) #endif #ifdef CONFIG_DEBUG_SENSORS_WARN -# define snwarn(format, ...) warn(format, ##__VA_ARGS__) -# define snllwarn(format, ...) llwarn(format, ##__VA_ARGS__) +# define snwarn(format, ...) _warn(format, ##__VA_ARGS__) +# define snllwarn(format, ...) _llwarn(format, ##__VA_ARGS__) #else # define snwarn(x...) # define snllwarn(x...) #endif #ifdef CONFIG_DEBUG_SENSORS_INFO -# define sninfo(format, ...) info(format, ##__VA_ARGS__) -# define snllinfo(format, ...) llinfo(format, ##__VA_ARGS__) +# define sninfo(format, ...) _info(format, ##__VA_ARGS__) +# define snllinfo(format, ...) _llinfo(format, ##__VA_ARGS__) #else # define sninfo(x...) # define snllinfo(x...) #endif #ifdef CONFIG_DEBUG_SPI_ERROR -# define spierr(format, ...) err(format, ##__VA_ARGS__) -# define spillerr(format, ...) llerr(format, ##__VA_ARGS__) +# define spierr(format, ...) _err(format, ##__VA_ARGS__) +# define spillerr(format, ...) _llerr(format, ##__VA_ARGS__) #else # define spierr(x...) # define spillerr(x...) #endif #ifdef CONFIG_DEBUG_SPI_WARN -# define spiwarn(format, ...) warn(format, ##__VA_ARGS__) -# define spillwarn(format, ...) llwarn(format, ##__VA_ARGS__) +# define spiwarn(format, ...) _warn(format, ##__VA_ARGS__) +# define spillwarn(format, ...) _llwarn(format, ##__VA_ARGS__) #else # define spiwarn(x...) # define spillwarn(x...) #endif #ifdef CONFIG_DEBUG_SPI_INFO -# define spiinfo(format, ...) info(format, ##__VA_ARGS__) -# define spillinfo(format, ...) llinfo(format, ##__VA_ARGS__) +# define spiinfo(format, ...) _info(format, ##__VA_ARGS__) +# define spillinfo(format, ...) _llinfo(format, ##__VA_ARGS__) #else # define spiinfo(x...) # define spillinfo(x...) #endif #ifdef CONFIG_DEBUG_TIMER_ERROR -# define tmrerr(format, ...) err(format, ##__VA_ARGS__) -# define tmrllerr(format, ...) llerr(format, ##__VA_ARGS__) +# define tmrerr(format, ...) _err(format, ##__VA_ARGS__) +# define tmrllerr(format, ...) _llerr(format, ##__VA_ARGS__) #else # define tmrerr(x...) # define tmrllerr(x...) #endif #ifdef CONFIG_DEBUG_TIMER_WARN -# define tmrwarn(format, ...) warn(format, ##__VA_ARGS__) -# define tmrllwarn(format, ...) llwarn(format, ##__VA_ARGS__) +# define tmrwarn(format, ...) _warn(format, ##__VA_ARGS__) +# define tmrllwarn(format, ...) _llwarn(format, ##__VA_ARGS__) #else # define tmrwarn(x...) # define tmrllwarn(x...) #endif #ifdef CONFIG_DEBUG_TIMER_INFO -# define tmrinfo(format, ...) info(format, ##__VA_ARGS__) -# define tmrllinfo(format, ...) llinfo(format, ##__VA_ARGS__) +# define tmrinfo(format, ...) _info(format, ##__VA_ARGS__) +# define tmrllinfo(format, ...) _llinfo(format, ##__VA_ARGS__) #else # define tmrinfo(x...) # define tmrllinfo(x...) #endif #ifdef CONFIG_DEBUG_USB_ERROR -# define uerr(format, ...) err(format, ##__VA_ARGS__) -# define ullerr(format, ...) llerr(format, ##__VA_ARGS__) +# define uerr(format, ...) _err(format, ##__VA_ARGS__) +# define ullerr(format, ...) _llerr(format, ##__VA_ARGS__) #else # define uerr(x...) # define ullerr(x...) #endif #ifdef CONFIG_DEBUG_USB_WARN -# define uwarn(format, ...) warn(format, ##__VA_ARGS__) -# define ullwarn(format, ...) llwarn(format, ##__VA_ARGS__) +# define uwarn(format, ...) _warn(format, ##__VA_ARGS__) +# define ullwarn(format, ...) _llwarn(format, ##__VA_ARGS__) #else # define uwarn(x...) # define ullwarn(x...) #endif #ifdef CONFIG_DEBUG_USB_INFO -# define uinfo(format, ...) info(format, ##__VA_ARGS__) -# define ullinfo(format, ...) llinfo(format, ##__VA_ARGS__) +# define uinfo(format, ...) _info(format, ##__VA_ARGS__) +# define ullinfo(format, ...) _llinfo(format, ##__VA_ARGS__) #else # define uinfo(x...) # define ullinfo(x...) #endif #ifdef CONFIG_DEBUG_WATCHDOG_ERROR -# define wderr(format, ...) err(format, ##__VA_ARGS__) -# define wdllerr(format, ...) llerr(format, ##__VA_ARGS__) +# define wderr(format, ...) _err(format, ##__VA_ARGS__) +# define wdllerr(format, ...) _llerr(format, ##__VA_ARGS__) #else # define wderr(x...) # define wdllerr(x...) #endif #ifdef CONFIG_DEBUG_WATCHDOG_WARN -# define wdwarn(format, ...) warn(format, ##__VA_ARGS__) -# define wdllwarn(format, ...) llwarn(format, ##__VA_ARGS__) +# define wdwarn(format, ...) _warn(format, ##__VA_ARGS__) +# define wdllwarn(format, ...) _llwarn(format, ##__VA_ARGS__) #else # define wdwarn(x...) # define wdllwarn(x...) #endif #ifdef CONFIG_DEBUG_WATCHDOG_INFO -# define wdinfo(format, ...) info(format, ##__VA_ARGS__) -# define wdllinfo(format, ...) llinfo(format, ##__VA_ARGS__) +# define wdinfo(format, ...) _info(format, ##__VA_ARGS__) +# define wdllinfo(format, ...) _llinfo(format, ##__VA_ARGS__) #else # define wdinfo(x...) # define wdllinfo(x...) @@ -895,724 +897,724 @@ #ifdef CONFIG_DEBUG_ERROR # ifndef CONFIG_ARCH_LOWPUTC -# define llerr (void) +# define _llerr (void) # endif #else -# define err (void) -# define llerr (void) +# define _err (void) +# define _llerr (void) #endif #ifdef CONFIG_DEBUG_WARN # ifndef CONFIG_ARCH_LOWPUTC -# define llwarn (void) +# define _llwarn (void) # endif #else -# define warn (void) -# define llwarn (void) +# define _warn (void) +# define _llwarn (void) #endif #ifdef CONFIG_DEBUG_INFO # ifndef CONFIG_ARCH_LOWPUTC -# define llinfo (void) +# define _llinfo (void) # endif #else -# define info (void) -# define llinfo (void) +# define _info (void) +# define _llinfo (void) #endif /* Subsystem specific debug */ #ifdef CONFIG_DEBUG_MM_ERROR -# define merr err -# define mllerr llerr +# define merr _err +# define mllerr _llerr #else # define merr (void) # define mllerr (void) #endif #ifdef CONFIG_DEBUG_MM_WARN -# define mwarn warn -# define mllwarn llwarn +# define mwarn _warn +# define mllwarn _llwarn #else # define mwarn (void) # define mllwarn (void) #endif #ifdef CONFIG_DEBUG_MM_INFO -# define minfo info -# define mllinfo llinfo +# define minfo _info +# define mllinfo _llinfo #else # define minfo (void) # define mllinfo (void) #endif #ifdef CONFIG_DEBUG_SCHED_ERROR -# define serr err -# define sllerr llerr +# define serr _err +# define sllerr _llerr #else # define serr (void) # define sllerr (void) #endif #ifdef CONFIG_DEBUG_SCHED_WARN -# define swarn warn -# define sllwarn llwarn +# define swarn _warn +# define sllwarn _llwarn #else # define swarn (void) # define sllwarn (void) #endif #ifdef CONFIG_DEBUG_SCHED_INFO -# define sinfo info -# define sllinfo llinfo +# define sinfo _info +# define sllinfo _llinfo #else # define sinfo (void) # define sllinfo (void) #endif #ifdef CONFIG_DEBUG_SYSCALL_ERROR -# define svcerr err -# define svcllerr llerr +# define svcerr _err +# define svcllerr _llerr #else # define svcerr (void) # define svcllerr (void) #endif #ifdef CONFIG_DEBUG_SYSCALL_WARN -# define svcwarn warn -# define svcllwarn llwarn +# define svcwarn _warn +# define svcllwarn _llwarn #else # define svcwarn (void) # define svcllwarn (void) #endif #ifdef CONFIG_DEBUG_SYSCALL_INFO -# define svcinfo info -# define svcllinfo llinfo +# define svcinfo _info +# define svcllinfo _llinfo #else # define svcinfo (void) # define svcllinfo (void) #endif #ifdef CONFIG_DEBUG_PAGING_ERROR -# define pgerr err -# define pgllerr llerr +# define pgerr _err +# define pgllerr _llerr #else # define pgerr (void) # define pgllerr (void) #endif #ifdef CONFIG_DEBUG_PAGING_WARN -# define pgwarn warn -# define pgllwarn llwarn +# define pgwarn _warn +# define pgllwarn _llwarn #else # define pgwarn (void) # define pgllwarn (void) #endif #ifdef CONFIG_DEBUG_PAGING_INFO -# define pginfo info -# define pgllinfo llinfo +# define pginfo _info +# define pgllinfo _llinfo #else # define pginfo (void) # define pgllinfo (void) #endif #ifdef CONFIG_DEBUG_NET_ERROR -# define nerr err -# define nllerr llerr +# define nerr _err +# define nllerr _llerr #else # define nerr (void) # define nllerr (void) #endif #ifdef CONFIG_DEBUG_NET_WARN -# define nwarn warn -# define nllwarn llwarn +# define nwarn _warn +# define nllwarn _llwarn #else # define nwarn (void) # define nllwarn (void) #endif #ifdef CONFIG_DEBUG_NET_INFO -# define ninfo info -# define nllinfo llinfo +# define ninfo _info +# define nllinfo _llinfo #else # define ninfo (void) # define nllinfo (void) #endif #ifdef CONFIG_DEBUG_FS_ERROR -# define ferr err -# define fllerr llerr +# define ferr _err +# define fllerr _llerr #else # define ferr (void) # define fllerr (void) #endif #ifdef CONFIG_DEBUG_FS_WARN -# define fwarn warn -# define fllwarn llwarn +# define fwarn _warn +# define fllwarn _llwarn #else # define fwarn (void) # define fllwarn (void) #endif #ifdef CONFIG_DEBUG_FS_INFO -# define finfo info -# define fllinfo llinfo +# define finfo _info +# define fllinfo _llinfo #else # define finfo (void) # define fllinfo (void) #endif #ifdef CONFIG_DEBUG_CRYPTO_ERROR -# define crypterr err -# define cryptllerr llerr +# define crypterr _err +# define cryptllerr _llerr #else # define crypterr (void) # define cryptllerr (void) #endif #ifdef CONFIG_DEBUG_CRYPTO_WARN -# define cryptwarn warn -# define cryptllwarn llwarn +# define cryptwarn _warn +# define cryptllwarn _llwarn #else # define cryptwarn (void) # define cryptllwarn (void) #endif #ifdef CONFIG_DEBUG_CRYPTO_INFO -# define cryptinfo info -# define cryptllinfo llinfo +# define cryptinfo _info +# define cryptllinfo _llinfo #else # define cryptinfo(x...) # define cryptllinfo(x...) #endif #ifdef CONFIG_DEBUG_INPUT_ERROR -# define ierr err -# define illerr llerr +# define ierr _err +# define illerr _llerr #else # define ierr (void) # define illerr (void) #endif #ifdef CONFIG_DEBUG_INPUT_WARN -# define iwarn warn -# define illwarn llwarn +# define iwarn _warn +# define illwarn _llwarn #else # define iwarn (void) # define illwarn (void) #endif #ifdef CONFIG_DEBUG_INPUT_INFO -# define iinfo info -# define illinfo llinfo +# define iinfo _info +# define illinfo _llinfo #else # define iinfo (void) # define illinfo (void) #endif #ifdef CONFIG_DEBUG_ANALOG_ERROR -# define aerr err -# define allerr llerr +# define aerr _err +# define allerr _llerr #else # define aerr (void) # define allerr (void) #endif #ifdef CONFIG_DEBUG_ANALOG_WARN -# define awarn warn -# define allwarn llwarn +# define awarn _warn +# define allwarn _llwarn #else # define awarn (void) # define allwarn (void) #endif #ifdef CONFIG_DEBUG_ANALOG_INFO -# define ainfo info -# define allinfo llinfo +# define ainfo _info +# define allinfo _llinfo #else # define ainfo (void) # define allinfo (void) #endif #ifdef CONFIG_DEBUG_CAN_ERROR -# define canerr err -# define canllerr llerr +# define canerr _err +# define canllerr _llerr #else -# define canerr (void) -# define canllerr (void) +# define canerr (void) +# define canllerr (void) #endif #ifdef CONFIG_DEBUG_CAN_WARN -# define canwarn warn -# define canllwarn llwarn +# define canwarn _warn +# define canllwarn _llwarn #else -# define canwarn (void) -# define canllwarn (void) +# define canwarn (void) +# define canllwarn (void) #endif #ifdef CONFIG_DEBUG_CAN_INFO -# define caninfo info -# define canllinfo llinfo +# define caninfo _info +# define canllinfo _llinfo #else -# define caninfo (void) -# define canllinfo (void) +# define caninfo (void) +# define canllinfo (void) #endif #ifdef CONFIG_DEBUG_GRAPHICS_ERROR -# define gerr err -# define gllerr llerr +# define gerr _err +# define gllerr _llerr #else # define gerr (void) # define gllerr (void) #endif #ifdef CONFIG_DEBUG_GRAPHICS_WARN -# define gwarn warn -# define gllwarn llwarn +# define gwarn _warn +# define gllwarn _llwarn #else # define gwarn (void) # define gllwarn (void) #endif #ifdef CONFIG_DEBUG_GRAPHICS_INFO -# define ginfo info -# define gllinfo llinfo +# define ginfo _info +# define gllinfo _llinfo #else # define ginfo (void) # define gllinfo (void) #endif #ifdef CONFIG_DEBUG_BINFMT_ERROR -# define berr err -# define bllerr llerr +# define berr _err +# define bllerr _llerr #else # define berr (void) # define bllerr (void) #endif #ifdef CONFIG_DEBUG_BINFMT_WARN -# define bwarn warn -# define bllwarn llwarn +# define bwarn _warn +# define bllwarn _llwarn #else # define bwarn (void) # define bllwarn (void) #endif #ifdef CONFIG_DEBUG_BINFMT_INFO -# define binfo info -# define bllinfo llinfo +# define binfo _info +# define bllinfo _llinfo #else # define binfo (void) # define bllinfo (void) #endif #ifdef CONFIG_DEBUG_LIB_ERROR -# define lerr err -# define lllerr llerr +# define lerr _err +# define lllerr _llerr #else # define lerr (void) # define lllerr (void) #endif #ifdef CONFIG_DEBUG_LIB_WARN -# define lwarn warn -# define lllwarn llwarn +# define lwarn _warn +# define lllwarn _llwarn #else # define lwarn (void) # define lllwarn (void) #endif #ifdef CONFIG_DEBUG_LIB_INFO -# define linfo info -# define lllinfo llinfo +# define linfo _info +# define lllinfo _llinfo #else # define linfo (void) # define lllinfo (void) #endif #ifdef CONFIG_DEBUG_AUDIO_ERROR -# define auderr err -# define audllerr llerr +# define auderr _err +# define audllerr _llerr #else # define auderr (void) # define audllerr (void) #endif #ifdef CONFIG_DEBUG_AUDIO_WARN -# define audwarn warn -# define audllwarn llwarn +# define audwarn _warn +# define audllwarn _llwarn #else # define audwarn (void) # define audllwarn (void) #endif #ifdef CONFIG_DEBUG_AUDIO_INFO -# define audinfo info -# define audllinfo llinfo +# define audinfo _info +# define audllinfo _llinfo #else # define audinfo (void) # define audllinfo (void) #endif #ifdef CONFIG_DEBUG_DMA_ERROR -# define dmaerr err -# define dmallerr llerr +# define dmaerr _err +# define dmallerr _llerr #else # define dmaerr (void) # define dmallerr (void) #endif #ifdef CONFIG_DEBUG_DMA_WARN -# define dmawarn warn -# define dmallwarn llwarn +# define dmawarn _warn +# define dmallwarn _llwarn #else # define dmawarn (void) # define dmallwarn (void) #endif #ifdef CONFIG_DEBUG_DMA_INFO -# define dmainfo info -# define dmallinfo llinfo +# define dmainfo _info +# define dmallinfo _llinfo #else # define dmainfo (void) # define dmallinfo (void) #endif #ifdef CONFIG_DEBUG_IRQ_ERROR -# define irqerr err -# define irqllerr llerr +# define irqerr _err +# define irqllerr _llerr #else # define irqerr (void) # define irqllerr (void) #endif #ifdef CONFIG_DEBUG_IRQ_WARN -# define irqwarn warn -# define irqllwarn llwarn +# define irqwarn _warn +# define irqllwarn _llwarn #else # define irqwarn (void) # define irqllwarn (void) #endif #ifdef CONFIG_DEBUG_IRQ_INFO -# define irqinfo info -# define irqllinfo llinfo +# define irqinfo _info +# define irqllinfo _llinfo #else # define irqinfo (void) # define irqllinfo (void) #endif #ifdef CONFIG_DEBUG_LCD_ERROR -# define lcderr err -# define lcdllerr llerr +# define lcderr _err +# define lcdllerr _llerr #else # define lcderr (void) # define lcdllerr (void) #endif #ifdef CONFIG_DEBUG_LCD_WARN -# define lcdwarn warn -# define lcdllwarn llwarn +# define lcdwarn _warn +# define lcdllwarn _llwarn #else # define lcdwarn (void) # define lcdllwarn (void) #endif #ifdef CONFIG_DEBUG_LCD_INFO -# define lcdinfo info -# define lcdllinfo llinfo +# define lcdinfo _info +# define lcdllinfo _llinfo #else # define lcdinfo (void) # define lcdllinfo (void) #endif #ifdef CONFIG_DEBUG_LEDS_ERROR -# define lederr err -# define ledllerr llerr +# define lederr _err +# define ledllerr _llerr #else # define lederr (void) # define ledllerr (void) #endif #ifdef CONFIG_DEBUG_LEDS_WARN -# define ledwarn warn -# define ledllwarn llwarn +# define ledwarn _warn +# define ledllwarn _llwarn #else # define ledwarn (void) # define ledllwarn (void) #endif #ifdef CONFIG_DEBUG_LEDS_INFO -# define ledinfo info -# define ledllinfo llinfo +# define ledinfo _info +# define ledllinfo _llinfo #else # define ledinfo (void) # define ledllinfo (void) #endif #ifdef CONFIG_DEBUG_GPIO_ERROR -# define gpioerr err -# define gpiollerr llerr +# define gpioerr _err +# define gpiollerr _llerr #else # define gpioerr (void) # define gpiollerr (void) #endif #ifdef CONFIG_DEBUG_GPIO_WARN -# define gpiowarn warn -# define gpiollwarn llwarn +# define gpiowarn _warn +# define gpiollwarn _llwarn #else # define gpiowarn (void) # define gpiollwarn (void) #endif #ifdef CONFIG_DEBUG_GPIO_INFO -# define gpioinfo info -# define gpiollinfo llinfo +# define gpioinfo _info +# define gpiollinfo _llinfo #else # define gpioinfo (void) # define gpiollinfo (void) #endif #ifdef CONFIG_DEBUG_I2C_ERROR -# define i2cerr err -# define i2cllerr llerr +# define i2cerr _err +# define i2cllerr _llerr #else # define i2cerr (void) # define i2cllerr (void) #endif #ifdef CONFIG_DEBUG_I2C_WARN -# define i2cwarn warn -# define i2cllwarn llwarn +# define i2cwarn _warn +# define i2cllwarn _llwarn #else # define i2cwarn (void) # define i2cllwarn (void) #endif #ifdef CONFIG_DEBUG_I2C_INFO -# define i2cinfo info -# define i2cllinfo llinfo +# define i2cinfo _info +# define i2cllinfo _llinfo #else # define i2cinfo (void) # define i2cllinfo (void) #endif #ifdef CONFIG_DEBUG_I2S_ERROR -# define i2serr err -# define i2sllerr llerr +# define i2serr _err +# define i2sllerr _llerr #else # define i2serr (void) # define i2sllerr (void) #endif #ifdef CONFIG_DEBUG_I2S_WARN -# define i2swarn warn -# define i2sllwarn llwarn +# define i2swarn _warn +# define i2sllwarn _llwarn #else # define i2swarn (void) # define i2sllwarn (void) #endif #ifdef CONFIG_DEBUG_I2S_INFO -# define i2sinfo info -# define i2sllinfo llinfo +# define i2sinfo _info +# define i2sllinfo _llinfo #else # define i2sinfo (void) # define i2sllinfo (void) #endif #ifdef CONFIG_DEBUG_PWM_ERROR -# define pwmerr err -# define pwmllerr llerr +# define pwmerr _err +# define pwmllerr _llerr #else # define pwmerr (void) # define pwmllerr (void) #endif #ifdef CONFIG_DEBUG_PWM_WARN -# define pwmwarn warn -# define pwmllwarn llwarn +# define pwmwarn _warn +# define pwmllwarn _llwarn #else # define pwmwarn (void) # define pwmllwarn (void) #endif #ifdef CONFIG_DEBUG_PWM_INFO -# define pwminfo info -# define pwmllinfo llinfo +# define pwminfo _info +# define pwmllinfo _llinfo #else # define pwminfo (void) # define pwmllinfo (void) #endif #ifdef CONFIG_DEBUG_RTC_ERROR -# define rtcerr err -# define rtcllerr llerr +# define rtcerr _err +# define rtcllerr _llerr #else # define rtcerr (void) # define rtcllerr (void) #endif #ifdef CONFIG_DEBUG_RTC_WARN -# define rtcwarn warn -# define rtcllwarn llwarn +# define rtcwarn _warn +# define rtcllwarn _llwarn #else # define rtcwarn (void) # define rtcllwarn (void) #endif #ifdef CONFIG_DEBUG_RTC_INFO -# define rtcinfo info -# define rtcllinfo llinfo +# define rtcinfo _info +# define rtcllinfo _llinfo #else # define rtcinfo (void) # define rtcllinfo (void) #endif #ifdef CONFIG_DEBUG_MEMCARD_ERROR -# define mcerr err -# define mcllerr llerr +# define mcerr _err +# define mcllerr _llerr #else # define mcerr (void) # define mcllerr (void) #endif #ifdef CONFIG_DEBUG_MEMCARD_WARN -# define mcwarn warn -# define mcllwarn llwarn +# define mcwarn _warn +# define mcllwarn _llwarn #else # define mcwarn (void) # define mcllwarn (void) #endif #ifdef CONFIG_DEBUG_MEMCARD_INFO -# define mcinfo info -# define mcllinfo llinfo +# define mcinfo _info +# define mcllinfo _llinfo #else # define mcinfo (void) # define mcllinfo (void) #endif #ifdef CONFIG_DEBUG_SENSORS_ERROR -# define snerr err -# define snllerr llerr +# define snerr _err +# define snllerr _llerr #else # define snerr (void) # define snllerr (void) #endif #ifdef CONFIG_DEBUG_SENSORS_WARN -# define snwarn warn -# define snllwarn llwarn +# define snwarn _warn +# define snllwarn _llwarn #else # define snwarn (void) # define snllwarn (void) #endif #ifdef CONFIG_DEBUG_SENSORS_INFO -# define sninfo info -# define snllinfo llinfo +# define sninfo _info +# define snllinfo _llinfo #else # define sninfo (void) # define snllinfo (void) #endif #ifdef CONFIG_DEBUG_SPI_ERROR -# define spierr err -# define spillerr llerr +# define spierr _err +# define spillerr _llerr #else # define spierr (void) # define spillerr (void) #endif #ifdef CONFIG_DEBUG_SPI_WARN -# define spiwarn warn -# define spillwarn llwarn +# define spiwarn _warn +# define spillwarn _llwarn #else # define spiwarn (void) # define spillwarn (void) #endif #ifdef CONFIG_DEBUG_SPI_INFO -# define spiinfo info -# define spillinfo llinfo +# define spiinfo _info +# define spillinfo _llinfo #else # define spiinfo (void) # define spillinfo (void) #endif #ifdef CONFIG_DEBUG_TIMER_ERROR -# define tmrerr err -# define tmrllerr llerr +# define tmrerr _err +# define tmrllerr _llerr #else # define tmrerr (void) # define tmrllerr (void) #endif #ifdef CONFIG_DEBUG_TIMER_WARN -# define tmrwarn warn -# define tmrllwarn llwarn +# define tmrwarn _warn +# define tmrllwarn _llwarn #else # define tmrwarn (void) # define tmrllwarn (void) #endif #ifdef CONFIG_DEBUG_TIMER_INFO -# define tmrinfo info -# define tmrllinfo llinfo +# define tmrinfo _info +# define tmrllinfo _llinfo #else # define tmrinfo (void) # define tmrllinfo (void) #endif #ifdef CONFIG_DEBUG_USB_ERROR -# define uerr err -# define ullerr llerr +# define uerr _err +# define ullerr _llerr #else # define uerr (void) # define ullerr (void) #endif #ifdef CONFIG_DEBUG_USB_WARN -# define uwarn warn -# define ullwarn llwarn +# define uwarn _warn +# define ullwarn _llwarn #else # define uwarn (void) # define ullwarn (void) #endif #ifdef CONFIG_DEBUG_USB_INFO -# define uinfo info -# define ullinfo llinfo +# define uinfo _info +# define ullinfo _llinfo #else # define uinfo (void) # define ullinfo (void) #endif #ifdef CONFIG_DEBUG_WATCHDOG_ERROR -# define wderr err -# define wdllerr llerr +# define wderr _err +# define wdllerr _llerr #else # define wderr (void) # define wdllerr (void) #endif #ifdef CONFIG_DEBUG_WATCHDOG_WARN -# define wdwarn warn -# define wdllwarn llwarn +# define wdwarn _warn +# define wdllwarn _llwarn #else # define wdwarn (void) # define wdllwarn (void) #endif #ifdef CONFIG_DEBUG_WATCHDOG_INFO -# define wdinfo info -# define wdllinfo llinfo +# define wdinfo _info +# define wdllinfo _llinfo #else # define wdinfo (void) # define wdllinfo (void) @@ -1897,26 +1899,26 @@ int alert(const char *format, ...); #endif #ifdef CONFIG_DEBUG_ERROR -int err(const char *format, ...); +int _err(const char *format, ...); # ifdef CONFIG_ARCH_LOWPUTC -int llerr(const char *format, ...); +int _llerr(const char *format, ...); # endif #endif /* CONFIG_DEBUG_ERROR */ #ifdef CONFIG_DEBUG_WARN -int warn(const char *format, ...); +int _warn(const char *format, ...); # ifdef CONFIG_ARCH_LOWPUTC -int llwarn(const char *format, ...); +int _llwarn(const char *format, ...); # endif #endif /* CONFIG_DEBUG_WARN */ #ifdef CONFIG_DEBUG_INFO -int info(const char *format, ...); +int _info(const char *format, ...); # ifdef CONFIG_ARCH_LOWPUTC -int llinfo(const char *format, ...); +int _llinfo(const char *format, ...); # endif #endif /* CONFIG_DEBUG_INFO */ #endif /* CONFIG_CPP_HAVE_VARARGS */ diff --git a/include/nuttx/mm/shm.h b/include/nuttx/mm/shm.h index 80d36f2f94..35f19c50d2 100644 --- a/include/nuttx/mm/shm.h +++ b/include/nuttx/mm/shm.h @@ -77,16 +77,16 @@ #ifdef CONFIG_CPP_HAVE_VARARGS # ifdef CONFIG_DEBUG_SHM -# define shmerr(format, ...) err(format, ##__VA_ARGS__) -# define shminfo(format, ...) info(format, ##__VA_ARGS__) +# define shmerr(format, ...) _err(format, ##__VA_ARGS__) +# define shminfo(format, ...) _info(format, ##__VA_ARGS__) # else # define shmerr(format, ...) merr(format, ##__VA_ARGS__) # define shminfo(format, ...) minfo(format, ##__VA_ARGS__) # endif #else # ifdef CONFIG_DEBUG_SHM -# define shmerr err -# define shminfo info +# define shmerr _err +# define shminfo _info # else # define shmerr (void) # define shminfo (void) diff --git a/include/nuttx/wireless/nrf24l01.h b/include/nuttx/wireless/nrf24l01.h index a166ebf034..4bb1482757 100644 --- a/include/nuttx/wireless/nrf24l01.h +++ b/include/nuttx/wireless/nrf24l01.h @@ -91,10 +91,10 @@ /* NRF24L01 debug */ #ifdef NRF24L01_DEBUG -# define werr(format, ...) err(format, ##__VA_ARGS__) -# define wllerr(format, ...) llerr(format, ##__VA_ARGS__) -# define winfo(format, ...) info(format, ##__VA_ARGS__) -# define wllinfo(format, ...) llinfo(format, ##__VA_ARGS__) +# define werr(format, ...) _err(format, ##__VA_ARGS__) +# define wllerr(format, ...) _llerr(format, ##__VA_ARGS__) +# define winfo(format, ...) _info(format, ##__VA_ARGS__) +# define wllinfo(format, ...) _llinfo(format, ##__VA_ARGS__) #else # define werr(x...) # define wllerr(x...) diff --git a/include/sys/wait.h b/include/sys/wait.h index b46e302879..500c8b51f9 100644 --- a/include/sys/wait.h +++ b/include/sys/wait.h @@ -50,7 +50,7 @@ ****************************************************************************/ /* The following are provided for analysis of returned status values. - * Encoded is as follows as 2 bytes of info(MS) then two bytes of code (LS). + * Encoded is as follows as 2 bytes of _info(MS) then two bytes of code (LS). * Code: * 0 - Child has exited, info is the exit code. * Other values - Not implemented diff --git a/libc/libc.csv b/libc/libc.csv index 87a98f778d..2c9eabe0b9 100644 --- a/libc/libc.csv +++ b/libc/libc.csv @@ -26,7 +26,7 @@ "dq_rem","queue.h","","void","FAR dq_entry_t *","dq_queue_t *" "dq_remfirst","queue.h","","FAR dq_entry_t","dq_queue_t *" "dq_remlast","queue.h","","FAR dq_entry_t","dq_queue_t *" -"err","debug.h","!defined(CONFIG_CPP_HAVE_VARARGS) && defined(CONFIG_DEBUG_ERROR)","int","const char *","..." +"_err","debug.h","!defined(CONFIG_CPP_HAVE_VARARGS) && defined(CONFIG_DEBUG_ERROR)","int","const char *","..." "ether_ntoa","netinet/ether.h","","FAR char","FAR const struct ether_addr *" "fclose","stdio.h","CONFIG_NFILE_DESCRIPTORS > 0 && CONFIG_NFILE_STREAMS > 0","int","FAR FILE *" "fdopen","stdio.h","CONFIG_NFILE_DESCRIPTORS > 0 && CONFIG_NFILE_STREAMS > 0","FAR FILE","int","FAR const char *" @@ -64,9 +64,9 @@ "lib_dumpbuffer","debug.h","","void","FAR const char *","FAR const uint8_t *","unsigned int" "lio_listio","aio.h","defined(CONFIG_FS_AIO)","int","int","FAR struct aiocb *const []|FAR struct aiocb *const *","int","FAR struct sigevent *" "llabs","stdlib.h","defined(CONFIG_HAVE_LONG_LONG)","long long int","long long int" -"llerr","debug.h","!defined(CONFIG_CPP_HAVE_VARARGS) && defined(CONFIG_DEBUG_ERROR) && defined(CONFIG_ARCH_LOWPUTC)","int","const char *","..." -"llinfo","debug.h","!defined(CONFIG_CPP_HAVE_VARARGS) && defined(CONFIG_DEBUG_INFO) && defined(CONFIG_ARCH_LOWPUTC)","int","const char *","..." -"llwarn","debug.h","!defined(CONFIG_CPP_HAVE_VARARGS) && defined(CONFIG_DEBUG_WARN) && defined(CONFIG_ARCH_LOWPUTC)","int","const char *","..." +"_llerr","debug.h","!defined(CONFIG_CPP_HAVE_VARARGS) && defined(CONFIG_DEBUG_ERROR) && defined(CONFIG_ARCH_LOWPUTC)","int","const char *","..." +"_llinfo","debug.h","!defined(CONFIG_CPP_HAVE_VARARGS) && defined(CONFIG_DEBUG_INFO) && defined(CONFIG_ARCH_LOWPUTC)","int","const char *","..." +"_llwarn","debug.h","!defined(CONFIG_CPP_HAVE_VARARGS) && defined(CONFIG_DEBUG_WARN) && defined(CONFIG_ARCH_LOWPUTC)","int","const char *","..." "lowsyslog","syslog.h","","int","int","FAR const char *","..." "lowvsyslog","syslog.h","","int","int","FAR const char *","va_list" "match","nuttx/regex.h","","int","const char *","const char *" @@ -169,11 +169,11 @@ "ub16sqr","fixedmath.h","!defined(CONFIG_HAVE_LONG_LONG)","ub16_t","ub16_t" "ungetc","stdio.h","CONFIG_NFILE_DESCRIPTORS > 0 && CONFIG_NFILE_STREAMS > 0","int","int","FAR FILE *" "usleep","unistd.h","!defined(CONFIG_DISABLE_SIGNALS)","int","int","FAR FILE *" -"info","debug.h","!defined(CONFIG_CPP_HAVE_VARARGS) && defined(CONFIG_DEBUG_INFO)","int","const char *","..." +"_info","debug.h","!defined(CONFIG_CPP_HAVE_VARARGS) && defined(CONFIG_DEBUG_INFO)","int","const char *","..." "vfprintf","stdio.h","CONFIG_NFILE_DESCRIPTORS > 0 && CONFIG_NFILE_STREAMS > 0","int","FAR FILE *","const char *","va_list" "vprintf","stdio.h","CONFIG_NFILE_DESCRIPTORS > 0 && CONFIG_NFILE_STREAMS > 0","int","FAR const char *","va_list" "vsnprintf","stdio.h","","int","FAR char *","size_t","const char *","va_list" "vsprintf","stdio.h","","int","FAR char *","const char *","va_list" "vsscanf","stdio.h","","int","char *","const char *","va_list" "vsyslog","syslog.h","","int","int","FAR const char *","va_list" -"warn","debug.h","!defined(CONFIG_CPP_HAVE_VARARGS) && defined(CONFIG_DEBUG_WARN)","int","const char *","..." +"_warn","debug.h","!defined(CONFIG_CPP_HAVE_VARARGS) && defined(CONFIG_DEBUG_WARN)","int","const char *","..." diff --git a/libc/misc/lib_debug.c b/libc/misc/lib_debug.c index cd1e703c09..7e6a33f8aa 100644 --- a/libc/misc/lib_debug.c +++ b/libc/misc/lib_debug.c @@ -51,7 +51,7 @@ ****************************************************************************/ /**************************************************************************** - * Name: alert, err, llerr, warn, llwarn, info, llinfo + * Name: alert, err, llerr, warn, llwarn, info, _llinfo * * Description: * If the cross-compiler's pre-processor does not support variable @@ -60,7 +60,7 @@ ****************************************************************************/ #ifdef CONFIG_ARCH_LOWPUTC -int alert(const char *format, ...) +int _alert(const char *format, ...) { va_list ap; int ret; @@ -74,7 +74,7 @@ int alert(const char *format, ...) #endif /* CONFIG_ARCH_LOWPUTC */ #ifdef CONFIG_DEBUG_FEATURES -int err(const char *format, ...) +int _err(const char *format, ...) { va_list ap; int ret; @@ -87,7 +87,7 @@ int err(const char *format, ...) } #ifdef CONFIG_ARCH_LOWPUTC -int llerr(const char *format, ...) +int _llerr(const char *format, ...) { va_list ap; int ret; @@ -102,7 +102,7 @@ int llerr(const char *format, ...) #endif /* CONFIG_DEBUG_FEATURES */ #ifdef CONFIG_DEBUG_WARN -int warn(const char *format, ...) +int _warn(const char *format, ...) { va_list ap; int ret; @@ -115,7 +115,7 @@ int warn(const char *format, ...) } #ifdef CONFIG_ARCH_LOWPUTC -int llwarn(const char *format, ...) +int _llwarn(const char *format, ...) { va_list ap; int ret; @@ -130,7 +130,7 @@ int llwarn(const char *format, ...) #endif /* CONFIG_DEBUG_INFO */ #ifdef CONFIG_DEBUG_INFO -int info(const char *format, ...) +int _info(const char *format, ...) { va_list ap; int ret; @@ -143,7 +143,7 @@ int info(const char *format, ...) } #ifdef CONFIG_ARCH_LOWPUTC -int llinfo(const char *format, ...) +int _llinfo(const char *format, ...) { va_list ap; int ret; diff --git a/libc/spawn/lib_psa_dump.c b/libc/spawn/lib_psa_dump.c index 81ccc7a675..9a66501556 100644 --- a/libc/spawn/lib_psa_dump.c +++ b/libc/spawn/lib_psa_dump.c @@ -74,63 +74,63 @@ void posix_spawnattr_dump(posix_spawnattr_t *attr) { #ifdef CONFIG_DEBUG_ERROR - err("attr[%p]:\n", attr); - err(" flags: %04x\n", attr->flags); + _err("attr[%p]:\n", attr); + _err(" flags: %04x\n", attr->flags); if (attr->flags == 0) { - err(" None\n"); + _err(" None\n"); } else { if ((attr->flags & POSIX_SPAWN_RESETIDS) != 0) { - err(" POSIX_SPAWN_RESETIDS\n"); + _err(" POSIX_SPAWN_RESETIDS\n"); } if ((attr->flags & POSIX_SPAWN_SETPGROUP) != 0) { - err(" POSIX_SPAWN_SETPGROUP\n"); + _err(" POSIX_SPAWN_SETPGROUP\n"); } if ((attr->flags & POSIX_SPAWN_SETSCHEDPARAM) != 0) { - err(" POSIX_SPAWN_SETSCHEDPARAM\n"); + _err(" POSIX_SPAWN_SETSCHEDPARAM\n"); } if ((attr->flags & POSIX_SPAWN_SETSCHEDULER) != 0) { - err(" POSIX_SPAWN_SETSCHEDULER\n"); + _err(" POSIX_SPAWN_SETSCHEDULER\n"); } if ((attr->flags & POSIX_SPAWN_SETSIGDEF) != 0) { - err(" POSIX_SPAWN_SETSIGDEF\n"); + _err(" POSIX_SPAWN_SETSIGDEF\n"); } if ((attr->flags & POSIX_SPAWN_SETSIGMASK) != 0) { - err(" POSIX_SPAWN_SETSIGMASK\n"); + _err(" POSIX_SPAWN_SETSIGMASK\n"); } } - err(" priority: %d\n", attr->priority); + _err(" priority: %d\n", attr->priority); - err(" policy: %d\n", attr->policy); + _err(" policy: %d\n", attr->policy); if (attr->policy == SCHED_FIFO) { - err(" SCHED_FIFO\n"); + _err(" SCHED_FIFO\n"); } else if (attr->policy == SCHED_RR) { - err(" SCHED_RR\n"); + _err(" SCHED_RR\n"); } else { - err(" Unrecognized\n"); + _err(" Unrecognized\n"); } #ifndef CONFIG_DISABLE_SIGNALS - err(" sigmask: %08x\n", attr->sigmask); + _err(" sigmask: %08x\n", attr->sigmask); #endif #endif /* CONFIG_DEBUG_ERROR */ } diff --git a/libc/spawn/lib_psfa_dump.c b/libc/spawn/lib_psfa_dump.c index b56564e2ec..e9371fec31 100644 --- a/libc/spawn/lib_psfa_dump.c +++ b/libc/spawn/lib_psfa_dump.c @@ -80,10 +80,10 @@ void posix_spawn_file_actions_dump(FAR posix_spawn_file_actions_t *file_actions) DEBUGASSERT(file_actions); - err("File Actions[%p->%p]:\n", file_actions, *file_actions); + _err("File Actions[%p->%p]:\n", file_actions, *file_actions); if (!*file_actions) { - err(" NONE\n"); + _err(" NONE\n"); return; } @@ -100,7 +100,7 @@ void posix_spawn_file_actions_dump(FAR posix_spawn_file_actions_t *file_actions) FAR struct spawn_close_file_action_s *action = (FAR struct spawn_close_file_action_s *)entry; - err(" CLOSE: fd=%d\n", action->fd); + _err(" CLOSE: fd=%d\n", action->fd); } break; @@ -109,7 +109,7 @@ void posix_spawn_file_actions_dump(FAR posix_spawn_file_actions_t *file_actions) FAR struct spawn_dup2_file_action_s *action = (FAR struct spawn_dup2_file_action_s *)entry; - err(" DUP2: %d->%d\n", action->fd1, action->fd2); + _err(" DUP2: %d->%d\n", action->fd1, action->fd2); } break; @@ -118,14 +118,14 @@ void posix_spawn_file_actions_dump(FAR posix_spawn_file_actions_t *file_actions) FAR struct spawn_open_file_action_s *action = (FAR struct spawn_open_file_action_s *)entry; - err(" OPEN: path=%s oflags=%04x mode=%04x fd=%d\n", + _err(" OPEN: path=%s oflags=%04x mode=%04x fd=%d\n", action->path, action->oflags, action->mode, action->fd); } break; case SPAWN_FILE_ACTION_NONE: default: - err(" ERROR: Unknown action: %d\n", entry->action); + _err(" ERROR: Unknown action: %d\n", entry->action); break; } } diff --git a/libxx/libxx_new.cxx b/libxx/libxx_new.cxx index 83d2b00009..423ab833b5 100644 --- a/libxx/libxx_new.cxx +++ b/libxx/libxx_new.cxx @@ -93,7 +93,7 @@ void *operator new(unsigned int nbytes) // Oh my.. we are required to return a valid pointer and // we cannot throw an exception! We are bad. - err("ERROR: Failed to allocate\n"); + _err("ERROR: Failed to allocate\n"); } #endif diff --git a/libxx/libxx_newa.cxx b/libxx/libxx_newa.cxx index 3dfb53dbd2..a3b327eb63 100644 --- a/libxx/libxx_newa.cxx +++ b/libxx/libxx_newa.cxx @@ -93,7 +93,7 @@ void *operator new[](unsigned int nbytes) // Oh my.. we are required to return a valid pointer and // we cannot throw an exception! We are bad. - err("ERROR: Failed to allocate\n"); + _err("ERROR: Failed to allocate\n"); } #endif diff --git a/libxx/libxx_stdthrow.cxx b/libxx/libxx_stdthrow.cxx index 18960a266f..20957e236b 100644 --- a/libxx/libxx_stdthrow.cxx +++ b/libxx/libxx_stdthrow.cxx @@ -56,25 +56,25 @@ namespace std { void __throw_out_of_range(const char*) { - err("ERROR: C++: Vector .at() with argument out of range\n"); + _err("ERROR: C++: Vector .at() with argument out of range\n"); abort(); } void __throw_length_error(const char*) { - err("ERROR: C++: Vector resize to excessive length\n"); + _err("ERROR: C++: Vector resize to excessive length\n"); abort(); } void __throw_bad_alloc() { - err("ERROR: C++: Bad allocation\n"); + _err("ERROR: C++: Bad allocation\n"); abort(); } void __throw_bad_function_call() { - err("ERROR: C++: Bad function call\n"); + _err("ERROR: C++: Bad function call\n"); abort(); } } diff --git a/mm/mm_gran/mm_gran.h b/mm/mm_gran/mm_gran.h index fb7378ac58..dcc04c7217 100644 --- a/mm/mm_gran/mm_gran.h +++ b/mm/mm_gran/mm_gran.h @@ -63,9 +63,9 @@ #ifdef CONFIG_CPP_HAVE_VARARGS # ifdef CONFIG_DEBUG_GRAM -# define granerr(format, ...) err(format, ##__VA_ARGS__) -# define granwarn(format, ...) warn(format, ##__VA_ARGS__) -# define graninfo(format, ...) info(format, ##__VA_ARGS__) +# define granerr(format, ...) _err(format, ##__VA_ARGS__) +# define granwarn(format, ...) _warn(format, ##__VA_ARGS__) +# define graninfo(format, ...) _info(format, ##__VA_ARGS__) # else # define granerr(format, ...) merr(format, ##__VA_ARGS__) # define granwarn(format, ...) mwarn(format, ##__VA_ARGS__) @@ -73,9 +73,9 @@ # endif #else # ifdef CONFIG_DEBUG_GRAM -# define granerr err -# define granwarn warn -# define graninfo info +# define granerr _err +# define granwarn _warn +# define graninfo _info # else # define granerr merr # define granwarn mwarn diff --git a/mm/mm_gran/mm_pgalloc.c b/mm/mm_gran/mm_pgalloc.c index f65e0b8982..2574e20912 100644 --- a/mm/mm_gran/mm_pgalloc.c +++ b/mm/mm_gran/mm_pgalloc.c @@ -66,9 +66,9 @@ #ifdef CONFIG_CPP_HAVE_VARARGS # ifdef CONFIG_DEBUG_PGALLOC -# define pgaerr(format, ...) err(format, ##__VA_ARGS__) -# define pgawarn(format, ...) warn(format, ##__VA_ARGS__) -# define pgainfo(format, ...) info(format, ##__VA_ARGS__) +# define pgaerr(format, ...) _err(format, ##__VA_ARGS__) +# define pgawarn(format, ...) _warn(format, ##__VA_ARGS__) +# define pgainfo(format, ...) _info(format, ##__VA_ARGS__) # else # define pgaerr(format, ...) merr(format, ##__VA_ARGS__) # define pgawarn(format, ...) mwarn(format, ##__VA_ARGS__) @@ -76,9 +76,9 @@ # endif #else # ifdef CONFIG_DEBUG_PGALLOC -# define pgaerr err -# define pgawarn warn -# define pgainfo info +# define pgaerr _err +# define pgawarn _warn +# define pgainfo _info # else # define pgaerr merr # define pgawarn mwarn diff --git a/mm/mm_heap/mm_sem.c b/mm/mm_heap/mm_sem.c index b34d61f8af..49083da213 100644 --- a/mm/mm_heap/mm_sem.c +++ b/mm/mm_heap/mm_sem.c @@ -54,16 +54,16 @@ #ifdef MONITOR_MM_SEMAPHORE # include -# define msemerr err -# define msemwarn warn -# define mseminfo info +# define msemerr _err +# define msemwarn _warn +# define mseminfo _info #else # ifdef CONFIG_CPP_HAVE_VARARGS # define msemerr(x...) # define msemwarn(x...) # define mseminfo(x...) # else -# define msemerr (void) +# define msemerr (void) # define msemwarn (void) # define mseminfo (void) # endif diff --git a/sched/group/group_childstatus.c b/sched/group/group_childstatus.c index 54d74bfee0..729fb23ef7 100644 --- a/sched/group/group_childstatus.c +++ b/sched/group/group_childstatus.c @@ -115,10 +115,10 @@ static void group_dumpchildren(FAR struct task_group_s *group, FAR struct child_status_s *child; int i; - info("Task group=%p: %s\n", group, msg); + _info("Task group=%p: %s\n", group, msg); for (i = 0, child = group->tg_children; child; i++, child = child->flink) { - info(" %d. ch_flags=%02x ch_pid=%d ch_status=%d\n", + _info(" %d. ch_flags=%02x ch_pid=%d ch_status=%d\n", i, child->ch_flags, child->ch_pid, child->ch_status); } } diff --git a/sched/irq/irq_unexpectedisr.c b/sched/irq/irq_unexpectedisr.c index c320b18563..136abf5791 100644 --- a/sched/irq/irq_unexpectedisr.c +++ b/sched/irq/irq_unexpectedisr.c @@ -61,7 +61,7 @@ int irq_unexpected_isr(int irq, FAR void *context) { (void)up_irq_save(); - llerr("ERROR irq: %d\n", irq); + _llerr("ERROR irq: %d\n", irq); PANIC(); return OK; /* Won't get here */ } diff --git a/sched/semaphore/sem_holder.c b/sched/semaphore/sem_holder.c index bb7a850511..f56eb1bc8d 100644 --- a/sched/semaphore/sem_holder.c +++ b/sched/semaphore/sem_holder.c @@ -402,10 +402,10 @@ static int sem_dumpholder(FAR struct semholder_s *pholder, FAR sem_t *sem, FAR void *arg) { #if CONFIG_SEM_PREALLOCHOLDERS > 0 - info(" %08x: %08x %08x %04x\n", + _info(" %08x: %08x %08x %04x\n", pholder, pholder->flink, pholder->htcb, pholder->counts); #else - info(" %08x: %08x %04x\n", pholder, pholder->htcb, pholder->counts); + _info(" %08x: %08x %04x\n", pholder, pholder->htcb, pholder->counts); #endif return 0; } From b39e53391d9e5499968150daf41e8fe72bf67f27 Mon Sep 17 00:00:00 2001 From: Gregory Nutt Date: Thu, 16 Jun 2016 12:38:05 -0600 Subject: [PATCH 10/75] Add underscore at beginning of alert() as well --- arch/arm/src/arm/up_assert.c | 40 +++++++++--------- arch/arm/src/arm/up_dataabort.c | 4 +- arch/arm/src/arm/up_prefetchabort.c | 2 +- arch/arm/src/arm/up_syscall.c | 2 +- arch/arm/src/arm/up_undefinedinsn.c | 2 +- arch/arm/src/armv6-m/up_assert.c | 48 +++++++++++----------- arch/arm/src/armv7-a/arm_assert.c | 48 +++++++++++----------- arch/arm/src/armv7-a/arm_dataabort.c | 4 +- arch/arm/src/armv7-a/arm_prefetchabort.c | 4 +- arch/arm/src/armv7-a/arm_syscall.c | 2 +- arch/arm/src/armv7-a/arm_undefinedinsn.c | 2 +- arch/arm/src/armv7-m/up_assert.c | 50 +++++++++++------------ arch/arm/src/armv7-r/arm_dataabort.c | 2 +- arch/arm/src/armv7-r/arm_prefetchabort.c | 2 +- arch/arm/src/armv7-r/arm_syscall.c | 2 +- arch/arm/src/armv7-r/arm_undefinedinsn.c | 2 +- arch/avr/src/at32uc3/at32uc3_irq.c | 2 +- arch/avr/src/avr/up_dumpstate.c | 44 ++++++++++---------- arch/avr/src/avr32/up_dumpstate.c | 38 ++++++++--------- arch/avr/src/common/up_assert.c | 4 +- arch/hc/src/m9s12/m9s12_assert.c | 40 +++++++++--------- arch/mips/src/mips32/up_assert.c | 4 +- arch/mips/src/mips32/up_dumpstate.c | 38 ++++++++--------- arch/mips/src/pic32mx/pic32mx-exception.c | 42 +++++++++---------- arch/mips/src/pic32mz/pic32mz-exception.c | 42 +++++++++---------- arch/sh/src/common/up_assert.c | 4 +- arch/sh/src/m16c/m16c_dumpstate.c | 30 +++++++------- arch/sh/src/sh1/sh1_dumpstate.c | 34 +++++++-------- arch/x86/src/common/up_assert.c | 30 +++++++------- arch/x86/src/i486/up_regdump.c | 8 ++-- arch/z16/src/common/up_assert.c | 8 ++-- arch/z16/src/common/up_registerdump.c | 6 +-- arch/z16/src/common/up_stackdump.c | 8 ++-- arch/z80/src/common/up_assert.c | 8 ++-- arch/z80/src/common/up_stackdump.c | 10 ++--- arch/z80/src/ez80/ez80_registerdump.c | 16 ++++---- arch/z80/src/z180/z180_registerdump.c | 10 ++--- arch/z80/src/z8/z8_registerdump.c | 4 +- arch/z80/src/z80/z80_registerdump.c | 8 ++-- include/debug.h | 10 ++--- 40 files changed, 332 insertions(+), 332 deletions(-) diff --git a/arch/arm/src/arm/up_assert.c b/arch/arm/src/arm/up_assert.c index 05fbbbb031..27788451da 100644 --- a/arch/arm/src/arm/up_assert.c +++ b/arch/arm/src/arm/up_assert.c @@ -99,7 +99,7 @@ static void up_stackdump(uint32_t sp, uint32_t stack_base) for (stack = sp & ~0x1f; stack < stack_base; stack += 32) { uint32_t *ptr = (uint32_t *)stack; - alert("%08x: %08x %08x %08x %08x %08x %08x %08x %08x\n", + _alert("%08x: %08x %08x %08x %08x %08x %08x %08x %08x\n", stack, ptr[0], ptr[1], ptr[2], ptr[3], ptr[4], ptr[5], ptr[6], ptr[7]); } @@ -126,12 +126,12 @@ static inline void up_registerdump(void) for (regs = REG_R0; regs <= REG_R15; regs += 8) { uint32_t *ptr = (uint32_t *)&CURRENT_REGS[regs]; - alert("R%d: %08x %08x %08x %08x %08x %08x %08x %08x\n", + _alert("R%d: %08x %08x %08x %08x %08x %08x %08x %08x\n", regs, ptr[0], ptr[1], ptr[2], ptr[3], ptr[4], ptr[5], ptr[6], ptr[7]); } - alert("CPSR: %08x\n", CURRENT_REGS[REG_CPSR]); + _alert("CPSR: %08x\n", CURRENT_REGS[REG_CPSR]); } } #else @@ -200,12 +200,12 @@ static void up_dumpstate(void) /* Show interrupt stack info */ - alert("sp: %08x\n", sp); - alert("IRQ stack:\n"); - alert(" base: %08x\n", istackbase); - alert(" size: %08x\n", istacksize); + _alert("sp: %08x\n", sp); + _alert("IRQ stack:\n"); + _alert(" base: %08x\n", istackbase); + _alert(" size: %08x\n", istacksize); #ifdef CONFIG_STACK_COLORATION - alert(" used: %08x\n", up_check_intstack()); + _alert(" used: %08x\n", up_check_intstack()); #endif /* Does the current stack pointer lie within the interrupt @@ -223,24 +223,24 @@ static void up_dumpstate(void) */ sp = g_intstackbase; - alert("sp: %08x\n", sp); + _alert("sp: %08x\n", sp); } /* Show user stack info */ - alert("User stack:\n"); - alert(" base: %08x\n", ustackbase); - alert(" size: %08x\n", ustacksize); + _alert("User stack:\n"); + _alert(" base: %08x\n", ustackbase); + _alert(" size: %08x\n", ustacksize); #ifdef CONFIG_STACK_COLORATION - alert(" used: %08x\n", up_check_tcbstack(rtcb)); + _alert(" used: %08x\n", up_check_tcbstack(rtcb)); #endif #else - alert("sp: %08x\n", sp); - alert("stack base: %08x\n", ustackbase); - alert("stack size: %08x\n", ustacksize); + _alert("sp: %08x\n", sp); + _alert("stack base: %08x\n", ustackbase); + _alert("stack size: %08x\n", ustacksize); #ifdef CONFIG_STACK_COLORATION - alert("stack used: %08x\n", up_check_tcbstack(rtcb)); + _alert("stack used: %08x\n", up_check_tcbstack(rtcb)); #endif #endif @@ -251,7 +251,7 @@ static void up_dumpstate(void) if (sp > ustackbase || sp <= ustackbase - ustacksize) { #if !defined(CONFIG_ARCH_INTERRUPTSTACK) || CONFIG_ARCH_INTERRUPTSTACK < 4 - alert("ERROR: Stack pointer is not within allocated stack\n"); + _alert("ERROR: Stack pointer is not within allocated stack\n"); #endif } else @@ -318,10 +318,10 @@ void up_assert(const uint8_t *filename, int lineno) board_autoled_on(LED_ASSERTION); #if CONFIG_TASK_NAME_SIZE > 0 - alert("Assertion failed at file:%s line: %d task: %s\n", + _alert("Assertion failed at file:%s line: %d task: %s\n", filename, lineno, rtcb->name); #else - alert("Assertion failed at file:%s line: %d\n", + _alert("Assertion failed at file:%s line: %d\n", filename, lineno); #endif diff --git a/arch/arm/src/arm/up_dataabort.c b/arch/arm/src/arm/up_dataabort.c index 621a42d328..926352fac4 100644 --- a/arch/arm/src/arm/up_dataabort.c +++ b/arch/arm/src/arm/up_dataabort.c @@ -156,7 +156,7 @@ void up_dataabort(uint32_t *regs, uint32_t far, uint32_t fsr) segfault: #endif - alert("Data abort. PC: %08x FAR: %08x FSR: %08x\n", regs[REG_PC], far, fsr); + _alert("Data abort. PC: %08x FAR: %08x FSR: %08x\n", regs[REG_PC], far, fsr); PANIC(); } @@ -172,7 +172,7 @@ void up_dataabort(uint32_t *regs) /* Crash -- possibly showing diagnost debug information. */ - alert("Data abort. PC: %08x\n", regs[REG_PC]); + _alert("Data abort. PC: %08x\n", regs[REG_PC]); PANIC(); } diff --git a/arch/arm/src/arm/up_prefetchabort.c b/arch/arm/src/arm/up_prefetchabort.c index 5d9d9561dc..070c1ce5d2 100644 --- a/arch/arm/src/arm/up_prefetchabort.c +++ b/arch/arm/src/arm/up_prefetchabort.c @@ -137,7 +137,7 @@ void up_prefetchabort(uint32_t *regs) else #endif { - alert("Prefetch abort. PC: %08x\n", regs[REG_PC]); + _alert("Prefetch abort. PC: %08x\n", regs[REG_PC]); PANIC(); } } diff --git a/arch/arm/src/arm/up_syscall.c b/arch/arm/src/arm/up_syscall.c index f7ee6f1312..c52b036951 100644 --- a/arch/arm/src/arm/up_syscall.c +++ b/arch/arm/src/arm/up_syscall.c @@ -66,7 +66,7 @@ void up_syscall(uint32_t *regs) { - alert("Syscall from 0x%x\n", regs[REG_PC]); + _alert("Syscall from 0x%x\n", regs[REG_PC]); CURRENT_REGS = regs; PANIC(); } diff --git a/arch/arm/src/arm/up_undefinedinsn.c b/arch/arm/src/arm/up_undefinedinsn.c index 22a895b816..364b072acd 100644 --- a/arch/arm/src/arm/up_undefinedinsn.c +++ b/arch/arm/src/arm/up_undefinedinsn.c @@ -57,7 +57,7 @@ void up_undefinedinsn(uint32_t *regs) { - alert("Undefined instruction at 0x%x\n", regs[REG_PC]); + _alert("Undefined instruction at 0x%x\n", regs[REG_PC]); CURRENT_REGS = regs; PANIC(); } diff --git a/arch/arm/src/armv6-m/up_assert.c b/arch/arm/src/armv6-m/up_assert.c index ef1757126a..93ff4a9f6f 100644 --- a/arch/arm/src/armv6-m/up_assert.c +++ b/arch/arm/src/armv6-m/up_assert.c @@ -98,7 +98,7 @@ static void up_stackdump(uint32_t sp, uint32_t stack_base) for (stack = sp & ~0x1f; stack < stack_base; stack += 32) { uint32_t *ptr = (uint32_t *)stack; - alert("%08x: %08x %08x %08x %08x %08x %08x %08x %08x\n", + _alert("%08x: %08x %08x %08x %08x %08x %08x %08x %08x\n", stack, ptr[0], ptr[1], ptr[2], ptr[3], ptr[4], ptr[5], ptr[6], ptr[7]); } @@ -117,11 +117,11 @@ static void up_taskdump(FAR struct tcb_s *tcb, FAR void *arg) /* Dump interesting properties of this task */ #if CONFIG_TASK_NAME_SIZE > 0 - alert("%s: PID=%d Stack Used=%lu of %lu\n", + _alert("%s: PID=%d Stack Used=%lu of %lu\n", tcb->name, tcb->pid, (unsigned long)up_check_tcbstack(tcb), (unsigned long)tcb->adj_stack_size); #else - alert("PID: %d Stack Used=%lu of %lu\n", + _alert("PID: %d Stack Used=%lu of %lu\n", tcb->pid, (unsigned long)up_check_tcbstack(tcb), (unsigned long)tcb->adj_stack_size); #endif @@ -156,22 +156,22 @@ static inline void up_registerdump(void) { /* Yes.. dump the interrupt registers */ - alert("R0: %08x %08x %08x %08x %08x %08x %08x %08x\n", + _alert("R0: %08x %08x %08x %08x %08x %08x %08x %08x\n", CURRENT_REGS[REG_R0], CURRENT_REGS[REG_R1], CURRENT_REGS[REG_R2], CURRENT_REGS[REG_R3], CURRENT_REGS[REG_R4], CURRENT_REGS[REG_R5], CURRENT_REGS[REG_R6], CURRENT_REGS[REG_R7]); - alert("R8: %08x %08x %08x %08x %08x %08x %08x %08x\n", + _alert("R8: %08x %08x %08x %08x %08x %08x %08x %08x\n", CURRENT_REGS[REG_R8], CURRENT_REGS[REG_R9], CURRENT_REGS[REG_R10], CURRENT_REGS[REG_R11], CURRENT_REGS[REG_R12], CURRENT_REGS[REG_R13], CURRENT_REGS[REG_R14], CURRENT_REGS[REG_R15]); #ifdef CONFIG_BUILD_PROTECTED - alert("xPSR: %08x PRIMASK: %08x EXEC_RETURN: %08x\n", + _alert("xPSR: %08x PRIMASK: %08x EXEC_RETURN: %08x\n", CURRENT_REGS[REG_XPSR], CURRENT_REGS[REG_PRIMASK], CURRENT_REGS[REG_EXC_RETURN]); #else - alert("xPSR: %08x PRIMASK: %08x\n", + _alert("xPSR: %08x PRIMASK: %08x\n", CURRENT_REGS[REG_XPSR], CURRENT_REGS[REG_PRIMASK]); #endif } @@ -242,12 +242,12 @@ static void up_dumpstate(void) /* Show interrupt stack info */ - alert("sp: %08x\n", sp); - alert("IRQ stack:\n"); - alert(" base: %08x\n", istackbase); - alert(" size: %08x\n", istacksize); + _alert("sp: %08x\n", sp); + _alert("IRQ stack:\n"); + _alert(" base: %08x\n", istackbase); + _alert(" size: %08x\n", istacksize); #ifdef CONFIG_STACK_COLORATION - alert(" used: %08x\n", up_check_intstack()); + _alert(" used: %08x\n", up_check_intstack()); #endif /* Does the current stack pointer lie within the interrupt @@ -269,14 +269,14 @@ static void up_dumpstate(void) if (CURRENT_REGS) { sp = CURRENT_REGS[REG_R13]; - alert("sp: %08x\n", sp); + _alert("sp: %08x\n", sp); } - alert("User stack:\n"); - alert(" base: %08x\n", ustackbase); - alert(" size: %08x\n", ustacksize); + _alert("User stack:\n"); + _alert(" base: %08x\n", ustackbase); + _alert(" size: %08x\n", ustacksize); #ifdef CONFIG_STACK_COLORATION - alert(" used: %08x\n", up_check_tcbstack(rtcb)); + _alert(" used: %08x\n", up_check_tcbstack(rtcb)); #endif /* Dump the user stack if the stack pointer lies within the allocated user @@ -289,11 +289,11 @@ static void up_dumpstate(void) } #else - alert("sp: %08x\n", sp); - alert("stack base: %08x\n", ustackbase); - alert("stack size: %08x\n", ustacksize); + _alert("sp: %08x\n", sp); + _alert("stack base: %08x\n", ustackbase); + _alert("stack size: %08x\n", ustacksize); #ifdef CONFIG_STACK_COLORATION - alert("stack used: %08x\n", up_check_tcbstack(rtcb)); + _alert("stack used: %08x\n", up_check_tcbstack(rtcb)); #endif /* Dump the user stack if the stack pointer lies within the allocated user @@ -302,7 +302,7 @@ static void up_dumpstate(void) if (sp > ustackbase || sp <= ustackbase - ustacksize) { - alert("ERROR: Stack pointer is not within allocated stack\n"); + _alert("ERROR: Stack pointer is not within allocated stack\n"); } else { @@ -373,10 +373,10 @@ void up_assert(const uint8_t *filename, int lineno) board_autoled_on(LED_ASSERTION); #if CONFIG_TASK_NAME_SIZE > 0 - alert("Assertion failed at file:%s line: %d task: %s\n", + _alert("Assertion failed at file:%s line: %d task: %s\n", filename, lineno, rtcb->name); #else - alert("Assertion failed at file:%s line: %d\n", + _alert("Assertion failed at file:%s line: %d\n", filename, lineno); #endif diff --git a/arch/arm/src/armv7-a/arm_assert.c b/arch/arm/src/armv7-a/arm_assert.c index d79200e0f5..bdeffa763c 100644 --- a/arch/arm/src/armv7-a/arm_assert.c +++ b/arch/arm/src/armv7-a/arm_assert.c @@ -97,7 +97,7 @@ static void up_stackdump(uint32_t sp, uint32_t stack_base) for (stack = sp & ~0x1f; stack < stack_base; stack += 32) { uint32_t *ptr = (uint32_t *)stack; - alert("%08x: %08x %08x %08x %08x %08x %08x %08x %08x\n", + _alert("%08x: %08x %08x %08x %08x %08x %08x %08x %08x\n", stack, ptr[0], ptr[1], ptr[2], ptr[3], ptr[4], ptr[5], ptr[6], ptr[7]); } @@ -116,11 +116,11 @@ static void up_taskdump(FAR struct tcb_s *tcb, FAR void *arg) /* Dump interesting properties of this task */ #if CONFIG_TASK_NAME_SIZE > 0 - alert("%s: PID=%d Stack Used=%lu of %lu\n", + _alert("%s: PID=%d Stack Used=%lu of %lu\n", tcb->name, tcb->pid, (unsigned long)up_check_tcbstack(tcb), (unsigned long)tcb->adj_stack_size); #else - alert("PID: %d Stack Used=%lu of %lu\n", + _alert("PID: %d Stack Used=%lu of %lu\n", tcb->pid, (unsigned long)up_check_tcbstack(tcb), (unsigned long)tcb->adj_stack_size); #endif @@ -160,12 +160,12 @@ static inline void up_registerdump(void) for (regs = REG_R0; regs <= REG_R15; regs += 8) { uint32_t *ptr = (uint32_t *)&CURRENT_REGS[regs]; - alert("R%d: %08x %08x %08x %08x %08x %08x %08x %08x\n", + _alert("R%d: %08x %08x %08x %08x %08x %08x %08x %08x\n", regs, ptr[0], ptr[1], ptr[2], ptr[3], ptr[4], ptr[5], ptr[6], ptr[7]); } - alert("CPSR: %08x\n", CURRENT_REGS[REG_CPSR]); + _alert("CPSR: %08x\n", CURRENT_REGS[REG_CPSR]); } } #else @@ -229,7 +229,7 @@ static void up_dumpstate(void) ustacksize = (uint32_t)rtcb->adj_stack_size; } - alert("Current sp: %08x\n", sp); + _alert("Current sp: %08x\n", sp); #if CONFIG_ARCH_INTERRUPTSTACK > 3 /* Get the limits on the interrupt stack memory */ @@ -239,21 +239,21 @@ static void up_dumpstate(void) /* Show interrupt stack info */ - alert("Interrupt stack:\n"); - alert(" base: %08x\n", istackbase); - alert(" size: %08x\n", istacksize); + _alert("Interrupt stack:\n"); + _alert(" base: %08x\n", istackbase); + _alert(" size: %08x\n", istacksize); #ifdef CONFIG_STACK_COLORATION - alert(" used: %08x\n", up_check_intstack()); + _alert(" used: %08x\n", up_check_intstack()); #endif #endif /* Show user stack info */ - alert("User stack:\n"); - alert(" base: %08x\n", ustackbase); - alert(" size: %08x\n", ustacksize); + _alert("User stack:\n"); + _alert(" base: %08x\n", ustackbase); + _alert(" size: %08x\n", ustacksize); #ifdef CONFIG_STACK_COLORATION - alert(" used: %08x\n", up_check_tcbstack(rtcb)); + _alert(" used: %08x\n", up_check_tcbstack(rtcb)); #endif #ifdef CONFIG_ARCH_KERNEL_STACK @@ -263,9 +263,9 @@ static void up_dumpstate(void) { kstackbase = (uint32_t)rtcb->xcp.kstack + CONFIG_ARCH_KERNEL_STACKSIZE - 4; - alert("Kernel stack:\n"); - alert(" base: %08x\n", kstackbase); - alert(" size: %08x\n", CONFIG_ARCH_KERNEL_STACKSIZE); + _alert("Kernel stack:\n"); + _alert(" base: %08x\n", kstackbase); + _alert(" size: %08x\n", CONFIG_ARCH_KERNEL_STACKSIZE); } #endif @@ -276,7 +276,7 @@ static void up_dumpstate(void) { /* Yes.. dump the interrupt stack */ - alert("Interrupt Stack\n", sp); + _alert("Interrupt Stack\n", sp); up_stackdump(sp, istackbase); /* Extract the user stack pointer which should lie @@ -284,7 +284,7 @@ static void up_dumpstate(void) */ sp = g_intstackbase; - alert("User sp: %08x\n", sp); + _alert("User sp: %08x\n", sp); } #endif @@ -294,7 +294,7 @@ static void up_dumpstate(void) if (sp > ustackbase - ustacksize && sp < ustackbase) { - alert("User Stack\n", sp); + _alert("User Stack\n", sp); up_stackdump(sp, ustackbase); } @@ -305,7 +305,7 @@ static void up_dumpstate(void) if (sp >= (uint32_t)rtcb->xcp.kstack && sp < kstackbase) { - alert("Kernel Stack\n", sp); + _alert("Kernel Stack\n", sp); up_stackdump(sp, kstackbase); } #endif @@ -313,7 +313,7 @@ static void up_dumpstate(void) #ifdef CONFIG_SMP /* Show the CPU number */ - alert("CPU%d:\n", up_cpu_index()); + _alert("CPU%d:\n", up_cpu_index()); #endif /* Then dump the CPU registers (if available) */ @@ -378,10 +378,10 @@ void up_assert(const uint8_t *filename, int lineno) board_autoled_on(LED_ASSERTION); #if CONFIG_TASK_NAME_SIZE > 0 - alert("Assertion failed at file:%s line: %d task: %s\n", + _alert("Assertion failed at file:%s line: %d task: %s\n", filename, lineno, rtcb->name); #else - alert("Assertion failed at file:%s line: %d\n", + _alert("Assertion failed at file:%s line: %d\n", filename, lineno); #endif up_dumpstate(); diff --git a/arch/arm/src/armv7-a/arm_dataabort.c b/arch/arm/src/armv7-a/arm_dataabort.c index 00a686f8a7..dae3b926e0 100644 --- a/arch/arm/src/armv7-a/arm_dataabort.c +++ b/arch/arm/src/armv7-a/arm_dataabort.c @@ -152,7 +152,7 @@ uint32_t *arm_dataabort(uint32_t *regs, uint32_t dfar, uint32_t dfsr) return regs; segfault: - alert("Data abort. PC: %08x DFAR: %08x DFSR: %08x\n", + _alert("Data abort. PC: %08x DFAR: %08x DFSR: %08x\n", regs[REG_PC], dfar, dfsr); PANIC(); return regs; /* To keep the compiler happy */ @@ -170,7 +170,7 @@ uint32_t *arm_dataabort(uint32_t *regs, uint32_t dfar, uint32_t dfsr) /* Crash -- possibly showing diagnostic debug information. */ - alert("Data abort. PC: %08x DFAR: %08x DFSR: %08x\n", + _alert("Data abort. PC: %08x DFAR: %08x DFSR: %08x\n", regs[REG_PC], dfar, dfsr); PANIC(); return regs; /* To keep the compiler happy */ diff --git a/arch/arm/src/armv7-a/arm_prefetchabort.c b/arch/arm/src/armv7-a/arm_prefetchabort.c index a6b73e3ad2..4e21143642 100644 --- a/arch/arm/src/armv7-a/arm_prefetchabort.c +++ b/arch/arm/src/armv7-a/arm_prefetchabort.c @@ -123,7 +123,7 @@ uint32_t *arm_prefetchabort(uint32_t *regs, uint32_t ifar, uint32_t ifsr) } else { - alert("Prefetch abort. PC: %08x IFAR: %08x IFSR: %08x\n", + _alert("Prefetch abort. PC: %08x IFAR: %08x IFSR: %08x\n", regs[REG_PC], ifar, ifsr); PANIC(); } @@ -143,7 +143,7 @@ uint32_t *arm_prefetchabort(uint32_t *regs, uint32_t ifar, uint32_t ifsr) /* Crash -- possibly showing diagnostic debug information. */ - alert("Prefetch abort. PC: %08x IFAR: %08x IFSR: %08x\n", + _alert("Prefetch abort. PC: %08x IFAR: %08x IFSR: %08x\n", regs[REG_PC], ifar, ifsr); PANIC(); return regs; /* To keep the compiler happy */ diff --git a/arch/arm/src/armv7-a/arm_syscall.c b/arch/arm/src/armv7-a/arm_syscall.c index 482345c417..0259acb5c6 100644 --- a/arch/arm/src/armv7-a/arm_syscall.c +++ b/arch/arm/src/armv7-a/arm_syscall.c @@ -500,7 +500,7 @@ uint32_t *arm_syscall(uint32_t *regs) uint32_t *arm_syscall(uint32_t *regs) { - alert("SYSCALL from 0x%x\n", regs[REG_PC]); + _alert("SYSCALL from 0x%x\n", regs[REG_PC]); CURRENT_REGS = regs; PANIC(); } diff --git a/arch/arm/src/armv7-a/arm_undefinedinsn.c b/arch/arm/src/armv7-a/arm_undefinedinsn.c index 70442b49ff..54dbcc25b8 100644 --- a/arch/arm/src/armv7-a/arm_undefinedinsn.c +++ b/arch/arm/src/armv7-a/arm_undefinedinsn.c @@ -57,7 +57,7 @@ uint32_t *arm_undefinedinsn(uint32_t *regs) { - alert("Undefined instruction at 0x%x\n", regs[REG_PC]); + _alert("Undefined instruction at 0x%x\n", regs[REG_PC]); CURRENT_REGS = regs; PANIC(); return regs; /* To keep the compiler happy */ diff --git a/arch/arm/src/armv7-m/up_assert.c b/arch/arm/src/armv7-m/up_assert.c index fbf29b29e7..eedfa522d8 100644 --- a/arch/arm/src/armv7-m/up_assert.c +++ b/arch/arm/src/armv7-m/up_assert.c @@ -97,7 +97,7 @@ static void up_stackdump(uint32_t sp, uint32_t stack_base) for (stack = sp & ~0x1f; stack < stack_base; stack += 32) { uint32_t *ptr = (uint32_t *)stack; - alert("%08x: %08x %08x %08x %08x %08x %08x %08x %08x\n", + _alert("%08x: %08x %08x %08x %08x %08x %08x %08x %08x\n", stack, ptr[0], ptr[1], ptr[2], ptr[3], ptr[4], ptr[5], ptr[6], ptr[7]); } @@ -116,11 +116,11 @@ static void up_taskdump(FAR struct tcb_s *tcb, FAR void *arg) /* Dump interesting properties of this task */ #if CONFIG_TASK_NAME_SIZE > 0 - alert("%s: PID=%d Stack Used=%lu of %lu\n", + _alert("%s: PID=%d Stack Used=%lu of %lu\n", tcb->name, tcb->pid, (unsigned long)up_check_tcbstack(tcb), (unsigned long)tcb->adj_stack_size); #else - alert("PID: %d Stack Used=%lu of %lu\n", + _alert("PID: %d Stack Used=%lu of %lu\n", tcb->pid, (unsigned long)up_check_tcbstack(tcb), (unsigned long)tcb->adj_stack_size); #endif @@ -155,29 +155,29 @@ static inline void up_registerdump(void) { /* Yes.. dump the interrupt registers */ - alert("R0: %08x %08x %08x %08x %08x %08x %08x %08x\n", + _alert("R0: %08x %08x %08x %08x %08x %08x %08x %08x\n", CURRENT_REGS[REG_R0], CURRENT_REGS[REG_R1], CURRENT_REGS[REG_R2], CURRENT_REGS[REG_R3], CURRENT_REGS[REG_R4], CURRENT_REGS[REG_R5], CURRENT_REGS[REG_R6], CURRENT_REGS[REG_R7]); - alert("R8: %08x %08x %08x %08x %08x %08x %08x %08x\n", + _alert("R8: %08x %08x %08x %08x %08x %08x %08x %08x\n", CURRENT_REGS[REG_R8], CURRENT_REGS[REG_R9], CURRENT_REGS[REG_R10], CURRENT_REGS[REG_R11], CURRENT_REGS[REG_R12], CURRENT_REGS[REG_R13], CURRENT_REGS[REG_R14], CURRENT_REGS[REG_R15]); #ifdef CONFIG_ARMV7M_USEBASEPRI - alert("xPSR: %08x BASEPRI: %08x CONTROL: %08x\n", + _alert("xPSR: %08x BASEPRI: %08x CONTROL: %08x\n", CURRENT_REGS[REG_XPSR], CURRENT_REGS[REG_BASEPRI], getcontrol()); #else - alert("xPSR: %08x PRIMASK: %08x CONTROL: %08x\n", + _alert("xPSR: %08x PRIMASK: %08x CONTROL: %08x\n", CURRENT_REGS[REG_XPSR], CURRENT_REGS[REG_PRIMASK], getcontrol()); #endif #ifdef REG_EXC_RETURN - alert("EXC_RETURN: %08x\n", CURRENT_REGS[REG_EXC_RETURN]); + _alert("EXC_RETURN: %08x\n", CURRENT_REGS[REG_EXC_RETURN]); #endif } } @@ -247,12 +247,12 @@ static void up_dumpstate(void) /* Show interrupt stack info */ - alert("sp: %08x\n", sp); - alert("IRQ stack:\n"); - alert(" base: %08x\n", istackbase); - alert(" size: %08x\n", istacksize); + _alert("sp: %08x\n", sp); + _alert("IRQ stack:\n"); + _alert(" base: %08x\n", istackbase); + _alert(" size: %08x\n", istacksize); #ifdef CONFIG_STACK_COLORATION - alert(" used: %08x\n", up_check_intstack()); + _alert(" used: %08x\n", up_check_intstack()); #endif /* Does the current stack pointer lie within the interrupt @@ -274,14 +274,14 @@ static void up_dumpstate(void) if (CURRENT_REGS) { sp = CURRENT_REGS[REG_R13]; - alert("sp: %08x\n", sp); + _alert("sp: %08x\n", sp); } - alert("User stack:\n"); - alert(" base: %08x\n", ustackbase); - alert(" size: %08x\n", ustacksize); + _alert("User stack:\n"); + _alert(" base: %08x\n", ustackbase); + _alert(" size: %08x\n", ustacksize); #ifdef CONFIG_STACK_COLORATION - alert(" used: %08x\n", up_check_tcbstack(rtcb)); + _alert(" used: %08x\n", up_check_tcbstack(rtcb)); #endif /* Dump the user stack if the stack pointer lies within the allocated user @@ -297,11 +297,11 @@ static void up_dumpstate(void) /* Show user stack info */ - alert("sp: %08x\n", sp); - alert("stack base: %08x\n", ustackbase); - alert("stack size: %08x\n", ustacksize); + _alert("sp: %08x\n", sp); + _alert("stack base: %08x\n", ustackbase); + _alert("stack size: %08x\n", ustacksize); #ifdef CONFIG_STACK_COLORATION - alert("stack used: %08x\n", up_check_tcbstack(rtcb)); + _alert("stack used: %08x\n", up_check_tcbstack(rtcb)); #endif /* Dump the user stack if the stack pointer lies within the allocated user @@ -310,7 +310,7 @@ static void up_dumpstate(void) if (sp > ustackbase || sp <= ustackbase - ustacksize) { - alert("ERROR: Stack pointer is not within the allocated stack\n"); + _alert("ERROR: Stack pointer is not within the allocated stack\n"); } else { @@ -382,10 +382,10 @@ void up_assert(const uint8_t *filename, int lineno) board_autoled_on(LED_ASSERTION); #if CONFIG_TASK_NAME_SIZE > 0 - alert("Assertion failed at file:%s line: %d task: %s\n", + _alert("Assertion failed at file:%s line: %d task: %s\n", filename, lineno, rtcb->name); #else - alert("Assertion failed at file:%s line: %d\n", + _alert("Assertion failed at file:%s line: %d\n", filename, lineno); #endif diff --git a/arch/arm/src/armv7-r/arm_dataabort.c b/arch/arm/src/armv7-r/arm_dataabort.c index 56cf88d8bc..52f5d12436 100644 --- a/arch/arm/src/armv7-r/arm_dataabort.c +++ b/arch/arm/src/armv7-r/arm_dataabort.c @@ -75,7 +75,7 @@ uint32_t *arm_dataabort(uint32_t *regs, uint32_t dfar, uint32_t dfsr) /* Crash -- possibly showing diagnostic debug information. */ - alert("Data abort. PC: %08x DFAR: %08x DFSR: %08x\n", + _alert("Data abort. PC: %08x DFAR: %08x DFSR: %08x\n", regs[REG_PC], dfar, dfsr); PANIC(); return regs; /* To keep the compiler happy */ diff --git a/arch/arm/src/armv7-r/arm_prefetchabort.c b/arch/arm/src/armv7-r/arm_prefetchabort.c index ee9c38be0a..74713f5ad3 100644 --- a/arch/arm/src/armv7-r/arm_prefetchabort.c +++ b/arch/arm/src/armv7-r/arm_prefetchabort.c @@ -71,7 +71,7 @@ uint32_t *arm_prefetchabort(uint32_t *regs, uint32_t ifar, uint32_t ifsr) /* Crash -- possibly showing diagnostic debug information. */ - alert("Prefetch abort. PC: %08x IFAR: %08x IFSR: %08x\n", + _alert("Prefetch abort. PC: %08x IFAR: %08x IFSR: %08x\n", regs[REG_PC], ifar, ifsr); PANIC(); return regs; /* To keep the compiler happy */ diff --git a/arch/arm/src/armv7-r/arm_syscall.c b/arch/arm/src/armv7-r/arm_syscall.c index c8a33f36c3..7d36ccb0d9 100644 --- a/arch/arm/src/armv7-r/arm_syscall.c +++ b/arch/arm/src/armv7-r/arm_syscall.c @@ -498,7 +498,7 @@ uint32_t *arm_syscall(uint32_t *regs) uint32_t *arm_syscall(uint32_t *regs) { - alert("SYSCALL from 0x%x\n", regs[REG_PC]); + _alert("SYSCALL from 0x%x\n", regs[REG_PC]); CURRENT_REGS = regs; PANIC(); } diff --git a/arch/arm/src/armv7-r/arm_undefinedinsn.c b/arch/arm/src/armv7-r/arm_undefinedinsn.c index d23af75301..733fb06cb2 100644 --- a/arch/arm/src/armv7-r/arm_undefinedinsn.c +++ b/arch/arm/src/armv7-r/arm_undefinedinsn.c @@ -57,7 +57,7 @@ uint32_t *arm_undefinedinsn(uint32_t *regs) { - alert("Undefined instruction at 0x%x\n", regs[REG_PC]); + _alert("Undefined instruction at 0x%x\n", regs[REG_PC]); CURRENT_REGS = regs; PANIC(); return regs; /* To keep the compiler happy */ diff --git a/arch/avr/src/at32uc3/at32uc3_irq.c b/arch/avr/src/at32uc3/at32uc3_irq.c index c552f462a9..1983e1f34f 100644 --- a/arch/avr/src/at32uc3/at32uc3_irq.c +++ b/arch/avr/src/at32uc3/at32uc3_irq.c @@ -177,7 +177,7 @@ static int up_getgrp(unsigned int irq) static int avr32_xcptn(int irq, FAR void *context) { (void)up_irq_save(); - alert("PANIC!!! Exception IRQ: %d\n", irq); + _alert("PANIC!!! Exception IRQ: %d\n", irq); PANIC(); return 0; } diff --git a/arch/avr/src/avr/up_dumpstate.c b/arch/avr/src/avr/up_dumpstate.c index 9e406b6cab..5a1660b81b 100644 --- a/arch/avr/src/avr/up_dumpstate.c +++ b/arch/avr/src/avr/up_dumpstate.c @@ -90,7 +90,7 @@ static void up_stackdump(uint16_t sp, uint16_t stack_base) for (stack = sp & ~3; stack < stack_base; stack += 12) { uint8_t *ptr = (uint8_t *)stack; - alert("%04x: %02x %02x %02x %02x %02x %02x %02x %02x" + _alert("%04x: %02x %02x %02x %02x %02x %02x %02x %02x" " %02x %02x %02x %02x\n", stack, ptr[0], ptr[1], ptr[2], ptr[3], ptr[4], ptr[5], ptr[6], ptr[7], @@ -108,28 +108,28 @@ static inline void up_registerdump(void) if (g_current_regs) { - alert("R%02d: %02x %02x %02x %02x %02x %02x %02x %02x\n", + _alert("R%02d: %02x %02x %02x %02x %02x %02x %02x %02x\n", 0, g_current_regs[REG_R0], g_current_regs[REG_R1], g_current_regs[REG_R2], g_current_regs[REG_R3], g_current_regs[REG_R4], g_current_regs[REG_R5], g_current_regs[REG_R6], g_current_regs[REG_R7]); - alert("R%02d: %02x %02x %02x %02x %02x %02x %02x %02x\n", + _alert("R%02d: %02x %02x %02x %02x %02x %02x %02x %02x\n", 8, g_current_regs[REG_R8], g_current_regs[REG_R9], g_current_regs[REG_R10], g_current_regs[REG_R11], g_current_regs[REG_R12], g_current_regs[REG_R13], g_current_regs[REG_R14], g_current_regs[REG_R15]); - alert("R%02d: %02x %02x %02x %02x %02x %02x %02x %02x\n", + _alert("R%02d: %02x %02x %02x %02x %02x %02x %02x %02x\n", 16, g_current_regs[REG_R16], g_current_regs[REG_R17], g_current_regs[REG_R18], g_current_regs[REG_R19], g_current_regs[REG_R20], g_current_regs[REG_R21], g_current_regs[REG_R22], g_current_regs[REG_R23]); - alert("R%02d: %02x %02x %02x %02x %02x %02x %02x %02x\n", + _alert("R%02d: %02x %02x %02x %02x %02x %02x %02x %02x\n", 24, g_current_regs[REG_R24], g_current_regs[REG_R25], g_current_regs[REG_R26], g_current_regs[REG_R27], @@ -137,12 +137,12 @@ static inline void up_registerdump(void) g_current_regs[REG_R30], g_current_regs[REG_R31]); #if !defined(REG_PC2) - alert("PC: %02x%02x SP: %02x%02x SREG: %02x\n", + _alert("PC: %02x%02x SP: %02x%02x SREG: %02x\n", g_current_regs[REG_PC0], g_current_regs[REG_PC1], g_current_regs[REG_SPH], g_current_regs[REG_SPL], g_current_regs[REG_SREG]); #else - alert("PC: %02x%02x%02x SP: %02x%02x SREG: %02x\n", + _alert("PC: %02x%02x%02x SP: %02x%02x SREG: %02x\n", g_current_regs[REG_PC0], g_current_regs[REG_PC1], g_current_regs[REG_PC2], g_current_regs[REG_SPH], g_current_regs[REG_SPL], g_current_regs[REG_SREG]); @@ -190,12 +190,12 @@ void up_dumpstate(void) /* Show interrupt stack info */ - alert("sp: %04x\n", sp); - alert("IRQ stack:\n"); - alert(" base: %04x\n", istackbase); - alert(" size: %04x\n", istacksize); + _alert("sp: %04x\n", sp); + _alert("IRQ stack:\n"); + _alert(" base: %04x\n", istackbase); + _alert(" size: %04x\n", istacksize); #ifdef CONFIG_STACK_COLORATION - alert(" used: %08x\n", up_check_intstack()); + _alert(" used: %08x\n", up_check_intstack()); #endif /* Does the current stack pointer lie within the interrupt @@ -217,14 +217,14 @@ void up_dumpstate(void) if (g_current_regs) { sp = g_current_regs[REG_R13]; - alert("sp: %04x\n", sp); + _alert("sp: %04x\n", sp); } - alert("User stack:\n"); - alert(" base: %04x\n", ustackbase); - alert(" size: %04x\n", ustacksize); + _alert("User stack:\n"); + _alert(" base: %04x\n", ustackbase); + _alert(" size: %04x\n", ustacksize); #ifdef CONFIG_STACK_COLORATION - alert(" used: %08x\n", up_check_tcbstack(rtcb)); + _alert(" used: %08x\n", up_check_tcbstack(rtcb)); #endif /* Dump the user stack if the stack pointer lies within the allocated user @@ -236,11 +236,11 @@ void up_dumpstate(void) up_stackdump(sp, ustackbase); } #else - alert("sp: %04x\n", sp); - alert("stack base: %04x\n", ustackbase); - alert("stack size: %04x\n", ustacksize); + _alert("sp: %04x\n", sp); + _alert("stack base: %04x\n", ustackbase); + _alert("stack size: %04x\n", ustacksize); #ifdef CONFIG_STACK_COLORATION - alert("stack used: %08x\n", up_check_tcbstack(rtcb)); + _alert("stack used: %08x\n", up_check_tcbstack(rtcb)); #endif /* Dump the user stack if the stack pointer lies within the allocated user @@ -249,7 +249,7 @@ void up_dumpstate(void) if (sp > ustackbase || sp <= ustackbase - ustacksize) { - alert("ERROR: Stack pointer is not within allocated stack\n"); + _alert("ERROR: Stack pointer is not within allocated stack\n"); } else { diff --git a/arch/avr/src/avr32/up_dumpstate.c b/arch/avr/src/avr32/up_dumpstate.c index 16a5406aa4..c15b331440 100644 --- a/arch/avr/src/avr32/up_dumpstate.c +++ b/arch/avr/src/avr32/up_dumpstate.c @@ -86,7 +86,7 @@ static void up_stackdump(uint32_t sp, uint32_t stack_base) for (stack = sp & ~0x1f; stack < stack_base; stack += 32) { uint32_t *ptr = (uint32_t *)stack; - alert("%08x: %08x %08x %08x %08x %08x %08x %08x %08x\n", + _alert("%08x: %08x %08x %08x %08x %08x %08x %08x %08x\n", stack, ptr[0], ptr[1], ptr[2], ptr[3], ptr[4], ptr[5], ptr[6], ptr[7]); } @@ -102,21 +102,21 @@ static inline void up_registerdump(void) if (g_current_regs) { - alert("R%d: %08x %08x %08x %08x %08x %08x %08x %08x\n", + _alert("R%d: %08x %08x %08x %08x %08x %08x %08x %08x\n", 0, g_current_regs[REG_R0], g_current_regs[REG_R1], g_current_regs[REG_R2], g_current_regs[REG_R3], g_current_regs[REG_R4], g_current_regs[REG_R5], g_current_regs[REG_R6], g_current_regs[REG_R7]); - alert("R%d: %08x %08x %08x %08x %08x %08x %08x %08x\n", + _alert("R%d: %08x %08x %08x %08x %08x %08x %08x %08x\n", 8, g_current_regs[REG_R8], g_current_regs[REG_R9], g_current_regs[REG_R10], g_current_regs[REG_R11], g_current_regs[REG_R12], g_current_regs[REG_R13], g_current_regs[REG_R14], g_current_regs[REG_R15]); - alert("SR: %08x\n", g_current_regs[REG_SR]); + _alert("SR: %08x\n", g_current_regs[REG_SR]); } } @@ -156,12 +156,12 @@ void up_dumpstate(void) /* Show interrupt stack info */ - alert("sp: %08x\n", sp); - alert("IRQ stack:\n"); - alert(" base: %08x\n", istackbase); - alert(" size: %08x\n", istacksize); + _alert("sp: %08x\n", sp); + _alert("IRQ stack:\n"); + _alert(" base: %08x\n", istackbase); + _alert(" size: %08x\n", istacksize); #ifdef CONFIG_STACK_COLORATION - alert(" used: %08x\n", up_check_intstack()); + _alert(" used: %08x\n", up_check_intstack()); #endif /* Does the current stack pointer lie within the interrupt @@ -183,14 +183,14 @@ void up_dumpstate(void) if (g_current_regs) { sp = g_current_regs[REG_R13]; - alert("sp: %08x\n", sp); + _alert("sp: %08x\n", sp); } - alert("User stack:\n"); - alert(" base: %08x\n", ustackbase); - alert(" size: %08x\n", ustacksize); + _alert("User stack:\n"); + _alert(" base: %08x\n", ustackbase); + _alert(" size: %08x\n", ustacksize); #ifdef CONFIG_STACK_COLORATION - alert(" used: %08x\n", up_check_tcbstack(rtcb)); + _alert(" used: %08x\n", up_check_tcbstack(rtcb)); #endif /* Dump the user stack if the stack pointer lies within the allocated user @@ -202,11 +202,11 @@ void up_dumpstate(void) up_stackdump(sp, ustackbase); } #else - alert("sp: %08x\n", sp); - alert("stack base: %08x\n", ustackbase); - alert("stack size: %08x\n", ustacksize); + _alert("sp: %08x\n", sp); + _alert("stack base: %08x\n", ustackbase); + _alert("stack size: %08x\n", ustacksize); #ifdef CONFIG_STACK_COLORATION - alert("stack used: %08x\n", up_check_tcbstack(rtcb)); + _alert("stack used: %08x\n", up_check_tcbstack(rtcb)); #endif /* Dump the user stack if the stack pointer lies within the allocated user @@ -215,7 +215,7 @@ void up_dumpstate(void) if (sp > ustackbase || sp <= ustackbase - ustacksize) { - alert("ERROR: Stack pointer is not within allocated stack\n"); + _alert("ERROR: Stack pointer is not within allocated stack\n"); } else { diff --git a/arch/avr/src/common/up_assert.c b/arch/avr/src/common/up_assert.c index dc6411081e..a93187c523 100644 --- a/arch/avr/src/common/up_assert.c +++ b/arch/avr/src/common/up_assert.c @@ -138,10 +138,10 @@ void up_assert(const uint8_t *filename, int lineno) board_autoled_on(LED_ASSERTION); #if CONFIG_TASK_NAME_SIZE > 0 - alert("Assertion failed at file:%s line: %d task: %s\n", + _alert("Assertion failed at file:%s line: %d task: %s\n", filename, lineno, rtcb->name); #else - alert("Assertion failed at file:%s line: %d\n", + _alert("Assertion failed at file:%s line: %d\n", filename, lineno); #endif diff --git a/arch/hc/src/m9s12/m9s12_assert.c b/arch/hc/src/m9s12/m9s12_assert.c index 1074adfb80..2f859314f1 100644 --- a/arch/hc/src/m9s12/m9s12_assert.c +++ b/arch/hc/src/m9s12/m9s12_assert.c @@ -80,7 +80,7 @@ static void up_stackdump(uint16_t sp, uint16_t stack_base) for (stack = sp; stack < stack_base; stack += 16) { uint8_t *ptr = (uint8_t*)stack; - alert("%04x: %02x %02x %02x %02x %02x %02x %02x %02x" + _alert("%04x: %02x %02x %02x %02x %02x %02x %02x %02x" " %02x %02x %02x %02x %02x %02x %02x %02x\n", stack, ptr[0], ptr[1], ptr[2], ptr[3], ptr[4], ptr[5], ptr[6], ptr[7], ptr[8], ptr[9], ptr[10], ptr[11], ptr[12], ptr[13], ptr[14], ptr[15]); @@ -101,11 +101,11 @@ static inline void up_registerdump(void) if (g_current_regs) { - alert("A:%02x B:%02x X:%02x%02x Y:%02x%02x PC:%02x%02x CCR:%02x\n", + _alert("A:%02x B:%02x X:%02x%02x Y:%02x%02x PC:%02x%02x CCR:%02x\n", g_current_regs[REG_A], g_current_regs[REG_B], g_current_regs[REG_XH], g_current_regs[REG_XL], g_current_regs[REG_YH], g_current_regs[REG_YL], g_current_regs[REG_PCH], g_current_regs[REG_PCL], g_current_regs[REG_CCR]); - alert("SP:%02x%02x FRAME:%02x%02x TMP:%02x%02x Z:%02x%02x XY:%02x\n", + _alert("SP:%02x%02x FRAME:%02x%02x TMP:%02x%02x Z:%02x%02x XY:%02x\n", g_current_regs[REG_SPH], g_current_regs[REG_SPL], g_current_regs[REG_FRAMEH], g_current_regs[REG_FRAMEL], g_current_regs[REG_TMPL], g_current_regs[REG_TMPH], g_current_regs[REG_ZL], @@ -114,16 +114,16 @@ static inline void up_registerdump(void) #if CONFIG_HCS12_MSOFTREGS > 2 # error "Need to save more registers" #elif CONFIG_HCS12_MSOFTREGS == 2 - alert("SOFTREGS: %02x%02x :%02x%02x\n", + _alert("SOFTREGS: %02x%02x :%02x%02x\n", g_current_regs[REG_SOFTREG1], g_current_regs[REG_SOFTREG1+1], g_current_regs[REG_SOFTREG2], g_current_regs[REG_SOFTREG2+1]); #elif CONFIG_HCS12_MSOFTREGS == 1 - alert("SOFTREGS: %02x%02x\n", g_current_regs[REG_SOFTREG1], + _alert("SOFTREGS: %02x%02x\n", g_current_regs[REG_SOFTREG1], g_current_regs[REG_SOFTREG1+1]); #endif #ifndef CONFIG_HCS12_NONBANKED - alert("PPAGE: %02x\n", g_current_regs[REG_PPAGE],); + _alert("PPAGE: %02x\n", g_current_regs[REG_PPAGE],); #endif } } @@ -193,10 +193,10 @@ static void up_dumpstate(void) /* Show interrupt stack info */ - alert("sp: %04x\n", sp); - alert("IRQ stack:\n"); - alert(" base: %04x\n", istackbase); - alert(" size: %04x\n", istacksize); + _alert("sp: %04x\n", sp); + _alert("IRQ stack:\n"); + _alert(" base: %04x\n", istackbase); + _alert(" size: %04x\n", istacksize); /* Does the current stack pointer lie within the interrupt * stack? @@ -213,18 +213,18 @@ static void up_dumpstate(void) */ sp = g_intstackbase; - alert("sp: %04x\n", sp); + _alert("sp: %04x\n", sp); } /* Show user stack info */ - alert("User stack:\n"); - alert(" base: %04x\n", ustackbase); - alert(" size: %04x\n", ustacksize); + _alert("User stack:\n"); + _alert(" base: %04x\n", ustackbase); + _alert(" size: %04x\n", ustacksize); #else - alert("sp: %04x\n", sp); - alert("stack base: %04x\n", ustackbase); - alert("stack size: %04x\n", ustacksize); + _alert("sp: %04x\n", sp); + _alert("stack base: %04x\n", ustackbase); + _alert("stack size: %04x\n", ustacksize); #endif /* Dump the user stack if the stack pointer lies within the allocated user @@ -234,7 +234,7 @@ static void up_dumpstate(void) if (sp > ustackbase || sp <= ustackbase - ustacksize) { #if !defined(CONFIG_ARCH_INTERRUPTSTACK) || CONFIG_ARCH_INTERRUPTSTACK < 4 - alert("ERROR: Stack pointer is not within allocated stack\n"); + _alert("ERROR: Stack pointer is not within allocated stack\n"); #endif } else @@ -301,10 +301,10 @@ void up_assert(const uint8_t *filename, int lineno) board_autoled_on(LED_ASSERTION); #if CONFIG_TASK_NAME_SIZE > 0 - alert("Assertion failed at file:%s line: %d task: %s\n", + _alert("Assertion failed at file:%s line: %d task: %s\n", filename, lineno, rtcb->name); #else - alert("Assertion failed at file:%s line: %d\n", + _alert("Assertion failed at file:%s line: %d\n", filename, lineno); #endif diff --git a/arch/mips/src/mips32/up_assert.c b/arch/mips/src/mips32/up_assert.c index 1f4ab15d6b..119844eb99 100644 --- a/arch/mips/src/mips32/up_assert.c +++ b/arch/mips/src/mips32/up_assert.c @@ -138,10 +138,10 @@ void up_assert(const uint8_t *filename, int lineno) board_autoled_on(LED_ASSERTION); #if CONFIG_TASK_NAME_SIZE > 0 - alert("Assertion failed at file:%s line: %d task: %s\n", + _alert("Assertion failed at file:%s line: %d task: %s\n", filename, lineno, rtcb->name); #else - alert("Assertion failed at file:%s line: %d\n", + _alert("Assertion failed at file:%s line: %d\n", filename, lineno); #endif diff --git a/arch/mips/src/mips32/up_dumpstate.c b/arch/mips/src/mips32/up_dumpstate.c index f5a2a8474d..db9fcda657 100644 --- a/arch/mips/src/mips32/up_dumpstate.c +++ b/arch/mips/src/mips32/up_dumpstate.c @@ -86,7 +86,7 @@ static void up_stackdump(uint32_t sp, uint32_t stack_base) for (stack = sp & ~0x1f; stack < stack_base; stack += 32) { uint32_t *ptr = (uint32_t *)stack; - alert("%08x: %08x %08x %08x %08x %08x %08x %08x %08x\n", + _alert("%08x: %08x %08x %08x %08x %08x %08x %08x %08x\n", stack, ptr[0], ptr[1], ptr[2], ptr[3], ptr[4], ptr[5], ptr[6], ptr[7]); } @@ -102,27 +102,27 @@ static inline void up_registerdump(void) if (g_current_regs) { - alert("MFLO:%08x MFHI:%08x EPC:%08x STATUS:%08x\n", + _alert("MFLO:%08x MFHI:%08x EPC:%08x STATUS:%08x\n", g_current_regs[REG_MFLO], g_current_regs[REG_MFHI], g_current_regs[REG_EPC], g_current_regs[REG_STATUS]); - alert("AT:%08x V0:%08x V1:%08x A0:%08x A1:%08x A2:%08x A3:%08x\n", + _alert("AT:%08x V0:%08x V1:%08x A0:%08x A1:%08x A2:%08x A3:%08x\n", g_current_regs[REG_AT], g_current_regs[REG_V0], g_current_regs[REG_V1], g_current_regs[REG_A0], g_current_regs[REG_A1], g_current_regs[REG_A2], g_current_regs[REG_A3]); - alert("T0:%08x T1:%08x T2:%08x T3:%08x T4:%08x T5:%08x T6:%08x T7:%08x\n", + _alert("T0:%08x T1:%08x T2:%08x T3:%08x T4:%08x T5:%08x T6:%08x T7:%08x\n", g_current_regs[REG_T0], g_current_regs[REG_T1], g_current_regs[REG_T2], g_current_regs[REG_T3], g_current_regs[REG_T4], g_current_regs[REG_T5], g_current_regs[REG_T6], g_current_regs[REG_T7]); - alert("S0:%08x S1:%08x S2:%08x S3:%08x S4:%08x S5:%08x S6:%08x S7:%08x\n", + _alert("S0:%08x S1:%08x S2:%08x S3:%08x S4:%08x S5:%08x S6:%08x S7:%08x\n", g_current_regs[REG_S0], g_current_regs[REG_S1], g_current_regs[REG_S2], g_current_regs[REG_S3], g_current_regs[REG_S4], g_current_regs[REG_S5], g_current_regs[REG_S6], g_current_regs[REG_S7]); #ifdef MIPS32_SAVE_GP - alert("T8:%08x T9:%08x GP:%08x SP:%08x FP:%08x RA:%08x\n", + _alert("T8:%08x T9:%08x GP:%08x SP:%08x FP:%08x RA:%08x\n", g_current_regs[REG_T8], g_current_regs[REG_T9], g_current_regs[REG_GP], g_current_regs[REG_SP], g_current_regs[REG_FP], g_current_regs[REG_RA]); #else - alert("T8:%08x T9:%08x SP:%08x FP:%08x RA:%08x\n", + _alert("T8:%08x T9:%08x SP:%08x FP:%08x RA:%08x\n", g_current_regs[REG_T8], g_current_regs[REG_T9], g_current_regs[REG_SP], g_current_regs[REG_FP], g_current_regs[REG_RA]); #endif @@ -169,10 +169,10 @@ void up_dumpstate(void) /* Show interrupt stack info */ - alert("sp: %08x\n", sp); - alert("IRQ stack:\n"); - alert(" base: %08x\n", istackbase); - alert(" size: %08x\n", istacksize); + _alert("sp: %08x\n", sp); + _alert("IRQ stack:\n"); + _alert(" base: %08x\n", istackbase); + _alert(" size: %08x\n", istacksize); /* Does the current stack pointer lie within the interrupt * stack? @@ -189,18 +189,18 @@ void up_dumpstate(void) */ sp = g_intstackbase; - alert("sp: %08x\n", sp); + _alert("sp: %08x\n", sp); } /* Show user stack info */ - alert("User stack:\n"); - alert(" base: %08x\n", ustackbase); - alert(" size: %08x\n", ustacksize); + _alert("User stack:\n"); + _alert(" base: %08x\n", ustackbase); + _alert(" size: %08x\n", ustacksize); #else - alert("sp: %08x\n", sp); - alert("stack base: %08x\n", ustackbase); - alert("stack size: %08x\n", ustacksize); + _alert("sp: %08x\n", sp); + _alert("stack base: %08x\n", ustackbase); + _alert("stack size: %08x\n", ustacksize); #endif /* Dump the user stack if the stack pointer lies within the allocated user @@ -210,7 +210,7 @@ void up_dumpstate(void) if (sp > ustackbase || sp <= ustackbase - ustacksize) { #if !defined(CONFIG_ARCH_INTERRUPTSTACK) || CONFIG_ARCH_INTERRUPTSTACK < 4 - alert("ERROR: Stack pointer is not within allocated stack\n"); + _alert("ERROR: Stack pointer is not within allocated stack\n"); #endif } else diff --git a/arch/mips/src/pic32mx/pic32mx-exception.c b/arch/mips/src/pic32mx/pic32mx-exception.c index 7ff728db31..86d8ddf133 100644 --- a/arch/mips/src/pic32mx/pic32mx-exception.c +++ b/arch/mips/src/pic32mx/pic32mx-exception.c @@ -90,88 +90,88 @@ uint32_t *pic32mx_exception(uint32_t *regs) switch (cause & CP0_CAUSE_EXCCODE_MASK) { case CP0_CAUSE_EXCCODE_INT: /* Interrupt */ - alert("EXCEPTION: Interrupt" + _alert("EXCEPTION: Interrupt" " CAUSE: %08x EPC: %08x\n", cause, epc); break; case CP0_CAUSE_EXCCODE_TLBL: /* TLB exception (load or instruction fetch) */ - alert("EXCEPTION: TLB exception (load or instruction fetch)" + _alert("EXCEPTION: TLB exception (load or instruction fetch)" " CAUSE: %08x EPC:%08x\n", cause, epc); break; case CP0_CAUSE_EXCCODE_TLBS: /* TLB exception (store) */ - alert("EXCEPTION: TLB exception (store)" + _alert("EXCEPTION: TLB exception (store)" " CAUSE: %08x EPC: %08x\n", cause, epc); break; case CP0_CAUSE_EXCCODE_ADEL: /* Address error exception (load or instruction fetch) */ - alert("EXCEPTION: Address error exception (load or instruction fetch)" + _alert("EXCEPTION: Address error exception (load or instruction fetch)" " CAUSE: %08x EPC: %08x\n", cause, epc); break; case CP0_CAUSE_EXCCODE_ADES: /* Address error exception (store) */ - alert("EXCEPTION: Address error exception (store)" + _alert("EXCEPTION: Address error exception (store)" " CAUSE: %08x EPC: %08x\n", cause, epc); break; case CP0_CAUSE_EXCCODE_IBE: /* Bus error exception (instruction fetch) */ - alert("EXCEPTION: Bus error exception (instruction fetch)" + _alert("EXCEPTION: Bus error exception (instruction fetch)" " CAUSE: %08x EPC: %08x\n", cause, epc); break; case CP0_CAUSE_EXCCODE_DBE: /* Bus error exception (data reference: load or store) */ - alert("EXCEPTION: Bus error exception (data reference: load or store)" + _alert("EXCEPTION: Bus error exception (data reference: load or store)" " CAUSE: %08x EPC: %08x\n", cause, epc); break; case CP0_CAUSE_EXCCODE_SYS: /* Syscall exception */ - alert("EXCEPTION: Syscall exception" + _alert("EXCEPTION: Syscall exception" " CAUSE: %08x EPC: %08x\n", cause, epc); break; case CP0_CAUSE_EXCCODE_BP: /* Breakpoint exception */ - alert("EXCEPTION: Breakpoint exception" + _alert("EXCEPTION: Breakpoint exception" " CAUSE: %08x EPC: %08x\n", cause, epc); break; case CP0_CAUSE_EXCCODE_RI: /* Reserved instruction exception */ - alert("EXCEPTION: Reserved instruction exception" + _alert("EXCEPTION: Reserved instruction exception" " CAUSE: %08x EPC: %08x\n", cause, epc); break; case CP0_CAUSE_EXCCODE_CPU: /* Coprocessor Unusable exception */ - alert("EXCEPTION: Coprocessor Unusable exception" + _alert("EXCEPTION: Coprocessor Unusable exception" " CAUSE: %08x EPC: %08x\n", cause, epc); break; case CP0_CAUSE_EXCCODE_OV: /* Arithmetic Overflow exception */ - alert("EXCEPTION: Arithmetic Overflow exception" + _alert("EXCEPTION: Arithmetic Overflow exception" " CAUSE: %08x EPC: %08x\n", cause, epc); break; case CP0_CAUSE_EXCCODE_TR: /* Trap exception */ - alert("EXCEPTION: Trap exception" + _alert("EXCEPTION: Trap exception" " CAUSE: %08x EPC: %08x\n", cause, epc); break; case CP0_CAUSE_EXCCODE_FPE: /* Floating point exception */ - alert("EXCEPTION: Floating point exception" + _alert("EXCEPTION: Floating point exception" " CAUSE: %08x EPC: %08x\n", cause, epc); break; case CP0_CAUSE_EXCCODE_C2E: /* Precise Coprocessor 2 exceptions */ - alert("EXCEPTION: Precise Coprocessor 2 exceptions" + _alert("EXCEPTION: Precise Coprocessor 2 exceptions" " CAUSE: %08x EPC: %08x\n", cause, epc); break; case CP0_CAUSE_EXCCODE_MDMX: /* MDMX Unusable (MIPS64) */ - alert("EXCEPTION: MDMX Unusable (MIPS64)" + _alert("EXCEPTION: MDMX Unusable (MIPS64)" " CAUSE: %08x EPC: %08x\n", cause, epc); break; case CP0_CAUSE_EXCCODE_WATCH: /* WatchHi/WatchLo address */ - alert("EXCEPTION: WatchHi/WatchLo address" + _alert("EXCEPTION: WatchHi/WatchLo address" " CAUSE: %08x EPC: %08x\n", cause, epc); break; case CP0_CAUSE_EXCCODE_MCHECK: /* Machine check */ - alert("EXCEPTION: Machine check" + _alert("EXCEPTION: Machine check" " CAUSE: %08x EPC: %08x\n", cause, epc); break; case CP0_CAUSE_EXCCODE_CACHEERR: /* Cache error */ - alert("EXCEPTION: Cache error" + _alert("EXCEPTION: Cache error" " CAUSE: %08x EPC: %08x\n", cause, epc); break; default: - alert("EXCEPTION: Unknown" + _alert("EXCEPTION: Unknown" " CAUSE: %08x EPC: %08x\n", cause, epc); break; } #else - alert("EXCEPTION: CAUSE: %08x EPC: %08x\n", cause, epc); + _alert("EXCEPTION: CAUSE: %08x EPC: %08x\n", cause, epc); #endif #endif diff --git a/arch/mips/src/pic32mz/pic32mz-exception.c b/arch/mips/src/pic32mz/pic32mz-exception.c index 1397d1063f..256010e910 100644 --- a/arch/mips/src/pic32mz/pic32mz-exception.c +++ b/arch/mips/src/pic32mz/pic32mz-exception.c @@ -90,88 +90,88 @@ uint32_t *pic32mz_exception(uint32_t *regs) switch (cause & CP0_CAUSE_EXCCODE_MASK) { case CP0_CAUSE_EXCCODE_INT: /* Interrupt */ - alert("EXCEPTION: Interrupt" + _alert("EXCEPTION: Interrupt" " CAUSE: %08x EPC: %08x\n", cause, epc); break; case CP0_CAUSE_EXCCODE_TLBL: /* TLB exception (load or instruction fetch) */ - alert("EXCEPTION: TLB exception (load or instruction fetch)" + _alert("EXCEPTION: TLB exception (load or instruction fetch)" " CAUSE: %08x EPC:%08x\n", cause, epc); break; case CP0_CAUSE_EXCCODE_TLBS: /* TLB exception (store) */ - alert("EXCEPTION: TLB exception (store)" + _alert("EXCEPTION: TLB exception (store)" " CAUSE: %08x EPC: %08x\n", cause, epc); break; case CP0_CAUSE_EXCCODE_ADEL: /* Address error exception (load or instruction fetch) */ - alert("EXCEPTION: Address error exception (load or instruction fetch)" + _alert("EXCEPTION: Address error exception (load or instruction fetch)" " CAUSE: %08x EPC: %08x\n", cause, epc); break; case CP0_CAUSE_EXCCODE_ADES: /* Address error exception (store) */ - alert("EXCEPTION: Address error exception (store)" + _alert("EXCEPTION: Address error exception (store)" " CAUSE: %08x EPC: %08x\n", cause, epc); break; case CP0_CAUSE_EXCCODE_IBE: /* Bus error exception (instruction fetch) */ - alert("EXCEPTION: Bus error exception (instruction fetch)" + _alert("EXCEPTION: Bus error exception (instruction fetch)" " CAUSE: %08x EPC: %08x\n", cause, epc); break; case CP0_CAUSE_EXCCODE_DBE: /* Bus error exception (data reference: load or store) */ - alert("EXCEPTION: Bus error exception (data reference: load or store)" + _alert("EXCEPTION: Bus error exception (data reference: load or store)" " CAUSE: %08x EPC: %08x\n", cause, epc); break; case CP0_CAUSE_EXCCODE_SYS: /* Syscall exception */ - alert("EXCEPTION: Syscall exception" + _alert("EXCEPTION: Syscall exception" " CAUSE: %08x EPC: %08x\n", cause, epc); break; case CP0_CAUSE_EXCCODE_BP: /* Breakpoint exception */ - alert("EXCEPTION: Breakpoint exception" + _alert("EXCEPTION: Breakpoint exception" " CAUSE: %08x EPC: %08x\n", cause, epc); break; case CP0_CAUSE_EXCCODE_RI: /* Reserved instruction exception */ - alert("EXCEPTION: Reserved instruction exception" + _alert("EXCEPTION: Reserved instruction exception" " CAUSE: %08x EPC: %08x\n", cause, epc); break; case CP0_CAUSE_EXCCODE_CPU: /* Coprocessor Unusable exception */ - alert("EXCEPTION: Coprocessor Unusable exception" + _alert("EXCEPTION: Coprocessor Unusable exception" " CAUSE: %08x EPC: %08x\n", cause, epc); break; case CP0_CAUSE_EXCCODE_OV: /* Arithmetic Overflow exception */ - alert("EXCEPTION: Arithmetic Overflow exception" + _alert("EXCEPTION: Arithmetic Overflow exception" " CAUSE: %08x EPC: %08x\n", cause, epc); break; case CP0_CAUSE_EXCCODE_TR: /* Trap exception */ - alert("EXCEPTION: Trap exception" + _alert("EXCEPTION: Trap exception" " CAUSE: %08x EPC: %08x\n", cause, epc); break; case CP0_CAUSE_EXCCODE_FPE: /* Floating point exception */ - alert("EXCEPTION: Floating point exception" + _alert("EXCEPTION: Floating point exception" " CAUSE: %08x EPC: %08x\n", cause, epc); break; case CP0_CAUSE_EXCCODE_C2E: /* Precise Coprocessor 2 exceptions */ - alert("EXCEPTION: Precise Coprocessor 2 exceptions" + _alert("EXCEPTION: Precise Coprocessor 2 exceptions" " CAUSE: %08x EPC: %08x\n", cause, epc); break; case CP0_CAUSE_EXCCODE_MDMX: /* MDMX Unusable (MIPS64) */ - alert("EXCEPTION: MDMX Unusable (MIPS64)" + _alert("EXCEPTION: MDMX Unusable (MIPS64)" " CAUSE: %08x EPC: %08x\n", cause, epc); break; case CP0_CAUSE_EXCCODE_WATCH: /* WatchHi/WatchLo address */ - alert("EXCEPTION: WatchHi/WatchLo address" + _alert("EXCEPTION: WatchHi/WatchLo address" " CAUSE: %08x EPC: %08x\n", cause, epc); break; case CP0_CAUSE_EXCCODE_MCHECK: /* Machine check */ - alert("EXCEPTION: Machine check" + _alert("EXCEPTION: Machine check" " CAUSE: %08x EPC: %08x\n", cause, epc); break; case CP0_CAUSE_EXCCODE_CACHEERR: /* Cache error */ - alert("EXCEPTION: Cache error" + _alert("EXCEPTION: Cache error" " CAUSE: %08x EPC: %08x\n", cause, epc); break; default: - alert("EXCEPTION: Unknown" + _alert("EXCEPTION: Unknown" " CAUSE: %08x EPC: %08x\n", cause, epc); break; } #else - alert("EXCEPTION: CAUSE: %08x EPC: %08x\n", cause, epc); + _alert("EXCEPTION: CAUSE: %08x EPC: %08x\n", cause, epc); #endif #endif diff --git a/arch/sh/src/common/up_assert.c b/arch/sh/src/common/up_assert.c index 4919a30363..95abc9b190 100644 --- a/arch/sh/src/common/up_assert.c +++ b/arch/sh/src/common/up_assert.c @@ -139,10 +139,10 @@ void up_assert(const uint8_t *filename, int lineno) board_autoled_on(LED_ASSERTION); #if CONFIG_TASK_NAME_SIZE > 0 - alert("Assertion failed at file:%s line: %d task: %s\n", + _alert("Assertion failed at file:%s line: %d task: %s\n", filename, lineno, rtcb->name); #else - alert("Assertion failed at file:%s line: %d\n", + _alert("Assertion failed at file:%s line: %d\n", filename, lineno); #endif diff --git a/arch/sh/src/m16c/m16c_dumpstate.c b/arch/sh/src/m16c/m16c_dumpstate.c index 6cd4f545d4..7dc1a74ee4 100644 --- a/arch/sh/src/m16c/m16c_dumpstate.c +++ b/arch/sh/src/m16c/m16c_dumpstate.c @@ -97,7 +97,7 @@ static void m16c_stackdump(uint16_t sp, uint16_t stack_base) for (stack = sp & ~7; stack < stack_base; stack += 8) { uint8_t *ptr = (uint8_t*)stack; - alert("%04x: %02x %02x %02x %02x %02x %02x %02x %02x\n", + _alert("%04x: %02x %02x %02x %02x %02x %02x %02x %02x\n", stack, ptr[0], ptr[1], ptr[2], ptr[3], ptr[4], ptr[5], ptr[6], ptr[7]); } } @@ -116,14 +116,14 @@ static inline void m16c_registerdump(void) { /* Yes.. dump the interrupt registers */ - alert("PC: %02x%02x%02x FLG: %02x00%02x FB: %02x%02x SB: %02x%02x SP: %02x%02x\n", + _alert("PC: %02x%02x%02x FLG: %02x00%02x FB: %02x%02x SB: %02x%02x SP: %02x%02x\n", ptr[REG_FLGPCHI] & 0xff, ptr[REG_PC], ptr[REG_PC+1], ptr[REG_FLGPCHI] >> 8, ptr[REG_FLG], ptr[REG_FB], ptr[REG_FB+1], ptr[REG_SB], ptr[REG_SB+1], ptr[REG_SP], ptr[REG_SP+1]); - alert("R0: %02x%02x R1: %02x%02x R2: %02x%02x A0: %02x%02x A1: %02x%02x\n", + _alert("R0: %02x%02x R1: %02x%02x R2: %02x%02x A0: %02x%02x A1: %02x%02x\n", ptr[REG_R0], ptr[REG_R0+1], ptr[REG_R1], ptr[REG_R1+1], ptr[REG_R2], ptr[REG_R2+1], ptr[REG_R3], ptr[REG_R3+1], ptr[REG_A0], ptr[REG_A0+1], ptr[REG_A1], ptr[REG_A1+1]); @@ -179,10 +179,10 @@ void up_dumpstate(void) /* Show interrupt stack info */ - alert("sp: %04x\n", sp); - alert("IRQ stack:\n"); - alert(" base: %04x\n", istackbase); - alert(" size: %04x\n", istacksize); + _alert("sp: %04x\n", sp); + _alert("IRQ stack:\n"); + _alert(" base: %04x\n", istackbase); + _alert(" size: %04x\n", istacksize); /* Does the current stack pointer lie within the interrupt * stack? @@ -197,18 +197,18 @@ void up_dumpstate(void) /* Extract the user stack pointer from the register area */ sp = m16c_getusersp(); - alert("sp: %04x\n", sp); + _alert("sp: %04x\n", sp); } /* Show user stack info */ - alert("User stack:\n"); - alert(" base: %04x\n", ustackbase); - alert(" size: %04x\n", ustacksize); + _alert("User stack:\n"); + _alert(" base: %04x\n", ustackbase); + _alert(" size: %04x\n", ustacksize); #else - alert("sp: %04x\n", sp); - alert("stack base: %04x\n", ustackbase); - alert("stack size: %04x\n", ustacksize); + _alert("sp: %04x\n", sp); + _alert("stack base: %04x\n", ustackbase); + _alert("stack size: %04x\n", ustacksize); #endif /* Dump the user stack if the stack pointer lies within the allocated user @@ -218,7 +218,7 @@ void up_dumpstate(void) if (sp > ustackbase || sp <= ustackbase - ustacksize) { #if !defined(CONFIG_ARCH_INTERRUPTSTACK) || CONFIG_ARCH_INTERRUPTSTACK < 4 - alert("ERROR: Stack pointer is not within allocated stack\n"); + _alert("ERROR: Stack pointer is not within allocated stack\n"); #endif } else diff --git a/arch/sh/src/sh1/sh1_dumpstate.c b/arch/sh/src/sh1/sh1_dumpstate.c index 487bc854ad..e9b0e59078 100644 --- a/arch/sh/src/sh1/sh1_dumpstate.c +++ b/arch/sh/src/sh1/sh1_dumpstate.c @@ -84,7 +84,7 @@ static void sh1_stackdump(uint32_t sp, uint32_t stack_base) for (stack = sp & ~0x1f; stack < stack_base; stack += 32) { uint32_t *ptr = (uint32_t*)stack; - alert("%08x: %08x %08x %08x %08x %08x %08x %08x %08x\n", + _alert("%08x: %08x %08x %08x %08x %08x %08x %08x %08x\n", stack, ptr[0], ptr[1], ptr[2], ptr[3], ptr[4], ptr[5], ptr[6], ptr[7]); } @@ -104,17 +104,17 @@ static inline void sh1_registerdump(void) { /* Yes.. dump the interrupt registers */ - alert("PC: %08x SR=%08x\n", + _alert("PC: %08x SR=%08x\n", ptr[REG_PC], ptr[REG_SR]); - alert("PR: %08x GBR: %08x MACH: %08x MACL: %08x\n", + _alert("PR: %08x GBR: %08x MACH: %08x MACL: %08x\n", ptr[REG_PR], ptr[REG_GBR], ptr[REG_MACH], ptr[REG_MACL]); - alert("R%d: %08x %08x %08x %08x %08x %08x %08x %08x\n", 0, + _alert("R%d: %08x %08x %08x %08x %08x %08x %08x %08x\n", 0, ptr[REG_R0], ptr[REG_R1], ptr[REG_R2], ptr[REG_R3], ptr[REG_R4], ptr[REG_R5], ptr[REG_R6], ptr[REG_R7]); - alert("R%d: %08x %08x %08x %08x %08x %08x %08x %08x\n", 8, + _alert("R%d: %08x %08x %08x %08x %08x %08x %08x %08x\n", 8, ptr[REG_R8], ptr[REG_R9], ptr[REG_R10], ptr[REG_R11], ptr[REG_R12], ptr[REG_R13], ptr[REG_R14], ptr[REG_R15]); } @@ -160,10 +160,10 @@ void up_dumpstate(void) /* Show interrupt stack info */ - alert("sp: %08x\n", sp); - alert("IRQ stack:\n"); - alert(" base: %08x\n", istackbase); - alert(" size: %08x\n", istacksize); + _alert("sp: %08x\n", sp); + _alert("IRQ stack:\n"); + _alert(" base: %08x\n", istackbase); + _alert(" size: %08x\n", istacksize); /* Does the current stack pointer lie within the interrupt * stack? @@ -180,18 +180,18 @@ void up_dumpstate(void) */ sp = g_intstackbase; - alert("sp: %08x\n", sp); + _alert("sp: %08x\n", sp); } /* Show user stack info */ - alert("User stack:\n"); - alert(" base: %08x\n", ustackbase); - alert(" size: %08x\n", ustacksize); + _alert("User stack:\n"); + _alert(" base: %08x\n", ustackbase); + _alert(" size: %08x\n", ustacksize); #else - alert("sp: %08x\n", sp); - alert("stack base: %08x\n", ustackbase); - alert("stack size: %08x\n", ustacksize); + _alert("sp: %08x\n", sp); + _alert("stack base: %08x\n", ustackbase); + _alert("stack size: %08x\n", ustacksize); #endif /* Dump the user stack if the stack pointer lies within the allocated user @@ -201,7 +201,7 @@ void up_dumpstate(void) if (sp > ustackbase || sp <= ustackbase - ustacksize) { #if !defined(CONFIG_ARCH_INTERRUPTSTACK) || CONFIG_ARCH_INTERRUPTSTACK < 4 - alert("ERROR: Stack pointer is not within allocated stack\n"); + _alert("ERROR: Stack pointer is not within allocated stack\n"); #endif } else diff --git a/arch/x86/src/common/up_assert.c b/arch/x86/src/common/up_assert.c index 5d450e6fd9..3b6caececc 100644 --- a/arch/x86/src/common/up_assert.c +++ b/arch/x86/src/common/up_assert.c @@ -81,7 +81,7 @@ static void up_stackdump(uint32_t sp, uint32_t stack_base) for (stack = sp & ~0x1f; stack < stack_base; stack += 32) { uint32_t *ptr = (uint32_t*)stack; - alert("%08x: %08x %08x %08x %08x %08x %08x %08x %08x\n", + _alert("%08x: %08x %08x %08x %08x %08x %08x %08x %08x\n", stack, ptr[0], ptr[1], ptr[2], ptr[3], ptr[4], ptr[5], ptr[6], ptr[7]); } @@ -152,10 +152,10 @@ static void up_dumpstate(void) /* Show interrupt stack info */ - alert("sp: %08x\n", sp); - alert("IRQ stack:\n"); - alert(" base: %08x\n", istackbase); - alert(" size: %08x\n", istacksize); + _alert("sp: %08x\n", sp); + _alert("IRQ stack:\n"); + _alert(" base: %08x\n", istackbase); + _alert(" size: %08x\n", istacksize); /* Does the current stack pointer lie within the interrupt * stack? @@ -172,18 +172,18 @@ static void up_dumpstate(void) */ sp = g_intstackbase; - alert("sp: %08x\n", sp); + _alert("sp: %08x\n", sp); } /* Show user stack info */ - alert("User stack:\n"); - alert(" base: %08x\n", ustackbase); - alert(" size: %08x\n", ustacksize); + _alert("User stack:\n"); + _alert(" base: %08x\n", ustackbase); + _alert(" size: %08x\n", ustacksize); #else - alert("sp: %08x\n", sp); - alert("stack base: %08x\n", ustackbase); - alert("stack size: %08x\n", ustacksize); + _alert("sp: %08x\n", sp); + _alert("stack base: %08x\n", ustackbase); + _alert("stack size: %08x\n", ustacksize); #endif /* Dump the user stack if the stack pointer lies within the allocated user @@ -193,7 +193,7 @@ static void up_dumpstate(void) if (sp > ustackbase || sp <= ustackbase - ustacksize) { #if !defined(CONFIG_ARCH_INTERRUPTSTACK) || CONFIG_ARCH_INTERRUPTSTACK < 4 - alert("ERROR: Stack pointer is not within allocated stack\n"); + _alert("ERROR: Stack pointer is not within allocated stack\n"); #endif } else @@ -263,10 +263,10 @@ void up_assert(const uint8_t *filename, int lineno) board_autoled_on(LED_ASSERTION); #if CONFIG_TASK_NAME_SIZE > 0 - alert("Assertion failed at file:%s line: %d task: %s\n", + _alert("Assertion failed at file:%s line: %d task: %s\n", filename, lineno, rtcb->name); #else - alert("Assertion failed at file:%s line: %d\n", + _alert("Assertion failed at file:%s line: %d\n", filename, lineno); #endif diff --git a/arch/x86/src/i486/up_regdump.c b/arch/x86/src/i486/up_regdump.c index b3da1b603e..d28ec481ed 100644 --- a/arch/x86/src/i486/up_regdump.c +++ b/arch/x86/src/i486/up_regdump.c @@ -54,13 +54,13 @@ void up_registerdump(uint32_t *regs) { - alert(" ds:%08x irq:%08x err:%08x\n", + _alert(" ds:%08x irq:%08x err:%08x\n", regs[REG_DS], regs[REG_IRQNO], regs[REG_ERRCODE]); - alert("edi:%08x esi:%08x ebp:%08x esp:%08x\n", + _alert("edi:%08x esi:%08x ebp:%08x esp:%08x\n", regs[REG_EDI], regs[REG_ESI], regs[REG_EBP], regs[REG_ESP]); - alert("ebx:%08x edx:%08x ecx:%08x eax:%08x\n", + _alert("ebx:%08x edx:%08x ecx:%08x eax:%08x\n", regs[REG_EBX], regs[REG_EDX], regs[REG_ECX], regs[REG_EAX]); - alert("eip:%08x cs:%08x flg:%08x sp:%08x ss:%08x\n", + _alert("eip:%08x cs:%08x flg:%08x sp:%08x ss:%08x\n", regs[REG_EIP], regs[REG_CS], regs[REG_EFLAGS], regs[REG_SP], regs[REG_SS]); } diff --git a/arch/z16/src/common/up_assert.c b/arch/z16/src/common/up_assert.c index 1ef880a041..628c34f1fa 100644 --- a/arch/z16/src/common/up_assert.c +++ b/arch/z16/src/common/up_assert.c @@ -143,17 +143,17 @@ void up_assert(void) #ifdef CONFIG_HAVE_FILENAME #if CONFIG_TASK_NAME_SIZE > 0 - alert("Assertion failed at file:%s line: %d task: %s\n", + _alert("Assertion failed at file:%s line: %d task: %s\n", filename, lineno, rtcb->name); #else - alert("Assertion failed at file:%s line: %d\n", + _alert("Assertion failed at file:%s line: %d\n", filename, lineno); #endif #else #if CONFIG_TASK_NAME_SIZE > 0 - alert("Assertion failed: task: %s\n", rtcb->name); + _alert("Assertion failed: task: %s\n", rtcb->name); #else - alert("Assertion failed\n"); + _alert("Assertion failed\n"); #endif #endif diff --git a/arch/z16/src/common/up_registerdump.c b/arch/z16/src/common/up_registerdump.c index f167926a52..dbee6553dd 100644 --- a/arch/z16/src/common/up_registerdump.c +++ b/arch/z16/src/common/up_registerdump.c @@ -62,14 +62,14 @@ static void up_registerdump(void) #ifdef CONFIG_DEBUG_INFO FAR uint32_t *regs32 = (FAR uint32_t*)g_current_regs; - alert("R0 :%08x R1 :%08x R2 :%08x R3 :%08x " + _alert("R0 :%08x R1 :%08x R2 :%08x R3 :%08x " "R4 :%08x R5 :%08x R6 :%08x R7 :%08x\n" regs32[REG_R0/2], regs32[REG_R1/2], regs32[REG_R2/2], regs32[REG_R3/2], regs32[REG_R4/2], regs32[REG_R5/2], regs32[REG_R6/2], regs32[REG_R7/2]); - alert("R8 :%08x R9 :%08x R10:%08x R11:%08x R12:%08x R13:%08x\n" + _alert("R8 :%08x R9 :%08x R10:%08x R11:%08x R12:%08x R13:%08x\n" regs32[REG_R8/2], regs32[REG_R9/2], regs32[REG_R10/2], regs3[REG_R11/2], regs32[REG_R12/2], regs32[REG_R13/2]); - alert("FP :%08x SP :%08x FLG:%04x\n" + _alert("FP :%08x SP :%08x FLG:%04x\n" regs32[REG_R14/2], regs32[REG_R15/2], g_current_regs[REG_FLAGS]); #endif } diff --git a/arch/z16/src/common/up_stackdump.c b/arch/z16/src/common/up_stackdump.c index 35bc6d4979..0abb3a33ae 100644 --- a/arch/z16/src/common/up_stackdump.c +++ b/arch/z16/src/common/up_stackdump.c @@ -67,9 +67,9 @@ static void up_stackdump(void) chipreg_t stack_base = (chipreg_t)rtcb->adj_stack_ptr; chipreg_t stack_size = (chipreg_t)rtcb->adj_stack_size; - alert("stack_base: %08x\n", stack_base); - alert("stack_size: %08x\n", stack_size); - alert("sp: %08x\n", sp); + _alert("stack_base: %08x\n", stack_base); + _alert("stack_size: %08x\n", stack_size); + _alert("sp: %08x\n", sp); if (sp >= stack_base || sp < stack_base - stack_size) { @@ -83,7 +83,7 @@ static void up_stackdump(void) for (stack = sp & ~0x0f; stack < stack_base; stack += 8*sizeof(chipreg_t)) { chipreg_t *ptr = (chipreg_t*)stack; - alert("%08x: %08x %08x %08x %08x %08x %08x %08x %08x\n", + _alert("%08x: %08x %08x %08x %08x %08x %08x %08x %08x\n", stack, ptr[0], ptr[1], ptr[2], ptr[3], ptr[4], ptr[5], ptr[6], ptr[7]); } diff --git a/arch/z80/src/common/up_assert.c b/arch/z80/src/common/up_assert.c index ea1dd0c5d7..49b7240928 100644 --- a/arch/z80/src/common/up_assert.c +++ b/arch/z80/src/common/up_assert.c @@ -142,17 +142,17 @@ void up_assert(void) #ifdef CONFIG_HAVE_FILENAME #if CONFIG_TASK_NAME_SIZE > 0 - alert("Assertion failed at file:%s line: %d task: %s\n", + _alert("Assertion failed at file:%s line: %d task: %s\n", filename, lineno, rtcb->name); #else - alert("Assertion failed at file:%s line: %d\n", + _alert("Assertion failed at file:%s line: %d\n", filename, lineno); #endif #else #if CONFIG_TASK_NAME_SIZE > 0 - alert("Assertion failed: task: %s\n", rtcb->name); + _alert("Assertion failed: task: %s\n", rtcb->name); #else - alert("Assertion failed\n"); + _alert("Assertion failed\n"); #endif #endif diff --git a/arch/z80/src/common/up_stackdump.c b/arch/z80/src/common/up_stackdump.c index 0e4e4ea9c4..1ad64c66a9 100644 --- a/arch/z80/src/common/up_stackdump.c +++ b/arch/z80/src/common/up_stackdump.c @@ -68,13 +68,13 @@ static void up_stackdump(void) uint16_t stack_base = (uint16_t)rtcb->adj_stack_ptr; uint16_t stack_size = (uint16_t)rtcb->adj_stack_size; - alert("stack_base: %04x\n", stack_base); - alert("stack_size: %04x\n", stack_size); - alert("sp: %04x\n", sp); + _alert("stack_base: %04x\n", stack_base); + _alert("stack_size: %04x\n", stack_size); + _alert("sp: %04x\n", sp); if (sp >= stack_base || sp < stack_base - stack_size) { - alert("ERROR: Stack pointer is not within allocated stack\n"); + _alert("ERROR: Stack pointer is not within allocated stack\n"); return; } else @@ -84,7 +84,7 @@ static void up_stackdump(void) for (stack = sp & ~0x0f; stack < stack_base; stack += 8*sizeof(uint16_t)) { uint16_t *ptr = (uint16_t*)stack; - alert("%04x: %04x %04x %04x %04x %04x %04x %04x %04x\n", + _alert("%04x: %04x %04x %04x %04x %04x %04x %04x %04x\n", stack, ptr[0], ptr[1], ptr[2], ptr[3], ptr[4], ptr[5], ptr[6], ptr[7]); } diff --git a/arch/z80/src/ez80/ez80_registerdump.c b/arch/z80/src/ez80/ez80_registerdump.c index 43faf25fee..7257627a81 100644 --- a/arch/z80/src/ez80/ez80_registerdump.c +++ b/arch/z80/src/ez80/ez80_registerdump.c @@ -70,22 +70,22 @@ static void ez80_registerdump(void) if (g_current_regs) { #ifdef CONFIG_EZ80_Z80MODE - alert("AF: %04x I: %04x\n", + _alert("AF: %04x I: %04x\n", g_current_regs[XCPT_AF], g_current_regs[XCPT_I]); - alert("BC: %04x DE: %04x HL: %04x\n", + _alert("BC: %04x DE: %04x HL: %04x\n", g_current_regs[XCPT_BC], g_current_regs[XCPT_DE], g_current_regs[XCPT_HL]); - alert("IX: %04x IY: %04x\n", + _alert("IX: %04x IY: %04x\n", g_current_regs[XCPT_IX], g_current_regs[XCPT_IY]); - alert("SP: %04x PC: %04x\n" + _alert("SP: %04x PC: %04x\n" g_current_regs[XCPT_SP], g_current_regs[XCPT_PC]); #else - alert("AF: %06x I: %06x\n", + _alert("AF: %06x I: %06x\n", g_current_regs[XCPT_AF], g_current_regs[XCPT_I]); - alert("BC: %06x DE: %06x HL: %06x\n", + _alert("BC: %06x DE: %06x HL: %06x\n", g_current_regs[XCPT_BC], g_current_regs[XCPT_DE], g_current_regs[XCPT_HL]); - alert("IX: %06x IY: %06x\n", + _alert("IX: %06x IY: %06x\n", g_current_regs[XCPT_IX], g_current_regs[XCPT_IY]); - alert("SP: %06x PC: %06x\n" + _alert("SP: %06x PC: %06x\n" g_current_regs[XCPT_SP], g_current_regs[XCPT_PC]); #endif } diff --git a/arch/z80/src/z180/z180_registerdump.c b/arch/z80/src/z180/z180_registerdump.c index 32b351c36d..00be16de85 100644 --- a/arch/z80/src/z180/z180_registerdump.c +++ b/arch/z80/src/z180/z180_registerdump.c @@ -61,15 +61,15 @@ static void z180_registerdump(void) { if (g_current_regs) { - alert("AF: %04x I: %04x\n", + _alert("AF: %04x I: %04x\n", g_current_regs[XCPT_AF], g_current_regs[XCPT_I]); - alert("BC: %04x DE: %04x HL: %04x\n", + _alert("BC: %04x DE: %04x HL: %04x\n", g_current_regs[XCPT_BC], g_current_regs[XCPT_DE], g_current_regs[XCPT_HL]); - alert("IX: %04x IY: %04x\n", + _alert("IX: %04x IY: %04x\n", g_current_regs[XCPT_IX], g_current_regs[XCPT_IY]); - alert("SP: %04x PC: %04x\n" + _alert("SP: %04x PC: %04x\n" g_current_regs[XCPT_SP], g_current_regs[XCPT_PC]); - alert("CBAR: %02x BBR: %02x CBR: %02x\n" + _alert("CBAR: %02x BBR: %02x CBR: %02x\n" inp(Z180_MMU_CBAR), inp(Z180_MMU_BBR), inp(Z180_MMU_CBR)); } } diff --git a/arch/z80/src/z8/z8_registerdump.c b/arch/z80/src/z8/z8_registerdump.c index 92ba675b40..0b0cdc6c2e 100644 --- a/arch/z80/src/z8/z8_registerdump.c +++ b/arch/z80/src/z8/z8_registerdump.c @@ -56,7 +56,7 @@ static inline void z8_dumpregs(FAR chipret_t *regs) { - alert("REGS: %04x %04x %04x %04x %04x %04x %04x %04x\n", + _alert("REGS: %04x %04x %04x %04x %04x %04x %04x %04x\n", regs[XCPT_RR0], regs[XCPT_RR2], regs[XCPT_RR4], regs[XCPT_RR6], regs[XCPT_RR8], regs[XCPT_RR10], regs[XCPT_RR12], regs[XCPT_RR14]); } @@ -64,7 +64,7 @@ static inline void z8_dumpregs(FAR chipret_t *regs) static inline void z8_dumpstate(chipreg_t sp, chipreg_t pc, uint8_t irqctl, chipreg_t rpflags) { - alert("SP: %04x PC: %04x IRQCTL: %02x RP: %02x FLAGS: %02x\n", + _alert("SP: %04x PC: %04x IRQCTL: %02x RP: %02x FLAGS: %02x\n", sp, pc, irqctl & 0xff, rpflags >> 8, rpflags & 0xff); } diff --git a/arch/z80/src/z80/z80_registerdump.c b/arch/z80/src/z80/z80_registerdump.c index 7f02662a06..9d87ccc9c0 100644 --- a/arch/z80/src/z80/z80_registerdump.c +++ b/arch/z80/src/z80/z80_registerdump.c @@ -61,13 +61,13 @@ static void z80_registerdump(void) { if (g_current_regs) { - alert("AF: %04x I: %04x\n", + _alert("AF: %04x I: %04x\n", g_current_regs[XCPT_AF], g_current_regs[XCPT_I]); - alert("BC: %04x DE: %04x HL: %04x\n", + _alert("BC: %04x DE: %04x HL: %04x\n", g_current_regs[XCPT_BC], g_current_regs[XCPT_DE], g_current_regs[XCPT_HL]); - alert("IX: %04x IY: %04x\n", + _alert("IX: %04x IY: %04x\n", g_current_regs[XCPT_IX], g_current_regs[XCPT_IY]); - alert("SP: %04x PC: %04x\n" + _alert("SP: %04x PC: %04x\n" g_current_regs[XCPT_SP], g_current_regs[XCPT_PC]); } } diff --git a/include/debug.h b/include/debug.h index 7251839ea6..9994b3a421 100644 --- a/include/debug.h +++ b/include/debug.h @@ -106,7 +106,7 @@ * information that you probably not want to suppress during normal debug * general debugging. * - * alert() - is a special, high-priority, unconditional version that is really + * _alert() - is a special, high-priority, unconditional version that is really * intended only for crash error reporting. */ @@ -138,10 +138,10 @@ #endif #ifdef CONFIG_ARCH_LOWPUTC -# define alert(format, ...) \ +# define _alert(format, ...) \ __arch_lowsyslog(LOG_EMERG, EXTRA_FMT format EXTRA_ARG, ##__VA_ARGS__) # else -# define alert(x...) +# define _alert(x...) # endif #ifdef CONFIG_DEBUG_ERROR @@ -892,7 +892,7 @@ /* Variadic macros NOT supported */ #ifndef CONFIG_ARCH_LOWPUTC -# define alert (void) +# define _alert (void) # endif #ifdef CONFIG_DEBUG_ERROR @@ -1895,7 +1895,7 @@ void lib_dumpbuffer(FAR const char *msg, FAR const uint8_t *buffer, #ifndef CONFIG_CPP_HAVE_VARARGS #ifndef CONFIG_ARCH_LOWPUTC -int alert(const char *format, ...); +int _alert(const char *format, ...); #endif #ifdef CONFIG_DEBUG_ERROR From 6c1678d1d9a139e59d3f8e9eb521b33c2e53dc56 Mon Sep 17 00:00:00 2001 From: Gregory Nutt Date: Thu, 16 Jun 2016 12:35:57 -0600 Subject: [PATCH 11/75] STM32 Ethernet: Fix a bad cut and paster error from recent changes --- arch/arm/src/stm32/stm32_eth.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm/src/stm32/stm32_eth.c b/arch/arm/src/stm32/stm32_eth.c index df02c0a857..d4899c98c9 100644 --- a/arch/arm/src/stm32/stm32_eth.c +++ b/arch/arm/src/stm32/stm32_eth.c @@ -2042,7 +2042,7 @@ static inline void stm32_interrupt_process(FAR struct stm32_ethmac_s *priv) { /* Just let the user know what happened */ - nllninfoAbormal event(s): %08x\n", dmasr); + nllnerr("ERROR: Abormal event(s): %08x\n", dmasr); /* Clear all pending abnormal events */ @@ -2246,7 +2246,7 @@ static void stm32_txtimeout_expiry(int argc, uint32_t arg, ...) { FAR struct stm32_ethmac_s *priv = (FAR struct stm32_ethmac_s *)arg; - nllninfoTimeout!\n"); + nllnerr("ERROR: Timeout!\n"); #ifdef CONFIG_NET_NOINTS /* Disable further Ethernet interrupts. This will prevent some race From bf0a3bf0c86ca1f55260638d9cdd82571d009adb Mon Sep 17 00:00:00 2001 From: Gregory Nutt Date: Thu, 16 Jun 2016 12:43:35 -0600 Subject: [PATCH 12/75] Fix error in recent LSE-related fix: Requires CONFIG_STM32_PWR, or will not build correctly --- arch/arm/src/stm32/stm32_rcc.c | 70 ++++++++++++++++++++++++---------- 1 file changed, 49 insertions(+), 21 deletions(-) diff --git a/arch/arm/src/stm32/stm32_rcc.c b/arch/arm/src/stm32/stm32_rcc.c index 87afb59d3a..5fd2ffb8c7 100644 --- a/arch/arm/src/stm32/stm32_rcc.c +++ b/arch/arm/src/stm32/stm32_rcc.c @@ -101,6 +101,53 @@ # define RCC_XXX_YYYRST RCC_BDCR_BDRST #endif +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/************************************************************************************ + * Name: rcc_enablebkp + * + * Description: + * The RTC needs to reset the Backup Domain to change RTCSEL and resetting the + * Backup Domain renders to disabling the LSE as consequence. In order to avoid + * resetting the Backup Domain when we already configured LSE we will reset the + * Backup Domain early (here). + * + * Input Parameters: + * None + * + * Returned Value: + * None + * + ************************************************************************************/ + +#ifdef CONFIG_STM32_PWR +static inline rcc_enablebkp(void) +{ + uint32_t regval; + + /* Check if the RTC is already configured */ + + regval = getreg32(RTC_MAGIC_REG); + if (regval != RTC_MAGIC) + { + (void)stm32_pwr_enablebkp(true); + + /* We might be changing RTCSEL - to ensure such changes work, we must + * reset the backup domain (having backed up the RTC_MAGIC token) + */ + + modifyreg32(STM32_RCC_XXX, 0, RCC_XXX_YYYRST); + modifyreg32(STM32_RCC_XXX, RCC_XXX_YYYRST, 0); + + (void)stm32_pwr_enablebkp(false); + } +} +#else +# define rcc_enablebkp() +#endif + /**************************************************************************** * Public Functions ****************************************************************************/ @@ -134,28 +181,9 @@ void stm32_clockconfig(void) rcc_reset(); - /* The RTC needs to reset the Backup Domain to change RTCSEL and resetting the - * Backup Domain renders to disabling the LSE as consequence. In order to avoid - * resetting the Backup Domain when we already configured LSE we will reset the - * Backup Domain early (here). - */ + /* Reset backup domain */ - /* Check if the RTC is already configured */ - - regval = getreg32(RTC_MAGIC_REG); - if (regval != RTC_MAGIC) - { - (void)stm32_pwr_enablebkp(true); - - /* We might be changing RTCSEL - to ensure such changes work, we must - * reset the backup domain (having backed up the RTC_MAGIC token) - */ - - modifyreg32(STM32_RCC_XXX, 0, RCC_XXX_YYYRST); - modifyreg32(STM32_RCC_XXX, RCC_XXX_YYYRST, 0); - - (void)stm32_pwr_enablebkp(false); - } + rcc_enablebkp(); #if defined(CONFIG_ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG) From e60ced183512115ea6539a3c223354e9fdbcc00c Mon Sep 17 00:00:00 2001 From: Gregory Nutt Date: Thu, 16 Jun 2016 12:51:21 -0600 Subject: [PATCH 13/75] Update last change... STM32 does not have STM32_RTC_BKR register. --- arch/arm/src/stm32/stm32_rcc.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/src/stm32/stm32_rcc.c b/arch/arm/src/stm32/stm32_rcc.c index 5fd2ffb8c7..5196dafa51 100644 --- a/arch/arm/src/stm32/stm32_rcc.c +++ b/arch/arm/src/stm32/stm32_rcc.c @@ -122,7 +122,7 @@ * ************************************************************************************/ -#ifdef CONFIG_STM32_PWR +#if defined(CONFIG_STM32_PWR) && !defined(CONFIG_STM32_STM32F10XX) static inline rcc_enablebkp(void) { uint32_t regval; From 53ec3ca1a2ab34f24dfe5a1fefef4f50b91d463a Mon Sep 17 00:00:00 2001 From: Gregory Nutt Date: Thu, 16 Jun 2016 13:18:59 -0600 Subject: [PATCH 14/75] Fix a cut-and-paste error: uusbinfo->usbinfo --- arch/arm/src/stm32/stm32_usbdev.c | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/arch/arm/src/stm32/stm32_usbdev.c b/arch/arm/src/stm32/stm32_usbdev.c index ec8be78bcc..3e918e00e7 100644 --- a/arch/arm/src/stm32/stm32_usbdev.c +++ b/arch/arm/src/stm32/stm32_usbdev.c @@ -2845,7 +2845,7 @@ static int stm32_epconfigure(struct usbdev_ep_s *ep, if (!ep || !desc) { usbtrace(TRACE_DEVERROR(STM32_TRACEERR_INVALIDPARMS), 0); - uusbinfo("ERROR: ep=%p desc=%p\n"); + usberr("ERROR: ep=%p desc=%p\n"); return -EINVAL; } #endif @@ -2941,7 +2941,7 @@ static int stm32_epdisable(struct usbdev_ep_s *ep) if (!ep) { usbtrace(TRACE_DEVERROR(STM32_TRACEERR_INVALIDPARMS), 0); - uusbinfo("ERROR: ep=%p\n", ep); + usberr("ERROR: ep=%p\n", ep); return -EINVAL; } #endif @@ -3029,7 +3029,7 @@ static int stm32_epsubmit(struct usbdev_ep_s *ep, struct usbdev_req_s *req) if (!req || !req->callback || !req->buf || !ep) { usbtrace(TRACE_DEVERROR(STM32_TRACEERR_INVALIDPARMS), 0); - uusbinfo("ERROR: req=%p callback=%p buf=%p ep=%p\n", req, req->callback, req->buf, ep); + usberr("ERROR: req=%p callback=%p buf=%p ep=%p\n", req, req->callback, req->buf, ep); return -EINVAL; } #endif @@ -3041,7 +3041,7 @@ static int stm32_epsubmit(struct usbdev_ep_s *ep, struct usbdev_req_s *req) if (!priv->driver) { usbtrace(TRACE_DEVERROR(STM32_TRACEERR_NOTCONFIGURED), priv->usbdev.speed); - uusbinfo("ERROR: driver=%p\n", priv->driver); + usberr("ERROR: driver=%p\n", priv->driver); return -ESHUTDOWN; } #endif @@ -3058,7 +3058,7 @@ static int stm32_epsubmit(struct usbdev_ep_s *ep, struct usbdev_req_s *req) if (privep->stalled) { stm32_abortrequest(privep, privreq, -EBUSY); - uusbinfo("ERROR: stalled\n"); + usberr("ERROR: stalled\n"); ret = -EBUSY; } From 865150f666a2627e98a54b7d4f06205b19dc7113 Mon Sep 17 00:00:00 2001 From: Gregory Nutt Date: Thu, 16 Jun 2016 13:36:50 -0600 Subject: [PATCH 15/75] STM32: Logic to reset backup domain only applies if the RTC is enabled. --- arch/arm/src/stm32/stm32_rcc.c | 16 ++++++---------- 1 file changed, 6 insertions(+), 10 deletions(-) diff --git a/arch/arm/src/stm32/stm32_rcc.c b/arch/arm/src/stm32/stm32_rcc.c index 5196dafa51..80e87fb37a 100644 --- a/arch/arm/src/stm32/stm32_rcc.c +++ b/arch/arm/src/stm32/stm32_rcc.c @@ -67,10 +67,6 @@ #define HSERDY_TIMEOUT (100 * CONFIG_BOARD_LOOPSPERMSEC) -/**************************************************************************** - * Private Data - ****************************************************************************/ - /**************************************************************************** * Private Functions ****************************************************************************/ @@ -106,7 +102,7 @@ ****************************************************************************/ /************************************************************************************ - * Name: rcc_enablebkp + * Name: rcc_resetbkp * * Description: * The RTC needs to reset the Backup Domain to change RTCSEL and resetting the @@ -122,8 +118,8 @@ * ************************************************************************************/ -#if defined(CONFIG_STM32_PWR) && !defined(CONFIG_STM32_STM32F10XX) -static inline rcc_enablebkp(void) +#if defined(CONFIG_RTC) && defined(CONFIG_STM32_PWR) && !defined(CONFIG_STM32_STM32F10XX) +static inline rcc_resetbkp(void) { uint32_t regval; @@ -145,7 +141,7 @@ static inline rcc_enablebkp(void) } } #else -# define rcc_enablebkp() +# define rcc_resetbkp() #endif /**************************************************************************** @@ -181,9 +177,9 @@ void stm32_clockconfig(void) rcc_reset(); - /* Reset backup domain */ + /* Reset backup domain if appropriate */ - rcc_enablebkp(); + rcc_resetbkp(); #if defined(CONFIG_ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG) From dd7297fb64eb94fe06a89fd9e8656f499cd8cc15 Mon Sep 17 00:00:00 2001 From: Alan Carvalho de Assis Date: Thu, 16 Jun 2016 13:43:09 -0600 Subject: [PATCH 16/75] STM32L4: Add logic reset backup domain early in initialization --- arch/arm/src/stm32l4/stm32l4_rcc.c | 53 ++++++++++++++++++++++++++++- arch/arm/src/stm32l4/stm32l4_rtc.h | 20 +++++++++++ arch/arm/src/stm32l4/stm32l4_rtcc.c | 9 +---- 3 files changed, 73 insertions(+), 9 deletions(-) diff --git a/arch/arm/src/stm32l4/stm32l4_rcc.c b/arch/arm/src/stm32l4/stm32l4_rcc.c index 0d51d7afd1..202b90176f 100644 --- a/arch/arm/src/stm32l4/stm32l4_rcc.c +++ b/arch/arm/src/stm32l4/stm32l4_rcc.c @@ -89,7 +89,58 @@ ****************************************************************************/ /************************************************************************************ - * Name: stm32l4_clockconfig + * Name: rcc_resetbkp + * + * Description: + * The RTC needs to reset the Backup Domain to change RTCSEL and resetting the + * Backup Domain renders to disabling the LSE as consequence. In order to avoid + * resetting the Backup Domain when we already configured LSE we will reset the + * Backup Domain early (here). + * + * Input Parameters: + * None + * + * Returned Value: + * None + * + ************************************************************************************/ + +#if defined(CONFIG_STM32_PWR) && defined(CONFIG_RTC) +static inline rcc_resetbkp(void) +{ + bool init_stat; + + /* Check if the RTC is already configured */ + + init_stat = rtc_is_inits(); + if(!init_stat) + { + /* Enable write access to the backup domain (RTC registers, RTC + * backup data registers and backup SRAM). + */ + + (void)stm32l4_pwr_enablebkp(true); + + /* We might be changing RTCSEL - to ensure such changes work, we must + * reset the backup domain (having backed up the RTC_MAGIC token) + */ + + modifyreg32(STM32L4_RCC_BDCR, 0, RCC_BDCR_BDRST); + modifyreg32(STM32L4_RCC_BDCR, RCC_BDCR_BDRST, 0); + + (void)stm32l4_pwr_enablebkp(false); + } +} +#else +# define rcc_resetbkp() +#endif + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/************************************************************************************ + * Name: stm32_clockconfig * * Description: * Called to establish the clock settings based on the values in board.h. This diff --git a/arch/arm/src/stm32l4/stm32l4_rtc.h b/arch/arm/src/stm32l4/stm32l4_rtc.h index b155bef8b0..222f5bc7c0 100644 --- a/arch/arm/src/stm32l4/stm32l4_rtc.h +++ b/arch/arm/src/stm32l4/stm32l4_rtc.h @@ -105,6 +105,26 @@ extern "C" * Public Functions ****************************************************************************/ +/************************************************************************************ + * Name: rtc_is_inits + * + * Description: + * Returns 'true' if the RTC has been initialized (according to the RTC itself). + * It will be 'false' if the RTC has never been initialized since first time power + * up, and the counters are stopped until it is first initialized. + * + * Input Parameters: + * None + * + * Returned Value: + * bool -- true if the INITS flag is set in the ISR. + * + ************************************************************************************/ +#ifdef CONFIG_RTC_DRIVER +bool rtc_is_inits(void); +#endif + + /**************************************************************************** * Name: stm32l4_rtc_getdatetime_with_subseconds * diff --git a/arch/arm/src/stm32l4/stm32l4_rtcc.c b/arch/arm/src/stm32l4/stm32l4_rtcc.c index c894fb54d8..830425e1a7 100644 --- a/arch/arm/src/stm32l4/stm32l4_rtcc.c +++ b/arch/arm/src/stm32l4/stm32l4_rtcc.c @@ -250,7 +250,7 @@ static void rtc_dumptime(FAR const struct tm *tp, FAR const char *msg) * ************************************************************************************/ -static bool rtc_is_inits(void) +bool rtc_is_inits(void) { uint32_t regval; @@ -832,13 +832,6 @@ int up_rtc_initialize(void) (void)stm32l4_pwr_enablebkp(true); -#if 0 - /* Do not reset the backup domain; you will lose your clock setup done in *rcc.c */ - - modifyreg32(STM32L4_RCC_BDCR, 0, RCC_BDCR_BDRST); - modifyreg32(STM32L4_RCC_BDCR, RCC_BDCR_BDRST, 0); -#endif - #if defined(CONFIG_STM32L4_RTC_HSECLOCK) modifyreg32(STM32L4_RCC_BDCR, RCC_BDCR_RTCSEL_MASK, RCC_BDCR_RTCSEL_HSE); #elif defined(CONFIG_STM32L4_RTC_LSICLOCK) From ae134712449af5d7b88c2ad2203ba73dc370d28a Mon Sep 17 00:00:00 2001 From: Gregory Nutt Date: Thu, 16 Jun 2016 13:36:04 -0600 Subject: [PATCH 17/75] One more time. Correct name of USB debug macros are uinfo and uerr, not usbinfo and usberr. --- arch/arm/src/stm32/stm32_otgfsdev.c | 8 ++--- arch/arm/src/stm32/stm32_otgfshost.c | 4 +-- arch/arm/src/stm32/stm32_otghsdev.c | 8 ++--- arch/arm/src/stm32/stm32_otghshost.c | 4 +-- arch/arm/src/stm32/stm32_usbdev.c | 44 ++++++++++++++-------------- 5 files changed, 34 insertions(+), 34 deletions(-) diff --git a/arch/arm/src/stm32/stm32_otgfsdev.c b/arch/arm/src/stm32/stm32_otgfsdev.c index 2d7912ac7b..693da846b2 100644 --- a/arch/arm/src/stm32/stm32_otgfsdev.c +++ b/arch/arm/src/stm32/stm32_otgfsdev.c @@ -817,7 +817,7 @@ static uint32_t stm32_getreg(uint32_t addr) { if (count == 4) { - usbinfo("...\n"); + uinfo("...\n"); } return val; @@ -834,7 +834,7 @@ static uint32_t stm32_getreg(uint32_t addr) { /* Yes.. then show how many times the value repeated */ - usbinfo("[repeats %d more times]\n", count-3); + uinfo("[repeats %d more times]\n", count-3); } /* Save the new address, value, and count */ @@ -846,7 +846,7 @@ static uint32_t stm32_getreg(uint32_t addr) /* Show the register value read */ - usbinfo("%08x->%08x\n", addr, val); + uinfo("%08x->%08x\n", addr, val); return val; } #endif @@ -864,7 +864,7 @@ static void stm32_putreg(uint32_t val, uint32_t addr) { /* Show the register value being written */ - usbinfo("%08x<-%08x\n", addr, val); + uinfo("%08x<-%08x\n", addr, val); /* Write the value */ diff --git a/arch/arm/src/stm32/stm32_otgfshost.c b/arch/arm/src/stm32/stm32_otgfshost.c index 632ba36287..ba5b76f124 100644 --- a/arch/arm/src/stm32/stm32_otgfshost.c +++ b/arch/arm/src/stm32/stm32_otgfshost.c @@ -506,7 +506,7 @@ static struct usbhost_connection_s g_usbconn = #ifdef CONFIG_STM32_USBHOST_REGDEBUG static void stm32_printreg(uint32_t addr, uint32_t val, bool iswrite) { - usbinfo("%08x%s%08x\n", addr, iswrite ? "<-" : "->", val); + uinfo("%08x%s%08x\n", addr, iswrite ? "<-" : "->", val); } #endif @@ -556,7 +556,7 @@ static void stm32_checkreg(uint32_t addr, uint32_t val, bool iswrite) { /* No.. More than one. */ - usbinfo("[repeats %d more times]\n", count); + uinfo("[repeats %d more times]\n", count); } } diff --git a/arch/arm/src/stm32/stm32_otghsdev.c b/arch/arm/src/stm32/stm32_otghsdev.c index c8d146373a..daa9fc3c36 100644 --- a/arch/arm/src/stm32/stm32_otghsdev.c +++ b/arch/arm/src/stm32/stm32_otghsdev.c @@ -817,7 +817,7 @@ static uint32_t stm32_getreg(uint32_t addr) { if (count == 4) { - usbinfo("...\n"); + uinfo("...\n"); } return val; @@ -834,7 +834,7 @@ static uint32_t stm32_getreg(uint32_t addr) { /* Yes.. then show how many times the value repeated */ - usbinfo("[repeats %d more times]\n", count-3); + uinfo("[repeats %d more times]\n", count-3); } /* Save the new address, value, and count */ @@ -846,7 +846,7 @@ static uint32_t stm32_getreg(uint32_t addr) /* Show the register value read */ - usbinfo("%08x->%08x\n", addr, val); + uinfo("%08x->%08x\n", addr, val); return val; } #endif @@ -864,7 +864,7 @@ static void stm32_putreg(uint32_t val, uint32_t addr) { /* Show the register value being written */ - usbinfo("%08x<-%08x\n", addr, val); + uinfo("%08x<-%08x\n", addr, val); /* Write the value */ diff --git a/arch/arm/src/stm32/stm32_otghshost.c b/arch/arm/src/stm32/stm32_otghshost.c index 42a68f6533..4ac58385c1 100644 --- a/arch/arm/src/stm32/stm32_otghshost.c +++ b/arch/arm/src/stm32/stm32_otghshost.c @@ -506,7 +506,7 @@ static struct usbhost_connection_s g_usbconn = #ifdef CONFIG_STM32_USBHOST_REGDEBUG static void stm32_printreg(uint32_t addr, uint32_t val, bool iswrite) { - usbinfo("%08x%s%08x\n", addr, iswrite ? "<-" : "->", val); + uinfo("%08x%s%08x\n", addr, iswrite ? "<-" : "->", val); } #endif @@ -556,7 +556,7 @@ static void stm32_checkreg(uint32_t addr, uint32_t val, bool iswrite) { /* No.. More than one. */ - usbinfo("[repeats %d more times]\n", count); + uinfo("[repeats %d more times]\n", count); } } diff --git a/arch/arm/src/stm32/stm32_usbdev.c b/arch/arm/src/stm32/stm32_usbdev.c index 3e918e00e7..1d69a4d175 100644 --- a/arch/arm/src/stm32/stm32_usbdev.c +++ b/arch/arm/src/stm32/stm32_usbdev.c @@ -674,7 +674,7 @@ static uint16_t stm32_getreg(uint32_t addr) { if (count == 4) { - usbinfo("...\n"); + uinfo("...\n"); } return val; } @@ -690,7 +690,7 @@ static uint16_t stm32_getreg(uint32_t addr) { /* Yes.. then show how many times the value repeated */ - usbinfo("[repeats %d more times]\n", count-3); + uinfo("[repeats %d more times]\n", count-3); } /* Save the new address, value, and count */ @@ -702,7 +702,7 @@ static uint16_t stm32_getreg(uint32_t addr) /* Show the register value read */ - usbinfo("%08x->%04x\n", addr, val); + uinfo("%08x->%04x\n", addr, val); return val; } #endif @@ -716,7 +716,7 @@ static void stm32_putreg(uint16_t val, uint32_t addr) { /* Show the register value being written */ - usbinfo("%08x<-%04x\n", addr, val); + uinfo("%08x<-%04x\n", addr, val); /* Write the value */ @@ -735,35 +735,35 @@ static void stm32_dumpep(int epno) /* Common registers */ - usbinfo("CNTR: %04x\n", getreg16(STM32_USB_CNTR)); - usbinfo("ISTR: %04x\n", getreg16(STM32_USB_ISTR)); - usbinfo("FNR: %04x\n", getreg16(STM32_USB_FNR)); - usbinfo("DADDR: %04x\n", getreg16(STM32_USB_DADDR)); - usbinfo("BTABLE: %04x\n", getreg16(STM32_USB_BTABLE)); + uinfo("CNTR: %04x\n", getreg16(STM32_USB_CNTR)); + uinfo("ISTR: %04x\n", getreg16(STM32_USB_ISTR)); + uinfo("FNR: %04x\n", getreg16(STM32_USB_FNR)); + uinfo("DADDR: %04x\n", getreg16(STM32_USB_DADDR)); + uinfo("BTABLE: %04x\n", getreg16(STM32_USB_BTABLE)); /* Endpoint register */ addr = STM32_USB_EPR(epno); - usbinfo("EPR%d: [%08x] %04x\n", epno, addr, getreg16(addr)); + uinfo("EPR%d: [%08x] %04x\n", epno, addr, getreg16(addr)); /* Endpoint descriptor */ addr = STM32_USB_BTABLE_ADDR(epno, 0); - usbinfo("DESC: %08x\n", addr); + uinfo("DESC: %08x\n", addr); /* Endpoint buffer descriptor */ addr = STM32_USB_ADDR_TX(epno); - usbinfo(" TX ADDR: [%08x] %04x\n", addr, getreg16(addr)); + uinfo(" TX ADDR: [%08x] %04x\n", addr, getreg16(addr)); addr = STM32_USB_COUNT_TX(epno); - usbinfo(" COUNT: [%08x] %04x\n", addr, getreg16(addr)); + uinfo(" COUNT: [%08x] %04x\n", addr, getreg16(addr)); addr = STM32_USB_ADDR_RX(epno); - usbinfo(" RX ADDR: [%08x] %04x\n", addr, getreg16(addr)); + uinfo(" RX ADDR: [%08x] %04x\n", addr, getreg16(addr)); addr = STM32_USB_COUNT_RX(epno); - usbinfo(" COUNT: [%08x] %04x\n", addr, getreg16(addr)); + uinfo(" COUNT: [%08x] %04x\n", addr, getreg16(addr)); } #endif @@ -778,12 +778,12 @@ static void stm32_checksetup(void) uint32_t apb1rstr = getreg32(STM32_RCC_APB1RSTR); uint32_t apb1enr = getreg32(STM32_RCC_APB1ENR); - usbinfo("CFGR: %08x APB1RSTR: %08x APB1ENR: %08x\n", cfgr, apb1rstr, apb1enr); + uinfo("CFGR: %08x APB1RSTR: %08x APB1ENR: %08x\n", cfgr, apb1rstr, apb1enr); if ((apb1rstr & RCC_APB1RSTR_USBRST) != 0 || (apb1enr & RCC_APB1ENR_USBEN) == 0) { - usbinfo("ERROR: USB is NOT setup correctly\n"); + uinfo("ERROR: USB is NOT setup correctly\n"); } } #endif @@ -2845,7 +2845,7 @@ static int stm32_epconfigure(struct usbdev_ep_s *ep, if (!ep || !desc) { usbtrace(TRACE_DEVERROR(STM32_TRACEERR_INVALIDPARMS), 0); - usberr("ERROR: ep=%p desc=%p\n"); + uerr("ERROR: ep=%p desc=%p\n"); return -EINVAL; } #endif @@ -2941,7 +2941,7 @@ static int stm32_epdisable(struct usbdev_ep_s *ep) if (!ep) { usbtrace(TRACE_DEVERROR(STM32_TRACEERR_INVALIDPARMS), 0); - usberr("ERROR: ep=%p\n", ep); + uerr("ERROR: ep=%p\n", ep); return -EINVAL; } #endif @@ -3029,7 +3029,7 @@ static int stm32_epsubmit(struct usbdev_ep_s *ep, struct usbdev_req_s *req) if (!req || !req->callback || !req->buf || !ep) { usbtrace(TRACE_DEVERROR(STM32_TRACEERR_INVALIDPARMS), 0); - usberr("ERROR: req=%p callback=%p buf=%p ep=%p\n", req, req->callback, req->buf, ep); + uerr("ERROR: req=%p callback=%p buf=%p ep=%p\n", req, req->callback, req->buf, ep); return -EINVAL; } #endif @@ -3041,7 +3041,7 @@ static int stm32_epsubmit(struct usbdev_ep_s *ep, struct usbdev_req_s *req) if (!priv->driver) { usbtrace(TRACE_DEVERROR(STM32_TRACEERR_NOTCONFIGURED), priv->usbdev.speed); - usberr("ERROR: driver=%p\n", priv->driver); + uerr("ERROR: driver=%p\n", priv->driver); return -ESHUTDOWN; } #endif @@ -3058,7 +3058,7 @@ static int stm32_epsubmit(struct usbdev_ep_s *ep, struct usbdev_req_s *req) if (privep->stalled) { stm32_abortrequest(privep, privreq, -EBUSY); - usberr("ERROR: stalled\n"); + uerr("ERROR: stalled\n"); ret = -EBUSY; } From 801d661423c1dec43801f802ed53eb3a1f5eb21f Mon Sep 17 00:00:00 2001 From: Gregory Nutt Date: Thu, 16 Jun 2016 15:10:08 -0600 Subject: [PATCH 18/75] Change *err() to either info() or err(ERROR:..), depending upon if an error has occurred. --- arch/arm/src/sam34/sam_rtc.c | 2 +- arch/arm/src/sama5/Kconfig | 53 ++++++----- arch/arm/src/sama5/sam_adc.c | 12 ++- arch/arm/src/sama5/sam_allocateheap.c | 36 ++++---- arch/arm/src/sama5/sam_can.c | 70 +++++++------- arch/arm/src/sama5/sam_dmac.c | 44 ++++----- arch/arm/src/sama5/sam_ehci.c | 54 +++++------ arch/arm/src/sama5/sam_emaca.c | 28 +++--- arch/arm/src/sama5/sam_emacb.c | 34 +++---- arch/arm/src/sama5/sam_gmac.c | 26 +++--- arch/arm/src/sama5/sam_hsmci.c | 68 +++++++------- arch/arm/src/sama5/sam_lcd.c | 82 ++++++++--------- arch/arm/src/sama5/sam_memories.c | 6 +- arch/arm/src/sama5/sam_nand.c | 8 +- arch/arm/src/sama5/sam_nand.h | 9 +- arch/arm/src/sama5/sam_ohci.c | 10 +- arch/arm/src/sama5/sam_pmecc.c | 6 +- arch/arm/src/sama5/sam_pwm.c | 19 ++-- arch/arm/src/sama5/sam_rtc.c | 2 +- arch/arm/src/sama5/sam_spi.c | 12 ++- arch/arm/src/sama5/sam_ssc.c | 10 +- arch/arm/src/sama5/sam_tc.c | 26 +++--- arch/arm/src/sama5/sam_tsd.c | 4 +- arch/arm/src/sama5/sam_twi.c | 10 +- arch/arm/src/sama5/sam_udphs.c | 42 ++++----- arch/arm/src/sama5/sam_wdt.c | 21 +++-- arch/arm/src/sama5/sam_xdmac.c | 58 ++++++------ arch/arm/src/samdl/Kconfig | 2 +- arch/arm/src/samdl/sam_dmac.c | 36 ++++---- arch/arm/src/samdl/sam_dmac.h | 12 +-- arch/arm/src/samdl/sam_port.c | 32 +++---- arch/arm/src/samdl/sam_spi.c | 22 +++-- arch/arm/src/samv7/Kconfig | 34 +++---- arch/arm/src/samv7/sam_emac.c | 42 ++++----- arch/arm/src/samv7/sam_hsmci.c | 94 ++++++++++--------- arch/arm/src/samv7/sam_mcan.c | 128 +++++++++++++------------- arch/arm/src/samv7/sam_qspi.c | 10 +- arch/arm/src/samv7/sam_rswdt.c | 21 +++-- arch/arm/src/samv7/sam_spi.c | 16 +++- arch/arm/src/samv7/sam_spi_slave.c | 14 ++- arch/arm/src/samv7/sam_ssc.c | 14 ++- arch/arm/src/samv7/sam_tc.c | 40 ++++---- arch/arm/src/samv7/sam_twihs.c | 10 +- arch/arm/src/samv7/sam_usbdevhs.c | 55 +++++------ arch/arm/src/samv7/sam_wdt.c | 21 +++-- arch/arm/src/samv7/sam_xdmac.c | 54 +++++------ arch/arm/src/samv7/sam_xdmac.h | 14 +-- 47 files changed, 735 insertions(+), 688 deletions(-) diff --git a/arch/arm/src/sam34/sam_rtc.c b/arch/arm/src/sam34/sam_rtc.c index 540fe3e44f..6c261ce415 100644 --- a/arch/arm/src/sam34/sam_rtc.c +++ b/arch/arm/src/sam34/sam_rtc.c @@ -274,7 +274,7 @@ static int rtc_interrupt(int irq, void *context) ret = work_queue(LPWORK, &g_alarmwork, rtc_worker, NULL, 0); if (ret < 0) { - rtcllerr("ERRPR: work_queue failed: %d\n", ret); + rtcllerr("ERR0R: work_queue failed: %d\n", ret); } /* Disable any further alarm interrupts */ diff --git a/arch/arm/src/sama5/Kconfig b/arch/arm/src/sama5/Kconfig index c2850d67e4..4f7b2371db 100644 --- a/arch/arm/src/sama5/Kconfig +++ b/arch/arm/src/sama5/Kconfig @@ -1393,9 +1393,9 @@ endif # SAMA5_LCDC_HCR config SAMA5_LCDC_REGDEBUG bool "Register-Level Debug" default n - depends on DEBUG_FEATURES + depends on DEBUG_LCD_INFO ---help--- - Enable very low-level register access debug. Depends on CONFIG_DEBUG_FEATURES. + Enable very low-level register access debug. Depends on CONFIG_DEBUG_LCD_INFO. endmenu # LCDC configuration endif # SAMA5_LCDC @@ -1499,9 +1499,9 @@ endif # !SAMA5_GMAC_AUTONEG config SAMA5_GMAC_REGDEBUG bool "Register-Level Debug" default n - depends on DEBUG_FEATURES + depends on DEBUG_NET_INFO ---help--- - Enable very low-level register access debug. Depends on CONFIG_DEBUG_FEATURES. + Enable very low-level register access debug. Depends on CONFIG_DEBUG_NET_INFO. endmenu # GMAC device driver options endif # SAMA5_GMAC @@ -1678,9 +1678,9 @@ config SAMA5_EMACA_NBC config SAMA5_EMACA_REGDEBUG bool "Register-Level Debug" default n - depends on DEBUG_FEATURES + depends on DEBUG_NET_FEATURES ---help--- - Enable very low-level register access debug. Depends on CONFIG_DEBUG_FEATURES. + Enable very low-level register access debug. Depends on CONFIG_DEBUG_NET_FEATURES. endmenu # EMAC device driver options endif # SAMA5_EMACA @@ -2087,9 +2087,9 @@ config SAMA5_EMACB_DEBUG config SAMA5_EMACB_REGDEBUG bool "Register-Level Debug" default n - depends on DEBUG_FEATURES + depends on DEBUG_NET_INFO ---help--- - Enable very low-level register access debug. Depends on CONFIG_DEBUG_FEATURES. + Enable very low-level register access debug. Depends on CONFIG_DEBUG_NET_INFO. endmenu # EMAC device driver options endif # SAMA5_EMACB @@ -2364,11 +2364,11 @@ config SAMA5_SPI_DMADEBUG config SAMA5_SPI_REGDEBUG bool "SPI Register level debug" - depends on DEBUG_FEATURES + depends on DEBUG_SPI_INFO default n ---help--- Output detailed register-level SPI device debug information. - Requires also CONFIG_DEBUG_FEATURES. + Requires also CONFIG_DEBUG_SPI_INFO. endmenu # SPI device driver options endif # SAMA5_SPI0 || SAMA5_SPI1 @@ -2399,11 +2399,11 @@ config SAMA5_TWI3_FREQUENCY config SAMA5_TWI_REGDEBUG bool "TWI register level debug" - depends on DEBUG_FEATURES + depends on DEBUG_I2C_INFO default n ---help--- Output detailed register-level TWI device debug information. - Very invasive! Requires also CONFIG_DEBUG_FEATURES. + Very invasive! Requires also CONFIG_DEBUG_I2C_INFO. endmenu # TWI device driver options endif # SAMA5_TWI0 || SAMA5_TWI1 || SAMA5_TWI2 || SAMA5_TWI3 @@ -2776,11 +2776,11 @@ config SAMA5_SSC_DMADEBUG config SAMA5_SSC_REGDEBUG bool "SSC Register level debug" - depends on DEBUG_FEATURES + depends on DEBUG_I2S_INFO default n ---help--- Output detailed register-level SSC device debug information. - Very invasive! Requires also CONFIG_DEBUG_FEATURES. + Very invasive! Requires also CONFIG_DEBUG_I2S_INFO. config SAMA5_SSC_QDEBUG bool "SSC Queue debug" @@ -2881,11 +2881,11 @@ config SAMA5_HSMCI_CMDDEBUG config SAMA5_HSMCI_REGDEBUG bool "HSMCI Register level debug" - depends on DEBUG_FEATURES + depends on DEBUG_MEMCARD_INFO default n ---help--- Output detailed register-level HSCMI device debug information. - Very invasive! Requires also CONFIG_DEBUG_FEATURES. + Very invasive! Requires also CONFIG_DEBUG_MEMCARD_INFO. endmenu # HSMCI device driver options endif # SAMA5_HSMCI0 || SAMA5_HSMCI1 || SAMA5_HSMCI2 @@ -2920,7 +2920,7 @@ config SAMA5_UDPHS_PREALLOCATE config SAMA5_UDPHS_REGDEBUG bool "Enable low-level UDPHS register debug" default n - depends on DEBUG_FEATURES + depends on DEBUG_USB_INFO endmenu # USB High Speed Device Controller driver (DCD) options endif # SAMA5_UDPHS @@ -2960,7 +2960,7 @@ config SAMA5_OHCI_TDBUFSIZE config SAMA5_OHCI_REGDEBUG bool "Enable low-level OHCI register debug" default n - depends on DEBUG_FEATURES + depends on DEBUG_USB_INFO endif # SAMA5_OHCI @@ -3009,7 +3009,7 @@ config SAMA5_EHCI_PREALLOCATE config SAMA5_EHCI_REGDEBUG bool "Enable low-level EHCI register debug" default n - depends on DEBUG_FEATURES + depends on DEBUG_USB_INFO endif # SAMA5_EHCI @@ -3661,7 +3661,7 @@ endif # SAMA5_ADC_HAVE_CHAN config SAMA5_ADC_REGDEBUG bool "Enable register-level ADC/touchscreen debug" default n - depends on DEBUG_FEATURES + depends on DEBUG_ANALOG_INFO ---help--- Enable very low register-level debug output. @@ -3915,11 +3915,11 @@ config SAMA5_TC_DEBUG config SAMA5_TC_REGDEBUG bool "TC register level debug" - depends on DEBUG_FEATURES + depends on DEBUG_TIMER_INFO default n ---help--- Output detailed register-level Timer/Counter device debug - information. Very invasive! Requires also CONFIG_DEBUG_FEATURES. + information. Very invasive! Requires also CONFIG_DEBUG_TIMER_INFO. endmenu # Timer/counter Configuration endif # SAMA5_HAVE_TC @@ -4150,7 +4150,7 @@ endif # SAMA5_PWM_CHAN3 config SAMA5_PWM_REGDEBUG bool "Enable register-level PWM debug" default n - depends on DEBUG_FEATURES + depends on DEBUG_PWM_INFO ---help--- Enable very low register-level debug output. @@ -4185,7 +4185,7 @@ config SAMA5_WDT_IDLEHALT config SAMA5_WDT_REGDEBUG bool "Register level debug" default n - depends on DEBUG_FEATURES + depends on DEBUG_WATCHDOG_INFO ---help--- Enable low-level register debug output @@ -4699,10 +4699,9 @@ config SAMA5_NAND_DMADEBUG config SAMA5_NAND_REGDEBUG bool "Register-Level NAND Debug" default n - depends on DEBUG_FEATURES && DEBUG_FS + depends on DEBUG_FS_INFO ---help--- - Enable very low-level register access debug. Depends on CONFIG_DEBUG_FEATURES and - DEBUG_FS. + Enable very low-level register access debug. Depends on CONFIG_DEBUG_FS_INFO. config SAMA5_NAND_DUMP bool "NAND data dump" diff --git a/arch/arm/src/sama5/sam_adc.c b/arch/arm/src/sama5/sam_adc.c index 24099c0d92..ad276ff947 100644 --- a/arch/arm/src/sama5/sam_adc.c +++ b/arch/arm/src/sama5/sam_adc.c @@ -371,6 +371,10 @@ #define SAMA5_ADC_SAMPLES (CONFIG_SAMA5_ADC_DMASAMPLES * SAMA5_NCHANNELS) +#ifndef CONFIG_DEBUG_ANALOG_INFO +# undef CONFIG_SAMA5_ADC_REGDEBUG +#endif + /**************************************************************************** * Private Types ****************************************************************************/ @@ -423,7 +427,7 @@ struct sam_adc_s ****************************************************************************/ /* Register operations ******************************************************/ -#if defined(CONFIG_SAMA5_ADC_REGDEBUG) && defined(CONFIG_DEBUG_FEATURES) +#ifdef CONFIG_SAMA5_ADC_REGDEBUG static bool sam_adc_checkreg(struct sam_adc_s *priv, bool wr, uint32_t regval, uintptr_t address); #endif @@ -544,7 +548,7 @@ static bool sam_adc_checkreg(struct sam_adc_s *priv, bool wr, { /* Yes... show how many times we did it */ - _llerr("...[Repeats %d times]...\n", priv->ntimes); + ainfo("...[Repeats %d times]...\n", priv->ntimes); } /* Save information about the new access */ @@ -2187,7 +2191,7 @@ uint32_t sam_adc_getreg(struct sam_adc_s *priv, uintptr_t address) if (sam_adc_checkreg(priv, false, regval, address)) { - _llerr("%08x->%08x\n", address, regval); + ainfo("%08x->%08x\n", address, regval); } return regval; @@ -2207,7 +2211,7 @@ void sam_adc_putreg(struct sam_adc_s *priv, uintptr_t address, uint32_t regval) { if (sam_adc_checkreg(priv, true, regval, address)) { - _llerr("%08x<-%08x\n", address, regval); + ainfo("%08x<-%08x\n", address, regval); } putreg32(regval, address); diff --git a/arch/arm/src/sama5/sam_allocateheap.c b/arch/arm/src/sama5/sam_allocateheap.c index f772735bae..29dcf728f6 100644 --- a/arch/arm/src/sama5/sam_allocateheap.c +++ b/arch/arm/src/sama5/sam_allocateheap.c @@ -312,9 +312,9 @@ void up_addregion(void) } else { - _llerr("ERROR: SDRAM memory not added to heap. CONFIG_MM_NREGIONS=%d\n", - CONFIG_MM_REGIONS); - _llerr(" Increase the size of CONFIG_MM_NREGIONS\n"); + serr("ERROR: SDRAM memory not added to heap. CONFIG_MM_NREGIONS=%d\n", + CONFIG_MM_REGIONS); + serr(" Increase the size of CONFIG_MM_NREGIONS\n"); } #endif @@ -331,9 +331,9 @@ void up_addregion(void) } else { - _llerr("ERROR: CS0 memory not added to heap. CONFIG_MM_NREGIONS=%d\n", - CONFIG_MM_REGIONS); - _llerr(" Increase the size of CONFIG_MM_NREGIONS\n"); + serr("ERROR: CS0 memory not added to heap. CONFIG_MM_NREGIONS=%d\n", + CONFIG_MM_REGIONS); + serr(" Increase the size of CONFIG_MM_NREGIONS\n"); } #endif @@ -350,9 +350,9 @@ void up_addregion(void) } else { - _llerr("ERROR: CS1 memory not added to heap. CONFIG_MM_NREGIONS=%d\n", - CONFIG_MM_REGIONS); - _llerr(" Increase the size of CONFIG_MM_NREGIONS\n"); + serr("ERROR: CS1 memory not added to heap. CONFIG_MM_NREGIONS=%d\n", + CONFIG_MM_REGIONS); + serr(" Increase the size of CONFIG_MM_NREGIONS\n"); } #endif @@ -369,9 +369,9 @@ void up_addregion(void) } else { - _llerr("ERROR: CS2 memory not added to heap. CONFIG_MM_NREGIONS=%d\n", - CONFIG_MM_REGIONS); - _llerr(" Increase the size of CONFIG_MM_NREGIONS\n"); + serr("ERROR: CS2 memory not added to heap. CONFIG_MM_NREGIONS=%d\n", + CONFIG_MM_REGIONS); + serr(" Increase the size of CONFIG_MM_NREGIONS\n"); } #endif @@ -388,9 +388,9 @@ void up_addregion(void) } else { - _llerr("ERROR: CS3 memory not added to heap. CONFIG_MM_NREGIONS=%d\n", - CONFIG_MM_REGIONS); - _llerr(" Increase the size of CONFIG_MM_NREGIONS\n"); + serr("ERROR: CS3 memory not added to heap. CONFIG_MM_NREGIONS=%d\n", + CONFIG_MM_REGIONS); + serr(" Increase the size of CONFIG_MM_NREGIONS\n"); } #endif @@ -398,9 +398,9 @@ void up_addregion(void) if (nregions > 0) { - _llerr("ERROR: Not all regions added to heap: %d added, but CONFIG_MM_NREGIONS=%d\n", - CONFIG_MM_REGIONS - nregions, CONFIG_MM_REGIONS); - _llerr(" Decrease the size of CONFIG_MM_NREGIONS\n"); + serr("ERROR: Not all regions added to heap: %d added, but CONFIG_MM_NREGIONS=%d\n", + CONFIG_MM_REGIONS - nregions, CONFIG_MM_REGIONS); + serr(" Decrease the size of CONFIG_MM_NREGIONS\n"); } } #endif diff --git a/arch/arm/src/sama5/sam_can.c b/arch/arm/src/sama5/sam_can.c index bb580c9e14..10bb9a4d33 100644 --- a/arch/arm/src/sama5/sam_can.c +++ b/arch/arm/src/sama5/sam_can.c @@ -371,7 +371,7 @@ static uint32_t can_getreg(FAR struct sam_can_s *priv, int offset) { if (priv->count == 4) { - _llerr("...\n"); + caninfo("...\n"); } return regval; @@ -388,7 +388,7 @@ static uint32_t can_getreg(FAR struct sam_can_s *priv, int offset) { /* Yes.. then show how many times the value repeated */ - _llerr("[repeats %d more times]\n", priv->count - 3); + caninfo("[repeats %d more times]\n", priv->count - 3); } /* Save the new address, value, and count */ @@ -400,7 +400,7 @@ static uint32_t can_getreg(FAR struct sam_can_s *priv, int offset) /* Show the register value read */ - _llerr("%08x->%08x\n", regaddr, regval); + caninfo("%08x->%08x\n", regaddr, regval); return regval; } @@ -437,7 +437,7 @@ static void can_putreg(FAR struct sam_can_s *priv, int offset, uint32_t regval) /* Show the register value being written */ - _llerr("%08x<-%08x\n", regaddr, regval); + caninfo("%08x<-%08x\n", regaddr, regval); /* Write the value */ @@ -474,29 +474,29 @@ static void can_dumpctrlregs(FAR struct sam_can_s *priv, FAR const char *msg) if (msg) { - canllerr("Control Registers: %s\n", msg); + caninfo("Control Registers: %s\n", msg); } else { - canllerr("Control Registers:\n"); + caninfo("Control Registers:\n"); } /* CAN control and status registers */ - _llerr(" MR: %08x IMR: %08x SR: %08x\n", - getreg32(config->base + SAM_CAN_MR_OFFSET), - getreg32(config->base + SAM_CAN_IMR_OFFSET), - getreg32(config->base + SAM_CAN_SR_OFFSET)); + caninfo(" MR: %08x IMR: %08x SR: %08x\n", + getreg32(config->base + SAM_CAN_MR_OFFSET), + getreg32(config->base + SAM_CAN_IMR_OFFSET), + getreg32(config->base + SAM_CAN_SR_OFFSET)); - _llerr(" BR: %08x TIM: %08x TIMESTP: %08x\n", - getreg32(config->base + SAM_CAN_BR_OFFSET), - getreg32(config->base + SAM_CAN_TIM_OFFSET), - getreg32(config->base + SAM_CAN_TIMESTP_OFFSET)); + caninfo(" BR: %08x TIM: %08x TIMESTP: %08x\n", + getreg32(config->base + SAM_CAN_BR_OFFSET), + getreg32(config->base + SAM_CAN_TIM_OFFSET), + getreg32(config->base + SAM_CAN_TIMESTP_OFFSET)); - _llerr(" ECR: %08x WPMR: %08x WPSR: %08x\n", - getreg32(config->base + SAM_CAN_ECR_OFFSET), - getreg32(config->base + SAM_CAN_TCR_OFFSET), - getreg32(config->base + SAM_CAN_ACR_OFFSET)); + caninfo(" ECR: %08x WPMR: %08x WPSR: %08x\n", + getreg32(config->base + SAM_CAN_ECR_OFFSET), + getreg32(config->base + SAM_CAN_TCR_OFFSET), + getreg32(config->base + SAM_CAN_ACR_OFFSET)); } #endif @@ -523,30 +523,30 @@ static void can_dumpmbregs(FAR struct sam_can_s *priv, FAR const char *msg) if (msg) { - canllerr("Mailbox Registers: %s\n", msg); + caninfo("Mailbox Registers: %s\n", msg); } else { - canllerr("Mailbox Registers:\n"); + caninfo("Mailbox Registers:\n"); } for (i = 0; i < SAM_CAN_NMAILBOXES; i++) { mbbase = config->base + SAM_CAN_MBn_OFFSET(i); - _llerr(" MB%d:\n", i); + caninfo(" MB%d:\n", i); /* CAN mailbox registers */ - _llerr(" MMR: %08x MAM: %08x MID: %08x MFID: %08x\n", - getreg32(mbbase + SAM_CAN_MMR_OFFSET), - getreg32(mbbase + SAM_CAN_MAM_OFFSET), - getreg32(mbbase + SAM_CAN_MID_OFFSET), - getreg32(mbbase + SAM_CAN_MFID_OFFSET)); + caninfo(" MMR: %08x MAM: %08x MID: %08x MFID: %08x\n", + getreg32(mbbase + SAM_CAN_MMR_OFFSET), + getreg32(mbbase + SAM_CAN_MAM_OFFSET), + getreg32(mbbase + SAM_CAN_MID_OFFSET), + getreg32(mbbase + SAM_CAN_MFID_OFFSET)); - _llerr(" MSR: %08x MDL: %08x MDH: %08x\n", - getreg32(mbbase + SAM_CAN_MSR_OFFSET), - getreg32(mbbase + SAM_CAN_MDL_OFFSET), - getreg32(mbbase + SAM_CAN_MDH_OFFSET)); + caninfo(" MSR: %08x MDL: %08x MDH: %08x\n", + getreg32(mbbase + SAM_CAN_MSR_OFFSET), + getreg32(mbbase + SAM_CAN_MDL_OFFSET), + getreg32(mbbase + SAM_CAN_MDH_OFFSET)); } } #endif @@ -851,7 +851,7 @@ static int can_setup(FAR struct can_dev_s *dev) ret = can_hwinitialize(priv); if (ret < 0) { - canllerr("CAN%d H/W initialization failed: %d\n", config->port, ret); + canllerr("ERROR: CAN%d H/W initialization failed: %d\n", config->port, ret); return ret; } @@ -863,7 +863,7 @@ static int can_setup(FAR struct can_dev_s *dev) ret = irq_attach(config->pid, config->handler); if (ret < 0) { - canllerr("Failed to attach CAN%d IRQ (%d)", config->port, config->pid); + canllerr("ERROR: Failed to attach CAN%d IRQ (%d)", config->port, config->pid); return ret; } @@ -872,7 +872,7 @@ static int can_setup(FAR struct can_dev_s *dev) ret = can_recvsetup(priv); if (ret < 0) { - canllerr("CAN%d H/W initialization failed: %d\n", config->port, ret); + canllerr("ERROR: CAN%d H/W initialization failed: %d\n", config->port, ret); return ret; } @@ -1693,7 +1693,7 @@ static int can_bittiming(struct sam_can_s *priv) { /* The BRP field must be within the range 1 - 0x7f */ - canerr("CAN%d: baud %d too high\n", config->port, config->baud); + canerr("CAN%d ERROR: baud %d too high\n", config->port, config->baud); return -EINVAL; } @@ -1741,7 +1741,7 @@ static int can_bittiming(struct sam_can_s *priv) if ((propag + phase1 + phase2) != (uint32_t)(tq - 4)) { - canerr("CAN%d: Could not realize baud %d\n", config->port, config->baud); + canerr("CAN%d ERROR: Could not realize baud %d\n", config->port, config->baud); return -EINVAL; } diff --git a/arch/arm/src/sama5/sam_dmac.c b/arch/arm/src/sama5/sam_dmac.c index db6bad2ce6..74bbd3f533 100644 --- a/arch/arm/src/sama5/sam_dmac.c +++ b/arch/arm/src/sama5/sam_dmac.c @@ -657,7 +657,7 @@ static uint8_t sam_channel(uint8_t pid, const struct sam_pidmap_s *table, } } - dmaerr("No channel found for pid %d\n", pid); + dmaerr("ERROR: No channel found for pid %d\n", pid); DEBUGPANIC(); return 0x3f; } @@ -2414,27 +2414,27 @@ void sam_dmadump(DMA_HANDLE handle, const struct sam_dmaregs_s *regs, struct sam_dmach_s *dmach = (struct sam_dmach_s *)handle; struct sam_dmac_s *dmac = sam_controller(dmach); - dmaerr("%s\n", msg); - dmaerr(" DMA Global Registers:\n"); - dmaerr(" GCFG[%08x]: %08x\n", dmac->base + SAM_DMAC_GCFG_OFFSET, regs->gcfg); - dmaerr(" EN[%08x]: %08x\n", dmac->base + SAM_DMAC_EN_OFFSET, regs->en); - dmaerr(" SREQ[%08x]: %08x\n", dmac->base + SAM_DMAC_SREQ_OFFSET, regs->sreq); - dmaerr(" CREQ[%08x]: %08x\n", dmac->base + SAM_DMAC_CREQ_OFFSET, regs->creq); - dmaerr(" LAST[%08x]: %08x\n", dmac->base + SAM_DMAC_LAST_OFFSET, regs->last); - dmaerr(" EBCIMR[%08x]: %08x\n", dmac->base + SAM_DMAC_EBCIMR_OFFSET, regs->ebcimr); - dmaerr(" EBCISR[%08x]: %08x\n", dmac->base + SAM_DMAC_EBCISR_OFFSET, regs->ebcisr); - dmaerr(" CHSR[%08x]: %08x\n", dmac->base + SAM_DMAC_CHSR_OFFSET, regs->chsr); - dmaerr(" WPMR[%08x]: %08x\n", dmac->base + SAM_DMAC_WPMR_OFFSET, regs->wpmr); - dmaerr(" WPSR[%08x]: %08x\n", dmac->base + SAM_DMAC_WPSR_OFFSET, regs->wpsr); - dmaerr(" DMA Channel Registers:\n"); - dmaerr(" SADDR[%08x]: %08x\n", dmach->base + SAM_DMAC_CH_SADDR_OFFSET, regs->saddr); - dmaerr(" DADDR[%08x]: %08x\n", dmach->base + SAM_DMAC_CH_DADDR_OFFSET, regs->daddr); - dmaerr(" DSCR[%08x]: %08x\n", dmach->base + SAM_DMAC_CH_DSCR_OFFSET, regs->dscr); - dmaerr(" CTRLA[%08x]: %08x\n", dmach->base + SAM_DMAC_CH_CTRLA_OFFSET, regs->ctrla); - dmaerr(" CTRLB[%08x]: %08x\n", dmach->base + SAM_DMAC_CH_CTRLB_OFFSET, regs->ctrlb); - dmaerr(" CFG[%08x]: %08x\n", dmach->base + SAM_DMAC_CH_CFG_OFFSET, regs->cfg); - dmaerr(" SPIP[%08x]: %08x\n", dmach->base + SAM_DMAC_CH_SPIP_OFFSET, regs->spip); - dmaerr(" DPIP[%08x]: %08x\n", dmach->base + SAM_DMAC_CH_DPIP_OFFSET, regs->dpip); + dmainfo("%s\n", msg); + dmainfo(" DMA Global Registers:\n"); + dmainfo(" GCFG[%08x]: %08x\n", dmac->base + SAM_DMAC_GCFG_OFFSET, regs->gcfg); + dmainfo(" EN[%08x]: %08x\n", dmac->base + SAM_DMAC_EN_OFFSET, regs->en); + dmainfo(" SREQ[%08x]: %08x\n", dmac->base + SAM_DMAC_SREQ_OFFSET, regs->sreq); + dmainfo(" CREQ[%08x]: %08x\n", dmac->base + SAM_DMAC_CREQ_OFFSET, regs->creq); + dmainfo(" LAST[%08x]: %08x\n", dmac->base + SAM_DMAC_LAST_OFFSET, regs->last); + dmainfo(" EBCIMR[%08x]: %08x\n", dmac->base + SAM_DMAC_EBCIMR_OFFSET, regs->ebcimr); + dmainfo(" EBCISR[%08x]: %08x\n", dmac->base + SAM_DMAC_EBCISR_OFFSET, regs->ebcisr); + dmainfo(" CHSR[%08x]: %08x\n", dmac->base + SAM_DMAC_CHSR_OFFSET, regs->chsr); + dmainfo(" WPMR[%08x]: %08x\n", dmac->base + SAM_DMAC_WPMR_OFFSET, regs->wpmr); + dmainfo(" WPSR[%08x]: %08x\n", dmac->base + SAM_DMAC_WPSR_OFFSET, regs->wpsr); + dmainfo(" DMA Channel Registers:\n"); + dmainfo(" SADDR[%08x]: %08x\n", dmach->base + SAM_DMAC_CH_SADDR_OFFSET, regs->saddr); + dmainfo(" DADDR[%08x]: %08x\n", dmach->base + SAM_DMAC_CH_DADDR_OFFSET, regs->daddr); + dmainfo(" DSCR[%08x]: %08x\n", dmach->base + SAM_DMAC_CH_DSCR_OFFSET, regs->dscr); + dmainfo(" CTRLA[%08x]: %08x\n", dmach->base + SAM_DMAC_CH_CTRLA_OFFSET, regs->ctrla); + dmainfo(" CTRLB[%08x]: %08x\n", dmach->base + SAM_DMAC_CH_CTRLB_OFFSET, regs->ctrlb); + dmainfo(" CFG[%08x]: %08x\n", dmach->base + SAM_DMAC_CH_CFG_OFFSET, regs->cfg); + dmainfo(" SPIP[%08x]: %08x\n", dmach->base + SAM_DMAC_CH_SPIP_OFFSET, regs->spip); + dmainfo(" DPIP[%08x]: %08x\n", dmach->base + SAM_DMAC_CH_DPIP_OFFSET, regs->dpip); } #endif /* CONFIG_DEBUG_DMA */ #endif /* CONFIG_SAMA5_DMAC0 || CONFIG_SAMA5_DMAC1 */ diff --git a/arch/arm/src/sama5/sam_ehci.c b/arch/arm/src/sama5/sam_ehci.c index b39d925c8b..cdd86c208b 100644 --- a/arch/arm/src/sama5/sam_ehci.c +++ b/arch/arm/src/sama5/sam_ehci.c @@ -112,7 +112,7 @@ /* Debug options */ -#ifndef CONFIG_DEBUG_FEATURES +#ifndef CONFIG_DEBUG_USB_INFO # undef CONFIG_SAMA5_EHCI_REGDEBUG #endif @@ -628,7 +628,7 @@ static uint32_t sam_swap32(uint32_t value) static void sam_printreg(volatile uint32_t *regaddr, uint32_t regval, bool iswrite) { - _llerr("%08x%s%08x\n", (uintptr_t)regaddr, iswrite ? "<-" : "->", regval); + uinfo("%08x%s%08x\n", (uintptr_t)regaddr, iswrite ? "<-" : "->", regval); } #endif @@ -679,7 +679,7 @@ static void sam_checkreg(volatile uint32_t *regaddr, uint32_t regval, bool iswri { /* No.. More than one. */ - _llerr("[repeats %d more times]\n", count); + uinfo("[repeats %d more times]\n", count); } } @@ -1268,13 +1268,13 @@ static int sam_qh_flush(struct sam_qh_s *qh) #ifdef CONFIG_SAMA5_EHCI_REGDEBUG static void sam_qtd_print(struct sam_qtd_s *qtd) { - uerr(" QTD[%p]:\n", qtd); - uerr(" hw:\n"); - uerr(" nqp: %08x alt: %08x token: %08x\n", - qtd->hw.nqp, qtd->hw.alt, qtd->hw.token); - uerr(" bpl: %08x %08x %08x %08x %08x\n", - qtd->hw.bpl[0], qtd->hw.bpl[1], qtd->hw.bpl[2], - qtd->hw.bpl[3], qtd->hw.bpl[4]); + uinfo(" QTD[%p]:\n", qtd); + uinfo(" hw:\n"); + uinfo(" nqp: %08x alt: %08x token: %08x\n", + qtd->hw.nqp, qtd->hw.alt, qtd->hw.token); + uinfo(" bpl: %08x %08x %08x %08x %08x\n", + qtd->hw.bpl[0], qtd->hw.bpl[1], qtd->hw.bpl[2], + qtd->hw.bpl[3], qtd->hw.bpl[4]); } #endif @@ -1292,30 +1292,30 @@ static void sam_qh_print(struct sam_qh_s *qh) struct sam_epinfo_s *epinfo; struct ehci_overlay_s *overlay; - uerr("QH[%p]:\n", qh); - uerr(" hw:\n"); - uerr(" hlp: %08x epchar: %08x epcaps: %08x cqp: %08x\n", - qh->hw.hlp, qh->hw.epchar, qh->hw.epcaps, qh->hw.cqp); + uinfo("QH[%p]:\n", qh); + uinfo(" hw:\n"); + uinfo(" hlp: %08x epchar: %08x epcaps: %08x cqp: %08x\n", + qh->hw.hlp, qh->hw.epchar, qh->hw.epcaps, qh->hw.cqp); overlay = &qh->hw.overlay; - uerr(" overlay:\n"); - uerr(" nqp: %08x alt: %08x token: %08x\n", - overlay->nqp, overlay->alt, overlay->token); - uerr(" bpl: %08x %08x %08x %08x %08x\n", - overlay->bpl[0], overlay->bpl[1], overlay->bpl[2], - overlay->bpl[3], overlay->bpl[4]); + uinfo(" overlay:\n"); + uinfo(" nqp: %08x alt: %08x token: %08x\n", + overlay->nqp, overlay->alt, overlay->token); + uinfo(" bpl: %08x %08x %08x %08x %08x\n", + overlay->bpl[0], overlay->bpl[1], overlay->bpl[2], + overlay->bpl[3], overlay->bpl[4]); - uerr(" fqp:\n", qh->fqp); + uinfo(" fqp:\n", qh->fqp); epinfo = qh->epinfo; - uerr(" epinfo[%p]:\n", epinfo); + uinfo(" epinfo[%p]:\n", epinfo); if (epinfo) { - uerr(" EP%d DIR=%s FA=%08x TYPE=%d MaxPacket=%d\n", - epinfo->epno, epinfo->dirin ? "IN" : "OUT", epinfo->devaddr, - epinfo->xfrtype, epinfo->maxpacket); - uerr(" Toggle=%d iocwait=%d speed=%d result=%d\n", - epinfo->toggle, epinfo->iocwait, epinfo->speed, epinfo->result); + uinfo(" EP%d DIR=%s FA=%08x TYPE=%d MaxPacket=%d\n", + epinfo->epno, epinfo->dirin ? "IN" : "OUT", epinfo->devaddr, + epinfo->xfrtype, epinfo->maxpacket); + uinfo(" Toggle=%d iocwait=%d speed=%d result=%d\n", + epinfo->toggle, epinfo->iocwait, epinfo->speed, epinfo->result); } } #endif diff --git a/arch/arm/src/sama5/sam_emaca.c b/arch/arm/src/sama5/sam_emaca.c index 04267d09a8..553d15f51b 100644 --- a/arch/arm/src/sama5/sam_emaca.c +++ b/arch/arm/src/sama5/sam_emaca.c @@ -223,7 +223,7 @@ * enabled. */ -#ifndef CONFIG_DEBUG_FEATURES +#ifndef CONFIG_DEBUG_NET_INFO # undef CONFIG_SAMA5_EMACA_REGDEBUG #endif @@ -335,7 +335,7 @@ static uint8_t g_rxbuffer[CONFIG_SAMA5_EMAC_NRXBUFFERS * EMAC_RX_UNITSIZE] ****************************************************************************/ /* Register operations ******************************************************/ -#if defined(CONFIG_SAMA5_EMACA_REGDEBUG) && defined(CONFIG_DEBUG_FEATURES) +#ifdef CONFIG_SAMA5_EMACA_REGDEBUG static bool sam_checkreg(struct sam_emac_s *priv, bool wr, uint32_t regval, uintptr_t address); static uint32_t sam_getreg(struct sam_emac_s *priv, uintptr_t addr); @@ -461,7 +461,7 @@ static bool sam_checkreg(struct sam_emac_s *priv, bool wr, uint32_t regval, { /* Yes... show how many times we did it */ - _llerr("...[Repeats %d times]...\n", priv->ntimes); + ninfo("...[Repeats %d times]...\n", priv->ntimes); } /* Save information about the new access */ @@ -493,7 +493,7 @@ static uint32_t sam_getreg(struct sam_emac_s *priv, uintptr_t address) if (sam_checkreg(priv, false, regval, address)) { - _llerr("%08x->%08x\n", address, regval); + ninfo("%08x->%08x\n", address, regval); } return regval; @@ -514,7 +514,7 @@ static void sam_putreg(struct sam_emac_s *priv, uintptr_t address, { if (sam_checkreg(priv, true, regval, address)) { - _llerr("%08x<-%08x\n", address, regval); + ninfo("%08x<-%08x\n", address, regval); } putreg32(regval, address); @@ -1212,7 +1212,7 @@ static void sam_receive(struct sam_emac_s *priv) if (dev->d_len > CONFIG_NET_ETH_MTU) { - nllerr("DROPPED: Too big: %d\n", dev->d_len); + nllwarn("WARNING: Dropped, Too big: %d\n", dev->d_len); continue; } @@ -1322,7 +1322,7 @@ static void sam_receive(struct sam_emac_s *priv) else #endif { - nllerr("DROPPED: Unknown type: %04x\n", BUF->type); + nllwarn("WARNING: Dropped, Unknown type: %04x\n", BUF->type); } } } @@ -1584,7 +1584,7 @@ static int sam_emac_interrupt(int irq, void *context) if ((pending & EMAC_INT_PFR) != 0) { - nllerr("Pause frame received\n"); + nllwarn("WARNING: Pause frame received\n"); } /* Check for Pause Time Zero (PTZ) @@ -1594,7 +1594,7 @@ static int sam_emac_interrupt(int irq, void *context) if ((pending & EMAC_INT_PTZ) != 0) { - nllerr("Pause TO!\n"); + nllwarn("WARNING: Pause TO!\n"); } #endif @@ -1624,7 +1624,7 @@ static void sam_txtimeout(int argc, uint32_t arg, ...) { struct sam_emac_s *priv = (struct sam_emac_s *)arg; - nllerr("Timeout!\n"); + nllerr("ERROR: Timeout!\n"); /* Then reset the hardware. Just take the interface down, then back * up again. @@ -1699,9 +1699,9 @@ static int sam_ifup(struct net_driver_s *dev) struct sam_emac_s *priv = (struct sam_emac_s *)dev->d_private; int ret; - nllerr("Bringing up: %d.%d.%d.%d\n", - dev->d_ipaddr & 0xff, (dev->d_ipaddr >> 8) & 0xff, - (dev->d_ipaddr >> 16) & 0xff, dev->d_ipaddr >> 24); + ninfo("Bringing up: %d.%d.%d.%d\n", + dev->d_ipaddr & 0xff, (dev->d_ipaddr >> 8) & 0xff, + (dev->d_ipaddr >> 16) & 0xff, dev->d_ipaddr >> 24); /* Configure the EMAC interface for normal operation. */ @@ -1775,7 +1775,7 @@ static int sam_ifdown(struct net_driver_s *dev) struct sam_emac_s *priv = (struct sam_emac_s *)dev->d_private; irqstate_t flags; - nllerr("Taking the network down\n"); + ninfo("Taking the network down\n"); /* Disable the EMAC interrupt */ diff --git a/arch/arm/src/sama5/sam_emacb.c b/arch/arm/src/sama5/sam_emacb.c index 66155406e9..6dab62599f 100644 --- a/arch/arm/src/sama5/sam_emacb.c +++ b/arch/arm/src/sama5/sam_emacb.c @@ -295,7 +295,7 @@ * enabled. */ -#ifndef CONFIG_DEBUG_FEATURES +#ifndef CONFIG_DEBUG_NET_INFO # undef CONFIG_SAMA5_EMACB_REGDEBUG #endif @@ -820,7 +820,7 @@ static bool sam_checkreg(struct sam_emac_s *priv, bool wr, uint32_t regval, { /* Yes... show how many times we did it */ - _llerr("...[Repeats %d times]...\n", priv->ntimes); + ninfo("...[Repeats %d times]...\n", priv->ntimes); } /* Save information about the new access */ @@ -853,7 +853,7 @@ static uint32_t sam_getreg(struct sam_emac_s *priv, uint16_t offset) #ifdef CONFIG_SAMA5_EMACB_REGDEBUG if (sam_checkreg(priv, false, regval, regaddr)) { - _llerr("%08x->%08x\n", regaddr, regval); + ninfo("%08x->%08x\n", regaddr, regval); } #endif @@ -877,7 +877,7 @@ static void sam_putreg(struct sam_emac_s *priv, uint16_t offset, #ifdef CONFIG_SAMA5_EMACB_REGDEBUG if (sam_checkreg(priv, true, regval, regaddr)) { - _llerr("%08x<-%08x\n", regaddr, regval); + ninfo("%08x<-%08x\n", regaddr, regval); } #endif @@ -1575,7 +1575,7 @@ static void sam_receive(struct sam_emac_s *priv) if (dev->d_len > CONFIG_NET_ETH_MTU) { - nllerr("DROPPED: Too big: %d\n", dev->d_len); + nllwarn("WARNING: Dropped, Too big: %d\n", dev->d_len); continue; } @@ -1685,7 +1685,7 @@ static void sam_receive(struct sam_emac_s *priv) else #endif { - nllerr("DROPPED: Unknown type: %04x\n", BUF->type); + nllwarn("WARNING: Dropped, Unknown type: %04x\n", BUF->type); } } } @@ -1972,7 +1972,7 @@ static inline void sam_interrupt_process(FAR struct sam_emac_s *priv) if ((pending & EMAC_INT_PFNZ) != 0) { - nllerr("Pause frame received\n"); + nllwarn("WARNING: Pause frame received\n"); } /* Check for Pause Time Zero (PTZ) @@ -1982,7 +1982,7 @@ static inline void sam_interrupt_process(FAR struct sam_emac_s *priv) if ((pending & EMAC_INT_PTZ) != 0) { - nllerr("Pause TO!\n"); + nllwarn("WARNING: Pause TO!\n"); } #endif } @@ -2147,7 +2147,7 @@ static int sam_emac1_interrupt(int irq, void *context) static inline void sam_txtimeout_process(FAR struct sam_emac_s *priv) { - nllerr("Timeout!\n"); + nllerr("ERROR: Timeout!\n"); /* Reset the hardware. Just take the interface down, then back up again. */ @@ -2377,15 +2377,15 @@ static int sam_ifup(struct net_driver_s *dev) int ret; #ifdef CONFIG_NET_IPv4 - nerr("Bringing up: %d.%d.%d.%d\n", - dev->d_ipaddr & 0xff, (dev->d_ipaddr >> 8) & 0xff, - (dev->d_ipaddr >> 16) & 0xff, dev->d_ipaddr >> 24); + ninfo("Bringing up: %d.%d.%d.%d\n", + dev->d_ipaddr & 0xff, (dev->d_ipaddr >> 8) & 0xff, + (dev->d_ipaddr >> 16) & 0xff, dev->d_ipaddr >> 24); #endif #ifdef CONFIG_NET_IPv6 - nerr("Bringing up: %04x:%04x:%04x:%04x:%04x:%04x:%04x:%04x\n", - dev->d_ipv6addr[0], dev->d_ipv6addr[1], dev->d_ipv6addr[2], - dev->d_ipv6addr[3], dev->d_ipv6addr[4], dev->d_ipv6addr[5], - dev->d_ipv6addr[6], dev->d_ipv6addr[7]); + ninfo("Bringing up: %04x:%04x:%04x:%04x:%04x:%04x:%04x:%04x\n", + dev->d_ipv6addr[0], dev->d_ipv6addr[1], dev->d_ipv6addr[2], + dev->d_ipv6addr[3], dev->d_ipv6addr[4], dev->d_ipv6addr[5], + dev->d_ipv6addr[6], dev->d_ipv6addr[7]); #endif /* Configure the EMAC interface for normal operation. */ @@ -2460,7 +2460,7 @@ static int sam_ifdown(struct net_driver_s *dev) struct sam_emac_s *priv = (struct sam_emac_s *)dev->d_private; irqstate_t flags; - nllerr("Taking the network down\n"); + nllinfo("Taking the network down\n"); /* Disable the EMAC interrupt */ diff --git a/arch/arm/src/sama5/sam_gmac.c b/arch/arm/src/sama5/sam_gmac.c index 3bf136c310..66472d3683 100644 --- a/arch/arm/src/sama5/sam_gmac.c +++ b/arch/arm/src/sama5/sam_gmac.c @@ -149,7 +149,7 @@ * enabled. */ -#ifndef CONFIG_DEBUG_FEATURES +#ifndef CONFIG_DEBUG_NET_INFO # undef CONFIG_SAMA5_GMAC_REGDEBUG #endif @@ -392,7 +392,7 @@ static bool sam_checkreg(struct sam_gmac_s *priv, bool wr, uint32_t regval, { /* Yes... show how many times we did it */ - _llerr("...[Repeats %d times]...\n", priv->ntimes); + ninfo("...[Repeats %d times]...\n", priv->ntimes); } /* Save information about the new access */ @@ -424,7 +424,7 @@ static uint32_t sam_getreg(struct sam_gmac_s *priv, uintptr_t address) if (sam_checkreg(priv, false, regval, address)) { - _llerr("%08x->%08x\n", address, regval); + ninfo("%08x->%08x\n", address, regval); } return regval; @@ -445,7 +445,7 @@ static void sam_putreg(struct sam_gmac_s *priv, uintptr_t address, { if (sam_checkreg(priv, true, regval, address)) { - _llerr("%08x<-%08x\n", address, regval); + ninfo("%08x<-%08x\n", address, regval); } putreg32(regval, address); @@ -1142,7 +1142,7 @@ static void sam_receive(struct sam_gmac_s *priv) if (dev->d_len > CONFIG_NET_ETH_MTU) { - nllerr("DROPPED: Too big: %d\n", dev->d_len); + nllwarn("WARNING: Dropped, Too big: %d\n", dev->d_len); continue; } @@ -1252,7 +1252,7 @@ static void sam_receive(struct sam_gmac_s *priv) else #endif { - nllerr("DROPPED: Unknown type: %04x\n", BUF->type); + nllwarn("WARNING: Dropped, Unknown type: %04x\n", BUF->type); } } } @@ -1536,7 +1536,7 @@ static int sam_gmac_interrupt(int irq, void *context) if ((pending & GMAC_INT_PFNZ) != 0) { - nllerr("Pause frame received\n"); + nllwarn("WARNING: Pause frame received\n"); } /* Check for Pause Time Zero (PTZ) @@ -1546,7 +1546,7 @@ static int sam_gmac_interrupt(int irq, void *context) if ((pending & GMAC_INT_PTZ) != 0) { - nllerr("Pause TO!\n"); + nllwarn("WARNING: Pause TO!\n"); } #endif @@ -1576,7 +1576,7 @@ static void sam_txtimeout(int argc, uint32_t arg, ...) { struct sam_gmac_s *priv = (struct sam_gmac_s *)arg; - nllerr("Timeout!\n"); + nllerr("ERROR: Timeout!\n"); /* Then reset the hardware. Just take the interface down, then back * up again. @@ -1651,9 +1651,9 @@ static int sam_ifup(struct net_driver_s *dev) struct sam_gmac_s *priv = (struct sam_gmac_s *)dev->d_private; int ret; - nllerr("Bringing up: %d.%d.%d.%d\n", - dev->d_ipaddr & 0xff, (dev->d_ipaddr >> 8) & 0xff, - (dev->d_ipaddr >> 16) & 0xff, dev->d_ipaddr >> 24); + ninfo("Bringing up: %d.%d.%d.%d\n", + dev->d_ipaddr & 0xff, (dev->d_ipaddr >> 8) & 0xff, + (dev->d_ipaddr >> 16) & 0xff, dev->d_ipaddr >> 24); /* Configure the GMAC interface for normal operation. */ @@ -1730,7 +1730,7 @@ static int sam_ifdown(struct net_driver_s *dev) struct sam_gmac_s *priv = (struct sam_gmac_s *)dev->d_private; irqstate_t flags; - nllerr("Taking the network down\n"); + ninfo("Taking the network down\n"); /* Disable the GMAC interrupt */ diff --git a/arch/arm/src/sama5/sam_hsmci.c b/arch/arm/src/sama5/sam_hsmci.c index 026424fae7..db8054fe2d 100644 --- a/arch/arm/src/sama5/sam_hsmci.c +++ b/arch/arm/src/sama5/sam_hsmci.c @@ -79,6 +79,10 @@ /* Configuration ************************************************************/ +#ifndef CONFIG_DEBUG_MEMCARD_INFO +# undef CONFIG_SAMA5_HSMCI_REGDEBUG +#endif + #if defined(ATSAMA5D3) /* The SAMA5D3 has three HSMCI blocks: HSMCI0-2. HSMCI0 requires DMAC0 * support, HSMCI1-2 require DMAC1 support. @@ -725,7 +729,7 @@ static bool sam_checkreg(struct sam_dev_s *priv, bool wr, uint32_t value, { /* Yes... show how many times we did it */ - _llerr("...[Repeats %d times]...\n", priv->ntimes); + mcinfo("...[Repeats %d times]...\n", priv->ntimes); } /* Save information about the new access */ @@ -758,7 +762,7 @@ static inline uint32_t sam_getreg(struct sam_dev_s *priv, unsigned int offset) #ifdef CONFIG_SAMA5_HSMCI_REGDEBUG if (sam_checkreg(priv, false, value, address)) { - _llerr("%08x->%08x\n", address, value); + mcinfo("%08x->%08x\n", address, value); } #endif @@ -781,7 +785,7 @@ static inline void sam_putreg(struct sam_dev_s *priv, uint32_t value, #ifdef CONFIG_SAMA5_HSMCI_REGDEBUG if (sam_checkreg(priv, true, value, address)) { - _llerr("%08x<-%08x\n", address, value); + mcinfo("%08x<-%08x\n", address, value); } #endif @@ -1003,23 +1007,23 @@ static void sam_hsmcisample(struct sam_dev_s *priv, static void sam_hsmcidump(struct sam_dev_s *priv, struct sam_hsmciregs_s *regs, const char *msg) { - ferr("HSMCI Registers: %s\n", msg); - ferr(" MR[%08x]: %08x\n", priv->base + SAM_HSMCI_MR_OFFSET, regs->mr); - ferr(" DTOR[%08x]: %08x\n", priv->base + SAM_HSMCI_DTOR_OFFSET, regs->dtor); - ferr(" SDCR[%08x]: %08x\n", priv->base + SAM_HSMCI_SDCR_OFFSET, regs->sdcr); - ferr(" ARGR[%08x]: %08x\n", priv->base + SAM_HSMCI_ARGR_OFFSET, regs->argr); - ferr(" BLKR[%08x]: %08x\n", priv->base + SAM_HSMCI_BLKR_OFFSET, regs->blkr); - ferr(" CSTOR[%08x]: %08x\n", priv->base + SAM_HSMCI_CSTOR_OFFSET, regs->cstor); - ferr(" RSPR0[%08x]: %08x\n", priv->base + SAM_HSMCI_RSPR0_OFFSET, regs->rsp0); - ferr(" RSPR1[%08x]: %08x\n", priv->base + SAM_HSMCI_RSPR1_OFFSET, regs->rsp1); - ferr(" RSPR2[%08x]: %08x\n", priv->base + SAM_HSMCI_RSPR2_OFFSET, regs->rsp2); - ferr(" RSPR3[%08x]: %08x\n", priv->base + SAM_HSMCI_RSPR3_OFFSET, regs->rsp3); - ferr(" SR[%08x]: %08x\n", priv->base + SAM_HSMCI_SR_OFFSET, regs->sr); - ferr(" IMR[%08x]: %08x\n", priv->base + SAM_HSMCI_IMR_OFFSET, regs->imr); - ferr(" DMA[%08x]: %08x\n", priv->base + SAM_HSMCI_DMA_OFFSET, regs->dma); - ferr(" CFG[%08x]: %08x\n", priv->base + SAM_HSMCI_CFG_OFFSET, regs->cfg); - ferr(" WPMR[%08x]: %08x\n", priv->base + SAM_HSMCI_WPMR_OFFSET, regs->wpmr); - ferr(" WPSR[%08x]: %08x\n", priv->base + SAM_HSMCI_WPSR_OFFSET, regs->wpsr); + lcdinfo("HSMCI Registers: %s\n", msg); + lcdinfo(" MR[%08x]: %08x\n", priv->base + SAM_HSMCI_MR_OFFSET, regs->mr); + lcdinfo(" DTOR[%08x]: %08x\n", priv->base + SAM_HSMCI_DTOR_OFFSET, regs->dtor); + lcdinfo(" SDCR[%08x]: %08x\n", priv->base + SAM_HSMCI_SDCR_OFFSET, regs->sdcr); + lcdinfo(" ARGR[%08x]: %08x\n", priv->base + SAM_HSMCI_ARGR_OFFSET, regs->argr); + lcdinfo(" BLKR[%08x]: %08x\n", priv->base + SAM_HSMCI_BLKR_OFFSET, regs->blkr); + lcdinfo(" CSTOR[%08x]: %08x\n", priv->base + SAM_HSMCI_CSTOR_OFFSET, regs->cstor); + lcdinfo(" RSPR0[%08x]: %08x\n", priv->base + SAM_HSMCI_RSPR0_OFFSET, regs->rsp0); + lcdinfo(" RSPR1[%08x]: %08x\n", priv->base + SAM_HSMCI_RSPR1_OFFSET, regs->rsp1); + lcdinfo(" RSPR2[%08x]: %08x\n", priv->base + SAM_HSMCI_RSPR2_OFFSET, regs->rsp2); + lcdinfo(" RSPR3[%08x]: %08x\n", priv->base + SAM_HSMCI_RSPR3_OFFSET, regs->rsp3); + lcdinfo(" SR[%08x]: %08x\n", priv->base + SAM_HSMCI_SR_OFFSET, regs->sr); + lcdinfo(" IMR[%08x]: %08x\n", priv->base + SAM_HSMCI_IMR_OFFSET, regs->imr); + lcdinfo(" DMA[%08x]: %08x\n", priv->base + SAM_HSMCI_DMA_OFFSET, regs->dma); + lcdinfo(" CFG[%08x]: %08x\n", priv->base + SAM_HSMCI_CFG_OFFSET, regs->cfg); + lcdinfo(" WPMR[%08x]: %08x\n", priv->base + SAM_HSMCI_WPMR_OFFSET, regs->wpmr); + lcdinfo(" WPSR[%08x]: %08x\n", priv->base + SAM_HSMCI_WPSR_OFFSET, regs->wpsr); } #endif @@ -1093,7 +1097,7 @@ static void sam_xfrdumpone(struct sam_dev_s *priv, int index, } else { - ferr("%s: Not collected\n", msg); + lcdinfo("%s: Not collected\n", msg); } } #endif @@ -2253,7 +2257,7 @@ static int sam_sendsetup(FAR struct sdio_dev_s *dev, FAR const uint8_t *buffer, { /* Some fatal error has occurred */ - ferr("ERROR: sr %08x\n", sr); + lcderr("ERROR: sr %08x\n", sr); return -EIO; } else if ((sr & HSMCI_INT_TXRDY) != 0) @@ -2388,7 +2392,7 @@ static int sam_waitresponse(FAR struct sdio_dev_s *dev, uint32_t cmd) { /* Yes.. Was the error some kind of timeout? */ - ferr("ERROR: cmd: %08x events: %08x SR: %08x\n", + lcderr("ERROR: cmd: %08x events: %08x SR: %08x\n", cmd, priv->cmdrmask, sr); if ((pending & HSMCI_RESPONSE_TIMEOUT_ERRORS) != 0) @@ -2418,8 +2422,8 @@ static int sam_waitresponse(FAR struct sdio_dev_s *dev, uint32_t cmd) } else if (--timeout <= 0) { - ferr("ERROR: Timeout cmd: %08x events: %08x SR: %08x\n", - cmd, priv->cmdrmask, sr); + lcderr("ERROR: Timeout cmd: %08x events: %08x SR: %08x\n", + cmd, priv->cmdrmask, sr); priv->wkupevent = SDIOWAIT_TIMEOUT; return -ETIMEDOUT; @@ -2493,7 +2497,7 @@ static int sam_recvshort(FAR struct sdio_dev_s *dev, #ifdef CONFIG_DEBUG_FEATURES if (!rshort) { - ferr("ERROR: rshort=NULL\n"); + lcderr("ERROR: rshort=NULL\n"); ret = -EINVAL; } @@ -2505,7 +2509,7 @@ static int sam_recvshort(FAR struct sdio_dev_s *dev, (cmd & MMCSD_RESPONSE_MASK) != MMCSD_R3_RESPONSE && (cmd & MMCSD_RESPONSE_MASK) != MMCSD_R7_RESPONSE) { - ferr("ERROR: Wrong response CMD=%08x\n", cmd); + lcderr("ERROR: Wrong response CMD=%08x\n", cmd); ret = -EINVAL; } else @@ -2555,7 +2559,7 @@ static int sam_recvlong(FAR struct sdio_dev_s *dev, uint32_t cmd, uint32_t rlong if ((cmd & MMCSD_RESPONSE_MASK) != MMCSD_R2_RESPONSE) { - ferr("ERROR: Wrong response CMD=%08x\n", cmd); + lcderr("ERROR: Wrong response CMD=%08x\n", cmd); ret = -EINVAL; } else @@ -2746,7 +2750,7 @@ static sdio_eventset_t sam_eventwait(FAR struct sdio_dev_s *dev, 1, (uint32_t)priv); if (ret != OK) { - ferr("ERROR: wd_start failed: %d\n", ret); + lcderr("ERROR: wd_start failed: %d\n", ret); } } @@ -3150,7 +3154,7 @@ static void sam_callback(void *arg) { /* NOTE: Currently, work_cancel only returns success */ - ferr("ERROR: Failed to cancel work: %d\n", ret); + lcderr("ERROR: Failed to cancel work: %d\n", ret); } fllinfo("Queuing callback to %p(%p)\n", priv->callback, priv->cbarg); @@ -3160,7 +3164,7 @@ static void sam_callback(void *arg) { /* NOTE: Currently, work_queue only returns success */ - ferr("ERROR: Failed to schedule work: %d\n", ret); + lcderr("ERROR: Failed to schedule work: %d\n", ret); } } @@ -3199,7 +3203,7 @@ FAR struct sdio_dev_s *sdio_initialize(int slotno) * for now, an* HSMCI peripheral does correspond to a slot. */ - ferr("slotno: %d\n", slotno); + lcdinfo("slotno: %d\n", slotno); #ifdef CONFIG_SAMA5_HSMCI0 if (slotno == 0) diff --git a/arch/arm/src/sama5/sam_lcd.c b/arch/arm/src/sama5/sam_lcd.c index eef9767adf..3befc8fec6 100644 --- a/arch/arm/src/sama5/sam_lcd.c +++ b/arch/arm/src/sama5/sam_lcd.c @@ -492,7 +492,7 @@ /* Debug */ -#ifndef CONFIG_DEBUG_FEATURES +#ifndef CONFIG_DEBUG_LCD_INFO # undef CONFIG_SAMA5_LCDC_REGDEBUG #endif @@ -666,7 +666,7 @@ struct sam_lcdc_s ****************************************************************************/ /* Register operations ******************************************************/ -#if defined(CONFIG_SAMA5_LCDC_REGDEBUG) && defined(CONFIG_DEBUG_FEATURES) +#ifdef CONFIG_SAMA5_LCDC_REGDEBUG static bool sam_checkreg(bool wr, uint32_t regval, uintptr_t address); static uint32_t sam_getreg(uintptr_t addr); static void sam_putreg(uintptr_t addr, uint32_t val); @@ -977,10 +977,6 @@ static const uintptr_t g_layerclut[LCDC_NLAYERS] = }; #endif -/**************************************************************************** - * Public Data - ****************************************************************************/ - /**************************************************************************** * Private Functions ****************************************************************************/ @@ -1021,7 +1017,7 @@ static bool sam_checkreg(bool wr, uint32_t regval, uintptr_t address) { /* Yes... show how many times we did it */ - _llerr("...[Repeats %d times]...\n", g_lcdc.ntimes); + lcdinfo("...[Repeats %d times]...\n", g_lcdc.ntimes); } /* Save information about the new access */ @@ -1053,7 +1049,7 @@ static uint32_t sam_getreg(uintptr_t address) if (sam_checkreg(false, regval, address)) { - _llerr("%08x->%08x\n", address, regval); + lcdinfo("%08x->%08x\n", address, regval); } return regval; @@ -1073,7 +1069,7 @@ static void sam_putreg(uintptr_t address, uint32_t regval) { if (sam_checkreg(true, regval, address)) { - _llerr("%08x<-%08x\n", address, regval); + lcdinfo("%08x<-%08x\n", address, regval); } putreg32(regval, address); @@ -1101,14 +1097,14 @@ static void sam_wait_lcdstatus(uint32_t mask, uint32_t value) static int sam_base_getvideoinfo(struct fb_vtable_s *vtable, struct fb_videoinfo_s *vinfo) { - ginfo("vtable=%p vinfo=%p\n", vtable, vinfo); + lcdinfo("vtable=%p vinfo=%p\n", vtable, vinfo); if (vtable && vinfo) { memcpy(vinfo, &g_base_videoinfo, sizeof(struct fb_videoinfo_s)); return OK; } - gerr("ERROR: Returning EINVAL\n"); + lcderr("ERROR: Returning EINVAL\n"); return -EINVAL; } @@ -1119,7 +1115,7 @@ static int sam_base_getvideoinfo(struct fb_vtable_s *vtable, static int sam_base_getplaneinfo(struct fb_vtable_s *vtable, int planeno, struct fb_planeinfo_s *pinfo) { - ginfo("vtable=%p planeno=%d pinfo=%p\n", vtable, planeno, pinfo); + lcdinfo("vtable=%p planeno=%d pinfo=%p\n", vtable, planeno, pinfo); if (vtable && planeno == 0 && pinfo) { pinfo->fbmem = (void *)LAYER_BASE.framebuffer; @@ -1130,7 +1126,7 @@ static int sam_base_getplaneinfo(struct fb_vtable_s *vtable, int planeno, return OK; } - gerr("Returning EINVAL\n"); + lcderr("ERROR: Returning EINVAL\n"); return -EINVAL; } @@ -1166,27 +1162,27 @@ static int sam_base_putcmap(struct fb_vtable_s *vtable, static int sam_hcr_getcursor(struct fb_vtable_s *vtable, struct fb_cursorattrib_s *attrib) { - ginfo("vtable=%p attrib=%p\n", vtable, attrib); + lcdinfo("vtable=%p attrib=%p\n", vtable, attrib); if (vtable && attrib) { #ifdef CONFIG_FB_HWCURSORIMAGE attrib->fmt = SAMA5_HCR_COLOR_FMT; #endif - ginfo("pos: (x=%d, y=%d)\n", g_lcdc.cpos.x, g_lcdc.cpos.y); + lcdinfo("pos: (x=%d, y=%d)\n", g_lcdc.cpos.x, g_lcdc.cpos.y); attrib->pos = g_lcdc.cpos; #ifdef CONFIG_FB_HWCURSORSIZE attrib->mxsize.h = CONFIG_SAMA5_LCDC_HCR_HEIGHT; attrib->mxsize.w = CONFIG_SAMA5_LCDC_HCR_WIDTH; - ginfo("size: (h=%d, w=%d)\n", g_lcdc.csize.h, g_lcdc.csize.w); + lcdinfo("size: (h=%d, w=%d)\n", g_lcdc.csize.h, g_lcdc.csize.w); attrib->size = g_lcdc.csize; #endif return OK; } - gerr("Returning EINVAL\n"); + lcderr("ERROR: Returning EINVAL\n"); return -EINVAL; } #endif @@ -1199,26 +1195,26 @@ static int sam_hcr_getcursor(struct fb_vtable_s *vtable, static int sam_hcr_setcursor(struct fb_vtable_s *vtable, struct fb_setcursor_s *setttings) { - ginfo("vtable=%p setttings=%p\n", vtable, setttings); + lcdinfo("vtable=%p setttings=%p\n", vtable, setttings); if (vtable && setttings) { - ginfo("flags: %02x\n", settings->flags); + lcdinfo("flags: %02x\n", settings->flags); if ((flags & FB_CUR_SETPOSITION) != 0) { g_lcdc.cpos = settings->pos; - ginfo("pos: (h:%d, w:%d)\n", g_lcdc.cpos.x, g_lcdc.cpos.y); + lcdinfo("pos: (h:%d, w:%d)\n", g_lcdc.cpos.x, g_lcdc.cpos.y); } #ifdef CONFIG_FB_HWCURSORSIZE if ((flags & FB_CUR_SETSIZE) != 0) { g_lcdc.csize = settings->size; - ginfo("size: (h:%d, w:%d)\n", g_lcdc.csize.h, g_lcdc.csize.w); + lcdinfo("size: (h:%d, w:%d)\n", g_lcdc.csize.h, g_lcdc.csize.w); } #endif #ifdef CONFIG_FB_HWCURSORIMAGE if ((flags & FB_CUR_SETIMAGE) != 0) { - ginfo("image: (h:%d, w:%d) @ %p\n", + lcdinfo("image: (h:%d, w:%d) @ %p\n", settings->img.height, settings->img.width, settings->img.image); } @@ -1226,7 +1222,7 @@ static int sam_hcr_setcursor(struct fb_vtable_s *vtable, return OK; } - gerr("Returning EINVAL\n"); + lcderr("ERROR: Returning EINVAL\n"); return -EINVAL; } #endif @@ -1294,11 +1290,11 @@ static void sam_dmasetup(int lid, struct sam_dscr_s *dscr, uint8_t *buffer) #if defined(CONFIG_DEBUG_GRAPHICS) && defined(CONFIG_DEBUG_INFO) /* Dump the DMA setup */ - ginfo("DMA descriptor: addr=%08x ctrl=%08x next=%08x\n", - dscr->addr, dscr->ctrl, dscr->next); - ginfo("DMA registers[%d]: head=%08x addr=%08x ctrl=%08x next=%08x\n", - lid, sam_getreg(g_layerhead[lid]), sam_getreg(g_layeraddr[lid]), - sam_getreg(g_layerctrl[lid]), sam_getreg(g_layernext[lid])); + lcdinfo("DMA descriptor: addr=%08x ctrl=%08x next=%08x\n", + dscr->addr, dscr->ctrl, dscr->next); + lcdinfo("DMA registers[%d]: head=%08x addr=%08x ctrl=%08x next=%08x\n", + lid, sam_getreg(g_layerhead[lid]), sam_getreg(g_layeraddr[lid]), + sam_getreg(g_layerctrl[lid]), sam_getreg(g_layernext[lid])); #endif } @@ -1379,8 +1375,8 @@ static int sam_setclut(struct sam_layer_s *layer, unsigned int end; int i; - ginfo("layer=%d cmap=%p first=%d len=%d\n", - layer->lid, cmap, cmap->first, cmap->len); + lcdinfo("layer=%d cmap=%p first=%d len=%d\n", + layer->lid, cmap, cmap->first, cmap->len); DEBUGASSERT(layer && cmap); @@ -1391,7 +1387,7 @@ static int sam_setclut(struct sam_layer_s *layer, if (offset >= SAM_LCDC_NCLUT) { - gerr("ERROR: CLUT offset is out of range: %d\n", offset); + lcderr("ERROR: CLUT offset is out of range: %d\n", offset); return -EINVAL; } @@ -1460,7 +1456,7 @@ static int sam_getclut(struct sam_layer_s *layer, uintptr_t regval; int i; - ginfo("layer=%d cmap=%p first=%d len=%d\n", + lcdinfo("layer=%d cmap=%p first=%d len=%d\n", layer->lid, cmap, layer->offset, layer->nclut); DEBUGASSERT(layer && cmap); @@ -1514,7 +1510,7 @@ static void sam_pio_config(void) { int i; - ginfo("Configuring pins\n"); + lcdinfo("Configuring pins\n"); /* Configure each pin */ @@ -2915,7 +2911,7 @@ int up_fbinitialize(int display) uint32_t regval; #endif - ginfo("Entry\n"); + lcdinfo("Entry\n"); /* Configure layer layer structures, DMA descriptor memory, and * framebuffers @@ -2931,7 +2927,7 @@ int up_fbinitialize(int display) sam_pio_config(); - ginfo("Configuring the LCD controller\n"); + lcdinfo("Configuring the LCD controller\n"); /* Enable the LCD peripheral clock */ @@ -2959,7 +2955,7 @@ int up_fbinitialize(int display) /* And turn the LCD on */ - ginfo("Enabling the display\n"); + lcdinfo("Enabling the display\n"); sam_lcd_enable(); /* Display base layer */ @@ -3012,7 +3008,7 @@ int up_fbinitialize(int display) FAR struct fb_vtable_s *up_fbgetvplane(int display, int vplane) { - ginfo("vplane: %d\n", vplane); + lcdinfo("vplane: %d\n", vplane); if (vplane == 0) { return (struct fb_vtable_s *)&g_base_vtable; @@ -3062,8 +3058,8 @@ void sam_lcdclear(nxgl_mxpixel_t color) uint16_t *dest = (uint16_t *)LAYER_BASE.framebuffer; int i; - ginfo("Clearing display: BPP=16 color=%04x framebuffer=%08x size=%d\n", - color, LAYER_BASE.framebuffer, SAMA5_BASE_FBSIZE); + lcdinfo("Clearing display: BPP=16 color=%04x framebuffer=%08x size=%d\n", + color, LAYER_BASE.framebuffer, SAMA5_BASE_FBSIZE); for (i = 0; i < SAMA5_BASE_FBSIZE; i += sizeof(uint16_t)) { @@ -3076,8 +3072,8 @@ void sam_lcdclear(nxgl_mxpixel_t color) uint8_t b; int i; - ginfo("Clearing display: BPP=24 color=%06x framebuffer=%08x size=%d\n", - color, LAYER_BASE.framebuffer, SAMA5_BASE_FBSIZE); + lcdinfo("Clearing display: BPP=24 color=%06x framebuffer=%08x size=%d\n", + color, LAYER_BASE.framebuffer, SAMA5_BASE_FBSIZE); b = color & 0xff; g = (color >> 8) & 0xff; @@ -3093,8 +3089,8 @@ void sam_lcdclear(nxgl_mxpixel_t color) uint32_t *dest = (uint32_t *)LAYER_BASE.framebuffer; int i; - ginfo("Clearing display: BPP=32 color=%08x framebuffer=%08x size=%d\n", - color, LAYER_BASE.framebuffer, SAMA5_BASE_FBSIZE); + lcdinfo("Clearing display: BPP=32 color=%08x framebuffer=%08x size=%d\n", + color, LAYER_BASE.framebuffer, SAMA5_BASE_FBSIZE); for (i = 0; i < SAMA5_BASE_FBSIZE; i += sizeof(uint32_t)) { diff --git a/arch/arm/src/sama5/sam_memories.c b/arch/arm/src/sama5/sam_memories.c index 6588309b88..54c8e65b56 100644 --- a/arch/arm/src/sama5/sam_memories.c +++ b/arch/arm/src/sama5/sam_memories.c @@ -766,7 +766,7 @@ uintptr_t sam_physregaddr(uintptr_t virtregaddr) * address */ - _err("Bad virtual address: %08lx\n", virtregaddr); + serr("ERROR: Bad virtual address: %08lx\n", virtregaddr); DEBUGPANIC(); return virtregaddr; } @@ -925,7 +925,7 @@ uintptr_t sam_physramaddr(uintptr_t virtramaddr) if (virtramaddr != 0) { - _err("Bad virtual address: %08lx\n", virtramaddr); + serr("ERROR: Bad virtual address: %08lx\n", virtramaddr); DEBUGPANIC(); } @@ -1058,7 +1058,7 @@ uintptr_t sam_virtramaddr(uintptr_t physramaddr) if (physramaddr != 0) { - _err("Bad physical address: %08lx\n|", physramaddr); + serr("ERROR: Bad physical address: %08lx\n|", physramaddr); DEBUGPANIC(); } diff --git a/arch/arm/src/sama5/sam_nand.c b/arch/arm/src/sama5/sam_nand.c index 6cb56fea97..f063f22fb2 100644 --- a/arch/arm/src/sama5/sam_nand.c +++ b/arch/arm/src/sama5/sam_nand.c @@ -1163,7 +1163,7 @@ static void nand_dma_sampleinit(struct sam_nandcs_s *priv) #ifdef CONFIG_SAMA5_NAND_DMADEBUG static void nand_dma_sampledone(struct sam_nandcs_s *priv, int result) { - _llerr("result: %d\n", result); + finfo("result: %d\n", result); /* Sample the final registers */ @@ -2098,7 +2098,7 @@ static int nand_readpage_pmecc(struct sam_nandcs_s *priv, off_t block, { /* Yes.. clear sector errors */ - ferr("Block=%d page=%d has been erased: %08x\n", + finfo("Block=%d page=%d has been erased: %08x\n", block, page, regval); regval = 0; } @@ -2983,7 +2983,7 @@ struct mtd_dev_s *sam_nand_initialize(int cs) ret = irq_attach(SAM_IRQ_HSMC, hsmc_interrupt); if (ret < 0) { - ferr("Failed to attach HSMC IRQ (%d)", SAM_IRQ_HSMC); + ferr("ERROR: Failed to attach HSMC IRQ (%d)", SAM_IRQ_HSMC); return NULL; } #endif @@ -3088,7 +3088,7 @@ bool nand_checkreg(bool wr, uintptr_t regaddr, uint32_t regval) { /* Yes... show how many times we did it */ - _llerr("...[Repeats %d times]...\n", g_nand.ntimes); + finfo("...[Repeats %d times]...\n", g_nand.ntimes); } /* Save information about the new access */ diff --git a/arch/arm/src/sama5/sam_nand.h b/arch/arm/src/sama5/sam_nand.h index 81e6cb8003..808b719aa5 100644 --- a/arch/arm/src/sama5/sam_nand.h +++ b/arch/arm/src/sama5/sam_nand.h @@ -259,14 +259,13 @@ /* Debug */ -#if !defined(CONFIG_DEBUG_FEATURES) || !defined(CONFIG_DEBUG_FS) -# undef CONFIG_DEBUG_FS +#ifndef defined(CONFIG_DEBUG_FS_INFO # undef CONFIG_SAMA5_NAND_DMADEBUG # undef CONFIG_SAMA5_NAND_REGDEBUG # undef CONFIG_SAMA5_NAND_DUMP #endif -#if !defined(CONFIG_SAMA5_NAND_DMA) || !defined(CONFIG_DEBUG_DMA) +#if !defined(CONFIG_SAMA5_NAND_DMA) || !defined(CONFIG_DEBUG_DMA_INFO) # undef CONFIG_SAMA5_NAND_DMADEBUG #endif @@ -518,7 +517,7 @@ static inline uint32_t nand_getreg(uintptr_t regaddr) #ifdef CONFIG_SAMA5_NAND_REGDEBUG if (nand_checkreg(false, regaddr, regval)) { - _llerr("%08x->%08x\n", regaddr, regval); + sinfo("%08x->%08x\n", regaddr, regval); } #endif @@ -538,7 +537,7 @@ static inline void nand_putreg(uintptr_t regaddr, uint32_t regval) #ifdef CONFIG_SAMA5_NAND_REGDEBUG if (nand_checkreg(true, regaddr, regval)) { - _llerr("%08x<-%08x\n", regaddr, regval); + sinfo("%08x<-%08x\n", regaddr, regval); } #endif diff --git a/arch/arm/src/sama5/sam_ohci.c b/arch/arm/src/sama5/sam_ohci.c index 76899223c6..bd3ec0b233 100644 --- a/arch/arm/src/sama5/sam_ohci.c +++ b/arch/arm/src/sama5/sam_ohci.c @@ -151,7 +151,7 @@ /* Debug */ -#ifndef CONFIG_DEBUG_FEATURES +#ifndef CONFIG_DEBUG_USB_INFO # undef CONFIG_SAMA5_OHCI_REGDEBUG #endif @@ -505,10 +505,6 @@ static struct sam_gtd_s g_tdalloc[SAMA5_OHCI_NTDS] static uint8_t g_bufalloc[SAM_BUFALLOC] __attribute__ ((aligned (SAMA5_DMA_ALIGN))); -/**************************************************************************** - * Public Data - ****************************************************************************/ - /**************************************************************************** * Private Functions ****************************************************************************/ @@ -524,7 +520,7 @@ static uint8_t g_bufalloc[SAM_BUFALLOC] #ifdef CONFIG_SAMA5_OHCI_REGDEBUG static void sam_printreg(uint32_t addr, uint32_t val, bool iswrite) { - _llerr("%08x%s%08x\n", addr, iswrite ? "<-" : "->", val); + uinfo("%08x%s%08x\n", addr, iswrite ? "<-" : "->", val); } #endif @@ -574,7 +570,7 @@ static void sam_checkreg(uint32_t addr, uint32_t val, bool iswrite) { /* No.. More than one. */ - _llerr("[repeats %d more times]\n", count); + uinfo("[repeats %d more times]\n", count); } } diff --git a/arch/arm/src/sama5/sam_pmecc.c b/arch/arm/src/sama5/sam_pmecc.c index d055d0b6b3..0339068c4f 100644 --- a/arch/arm/src/sama5/sam_pmecc.c +++ b/arch/arm/src/sama5/sam_pmecc.c @@ -632,7 +632,7 @@ static uint32_t pmecc_errorcorrection(uintptr_t sectorbase, if (bytepos < sectorsz + nand_getreg(SAM_HSMC_PMECCSADDR)) { - ferr("Correct error bit @[Byte %d, Bit %d]\n", + fwarn("WARNING: Correct error bit @[Byte %d, Bit %d]\n", (int)bytepos, (int)bitpos); if (*(uint8_t *)(sectorbase + bytepos) & (1 << bitpos)) @@ -870,7 +870,7 @@ static int pmecc_pagelayout(uint16_t datasize, uint16_t eccsize) bcherr512 = pmecc_bcherr512(nsectors512, eccsize); if (bcherr512 < 0) { - ferr("WARNING: Cannot realize 512B sectors\n"); + fwarn("WARNING: Cannot realize 512B sectors\n"); } else { @@ -895,7 +895,7 @@ static int pmecc_pagelayout(uint16_t datasize, uint16_t eccsize) if (bcherr1k < 0) { - ferr("WARNING: Cannot realize 1KB sectors\n"); + fwarn("WARNING: Cannot realize 1KB sectors\n"); } else { diff --git a/arch/arm/src/sama5/sam_pwm.c b/arch/arm/src/sama5/sam_pwm.c index 4aac3affa8..0de1d91dea 100644 --- a/arch/arm/src/sama5/sam_pwm.c +++ b/arch/arm/src/sama5/sam_pwm.c @@ -65,6 +65,11 @@ * Pre-processor Definitions ****************************************************************************/ /* Configuration ************************************************************/ + +#ifndef CONFIG_DEBUG_PWM_INFO +# undef CONFIG_SAMA5_PWM_REGDEBUG +#endif + /* Currently, we support only a single PWM peripheral. However, the hooks * are in place to support multiple PWM peripherals. */ @@ -689,7 +694,7 @@ static bool pwm_checkreg(FAR struct sam_pwm_s *pwm, bool wr, uint32_t regval, { /* Yes... show how many times we did it */ - _llerr("...[Repeats %d times]...\n", pwm->count); + pwminfo("...[Repeats %d times]...\n", pwm->count); } /* Save information about the new access */ @@ -733,7 +738,7 @@ static uint32_t pwm_getreg(struct sam_pwm_chan_s *chan, int offset) #ifdef CONFIG_SAMA5_PWM_REGDEBUG if (pwm_checkreg(&g_pwm, false, regval, regaddr)) { - _llerr("%08x->%08x\n", regaddr, regval); + pwminfo("%08x->%08x\n", regaddr, regval); } #endif @@ -750,7 +755,7 @@ static uint32_t pwm_getreg(struct sam_pwm_chan_s *chan, int offset) #ifdef CONFIG_SAMA5_PWM_REGDEBUG if (pwm_checkreg(pwm, false, regval, regaddr)) { - _llerr("%08x->%08x\n", regaddr, regval); + pwminfo("%08x->%08x\n", regaddr, regval); } #endif @@ -789,7 +794,7 @@ static uint32_t pwm_chan_getreg(struct sam_pwm_chan_s *chan, int offset) if (pwm_checkreg(chan->pwm, false, regval, regaddr)) #endif { - _llerr("%08x->%08x\n", regaddr, regval); + pwminfo("%08x->%08x\n", regaddr, regval); } #endif @@ -820,7 +825,7 @@ static void pwm_putreg(struct sam_pwm_chan_s *chan, int offset, #ifdef CONFIG_SAMA5_PWM_REGDEBUG if (pwm_checkreg(&g_pwm, true, regval, regaddr)) { - _llerr("%08x<-%08x\n", regaddr, regval); + pwminfo("%08x<-%08x\n", regaddr, regval); } #endif @@ -833,7 +838,7 @@ static void pwm_putreg(struct sam_pwm_chan_s *chan, int offset, #ifdef CONFIG_SAMA5_PWM_REGDEBUG if (pwm_checkreg(pwm, true, regval, regaddr)) { - _llerr("%08x<-%08x\n", regaddr, regval); + pwminfo("%08x<-%08x\n", regaddr, regval); } #endif @@ -869,7 +874,7 @@ static void pwm_chan_putreg(struct sam_pwm_chan_s *chan, int offset, if (pwm_checkreg(chan->pwm, true, regval, regaddr)) #endif { - _llerr("%08x<-%08x\n", regaddr, regval); + pwminfo("%08x<-%08x\n", regaddr, regval); } #endif diff --git a/arch/arm/src/sama5/sam_rtc.c b/arch/arm/src/sama5/sam_rtc.c index 16c4a4f295..d710ff711f 100644 --- a/arch/arm/src/sama5/sam_rtc.c +++ b/arch/arm/src/sama5/sam_rtc.c @@ -265,7 +265,7 @@ static int rtc_interrupt(int irq, void *context) ret = work_queue(LPWORK, &g_alarmwork, rtc_worker, NULL, 0); if (ret < 0) { - rtcllerr("ERRPR: work_queue failed: %d\n", ret); + rtcllerr("ERROR: work_queue failed: %d\n", ret); } /* Disable any further alarm interrupts */ diff --git a/arch/arm/src/sama5/sam_spi.c b/arch/arm/src/sama5/sam_spi.c index 33cd3cb93e..0386fcc681 100644 --- a/arch/arm/src/sama5/sam_spi.c +++ b/arch/arm/src/sama5/sam_spi.c @@ -90,6 +90,10 @@ # define CONFIG_SAMA5_SPI_DMATHRESHOLD 4 #endif +#ifndef CONFIG_DEBUG_SPI_INFO +# undef CONFIG_SAMA5_SPI_REGDEBUG +#endif + #ifdef CONFIG_SAMA5_SPI_DMA # if defined(CONFIG_SAMA5_SPI0) && defined(CONFIG_SAMA5_DMAC0) @@ -409,7 +413,7 @@ static bool spi_checkreg(struct sam_spidev_s *spi, bool wr, uint32_t value, { /* Yes... show how many times we did it */ - _llerr("...[Repeats %d times]...\n", spi->ntimes); + spiinfo("...[Repeats %d times]...\n", spi->ntimes); } /* Save information about the new access */ @@ -443,7 +447,7 @@ static inline uint32_t spi_getreg(struct sam_spidev_s *spi, #ifdef CONFIG_SAMA5_SPI_REGDEBUG if (spi_checkreg(spi, false, value, address)) { - _llerr("%08x->%08x\n", address, value); + spiinfo("%08x->%08x\n", address, value); } #endif @@ -466,7 +470,7 @@ static inline void spi_putreg(struct sam_spidev_s *spi, uint32_t value, #ifdef CONFIG_SAMA5_SPI_REGDEBUG if (spi_checkreg(spi, true, value, address)) { - _llerr("%08x<-%08x\n", address, value); + spiinfo("%08x<-%08x\n", address, value); } #endif @@ -1044,7 +1048,7 @@ static uint32_t spi_setfrequency(struct spi_dev_s *dev, uint32_t frequency) spics->frequency = frequency; spics->actual = actual; - spierr("Frequency %d->%d\n", frequency, actual); + spiinfo("Frequency %d->%d\n", frequency, actual); return actual; } diff --git a/arch/arm/src/sama5/sam_ssc.c b/arch/arm/src/sama5/sam_ssc.c index 46c564b66e..ff50c3988e 100644 --- a/arch/arm/src/sama5/sam_ssc.c +++ b/arch/arm/src/sama5/sam_ssc.c @@ -703,7 +703,7 @@ static bool ssc_checkreg(struct sam_ssc_s *priv, bool wr, uint32_t regval, { /* Yes... show how many times we did it */ - _llerr("...[Repeats %d times]...\n", priv->count); + i2sinfo("...[Repeats %d times]...\n", priv->count); } /* Save information about the new access */ @@ -737,7 +737,7 @@ static inline uint32_t ssc_getreg(struct sam_ssc_s *priv, #ifdef CONFIG_SAMA5_SSC_REGDEBUG if (ssc_checkreg(priv, false, regval, regaddr)) { - _llerr("%08x->%08x\n", regaddr, regval); + i2sinfo("%08x->%08x\n", regaddr, regval); } #endif @@ -760,7 +760,7 @@ static inline void ssc_putreg(struct sam_ssc_s *priv, unsigned int offset, #ifdef CONFIG_SAMA5_SSC_REGDEBUG if (ssc_checkreg(priv, true, regval, regaddr)) { - _llerr("%08x<-%08x\n", regaddr, regval); + i2sinfo("%08x<-%08x\n", regaddr, regval); } #endif @@ -1090,7 +1090,7 @@ static void ssc_dma_sampleinit(struct sam_ssc_s *priv, #if defined(CONFIG_SAMA5_SSC_DMADEBUG) && defined(SSC_HAVE_RX) static void ssc_rxdma_sampledone(struct sam_ssc_s *priv, int result) { - _llerr("result: %d\n", result); + i2sinfo("result: %d\n", result); /* Sample the final registers */ @@ -1155,7 +1155,7 @@ static void ssc_rxdma_sampledone(struct sam_ssc_s *priv, int result) #if defined(CONFIG_SAMA5_SSC_DMADEBUG) && defined(SSC_HAVE_TX) static void ssc_txdma_sampledone(struct sam_ssc_s *priv, int result) { - _llerr("result: %d\n", result); + i2sinfo("result: %d\n", result); /* Sample the final registers */ diff --git a/arch/arm/src/sama5/sam_tc.c b/arch/arm/src/sama5/sam_tc.c index 9ea38a333d..fc0bc9c876 100644 --- a/arch/arm/src/sama5/sam_tc.c +++ b/arch/arm/src/sama5/sam_tc.c @@ -75,6 +75,10 @@ * Pre-processor Definitions ****************************************************************************/ +#ifndef CONFIG_DEBUG_TIMER_INFO +# undef CONFIG_SAMA5_TC_REGDEBUG +#endif + /**************************************************************************** * Private Types ****************************************************************************/ @@ -501,20 +505,20 @@ static void sam_regdump(struct sam_chan_s *chan, const char *msg) uintptr_t base; base = tc->base; - _llerr("TC%d [%08x]: %s\n", tc->tc, (int)base, msg); - _llerr(" BMR: %08x QIMR: %08x QISR: %08x WPMR: %08x\n", + tminfo("TC%d [%08x]: %s\n", tc->tc, (int)base, msg); + tminfo(" BMR: %08x QIMR: %08x QISR: %08x WPMR: %08x\n", getreg32(base+SAM_TC_BMR_OFFSET), getreg32(base+SAM_TC_QIMR_OFFSET), getreg32(base+SAM_TC_QISR_OFFSET), getreg32(base+SAM_TC_WPMR_OFFSET)); base = chan->base; - _llerr("TC%d Channel %d [%08x]: %s\n", tc->tc, chan->chan, (int)base, msg); - _llerr(" CMR: %08x SSMR: %08x RAB: %08x CV: %08x\n", + tminfo("TC%d Channel %d [%08x]: %s\n", tc->tc, chan->chan, (int)base, msg); + tminfo(" CMR: %08x SSMR: %08x RAB: %08x CV: %08x\n", getreg32(base+SAM_TC_CMR_OFFSET), getreg32(base+SAM_TC_SMMR_OFFSET), getreg32(base+SAM_TC_RAB_OFFSET), getreg32(base+SAM_TC_CV_OFFSET)); - _llerr(" RA: %08x RB: %08x RC: %08x SR: %08x\n", + tminfo(" RA: %08x RB: %08x RC: %08x SR: %08x\n", getreg32(base+SAM_TC_RA_OFFSET), getreg32(base+SAM_TC_RB_OFFSET), getreg32(base+SAM_TC_RC_OFFSET), getreg32(base+SAM_TC_SR_OFFSET)); - _llerr(" IMR: %08x\n", + tminfo(" IMR: %08x\n", getreg32(base+SAM_TC_IMR_OFFSET)); } #endif @@ -558,7 +562,7 @@ static bool sam_checkreg(struct sam_tc_s *tc, bool wr, uint32_t regaddr, { /* Yes... show how many times we did it */ - _llerr("...[Repeats %d times]...\n", tc->ntimes); + tminfo("...[Repeats %d times]...\n", tc->ntimes); } /* Save information about the new access */ @@ -593,7 +597,7 @@ static inline uint32_t sam_tc_getreg(struct sam_chan_s *chan, #ifdef CONFIG_SAMA5_TC_REGDEBUG if (sam_checkreg(tc, false, regaddr, regval)) { - _llerr("%08x->%08x\n", regaddr, regval); + tminfo("%08x->%08x\n", regaddr, regval); } #endif @@ -617,7 +621,7 @@ static inline void sam_tc_putreg(struct sam_chan_s *chan, uint32_t regval, #ifdef CONFIG_SAMA5_TC_REGDEBUG if (sam_checkreg(tc, true, regaddr, regval)) { - _llerr("%08x<-%08x\n", regaddr, regval); + tminfo("%08x<-%08x\n", regaddr, regval); } #endif @@ -641,7 +645,7 @@ static inline uint32_t sam_chan_getreg(struct sam_chan_s *chan, #ifdef CONFIG_SAMA5_TC_REGDEBUG if (sam_checkreg(chan->tc, false, regaddr, regval)) { - _llerr("%08x->%08x\n", regaddr, regval); + tminfo("%08x->%08x\n", regaddr, regval); } #endif @@ -664,7 +668,7 @@ static inline void sam_chan_putreg(struct sam_chan_s *chan, unsigned int offset, #ifdef CONFIG_SAMA5_TC_REGDEBUG if (sam_checkreg(chan->tc, true, regaddr, regval)) { - _llerr("%08x<-%08x\n", regaddr, regval); + tminfo("%08x<-%08x\n", regaddr, regval); } #endif diff --git a/arch/arm/src/sama5/sam_tsd.c b/arch/arm/src/sama5/sam_tsd.c index de28c0a953..9961cbee74 100644 --- a/arch/arm/src/sama5/sam_tsd.c +++ b/arch/arm/src/sama5/sam_tsd.c @@ -644,7 +644,7 @@ static void sam_tsd_bottomhalf(void *arg) if (xraw == 0 || xraw >= xscale || yraw == 0 || yraw > yscale) { - ierr("Discarding: x %d:%d y %d:%d\n", xraw, xscale); + iwarn("WARNING: Discarding: x %d:%d y %d:%d\n", xraw, xscale); goto ignored; } @@ -799,7 +799,7 @@ static int sam_tsd_schedule(struct sam_tsd_s *priv) ret = work_queue(HPWORK, &priv->work, sam_tsd_bottomhalf, priv, 0); if (ret != 0) { - illerr("Failed to queue work: %d\n", ret); + illerr("ERROR: Failed to queue work: %d\n", ret); } return OK; diff --git a/arch/arm/src/sama5/sam_twi.c b/arch/arm/src/sama5/sam_twi.c index 095fb7e895..a15ec4e1b1 100644 --- a/arch/arm/src/sama5/sam_twi.c +++ b/arch/arm/src/sama5/sam_twi.c @@ -95,6 +95,10 @@ # define CONFIG_SAMA5_TWI3_FREQUENCY 100000 #endif +#ifndef CONFIG_DEBUG_I2C_INFO +# undef CONFIG_SAMA5_TWI_REGDEBUG +#endif + /* Driver internal definitions *************************************************/ /* If verbose I2C debug output is enabled, then allow more time before we declare * a timeout. The debug output from twi_interrupt will really slow things down! @@ -369,7 +373,7 @@ static bool twi_checkreg(struct twi_dev_s *priv, bool wr, uint32_t value, { /* Yes... show how many times we did it */ - _llerr("...[Repeats %d times]...\n", priv->ntimes); + i2cinfo("...[Repeats %d times]...\n", priv->ntimes); } /* Save information about the new access */ @@ -401,7 +405,7 @@ static uint32_t twi_getabs(struct twi_dev_s *priv, uintptr_t address) if (twi_checkreg(priv, false, value, address)) { - _llerr("%08x->%08x\n", address, value); + i2cinfo("%08x->%08x\n", address, value); } return value; @@ -422,7 +426,7 @@ static void twi_putabs(struct twi_dev_s *priv, uintptr_t address, { if (twi_checkreg(priv, true, value, address)) { - _llerr("%08x<-%08x\n", address, value); + i2cinfo("%08x<-%08x\n", address, value); } putreg32(value, address); diff --git a/arch/arm/src/sama5/sam_udphs.c b/arch/arm/src/sama5/sam_udphs.c index a5dba4368d..b7e4b60357 100644 --- a/arch/arm/src/sama5/sam_udphs.c +++ b/arch/arm/src/sama5/sam_udphs.c @@ -91,11 +91,7 @@ # define CONFIG_SAMA5_UDPHS_NDTDS 8 #endif -/* Extremely detailed register debug that you would normally never want - * enabled. - */ - -#ifndef CONFIG_DEBUG_FEATURES +#ifdef CONFIG_DEBUG_USB_INFO # undef CONFIG_SAMA5_UDPHS_REGDEBUG #endif @@ -671,7 +667,7 @@ const struct trace_msg_t g_usb_trace_strings_intdecode[] = #ifdef CONFIG_SAMA5_UDPHS_REGDEBUG static void sam_printreg(uintptr_t regaddr, uint32_t regval, bool iswrite) { - _llerr("%p%s%08x\n", regaddr, iswrite ? "<-" : "->", regval); + uinfo("%p%s%08x\n", regaddr, iswrite ? "<-" : "->", regval); } #endif @@ -722,7 +718,7 @@ static void sam_checkreg(uintptr_t regaddr, uint32_t regval, bool iswrite) { /* No.. More than one. */ - _llerr("[repeats %d more times]\n", count); + uinfo("[repeats %d more times]\n", count); } } @@ -802,31 +798,31 @@ static void sam_dumpep(struct sam_usbdev_s *priv, int epno) { /* Global Registers */ - _llerr("Global Register:\n"); - _llerr(" CTRL: %04x\n", sam_getreg(SAM_UDPHS_CTRL)); - _llerr(" FNUM: %04x\n", sam_getreg(SAM_UDPHS_FNUM)); - _llerr(" IEN: %04x\n", sam_getreg(SAM_UDPHS_IEN)); - _llerr(" INSTA: %04x\n", sam_getreg(SAM_UDPHS_INTSTA)); - _llerr(" TST: %04x\n", sam_getreg(SAM_UDPHS_TST)); + uinfo("Global Register:\n"); + uinfo(" CTRL: %04x\n", sam_getreg(SAM_UDPHS_CTRL)); + uinfo(" FNUM: %04x\n", sam_getreg(SAM_UDPHS_FNUM)); + uinfo(" IEN: %04x\n", sam_getreg(SAM_UDPHS_IEN)); + uinfo(" INSTA: %04x\n", sam_getreg(SAM_UDPHS_INTSTA)); + uinfo(" TST: %04x\n", sam_getreg(SAM_UDPHS_TST)); /* Endpoint registers */ - _llerr("Endpoint %d Register:\n", epno); - _llerr(" CFG: %04x\n", sam_getreg(SAM_UDPHS_EPTCFG(epno))); - _llerr(" CTL: %04x\n", sam_getreg(SAM_UDPHS_EPTCTL(epno))); - _llerr(" STA: %04x\n", sam_getreg(SAM_UDPHS_EPTSTA(epno))); + uinfo("Endpoint %d Register:\n", epno); + uinfo(" CFG: %04x\n", sam_getreg(SAM_UDPHS_EPTCFG(epno))); + uinfo(" CTL: %04x\n", sam_getreg(SAM_UDPHS_EPTCTL(epno))); + uinfo(" STA: %04x\n", sam_getreg(SAM_UDPHS_EPTSTA(epno))); - _llerr("DMA %d Register:\n", epno); + uinfo("DMA %d Register:\n", epno); if ((SAM_EPSET_DMA & SAM_EP_BIT(epno)) != 0) { - _llerr(" NXTDSC: %04x\n", sam_getreg(SAM_UDPHS_DMANXTDSC(epno))); - _llerr(" ADDRESS: %04x\n", sam_getreg(SAM_UDPHS_DMAADDRESS(epno))); - _llerr(" CONTROL: %04x\n", sam_getreg(SAM_UDPHS_DMACONTROL(epno))); - _llerr(" STATUS: %04x\n", sam_getreg(SAM_UDPHS_DMASTATUS(epno))); + uinfo(" NXTDSC: %04x\n", sam_getreg(SAM_UDPHS_DMANXTDSC(epno))); + uinfo(" ADDRESS: %04x\n", sam_getreg(SAM_UDPHS_DMAADDRESS(epno))); + uinfo(" CONTROL: %04x\n", sam_getreg(SAM_UDPHS_DMACONTROL(epno))); + uinfo(" STATUS: %04x\n", sam_getreg(SAM_UDPHS_DMASTATUS(epno))); } else { - _llerr(" None\n"); + uinfo(" None\n"); } } #endif diff --git a/arch/arm/src/sama5/sam_wdt.c b/arch/arm/src/sama5/sam_wdt.c index aa16905888..26f40860b7 100644 --- a/arch/arm/src/sama5/sam_wdt.c +++ b/arch/arm/src/sama5/sam_wdt.c @@ -57,6 +57,11 @@ * Pre-processor Definitions ****************************************************************************/ /* Configuration ************************************************************/ + +#ifndef CONFIG_DEBUG_WATCHDOG_INFO +# undef CONFIG_SAMA5_WDT_REGDEBUG +#endif + /* The Watchdog Timer uses the Slow Clock divided by 128 to establish the * maximum Watchdog period to be 16 seconds (with a typical Slow Clock of * 32768 kHz). @@ -104,7 +109,7 @@ struct sam_lowerhalf_s ****************************************************************************/ /* Register operations ******************************************************/ -#if defined(CONFIG_SAMA5_WDT_REGDEBUG) && defined(CONFIG_DEBUG_FEATURES) +#ifdef CONFIG_SAMA5_WDT_REGDEBUG static uint32_t sam_getreg(uintptr_t regaddr); static void sam_putreg(uint32_t regval, uintptr_t regaddr); #else @@ -164,7 +169,7 @@ static struct sam_lowerhalf_s g_wdtdev; * ****************************************************************************/ -#if defined(CONFIG_SAMA5_WDT_REGDEBUG) && defined(CONFIG_DEBUG_FEATURES) +#ifdef CONFIG_SAMA5_WDT_REGDEBUG static uint32_t sam_getreg(uintptr_t regaddr) { static uint32_t prevaddr = 0; @@ -185,7 +190,7 @@ static uint32_t sam_getreg(uintptr_t regaddr) { if (count == 4) { - _llerr("...\n"); + wdinfo("...\n"); } return regval; @@ -202,7 +207,7 @@ static uint32_t sam_getreg(uintptr_t regaddr) { /* Yes.. then show how many times the value repeated */ - _llerr("[repeats %d more times]\n", count-3); + wdinfo("[repeats %d more times]\n", count-3); } /* Save the new address, value, and count */ @@ -214,7 +219,7 @@ static uint32_t sam_getreg(uintptr_t regaddr) /* Show the register value read */ - _llerr("%08x->%048\n", regaddr, regval); + wdinfo("%08x->%048\n", regaddr, regval); return regval; } #endif @@ -227,12 +232,12 @@ static uint32_t sam_getreg(uintptr_t regaddr) * ****************************************************************************/ -#if defined(CONFIG_SAMA5_WDT_REGDEBUG) && defined(CONFIG_DEBUG_FEATURES) +#ifdef CONFIG_SAMA5_WDT_REGDEBUG static void sam_putreg(uint32_t regval, uintptr_t regaddr) { /* Show the register value being written */ - _llerr("%08x<-%08x\n", regaddr, regval); + wdinfo("%08x<-%08x\n", regaddr, regval); /* Write the value */ @@ -449,7 +454,7 @@ static int sam_settimeout(FAR struct watchdog_lowerhalf_s *lower, if (timeout < WDT_MINTIMEOUT || timeout >= WDT_MAXTIMEOUT) { - wderr("Cannot represent timeout: %d < %d > %d\n", + wderr("ERROR: Cannot represent timeout: %d < %d > %d\n", WDT_MINTIMEOUT, timeout, WDT_MAXTIMEOUT); return -ERANGE; } diff --git a/arch/arm/src/sama5/sam_xdmac.c b/arch/arm/src/sama5/sam_xdmac.c index 48a69a16e3..ef7238a209 100644 --- a/arch/arm/src/sama5/sam_xdmac.c +++ b/arch/arm/src/sama5/sam_xdmac.c @@ -807,7 +807,7 @@ static uint8_t sam_channel(uint8_t pid, const struct sam_pidmap_s *table, } } - dmaerr("No channel found for pid %d\n", pid); + dmaerr("ERROR: No channel found for pid %d\n", pid); DEBUGPANIC(); return 0x3f; } @@ -2403,7 +2403,7 @@ void sam_dmastop(DMA_HANDLE handle) * ****************************************************************************/ -#ifdef CONFIG_DEBUG_DMA +#ifdef CONFIG_DEBUG_DMA_INFO void sam_dmasample(DMA_HANDLE handle, struct sam_dmaregs_s *regs) { struct sam_xdmach_s *xdmach = (struct sam_xdmach_s *)handle; @@ -2445,7 +2445,7 @@ void sam_dmasample(DMA_HANDLE handle, struct sam_dmaregs_s *regs) leave_critical_section(flags); } -#endif /* CONFIG_DEBUG_DMA */ +#endif /* CONFIG_DEBUG_DMA_INFO */ /**************************************************************************** * Name: sam_dmadump @@ -2458,37 +2458,37 @@ void sam_dmasample(DMA_HANDLE handle, struct sam_dmaregs_s *regs) * ****************************************************************************/ -#ifdef CONFIG_DEBUG_DMA +#ifdef CONFIG_DEBUG_DMA_INFO void sam_dmadump(DMA_HANDLE handle, const struct sam_dmaregs_s *regs, const char *msg) { struct sam_xdmach_s *xdmach = (struct sam_xdmach_s *)handle; struct sam_xdmac_s *xdmac = sam_controller(xdmach); - dmaerr("%s\n", msg); - dmaerr(" DMA Global Registers:\n"); - dmaerr(" GTYPE[%08x]: %08x\n", xdmac->base + SAM_XDMAC_GTYPE_OFFSET, regs->gtype); - dmaerr(" GCFG[%08x]: %08x\n", xdmac->base + SAM_XDMAC_GCFG_OFFSET, regs->gcfg); - dmaerr(" GWAC[%08x]: %08x\n", xdmac->base + SAM_XDMAC_GWAC_OFFSET, regs->gwac); - dmaerr(" GIM[%08x]: %08x\n", xdmac->base + SAM_XDMAC_GIM_OFFSET, regs->gim); - dmaerr(" GIS[%08x]: %08x\n", xdmac->base + SAM_XDMAC_GIS_OFFSET, regs->gis); - dmaerr(" GS[%08x]: %08x\n", xdmac->base + SAM_XDMAC_GS_OFFSET, regs->gs); - dmaerr(" GRS[%08x]: %08x\n", xdmac->base + SAM_XDMAC_GRS_OFFSET, regs->grs); - dmaerr(" GWS[%08x]: %08x\n", xdmac->base + SAM_XDMAC_GWS_OFFSET, regs->gws); - dmaerr(" GSWS[%08x]: %08x\n", xdmac->base + SAM_XDMAC_GSWS_OFFSET, regs->gsws); - dmaerr(" DMA Channel Registers:\n"); - dmaerr(" CIM[%08x]: %08x\n", xdmach->base + SAM_XDMACH_CIM_OFFSET, regs->cim); - dmaerr(" CIS[%08x]: %08x\n", xdmach->base + SAM_XDMACH_CIS_OFFSET, regs->cis); - dmaerr(" CSA[%08x]: %08x\n", xdmach->base + SAM_XDMACH_CSA_OFFSET, regs->csa); - dmaerr(" CDA[%08x]: %08x\n", xdmach->base + SAM_XDMACH_CDA_OFFSET, regs->cda); - dmaerr(" CNDA[%08x]: %08x\n", xdmach->base + SAM_XDMACH_CNDA_OFFSET, regs->cnda); - dmaerr(" CNDC[%08x]: %08x\n", xdmach->base + SAM_XDMACH_CNDC_OFFSET, regs->cndc); - dmaerr(" CUBC[%08x]: %08x\n", xdmach->base + SAM_XDMACH_CUBC_OFFSET, regs->cubc); - dmaerr(" CBC[%08x]: %08x\n", xdmach->base + SAM_XDMACH_CBC_OFFSET, regs->cbc); - dmaerr(" CC[%08x]: %08x\n", xdmach->base + SAM_XDMACH_CC_OFFSET, regs->cc); - dmaerr(" CDSMSP[%08x]: %08x\n", xdmach->base + SAM_XDMACH_CDSMSP_OFFSET, regs->cdsmsp); - dmaerr(" CSUS[%08x]: %08x\n", xdmach->base + SAM_XDMACH_CSUS_OFFSET, regs->csus); - dmaerr(" CDUS[%08x]: %08x\n", xdmach->base + SAM_XDMACH_CDUS_OFFSET, regs->cdus); + dmainfo("%s\n", msg); + dmainfo(" DMA Global Registers:\n"); + dmainfo(" GTYPE[%08x]: %08x\n", xdmac->base + SAM_XDMAC_GTYPE_OFFSET, regs->gtype); + dmainfo(" GCFG[%08x]: %08x\n", xdmac->base + SAM_XDMAC_GCFG_OFFSET, regs->gcfg); + dmainfo(" GWAC[%08x]: %08x\n", xdmac->base + SAM_XDMAC_GWAC_OFFSET, regs->gwac); + dmainfo(" GIM[%08x]: %08x\n", xdmac->base + SAM_XDMAC_GIM_OFFSET, regs->gim); + dmainfo(" GIS[%08x]: %08x\n", xdmac->base + SAM_XDMAC_GIS_OFFSET, regs->gis); + dmainfo(" GS[%08x]: %08x\n", xdmac->base + SAM_XDMAC_GS_OFFSET, regs->gs); + dmainfo(" GRS[%08x]: %08x\n", xdmac->base + SAM_XDMAC_GRS_OFFSET, regs->grs); + dmainfo(" GWS[%08x]: %08x\n", xdmac->base + SAM_XDMAC_GWS_OFFSET, regs->gws); + dmainfo(" GSWS[%08x]: %08x\n", xdmac->base + SAM_XDMAC_GSWS_OFFSET, regs->gsws); + dmainfo(" DMA Channel Registers:\n"); + dmainfo(" CIM[%08x]: %08x\n", xdmach->base + SAM_XDMACH_CIM_OFFSET, regs->cim); + dmainfo(" CIS[%08x]: %08x\n", xdmach->base + SAM_XDMACH_CIS_OFFSET, regs->cis); + dmainfo(" CSA[%08x]: %08x\n", xdmach->base + SAM_XDMACH_CSA_OFFSET, regs->csa); + dmainfo(" CDA[%08x]: %08x\n", xdmach->base + SAM_XDMACH_CDA_OFFSET, regs->cda); + dmainfo(" CNDA[%08x]: %08x\n", xdmach->base + SAM_XDMACH_CNDA_OFFSET, regs->cnda); + dmainfo(" CNDC[%08x]: %08x\n", xdmach->base + SAM_XDMACH_CNDC_OFFSET, regs->cndc); + dmainfo(" CUBC[%08x]: %08x\n", xdmach->base + SAM_XDMACH_CUBC_OFFSET, regs->cubc); + dmainfo(" CBC[%08x]: %08x\n", xdmach->base + SAM_XDMACH_CBC_OFFSET, regs->cbc); + dmainfo(" CC[%08x]: %08x\n", xdmach->base + SAM_XDMACH_CC_OFFSET, regs->cc); + dmainfo(" CDSMSP[%08x]: %08x\n", xdmach->base + SAM_XDMACH_CDSMSP_OFFSET, regs->cdsmsp); + dmainfo(" CSUS[%08x]: %08x\n", xdmach->base + SAM_XDMACH_CSUS_OFFSET, regs->csus); + dmainfo(" CDUS[%08x]: %08x\n", xdmach->base + SAM_XDMACH_CDUS_OFFSET, regs->cdus); } -#endif /* CONFIG_DEBUG_DMA */ +#endif /* CONFIG_DEBUG_DMA_INFO */ #endif /* CONFIG_SAMA5_XDMAC0 || CONFIG_SAMA5_XDMAC1 */ diff --git a/arch/arm/src/samdl/Kconfig b/arch/arm/src/samdl/Kconfig index a890db6a0f..28ca29c90c 100644 --- a/arch/arm/src/samdl/Kconfig +++ b/arch/arm/src/samdl/Kconfig @@ -711,7 +711,7 @@ if SAMDL_HAVE_SPI config SAMDL_SPI_REGDEBUG bool "SPI register-Level Debug" default n - depends on DEBUG_SPI + depends on DEBUG_SPI_INFO ---help--- Enable very low-level register access debug. Depends on DEBUG_SPI. diff --git a/arch/arm/src/samdl/sam_dmac.c b/arch/arm/src/samdl/sam_dmac.c index f1afd24ff0..f81d77f75d 100644 --- a/arch/arm/src/samdl/sam_dmac.c +++ b/arch/arm/src/samdl/sam_dmac.c @@ -1259,7 +1259,7 @@ void sam_dmastop(DMA_HANDLE handle) * ****************************************************************************/ -#ifdef CONFIG_DEBUG_DMA +#ifdef CONFIG_DEBUG_DMA_INFO void sam_dmasample(DMA_HANDLE handle, struct sam_dmaregs_s *regs) { struct sam_dmach_s *dmach = (struct sam_dmach_s *)handle; @@ -1291,7 +1291,7 @@ void sam_dmasample(DMA_HANDLE handle, struct sam_dmaregs_s *regs) regs->chintflag = getreg8(SAM_DMAC_CHINTFLAG); /* Channel Interrupt Flag Status and Clear Register */ regs->chstatus = getreg8(SAM_DMAC_CHSTATUS); /* Channel Status Register */ } -#endif /* CONFIG_DEBUG_DMA */ +#endif /* CONFIG_DEBUG_DMA_INFO */ /**************************************************************************** * Name: sam_dmadump @@ -1304,26 +1304,26 @@ void sam_dmasample(DMA_HANDLE handle, struct sam_dmaregs_s *regs) * ****************************************************************************/ -#ifdef CONFIG_DEBUG_DMA +#ifdef CONFIG_DEBUG_DMA_INFO void sam_dmadump(DMA_HANDLE handle, const struct sam_dmaregs_s *regs, const char *msg) { struct sam_dmach_s *dmach = (struct sam_dmach_s *)handle; - dmaerr("%s\n", msg); - dmaerr(" DMAC Registers:\n"); - dmaerr(" CTRL: %04x CRCCTRL: %04x CRCDATAIN: %08x CRCCHKSUM: %08x\n", - regs->ctrl, regs->crcctrl, regs->crcdatain, regs->crcchksum); - dmaerr(" CRCSTATUS: %02x DBGCTRL: %02x QOSCTRL: %02x SWTRIGCTRL: %08x\n", - regs->crcstatus, regs->errctrl, regs->qosctrl, regs->swtrigctrl); - dmaerr(" PRICTRL0: %08x INTPEND: %04x INSTSTATUS: %08x BUSYCH: %08x\n", - regs->prictrl0, regs->intpend, regs->intstatus, regs->busych); - dmaerr(" PENDCH: %08x ACTIVE: %08x BASEADDR: %08x WRBADDR: %08x\n", - regs->pendch, regs->active, regs->baseaddr, regs->wrbaddr); - dmaerr(" CHID: %02x CHCRTRLA: %02x CHCRTRLB: %08x CHINFLAG: %02x\n", - regs->chid, regs->chctrla, regs->chctrlb, regs->chintflag, - dmaerr(" CHSTATUS: %02x\n", - regs->chstatus); + dmainfo("%s\n", msg); + dmainfo(" DMAC Registers:\n"); + dmainfo(" CTRL: %04x CRCCTRL: %04x CRCDATAIN: %08x CRCCHKSUM: %08x\n", + regs->ctrl, regs->crcctrl, regs->crcdatain, regs->crcchksum); + dmainfo(" CRCSTATUS: %02x DBGCTRL: %02x QOSCTRL: %02x SWTRIGCTRL: %08x\n", + regs->crcstatus, regs->errctrl, regs->qosctrl, regs->swtrigctrl); + dmainfo(" PRICTRL0: %08x INTPEND: %04x INSTSTATUS: %08x BUSYCH: %08x\n", + regs->prictrl0, regs->intpend, regs->intstatus, regs->busych); + dmainfo(" PENDCH: %08x ACTIVE: %08x BASEADDR: %08x WRBADDR: %08x\n", + regs->pendch, regs->active, regs->baseaddr, regs->wrbaddr); + dmainfo(" CHID: %02x CHCRTRLA: %02x CHCRTRLB: %08x CHINFLAG: %02x\n", + regs->chid, regs->chctrla, regs->chctrlb, regs->chintflag, + dmainfo(" CHSTATUS: %02x\n", + regs->chstatus); } -#endif /* CONFIG_DEBUG_DMA */ +#endif /* CONFIG_DEBUG_DMA_INFO */ #endif /* CONFIG_SAMDL_DMAC */ diff --git a/arch/arm/src/samdl/sam_dmac.h b/arch/arm/src/samdl/sam_dmac.h index 86224469ff..2a6937dd68 100644 --- a/arch/arm/src/samdl/sam_dmac.h +++ b/arch/arm/src/samdl/sam_dmac.h @@ -62,12 +62,6 @@ * Pre-processor Definitions ************************************************************************************/ -/* Configuration ********************************************************************/ - -#ifndef CONFIG_DEBUG_FEATURES -# undef CONFIG_DEBUG_DMA -#endif - /* DMA ******************************************************************************/ /* Flags used to characterize the desired DMA channel. The naming convention is that @@ -157,7 +151,7 @@ typedef void (*dma_callback_t)(DMA_HANDLE handle, void *arg, int result); /* The following is used for sampling DMA registers when CONFIG DEBUG_DMA is selected */ -#ifdef CONFIG_DEBUG_DMA +#ifdef CONFIG_DEBUG_DMA_INFO struct sam_dmaregs_s { /* DMAC Registers */ @@ -321,7 +315,7 @@ void sam_dmastop(DMA_HANDLE handle); * ************************************************************************************/ -#ifdef CONFIG_DEBUG_DMA +#ifdef CONFIG_DEBUG_DMA_INFO void sam_dmasample(DMA_HANDLE handle, struct sam_dmaregs_s *regs); #else # define sam_dmasample(handle,regs) @@ -335,7 +329,7 @@ void sam_dmasample(DMA_HANDLE handle, struct sam_dmaregs_s *regs); * ************************************************************************************/ -#ifdef CONFIG_DEBUG_DMA +#ifdef CONFIG_DEBUG_DMA_INFO void sam_dmadump(DMA_HANDLE handle, const struct sam_dmaregs_s *regs, const char *msg); #else diff --git a/arch/arm/src/samdl/sam_port.c b/arch/arm/src/samdl/sam_port.c index 1b4cd115fb..8ba1e1f88c 100644 --- a/arch/arm/src/samdl/sam_port.c +++ b/arch/arm/src/samdl/sam_port.c @@ -62,7 +62,7 @@ * Private Data ****************************************************************************/ -#ifdef CONFIG_DEBUG_PORT +#ifdef CONFIG_DEBUG_GPIO_INFO static const char g_portchar[2] = { 'A', 'B' }; #endif @@ -521,7 +521,7 @@ bool sam_portread(port_pinset_t pinset) * ************************************************************************************/ -#ifdef CONFIG_DEBUG_PORT +#ifdef CONFIG_DEBUG_GPIO_INFO int sam_dumpport(uint32_t pinset, const char *msg) { irqstate_t flags; @@ -538,20 +538,20 @@ int sam_dumpport(uint32_t pinset, const char *msg) /* The following requires exclusive access to the PORT registers */ flags = enter_critical_section(); - _llerr("PORT%c pin: %d pinset: %08x base: %08x -- %s\n", - g_portchar[port], pin, pinset, base, msg); - _llerr(" DIR: %08x OUT: %08x IN: %08x\n", - getreg32(base + SAM_PORT_DIR_OFFSET), - getreg32(base + SAM_PORT_OUT_OFFSET), - getreg32(base + SAM_PORT_IN_OFFSET)); - _llerr(" CTRL: %08x WRCONFIG: %08x\n", - getreg32(base + SAM_PORT_CTRL_OFFSET), - getreg32(base + SAM_PORT_WRCONFIG_OFFSET)); - _llerr(" PMUX[%08x]: %02x PINCFG[%08x]: %02x\n", - base + SAM_PORT_PMUX_OFFSET(pin), - getreg8(base + SAM_PORT_PMUX_OFFSET(pin)), - base + SAM_PORT_PINCFG_OFFSET(pin), - getreg8(base + SAM_PORT_PINCFG_OFFSET(pin))); + gpioinfo("PORT%c pin: %d pinset: %08x base: %08x -- %s\n", + g_portchar[port], pin, pinset, base, msg); + gpioinfo(" DIR: %08x OUT: %08x IN: %08x\n", + getreg32(base + SAM_PORT_DIR_OFFSET), + getreg32(base + SAM_PORT_OUT_OFFSET), + getreg32(base + SAM_PORT_IN_OFFSET)); + gpioinfo(" CTRL: %08x WRCONFIG: %08x\n", + getreg32(base + SAM_PORT_CTRL_OFFSET), + getreg32(base + SAM_PORT_WRCONFIG_OFFSET)); + gpioinfo(" PMUX[%08x]: %02x PINCFG[%08x]: %02x\n", + base + SAM_PORT_PMUX_OFFSET(pin), + getreg8(base + SAM_PORT_PMUX_OFFSET(pin)), + base + SAM_PORT_PINCFG_OFFSET(pin), + getreg8(base + SAM_PORT_PINCFG_OFFSET(pin))); leave_critical_section(flags); return OK; diff --git a/arch/arm/src/samdl/sam_spi.c b/arch/arm/src/samdl/sam_spi.c index 1d8f2c4163..ac7ea3d2cc 100644 --- a/arch/arm/src/samdl/sam_spi.c +++ b/arch/arm/src/samdl/sam_spi.c @@ -73,6 +73,14 @@ #ifdef SAMDL_HAVE_SPI +/**************************************************************************** + * Pre-process Definitions + ****************************************************************************/ + +#ifndef CONFIG_DEBUG_SPI_INFO +# undef CONFIG_SAMDL_SPI_REGDEBUG +#endif + /**************************************************************************** * Private Types ****************************************************************************/ @@ -540,7 +548,7 @@ static bool spi_checkreg(struct sam_spidev_s *priv, bool wr, uint32_t regval, { /* Yes... show how many times we did it */ - _llerr("...[Repeats %d times]...\n", priv->ntimes); + spiinfo("...[Repeats %d times]...\n", priv->ntimes); } /* Save information about the new access */ @@ -573,7 +581,7 @@ static uint8_t spi_getreg8(struct sam_spidev_s *priv, unsigned int offset) #ifdef CONFIG_SAMDL_SPI_REGDEBUG if (spi_checkreg(priv, false, (uint32_t)regval, regaddr)) { - _llerr("%08x->%02x\n", regaddr, regval); + spiinfo("%08x->%02x\n", regaddr, regval); } #endif @@ -596,7 +604,7 @@ static void spi_putreg8(struct sam_spidev_s *priv, uint8_t regval, #ifdef CONFIG_SAMDL_SPI_REGDEBUG if (spi_checkreg(priv, true, (uint32_t)regval, regaddr)) { - _llerr("%08x<-%02x\n", regaddr, regval); + spiinfo("%08x<-%02x\n", regaddr, regval); } #endif @@ -619,7 +627,7 @@ static uint16_t spi_getreg16(struct sam_spidev_s *priv, unsigned int offset) #ifdef CONFIG_SAMDL_SPI_REGDEBUG if (spi_checkreg(priv, false, (uint32_t)regval, regaddr)) { - _llerr("%08x->%04x\n", regaddr, regval); + spiinfo("%08x->%04x\n", regaddr, regval); } #endif @@ -642,7 +650,7 @@ static void spi_putreg16(struct sam_spidev_s *priv, uint16_t regval, #ifdef CONFIG_SAMDL_SPI_REGDEBUG if (spi_checkreg(priv, true, (uint32_t)regval, regaddr)) { - _llerr("%08x<-%04x\n", regaddr, regval); + spiinfo("%08x<-%04x\n", regaddr, regval); } #endif @@ -665,7 +673,7 @@ static uint32_t spi_getreg32(struct sam_spidev_s *priv, unsigned int offset) #ifdef CONFIG_SAMDL_SPI_REGDEBUG if (spi_checkreg(priv, false, regval, regaddr)) { - _llerr("%08x->%08x\n", regaddr, regval); + spiinfo("%08x->%08x\n", regaddr, regval); } #endif @@ -688,7 +696,7 @@ static void spi_putreg32(struct sam_spidev_s *priv, uint32_t regval, #ifdef CONFIG_SAMDL_SPI_REGDEBUG if (spi_checkreg(priv, true, regval, regaddr)) { - _llerr("%08x<-%08x\n", regaddr, regval); + spiinfo("%08x<-%08x\n", regaddr, regval); } #endif diff --git a/arch/arm/src/samv7/Kconfig b/arch/arm/src/samv7/Kconfig index bbed32a7b8..1f217e5d4a 100644 --- a/arch/arm/src/samv7/Kconfig +++ b/arch/arm/src/samv7/Kconfig @@ -701,7 +701,7 @@ config SAMV7_WDT_IDLEHALT config SAMV7_WDT_REGDEBUG bool "Register level debug" default n - depends on DEBUG_FEATURES + depends on DEBUG_WATCHDOG_INFO ---help--- Enable low-level register debug output @@ -735,7 +735,7 @@ config SAMV7_RSWDT_IDLEHALT config SAMV7_RSWDT_REGDEBUG bool "Register level debug" default n - depends on DEBUG_FEATURES + depends on DEBUG_WATCHDOG_INFO ---help--- Enable low-level register debug output @@ -894,11 +894,11 @@ endif # SAMV7_SPI_SLAVE config SAMV7_SPI_REGDEBUG bool "SPI Register level debug" - depends on DEBUG_FEATURES + depends on DEBUG_SPI_INFO default n ---help--- Output detailed register-level SPI device debug information. - Requires also CONFIG_DEBUG_FEATURES. + Requires also CONFIG_DEBUG_SPI_INFO. endmenu # SPI device driver options @@ -941,11 +941,11 @@ config SAMV7_QSPI_DMADEBUG config SAMV7_QSPI_REGDEBUG bool "QSPI Register level debug" - depends on DEBUG_FEATURES + depends on DEBUG_SPI_INFO default n ---help--- Output detailed register-level QSPI device debug information. - Requires also CONFIG_DEBUG_FEATURES. + Requires also CONFIG_DEBUG_SPI_INFO. endmenu # QSPI device driver options @@ -969,11 +969,11 @@ config SAMV7_TWIHS2_FREQUENCY config SAMV7_TWIHS_REGDEBUG bool "TWIHS register level debug" - depends on DEBUG_FEATURES + depends on DEBUG_I2C_INFO default n ---help--- Output detailed register-level TWIHS device debug information. - Very invasive! Requires also CONFIG_DEBUG_FEATURES. + Very invasive! Requires also CONFIG_DEBUG_I2C_INFO. endmenu # TWIHS device driver options @@ -1345,11 +1345,11 @@ config SAMV7_SSC_DMADEBUG config SAMV7_SSC_REGDEBUG bool "SSC Register level debug" - depends on DEBUG_FEATURES + depends on DEBUG_I2S_INFO default n ---help--- Output detailed register-level SSC device debug information. - Very invasive! Requires also CONFIG_DEBUG_FEATURES. + Very invasive! Requires also CONFIG_DEBUG_I2S_INFO. config SAMV7_SSC_QDEBUG bool "SSC Queue debug" @@ -1580,11 +1580,11 @@ config SAMV7_TC_DEBUG config SAMV7_TC_REGDEBUG bool "TC register level debug" - depends on DEBUG_FEATURES + depends on DEBUG_TIMER_INFO default n ---help--- Output detailed register-level Timer/Counter device debug - information. Very invasive! Requires also CONFIG_DEBUG_FEATURES. + information. Very invasive! Requires also CONFIG_DEBUG_TIMER_INFO. endmenu # Timer/counter Configuration endif # SAMV7_HAVE_TC @@ -1658,11 +1658,11 @@ config SAMV7_HSMCI_CMDDEBUG config SAMV7_HSMCI_REGDEBUG bool "HSMCI Register level debug" - depends on DEBUG_FEATURES + depends on DEBUG_MEMCARD_INFO default n ---help--- Output detailed register-level HSCMI device debug information. - Very invasive! Requires also CONFIG_DEBUG_FEATURES. + Very invasive! Requires also DEBUG_MEMCARD_INFO. endmenu # HSMCI device driver options @@ -1882,9 +1882,9 @@ config SAMV7_EMAC_DEBUG config SAMV7_EMAC_REGDEBUG bool "Register-Level Debug" default n - depends on DEBUG_FEATURES + depends on DEBUG_NET_INFO ---help--- - Enable very low-level register access debug. Depends on CONFIG_DEBUG_FEATURES. + Enable very low-level register access debug. Depends on CONFIG_DEBUG_NET_INFO. endmenu # EMAC0 device driver options @@ -1940,7 +1940,7 @@ config SAMV7_USBHS_EP7DMA_WAR config SAMV7_USBHS_REGDEBUG bool "Enable low-level USBHS register debug" default n - depends on DEBUG_FEATURES + depends on DEBUG_USB_INFO endmenu # USB High Speed Device Controller driver (DCD) options diff --git a/arch/arm/src/samv7/sam_emac.c b/arch/arm/src/samv7/sam_emac.c index f43d432b68..ae1151a04f 100644 --- a/arch/arm/src/samv7/sam_emac.c +++ b/arch/arm/src/samv7/sam_emac.c @@ -307,16 +307,16 @@ * enabled. */ -#ifndef CONFIG_DEBUG_FEATURES -# undef CONFIG_SAMV7_EMAC_REGDEBUG -#endif - #ifdef CONFIG_NET_DUMPPACKET # define sam_dumppacket(m,a,n) lib_dumpbuffer(m,a,n) #else # define sam_dumppacket(m,a,n) #endif +#ifndef CONFIG_NET_INFO +# undef CONFIG_SAMV7_EMAC_REGDEBUG +#endif + /* EMAC buffer sizes, number of buffers, and number of descriptors *********** * * REVISIT: The CONFIG_NET_MULTIBUFFER might be useful. It might be possible @@ -560,7 +560,7 @@ struct sam_emac_s ****************************************************************************/ /* Register operations ******************************************************/ -#if defined(CONFIG_SAMV7_EMAC_REGDEBUG) && defined(CONFIG_DEBUG_FEATURES) +#ifdef CONFIG_SAMV7_EMAC_REGDEBUG static bool sam_checkreg(struct sam_emac_s *priv, bool wr, uint32_t regval, uintptr_t address); #endif @@ -966,7 +966,7 @@ static bool sam_checkreg(struct sam_emac_s *priv, bool wr, uint32_t regval, { /* Yes... show how many times we did it */ - _llerr("...[Repeats %d times]...\n", priv->ntimes); + ninfo("...[Repeats %d times]...\n", priv->ntimes); } /* Save information about the new access */ @@ -999,7 +999,7 @@ static uint32_t sam_getreg(struct sam_emac_s *priv, uint16_t offset) #ifdef CONFIG_SAMV7_EMAC_REGDEBUG if (sam_checkreg(priv, false, regval, regaddr)) { - _llerr("%08x->%08x\n", regaddr, regval); + ninfo("%08x->%08x\n", regaddr, regval); } #endif @@ -1023,7 +1023,7 @@ static void sam_putreg(struct sam_emac_s *priv, uint16_t offset, #ifdef CONFIG_SAMV7_EMAC_REGDEBUG if (sam_checkreg(priv, true, regval, regaddr)) { - _llerr("%08x<-%08x\n", regaddr, regval); + ninfo("%08x<-%08x\n", regaddr, regval); } #endif @@ -1896,7 +1896,7 @@ static void sam_receive(struct sam_emac_s *priv, int qid) if (dev->d_len > CONFIG_NET_ETH_MTU) { - nllerr("DROPPED: Too big: %d\n", dev->d_len); + nllwarn("WARNING: Dropped, Too big: %d\n", dev->d_len); NETDEV_RXERRORS(&priv->dev); continue; } @@ -2010,7 +2010,7 @@ static void sam_receive(struct sam_emac_s *priv, int qid) else #endif { - nllerr("DROPPED: Unknown type: %04x\n", BUF->type); + nllwarn("WARNING: Dropped, Unknown type: %04x\n", BUF->type); NETDEV_RXDROPPED(&priv->dev); } } @@ -2418,7 +2418,7 @@ static inline void sam_interrupt_process(FAR struct sam_emac_s *priv, int qid) if ((pending & EMAC_INT_PFNZ) != 0) { - nllerr("Pause frame received\n"); + nllinfo("Pause frame received\n"); } /* Check for Pause Time Zero (PTZ) @@ -2428,7 +2428,7 @@ static inline void sam_interrupt_process(FAR struct sam_emac_s *priv, int qid) if ((pending & EMAC_INT_PTZ) != 0) { - nllerr("Pause TO!\n"); + nllinfo("Pause TO!\n"); } #endif } @@ -2593,7 +2593,7 @@ static int sam_emac1_interrupt(int irq, void *context) static inline void sam_txtimeout_process(FAR struct sam_emac_s *priv) { - nllerr("Timeout!\n"); + nllerr("ERROR: Timeout!\n"); NETDEV_TXTIMEOUTS(&priv->dev); /* Reset the hardware. Just take the interface down, then back up again. */ @@ -2824,15 +2824,15 @@ static int sam_ifup(struct net_driver_s *dev) int ret; #ifdef CONFIG_NET_IPv4 - nerr("Bringing up: %d.%d.%d.%d\n", - dev->d_ipaddr & 0xff, (dev->d_ipaddr >> 8) & 0xff, - (dev->d_ipaddr >> 16) & 0xff, dev->d_ipaddr >> 24); + ninfo("Bringing up: %d.%d.%d.%d\n", + dev->d_ipaddr & 0xff, (dev->d_ipaddr >> 8) & 0xff, + (dev->d_ipaddr >> 16) & 0xff, dev->d_ipaddr >> 24); #endif #ifdef CONFIG_NET_IPv6 - nerr("Bringing up: %04x:%04x:%04x:%04x:%04x:%04x:%04x:%04x\n", - dev->d_ipv6addr[0], dev->d_ipv6addr[1], dev->d_ipv6addr[2], - dev->d_ipv6addr[3], dev->d_ipv6addr[4], dev->d_ipv6addr[5], - dev->d_ipv6addr[6], dev->d_ipv6addr[7]); + ninfo("Bringing up: %04x:%04x:%04x:%04x:%04x:%04x:%04x:%04x\n", + dev->d_ipv6addr[0], dev->d_ipv6addr[1], dev->d_ipv6addr[2], + dev->d_ipv6addr[3], dev->d_ipv6addr[4], dev->d_ipv6addr[5], + dev->d_ipv6addr[6], dev->d_ipv6addr[7]); #endif /* Configure the EMAC interface for normal operation. */ @@ -2910,7 +2910,7 @@ static int sam_ifdown(struct net_driver_s *dev) struct sam_emac_s *priv = (struct sam_emac_s *)dev->d_private; irqstate_t flags; - nllerr("Taking the network down\n"); + nllinfo("Taking the network down\n"); /* Disable the EMAC interrupt */ diff --git a/arch/arm/src/samv7/sam_hsmci.c b/arch/arm/src/samv7/sam_hsmci.c index ec664e0e93..bddf8e7f9a 100644 --- a/arch/arm/src/samv7/sam_hsmci.c +++ b/arch/arm/src/samv7/sam_hsmci.c @@ -81,6 +81,10 @@ # error "HSMCI support requires CONFIG_SAMV7_XDMAC" #endif +#ifndef CONFIG_DEBUG_MEMCARD_INFO +# undef CONFIG_SAMV7_HSMCI_REGDEBUG +#endif + /* System Bus Interfaces */ #if defined(CONFIG_ARCH_CHIP_SAMV71) || defined(CONFIG_ARCH_CHIP_SAME70) @@ -653,7 +657,7 @@ static bool sam_checkreg(struct sam_dev_s *priv, bool wr, uint32_t value, { /* Yes... show how many times we did it */ - _llerr("...[Repeats %d times]...\n", priv->ntimes); + mcinfo("...[Repeats %d times]...\n", priv->ntimes); } /* Save information about the new access */ @@ -686,7 +690,7 @@ static inline uint32_t sam_getreg(struct sam_dev_s *priv, unsigned int offset) #ifdef CONFIG_SAMV7_HSMCI_REGDEBUG if (sam_checkreg(priv, false, value, address)) { - _llerr("%08x->%08x\n", address, value); + mcinfo("%08x->%08x\n", address, value); } #endif @@ -709,7 +713,7 @@ static inline void sam_putreg(struct sam_dev_s *priv, uint32_t value, #ifdef CONFIG_SAMV7_HSMCI_REGDEBUG if (sam_checkreg(priv, true, value, address)) { - _llerr("%08x<-%08x\n", address, value); + mcinfo("%08x<-%08x\n", address, value); } #endif @@ -933,25 +937,25 @@ static void sam_hsmcisample(struct sam_dev_s *priv, static void sam_hsmcidump(struct sam_dev_s *priv, struct sam_hsmciregs_s *regs, const char *msg) { - ferr("HSMCI Registers: %s\n", msg); - ferr(" MR[%08x]: %08x\n", priv->base + SAM_HSMCI_MR_OFFSET, regs->mr); - ferr(" DTOR[%08x]: %08x\n", priv->base + SAM_HSMCI_DTOR_OFFSET, regs->dtor); - ferr(" SDCR[%08x]: %08x\n", priv->base + SAM_HSMCI_SDCR_OFFSET, regs->sdcr); - ferr(" ARGR[%08x]: %08x\n", priv->base + SAM_HSMCI_ARGR_OFFSET, regs->argr); - ferr(" BLKR[%08x]: %08x\n", priv->base + SAM_HSMCI_BLKR_OFFSET, regs->blkr); - ferr(" CSTOR[%08x]: %08x\n", priv->base + SAM_HSMCI_CSTOR_OFFSET, regs->cstor); + mcinfo("HSMCI Registers: %s\n", msg); + mcinfo(" MR[%08x]: %08x\n", priv->base + SAM_HSMCI_MR_OFFSET, regs->mr); + mcinfo(" DTOR[%08x]: %08x\n", priv->base + SAM_HSMCI_DTOR_OFFSET, regs->dtor); + mcinfo(" SDCR[%08x]: %08x\n", priv->base + SAM_HSMCI_SDCR_OFFSET, regs->sdcr); + mcinfo(" ARGR[%08x]: %08x\n", priv->base + SAM_HSMCI_ARGR_OFFSET, regs->argr); + mcinfo(" BLKR[%08x]: %08x\n", priv->base + SAM_HSMCI_BLKR_OFFSET, regs->blkr); + mcinfo(" CSTOR[%08x]: %08x\n", priv->base + SAM_HSMCI_CSTOR_OFFSET, regs->cstor); #if 0 /* Reading these can cause loss of response data */ - ferr(" RSPR0[%08x]: %08x\n", priv->base + SAM_HSMCI_RSPR0_OFFSET, regs->rsp0); - ferr(" RSPR1[%08x]: %08x\n", priv->base + SAM_HSMCI_RSPR1_OFFSET, regs->rsp1); - ferr(" RSPR2[%08x]: %08x\n", priv->base + SAM_HSMCI_RSPR2_OFFSET, regs->rsp2); - ferr(" RSPR3[%08x]: %08x\n", priv->base + SAM_HSMCI_RSPR3_OFFSET, regs->rsp3); + mcinfo(" RSPR0[%08x]: %08x\n", priv->base + SAM_HSMCI_RSPR0_OFFSET, regs->rsp0); + mcinfo(" RSPR1[%08x]: %08x\n", priv->base + SAM_HSMCI_RSPR1_OFFSET, regs->rsp1); + mcinfo(" RSPR2[%08x]: %08x\n", priv->base + SAM_HSMCI_RSPR2_OFFSET, regs->rsp2); + mcinfo(" RSPR3[%08x]: %08x\n", priv->base + SAM_HSMCI_RSPR3_OFFSET, regs->rsp3); #endif - ferr(" SR[%08x]: %08x\n", priv->base + SAM_HSMCI_SR_OFFSET, regs->sr); - ferr(" IMR[%08x]: %08x\n", priv->base + SAM_HSMCI_IMR_OFFSET, regs->imr); - ferr(" DMA[%08x]: %08x\n", priv->base + SAM_HSMCI_DMA_OFFSET, regs->dma); - ferr(" CFG[%08x]: %08x\n", priv->base + SAM_HSMCI_CFG_OFFSET, regs->cfg); - ferr(" WPMR[%08x]: %08x\n", priv->base + SAM_HSMCI_WPMR_OFFSET, regs->wpmr); - ferr(" WPSR[%08x]: %08x\n", priv->base + SAM_HSMCI_WPSR_OFFSET, regs->wpsr); + mcinfo(" SR[%08x]: %08x\n", priv->base + SAM_HSMCI_SR_OFFSET, regs->sr); + mcinfo(" IMR[%08x]: %08x\n", priv->base + SAM_HSMCI_IMR_OFFSET, regs->imr); + mcinfo(" DMA[%08x]: %08x\n", priv->base + SAM_HSMCI_DMA_OFFSET, regs->dma); + mcinfo(" CFG[%08x]: %08x\n", priv->base + SAM_HSMCI_CFG_OFFSET, regs->cfg); + mcinfo(" WPMR[%08x]: %08x\n", priv->base + SAM_HSMCI_WPMR_OFFSET, regs->wpmr); + mcinfo(" WPSR[%08x]: %08x\n", priv->base + SAM_HSMCI_WPSR_OFFSET, regs->wpsr); } #endif @@ -1025,7 +1029,7 @@ static void sam_xfrdumpone(struct sam_dev_s *priv, int index, } else { - ferr("%s: Not collected\n", msg); + mcerr("ERROR: %s: Not collected\n", msg); } } #endif @@ -1169,7 +1173,7 @@ static void sam_dmacallback(DMA_HANDLE handle, void *arg, int result) if (result < 0) { wkupevent = (result == -ETIMEDOUT ? SDIOWAIT_TIMEOUT : SDIOWAIT_ERROR); - fllerr("ERROR: DMA failed: result=%d wkupevent=%04x\n", result, wkupevent); + mcllerr("ERROR: DMA failed: result=%d wkupevent=%04x\n", result, wkupevent); /* sam_endtransfer will terminate the transfer and wait up the waiting * client in this case. @@ -1269,7 +1273,7 @@ static void sam_eventtimeout(int argc, uint32_t arg) /* Yes.. wake up any waiting threads */ sam_endwait(priv, SDIOWAIT_TIMEOUT); - fllerr("ERROR: Timeout\n"); + mcllerr("ERROR: Timeout\n"); } } @@ -1469,7 +1473,7 @@ static int sam_hsmci_interrupt(struct sam_dev_s *priv) { /* Yes.. Was it some kind of timeout error? */ - fllerr("ERROR: enabled: %08x pending: %08x\n", enabled, pending); + mcllerr("ERROR: enabled: %08x pending: %08x\n", enabled, pending); if ((pending & HSMCI_DATA_TIMEOUT_ERRORS) != 0) { /* Yes.. Terminate with a timeout. */ @@ -1590,7 +1594,7 @@ static int sam_hsmci_interrupt(struct sam_dev_s *priv) { /* Yes.. Was the error some kind of timeout? */ - fllinfo("ERROR: events: %08x SR: %08x\n", + mcllinfo("ERROR: events: %08x SR: %08x\n", priv->cmdrmask, enabled); if ((pending & HSMCI_RESPONSE_TIMEOUT_ERRORS) != 0) @@ -2056,7 +2060,7 @@ static int sam_sendcmd(FAR struct sdio_dev_s *dev, /* Write the fully decorated command to CMDR */ - finfo("cmd: %08x arg: %08x regval: %08x\n", cmd, arg, regval); + mcinfo("cmd: %08x arg: %08x regval: %08x\n", cmd, arg, regval); sam_putreg(priv, regval, SAM_HSMCI_CMDR_OFFSET); sam_cmdsample1(priv, SAMPLENDX_AFTER_CMDR); return OK; @@ -2239,7 +2243,7 @@ static int sam_sendsetup(FAR struct sdio_dev_s *dev, FAR const uint8_t *buffer, { /* Some fatal error has occurred */ - ferr("ERROR: sr %08x\n", sr); + mcerr("ERROR: sr %08x\n", sr); return -EIO; } else if ((sr & HSMCI_INT_TXRDY) != 0) @@ -2419,7 +2423,7 @@ static int sam_waitresponse(FAR struct sdio_dev_s *dev, uint32_t cmd) { /* Yes.. Was the error some kind of timeout? */ - ferr("ERROR: cmd: %08x events: %08x SR: %08x\n", + mcerr("ERROR: cmd: %08x events: %08x SR: %08x\n", cmd, priv->cmdrmask, sr); if ((pending & HSMCI_RESPONSE_TIMEOUT_ERRORS) != 0) @@ -2449,7 +2453,7 @@ static int sam_waitresponse(FAR struct sdio_dev_s *dev, uint32_t cmd) } else if (--timeout <= 0) { - ferr("ERROR: Timeout cmd: %08x events: %08x SR: %08x\n", + mcerr("ERROR: Timeout cmd: %08x events: %08x SR: %08x\n", cmd, priv->cmdrmask, sr); priv->wkupevent = SDIOWAIT_TIMEOUT; @@ -2524,7 +2528,7 @@ static int sam_recvshort(FAR struct sdio_dev_s *dev, #ifdef CONFIG_DEBUG_FEATURES if (!rshort) { - ferr("ERROR: rshort=NULL\n"); + mcerr("ERROR: rshort=NULL\n"); ret = -EINVAL; } @@ -2536,7 +2540,7 @@ static int sam_recvshort(FAR struct sdio_dev_s *dev, (cmd & MMCSD_RESPONSE_MASK) != MMCSD_R3_RESPONSE && (cmd & MMCSD_RESPONSE_MASK) != MMCSD_R7_RESPONSE) { - ferr("ERROR: Wrong response CMD=%08x\n", cmd); + mcerr("ERROR: Wrong response CMD=%08x\n", cmd); ret = -EINVAL; } else @@ -2587,7 +2591,7 @@ static int sam_recvlong(FAR struct sdio_dev_s *dev, uint32_t cmd, if ((cmd & MMCSD_RESPONSE_MASK) != MMCSD_R2_RESPONSE) { - ferr("ERROR: Wrong response CMD=%08x\n", cmd); + mcerr("ERROR: Wrong response CMD=%08x\n", cmd); ret = -EINVAL; } else @@ -2597,7 +2601,7 @@ static int sam_recvlong(FAR struct sdio_dev_s *dev, uint32_t cmd, if ((priv->wkupevent & SDIOWAIT_TIMEOUT) != 0) { - ferr("ERROR: timeout\n"); + mcerr("ERROR: timeout\n"); ret = -EINVAL; } @@ -2605,7 +2609,7 @@ static int sam_recvlong(FAR struct sdio_dev_s *dev, uint32_t cmd, else if ((priv->wkupevent & SDIOWAIT_ERROR) != 0) { - ferr("ERROR: Other error\n"); + mcerr("ERROR: Other error\n"); ret = -EIO; } @@ -2781,7 +2785,7 @@ static sdio_eventset_t sam_eventwait(FAR struct sdio_dev_s *dev, 1, (uint32_t)priv); if (ret != OK) { - ferr("ERROR: wd_start failed: %d\n", ret); + mcerr("ERROR: wd_start failed: %d\n", ret); } } @@ -2847,7 +2851,7 @@ static void sam_callbackenable(FAR struct sdio_dev_s *dev, { struct sam_dev_s *priv = (struct sam_dev_s *)dev; - finfo("eventset: %02x\n", eventset); + mcinfo("eventset: %02x\n", eventset); DEBUGASSERT(priv != NULL); priv->cbevents = eventset; @@ -2883,7 +2887,7 @@ static int sam_registercallback(FAR struct sdio_dev_s *dev, /* Disable callbacks and register this callback and is argument */ - finfo("Register %p(%p)\n", callback, arg); + mcinfo("Register %p(%p)\n", callback, arg); DEBUGASSERT(priv != NULL); priv->cbevents = 0; @@ -3158,7 +3162,7 @@ static void sam_callback(void *arg) /* Is a callback registered? */ DEBUGASSERT(priv != NULL); - finfo("Callback %p(%p) cbevents: %02x cdstatus: %02x\n", + mcinfo("Callback %p(%p) cbevents: %02x cdstatus: %02x\n", priv->callback, priv->cbarg, priv->cbevents, priv->cdstatus); flags = enter_critical_section(); @@ -3213,17 +3217,17 @@ static void sam_callback(void *arg) { /* NOTE: Currently, work_cancel only returns success */ - ferr("ERROR: Failed to cancel work: %d\n", ret); + mcerr("ERROR: Failed to cancel work: %d\n", ret); } - fllinfo("Queuing callback to %p(%p)\n", priv->callback, priv->cbarg); + mcllinfo("Queuing callback to %p(%p)\n", priv->callback, priv->cbarg); ret = work_queue(LPWORK, &priv->cbwork, (worker_t)priv->callback, priv->cbarg, 0); if (ret < 0) { /* NOTE: Currently, work_queue only returns success */ - ferr("ERROR: Failed to schedule work: %d\n", ret); + mcerr("ERROR: Failed to schedule work: %d\n", ret); } } @@ -3261,7 +3265,7 @@ FAR struct sdio_dev_s *sdio_initialize(int slotno) * for now, an* HSMCI peripheral does correspond to a slot. */ - finfo("slotno: %d\n", slotno); + mcinfo("slotno: %d\n", slotno); #ifdef CONFIG_SAMV7_HSMCI0 if (slotno == 0) @@ -3344,7 +3348,7 @@ FAR struct sdio_dev_s *sdio_initialize(int slotno) return NULL; } - finfo("priv: %p base: %08x hsmci: %d pid: %d\n", + mcinfo("priv: %p base: %08x hsmci: %d pid: %d\n", priv, priv->base, priv->hsmci, pid); /* Initialize the HSMCI slot structure */ @@ -3414,7 +3418,7 @@ void sdio_mediachange(FAR struct sdio_dev_s *dev, bool cardinslot) priv->cdstatus &= ~SDIO_STATUS_PRESENT; } - fllinfo("cdstatus OLD: %02x NEW: %02x\n", cdstatus, priv->cdstatus); + mcllinfo("cdstatus OLD: %02x NEW: %02x\n", cdstatus, priv->cdstatus); /* Perform any requested callback if the status has changed */ @@ -3459,7 +3463,7 @@ void sdio_wrprotect(FAR struct sdio_dev_s *dev, bool wrprotect) priv->cdstatus &= ~SDIO_STATUS_WRPROTECTED; } - finfo("cdstatus: %02x\n", priv->cdstatus); + mcinfo("cdstatus: %02x\n", priv->cdstatus); leave_critical_section(flags); } diff --git a/arch/arm/src/samv7/sam_mcan.c b/arch/arm/src/samv7/sam_mcan.c index 1cf299e055..adade97363 100644 --- a/arch/arm/src/samv7/sam_mcan.c +++ b/arch/arm/src/samv7/sam_mcan.c @@ -1195,7 +1195,7 @@ static uint32_t mcan_getreg(FAR struct sam_mcan_s *priv, int offset) { if (priv->count == 4) { - _llerr("...\n"); + caninfo("...\n"); } return regval; @@ -1212,7 +1212,7 @@ static uint32_t mcan_getreg(FAR struct sam_mcan_s *priv, int offset) { /* Yes.. then show how many times the value repeated */ - _llerr("[repeats %d more times]\n", priv->count - 3); + caninfo("[repeats %d more times]\n", priv->count - 3); } /* Save the new address, value, and count */ @@ -1224,7 +1224,7 @@ static uint32_t mcan_getreg(FAR struct sam_mcan_s *priv, int offset) /* Show the register value read */ - _llerr("%08x->%08x\n", regaddr, regval); + caninfo("%08x->%08x\n", regaddr, regval); return regval; } @@ -1261,7 +1261,7 @@ static void mcan_putreg(FAR struct sam_mcan_s *priv, int offset, uint32_t regval /* Show the register value being written */ - _llerr("%08x<-%08x\n", regaddr, regval); + caninfo("%08x<-%08x\n", regaddr, regval); /* Write the value */ @@ -1296,74 +1296,74 @@ static void mcan_dumpregs(FAR struct sam_mcan_s *priv, FAR const char *msg) { FAR const struct sam_config_s *config = priv->config; - _llerr("MCAN%d Registers: %s\n", config->port, msg); - _llerr(" Base: %08x\n", config->base); + caninfo("MCAN%d Registers: %s\n", config->port, msg); + caninfo(" Base: %08x\n", config->base); - _llerr(" CUST: %08x FBTP: %08x TEST: %08x RWD: %08x\n", - getreg32(config->base + SAM_MCAN_CUST_OFFSET), - getreg32(config->base + SAM_MCAN_FBTP_OFFSET), - getreg32(config->base + SAM_MCAN_TEST_OFFSET), - getreg32(config->base + SAM_MCAN_RWD_OFFSET)); + caninfo(" CUST: %08x FBTP: %08x TEST: %08x RWD: %08x\n", + getreg32(config->base + SAM_MCAN_CUST_OFFSET), + getreg32(config->base + SAM_MCAN_FBTP_OFFSET), + getreg32(config->base + SAM_MCAN_TEST_OFFSET), + getreg32(config->base + SAM_MCAN_RWD_OFFSET)); - _llerr(" CCCR: %08x BTP: %08x TSCC: %08x TSCV: %08x\n", - getreg32(config->base + SAM_MCAN_CCCR_OFFSET), - getreg32(config->base + SAM_MCAN_BTP_OFFSET), - getreg32(config->base + SAM_MCAN_TSCC_OFFSET), - getreg32(config->base + SAM_MCAN_TSCV_OFFSET)); + caninfo(" CCCR: %08x BTP: %08x TSCC: %08x TSCV: %08x\n", + getreg32(config->base + SAM_MCAN_CCCR_OFFSET), + getreg32(config->base + SAM_MCAN_BTP_OFFSET), + getreg32(config->base + SAM_MCAN_TSCC_OFFSET), + getreg32(config->base + SAM_MCAN_TSCV_OFFSET)); - _llerr(" TOCC: %08x TOCV: %08x ECR: %08x PSR: %08x\n", - getreg32(config->base + SAM_MCAN_TOCC_OFFSET), - getreg32(config->base + SAM_MCAN_TOCV_OFFSET), - getreg32(config->base + SAM_MCAN_ECR_OFFSET), - getreg32(config->base + SAM_MCAN_PSR_OFFSET)); + caninfo(" TOCC: %08x TOCV: %08x ECR: %08x PSR: %08x\n", + getreg32(config->base + SAM_MCAN_TOCC_OFFSET), + getreg32(config->base + SAM_MCAN_TOCV_OFFSET), + getreg32(config->base + SAM_MCAN_ECR_OFFSET), + getreg32(config->base + SAM_MCAN_PSR_OFFSET)); - _llerr(" IR: %08x IE: %08x ILS: %08x ILE: %08x\n", - getreg32(config->base + SAM_MCAN_IR_OFFSET), - getreg32(config->base + SAM_MCAN_IE_OFFSET), - getreg32(config->base + SAM_MCAN_ILS_OFFSET), - getreg32(config->base + SAM_MCAN_ILE_OFFSET)); + caninfo(" IR: %08x IE: %08x ILS: %08x ILE: %08x\n", + getreg32(config->base + SAM_MCAN_IR_OFFSET), + getreg32(config->base + SAM_MCAN_IE_OFFSET), + getreg32(config->base + SAM_MCAN_ILS_OFFSET), + getreg32(config->base + SAM_MCAN_ILE_OFFSET)); - _llerr(" GFC: %08x SIDFC: %08x XIDFC: %08x XIDAM: %08x\n", - getreg32(config->base + SAM_MCAN_GFC_OFFSET), - getreg32(config->base + SAM_MCAN_SIDFC_OFFSET), - getreg32(config->base + SAM_MCAN_XIDFC_OFFSET), - getreg32(config->base + SAM_MCAN_XIDAM_OFFSET)); + caninfo(" GFC: %08x SIDFC: %08x XIDFC: %08x XIDAM: %08x\n", + getreg32(config->base + SAM_MCAN_GFC_OFFSET), + getreg32(config->base + SAM_MCAN_SIDFC_OFFSET), + getreg32(config->base + SAM_MCAN_XIDFC_OFFSET), + getreg32(config->base + SAM_MCAN_XIDAM_OFFSET)); - _llerr(" HPMS: %08x NDAT1: %08x NDAT2: %08x RXF0C: %08x\n", - getreg32(config->base + SAM_MCAN_HPMS_OFFSET), - getreg32(config->base + SAM_MCAN_NDAT1_OFFSET), - getreg32(config->base + SAM_MCAN_NDAT2_OFFSET), - getreg32(config->base + SAM_MCAN_RXF0C_OFFSET)); + caninfo(" HPMS: %08x NDAT1: %08x NDAT2: %08x RXF0C: %08x\n", + getreg32(config->base + SAM_MCAN_HPMS_OFFSET), + getreg32(config->base + SAM_MCAN_NDAT1_OFFSET), + getreg32(config->base + SAM_MCAN_NDAT2_OFFSET), + getreg32(config->base + SAM_MCAN_RXF0C_OFFSET)); - _llerr(" RXF0S: %08x FXF0A: %08x RXBC: %08x RXF1C: %08x\n", - getreg32(config->base + SAM_MCAN_RXF0S_OFFSET), - getreg32(config->base + SAM_MCAN_RXF0A_OFFSET), - getreg32(config->base + SAM_MCAN_RXBC_OFFSET), - getreg32(config->base + SAM_MCAN_RXF1C_OFFSET)); + caninfo(" RXF0S: %08x FXF0A: %08x RXBC: %08x RXF1C: %08x\n", + getreg32(config->base + SAM_MCAN_RXF0S_OFFSET), + getreg32(config->base + SAM_MCAN_RXF0A_OFFSET), + getreg32(config->base + SAM_MCAN_RXBC_OFFSET), + getreg32(config->base + SAM_MCAN_RXF1C_OFFSET)); - _llerr(" RXF1S: %08x FXF1A: %08x RXESC: %08x TXBC: %08x\n", - getreg32(config->base + SAM_MCAN_RXF1S_OFFSET), - getreg32(config->base + SAM_MCAN_RXF1A_OFFSET), - getreg32(config->base + SAM_MCAN_RXESC_OFFSET), - getreg32(config->base + SAM_MCAN_TXBC_OFFSET)); + caninfo(" RXF1S: %08x FXF1A: %08x RXESC: %08x TXBC: %08x\n", + getreg32(config->base + SAM_MCAN_RXF1S_OFFSET), + getreg32(config->base + SAM_MCAN_RXF1A_OFFSET), + getreg32(config->base + SAM_MCAN_RXESC_OFFSET), + getreg32(config->base + SAM_MCAN_TXBC_OFFSET)); - _llerr(" TXFQS: %08x TXESC: %08x TXBRP: %08x TXBAR: %08x\n", - getreg32(config->base + SAM_MCAN_TXFQS_OFFSET), - getreg32(config->base + SAM_MCAN_TXESC_OFFSET), - getreg32(config->base + SAM_MCAN_TXBRP_OFFSET), - getreg32(config->base + SAM_MCAN_TXBAR_OFFSET)); + caninfo(" TXFQS: %08x TXESC: %08x TXBRP: %08x TXBAR: %08x\n", + getreg32(config->base + SAM_MCAN_TXFQS_OFFSET), + getreg32(config->base + SAM_MCAN_TXESC_OFFSET), + getreg32(config->base + SAM_MCAN_TXBRP_OFFSET), + getreg32(config->base + SAM_MCAN_TXBAR_OFFSET)); - _llerr(" TXBCR: %08x TXBTO: %08x TXBCF: %08x TXBTIE: %08x\n", - getreg32(config->base + SAM_MCAN_TXBCR_OFFSET), - getreg32(config->base + SAM_MCAN_TXBTO_OFFSET), - getreg32(config->base + SAM_MCAN_TXBCF_OFFSET), - getreg32(config->base + SAM_MCAN_TXBTIE_OFFSET)); + caninfo(" TXBCR: %08x TXBTO: %08x TXBCF: %08x TXBTIE: %08x\n", + getreg32(config->base + SAM_MCAN_TXBCR_OFFSET), + getreg32(config->base + SAM_MCAN_TXBTO_OFFSET), + getreg32(config->base + SAM_MCAN_TXBCF_OFFSET), + getreg32(config->base + SAM_MCAN_TXBTIE_OFFSET)); - _llerr("TXBCIE: %08x TXEFC: %08x TXEFS: %08x TXEFA: %08x\n", - getreg32(config->base + SAM_MCAN_TXBCIE_OFFSET), - getreg32(config->base + SAM_MCAN_TXEFC_OFFSET), - getreg32(config->base + SAM_MCAN_TXEFS_OFFSET), - getreg32(config->base + SAM_MCAN_TXEFA_OFFSET)); + caninfo("TXBCIE: %08x TXEFC: %08x TXEFS: %08x TXEFA: %08x\n", + getreg32(config->base + SAM_MCAN_TXBCIE_OFFSET), + getreg32(config->base + SAM_MCAN_TXEFC_OFFSET), + getreg32(config->base + SAM_MCAN_TXEFS_OFFSET), + getreg32(config->base + SAM_MCAN_TXEFA_OFFSET)); } #endif @@ -2205,7 +2205,7 @@ static int mcan_setup(FAR struct can_dev_s *dev) ret = mcan_hw_initialize(priv); if (ret < 0) { - canllerr("MCAN%d H/W initialization failed: %d\n", config->port, ret); + canllerr("ERROR: MCAN%d H/W initialization failed: %d\n", config->port, ret); return ret; } @@ -2216,7 +2216,7 @@ static int mcan_setup(FAR struct can_dev_s *dev) ret = irq_attach(config->irq0, config->handler); if (ret < 0) { - canllerr("Failed to attach MCAN%d line 0 IRQ (%d)", + canllerr("ERROR: Failed to attach MCAN%d line 0 IRQ (%d)", config->port, config->irq0); return ret; } @@ -2224,7 +2224,7 @@ static int mcan_setup(FAR struct can_dev_s *dev) ret = irq_attach(config->irq1, config->handler); if (ret < 0) { - canllerr("Failed to attach MCAN%d line 1 IRQ (%d)", + canllerr("ERROR: Failed to attach MCAN%d line 1 IRQ (%d)", config->port, config->irq1); return ret; } diff --git a/arch/arm/src/samv7/sam_qspi.c b/arch/arm/src/samv7/sam_qspi.c index 569f374702..b90a515d8b 100644 --- a/arch/arm/src/samv7/sam_qspi.c +++ b/arch/arm/src/samv7/sam_qspi.c @@ -85,6 +85,10 @@ # define CONFIG_SAMV7_QSPI_DLYBCT 0 #endif +#ifndef CONFIG_DEBUG_SPI_INFO +# undef CONFIG_SAMV7_QSPI_REGDEBUG +#endif + /* When QSPI DMA is enabled, small DMA transfers will still be performed by * polling logic. But we need a threshold value to determine what is small. * That value is provided by CONFIG_SAMV7_QSPI_DMATHRESHOLD. @@ -374,7 +378,7 @@ static bool qspi_checkreg(struct sam_qspidev_s *priv, bool wr, uint32_t value, { /* Yes... show how many times we did it */ - _llerr("...[Repeats %d times]...\n", priv->ntimes); + spiinfo("...[Repeats %d times]...\n", priv->ntimes); } /* Save information about the new access */ @@ -408,7 +412,7 @@ static inline uint32_t qspi_getreg(struct sam_qspidev_s *priv, #ifdef CONFIG_SAMV7_QSPI_REGDEBUG if (qspi_checkreg(priv, false, value, address)) { - _llerr("%08x->%08x\n", address, value); + spiinfo("%08x->%08x\n", address, value); } #endif @@ -431,7 +435,7 @@ static inline void qspi_putreg(struct sam_qspidev_s *priv, uint32_t value, #ifdef CONFIG_SAMV7_QSPI_REGDEBUG if (qspi_checkreg(priv, true, value, address)) { - _llerr("%08x<-%08x\n", address, value); + spiinfo("%08x<-%08x\n", address, value); } #endif diff --git a/arch/arm/src/samv7/sam_rswdt.c b/arch/arm/src/samv7/sam_rswdt.c index 3723a0bc83..980ecd5b03 100644 --- a/arch/arm/src/samv7/sam_rswdt.c +++ b/arch/arm/src/samv7/sam_rswdt.c @@ -57,6 +57,11 @@ * Pre-processor Definitions ****************************************************************************/ /* Configuration ************************************************************/ + +#ifndef CONFIG_DEBUG_WATCHDOG_INFO +# undef CONFIG_SAMV7_RSWDT_REGDEBUG +#endif + /* The Watchdog Timer uses the Slow Clock divided by 128 to establish the * maximum Watchdog period to be 16 seconds (with a typical Slow Clock of * 32768 kHz). @@ -104,7 +109,7 @@ struct sam_lowerhalf_s ****************************************************************************/ /* Register operations ******************************************************/ -#if defined(CONFIG_SAMV7_RSWDT_REGDEBUG) && defined(CONFIG_DEBUG_FEATURES) +#ifdef CONFIG_SAMV7_RSWDT_REGDEBUG static uint32_t sam_getreg(uintptr_t regaddr); static void sam_putreg(uint32_t regval, uintptr_t regaddr); #else @@ -164,7 +169,7 @@ static struct sam_lowerhalf_s g_wdtdev; * ****************************************************************************/ -#if defined(CONFIG_SAMV7_RSWDT_REGDEBUG) && defined(CONFIG_DEBUG_FEATURES) +#ifdef CONFIG_SAMV7_RSWDT_REGDEBUG static uint32_t sam_getreg(uintptr_t regaddr) { static uint32_t prevaddr = 0; @@ -185,7 +190,7 @@ static uint32_t sam_getreg(uintptr_t regaddr) { if (count == 4) { - _llerr("...\n"); + wdinfo("...\n"); } return regval; @@ -202,7 +207,7 @@ static uint32_t sam_getreg(uintptr_t regaddr) { /* Yes.. then show how many times the value repeated */ - _llerr("[repeats %d more times]\n", count-3); + wdinfo("[repeats %d more times]\n", count-3); } /* Save the new address, value, and count */ @@ -214,7 +219,7 @@ static uint32_t sam_getreg(uintptr_t regaddr) /* Show the register value read */ - _llerr("%08x->%048\n", regaddr, regval); + wdinfo("%08x->%048\n", regaddr, regval); return regval; } #endif @@ -227,12 +232,12 @@ static uint32_t sam_getreg(uintptr_t regaddr) * ****************************************************************************/ -#if defined(CONFIG_SAMV7_RSWDT_REGDEBUG) && defined(CONFIG_DEBUG_FEATURES) +#ifdef CONFIG_SAMV7_RSWDT_REGDEBUG static void sam_putreg(uint32_t regval, uintptr_t regaddr) { /* Show the register value being written */ - _llerr("%08x<-%08x\n", regaddr, regval); + wdinfo("%08x<-%08x\n", regaddr, regval); /* Write the value */ @@ -449,7 +454,7 @@ static int sam_settimeout(FAR struct watchdog_lowerhalf_s *lower, if (timeout < RSWDT_MINTIMEOUT || timeout >= RSWDT_MAXTIMEOUT) { - wderr("Cannot represent timeout: %d < %d > %d\n", + wderr("ERROR: Cannot represent timeout: %d < %d > %d\n", RSWDT_MINTIMEOUT, timeout, RSWDT_MAXTIMEOUT); return -ERANGE; } diff --git a/arch/arm/src/samv7/sam_spi.c b/arch/arm/src/samv7/sam_spi.c index 7af29d3a70..34caed374c 100644 --- a/arch/arm/src/samv7/sam_spi.c +++ b/arch/arm/src/samv7/sam_spi.c @@ -105,6 +105,14 @@ # undef CONFIG_SAMV7_SPI_DMADEBUG #endif +#ifndef CONFIG_DEBUG_DMA_INFO +# undef CONFIG_SAMV7_SPI_DMADEBUG +#endif + +#ifndef CONFIG_DEBUG_SPI_INFO +# undef CONFIG_SAMV7_SPI_REGDEBUG +#endif + /* Clocking *****************************************************************/ /* The SPI Baud rate clock is generated by dividing the peripheral clock by * a value between 1 and 255 @@ -428,7 +436,7 @@ static bool spi_checkreg(struct sam_spidev_s *spi, bool wr, uint32_t value, { /* Yes... show how many times we did it */ - _llerr("...[Repeats %d times]...\n", spi->ntimes); + spiinfo("...[Repeats %d times]...\n", spi->ntimes); } /* Save information about the new access */ @@ -462,7 +470,7 @@ static inline uint32_t spi_getreg(struct sam_spidev_s *spi, #ifdef CONFIG_SAMV7_SPI_REGDEBUG if (spi_checkreg(spi, false, value, address)) { - _llerr("%08x->%08x\n", address, value); + spiinfo("%08x->%08x\n", address, value); } #endif @@ -485,7 +493,7 @@ static inline void spi_putreg(struct sam_spidev_s *spi, uint32_t value, #ifdef CONFIG_SAMV7_SPI_REGDEBUG if (spi_checkreg(spi, true, value, address)) { - _llerr("%08x<-%08x\n", address, value); + spiinfo("%08x<-%08x\n", address, value); } #endif @@ -1089,7 +1097,7 @@ static uint32_t spi_setfrequency(struct spi_dev_s *dev, uint32_t frequency) spics->frequency = frequency; spics->actual = actual; - spierr("Frequency %d->%d\n", frequency, actual); + spiinfo("Frequency %d->%d\n", frequency, actual); return actual; } diff --git a/arch/arm/src/samv7/sam_spi_slave.c b/arch/arm/src/samv7/sam_spi_slave.c index 574b5ab0bf..d2856cd2e9 100644 --- a/arch/arm/src/samv7/sam_spi_slave.c +++ b/arch/arm/src/samv7/sam_spi_slave.c @@ -74,6 +74,10 @@ # define CONFIG_SAMV7_SPI_SLAVE_QSIZE 8 #endif +#ifndef CONFIG_DEBUG_SPI_INFO +# undef CONFIG_SAMV7_SPI_REGDEBUG +#endif + /**************************************************************************** * Private Types ****************************************************************************/ @@ -248,7 +252,7 @@ static bool spi_checkreg(struct sam_spidev_s *priv, bool wr, uint32_t value, { /* Yes... show how many times we did it */ - _llerr("...[Repeats %d times]...\n", priv->ntimes); + spiinfo("...[Repeats %d times]...\n", priv->ntimes); } /* Save information about the new access */ @@ -281,7 +285,7 @@ static uint32_t spi_getreg(struct sam_spidev_s *priv, unsigned int offset) #ifdef CONFIG_SAMV7_SPI_REGDEBUG if (spi_checkreg(priv, false, value, address)) { - _llerr("%08x->%08x\n", address, value); + spiinfo("%08x->%08x\n", address, value); } #endif @@ -304,7 +308,7 @@ static void spi_putreg(struct sam_spidev_s *priv, uint32_t value, #ifdef CONFIG_SAMV7_SPI_REGDEBUG if (spi_checkreg(priv, true, value, address)) { - _llerr("%08x<-%08x\n", address, value); + spiinfo("%08x<-%08x\n", address, value); } #endif @@ -442,7 +446,7 @@ static int spi_interrupt(struct sam_spidev_s *priv) { /* If debug is enabled, report any overrun errors */ - spierr("Error: Overrun (OVRES): %08x\n", pending); + spierr("ERROR: Overrun (OVRES): %08x\n", pending); /* OVRES was cleared by the status read. */ } @@ -509,7 +513,7 @@ static int spi_interrupt(struct sam_spidev_s *priv) { /* If debug is enabled, report any overrun errors */ - spierr("Error: Underrun (UNDEX): %08x\n", pending); + spierr("ERROR: Underrun (UNDEX): %08x\n", pending); /* UNDES was cleared by the status read. */ } diff --git a/arch/arm/src/samv7/sam_ssc.c b/arch/arm/src/samv7/sam_ssc.c index eb21113bd3..c07d554258 100644 --- a/arch/arm/src/samv7/sam_ssc.c +++ b/arch/arm/src/samv7/sam_ssc.c @@ -91,6 +91,10 @@ # define CONFIG_SAMV7_SSC_MAXINFLIGHT 16 #endif +#ifndef CONFIG_DEBUG_I2S_INFO +# undef CONFIG_SAMV7_SSC_REGDEBUG +#endif + /* Assume no RX/TX support until we learn better */ #undef SSC_HAVE_RX @@ -674,7 +678,7 @@ static bool ssc_checkreg(struct sam_ssc_s *priv, bool wr, uint32_t regval, { /* Yes... show how many times we did it */ - _llerr("...[Repeats %d times]...\n", priv->count); + i2sinfo("...[Repeats %d times]...\n", priv->count); } /* Save information about the new access */ @@ -708,7 +712,7 @@ static inline uint32_t ssc_getreg(struct sam_ssc_s *priv, #ifdef CONFIG_SAMV7_SSC_REGDEBUG if (ssc_checkreg(priv, false, regval, regaddr)) { - _llerr("%08x->%08x\n", regaddr, regval); + i2sinfo("%08x->%08x\n", regaddr, regval); } #endif @@ -731,7 +735,7 @@ static inline void ssc_putreg(struct sam_ssc_s *priv, unsigned int offset, #ifdef CONFIG_SAMV7_SSC_REGDEBUG if (ssc_checkreg(priv, true, regval, regaddr)) { - _llerr("%08x<-%08x\n", regaddr, regval); + i2sinfo("%08x<-%08x\n", regaddr, regval); } #endif @@ -1060,7 +1064,7 @@ static void ssc_dma_sampleinit(struct sam_ssc_s *priv, #if defined(CONFIG_SAMV7_SSC_DMADEBUG) && defined(SSC_HAVE_RX) static void ssc_rxdma_sampledone(struct sam_ssc_s *priv, int result) { - _llerr("result: %d\n", result); + i2sinfo("result: %d\n", result); /* Sample the final registers */ @@ -1125,7 +1129,7 @@ static void ssc_rxdma_sampledone(struct sam_ssc_s *priv, int result) #if defined(CONFIG_SAMV7_SSC_DMADEBUG) && defined(SSC_HAVE_TX) static void ssc_txdma_sampledone(struct sam_ssc_s *priv, int result) { - _llerr("result: %d\n", result); + i2sinfo("result: %d\n", result); /* Sample the final registers */ diff --git a/arch/arm/src/samv7/sam_tc.c b/arch/arm/src/samv7/sam_tc.c index 4eba2f077b..98c5347a8c 100644 --- a/arch/arm/src/samv7/sam_tc.c +++ b/arch/arm/src/samv7/sam_tc.c @@ -77,6 +77,10 @@ * Pre-processor Definitions ****************************************************************************/ +#ifndef CONFIG_DEBUG_TIMER_INFO +# undef CONFIG_SAMV7_TC_REGDEBUG +#endif + /**************************************************************************** * Private Types ****************************************************************************/ @@ -643,19 +647,19 @@ static void sam_regdump(struct sam_chan_s *chan, const char *msg) uintptr_t base; base = tc->base; - _llerr("TC%d [%08x]: %s\n", tc->tc, (int)base, msg); - _llerr(" BMR: %08x QIMR: %08x QISR: %08x WPMR: %08x\n", - getreg32(base+SAM_TC_BMR_OFFSET), getreg32(base+SAM_TC_QIMR_OFFSET), - getreg32(base+SAM_TC_QISR_OFFSET), getreg32(base+SAM_TC_WPMR_OFFSET)); + tmrinfo("TC%d [%08x]: %s\n", tc->tc, (int)base, msg); + tmrinfo(" BMR: %08x QIMR: %08x QISR: %08x WPMR: %08x\n", + getreg32(base+SAM_TC_BMR_OFFSET), getreg32(base+SAM_TC_QIMR_OFFSET), + getreg32(base+SAM_TC_QISR_OFFSET), getreg32(base+SAM_TC_WPMR_OFFSET)); base = chan->base; - _llerr("TC%d Channel %d [%08x]: %s\n", tc->tc, chan->chan, (int)base, msg); - _llerr(" CMR: %08x SSMR: %08x RAB: %08x CV: %08x\n", - getreg32(base+SAM_TC_CMR_OFFSET), getreg32(base+SAM_TC_SMMR_OFFSET), - getreg32(base+SAM_TC_RAB_OFFSET), getreg32(base+SAM_TC_CV_OFFSET)); - _llerr(" RA: %08x RB: %08x RC: %08x IMR: %08x\n", - getreg32(base+SAM_TC_RA_OFFSET), getreg32(base+SAM_TC_RB_OFFSET), - getreg32(base+SAM_TC_RC_OFFSET), getreg32(base+SAM_TC_IMR_OFFSET)); + tmrinfo("TC%d Channel %d [%08x]: %s\n", tc->tc, chan->chan, (int)base, msg); + tmrinfo(" CMR: %08x SSMR: %08x RAB: %08x CV: %08x\n", + getreg32(base+SAM_TC_CMR_OFFSET), getreg32(base+SAM_TC_SMMR_OFFSET), + getreg32(base+SAM_TC_RAB_OFFSET), getreg32(base+SAM_TC_CV_OFFSET)); + tmrinfo(" RA: %08x RB: %08x RC: %08x IMR: %08x\n", + getreg32(base+SAM_TC_RA_OFFSET), getreg32(base+SAM_TC_RB_OFFSET), + getreg32(base+SAM_TC_RC_OFFSET), getreg32(base+SAM_TC_IMR_OFFSET)); } #endif @@ -698,7 +702,7 @@ static bool sam_checkreg(struct sam_tc_s *tc, bool wr, uint32_t regaddr, { /* Yes... show how many times we did it */ - _llerr("...[Repeats %d times]...\n", tc->ntimes); + tmrinfo("...[Repeats %d times]...\n", tc->ntimes); } /* Save information about the new access */ @@ -733,7 +737,7 @@ static inline uint32_t sam_tc_getreg(struct sam_chan_s *chan, #ifdef CONFIG_SAMV7_TC_REGDEBUG if (sam_checkreg(tc, false, regaddr, regval)) { - _llerr("%08x->%08x\n", regaddr, regval); + tmrinfo("%08x->%08x\n", regaddr, regval); } #endif @@ -757,7 +761,7 @@ static inline void sam_tc_putreg(struct sam_chan_s *chan, uint32_t regval, #ifdef CONFIG_SAMV7_TC_REGDEBUG if (sam_checkreg(tc, true, regaddr, regval)) { - _llerr("%08x<-%08x\n", regaddr, regval); + tmrinfo("%08x<-%08x\n", regaddr, regval); } #endif @@ -781,7 +785,7 @@ static inline uint32_t sam_chan_getreg(struct sam_chan_s *chan, #ifdef CONFIG_SAMV7_TC_REGDEBUG if (sam_checkreg(chan->tc, false, regaddr, regval)) { - _llerr("%08x->%08x\n", regaddr, regval); + tmrinfo("%08x->%08x\n", regaddr, regval); } #endif @@ -804,7 +808,7 @@ static inline void sam_chan_putreg(struct sam_chan_s *chan, unsigned int offset, #ifdef CONFIG_SAMV7_TC_REGDEBUG if (sam_checkreg(chan->tc, true, regaddr, regval)) { - _llerr("%08x<-%08x\n", regaddr, regval); + tmrinfo("%08x<-%08x\n", regaddr, regval); } #endif @@ -1066,7 +1070,7 @@ static int sam_tc_mcksrc(uint32_t frequency, uint32_t *tcclks, { /* If no divisor can be found, return -ERANGE */ - tmrerr("Lower bound search failed\n"); + tmrerr("ERROR: Lower bound search failed\n"); return -ERANGE; } @@ -1225,7 +1229,7 @@ static inline struct sam_chan_s *sam_tc_initialize(int channel) { /* Yes.. return a failure */ - tmrerr("Channel %d is in-use\n", channel); + tmrerr("ERROR: Channel %d is in-use\n", channel); sam_givesem(tc); return NULL; } diff --git a/arch/arm/src/samv7/sam_twihs.c b/arch/arm/src/samv7/sam_twihs.c index 4dc6fcae9b..93d59f2a87 100644 --- a/arch/arm/src/samv7/sam_twihs.c +++ b/arch/arm/src/samv7/sam_twihs.c @@ -91,6 +91,10 @@ # define CONFIG_SAMV7_TWIHS2_FREQUENCY 100000 #endif +#ifndef CONFIG_DEBUG_I2C_INFO +# undef CONFIG_SAMV7_TWIHSHS_REGDEBUG +#endif + /* Driver internal definitions *************************************************/ /* If verbose I2C debug output is enable, then allow more time before we declare * a timeout. The debug output from twi_interrupt will really slow things down! @@ -349,7 +353,7 @@ static bool twi_checkreg(struct twi_dev_s *priv, bool wr, uint32_t value, { /* Yes... show how many times we did it */ - _llerr("...[Repeats %d times]...\n", priv->ntimes); + i2cinfo("...[Repeats %d times]...\n", priv->ntimes); } /* Save information about the new access */ @@ -381,7 +385,7 @@ static uint32_t twi_getabs(struct twi_dev_s *priv, uintptr_t address) if (twi_checkreg(priv, false, value, address)) { - _llerr("%08x->%08x\n", address, value); + i2cinfo("%08x->%08x\n", address, value); } return value; @@ -402,7 +406,7 @@ static void twi_putabs(struct twi_dev_s *priv, uintptr_t address, { if (twi_checkreg(priv, true, value, address)) { - _llerr("%08x<-%08x\n", address, value); + i2cinfo("%08x<-%08x\n", address, value); } putreg32(value, address); diff --git a/arch/arm/src/samv7/sam_usbdevhs.c b/arch/arm/src/samv7/sam_usbdevhs.c index 43a86c0e79..e7660280b6 100644 --- a/arch/arm/src/samv7/sam_usbdevhs.c +++ b/arch/arm/src/samv7/sam_usbdevhs.c @@ -90,6 +90,10 @@ # define CONFIG_USBDEV_EP0_MAXSIZE 64 #endif +#ifndef CONFIG_DEBUG_USB_INFO +# undef CONFIG_SAMV7_USBHS_REGDEBUG +#endif + /* Number of DMA transfer descriptors. Default: 8 */ #ifndef CONFIG_SAMV7_USBDEVHS_NDTDS @@ -108,14 +112,6 @@ # warning CONFIG_USBDEV_DUALSPEED should be defined for high speed support #endif -/* Extremely detailed register debug that you would normally never want - * enabled. - */ - -#ifndef CONFIG_DEBUG_FEATURES -# undef CONFIG_SAMV7_USBHS_REGDEBUG -#endif - /* Not yet supported */ #undef CONFIG_SAMV7_USBDEVHS_SCATTERGATHER @@ -721,10 +717,6 @@ const struct trace_msg_t g_usb_trace_strings_intdecode[] = }; #endif -/**************************************************************************** - * Public Data - ****************************************************************************/ - /**************************************************************************** * Private Private Functions ****************************************************************************/ @@ -732,6 +724,7 @@ const struct trace_msg_t g_usb_trace_strings_intdecode[] = /**************************************************************************** * Register Operations ****************************************************************************/ + /**************************************************************************** * Name: sam_printreg * @@ -743,7 +736,7 @@ const struct trace_msg_t g_usb_trace_strings_intdecode[] = #ifdef CONFIG_SAMV7_USBHS_REGDEBUG static void sam_printreg(uintptr_t regaddr, uint32_t regval, bool iswrite) { - _llerr("%p%s%08x\n", regaddr, iswrite ? "<-" : "->", regval); + uinfo("%p%s%08x\n", regaddr, iswrite ? "<-" : "->", regval); } #endif @@ -794,7 +787,7 @@ static void sam_checkreg(uintptr_t regaddr, uint32_t regval, bool iswrite) { /* No.. More than one. */ - _llerr("[repeats %d more times]\n", count); + uinfo("[repeats %d more times]\n", count); } } @@ -869,36 +862,36 @@ static inline void sam_putreg(uint32_t regval, uint32_t regaddr) * Name: sam_dumpep ****************************************************************************/ -#if defined(CONFIG_SAMV7_USBHS_REGDEBUG) && defined(CONFIG_DEBUG_FEATURES) +#ifdef CONFIG_SAMV7_USBHS_REGDEBUG static void sam_dumpep(struct sam_usbdev_s *priv, int epno) { /* Global Registers */ - _llerr("Global Register:\n"); - _llerr(" CTRL: %08x\n", sam_getreg(SAM_USBHS_DEVCTRL)); - _llerr(" ISR: %08x\n", sam_getreg(SAM_USBHS_DEVISR)); - _llerr(" IMR: %08x\n", sam_getreg(SAM_USBHS_DEVIMR)); - _llerr(" EPT: %08x\n", sam_getreg(SAM_USBHS_DEVEPT)); - _llerr(" FNUM: %08x\n", sam_getreg(SAM_USBHS_DEVFNUM)); + uinfo("Global Register:\n"); + uinfo(" CTRL: %08x\n", sam_getreg(SAM_USBHS_DEVCTRL)); + uinfo(" ISR: %08x\n", sam_getreg(SAM_USBHS_DEVISR)); + uinfo(" IMR: %08x\n", sam_getreg(SAM_USBHS_DEVIMR)); + uinfo(" EPT: %08x\n", sam_getreg(SAM_USBHS_DEVEPT)); + uinfo(" FNUM: %08x\n", sam_getreg(SAM_USBHS_DEVFNUM)); /* Endpoint registers */ - _llerr("Endpoint %d Register:\n", epno); - _llerr(" CFG: %08x\n", sam_getreg(SAM_USBHS_DEVEPTCFG(epno))); - _llerr(" ISR: %08x\n", sam_getreg(SAM_USBHS_DEVEPTISR(epno))); - _llerr(" IMR: %08x\n", sam_getreg(SAM_USBHS_DEVEPTIMR(epno))); + uinfo("Endpoint %d Register:\n", epno); + uinfo(" CFG: %08x\n", sam_getreg(SAM_USBHS_DEVEPTCFG(epno))); + uinfo(" ISR: %08x\n", sam_getreg(SAM_USBHS_DEVEPTISR(epno))); + uinfo(" IMR: %08x\n", sam_getreg(SAM_USBHS_DEVEPTIMR(epno))); - _llerr("DMA %d Register:\n", epno); + uinfo("DMA %d Register:\n", epno); if ((SAM_EPSET_DMA & SAM_EP_BIT(epno)) != 0) { - _llerr(" NXTDSC: %08x\n", sam_getreg(SAM_USBHS_DEVDMANXTDSC(epno))); - _llerr(" ADDRESS: %08x\n", sam_getreg(SAM_USBHS_DEVDMAADDR(epno))); - _llerr(" CONTROL: %08x\n", sam_getreg(SAM_USBHS_DEVDMACTRL(epno))); - _llerr(" STATUS: %08x\n", sam_getreg(SAM_USBHS_DEVDMASTA(epno))); + uinfo(" NXTDSC: %08x\n", sam_getreg(SAM_USBHS_DEVDMANXTDSC(epno))); + uinfo(" ADDRESS: %08x\n", sam_getreg(SAM_USBHS_DEVDMAADDR(epno))); + uinfo(" CONTROL: %08x\n", sam_getreg(SAM_USBHS_DEVDMACTRL(epno))); + uinfo(" STATUS: %08x\n", sam_getreg(SAM_USBHS_DEVDMASTA(epno))); } else { - _llerr(" None\n"); + uinfo(" None\n"); } } #endif diff --git a/arch/arm/src/samv7/sam_wdt.c b/arch/arm/src/samv7/sam_wdt.c index d8c870b1f6..d317bbd74d 100644 --- a/arch/arm/src/samv7/sam_wdt.c +++ b/arch/arm/src/samv7/sam_wdt.c @@ -57,6 +57,11 @@ * Pre-processor Definitions ****************************************************************************/ /* Configuration ************************************************************/ + +#ifndef CONFIG_DEBUG_WATCHDOG_INFO +# undef CONFIG_SAMV7_WDT_REGDEBUG +#endif + /* The Watchdog Timer uses the Slow Clock divided by 128 to establish the * maximum Watchdog period to be 16 seconds (with a typical Slow Clock of * 32768 kHz). @@ -104,7 +109,7 @@ struct sam_lowerhalf_s ****************************************************************************/ /* Register operations ******************************************************/ -#if defined(CONFIG_SAMV7_WDT_REGDEBUG) && defined(CONFIG_DEBUG_FEATURES) +#ifdef CONFIG_SAMV7_WDT_REGDEBUG static uint32_t sam_getreg(uintptr_t regaddr); static void sam_putreg(uint32_t regval, uintptr_t regaddr); #else @@ -164,7 +169,7 @@ static struct sam_lowerhalf_s g_wdtdev; * ****************************************************************************/ -#if defined(CONFIG_SAMV7_WDT_REGDEBUG) && defined(CONFIG_DEBUG_FEATURES) +#ifdef CONFIG_SAMV7_WDT_REGDEBUG static uint32_t sam_getreg(uintptr_t regaddr) { static uint32_t prevaddr = 0; @@ -185,7 +190,7 @@ static uint32_t sam_getreg(uintptr_t regaddr) { if (count == 4) { - _llerr("...\n"); + wdinfo("...\n"); } return regval; @@ -202,7 +207,7 @@ static uint32_t sam_getreg(uintptr_t regaddr) { /* Yes.. then show how many times the value repeated */ - _llerr("[repeats %d more times]\n", count-3); + wdinfo("[repeats %d more times]\n", count-3); } /* Save the new address, value, and count */ @@ -214,7 +219,7 @@ static uint32_t sam_getreg(uintptr_t regaddr) /* Show the register value read */ - _llerr("%08x->%048\n", regaddr, regval); + wdinfo("%08x->%048\n", regaddr, regval); return regval; } #endif @@ -227,12 +232,12 @@ static uint32_t sam_getreg(uintptr_t regaddr) * ****************************************************************************/ -#if defined(CONFIG_SAMV7_WDT_REGDEBUG) && defined(CONFIG_DEBUG_FEATURES) +#ifdef CONFIG_SAMV7_WDT_REGDEBUG static void sam_putreg(uint32_t regval, uintptr_t regaddr) { /* Show the register value being written */ - _llerr("%08x<-%08x\n", regaddr, regval); + wdinfo("%08x<-%08x\n", regaddr, regval); /* Write the value */ @@ -449,7 +454,7 @@ static int sam_settimeout(FAR struct watchdog_lowerhalf_s *lower, if (timeout < WDT_MINTIMEOUT || timeout >= WDT_MAXTIMEOUT) { - wderr("Cannot represent timeout: %d < %d > %d\n", + wderr("ERROR: Cannot represent timeout: %d < %d > %d\n", WDT_MINTIMEOUT, timeout, WDT_MAXTIMEOUT); return -ERANGE; } diff --git a/arch/arm/src/samv7/sam_xdmac.c b/arch/arm/src/samv7/sam_xdmac.c index 2666457a40..8835b0386d 100644 --- a/arch/arm/src/samv7/sam_xdmac.c +++ b/arch/arm/src/samv7/sam_xdmac.c @@ -551,7 +551,7 @@ static uint8_t sam_channel(uint8_t pid, const struct sam_pidmap_s *table, } } - dmaerr("No channel found for pid %d\n", pid); + dmaerr("ERROR: No channel found for pid %d\n", pid); DEBUGPANIC(); return 0x3f; } @@ -2017,7 +2017,7 @@ void sam_dmastop(DMA_HANDLE handle) * ****************************************************************************/ -#ifdef CONFIG_DEBUG_DMA +#ifdef CONFIG_DEBUG_DMA_INFO void sam_dmasample(DMA_HANDLE handle, struct sam_dmaregs_s *regs) { struct sam_xdmach_s *xdmach = (struct sam_xdmach_s *)handle; @@ -2057,7 +2057,7 @@ void sam_dmasample(DMA_HANDLE handle, struct sam_dmaregs_s *regs) leave_critical_section(flags); } -#endif /* CONFIG_DEBUG_DMA */ +#endif /* CONFIG_DEBUG_DMA_INFO */ /**************************************************************************** * Name: sam_dmadump @@ -2070,34 +2070,34 @@ void sam_dmasample(DMA_HANDLE handle, struct sam_dmaregs_s *regs) * ****************************************************************************/ -#ifdef CONFIG_DEBUG_DMA +#ifdef CONFIG_DEBUG_DMA_INFO void sam_dmadump(DMA_HANDLE handle, const struct sam_dmaregs_s *regs, const char *msg) { struct sam_xdmach_s *xdmach = (struct sam_xdmach_s *)handle; - dmaerr("%s\n", msg); - dmaerr(" DMA Global Registers:\n"); - dmaerr(" GTYPE[%08x]: %08x\n", SAM_XDMAC_GTYPE, regs->gtype); - dmaerr(" GCFG[%08x]: %08x\n", SAM_XDMAC_GCFG, regs->gcfg); - dmaerr(" GWAC[%08x]: %08x\n", SAM_XDMAC_GWAC, regs->gwac); - dmaerr(" GIM[%08x]: %08x\n", SAM_XDMAC_GIM, regs->gim); - dmaerr(" GS[%08x]: %08x\n", SAM_XDMAC_GS, regs->gs); - dmaerr(" GRS[%08x]: %08x\n", SAM_XDMAC_GRS, regs->grs); - dmaerr(" GWS[%08x]: %08x\n", SAM_XDMAC_GWS, regs->gws); - dmaerr(" GSWS[%08x]: %08x\n", SAM_XDMAC_GSWS, regs->gsws); - dmaerr(" DMA Channel Registers:\n"); - dmaerr(" CIM[%08x]: %08x\n", xdmach->base + SAM_XDMACH_CIM_OFFSET, regs->cim); - dmaerr(" CSA[%08x]: %08x\n", xdmach->base + SAM_XDMACH_CSA_OFFSET, regs->csa); - dmaerr(" CDA[%08x]: %08x\n", xdmach->base + SAM_XDMACH_CDA_OFFSET, regs->cda); - dmaerr(" CNDA[%08x]: %08x\n", xdmach->base + SAM_XDMACH_CNDA_OFFSET, regs->cnda); - dmaerr(" CNDC[%08x]: %08x\n", xdmach->base + SAM_XDMACH_CNDC_OFFSET, regs->cndc); - dmaerr(" CUBC[%08x]: %08x\n", xdmach->base + SAM_XDMACH_CUBC_OFFSET, regs->cubc); - dmaerr(" CBC[%08x]: %08x\n", xdmach->base + SAM_XDMACH_CBC_OFFSET, regs->cbc); - dmaerr(" CC[%08x]: %08x\n", xdmach->base + SAM_XDMACH_CC_OFFSET, regs->cc); - dmaerr(" CDSMSP[%08x]: %08x\n", xdmach->base + SAM_XDMACH_CDSMSP_OFFSET, regs->cdsmsp); - dmaerr(" CSUS[%08x]: %08x\n", xdmach->base + SAM_XDMACH_CSUS_OFFSET, regs->csus); - dmaerr(" CDUS[%08x]: %08x\n", xdmach->base + SAM_XDMACH_CDUS_OFFSET, regs->cdus); + dmainfo("%s\n", msg); + dmainfo(" DMA Global Registers:\n"); + dmainfo(" GTYPE[%08x]: %08x\n", SAM_XDMAC_GTYPE, regs->gtype); + dmainfo(" GCFG[%08x]: %08x\n", SAM_XDMAC_GCFG, regs->gcfg); + dmainfo(" GWAC[%08x]: %08x\n", SAM_XDMAC_GWAC, regs->gwac); + dmainfo(" GIM[%08x]: %08x\n", SAM_XDMAC_GIM, regs->gim); + dmainfo(" GS[%08x]: %08x\n", SAM_XDMAC_GS, regs->gs); + dmainfo(" GRS[%08x]: %08x\n", SAM_XDMAC_GRS, regs->grs); + dmainfo(" GWS[%08x]: %08x\n", SAM_XDMAC_GWS, regs->gws); + dmainfo(" GSWS[%08x]: %08x\n", SAM_XDMAC_GSWS, regs->gsws); + dmainfo(" DMA Channel Registers:\n"); + dmainfo(" CIM[%08x]: %08x\n", xdmach->base + SAM_XDMACH_CIM_OFFSET, regs->cim); + dmainfo(" CSA[%08x]: %08x\n", xdmach->base + SAM_XDMACH_CSA_OFFSET, regs->csa); + dmainfo(" CDA[%08x]: %08x\n", xdmach->base + SAM_XDMACH_CDA_OFFSET, regs->cda); + dmainfo(" CNDA[%08x]: %08x\n", xdmach->base + SAM_XDMACH_CNDA_OFFSET, regs->cnda); + dmainfo(" CNDC[%08x]: %08x\n", xdmach->base + SAM_XDMACH_CNDC_OFFSET, regs->cndc); + dmainfo(" CUBC[%08x]: %08x\n", xdmach->base + SAM_XDMACH_CUBC_OFFSET, regs->cubc); + dmainfo(" CBC[%08x]: %08x\n", xdmach->base + SAM_XDMACH_CBC_OFFSET, regs->cbc); + dmainfo(" CC[%08x]: %08x\n", xdmach->base + SAM_XDMACH_CC_OFFSET, regs->cc); + dmainfo(" CDSMSP[%08x]: %08x\n", xdmach->base + SAM_XDMACH_CDSMSP_OFFSET, regs->cdsmsp); + dmainfo(" CSUS[%08x]: %08x\n", xdmach->base + SAM_XDMACH_CSUS_OFFSET, regs->csus); + dmainfo(" CDUS[%08x]: %08x\n", xdmach->base + SAM_XDMACH_CDUS_OFFSET, regs->cdus); } -#endif /* CONFIG_DEBUG_DMA */ +#endif /* CONFIG_DEBUG_DMA_INFO */ #endif /* CONFIG_SAMV7_XDMAC */ diff --git a/arch/arm/src/samv7/sam_xdmac.h b/arch/arm/src/samv7/sam_xdmac.h index 775591f94a..cfbf14fe0d 100644 --- a/arch/arm/src/samv7/sam_xdmac.h +++ b/arch/arm/src/samv7/sam_xdmac.h @@ -50,12 +50,6 @@ * Pre-processor Definitions ************************************************************************************/ -/* Configuration ********************************************************************/ - -#ifndef CONFIG_DEBUG_FEATURES -# undef CONFIG_DEBUG_DMA -#endif - /* DMA ******************************************************************************/ /* Flags used to characterize the DMA channel. The naming convention is that one @@ -172,7 +166,7 @@ typedef void (*dma_callback_t)(DMA_HANDLE handle, void *arg, int result); /* The following is used for sampling DMA registers when CONFIG DEBUG_DMA is selected */ -#ifdef CONFIG_DEBUG_DMA +#ifdef CONFIG_DEBUG_DMA_INFO struct sam_dmaregs_s { /* Global Registers. @@ -210,7 +204,7 @@ struct sam_dmaregs_s uint32_t csus; /* Channel Source Microblock Stride */ uint32_t cdus; /* Channel Destination Microblock Stride */ }; -#endif /* CONFIG_DEBUG_DMA */ +#endif /* CONFIG_DEBUG_DMA_INFO */ /************************************************************************************ * Inline Functions @@ -342,7 +336,7 @@ void sam_dmastop(DMA_HANDLE handle); * ************************************************************************************/ -#ifdef CONFIG_DEBUG_DMA +#ifdef CONFIG_DEBUG_DMA_INFO void sam_dmasample(DMA_HANDLE handle, struct sam_dmaregs_s *regs); #else # define sam_dmasample(handle,regs) @@ -356,7 +350,7 @@ void sam_dmasample(DMA_HANDLE handle, struct sam_dmaregs_s *regs); * ************************************************************************************/ -#ifdef CONFIG_DEBUG_DMA +#ifdef CONFIG_DEBUG_DMA_INFO void sam_dmadump(DMA_HANDLE handle, const struct sam_dmaregs_s *regs, const char *msg); #else # define sam_dmadump(handle,regs,msg) From a63072d08091c63624da25e79fdf778b4d638b7d Mon Sep 17 00:00:00 2001 From: Gregory Nutt Date: Thu, 16 Jun 2016 15:06:13 -0600 Subject: [PATCH 19/75] Fix yet more typos from the last commits --- arch/arm/src/stm32/stm32_eth.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm/src/stm32/stm32_eth.c b/arch/arm/src/stm32/stm32_eth.c index d4899c98c9..e4add73879 100644 --- a/arch/arm/src/stm32/stm32_eth.c +++ b/arch/arm/src/stm32/stm32_eth.c @@ -2042,7 +2042,7 @@ static inline void stm32_interrupt_process(FAR struct stm32_ethmac_s *priv) { /* Just let the user know what happened */ - nllnerr("ERROR: Abormal event(s): %08x\n", dmasr); + nllerr("ERROR: Abormal event(s): %08x\n", dmasr); /* Clear all pending abnormal events */ @@ -2246,7 +2246,7 @@ static void stm32_txtimeout_expiry(int argc, uint32_t arg, ...) { FAR struct stm32_ethmac_s *priv = (FAR struct stm32_ethmac_s *)arg; - nllnerr("ERROR: Timeout!\n"); + nllerr("ERROR: Timeout!\n"); #ifdef CONFIG_NET_NOINTS /* Disable further Ethernet interrupts. This will prevent some race From 6b7959202f9c2ded50a4417fa4549517cc5f9694 Mon Sep 17 00:00:00 2001 From: Jim Paris Date: Thu, 16 Jun 2016 17:26:13 -0400 Subject: [PATCH 20/75] Remove duplicate lines in Makefile They're already there, a few lines up. --- arch/arm/src/stm32l4/Make.defs | 4 ---- 1 file changed, 4 deletions(-) diff --git a/arch/arm/src/stm32l4/Make.defs b/arch/arm/src/stm32l4/Make.defs index a1acddd1ba..d4f1c94494 100644 --- a/arch/arm/src/stm32l4/Make.defs +++ b/arch/arm/src/stm32l4/Make.defs @@ -105,10 +105,6 @@ else ifeq ($(CONFIG_MODULE),y) CMN_CSRCS += up_elf.c up_coherent_dcache.c endif -ifeq ($(CONFIG_STACK_COLORATION),y) -CMN_CSRCS += up_checkstack.c -endif - # Required STM32L4 files CHIP_ASRCS = From 5ecb8da118120dc5b8aeb0490ed99e1e39a75bd5 Mon Sep 17 00:00:00 2001 From: Gregory Nutt Date: Thu, 16 Jun 2016 15:26:19 -0600 Subject: [PATCH 21/75] Eliminate a warning --- arch/arm/src/stm32/stm32_rcc.c | 2 -- arch/arm/src/stm32/stm32_rtc.c | 16 ---------------- 2 files changed, 18 deletions(-) diff --git a/arch/arm/src/stm32/stm32_rcc.c b/arch/arm/src/stm32/stm32_rcc.c index 80e87fb37a..0dee8dc216 100644 --- a/arch/arm/src/stm32/stm32_rcc.c +++ b/arch/arm/src/stm32/stm32_rcc.c @@ -171,8 +171,6 @@ static inline rcc_resetbkp(void) void stm32_clockconfig(void) { - uint32_t regval; - /* Make sure that we are starting in the reset state */ rcc_reset(); diff --git a/arch/arm/src/stm32/stm32_rtc.c b/arch/arm/src/stm32/stm32_rtc.c index 0080b78cd2..3e8dc0b0d7 100644 --- a/arch/arm/src/stm32/stm32_rtc.c +++ b/arch/arm/src/stm32/stm32_rtc.c @@ -41,22 +41,6 @@ #include "chip.h" -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/**************************************************************************** - * Private Types - ****************************************************************************/ - -/**************************************************************************** - * Private Data - ****************************************************************************/ - -/**************************************************************************** - * Private Functions - ****************************************************************************/ - /**************************************************************************** * Public Functions ****************************************************************************/ From 1b53214a820a184f4e98e9ed1facfe72ffa96878 Mon Sep 17 00:00:00 2001 From: Gregory Nutt Date: Thu, 16 Jun 2016 15:26:48 -0600 Subject: [PATCH 22/75] STM32L4: Last change added rcc_resetbkp(), but the function was never called. --- arch/arm/src/stm32l4/stm32l4_rcc.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/arm/src/stm32l4/stm32l4_rcc.c b/arch/arm/src/stm32l4/stm32l4_rcc.c index 202b90176f..6cf4b46e49 100644 --- a/arch/arm/src/stm32l4/stm32l4_rcc.c +++ b/arch/arm/src/stm32l4/stm32l4_rcc.c @@ -166,6 +166,10 @@ void stm32l4_clockconfig(void) rcc_reset(); + /* Reset backup domain if appropriate */ + + rcc_resetbkp(); + #if defined(CONFIG_ARCH_BOARD_STM32L4_CUSTOM_CLOCKCONFIG) /* Invoke Board Custom Clock Configuration */ From 088e9920a8de8494bbb24092ca8a96eab2da4873 Mon Sep 17 00:00:00 2001 From: Gregory Nutt Date: Thu, 16 Jun 2016 15:45:57 -0600 Subject: [PATCH 23/75] Cosmetic: Fix some long lines in comment blocks --- arch/arm/src/stm32/stm32_rcc.c | 29 ++++++++++++++--------------- arch/arm/src/stm32l4/stm32l4_rcc.c | 28 ++++++++++++++-------------- 2 files changed, 28 insertions(+), 29 deletions(-) diff --git a/arch/arm/src/stm32/stm32_rcc.c b/arch/arm/src/stm32/stm32_rcc.c index 0dee8dc216..3bd2913076 100644 --- a/arch/arm/src/stm32/stm32_rcc.c +++ b/arch/arm/src/stm32/stm32_rcc.c @@ -101,14 +101,14 @@ * Public Functions ****************************************************************************/ -/************************************************************************************ +/**************************************************************************** * Name: rcc_resetbkp * * Description: - * The RTC needs to reset the Backup Domain to change RTCSEL and resetting the - * Backup Domain renders to disabling the LSE as consequence. In order to avoid - * resetting the Backup Domain when we already configured LSE we will reset the - * Backup Domain early (here). + * The RTC needs to reset the Backup Domain to change RTCSEL and resetting + * the Backup Domain renders to disabling the LSE as consequence. In order + * to avoid resetting the Backup Domain when we already configured LSE we + * will reset the Backup Domain early (here). * * Input Parameters: * None @@ -116,7 +116,7 @@ * Returned Value: * None * - ************************************************************************************/ + ****************************************************************************/ #if defined(CONFIG_RTC) && defined(CONFIG_STM32_PWR) && !defined(CONFIG_STM32_STM32F10XX) static inline rcc_resetbkp(void) @@ -148,17 +148,17 @@ static inline rcc_resetbkp(void) * Public Functions ****************************************************************************/ -/************************************************************************************ +/**************************************************************************** * Name: stm32_clockconfig * * Description: - * Called to establish the clock settings based on the values in board.h. This - * function (by default) will reset most everything, enable the PLL, and enable - * peripheral clocking for all periperipherals enabled in the NuttX configuration - * file. + * Called to establish the clock settings based on the values in board.h. + * This function (by default) will reset most everything, enable the PLL, + * and enable peripheral clocking for all peripherals enabled in the NuttX + * configuration file. * - * If CONFIG_ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG is defined, then clocking will - * be enabled by an externally provided, board-specific function called + * If CONFIG_ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG is defined, then clocking + * will be enabled by an externally provided, board-specific function called * stm32_board_clockconfig(). * * Input Parameters: @@ -167,7 +167,7 @@ static inline rcc_resetbkp(void) * Returned Value: * None * - ************************************************************************************/ + ****************************************************************************/ void stm32_clockconfig(void) { @@ -241,4 +241,3 @@ void stm32_clockenable(void) #endif } #endif - diff --git a/arch/arm/src/stm32l4/stm32l4_rcc.c b/arch/arm/src/stm32l4/stm32l4_rcc.c index 6cf4b46e49..b972c2680b 100644 --- a/arch/arm/src/stm32l4/stm32l4_rcc.c +++ b/arch/arm/src/stm32l4/stm32l4_rcc.c @@ -88,14 +88,14 @@ * Public Functions ****************************************************************************/ -/************************************************************************************ +/**************************************************************************** * Name: rcc_resetbkp * * Description: - * The RTC needs to reset the Backup Domain to change RTCSEL and resetting the - * Backup Domain renders to disabling the LSE as consequence. In order to avoid - * resetting the Backup Domain when we already configured LSE we will reset the - * Backup Domain early (here). + * The RTC needs to reset the Backup Domain to change RTCSEL and resetting + * the Backup Domain renders to disabling the LSE as consequence. In order + * to avoid resetting the Backup Domain when we already configured LSE we + * will reset the Backup Domain early (here). * * Input Parameters: * None @@ -103,7 +103,7 @@ * Returned Value: * None * - ************************************************************************************/ + ****************************************************************************/ #if defined(CONFIG_STM32_PWR) && defined(CONFIG_RTC) static inline rcc_resetbkp(void) @@ -139,17 +139,17 @@ static inline rcc_resetbkp(void) * Public Functions ****************************************************************************/ -/************************************************************************************ +/**************************************************************************** * Name: stm32_clockconfig * * Description: - * Called to establish the clock settings based on the values in board.h. This - * function (by default) will reset most everything, enable the PLL, and enable - * peripheral clocking for all periperipherals enabled in the NuttX configuration - * file. + * Called to establish the clock settings based on the values in board.h. + * This function (by default) will reset most everything, enable the PLL, + * and enable peripheral clocking for all peripherals enabled in the NuttX + * configuration file. * - * If CONFIG_ARCH_BOARD_STM32L4_CUSTOM_CLOCKCONFIG is defined, then clocking will - * be enabled by an externally provided, board-specific function called + * If CONFIG_ARCH_BOARD_STM32L4_CUSTOM_CLOCKCONFIG is defined, then clocking + * will be enabled by an externally provided, board-specific function called * stm32l4_board_clockconfig(). * * Input Parameters: @@ -158,7 +158,7 @@ static inline rcc_resetbkp(void) * Returned Value: * None * - ************************************************************************************/ + ****************************************************************************/ void stm32l4_clockconfig(void) { From f35086dbf77f0846215d648bccb99e26a5f17f09 Mon Sep 17 00:00:00 2001 From: Gregory Nutt Date: Thu, 16 Jun 2016 16:30:45 -0600 Subject: [PATCH 24/75] Change *err() to either info() or err(ERROR:..), depending upon if an error has occurred. --- arch/arm/src/moxart/moxart_irq.c | 21 ++-- arch/arm/src/nuc1xx/nuc_dumpgpio.c | 42 +++----- arch/arm/src/sam34/Kconfig | 12 +-- arch/arm/src/sam34/sam4cm_tc.c | 36 ++++--- arch/arm/src/sam34/sam_dmac.c | 40 +++---- arch/arm/src/sam34/sam_dmac.h | 12 +-- arch/arm/src/sam34/sam_emac.c | 166 ++++++++++++++--------------- arch/arm/src/sam34/sam_hsmci.c | 100 ++++++++--------- arch/arm/src/sam34/sam_rtc.c | 2 +- arch/arm/src/sam34/sam_rtt.c | 54 ++++------ arch/arm/src/sam34/sam_spi.c | 16 +-- arch/arm/src/sam34/sam_tc.c | 20 ++-- arch/arm/src/sam34/sam_twi.c | 16 +-- arch/arm/src/sam34/sam_udp.c | 6 +- arch/arm/src/sam34/sam_wdt.c | 20 ++-- 15 files changed, 279 insertions(+), 284 deletions(-) diff --git a/arch/arm/src/moxart/moxart_irq.c b/arch/arm/src/moxart/moxart_irq.c index 0dfd4d92ea..31ed83c80f 100644 --- a/arch/arm/src/moxart/moxart_irq.c +++ b/arch/arm/src/moxart/moxart_irq.c @@ -143,18 +143,15 @@ void up_irqinitialize(void) /* And finally, enable interrupts */ -#if 1 -#define REG(x) (*(volatile uint32_t *)(x)) - _llerr("\n=============================================================\n"); - _llerr("TM CNTL=%08x INTRS=%08x MASK=%08x LOAD=%08x COUNT=%08x M1=%08x\n", - REG(0x98400030), REG(0x98400034), REG(0x98400038), REG(0x98400004), - REG(0x98400000), REG(0x98400008)); - _llerr("IRQ STATUS=%08x MASK=%08x MODE=%08x LEVEL=%08x\n", - REG(0x98800014), REG(0x98800004), REG(0x9880000C), REG(0x98800010)); - _llerr("FIQ STATUS=%08x MASK=%08x MODE=%08x LEVEL=%08x\n", - REG(0x98800034), REG(0x98800024), REG(0x9880002C), REG(0x98800020)); - _llerr("=============================================================\n"); -#endif + irqinfo("TM CNTL=%08x INTRS=%08x MASK=%08x LOAD=%08x COUNT=%08x M1=%08x\n", + getreg32(0x98400030), getreg32(0x98400034), getreg32(0x98400038), + getreg32(0x98400004), getreg32(0x98400000), getreg32(0x98400008)); + irqinfo("IRQ STATUS=%08x MASK=%08x MODE=%08x LEVEL=%08x\n", + getreg32(0x98800014), getreg32(0x98800004), getreg32(0x9880000C), + getreg32(0x98800010)); + irqinfo("FIQ STATUS=%08x MASK=%08x MODE=%08x LEVEL=%08x\n", + getreg32(0x98800034), getreg32(0x98800024), getreg32(0x9880002C), + getreg32(0x98800020)); #ifndef CONFIG_SUPPRESS_INTERRUPTS up_irq_restore(SVC_MODE | PSR_F_BIT); diff --git a/arch/arm/src/nuc1xx/nuc_dumpgpio.c b/arch/arm/src/nuc1xx/nuc_dumpgpio.c index 780f8c61d4..82db651a69 100644 --- a/arch/arm/src/nuc1xx/nuc_dumpgpio.c +++ b/arch/arm/src/nuc1xx/nuc_dumpgpio.c @@ -49,14 +49,13 @@ #include "chip.h" #include "nuc_gpio.h" -#ifdef CONFIG_DEBUG_FEATURES +#ifdef CONFIG_DEBUG_GPIO_INFO /**************************************************************************** * Private Data ****************************************************************************/ /* Port letters for prettier debug output */ -#ifdef CONFIG_DEBUG_FEATURES static const char g_portchar[NUC_GPIO_NPORTS] = { #if NUC_GPIO_NPORTS > 9 @@ -83,15 +82,6 @@ static const char g_portchar[NUC_GPIO_NPORTS] = # error "Bad number of GPIOs" #endif }; -#endif - -/**************************************************************************** - * Public Data - ****************************************************************************/ - -/**************************************************************************** - * Private Functions - ****************************************************************************/ /**************************************************************************** * Public Functions @@ -124,22 +114,22 @@ void nuc_dumpgpio(gpio_cfgset_t pinset, const char *msg) flags = enter_critical_section(); - _llerr("GPIO%c pinset: %08x base: %08x -- %s\n", - g_portchar[port], pinset, base, msg); - _llerr(" PMD: %08x OFFD: %08x DOUT: %08x DMASK: %08x\n", - getreg32(base + NUC_GPIO_PMD_OFFSET), - getreg32(base + NUC_GPIO_OFFD_OFFSET), - getreg32(base + NUC_GPIO_DOUT_OFFSET), - getreg32(base + NUC_GPIO_DMASK_OFFSET)); - _llerr(" PIN: %08x DBEN: %08x IMD: %08x IEN: %08x\n", - getreg32(base + NUC_GPIO_PIN_OFFSET), - getreg32(base + NUC_GPIO_DBEN_OFFSET), - getreg32(base + NUC_GPIO_IMD_OFFSET), - getreg32(base + NUC_GPIO_IEN_OFFSET)); - _llerr(" ISRC: %08x\n", - getreg32(base + NUC_GPIO_ISRC_OFFSET)); + gpioinfo("GPIO%c pinset: %08x base: %08x -- %s\n", + g_portchar[port], pinset, base, msg); + gpioinfo(" PMD: %08x OFFD: %08x DOUT: %08x DMASK: %08x\n", + getreg32(base + NUC_GPIO_PMD_OFFSET), + getreg32(base + NUC_GPIO_OFFD_OFFSET), + getreg32(base + NUC_GPIO_DOUT_OFFSET), + getreg32(base + NUC_GPIO_DMASK_OFFSET)); + gpioinfo(" PIN: %08x DBEN: %08x IMD: %08x IEN: %08x\n", + getreg32(base + NUC_GPIO_PIN_OFFSET), + getreg32(base + NUC_GPIO_DBEN_OFFSET), + getreg32(base + NUC_GPIO_IMD_OFFSET), + getreg32(base + NUC_GPIO_IEN_OFFSET)); + gpioinfo(" ISRC: %08x\n", + getreg32(base + NUC_GPIO_ISRC_OFFSET)); leave_critical_section(flags); } -#endif /* CONFIG_DEBUG_FEATURES */ +#endif /* CONFIG_DEBUG_GPIO_INFO */ diff --git a/arch/arm/src/sam34/Kconfig b/arch/arm/src/sam34/Kconfig index ce158857cd..bc191c88df 100644 --- a/arch/arm/src/sam34/Kconfig +++ b/arch/arm/src/sam34/Kconfig @@ -1128,11 +1128,11 @@ config SAM34_SPI_DMADEBUG config SAM34_SPI_REGDEBUG bool "SPI Register level debug" - depends on DEBUG_FEATURES + depends on DEBUG_SPI_INFO default n ---help--- Output detailed register-level SPI device debug information. - Requires also CONFIG_DEBUG_FEATURES. + Requires also CONFIG_SPI_INFO. endmenu # AT91SAM3/4 SPI device driver options endif # SAM34_SPI0 || SAM34_SPI1 @@ -1336,9 +1336,9 @@ config SAM34_EMAC_PHYSR_100FD config SAM34_EMAC_REGDEBUG bool "Register-Level Debug" default n - depends on DEBUG_FEATURES + depends on DEBUG_NET_INFO ---help--- - Enable very low-level register access debug. Depends on CONFIG_DEBUG_FEATURES. + Enable very low-level register access debug. Depends on CONFIG_DEBUG_NET_INFO. config SAM34_EMAC_ISETH0 bool @@ -1400,7 +1400,7 @@ menu "AT91SAM3/4 USB Full Speed Device Controller driver (DCD) options" config SAM34_UDP_REGDEBUG bool "Enable low-level UDP register debug" default n - depends on DEBUG_FEATURES + depends on DEBUG_USB_INFO endmenu # USB Full Speed Device Controller driver (DCD) options @@ -1415,7 +1415,7 @@ menu "AT91SAM3/4 Timer/Counter options" config SAM34_TC_REGDEBUG bool "Enable low-level timer/counter register debug" default n - depends on DEBUG_FEATURES + depends on DEBUG_TIMER_INFO endmenu # USB Full Speed Device Controller driver (DCD) options diff --git a/arch/arm/src/sam34/sam4cm_tc.c b/arch/arm/src/sam34/sam4cm_tc.c index 8766a88720..d10ac33101 100644 --- a/arch/arm/src/sam34/sam4cm_tc.c +++ b/arch/arm/src/sam34/sam4cm_tc.c @@ -77,6 +77,10 @@ * Pre-processor Definitions ****************************************************************************/ +#ifndef CONFIG_DEBUG_TIMER_INFO +# undef CONFIG_SAM34_TC_REGDEBUG +#endif + /**************************************************************************** * Private Types ****************************************************************************/ @@ -390,21 +394,21 @@ static void sam_regdump(struct sam_chan_s *chan, const char *msg) uintptr_t base; base = chan->base; - _llerr("TC%d [%08x]: %s\n", chan->chan, (int)base, msg); - _llerr(" BMR: %08x QIMR: %08x QISR: %08x WPMR: %08x\n", - getreg32(base+SAM_TC_BMR_OFFSET), getreg32(base+SAM_TC_QIMR_OFFSET), - getreg32(base+SAM_TC_QISR_OFFSET), getreg32(base+SAM_TC_WPMR_OFFSET)); + tmrinfo("TC%d [%08x]: %s\n", chan->chan, (int)base, msg); + tmrinfo(" BMR: %08x QIMR: %08x QISR: %08x WPMR: %08x\n", + getreg32(base+SAM_TC_BMR_OFFSET), getreg32(base+SAM_TC_QIMR_OFFSET), + getreg32(base+SAM_TC_QISR_OFFSET), getreg32(base+SAM_TC_WPMR_OFFSET)); base = chan->base; - _llerr("TC%d Channel %d [%08x]: %s\n", chan->chan, chan->chan, (int)base, msg); - _llerr(" CMR: %08x SSMR: %08x RAB: %08x CV: %08x\n", - getreg32(base+SAM_TC_CMR_OFFSET), getreg32(base+SAM_TC_SMMR_OFFSET), - getreg32(base+SAM_TC_RAB_OFFSET), getreg32(base+SAM_TC_CV_OFFSET)); - _llerr(" RA: %08x RB: %08x RC: %08x SR: %08x\n", - getreg32(base+SAM_TC_RA_OFFSET), getreg32(base+SAM_TC_RB_OFFSET), - getreg32(base+SAM_TC_RC_OFFSET), getreg32(base+SAM_TC_SR_OFFSET)); - _llerr(" IMR: %08x\n", - getreg32(base+SAM_TC_IMR_OFFSET)); + tmrinfo("TC%d Channel %d [%08x]: %s\n", chan->chan, chan->chan, (int)base, msg); + tmrinfo(" CMR: %08x SSMR: %08x RAB: %08x CV: %08x\n", + getreg32(base+SAM_TC_CMR_OFFSET), getreg32(base+SAM_TC_SMMR_OFFSET), + getreg32(base+SAM_TC_RAB_OFFSET), getreg32(base+SAM_TC_CV_OFFSET)); + tmrinfo(" RA: %08x RB: %08x RC: %08x SR: %08x\n", + getreg32(base+SAM_TC_RA_OFFSET), getreg32(base+SAM_TC_RB_OFFSET), + getreg32(base+SAM_TC_RC_OFFSET), getreg32(base+SAM_TC_SR_OFFSET)); + tmrinfo(" IMR: %08x\n", + getreg32(base+SAM_TC_IMR_OFFSET)); } #endif @@ -447,7 +451,7 @@ static bool sam_checkreg(struct sam_chan_s *chan, bool wr, uint32_t regaddr, { /* Yes... show how many times we did it */ - _llerr("...[Repeats %d times]...\n", chan->ntimes); + tmrinfo("...[Repeats %d times]...\n", chan->ntimes); } /* Save information about the new access */ @@ -481,7 +485,7 @@ static inline uint32_t sam_chan_getreg(struct sam_chan_s *chan, #ifdef CONFIG_SAM34_TC_REGDEBUG if (sam_checkreg(chan, false, regaddr, regval)) { - _llerr("%08x->%08x\n", regaddr, regval); + tmrinfo("%08x->%08x\n", regaddr, regval); } #endif @@ -504,7 +508,7 @@ static inline void sam_chan_putreg(struct sam_chan_s *chan, unsigned int offset, #ifdef CONFIG_SAM34_TC_REGDEBUG if (sam_checkreg(chan, true, regaddr, regval)) { - _llerr("%08x<-%08x\n", regaddr, regval); + tmrinfo("%08x<-%08x\n", regaddr, regval); } #endif diff --git a/arch/arm/src/sam34/sam_dmac.c b/arch/arm/src/sam34/sam_dmac.c index 7eb31148cb..01b7f65656 100644 --- a/arch/arm/src/sam34/sam_dmac.c +++ b/arch/arm/src/sam34/sam_dmac.c @@ -1730,7 +1730,7 @@ void sam_dmastop(DMA_HANDLE handle) * ****************************************************************************/ -#ifdef CONFIG_DEBUG_DMA +#ifdef CONFIG_DEBUG_DMA_INFO void sam_dmasample(DMA_HANDLE handle, struct sam_dmaregs_s *regs) { struct sam_dma_s *dmach = (struct sam_dma_s *)handle; @@ -1761,7 +1761,7 @@ void sam_dmasample(DMA_HANDLE handle, struct sam_dmaregs_s *regs) regs->cfg = getreg32(dmach->base + SAM_DMACHAN_CFG_OFFSET); leave_critical_section(flags); } -#endif /* CONFIG_DEBUG_DMA */ +#endif /* CONFIG_DEBUG_DMA_INFO */ /**************************************************************************** * Name: sam_dmadump @@ -1774,28 +1774,28 @@ void sam_dmasample(DMA_HANDLE handle, struct sam_dmaregs_s *regs) * ****************************************************************************/ -#ifdef CONFIG_DEBUG_DMA +#ifdef CONFIG_DEBUG_DMA_INFO void sam_dmadump(DMA_HANDLE handle, const struct sam_dmaregs_s *regs, const char *msg) { struct sam_dma_s *dmach = (struct sam_dma_s *)handle; - dmaerr("%s\n", msg); - dmaerr(" DMA Global Registers:\n"); - dmaerr(" GCFG[%08x]: %08x\n", SAM_DMAC_GCFG, regs->gcfg); - dmaerr(" EN[%08x]: %08x\n", SAM_DMAC_EN, regs->en); - dmaerr(" SREQ[%08x]: %08x\n", SAM_DMAC_SREQ, regs->sreq); - dmaerr(" CREQ[%08x]: %08x\n", SAM_DMAC_CREQ, regs->creq); - dmaerr(" LAST[%08x]: %08x\n", SAM_DMAC_LAST, regs->last); - dmaerr(" EBCIMR[%08x]: %08x\n", SAM_DMAC_EBCIMR, regs->ebcimr); - dmaerr(" CHSR[%08x]: %08x\n", SAM_DMAC_CHSR, regs->chsr); - dmaerr(" DMA Channel Registers:\n"); - dmaerr(" SADDR[%08x]: %08x\n", dmach->base + SAM_DMACHAN_SADDR_OFFSET, regs->saddr); - dmaerr(" DADDR[%08x]: %08x\n", dmach->base + SAM_DMACHAN_DADDR_OFFSET, regs->daddr); - dmaerr(" DSCR[%08x]: %08x\n", dmach->base + SAM_DMACHAN_DSCR_OFFSET, regs->dscr); - dmaerr(" CTRLA[%08x]: %08x\n", dmach->base + SAM_DMACHAN_CTRLA_OFFSET, regs->ctrla); - dmaerr(" CTRLB[%08x]: %08x\n", dmach->base + SAM_DMACHAN_CTRLB_OFFSET, regs->ctrlb); - dmaerr(" CFG[%08x]: %08x\n", dmach->base + SAM_DMACHAN_CFG_OFFSET, regs->cfg); + dmainfo("%s\n", msg); + dmainfo(" DMA Global Registers:\n"); + dmainfo(" GCFG[%08x]: %08x\n", SAM_DMAC_GCFG, regs->gcfg); + dmainfo(" EN[%08x]: %08x\n", SAM_DMAC_EN, regs->en); + dmainfo(" SREQ[%08x]: %08x\n", SAM_DMAC_SREQ, regs->sreq); + dmainfo(" CREQ[%08x]: %08x\n", SAM_DMAC_CREQ, regs->creq); + dmainfo(" LAST[%08x]: %08x\n", SAM_DMAC_LAST, regs->last); + dmainfo(" EBCIMR[%08x]: %08x\n", SAM_DMAC_EBCIMR, regs->ebcimr); + dmainfo(" CHSR[%08x]: %08x\n", SAM_DMAC_CHSR, regs->chsr); + dmainfo(" DMA Channel Registers:\n"); + dmainfo(" SADDR[%08x]: %08x\n", dmach->base + SAM_DMACHAN_SADDR_OFFSET, regs->saddr); + dmainfo(" DADDR[%08x]: %08x\n", dmach->base + SAM_DMACHAN_DADDR_OFFSET, regs->daddr); + dmainfo(" DSCR[%08x]: %08x\n", dmach->base + SAM_DMACHAN_DSCR_OFFSET, regs->dscr); + dmainfo(" CTRLA[%08x]: %08x\n", dmach->base + SAM_DMACHAN_CTRLA_OFFSET, regs->ctrla); + dmainfo(" CTRLB[%08x]: %08x\n", dmach->base + SAM_DMACHAN_CTRLB_OFFSET, regs->ctrlb); + dmainfo(" CFG[%08x]: %08x\n", dmach->base + SAM_DMACHAN_CFG_OFFSET, regs->cfg); } -#endif /* CONFIG_DEBUG_DMA */ +#endif /* CONFIG_DEBUG_DMA_INFO */ #endif /* CONFIG_SAM34_DMAC0 */ diff --git a/arch/arm/src/sam34/sam_dmac.h b/arch/arm/src/sam34/sam_dmac.h index 3b8a3cc2c4..58e7e68eb8 100644 --- a/arch/arm/src/sam34/sam_dmac.h +++ b/arch/arm/src/sam34/sam_dmac.h @@ -50,12 +50,6 @@ * Pre-processor Definitions ************************************************************************************/ -/* Configuration ********************************************************************/ - -#ifndef CONFIG_DEBUG_FEATURES -# undef CONFIG_DEBUG_DMA -#endif - /* DMA ******************************************************************************/ /* Flags used to characterize the desired DMA channel. The naming convention is that @@ -125,7 +119,7 @@ typedef void (*dma_callback_t)(DMA_HANDLE handle, void *arg, int result); /* The following is used for sampling DMA registers when CONFIG DEBUG_DMA is selected */ -#ifdef CONFIG_DEBUG_DMA +#ifdef CONFIG_DEBUG_DMA_INFO struct sam_dmaregs_s { /* Global Registers */ @@ -285,7 +279,7 @@ void sam_dmastop(DMA_HANDLE handle); * ****************************************************************************/ -#ifdef CONFIG_DEBUG_DMA +#ifdef CONFIG_DEBUG_DMA_INFO void sam_dmasample(DMA_HANDLE handle, struct sam_dmaregs_s *regs); #else # define sam_dmasample(handle,regs) @@ -299,7 +293,7 @@ void sam_dmasample(DMA_HANDLE handle, struct sam_dmaregs_s *regs); * ****************************************************************************/ -#ifdef CONFIG_DEBUG_DMA +#ifdef CONFIG_DEBUG_DMA_INFO void sam_dmadump(DMA_HANDLE handle, const struct sam_dmaregs_s *regs, const char *msg); #else diff --git a/arch/arm/src/sam34/sam_emac.c b/arch/arm/src/sam34/sam_emac.c index 5a8d2673b8..b1a665dd9a 100644 --- a/arch/arm/src/sam34/sam_emac.c +++ b/arch/arm/src/sam34/sam_emac.c @@ -231,7 +231,7 @@ * enabled. */ -#ifndef CONFIG_DEBUG_FEATURES +#ifndef CONFIG_DEBUG_NET_INFO # undef CONFIG_SAM34_EMAC_REGDEBUG #endif @@ -490,7 +490,7 @@ static bool sam_checkreg(struct sam_emac_s *priv, bool wr, uint32_t regval, { /* Yes... show how many times we did it */ - _llerr("...[Repeats %d times]...\n", priv->ntimes); + ninfo("...[Repeats %d times]...\n", priv->ntimes); } /* Save information about the new access */ @@ -522,7 +522,7 @@ static uint32_t sam_getreg(struct sam_emac_s *priv, uintptr_t address) if (sam_checkreg(priv, false, regval, address)) { - _llerr("%08x->%08x\n", address, regval); + ninfo("%08x->%08x\n", address, regval); } return regval; @@ -543,7 +543,7 @@ static void sam_putreg(struct sam_emac_s *priv, uintptr_t address, { if (sam_checkreg(priv, true, regval, address)) { - _llerr("%08x<-%08x\n", address, regval); + ninfo("%08x<-%08x\n", address, regval); } putreg32(regval, address); @@ -636,7 +636,7 @@ static int sam_buffer_initialize(struct sam_emac_s *priv) priv->txdesc = (struct emac_txdesc_s *)kmm_memalign(8, allocsize); if (!priv->txdesc) { - nllerr("ERROR: Failed to allocate TX descriptors\n"); + nerr("ERROR: Failed to allocate TX descriptors\n"); return -ENOMEM; } @@ -646,7 +646,7 @@ static int sam_buffer_initialize(struct sam_emac_s *priv) priv->rxdesc = (struct emac_rxdesc_s *)kmm_memalign(8, allocsize); if (!priv->rxdesc) { - nllerr("ERROR: Failed to allocate RX descriptors\n"); + nerr("ERROR: Failed to allocate RX descriptors\n"); sam_buffer_free(priv); return -ENOMEM; } @@ -657,7 +657,7 @@ static int sam_buffer_initialize(struct sam_emac_s *priv) priv->txbuffer = (uint8_t *)kmm_memalign(8, allocsize); if (!priv->txbuffer) { - nllerr("ERROR: Failed to allocate TX buffer\n"); + nerr("ERROR: Failed to allocate TX buffer\n"); sam_buffer_free(priv); return -ENOMEM; } @@ -666,7 +666,7 @@ static int sam_buffer_initialize(struct sam_emac_s *priv) priv->rxbuffer = (uint8_t *)kmm_memalign(8, allocsize); if (!priv->rxbuffer) { - nllerr("ERROR: Failed to allocate RX buffer\n"); + nerr("ERROR: Failed to allocate RX buffer\n"); sam_buffer_free(priv); return -ENOMEM; } @@ -1207,7 +1207,7 @@ static void sam_receive(struct sam_emac_s *priv) if (dev->d_len > CONFIG_NET_ETH_MTU) { - nllerr("DROPPED: Too big: %d\n", dev->d_len); + nllwarn("WARNING: Dropped, Too big: %d\n", dev->d_len); continue; } @@ -1317,7 +1317,7 @@ static void sam_receive(struct sam_emac_s *priv) else #endif { - nllerr("DROPPED: Unknown type: %04x\n", BUF->type); + nllwarn("WARNING: Dropped, Unknown type: %04x\n", BUF->type); } } } @@ -1578,7 +1578,7 @@ static inline void sam_interrupt_process(FAR struct sam_emac_s *priv) if ((pending & EMAC_INT_PFNZ) != 0) { - nllerr("Pause frame received\n"); + nllwarn("WARNING: Pause frame received\n"); } /* Check for Pause Time Zero (PTZ) @@ -1588,7 +1588,7 @@ static inline void sam_interrupt_process(FAR struct sam_emac_s *priv) if ((pending & EMAC_INT_PTZ) != 0) { - nllerr("Pause TO!\n"); + nllwarn("WARNING: Pause TO!\n"); } #endif } @@ -1725,7 +1725,7 @@ static int sam_emac_interrupt(int irq, void *context) static inline void sam_txtimeout_process(FAR struct sam_emac_s *priv) { - nllerr("Timeout!\n"); + nllerr("ERROR: Timeout!\n"); /* Then reset the hardware. Just take the interface down, then back * up again. @@ -1956,13 +1956,13 @@ static int sam_ifup(struct net_driver_s *dev) struct sam_emac_s *priv = (struct sam_emac_s *)dev->d_private; int ret; - nllerr("Bringing up: %d.%d.%d.%d\n", - dev->d_ipaddr & 0xff, (dev->d_ipaddr >> 8) & 0xff, - (dev->d_ipaddr >> 16) & 0xff, dev->d_ipaddr >> 24); + ninfo("Bringing up: %d.%d.%d.%d\n", + dev->d_ipaddr & 0xff, (dev->d_ipaddr >> 8) & 0xff, + (dev->d_ipaddr >> 16) & 0xff, dev->d_ipaddr >> 24); /* Configure the EMAC interface for normal operation. */ - nllinfo("Initialize the EMAC\n"); + ninfo("Initialize the EMAC\n"); sam_emac_configure(priv); /* Set the MAC address (should have been configured while we were down) */ @@ -1980,7 +1980,7 @@ static int sam_ifup(struct net_driver_s *dev) ret = sam_phyinit(priv); if (ret < 0) { - nllerr("ERROR: sam_phyinit failed: %d\n", ret); + nerr("ERROR: sam_phyinit failed: %d\n", ret); return ret; } @@ -1989,16 +1989,16 @@ static int sam_ifup(struct net_driver_s *dev) ret = sam_autonegotiate(priv); if (ret < 0) { - nllerr("ERROR: sam_autonegotiate failed: %d\n", ret); + nerr("ERROR: sam_autonegotiate failed: %d\n", ret); return ret; } while (sam_linkup(priv) == 0); - nllinfo("Link detected \n"); + ninfo("Link detected \n"); /* Enable normal MAC operation */ - nllinfo("Enable normal operation\n"); + ninfo("Enable normal operation\n"); /* Set and activate a timer process */ @@ -2032,7 +2032,7 @@ static int sam_ifdown(struct net_driver_s *dev) struct sam_emac_s *priv = (struct sam_emac_s *)dev->d_private; irqstate_t flags; - nllerr("Taking the network down\n"); + ninfo("Taking the network down\n"); /* Disable the EMAC interrupt */ @@ -2077,7 +2077,7 @@ static int sam_ifdown(struct net_driver_s *dev) static inline void sam_txavail_process(FAR struct sam_emac_s *priv) { - nllinfo("ifup: %d\n", priv->ifup); + ninfo("ifup: %d\n", priv->ifup); /* Ignore the notification if the interface is not yet up */ @@ -2331,8 +2331,8 @@ static int sam_addmac(struct net_driver_s *dev, const uint8_t *mac) unsigned int bit; UNUSED(priv); - nllinfo("MAC: %02x:%02x:%02x:%02x:%02x:%02x\n", - mac[0], mac[1], mac[2], mac[3], mac[4], mac[5]); + ninfo("MAC: %02x:%02x:%02x:%02x:%02x:%02x\n", + mac[0], mac[1], mac[2], mac[3], mac[4], mac[5]); /* Calculate the 6-bit has table index */ @@ -2405,8 +2405,8 @@ static int sam_rmmac(struct net_driver_s *dev, const uint8_t *mac) unsigned int bit; UNUSED(priv); - nllinfo("MAC: %02x:%02x:%02x:%02x:%02x:%02x\n", - mac[0], mac[1], mac[2], mac[3], mac[4], mac[5]); + ninfo("MAC: %02x:%02x:%02x:%02x:%02x:%02x\n", + mac[0], mac[1], mac[2], mac[3], mac[4], mac[5]); /* Calculate the 6-bit has table index */ @@ -2601,21 +2601,21 @@ static void sam_phydump(struct sam_emac_s *priv) sam_putreg(priv, SAM_EMAC_NCR, regval); #ifdef CONFIG_SAM34_EMAC_RMII - nllinfo("RMII Registers (Address %02x)\n", priv->phyaddr); + ninfo("RMII Registers (Address %02x)\n", priv->phyaddr); #else /* defined(CONFIG_SAM34_EMAC_MII) */ - nllinfo("MII Registers (Address %02x)\n", priv->phyaddr); + ninfo("MII Registers (Address %02x)\n", priv->phyaddr); #endif sam_phyread(priv, priv->phyaddr, MII_MCR, &phyval); - nllinfo(" MCR: %04x\n", phyval); + ninfo(" MCR: %04x\n", phyval); sam_phyread(priv, priv->phyaddr, MII_MSR, &phyval); - nllinfo(" MSR: %04x\n", phyval); + ninfo(" MSR: %04x\n", phyval); sam_phyread(priv, priv->phyaddr, MII_ADVERTISE, &phyval); - nllinfo(" ADVERTISE: %04x\n", phyval); + ninfo(" ADVERTISE: %04x\n", phyval); sam_phyread(priv, priv->phyaddr, MII_LPA, &phyval); - nllinfo(" LPR: %04x\n", phyval); + ninfo(" LPR: %04x\n", phyval); sam_phyread(priv, priv->phyaddr, CONFIG_SAM34_EMAC_PHYSR, &phyval); - nllinfo(" PHYSR: %04x\n", phyval); + ninfo(" PHYSR: %04x\n", phyval); /* Disable management port */ @@ -2738,7 +2738,7 @@ static int sam_phyreset(struct sam_emac_s *priv) int timeout; int ret; - nllinfo(" sam_phyreset\n"); + ninfo(" sam_phyreset\n"); /* Enable management port */ @@ -2751,7 +2751,7 @@ static int sam_phyreset(struct sam_emac_s *priv) ret = sam_phywrite(priv, priv->phyaddr, MII_MCR, MII_MCR_RESET); if (ret < 0) { - nllerr("ERROR: sam_phywrite failed: %d\n", ret); + nerr("ERROR: sam_phywrite failed: %d\n", ret); } /* Wait for the PHY reset to complete */ @@ -2763,7 +2763,7 @@ static int sam_phyreset(struct sam_emac_s *priv) int result = sam_phyread(priv, priv->phyaddr, MII_MCR, &mcr); if (result < 0) { - nllerr("ERROR: Failed to read the MCR register: %d\n", ret); + nerr("ERROR: Failed to read the MCR register: %d\n", ret); ret = result; } else if ((mcr & MII_MCR_RESET) == 0) @@ -2805,7 +2805,7 @@ static int sam_phyfind(struct sam_emac_s *priv, uint8_t *phyaddr) unsigned int offset; int ret = -ESRCH; - nllinfo("Find a valid PHY address\n"); + ninfo("Find a valid PHY address\n"); /* Enable management port */ @@ -2828,8 +2828,8 @@ static int sam_phyfind(struct sam_emac_s *priv, uint8_t *phyaddr) else { - nllerr("ERROR: sam_phyread failed for PHY address %02x: %d\n", - candidate, ret); + nerr("ERROR: sam_phyread failed for PHY address %02x: %d\n", + candidate, ret); for (offset = 0; offset < 32; offset++) { @@ -2850,10 +2850,10 @@ static int sam_phyfind(struct sam_emac_s *priv, uint8_t *phyaddr) if (ret == OK) { - nllinfo(" PHYID1: %04x PHY addr: %d\n", phyval, candidate); + ninfo(" PHYID1: %04x PHY addr: %d\n", phyval, candidate); *phyaddr = candidate; sam_phyread(priv, candidate, CONFIG_SAM34_EMAC_PHYSR, &phyval); - nllinfo(" PHYSR: %04x PHY addr: %d\n", phyval, candidate); + ninfo(" PHYSR: %04x PHY addr: %d\n", phyval, candidate); } /* Disable management port */ @@ -2894,7 +2894,7 @@ static int sam_phyread(struct sam_emac_s *priv, uint8_t phyaddr, ret = sam_phywait(priv); if (ret < 0) { - nllerr("ERROR: sam_phywait failed: %d\n", ret); + nerr("ERROR: sam_phywait failed: %d\n", ret); return ret; } @@ -2918,7 +2918,7 @@ static int sam_phyread(struct sam_emac_s *priv, uint8_t phyaddr, ret = sam_phywait(priv); if (ret < 0) { - nllerr("ERROR: sam_phywait failed: %d\n", ret); + nerr("ERROR: sam_phywait failed: %d\n", ret); return ret; } @@ -2958,7 +2958,7 @@ static int sam_phywrite(struct sam_emac_s *priv, uint8_t phyaddr, ret = sam_phywait(priv); if (ret < 0) { - nllerr("ERROR: sam_phywait failed: %d\n", ret); + nerr("ERROR: sam_phywait failed: %d\n", ret); return ret; } @@ -2982,7 +2982,7 @@ static int sam_phywrite(struct sam_emac_s *priv, uint8_t phyaddr, ret = sam_phywait(priv); if (ret < 0) { - nllerr("ERROR: sam_phywait failed: %d\n", ret); + nerr("ERROR: sam_phywait failed: %d\n", ret); return ret; } @@ -3026,32 +3026,32 @@ static int sam_autonegotiate(struct sam_emac_s *priv) ret = sam_phyread(priv, priv->phyaddr, MII_PHYID1, &phyid1); if (ret < 0) { - nllerr("ERROR: Failed to read PHYID1\n"); + nerr("ERROR: Failed to read PHYID1\n"); goto errout; } - nllinfo("PHYID1: %04x PHY address: %02x\n", phyid1, priv->phyaddr); + ninfo("PHYID1: %04x PHY address: %02x\n", phyid1, priv->phyaddr); ret = sam_phyread(priv, priv->phyaddr, MII_PHYID2, &phyid2); if (ret < 0) { - nllerr("ERROR: Failed to read PHYID2\n"); + nerr("ERROR: Failed to read PHYID2\n"); goto errout; } - nllinfo("PHYID2: %04x PHY address: %02x\n", phyid2, priv->phyaddr); + ninfo("PHYID2: %04x PHY address: %02x\n", phyid2, priv->phyaddr); if (phyid1 == MII_OUI_MSB && ((phyid2 & MII_PHYID2_OUI_MASK) >> MII_PHYID2_OUI_SHIFT) == MII_OUI_LSB) { - nllinfo(" Vendor Model Number: %04x\n", - (phyid2 & MII_PHYID2_MODEL_MASK) >> MII_PHYID2_MODEL_SHIFT); - nllinfo(" Model Revision Number: %04x\n", - (phyid2 & MII_PHYID2_REV_MASK) >> MII_PHYID2_REV_SHIFT); + ninfo(" Vendor Model Number: %04x\n", + (phyid2 & MII_PHYID2_MODEL_MASK) >> MII_PHYID2_MODEL_SHIFT); + ninfo(" Model Revision Number: %04x\n", + (phyid2 & MII_PHYID2_REV_MASK) >> MII_PHYID2_REV_SHIFT); } else { - nllerr("ERROR: PHY not recognized\n"); + nerr("ERROR: PHY not recognized\n"); } /* Setup control register */ @@ -3059,7 +3059,7 @@ static int sam_autonegotiate(struct sam_emac_s *priv) ret = sam_phyread(priv, priv->phyaddr, MII_MCR, &mcr); if (ret < 0) { - nllerr("ERROR: Failed to read MCR\n"); + nerr("ERROR: Failed to read MCR\n"); goto errout; } @@ -3070,7 +3070,7 @@ static int sam_autonegotiate(struct sam_emac_s *priv) ret = sam_phywrite(priv, priv->phyaddr, MII_MCR, mcr); if (ret < 0) { - nllerr("ERROR: Failed to write MCR\n"); + nerr("ERROR: Failed to write MCR\n"); goto errout; } @@ -3085,7 +3085,7 @@ static int sam_autonegotiate(struct sam_emac_s *priv) ret = sam_phywrite(priv, priv->phyaddr, MII_ADVERTISE, advertise); if (ret < 0) { - nllerr("ERROR: Failed to write ANAR\n"); + nerr("ERROR: Failed to write ANAR\n"); goto errout; } @@ -3094,7 +3094,7 @@ static int sam_autonegotiate(struct sam_emac_s *priv) ret = sam_phyread(priv, priv->phyaddr, MII_MCR, &mcr); if (ret < 0) { - nllerr("ERROR: Failed to read MCR\n"); + nerr("ERROR: Failed to read MCR\n"); goto errout; } @@ -3102,7 +3102,7 @@ static int sam_autonegotiate(struct sam_emac_s *priv) ret = sam_phywrite(priv, priv->phyaddr, MII_MCR, mcr); if (ret < 0) { - nllerr("ERROR: Failed to write MCR\n"); + nerr("ERROR: Failed to write MCR\n"); goto errout; } @@ -3114,11 +3114,11 @@ static int sam_autonegotiate(struct sam_emac_s *priv) ret = sam_phywrite(priv, priv->phyaddr, MII_MCR, mcr); if (ret < 0) { - nllerr("ERROR: Failed to write MCR\n"); + nerr("ERROR: Failed to write MCR\n"); goto errout; } - nllinfo(" MCR: %04x\n", mcr); + ninfo(" MCR: %04x\n", mcr); /* Check AutoNegotiate complete */ @@ -3128,7 +3128,7 @@ static int sam_autonegotiate(struct sam_emac_s *priv) ret = sam_phyread(priv, priv->phyaddr, MII_MSR, &msr); if (ret < 0) { - nllerr("ERROR: Failed to read MSR\n"); + nerr("ERROR: Failed to read MSR\n"); goto errout; } @@ -3138,7 +3138,7 @@ static int sam_autonegotiate(struct sam_emac_s *priv) { /* Yes.. break out of the loop */ - nllinfo("AutoNegotiate complete\n"); + ninfo("AutoNegotiate complete\n"); break; } @@ -3146,7 +3146,7 @@ static int sam_autonegotiate(struct sam_emac_s *priv) if (++timeout >= PHY_RETRY_MAX) { - nllerr("ERROR: TimeOut\n"); + nerr("ERROR: TimeOut\n"); sam_phydump(priv); ret = -ETIMEDOUT; goto errout; @@ -3158,7 +3158,7 @@ static int sam_autonegotiate(struct sam_emac_s *priv) ret = sam_phyread(priv, priv->phyaddr, MII_LPA, &lpa); if (ret < 0) { - nllerr("ERROR: Failed to read ANLPAR\n"); + nerr("ERROR: Failed to read ANLPAR\n"); goto errout; } @@ -3244,13 +3244,13 @@ static bool sam_linkup(struct sam_emac_s *priv) ret = sam_phyread(priv, priv->phyaddr, MII_MSR, &msr); if (ret < 0) { - nllerr("ERROR: Failed to read MSR: %d\n", ret); + nerr("ERROR: Failed to read MSR: %d\n", ret); goto errout; } if ((msr & MII_MSR_LINKSTATUS) == 0) { - nllerr("ERROR: MSR LinkStatus: %04x\n", msr); + nerr("ERROR: MSR LinkStatus: %04x\n", msr); goto errout; } @@ -3259,7 +3259,7 @@ static bool sam_linkup(struct sam_emac_s *priv) ret = sam_phyread(priv, priv->phyaddr, CONFIG_SAM34_EMAC_PHYSR, &physr); if (ret < 0) { - nllerr("ERROR: Failed to read PHYSR: %d\n", ret); + nerr("ERROR: Failed to read PHYSR: %d\n", ret); goto errout; } @@ -3297,7 +3297,7 @@ static bool sam_linkup(struct sam_emac_s *priv) /* Start the EMAC transfers */ - nllinfo("Link is up\n"); + ninfo("Link is up\n"); linkup = true; errout: @@ -3354,7 +3354,7 @@ static int sam_phyinit(struct sam_emac_s *priv) ret = sam_phyfind(priv, &priv->phyaddr); if (ret < 0) { - nllerr("ERROR: sam_phyfind failed: %d\n", ret); + nerr("ERROR: sam_phyfind failed: %d\n", ret); return ret; } @@ -3598,11 +3598,11 @@ static void sam_macaddress(struct sam_emac_s *priv) struct net_driver_s *dev = &priv->dev; uint32_t regval; - nllinfo("%s MAC: %02x:%02x:%02x:%02x:%02x:%02x\n", - dev->d_ifname, - dev->d_mac.ether_addr_octet[0], dev->d_mac.ether_addr_octet[1], - dev->d_mac.ether_addr_octet[2], dev->d_mac.ether_addr_octet[3], - dev->d_mac.ether_addr_octet[4], dev->d_mac.ether_addr_octet[5]); + ninfo("%s MAC: %02x:%02x:%02x:%02x:%02x:%02x\n", + dev->d_ifname, + dev->d_mac.ether_addr_octet[0], dev->d_mac.ether_addr_octet[1], + dev->d_mac.ether_addr_octet[2], dev->d_mac.ether_addr_octet[3], + dev->d_mac.ether_addr_octet[4], dev->d_mac.ether_addr_octet[5]); /* Set the MAC address */ @@ -3710,7 +3710,7 @@ static int sam_emac_configure(struct sam_emac_s *priv) { uint32_t regval; - nllinfo("Entry\n"); + ninfo("Entry\n"); /* Enable clocking to the EMAC peripheral */ @@ -3823,14 +3823,14 @@ void up_netinitialize(void) priv->txpoll = wd_create(); if (!priv->txpoll) { - nllerr("ERROR: Failed to create periodic poll timer\n"); + nerr("ERROR: Failed to create periodic poll timer\n"); return; } priv->txtimeout = wd_create(); /* Create TX timeout timer */ if (!priv->txtimeout) { - nllerr("ERROR: Failed to create periodic poll timer\n"); + nerr("ERROR: Failed to create periodic poll timer\n"); goto errout_with_txpoll; } @@ -3843,7 +3843,7 @@ void up_netinitialize(void) ret = sam_buffer_initialize(priv); if (ret < 0) { - nllerr("ERROR: sam_buffer_initialize failed: %d\n", ret); + nerr("ERROR: sam_buffer_initialize failed: %d\n", ret); goto errout_with_txtimeout; } @@ -3854,7 +3854,7 @@ void up_netinitialize(void) ret = irq_attach(SAM_IRQ_EMAC, sam_emac_interrupt); if (ret < 0) { - nllerr("ERROR: Failed to attach the handler to the IRQ%d\n", SAM_IRQ_EMAC); + nerr("ERROR: Failed to attach the handler to the IRQ%d\n", SAM_IRQ_EMAC); goto errout_with_buffers; } @@ -3867,7 +3867,7 @@ void up_netinitialize(void) ret = sam_ifdown(&priv->dev); if (ret < 0) { - nllerr("ERROR: Failed to put the interface in the down state: %d\n", ret); + nerr("ERROR: Failed to put the interface in the down state: %d\n", ret); goto errout_with_buffers; } @@ -3879,7 +3879,7 @@ void up_netinitialize(void) return; } - nllerr("ERROR: netdev_register() failed: %d\n", ret); + nerr("ERROR: netdev_register() failed: %d\n", ret); errout_with_buffers: sam_buffer_free(priv); diff --git a/arch/arm/src/sam34/sam_hsmci.c b/arch/arm/src/sam34/sam_hsmci.c index f07fdf5be3..e46ee1c370 100644 --- a/arch/arm/src/sam34/sam_hsmci.c +++ b/arch/arm/src/sam34/sam_hsmci.c @@ -104,7 +104,7 @@ #define SAM34_HSMCI_PRIO NVIC_SYSH_PRIORITY_DEFAULT -#if !defined(CONFIG_DEBUG_FS) || !defined(CONFIG_DEBUG_INFO) +#ifndef CONFIG_DEBUG_MEMCARD_INFO # undef CONFIG_SAM34_HSMCI_CMDDEBUG # undef CONFIG_SAM34_HSMCI_XFRDEBUG #endif @@ -831,38 +831,38 @@ static void sam_hsmcisample(struct sam_hsmciregs_s *regs) #if defined(CONFIG_SAM34_HSMCI_XFRDEBUG) || defined(CONFIG_SAM34_HSMCI_CMDDEBUG) static void sam_hsmcidump(struct sam_hsmciregs_s *regs, const char *msg) { - ferr("HSMCI Registers: %s\n", msg); - ferr(" MR[%08x]: %08x\n", SAM_HSMCI_MR, regs->mr); - ferr(" DTOR[%08x]: %08x\n", SAM_HSMCI_DTOR, regs->dtor); - ferr(" SDCR[%08x]: %08x\n", SAM_HSMCI_SDCR, regs->sdcr); - ferr(" ARGR[%08x]: %08x\n", SAM_HSMCI_ARGR, regs->argr); - ferr(" BLKR[%08x]: %08x\n", SAM_HSMCI_BLKR, regs->blkr); - ferr(" CSTOR[%08x]: %08x\n", SAM_HSMCI_CSTOR, regs->cstor); - ferr(" RSPR0[%08x]: %08x\n", SAM_HSMCI_RSPR0, regs->rsp0); - ferr(" RSPR1[%08x]: %08x\n", SAM_HSMCI_RSPR1, regs->rsp1); - ferr(" RSPR2[%08x]: %08x\n", SAM_HSMCI_RSPR2, regs->rsp2); - ferr(" RSPR3[%08x]: %08x\n", SAM_HSMCI_RSPR3, regs->rsp3); - ferr(" SR[%08x]: %08x\n", SAM_HSMCI_SR, regs->sr); - ferr(" IMR[%08x]: %08x\n", SAM_HSMCI_IMR, regs->imr); + mcinfo("HSMCI Registers: %s\n", msg); + mcinfo(" MR[%08x]: %08x\n", SAM_HSMCI_MR, regs->mr); + mcinfo(" DTOR[%08x]: %08x\n", SAM_HSMCI_DTOR, regs->dtor); + mcinfo(" SDCR[%08x]: %08x\n", SAM_HSMCI_SDCR, regs->sdcr); + mcinfo(" ARGR[%08x]: %08x\n", SAM_HSMCI_ARGR, regs->argr); + mcinfo(" BLKR[%08x]: %08x\n", SAM_HSMCI_BLKR, regs->blkr); + mcinfo(" CSTOR[%08x]: %08x\n", SAM_HSMCI_CSTOR, regs->cstor); + mcinfo(" RSPR0[%08x]: %08x\n", SAM_HSMCI_RSPR0, regs->rsp0); + mcinfo(" RSPR1[%08x]: %08x\n", SAM_HSMCI_RSPR1, regs->rsp1); + mcinfo(" RSPR2[%08x]: %08x\n", SAM_HSMCI_RSPR2, regs->rsp2); + mcinfo(" RSPR3[%08x]: %08x\n", SAM_HSMCI_RSPR3, regs->rsp3); + mcinfo(" SR[%08x]: %08x\n", SAM_HSMCI_SR, regs->sr); + mcinfo(" IMR[%08x]: %08x\n", SAM_HSMCI_IMR, regs->imr); #if defined(CONFIG_ARCH_CHIP_SAM3U) - ferr(" DMA[%08x]: %08x\n", SAM_HSMCI_DMA, regs->dma); + mcinfo(" DMA[%08x]: %08x\n", SAM_HSMCI_DMA, regs->dma); #endif - ferr(" CFG[%08x]: %08x\n", SAM_HSMCI_CFG, regs->cfg); - ferr(" WPMR[%08x]: %08x\n", SAM_HSMCI_WPMR, regs->wpmr); - ferr(" WPSR[%08x]: %08x\n", SAM_HSMCI_WPSR, regs->wpsr); + mcinfo(" CFG[%08x]: %08x\n", SAM_HSMCI_CFG, regs->cfg); + mcinfo(" WPMR[%08x]: %08x\n", SAM_HSMCI_WPMR, regs->wpmr); + mcinfo(" WPSR[%08x]: %08x\n", SAM_HSMCI_WPSR, regs->wpsr); #ifdef CONFIG_SAM34_PDCA - ferr("HSMCI PDC Registers:\n"); - ferr(" RPR[%08x]: %08x\n", SAM_HSMCI_PDC_RPR, regs->pdc_rpr); - ferr(" RCR[%08x]: %08x\n", SAM_HSMCI_PDC_RCR, regs->pdc_rcr); - ferr(" TPR[%08x]: %08x\n", SAM_HSMCI_PDC_TPR, regs->pdc_tpr); - ferr(" TCR[%08x]: %08x\n", SAM_HSMCI_PDC_TCR, regs->pdc_tcr); - ferr(" RNPR[%08x]: %08x\n", SAM_HSMCI_PDC_RNPR, regs->pdc_rnpr); - ferr(" RNCR[%08x]: %08x\n", SAM_HSMCI_PDC_RNCR, regs->pdc_rncr); - ferr(" TNPR[%08x]: %08x\n", SAM_HSMCI_PDC_TNPR, regs->pdc_tnpr); - ferr(" TNCR[%08x]: %08x\n", SAM_HSMCI_PDC_TNCR, regs->pdc_tncr); -//ferr(" TCR[%08x]: %08x\n", SAM_HSMCI_PDC_PTCR, regs->pdc_ptcr); - ferr(" PTSR[%08x]: %08x\n", SAM_HSMCI_PDC_PTSR, regs->pdc_ptsr); + mcinfo("HSMCI PDC Registers:\n"); + mcinfo(" RPR[%08x]: %08x\n", SAM_HSMCI_PDC_RPR, regs->pdc_rpr); + mcinfo(" RCR[%08x]: %08x\n", SAM_HSMCI_PDC_RCR, regs->pdc_rcr); + mcinfo(" TPR[%08x]: %08x\n", SAM_HSMCI_PDC_TPR, regs->pdc_tpr); + mcinfo(" TCR[%08x]: %08x\n", SAM_HSMCI_PDC_TCR, regs->pdc_tcr); + mcinfo(" RNPR[%08x]: %08x\n", SAM_HSMCI_PDC_RNPR, regs->pdc_rnpr); + mcinfo(" RNCR[%08x]: %08x\n", SAM_HSMCI_PDC_RNCR, regs->pdc_rncr); + mcinfo(" TNPR[%08x]: %08x\n", SAM_HSMCI_PDC_TNPR, regs->pdc_tnpr); + mcinfo(" TNCR[%08x]: %08x\n", SAM_HSMCI_PDC_TNCR, regs->pdc_tncr); +//mcinfo(" TCR[%08x]: %08x\n", SAM_HSMCI_PDC_PTCR, regs->pdc_ptcr); + mcinfo(" PTSR[%08x]: %08x\n", SAM_HSMCI_PDC_PTSR, regs->pdc_ptsr); #endif } #endif @@ -1083,7 +1083,7 @@ static void sam_eventtimeout(int argc, uint32_t arg) /* Yes.. wake up any waiting threads */ sam_endwait(priv, SDIOWAIT_TIMEOUT); - fllerr("Timeout\n"); + mcllerr("ERROR: Timeout\n"); } } @@ -1278,7 +1278,7 @@ static int sam_interrupt(int irq, void *context) { /* Yes.. Was it some kind of timeout error? */ - fllerr("ERROR: enabled: %08x pending: %08x\n", enabled, pending); + mcllerr("ERROR: enabled: %08x pending: %08x\n", enabled, pending); if ((pending & HSMCI_DATA_TIMEOUT_ERRORS) != 0) { /* Yes.. Terminate with a timeout. */ @@ -1320,7 +1320,7 @@ static int sam_interrupt(int irq, void *context) { /* Yes.. Was the error some kind of timeout? */ - fllinfo("ERROR: events: %08x SR: %08x\n", + mcllinfo("ERROR: events: %08x SR: %08x\n", priv->cmdrmask, enabled); if ((pending & HSMCI_RESPONSE_TIMEOUT_ERRORS) != 0) @@ -1754,7 +1754,7 @@ static int sam_sendcmd(FAR struct sdio_dev_s *dev, /* Write the fully decorated command to CMDR */ - finfo("cmd: %08x arg: %08x regval: %08x\n", cmd, arg, regval); + mcinfo("cmd: %08x arg: %08x regval: %08x\n", cmd, arg, regval); putreg32(regval, SAM_HSMCI_CMDR); sam_cmdsample1(SAMPLENDX_AFTER_CMDR); return OK; @@ -1933,7 +1933,7 @@ static int sam_waitresponse(FAR struct sdio_dev_s *dev, uint32_t cmd) { /* Yes.. Was the error some kind of timeout? */ - ferr("ERROR: cmd: %08x events: %08x SR: %08x\n", + mcerr("ERROR: cmd: %08x events: %08x SR: %08x\n", cmd, priv->cmdrmask, sr); if ((pending & HSMCI_RESPONSE_TIMEOUT_ERRORS) != 0) @@ -1963,7 +1963,7 @@ static int sam_waitresponse(FAR struct sdio_dev_s *dev, uint32_t cmd) } else if (--timeout <= 0) { - ferr("ERROR: Timeout cmd: %08x events: %08x SR: %08x\n", + mcerr("ERROR: Timeout cmd: %08x events: %08x SR: %08x\n", cmd, priv->cmdrmask, sr); priv->wkupevent = SDIOWAIT_TIMEOUT; @@ -2038,7 +2038,7 @@ static int sam_recvshort(FAR struct sdio_dev_s *dev, #ifdef CONFIG_DEBUG_FEATURES if (!rshort) { - ferr("ERROR: rshort=NULL\n"); + mcerr("ERROR: rshort=NULL\n"); ret = -EINVAL; } @@ -2050,7 +2050,7 @@ static int sam_recvshort(FAR struct sdio_dev_s *dev, (cmd & MMCSD_RESPONSE_MASK) != MMCSD_R3_RESPONSE && (cmd & MMCSD_RESPONSE_MASK) != MMCSD_R7_RESPONSE) { - ferr("ERROR: Wrong response CMD=%08x\n", cmd); + mcerr("ERROR: Wrong response CMD=%08x\n", cmd); ret = -EINVAL; } else @@ -2100,7 +2100,7 @@ static int sam_recvlong(FAR struct sdio_dev_s *dev, uint32_t cmd, uint32_t rlong if ((cmd & MMCSD_RESPONSE_MASK) != MMCSD_R2_RESPONSE) { - ferr("ERROR: Wrong response CMD=%08x\n", cmd); + mcerr("ERROR: Wrong response CMD=%08x\n", cmd); ret = -EINVAL; } else @@ -2282,7 +2282,7 @@ static sdio_eventset_t sam_eventwait(FAR struct sdio_dev_s *dev, 1, (uint32_t)priv); if (ret != OK) { - ferr("ERROR: wd_start failed: %d\n", ret); + mcerr("ERROR: wd_start failed: %d\n", ret); } } @@ -2348,7 +2348,7 @@ static void sam_callbackenable(FAR struct sdio_dev_s *dev, { struct sam_dev_s *priv = (struct sam_dev_s *)dev; - finfo("eventset: %02x\n", eventset); + mcinfo("eventset: %02x\n", eventset); DEBUGASSERT(priv != NULL); priv->cbevents = eventset; @@ -2384,7 +2384,7 @@ static int sam_registercallback(FAR struct sdio_dev_s *dev, /* Disable callbacks and register this callback and is argument */ - finfo("Register %p(%p)\n", callback, arg); + mcinfo("Register %p(%p)\n", callback, arg); DEBUGASSERT(priv != NULL); priv->cbevents = 0; @@ -2472,7 +2472,8 @@ static int sam_dmarecvsetup(FAR struct sdio_dev_s *dev, FAR uint8_t *buffer, #ifdef CONFIG_SAM34_PDCA modifyreg32(SAM_HSMCI_MR, 0, HSMCI_MR_PDCMODE); - ferr("SAM_HSMCI_MR = 0x%08X\n", getreg32(SAM_HSMCI_MR)); + mcinfo("SAM_HSMCI_MR = 0x%08X\n", getreg32(SAM_HSMCI_MR)); + putreg32((uint32_t)buffer, SAM_HSMCI_PDC_RPR); putreg32(buflen/4, SAM_HSMCI_PDC_RCR); putreg32(PDC_PTCR_RXTEN, SAM_HSMCI_PDC_PTCR); @@ -2541,7 +2542,8 @@ static int sam_dmasendsetup(FAR struct sdio_dev_s *dev, #ifdef CONFIG_SAM34_PDCA modifyreg32(SAM_HSMCI_MR, 0, HSMCI_MR_PDCMODE); - ferr("SAM_HSMCI_MR = 0x%08X\n", getreg32(SAM_HSMCI_MR)); + mcinfo("SAM_HSMCI_MR = 0x%08X\n", getreg32(SAM_HSMCI_MR)); + putreg32((uint32_t)buffer, SAM_HSMCI_PDC_TPR); putreg32(buflen/4, SAM_HSMCI_PDC_TCR); putreg32(PDC_PTCR_TXTEN, SAM_HSMCI_PDC_PTCR); @@ -2581,7 +2583,7 @@ static void sam_callback(void *arg) /* Is a callback registered? */ DEBUGASSERT(priv != NULL); - finfo("Callback %p(%p) cbevents: %02x cdstatus: %02x\n", + mcinfo("Callback %p(%p) cbevents: %02x cdstatus: %02x\n", priv->callback, priv->cbarg, priv->cbevents, priv->cdstatus); if (priv->callback) @@ -2626,14 +2628,14 @@ static void sam_callback(void *arg) { /* Yes.. queue it */ - fllinfo("Queuing callback to %p(%p)\n", priv->callback, priv->cbarg); + mcllinfo("Queuing callback to %p(%p)\n", priv->callback, priv->cbarg); (void)work_queue(LPWORK, &priv->cbwork, (worker_t)priv->callback, priv->cbarg, 0); } else { /* No.. then just call the callback here */ - finfo("Callback to %p(%p)\n", priv->callback, priv->cbarg); + mcinfo("Callback to %p(%p)\n", priv->callback, priv->cbarg); priv->callback(priv->cbarg); } } @@ -2663,7 +2665,7 @@ FAR struct sdio_dev_s *sdio_initialize(int slotno) struct sam_dev_s *priv = &g_sdiodev; - ferr("slotno: %d\n", slotno); + mcinfo("slotno: %d\n", slotno); /* Initialize the HSMCI slot structure */ @@ -2741,7 +2743,7 @@ void sdio_mediachange(FAR struct sdio_dev_s *dev, bool cardinslot) priv->cdstatus &= ~SDIO_STATUS_PRESENT; } - fllinfo("cdstatus OLD: %02x NEW: %02x\n", cdstatus, priv->cdstatus); + mcllinfo("cdstatus OLD: %02x NEW: %02x\n", cdstatus, priv->cdstatus); /* Perform any requested callback if the status has changed */ @@ -2786,7 +2788,7 @@ void sdio_wrprotect(FAR struct sdio_dev_s *dev, bool wrprotect) priv->cdstatus &= ~SDIO_STATUS_WRPROTECTED; } - finfo("cdstatus: %02x\n", priv->cdstatus); + mcinfo("cdstatus: %02x\n", priv->cdstatus); leave_critical_section(flags); } #endif /* CONFIG_SAM34_HSMCI */ diff --git a/arch/arm/src/sam34/sam_rtc.c b/arch/arm/src/sam34/sam_rtc.c index 6c261ce415..e6e5d0b699 100644 --- a/arch/arm/src/sam34/sam_rtc.c +++ b/arch/arm/src/sam34/sam_rtc.c @@ -274,7 +274,7 @@ static int rtc_interrupt(int irq, void *context) ret = work_queue(LPWORK, &g_alarmwork, rtc_worker, NULL, 0); if (ret < 0) { - rtcllerr("ERR0R: work_queue failed: %d\n", ret); + rtcllerr("ERROR: work_queue failed: %d\n", ret); } /* Disable any further alarm interrupts */ diff --git a/arch/arm/src/sam34/sam_rtt.c b/arch/arm/src/sam34/sam_rtt.c index 385aa37d01..9df244ccce 100644 --- a/arch/arm/src/sam34/sam_rtt.c +++ b/arch/arm/src/sam34/sam_rtt.c @@ -74,18 +74,8 @@ /* Configuration ************************************************************/ -/* Debug ********************************************************************/ -/* Non-standard debug that may be enabled just for testing the timer - * driver. NOTE: that only llerr types are used so that the output is - * immediately available. - */ - -#ifdef CONFIG_DEBUG_RTT -# define rtterr _llerr -# define rttinfo _llinfo -#else -# define rtterr(x...) -# define rttinfo(x...) +#ifndef CONFIG_DEBUG_TIMER_INFO +# undef CONFIG_SAM34_RTT_REGDEBUG #endif /**************************************************************************** @@ -115,7 +105,7 @@ struct sam34_lowerhalf_s ****************************************************************************/ /* Register operations ******************************************************/ -#if defined(CONFIG_SAM34_RTT_REGDEBUG) && defined(CONFIG_DEBUG_FEATURES) +#ifdef CONFIG_SAM34_RTT_REGDEBUG static uint32_t sam34_getreg(uint32_t addr); static void sam34_putreg(uint32_t val, uint32_t addr); #else @@ -193,7 +183,7 @@ static inline uint32_t sam34_readvr(void) * ****************************************************************************/ -#if defined(CONFIG_SAM34_RTT_REGDEBUG) && defined(CONFIG_DEBUG_FEATURES) +#ifdef CONFIG_SAM34_RTT_REGDEBUG static uint32_t sam34_getreg(uint32_t addr) { static uint32_t prevaddr = 0; @@ -214,7 +204,7 @@ static uint32_t sam34_getreg(uint32_t addr) { if (count == 4) { - _llerr("...\n"); + tmrinfo("...\n"); } return val; @@ -231,7 +221,7 @@ static uint32_t sam34_getreg(uint32_t addr) { /* Yes.. then show how many times the value repeated */ - _llerr("[repeats %d more times]\n", count-3); + tmrinfo("[repeats %d more times]\n", count-3); } /* Save the new address, value, and count */ @@ -243,7 +233,7 @@ static uint32_t sam34_getreg(uint32_t addr) /* Show the register value read */ - _llerr("%08lx->%08lx\n", addr, val); + tmrinfo("%08lx->%08lx\n", addr, val); return val; } #endif @@ -256,12 +246,12 @@ static uint32_t sam34_getreg(uint32_t addr) * ****************************************************************************/ -#if defined(CONFIG_SAM34_RTT_REGDEBUG) && defined(CONFIG_DEBUG_FEATURES) +#ifdef CONFIG_SAM34_RTT_REGDEBUG static void sam34_putreg(uint32_t val, uint32_t addr) { /* Show the register value being written */ - _llerr("%08lx<-%08lx\n", addr, val); + tmrinfo("%08lx<-%08lx\n", addr, val); /* Write the value */ @@ -287,7 +277,7 @@ static int sam34_interrupt(int irq, FAR void *context) { FAR struct sam34_lowerhalf_s *priv = &g_tcdev; - rttinfo("Entry\n"); + tmrinfo("Entry\n"); DEBUGASSERT(irq == SAM_IRQ_RTT); /* Check if the interrupt is really pending */ @@ -373,7 +363,7 @@ static int sam34_start(FAR struct timer_lowerhalf_s *lower) uint32_t mr; uint32_t vr; - rttinfo("Entry\n"); + tmrinfo("Entry\n"); DEBUGASSERT(priv); if (priv->started) @@ -433,7 +423,7 @@ static int sam34_start(FAR struct timer_lowerhalf_s *lower) static int sam34_stop(FAR struct timer_lowerhalf_s *lower) { FAR struct sam34_lowerhalf_s *priv = (FAR struct sam34_lowerhalf_s *)lower; - rttinfo("Entry\n"); + tmrinfo("Entry\n"); DEBUGASSERT(priv); if (!priv->started) @@ -474,7 +464,7 @@ static int sam34_getstatus(FAR struct timer_lowerhalf_s *lower, { FAR struct sam34_lowerhalf_s *priv = (FAR struct sam34_lowerhalf_s *)lower; - rttinfo("Entry\n"); + tmrinfo("Entry\n"); DEBUGASSERT(priv); /* Return the status bit */ @@ -498,9 +488,9 @@ static int sam34_getstatus(FAR struct timer_lowerhalf_s *lower, status->timeleft = 1000000ULL*(sam34_getreg(SAM_RTT_AR) - sam34_readvr())/RTT_FCLK; - rttinfo(" flags : %08x\n", status->flags); - rttinfo(" timeout : %d\n", status->timeout); - rttinfo(" timeleft : %d\n", status->timeleft); + tmrinfo(" flags : %08x\n", status->flags); + tmrinfo(" timeout : %d\n", status->timeout); + tmrinfo(" timeleft : %d\n", status->timeleft); return OK; } @@ -526,7 +516,7 @@ static int sam34_settimeout(FAR struct timer_lowerhalf_s *lower, FAR struct sam34_lowerhalf_s *priv = (FAR struct sam34_lowerhalf_s *)lower; DEBUGASSERT(priv); - rttinfo("Entry: timeout=%d\n", timeout); + tmrinfo("Entry: timeout=%d\n", timeout); if (priv->started) { @@ -537,7 +527,7 @@ static int sam34_settimeout(FAR struct timer_lowerhalf_s *lower, if (timeout < 1 || timeout > RTT_MAXTIMEOUT) { - rtterr("Cannot represent timeout=%lu > %lu\n", + tmrerr("ERROR: Cannot represent timeout=%lu > %lu\n", timeout, RTT_MAXTIMEOUT); return -ERANGE; } @@ -547,7 +537,7 @@ static int sam34_settimeout(FAR struct timer_lowerhalf_s *lower, timeout = (1000000ULL * priv->clkticks) / RTT_FCLK; /* Truncated timeout */ priv->adjustment = priv->timeout - timeout; /* Truncated time to be added to next interval (dither) */ - rttinfo("fclk=%d clkticks=%d timout=%d, adjustment=%d\n", + tmrinfo("fclk=%d clkticks=%d timout=%d, adjustment=%d\n", RTT_FCLK, priv->clkticks, priv->timeout, priv->adjustment); return OK; @@ -582,7 +572,7 @@ static tccb_t sam34_sethandler(FAR struct timer_lowerhalf_s *lower, flags = enter_critical_section(); DEBUGASSERT(priv); - rttinfo("Entry: handler=%p\n", handler); + tmrinfo("Entry: handler=%p\n", handler); /* Get the old handler return value */ @@ -623,7 +613,7 @@ static int sam34_ioctl(FAR struct timer_lowerhalf_s *lower, int cmd, int ret = -ENOTTY; DEBUGASSERT(priv); - rttinfo("Entry: cmd=%d arg=%ld\n", cmd, arg); + tmrinfo("Entry: cmd=%d arg=%ld\n", cmd, arg); UNUSED(priv); return ret; @@ -653,7 +643,7 @@ void sam_rttinitialize(FAR const char *devpath) { FAR struct sam34_lowerhalf_s *priv = &g_tcdev; - rttinfo("Entry: devpath=%s\n", devpath); + tmrinfo("Entry: devpath=%s\n", devpath); /* Initialize the driver state structure. Here we assume: (1) the state * structure lies in .bss and was zeroed at reset time. (2) This function diff --git a/arch/arm/src/sam34/sam_spi.c b/arch/arm/src/sam34/sam_spi.c index 488a0d8d1e..4b7f1dba7e 100644 --- a/arch/arm/src/sam34/sam_spi.c +++ b/arch/arm/src/sam34/sam_spi.c @@ -102,7 +102,11 @@ # endif #endif -#ifndef CONFIG_SAM34_SPI_DMA +#ifndef CONFIG_DEBUG_SPI_INFO +# undef CONFIG_SAM34_SPI_REGDEBUG +#endif + +#ifndef CONFIG_DEBUG_DMA_INFO # undef CONFIG_SAM34_SPI_DMADEBUG #endif @@ -134,7 +138,7 @@ /* Debug *******************************************************************/ /* Check if SPI debut is enabled */ -#ifndef CONFIG_DEBUG_DMA +#ifndef CONFIG_DEBUG_DMA_INFO # undef CONFIG_SAM34_SPI_DMADEBUG #endif @@ -420,7 +424,7 @@ static bool spi_checkreg(struct sam_spidev_s *spi, bool wr, uint32_t value, { /* Yes... show how many times we did it */ - _llerr("...[Repeats %d times]...\n", spi->ntimes); + spiinfo("...[Repeats %d times]...\n", spi->ntimes); } /* Save information about the new access */ @@ -454,7 +458,7 @@ static inline uint32_t spi_getreg(struct sam_spidev_s *spi, #ifdef CONFIG_SAM34_SPI_REGDEBUG if (spi_checkreg(spi, false, value, address)) { - _llerr("%08x->%08x\n", address, value); + spiinfo("%08x->%08x\n", address, value); } #endif @@ -477,7 +481,7 @@ static inline void spi_putreg(struct sam_spidev_s *spi, uint32_t value, #ifdef CONFIG_SAM34_SPI_REGDEBUG if (spi_checkreg(spi, true, value, address)) { - _llerr("%08x<-%08x\n", address, value); + spiinfo("%08x<-%08x\n", address, value); } #endif @@ -1055,7 +1059,7 @@ static uint32_t spi_setfrequency(struct spi_dev_s *dev, uint32_t frequency) spics->frequency = frequency; spics->actual = actual; - spierr("Frequency %d->%d\n", frequency, actual); + spiinfo("Frequency %d->%d\n", frequency, actual); return actual; } diff --git a/arch/arm/src/sam34/sam_tc.c b/arch/arm/src/sam34/sam_tc.c index 26a73eff82..369aa7323a 100644 --- a/arch/arm/src/sam34/sam_tc.c +++ b/arch/arm/src/sam34/sam_tc.c @@ -63,6 +63,12 @@ /**************************************************************************** * Pre-processor Definitions ****************************************************************************/ +/* Configuration ************************************************************/ + +#ifndef CONFIG_DEBUG_TIMER_INFO +# undef CONFIG_SAM34_TC_REGDEBUG +#endif + /* Clocking *****************************************************************/ /* TODO: Allow selection of any of the input clocks */ @@ -98,7 +104,7 @@ struct sam34_lowerhalf_s ****************************************************************************/ /* Register operations ******************************************************/ -#if defined(CONFIG_SAM34_TC_REGDEBUG) && defined(CONFIG_DEBUG_FEATURES) +#ifdef CONFIG_SAM34_TC_REGDEBUG static uint32_t sam34_getreg(uint32_t addr); static void sam34_putreg(uint32_t val, uint32_t addr); #else @@ -158,7 +164,7 @@ static struct sam34_lowerhalf_s g_tcdevs[6]; * ****************************************************************************/ -#if defined(CONFIG_SAM34_TC_REGDEBUG) && defined(CONFIG_DEBUG_FEATURES) +#ifdef CONFIG_SAM34_TC_REGDEBUG static uint32_t sam34_getreg(uint32_t addr) { static uint32_t prevaddr = 0; @@ -179,7 +185,7 @@ static uint32_t sam34_getreg(uint32_t addr) { if (count == 4) { - _llerr("...\n"); + tmrinfo("...\n"); } return val; @@ -196,7 +202,7 @@ static uint32_t sam34_getreg(uint32_t addr) { /* Yes.. then show how many times the value repeated */ - _llerr("[repeats %d more times]\n", count-3); + tmrinfo("[repeats %d more times]\n", count-3); } /* Save the new address, value, and count */ @@ -208,7 +214,7 @@ static uint32_t sam34_getreg(uint32_t addr) /* Show the register value read */ - _llerr("%08lx->%08lx\n", addr, val); + tmrinfo("%08lx->%08lx\n", addr, val); return val; } #endif @@ -221,12 +227,12 @@ static uint32_t sam34_getreg(uint32_t addr) * ****************************************************************************/ -#if defined(CONFIG_SAM34_TC_REGDEBUG) && defined(CONFIG_DEBUG_FEATURES) +#ifdef CONFIG_SAM34_TC_REGDEBUG static void sam34_putreg(uint32_t val, uint32_t addr) { /* Show the register value being written */ - _llerr("%08lx<-%08lx\n", addr, val); + tmrinfo("%08lx<-%08lx\n", addr, val); /* Write the value */ diff --git a/arch/arm/src/sam34/sam_twi.c b/arch/arm/src/sam34/sam_twi.c index bc13070664..af90936b1b 100644 --- a/arch/arm/src/sam34/sam_twi.c +++ b/arch/arm/src/sam34/sam_twi.c @@ -85,6 +85,10 @@ # define CONFIG_SAM34_TWI1_FREQUENCY 100000 #endif +#ifndef CONFIG_DEBUG_I2C_INFO +# undef CONFIG_SAM34_TWI_REGDEBUG +#endif + /* Driver internal definitions *************************************************/ #define TWI_TIMEOUT ((100 * CLK_TCK) / 1000) /* 100 mS */ @@ -273,7 +277,7 @@ static bool twi_checkreg(struct twi_dev_s *priv, bool wr, uint32_t value, { /* Yes... show how many times we did it */ - _llerr("...[Repeats %d times]...\n", priv->ntimes); + i2cinfo("...[Repeats %d times]...\n", priv->ntimes); } /* Save information about the new access */ @@ -305,7 +309,7 @@ static uint32_t twi_getabs(struct twi_dev_s *priv, uintptr_t address) if (twi_checkreg(priv, false, value, address)) { - _llerr("%08x->%08x\n", address, value); + i2cinfo("%08x->%08x\n", address, value); } return value; @@ -326,7 +330,7 @@ static void twi_putabs(struct twi_dev_s *priv, uintptr_t address, { if (twi_checkreg(priv, true, value, address)) { - _llerr("%08x<-%08x\n", address, value); + i2cinfo("%08x<-%08x\n", address, value); } putreg32(value, address); @@ -386,9 +390,9 @@ static int twi_wait(struct twi_dev_s *priv) do { - i2cllerr("TWI%d Waiting...\n", priv->twi); + i2cllinfo("TWI%d Waiting...\n", priv->twi); twi_takesem(&priv->waitsem); - i2cllerr("TWI%d Awakened with result: %d\n", priv->twi, priv->result); + i2cllinfo("TWI%d Awakened with result: %d\n", priv->twi, priv->result); } while (priv->result == -EBUSY); @@ -578,7 +582,7 @@ static void twi_timeout(int argc, uint32_t arg, ...) { struct twi_dev_s *priv = (struct twi_dev_s *)arg; - i2cllerr("TWI%d Timeout!\n", priv->twi); + i2cllerr("ERROR: TWI%d Timeout!\n", priv->twi); twi_wakeup(priv, -ETIMEDOUT); } diff --git a/arch/arm/src/sam34/sam_udp.c b/arch/arm/src/sam34/sam_udp.c index 4615cd01b0..8c84fce2f8 100644 --- a/arch/arm/src/sam34/sam_udp.c +++ b/arch/arm/src/sam34/sam_udp.c @@ -3115,11 +3115,11 @@ static int sam_ep_submit(struct usbdev_ep_s *ep, struct usbdev_req_s *req) if (privep->stalled || privep->pending) { - /* Yes.. in this case, save the new they will get in a special - * "pending" they will get queue until the stall is cleared. + /* Yes.. in this case, save the request in a special "pending" + * queue. They will stay queuee until the stall is cleared. */ - ullerr("Pending stall clear\n"); + ullinfo("Pending stall clear\n"); sam_req_enqueue(&privep->pendq, privreq); usbtrace(TRACE_INREQQUEUED(epno), req->len); ret = OK; diff --git a/arch/arm/src/sam34/sam_wdt.c b/arch/arm/src/sam34/sam_wdt.c index aa033f4e87..cf3d70b161 100644 --- a/arch/arm/src/sam34/sam_wdt.c +++ b/arch/arm/src/sam34/sam_wdt.c @@ -81,6 +81,10 @@ # define CONFIG_SAM34_WDT_DEFTIMOUT WDT_MAXTIMEOUT #endif +#ifndef CONFIG_DEBUG_WATCHDOG_INFO +# undef CONFIG_SAM34_WDT_REGDEBUG +#endif + /**************************************************************************** * Private Types ****************************************************************************/ @@ -104,7 +108,7 @@ struct sam34_lowerhalf_s ****************************************************************************/ /* Register operations ******************************************************/ -#if defined(CONFIG_SAM34_WDT_REGDEBUG) && defined(CONFIG_DEBUG_FEATURES) +#ifdef CONFIG_SAM34_WDT_REGDEBUG static uint32_t sam34_getreg(uint32_t addr); static void sam34_putreg(uint32_t val, uint32_t addr); #else @@ -162,7 +166,7 @@ static struct sam34_lowerhalf_s g_wdgdev; * ****************************************************************************/ -#if defined(CONFIG_SAM34_WDT_REGDEBUG) && defined(CONFIG_DEBUG_FEATURES) +#ifdef CONFIG_SAM34_WDT_REGDEBUG static uint32_t sam34_getreg(uint32_t addr) { static uint32_t prevaddr = 0; @@ -183,7 +187,7 @@ static uint32_t sam34_getreg(uint32_t addr) { if (count == 4) { - _llerr("...\n"); + wdinfo("...\n"); } return val; @@ -200,7 +204,7 @@ static uint32_t sam34_getreg(uint32_t addr) { /* Yes.. then show how many times the value repeated */ - _llerr("[repeats %d more times]\n", count-3); + wdinfo("[repeats %d more times]\n", count-3); } /* Save the new address, value, and count */ @@ -212,7 +216,7 @@ static uint32_t sam34_getreg(uint32_t addr) /* Show the register value read */ - _llerr("%08x->%08x\n", addr, val); + wdinfo("%08x->%08x\n", addr, val); return val; } #endif @@ -225,12 +229,12 @@ static uint32_t sam34_getreg(uint32_t addr) * ****************************************************************************/ -#if defined(CONFIG_SAM34_WDT_REGDEBUG) && defined(CONFIG_DEBUG_FEATURES) +#ifdef CONFIG_SAM34_WDT_REGDEBUG static void sam34_putreg(uint32_t val, uint32_t addr) { /* Show the register value being written */ - _llerr("%08x<-%08x\n", addr, val); + wdinfo("%08x<-%08x\n", addr, val); /* Write the value */ @@ -463,7 +467,7 @@ static int sam34_settimeout(FAR struct watchdog_lowerhalf_s *lower, if (timeout < 1 || timeout > WDT_MAXTIMEOUT) { - wderr("Cannot represent timeout=%d > %d\n", + wderr("ERROR: Cannot represent timeout=%d > %d\n", timeout, WDT_MAXTIMEOUT); return -ERANGE; } From 4a34540e8f1c2317a1492994ed16138052e4a8b8 Mon Sep 17 00:00:00 2001 From: Gregory Nutt Date: Thu, 16 Jun 2016 16:22:01 -0600 Subject: [PATCH 25/75] Eliminate a warning --- arch/arm/src/stm32/stm32_rcc.c | 2 +- arch/arm/src/stm32l4/stm32l4_rcc.c | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm/src/stm32/stm32_rcc.c b/arch/arm/src/stm32/stm32_rcc.c index 3bd2913076..553f76e73d 100644 --- a/arch/arm/src/stm32/stm32_rcc.c +++ b/arch/arm/src/stm32/stm32_rcc.c @@ -119,7 +119,7 @@ ****************************************************************************/ #if defined(CONFIG_RTC) && defined(CONFIG_STM32_PWR) && !defined(CONFIG_STM32_STM32F10XX) -static inline rcc_resetbkp(void) +static inline void rcc_resetbkp(void) { uint32_t regval; diff --git a/arch/arm/src/stm32l4/stm32l4_rcc.c b/arch/arm/src/stm32l4/stm32l4_rcc.c index b972c2680b..34e6052eef 100644 --- a/arch/arm/src/stm32l4/stm32l4_rcc.c +++ b/arch/arm/src/stm32l4/stm32l4_rcc.c @@ -106,7 +106,7 @@ ****************************************************************************/ #if defined(CONFIG_STM32_PWR) && defined(CONFIG_RTC) -static inline rcc_resetbkp(void) +static inline void rcc_resetbkp(void) { bool init_stat; From 74d0cb8f056a9b4cec42983a6f8a0eff06166a2f Mon Sep 17 00:00:00 2001 From: Gregory Nutt Date: Thu, 16 Jun 2016 16:47:38 -0600 Subject: [PATCH 26/75] Fix another typo introduced in the last set of changes --- arch/arm/src/tiva/lm3s_ethernet.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/src/tiva/lm3s_ethernet.c b/arch/arm/src/tiva/lm3s_ethernet.c index e5e242c624..15f743e072 100644 --- a/arch/arm/src/tiva/lm3s_ethernet.c +++ b/arch/arm/src/tiva/lm3s_ethernet.c @@ -686,7 +686,7 @@ static void tiva_receive(struct tiva_driver_s *priv) /* We will have to drop this packet */ - nllwarn("WARNING: "Bad packet size dropped (%d)\n", pktlen); + nllwarn("WARNING: Bad packet size dropped (%d)\n", pktlen); NETDEV_RXERRORS(&priv->ld_dev); /* The number of bytes and words left to read is pktlen - 4 (including, From 46de4a57791097e4962dc37ad85a5fb0e59d7d0f Mon Sep 17 00:00:00 2001 From: Gregory Nutt Date: Thu, 16 Jun 2016 18:19:37 -0600 Subject: [PATCH 27/75] Fix another search and replace error from last set of changes --- arch/arm/src/stm32/stm32_otghsdev.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm/src/stm32/stm32_otghsdev.c b/arch/arm/src/stm32/stm32_otghsdev.c index daa9fc3c36..08db9b9f37 100644 --- a/arch/arm/src/stm32/stm32_otghsdev.c +++ b/arch/arm/src/stm32/stm32_otghsdev.c @@ -2629,7 +2629,7 @@ static inline void stm32_epout_interrupt(FAR struct stm32_usbdev_s *priv) if ((daint & 1) != 0) { regval = stm32_getreg(STM32_OTGHS_DOEPINT(epno)); - ulinfo("("DOEPINT(%d) = %08x\n", epno, regval); + ulinfo("DOEPINT(%d) = %08x\n", epno, regval); stm32_putreg(0xFF, STM32_OTGHS_DOEPINT(epno)); } @@ -2859,7 +2859,7 @@ static inline void stm32_epin_interrupt(FAR struct stm32_usbdev_s *priv) { if ((daint & 1) != 0) { - ulinfo("("DIEPINT(%d) = %08x\n", + ulinfo("DIEPINT(%d) = %08x\n", epno, stm32_getreg(STM32_OTGHS_DIEPINT(epno))); stm32_putreg(0xFF, STM32_OTGHS_DIEPINT(epno)); } From ea8241027ea2bd2d30268a72bc6ca8d97d1d4bb9 Mon Sep 17 00:00:00 2001 From: Gregory Nutt Date: Thu, 16 Jun 2016 19:57:06 -0600 Subject: [PATCH 28/75] syslog() will now automatically redirect output to lowsyslog() if called from an interrupt handler --- libc/syslog/lib_lowsyslog.c | 10 ++++++++++ libc/syslog/lib_syslog.c | 37 +++++++++++++++++++++++++++++++++---- 2 files changed, 43 insertions(+), 4 deletions(-) diff --git a/libc/syslog/lib_lowsyslog.c b/libc/syslog/lib_lowsyslog.c index 8c9c84c177..8c4b7ed959 100644 --- a/libc/syslog/lib_lowsyslog.c +++ b/libc/syslog/lib_lowsyslog.c @@ -47,6 +47,15 @@ #include "syslog/syslog.h" #if defined(CONFIG_ARCH_LOWPUTC) || defined(CONFIG_SYSLOG) +/* The low-level SYSLOG functions can be used only if we have access to + * either the low-level serial interface, up_putc(), and to syslog_putc() + */ + +#if defined(CONFIG_BUILD_FLAT) || defined (__KERNEL__) +/* The low-level serial interface, up_putc(), and syslog_putc() are only + * available in the FLAT build or during the kernel pass of the protected or + * kernel two pass builds. + */ /**************************************************************************** * Private Functions @@ -136,4 +145,5 @@ int lowsyslog(int priority, FAR const IPTR char *fmt, ...) return ret; } +#endif /* CONFIG_BUILD_FLAT) || __KERNEL__ */ #endif /* CONFIG_ARCH_LOWPUTC || CONFIG_SYSLOG */ diff --git a/libc/syslog/lib_syslog.c b/libc/syslog/lib_syslog.c index f6e35b35b5..32087d86f7 100644 --- a/libc/syslog/lib_syslog.c +++ b/libc/syslog/lib_syslog.c @@ -43,6 +43,7 @@ #include #include +#include #include #include @@ -162,13 +163,41 @@ int vsyslog(int priority, FAR const IPTR char *fmt, va_list ap) { int ret = 0; - /* Check if this priority is enabled */ +#if !defined(CONFIG_SYSLOG) && CONFIG_NFILE_DESCRIPTORS > 0 + /* Are we are generating output on stdout? If so, was this function + * called from an interrupt handler? We cannot send data to stdout from + * an interrupt handler. + */ - if ((g_syslog_mask & LOG_MASK(priority)) != 0) + if (up_interrupt_context()) { - /* Yes.. let vsylog_internal do the deed */ +#ifdef CONFIG_ARCH_LOWPUTC + /* But the low-level serial interface up_putc() is provided so we may + * be able to generate low-level serial output instead. + * NOTE: The low-level serial output is not necessarily the same + * output destination as stdout! + */ - ret = vsyslog_internal(fmt, ap); +#if defined(CONFIG_BUILD_FLAT) || defined (__KERNEL__) + /* lowvsyslog() in only available in the FLAT build or during the + * kernel pass of the protected or kernel two pass builds. + */ + + ret = lowvsyslog(priority, fmt, ap); +#endif +#endif + } + else +#endif + { + /* Check if this priority is enabled */ + + if ((g_syslog_mask & LOG_MASK(priority)) != 0) + { + /* Yes.. let vsylog_internal do the deed */ + + ret = vsyslog_internal(fmt, ap); + } } return ret; From 28192d3c6007bb406ddbdb35a2fb1a0ffcacbd10 Mon Sep 17 00:00:00 2001 From: Gregory Nutt Date: Thu, 16 Jun 2016 20:10:19 -0600 Subject: [PATCH 29/75] Re-order some conditional compilation; up_interrupt_context() is not generally available to applications. --- libc/syslog/lib_syslog.c | 22 ++++++++++++---------- 1 file changed, 12 insertions(+), 10 deletions(-) diff --git a/libc/syslog/lib_syslog.c b/libc/syslog/lib_syslog.c index 32087d86f7..8b8ad24882 100644 --- a/libc/syslog/lib_syslog.c +++ b/libc/syslog/lib_syslog.c @@ -163,9 +163,15 @@ int vsyslog(int priority, FAR const IPTR char *fmt, va_list ap) { int ret = 0; +#if defined(CONFIG_BUILD_FLAT) || defined (__KERNEL__) + /* up_interrupt_context() and lowvsyslog() are only available in the FLAT + * build or during the kernel pass of the protected or kernel two pass + * builds. + */ + #if !defined(CONFIG_SYSLOG) && CONFIG_NFILE_DESCRIPTORS > 0 - /* Are we are generating output on stdout? If so, was this function - * called from an interrupt handler? We cannot send data to stdout from + /* We are generating output on stdout. So check if this function was + * called from an interrupt handler. We cannot send data to stdout from * an interrupt handler. */ @@ -178,17 +184,13 @@ int vsyslog(int priority, FAR const IPTR char *fmt, va_list ap) * output destination as stdout! */ -#if defined(CONFIG_BUILD_FLAT) || defined (__KERNEL__) - /* lowvsyslog() in only available in the FLAT build or during the - * kernel pass of the protected or kernel two pass builds. - */ - ret = lowvsyslog(priority, fmt, ap); -#endif -#endif + +#endif /* CONFIG_ARCH_LOWPUTC */ } else -#endif +#endif /* !CONFIG_SYSLOG && CONFIG_NFILE_DESCRIPTORS > 0 */ +#endif /* CONFIG_BUILD_FLAT || __KERNEL */ { /* Check if this priority is enabled */ From d3b8c03a8a24d7db5d3fab42fc81a6ac0099f682 Mon Sep 17 00:00:00 2001 From: Gregory Nutt Date: Fri, 17 Jun 2016 06:00:45 -0600 Subject: [PATCH 30/75] Fix a few missed changes from *dbg() to *err() and *vdbg() to *info() --- arch/arm/src/samv7/sam_spi.c | 12 +++--- arch/arm/src/stm32f7/stm32_adc.c | 62 ++++++++++++++-------------- configs/stm32f746-ws/src/stm32_spi.c | 12 +++--- libc/syslog/lib_syslog.c | 4 ++ 4 files changed, 47 insertions(+), 43 deletions(-) diff --git a/arch/arm/src/samv7/sam_spi.c b/arch/arm/src/samv7/sam_spi.c index 34caed374c..22661ec101 100644 --- a/arch/arm/src/samv7/sam_spi.c +++ b/arch/arm/src/samv7/sam_spi.c @@ -436,7 +436,7 @@ static bool spi_checkreg(struct sam_spidev_s *spi, bool wr, uint32_t value, { /* Yes... show how many times we did it */ - spiinfo("...[Repeats %d times]...\n", spi->ntimes); + spillinfo("...[Repeats %d times]...\n", spi->ntimes); } /* Save information about the new access */ @@ -470,7 +470,7 @@ static inline uint32_t spi_getreg(struct sam_spidev_s *spi, #ifdef CONFIG_SAMV7_SPI_REGDEBUG if (spi_checkreg(spi, false, value, address)) { - spiinfo("%08x->%08x\n", address, value); + spillinfo("%08x->%08x\n", address, value); } #endif @@ -493,7 +493,7 @@ static inline void spi_putreg(struct sam_spidev_s *spi, uint32_t value, #ifdef CONFIG_SAMV7_SPI_REGDEBUG if (spi_checkreg(spi, true, value, address)) { - spiinfo("%08x<-%08x\n", address, value); + spillinfo("%08x<-%08x\n", address, value); } #endif @@ -1130,9 +1130,9 @@ static int spi_setdelay(struct spi_dev_s *dev, uint32_t startdelay, uint32_t regval; unsigned int offset; - spivdbg("cs=%d startdelay=%d\n", spics->cs, startdelay); - spivdbg("cs=%d stopdelay=%d\n", spics->cs, stopdelay); - spivdbg("cs=%d csdelay=%d\n", spics->cs, csdelay); + spiinfo("cs=%d startdelay=%d\n", spics->cs, startdelay); + spiinfo("cs=%d stopdelay=%d\n", spics->cs, stopdelay); + spiinfo("cs=%d csdelay=%d\n", spics->cs, csdelay); offset = (unsigned int)g_csroffset[spics->cs]; diff --git a/arch/arm/src/stm32f7/stm32_adc.c b/arch/arm/src/stm32f7/stm32_adc.c index 89c4f03b1f..fa357867c8 100644 --- a/arch/arm/src/stm32f7/stm32_adc.c +++ b/arch/arm/src/stm32f7/stm32_adc.c @@ -536,29 +536,29 @@ static void tim_modifyreg(FAR struct stm32_dev_s *priv, int offset, #ifdef ADC_HAVE_TIMER static void tim_dumpregs(FAR struct stm32_dev_s *priv, FAR const char *msg) { - avdbg("%s:\n", msg); - avdbg(" CR1: %04x CR2: %04x SMCR: %04x DIER: %04x\n", + ainfo("%s:\n", msg); + ainfo(" CR1: %04x CR2: %04x SMCR: %04x DIER: %04x\n", tim_getreg(priv, STM32_GTIM_CR1_OFFSET), tim_getreg(priv, STM32_GTIM_CR2_OFFSET), tim_getreg(priv, STM32_GTIM_SMCR_OFFSET), tim_getreg(priv, STM32_GTIM_DIER_OFFSET)); - avdbg(" SR: %04x EGR: 0000 CCMR1: %04x CCMR2: %04x\n", + ainfo(" SR: %04x EGR: 0000 CCMR1: %04x CCMR2: %04x\n", tim_getreg(priv, STM32_GTIM_SR_OFFSET), tim_getreg(priv, STM32_GTIM_CCMR1_OFFSET), tim_getreg(priv, STM32_GTIM_CCMR2_OFFSET)); - avdbg(" CCER: %04x CNT: %04x PSC: %04x ARR: %04x\n", + ainfo(" CCER: %04x CNT: %04x PSC: %04x ARR: %04x\n", tim_getreg(priv, STM32_GTIM_CCER_OFFSET), tim_getreg(priv, STM32_GTIM_CNT_OFFSET), tim_getreg(priv, STM32_GTIM_PSC_OFFSET), tim_getreg(priv, STM32_GTIM_ARR_OFFSET)); - avdbg(" CCR1: %04x CCR2: %04x CCR3: %04x CCR4: %04x\n", + ainfo(" CCR1: %04x CCR2: %04x CCR3: %04x CCR4: %04x\n", tim_getreg(priv, STM32_GTIM_CCR1_OFFSET), tim_getreg(priv, STM32_GTIM_CCR2_OFFSET), tim_getreg(priv, STM32_GTIM_CCR3_OFFSET), tim_getreg(priv, STM32_GTIM_CCR4_OFFSET)); if (priv->tbase == STM32_TIM1_BASE || priv->tbase == STM32_TIM8_BASE) { - avdbg(" RCR: %04x BDTR: %04x DCR: %04x DMAR: %04x\n", + ainfo(" RCR: %04x BDTR: %04x DCR: %04x DMAR: %04x\n", tim_getreg(priv, STM32_ATIM_RCR_OFFSET), tim_getreg(priv, STM32_ATIM_BDTR_OFFSET), tim_getreg(priv, STM32_ATIM_DCR_OFFSET), @@ -566,7 +566,7 @@ static void tim_dumpregs(FAR struct stm32_dev_s *priv, FAR const char *msg) } else { - avdbg(" DCR: %04x DMAR: %04x\n", + ainfo(" DCR: %04x DMAR: %04x\n", tim_getreg(priv, STM32_GTIM_DCR_OFFSET), tim_getreg(priv, STM32_GTIM_DMAR_OFFSET)); } @@ -590,7 +590,7 @@ static void tim_dumpregs(FAR struct stm32_dev_s *priv, FAR const char *msg) #ifdef ADC_HAVE_TIMER static void adc_timstart(FAR struct stm32_dev_s *priv, bool enable) { - avdbg("enable: %d\n", enable ? 1 : 0); + ainfo("enable: %d\n", enable ? 1 : 0); if (enable) { @@ -659,7 +659,7 @@ static int adc_timinit(FAR struct stm32_dev_s *priv) * position. */ - avdbg("Initializing timers extsel = 0x%08x\n", priv->extsel); + ainfo("Initializing timers extsel = 0x%08x\n", priv->extsel); adc_modifyreg(priv, STM32_ADC_EXTREG_OFFSET, ADC_EXTREG_EXTEN_MASK | ADC_EXTREG_EXTSEL_MASK, @@ -692,7 +692,7 @@ static int adc_timinit(FAR struct stm32_dev_s *priv) if (prescaler < 1) { - adbg("WARNING: Prescaler underflowed.\n"); + awarn("WARNING: Prescaler underflowed.\n"); prescaler = 1; } @@ -700,7 +700,7 @@ static int adc_timinit(FAR struct stm32_dev_s *priv) else if (prescaler > 65536) { - adbg("WARNING: Prescaler overflowed.\n"); + awarn("WARNING: Prescaler overflowed.\n"); prescaler = 65536; } @@ -709,12 +709,12 @@ static int adc_timinit(FAR struct stm32_dev_s *priv) reload = timclk / priv->freq; if (reload < 1) { - adbg("WARNING: Reload value underflowed.\n"); + awarn("WARNING: Reload value underflowed.\n"); reload = 1; } else if (reload > 65535) { - adbg("WARNING: Reload value overflowed.\n"); + awarn("WARNING: Reload value overflowed.\n"); reload = 65535; } @@ -854,7 +854,7 @@ static int adc_timinit(FAR struct stm32_dev_s *priv) break; default: - adbg("No such trigger: %d\n", priv->trigger); + aerr("ERROR: No such trigger: %d\n", priv->trigger); return -EINVAL; } @@ -955,7 +955,7 @@ static int adc_timinit(FAR struct stm32_dev_s *priv) static void adc_startconv(FAR struct stm32_dev_s *priv, bool enable) { - avdbg("enable: %d\n", enable ? 1 : 0); + ainfo("enable: %d\n", enable ? 1 : 0); if (enable) { @@ -1060,7 +1060,7 @@ static void adc_enable(FAR struct stm32_dev_s *priv, bool enable) bool enabled = false; #endif - avdbg("enable: %d\n", enable ? 1 : 0); + ainfo("enable: %d\n", enable ? 1 : 0); if (!enabled && enable) { @@ -1263,7 +1263,7 @@ static void adc_reset(FAR struct adc_dev_s *dev) ret = adc_timinit(priv); if (ret < 0) { - adbg("adc_timinit failed: %d\n", ret); + aerr("ERROR: adc_timinit failed: %d\n", ret); } } #ifndef CONFIG_ADC_NO_STARTUP_CONV @@ -1278,17 +1278,17 @@ static void adc_reset(FAR struct adc_dev_s *dev) leave_critical_section(flags); - avdbg("SR: 0x%08x CR1: 0x%08x CR2: 0x%08x\n", + ainfo("SR: 0x%08x CR1: 0x%08x CR2: 0x%08x\n", adc_getreg(priv, STM32_ADC_SR_OFFSET), adc_getreg(priv, STM32_ADC_CR1_OFFSET), adc_getreg(priv, STM32_ADC_CR2_OFFSET)); - avdbg("SQR1: 0x%08x SQR2: 0x%08x SQR3: 0x%08x\n", + ainfo("SQR1: 0x%08x SQR2: 0x%08x SQR3: 0x%08x\n", adc_getreg(priv, STM32_ADC_SQR1_OFFSET), adc_getreg(priv, STM32_ADC_SQR2_OFFSET), adc_getreg(priv, STM32_ADC_SQR3_OFFSET)); - avdbg("CCR: 0x%08x\n", getreg32(STM32_ADC_CCR)); + ainfo("CCR: 0x%08x\n", getreg32(STM32_ADC_CCR)); } @@ -1317,7 +1317,7 @@ static int adc_setup(FAR struct adc_dev_s *dev) ret = irq_attach(priv->irq, priv->isr); if (ret < 0) { - avdbg("irq_attach failed: %d\n", ret); + ainfo("irq_attach failed: %d\n", ret); return ret; } @@ -1327,7 +1327,7 @@ static int adc_setup(FAR struct adc_dev_s *dev) /* Enable the ADC interrupt */ - avdbg("Enable the ADC interrupt: irq=%d\n", priv->irq); + ainfo("Enable the ADC interrupt: irq=%d\n", priv->irq); up_enable_irq(priv->irq); return ret; @@ -1378,7 +1378,7 @@ static void adc_rxint(FAR struct adc_dev_s *dev, bool enable) { FAR struct stm32_dev_s *priv = (FAR struct stm32_dev_s *)dev->ad_priv; - avdbg("intf: %d enable: %d\n", priv->intf, enable ? 1 : 0); + ainfo("intf: %d enable: %d\n", priv->intf, enable ? 1 : 0); if (enable) { @@ -1503,7 +1503,7 @@ static int adc_ioctl(FAR struct adc_dev_s *dev, int cmd, unsigned long arg) break; default: - adbg("ERROR: Unknown cmd: %d\n", cmd); + aerr("ERROR: Unknown cmd: %d\n", cmd); ret = -ENOTTY; break; } @@ -1541,12 +1541,12 @@ static int adc_interrupt(FAR struct adc_dev_s *dev) if ((regval & ADC_ISR_AWD) != 0) { - alldbg("WARNING: Analog Watchdog, Value converted out of range!\n"); + allwarn("WARNING: Analog Watchdog, Value converted out of range!\n"); } if ((regval & ADC_ISR_OVR) != 0) { - alldbg("WARNING: Overrun has occurred!\n"); + allwarn("WARNING: Overrun has occurred!\n"); } /* EOC: End of conversion */ @@ -1653,30 +1653,30 @@ struct adc_dev_s *stm32_adc_initialize(int intf, FAR const uint8_t *chanlist, FAR struct adc_dev_s *dev; FAR struct stm32_dev_s *priv; - avdbg("intf: %d cchannels: %d\n", intf, cchannels); + ainfo("intf: %d cchannels: %d\n", intf, cchannels); switch (intf) { #ifdef CONFIG_STM32F7_ADC1 case 1: - avdbg("ADC1 selected\n"); + ainfo("ADC1 selected\n"); dev = &g_adcdev1; break; #endif #ifdef CONFIG_STM32F7_ADC2 case 2: - avdbg("ADC2 selected\n"); + ainfo("ADC2 selected\n"); dev = &g_adcdev2; break; #endif #ifdef CONFIG_STM32F7_ADC3 case 3: - avdbg("ADC3 selected\n"); + ainfo("ADC3 selected\n"); dev = &g_adcdev3; break; #endif default: - adbg("No ADC interface defined\n"); + aerr("ERROR: No ADC interface defined\n"); return NULL; } diff --git a/configs/stm32f746-ws/src/stm32_spi.c b/configs/stm32f746-ws/src/stm32_spi.c index e973ca9b82..517ea3761b 100644 --- a/configs/stm32f746-ws/src/stm32_spi.c +++ b/configs/stm32f746-ws/src/stm32_spi.c @@ -101,7 +101,7 @@ void weak_function stm32_spidev_initialize(void) #ifdef CONFIG_STM32F7_SPI1 void stm32_spi1select(FAR struct spi_dev_s *dev, enum spi_dev_e devid, bool selected) { - spidbg("devid: %d CS: %s\n", (int)devid, selected ? "assert" : "de-assert"); + spiinfo("devid: %d CS: %s\n", (int)devid, selected ? "assert" : "de-assert"); } uint8_t stm32_spi1status(FAR struct spi_dev_s *dev, enum spi_dev_e devid) @@ -113,7 +113,7 @@ uint8_t stm32_spi1status(FAR struct spi_dev_s *dev, enum spi_dev_e devid) #ifdef CONFIG_STM32F7_SPI2 void stm32_spi2select(FAR struct spi_dev_s *dev, enum spi_dev_e devid, bool selected) { - spidbg("devid: %d CS: %s\n", (int)devid, selected ? "assert" : "de-assert"); + spiinfo("devid: %d CS: %s\n", (int)devid, selected ? "assert" : "de-assert"); } uint8_t stm32_spi2status(FAR struct spi_dev_s *dev, enum spi_dev_e devid) @@ -125,7 +125,7 @@ uint8_t stm32_spi2status(FAR struct spi_dev_s *dev, enum spi_dev_e devid) #ifdef CONFIG_STM32F7_SPI3 void stm32_spi3select(FAR struct spi_dev_s *dev, enum spi_dev_e devid, bool selected) { - spidbg("devid: %d CS: %s\n", (int)devid, selected ? "assert" : "de-assert"); + spiinfo("devid: %d CS: %s\n", (int)devid, selected ? "assert" : "de-assert"); } uint8_t stm32_spi3status(FAR struct spi_dev_s *dev, enum spi_dev_e devid) @@ -137,7 +137,7 @@ uint8_t stm32_spi3status(FAR struct spi_dev_s *dev, enum spi_dev_e devid) #ifdef CONFIG_STM32F7_SPI4 void stm32_spi4select(FAR struct spi_dev_s *dev, enum spi_dev_e devid, bool selected) { - spidbg("devid: %d CS: %s\n", (int)devid, selected ? "assert" : "de-assert"); + spiinfo("devid: %d CS: %s\n", (int)devid, selected ? "assert" : "de-assert"); } uint8_t stm32_spi4status(FAR struct spi_dev_s *dev, enum spi_dev_e devid) @@ -149,7 +149,7 @@ uint8_t stm32_spi4status(FAR struct spi_dev_s *dev, enum spi_dev_e devid) #ifdef CONFIG_STM32F7_SPI5 void stm32_spi5select(FAR struct spi_dev_s *dev, enum spi_dev_e devid, bool selected) { - spidbg("devid: %d CS: %s\n", (int)devid, selected ? "assert" : "de-assert"); + spiinfo("devid: %d CS: %s\n", (int)devid, selected ? "assert" : "de-assert"); } uint8_t stm32_spi5status(FAR struct spi_dev_s *dev, enum spi_dev_e devid) @@ -161,7 +161,7 @@ uint8_t stm32_spi5status(FAR struct spi_dev_s *dev, enum spi_dev_e devid) #ifdef CONFIG_STM32F7_SPI6 void stm32_spi6select(FAR struct spi_dev_s *dev, enum spi_dev_e devid, bool selected) { - spidbg("devid: %d CS: %s\n", (int)devid, selected ? "assert" : "de-assert"); + spiinfo("devid: %d CS: %s\n", (int)devid, selected ? "assert" : "de-assert"); } uint8_t stm32_spi6status(FAR struct spi_dev_s *dev, enum spi_dev_e devid) diff --git a/libc/syslog/lib_syslog.c b/libc/syslog/lib_syslog.c index 8b8ad24882..66f8b236f7 100644 --- a/libc/syslog/lib_syslog.c +++ b/libc/syslog/lib_syslog.c @@ -92,6 +92,8 @@ static inline int vsyslog_internal(FAR const IPTR char *fmt, va_list ap) #if defined(CONFIG_SYSLOG) /* Wrap the low-level output in a stream object and let lib_vsprintf * do the work. + * REVISIT: lib_syslogstream() is only available in the FLAT build or + * the kernel phase of other builds. */ lib_syslogstream((FAR struct lib_outstream_s *)&stream); @@ -125,6 +127,8 @@ static inline int vsyslog_internal(FAR const IPTR char *fmt, va_list ap) #elif defined(CONFIG_ARCH_LOWPUTC) /* Wrap the low-level output in a stream object and let lib_vsprintf * do the work. + * REVISIT: lib_lowoutstream() is only available in the FLAT build or + * the kernel phase of other builds. */ lib_lowoutstream((FAR struct lib_outstream_s *)&stream); From 794a64a99ba768bf674b3f95e90cced9ed157624 Mon Sep 17 00:00:00 2001 From: Pascal Speck Date: Fri, 17 Jun 2016 06:23:18 -0600 Subject: [PATCH 31/75] hen configuring a GPIO via stm32_configgpio() the function will first set the mode to output and then set the initial state of the gpio later on. If you have an application with an externaly pulled-up pin, this would lead to a glitch on the line that may be dangerous in some applications (e.G. Reset Line for other chips, etc). This changes sets the output state before configuring the pin as an output. --- arch/arm/src/samv7/sam_tc.c | 14 +++++++------- arch/arm/src/stm32/stm32_gpio.c | 11 ++--------- 2 files changed, 9 insertions(+), 16 deletions(-) diff --git a/arch/arm/src/samv7/sam_tc.c b/arch/arm/src/samv7/sam_tc.c index 98c5347a8c..b8fd7abe41 100644 --- a/arch/arm/src/samv7/sam_tc.c +++ b/arch/arm/src/samv7/sam_tc.c @@ -702,7 +702,7 @@ static bool sam_checkreg(struct sam_tc_s *tc, bool wr, uint32_t regaddr, { /* Yes... show how many times we did it */ - tmrinfo("...[Repeats %d times]...\n", tc->ntimes); + tmrllinfo("...[Repeats %d times]...\n", tc->ntimes); } /* Save information about the new access */ @@ -737,7 +737,7 @@ static inline uint32_t sam_tc_getreg(struct sam_chan_s *chan, #ifdef CONFIG_SAMV7_TC_REGDEBUG if (sam_checkreg(tc, false, regaddr, regval)) { - tmrinfo("%08x->%08x\n", regaddr, regval); + tmrllinfo("%08x->%08x\n", regaddr, regval); } #endif @@ -761,7 +761,7 @@ static inline void sam_tc_putreg(struct sam_chan_s *chan, uint32_t regval, #ifdef CONFIG_SAMV7_TC_REGDEBUG if (sam_checkreg(tc, true, regaddr, regval)) { - tmrinfo("%08x<-%08x\n", regaddr, regval); + tmrllinfo("%08x<-%08x\n", regaddr, regval); } #endif @@ -785,7 +785,7 @@ static inline uint32_t sam_chan_getreg(struct sam_chan_s *chan, #ifdef CONFIG_SAMV7_TC_REGDEBUG if (sam_checkreg(chan->tc, false, regaddr, regval)) { - tmrinfo("%08x->%08x\n", regaddr, regval); + tmrllinfo("%08x->%08x\n", regaddr, regval); } #endif @@ -808,7 +808,7 @@ static inline void sam_chan_putreg(struct sam_chan_s *chan, unsigned int offset, #ifdef CONFIG_SAMV7_TC_REGDEBUG if (sam_checkreg(chan->tc, true, regaddr, regval)) { - tmrinfo("%08x<-%08x\n", regaddr, regval); + tmrllinfo("%08x<-%08x\n", regaddr, regval); } #endif @@ -845,8 +845,8 @@ static int sam_tc_interrupt(struct sam_tc_s *tc, struct sam_chan_s *chan) imr = sam_chan_getreg(chan, SAM_TC_IMR_OFFSET); pending = sr & imr; - tcllinfo("TC%d Channel %d: pending=%08lx\n", - tc->tc, chan->chan, (unsigned long)pending); + tmrllinfo("TC%d Channel %d: pending=%08lx\n", + tc->tc, chan->chan, (unsigned long)pending); /* Are there any pending interrupts for this channel? */ diff --git a/arch/arm/src/stm32/stm32_gpio.c b/arch/arm/src/stm32/stm32_gpio.c index 6426107b3b..63d09e982e 100644 --- a/arch/arm/src/stm32/stm32_gpio.c +++ b/arch/arm/src/stm32/stm32_gpio.c @@ -469,6 +469,7 @@ int stm32_configgpio(uint32_t cfgset) break; case GPIO_OUTPUT: /* General purpose output mode */ + stm32_gpiowrite(cfgset, (cfgset & GPIO_OUTPUT_SET) != 0); /* Set the initial output value */ pinmode = GPIO_MODER_OUTPUT; break; @@ -619,17 +620,9 @@ int stm32_configgpio(uint32_t cfgset) putreg32(regval, base + STM32_GPIO_OTYPER_OFFSET); - /* If it is an output... set the pin to the correct initial state. */ - - if (pinmode == GPIO_MODER_OUTPUT) - { - bool value = ((cfgset & GPIO_OUTPUT_SET) != 0); - stm32_gpiowrite(cfgset, value); - } - /* Otherwise, it is an input pin. Should it configured as an EXTI interrupt? */ - else if ((cfgset & GPIO_EXTI) != 0) + if (pinmode != GPIO_MODER_OUTPUT && (cfgset & GPIO_EXTI) != 0) { /* "In STM32 F1 the selection of the EXTI line source is performed through * the EXTIx bits in the AFIO_EXTICRx registers, while in F2 series this From 9b55cc6bfe7af2a358a187529b0a186c28fbd47f Mon Sep 17 00:00:00 2001 From: Gregory Nutt Date: Fri, 17 Jun 2016 06:40:04 -0600 Subject: [PATCH 32/75] Apply same STM32 patch to STM32 F7 --- arch/arm/src/stm32f7/stm32_gpio.c | 11 ++--------- 1 file changed, 2 insertions(+), 9 deletions(-) diff --git a/arch/arm/src/stm32f7/stm32_gpio.c b/arch/arm/src/stm32f7/stm32_gpio.c index 0cd386725f..17e8b4c108 100644 --- a/arch/arm/src/stm32f7/stm32_gpio.c +++ b/arch/arm/src/stm32f7/stm32_gpio.c @@ -182,6 +182,7 @@ int stm32_configgpio(uint32_t cfgset) break; case GPIO_OUTPUT: /* General purpose output mode */ + stm32_gpiowrite(cfgset, (cfgset & GPIO_OUTPUT_SET) != 0); /* Set the initial output value */ pinmode = GPIO_MODER_OUTPUT; break; @@ -311,17 +312,9 @@ int stm32_configgpio(uint32_t cfgset) putreg32(regval, base + STM32_GPIO_OTYPER_OFFSET); - /* If it is an output... set the pin to the correct initial state. */ - - if (pinmode == GPIO_MODER_OUTPUT) - { - bool value = ((cfgset & GPIO_OUTPUT_SET) != 0); - stm32_gpiowrite(cfgset, value); - } - /* Otherwise, it is an input pin. Should it configured as an EXTI interrupt? */ - else if ((cfgset & GPIO_EXTI) != 0) + if (pinmode != GPIO_MODER_OUTPUT && (cfgset & GPIO_EXTI) != 0) { /* "In STM32 F1 the selection of the EXTI line source is performed through * the EXTIx bits in the AFIO_EXTICRx registers, while in F2 series this From 0d3ecb3ddd0fa08dfc7fc23f7d29e4c826d38c0a Mon Sep 17 00:00:00 2001 From: Gregory Nutt Date: Fri, 17 Jun 2016 07:00:33 -0600 Subject: [PATCH 33/75] Fix another victim of the mass name changes: xyz_errmonitor->xyz_dbgmonitor --- arch/arm/src/efm32/efm32_irq.c | 6 +++--- arch/arm/src/kinetis/kinetis_irq.c | 6 +++--- arch/arm/src/kl/kl_irq.c | 2 +- arch/arm/src/lpc11xx/lpc11_irq.c | 2 +- arch/arm/src/lpc17xx/lpc17_irq.c | 6 +++--- arch/arm/src/lpc43xx/lpc43_irq.c | 6 +++--- arch/arm/src/nuc1xx/nuc_irq.c | 2 +- arch/arm/src/sam34/sam_irq.c | 6 +++--- arch/arm/src/samdl/sam_irq.c | 2 +- arch/arm/src/samv7/sam_irq.c | 6 +++--- arch/arm/src/stm32/stm32_irq.c | 6 +++--- arch/arm/src/stm32f7/stm32_irq.c | 6 +++--- arch/arm/src/stm32l4/stm32l4_irq.c | 6 +++--- arch/arm/src/tiva/tiva_irq.c | 6 +++--- 14 files changed, 34 insertions(+), 34 deletions(-) diff --git a/arch/arm/src/efm32/efm32_irq.c b/arch/arm/src/efm32/efm32_irq.c index 05d28c74a4..63fa4b18ec 100644 --- a/arch/arm/src/efm32/efm32_irq.c +++ b/arch/arm/src/efm32/efm32_irq.c @@ -157,7 +157,7 @@ static void efm32_dumpnvic(const char *msg, int irq) /**************************************************************************** * Name: efm32_nmi, efm32_busfault, efm32_usagefault, efm32_pendsv, - * efm32_errmonitor, efm32_pendsv, efm32_reserved + * efm32_dbgmonitor, efm32_pendsv, efm32_reserved * * Description: * Handlers for various exceptions. None are handled and all are fatal @@ -199,7 +199,7 @@ static int efm32_pendsv(int irq, FAR void *context) return 0; } -static int efm32_errmonitor(int irq, FAR void *context) +static int efm32_dbgmonitor(int irq, FAR void *context) { (void)up_irq_save(); _err("PANIC!!! Debug Monitor received\n"); @@ -458,7 +458,7 @@ void up_irqinitialize(void) irq_attach(EFM32_IRQ_BUSFAULT, efm32_busfault); irq_attach(EFM32_IRQ_USAGEFAULT, efm32_usagefault); irq_attach(EFM32_IRQ_PENDSV, efm32_pendsv); - irq_attach(EFM32_IRQ_DBGMONITOR, efm32_errmonitor); + irq_attach(EFM32_IRQ_DBGMONITOR, efm32_dbgmonitor); irq_attach(EFM32_IRQ_RESERVED, efm32_reserved); #endif diff --git a/arch/arm/src/kinetis/kinetis_irq.c b/arch/arm/src/kinetis/kinetis_irq.c index 2ce3d373a9..d2a04de3ae 100644 --- a/arch/arm/src/kinetis/kinetis_irq.c +++ b/arch/arm/src/kinetis/kinetis_irq.c @@ -160,7 +160,7 @@ static void kinetis_dumpnvic(const char *msg, int irq) /**************************************************************************** * Name: kinetis_nmi, kinetis_busfault, kinetis_usagefault, kinetis_pendsv, - * kinetis_errmonitor, kinetis_pendsv, kinetis_reserved + * kinetis_dbgmonitor, kinetis_pendsv, kinetis_reserved * * Description: * Handlers for various execptions. None are handled and all are fatal @@ -202,7 +202,7 @@ static int kinetis_pendsv(int irq, FAR void *context) return 0; } -static int kinetis_errmonitor(int irq, FAR void *context) +static int kinetis_dbgmonitor(int irq, FAR void *context) { (void)up_irq_save(); _err("PANIC!!! Debug Monitor received\n"); @@ -429,7 +429,7 @@ void up_irqinitialize(void) irq_attach(KINETIS_IRQ_BUSFAULT, kinetis_busfault); irq_attach(KINETIS_IRQ_USAGEFAULT, kinetis_usagefault); irq_attach(KINETIS_IRQ_PENDSV, kinetis_pendsv); - irq_attach(KINETIS_IRQ_DBGMONITOR, kinetis_errmonitor); + irq_attach(KINETIS_IRQ_DBGMONITOR, kinetis_dbgmonitor); irq_attach(KINETIS_IRQ_RESERVED, kinetis_reserved); #endif diff --git a/arch/arm/src/kl/kl_irq.c b/arch/arm/src/kl/kl_irq.c index c76a07ed25..b37f7afe1c 100644 --- a/arch/arm/src/kl/kl_irq.c +++ b/arch/arm/src/kl/kl_irq.c @@ -128,7 +128,7 @@ static void kl_dumpnvic(const char *msg, int irq) /**************************************************************************** * Name: kl_nmi, kl_busfault, kl_usagefault, kl_pendsv, - * kl_errmonitor, kl_pendsv, kl_reserved + * kl_dbgmonitor, kl_pendsv, kl_reserved * * Description: * Handlers for various execptions. None are handled and all are fatal diff --git a/arch/arm/src/lpc11xx/lpc11_irq.c b/arch/arm/src/lpc11xx/lpc11_irq.c index d907b7d4ae..f861943bc0 100644 --- a/arch/arm/src/lpc11xx/lpc11_irq.c +++ b/arch/arm/src/lpc11xx/lpc11_irq.c @@ -124,7 +124,7 @@ static void lpc11_dumpnvic(const char *msg, int irq) /**************************************************************************** * Name: lpc11_nmi, lpc11_busfault, lpc11_usagefault, lpc11_pendsv, - * lpc11_errmonitor, lpc11_pendsv, lpc11_reserved + * lpc11_dbgmonitor, lpc11_pendsv, lpc11_reserved * * Description: * Handlers for various execptions. None are handled and all are fatal diff --git a/arch/arm/src/lpc17xx/lpc17_irq.c b/arch/arm/src/lpc17xx/lpc17_irq.c index a3ada9cbe8..44d149c734 100644 --- a/arch/arm/src/lpc17xx/lpc17_irq.c +++ b/arch/arm/src/lpc17xx/lpc17_irq.c @@ -139,7 +139,7 @@ static void lpc17_dumpnvic(const char *msg, int irq) /**************************************************************************** * Name: lpc17_nmi, lpc17_busfault, lpc17_usagefault, lpc17_pendsv, - * lpc17_errmonitor, lpc17_pendsv, lpc17_reserved + * lpc17_dbgmonitor, lpc17_pendsv, lpc17_reserved * * Description: * Handlers for various execptions. None are handled and all are fatal @@ -181,7 +181,7 @@ static int lpc17_pendsv(int irq, FAR void *context) return 0; } -static int lpc17_errmonitor(int irq, FAR void *context) +static int lpc17_dbgmonitor(int irq, FAR void *context) { (void)up_irq_save(); _err("PANIC!!! Debug Monitor received\n"); @@ -402,7 +402,7 @@ void up_irqinitialize(void) irq_attach(LPC17_IRQ_BUSFAULT, lpc17_busfault); irq_attach(LPC17_IRQ_USAGEFAULT, lpc17_usagefault); irq_attach(LPC17_IRQ_PENDSV, lpc17_pendsv); - irq_attach(LPC17_IRQ_DBGMONITOR, lpc17_errmonitor); + irq_attach(LPC17_IRQ_DBGMONITOR, lpc17_dbgmonitor); irq_attach(LPC17_IRQ_RESERVED, lpc17_reserved); #endif diff --git a/arch/arm/src/lpc43xx/lpc43_irq.c b/arch/arm/src/lpc43xx/lpc43_irq.c index ea87cec8fe..345f63b5c2 100644 --- a/arch/arm/src/lpc43xx/lpc43_irq.c +++ b/arch/arm/src/lpc43xx/lpc43_irq.c @@ -148,7 +148,7 @@ static void lpc43_dumpnvic(const char *msg, int irq) /**************************************************************************** * Name: lpc43_nmi, lpc43_busfault, lpc43_usagefault, lpc43_pendsv, - * lpc43_errmonitor, lpc43_pendsv, lpc43_reserved + * lpc43_dbgmonitor, lpc43_pendsv, lpc43_reserved * * Description: * Handlers for various exceptions. None are handled and all are fatal @@ -190,7 +190,7 @@ static int lpc43_pendsv(int irq, FAR void *context) return 0; } -static int lpc43_errmonitor(int irq, FAR void *context) +static int lpc43_dbgmonitor(int irq, FAR void *context) { (void)up_irq_save(); _err("PANIC!!! Debug Monitor received\n"); @@ -437,7 +437,7 @@ void up_irqinitialize(void) irq_attach(LPC43_IRQ_BUSFAULT, lpc43_busfault); irq_attach(LPC43_IRQ_USAGEFAULT, lpc43_usagefault); irq_attach(LPC43_IRQ_PENDSV, lpc43_pendsv); - irq_attach(LPC43_IRQ_DBGMONITOR, lpc43_errmonitor); + irq_attach(LPC43_IRQ_DBGMONITOR, lpc43_dbgmonitor); irq_attach(LPC43_IRQ_RESERVED, lpc43_reserved); #endif diff --git a/arch/arm/src/nuc1xx/nuc_irq.c b/arch/arm/src/nuc1xx/nuc_irq.c index ec045c3734..66f6d78044 100644 --- a/arch/arm/src/nuc1xx/nuc_irq.c +++ b/arch/arm/src/nuc1xx/nuc_irq.c @@ -128,7 +128,7 @@ static void nuc_dumpnvic(const char *msg, int irq) /**************************************************************************** * Name: nuc_nmi, nuc_busfault, nuc_usagefault, nuc_pendsv, - * nuc_errmonitor, nuc_pendsv, nuc_reserved + * nuc_dbgmonitor, nuc_pendsv, nuc_reserved * * Description: * Handlers for various execptions. None are handled and all are fatal diff --git a/arch/arm/src/sam34/sam_irq.c b/arch/arm/src/sam34/sam_irq.c index 7e002224fb..68f1777434 100644 --- a/arch/arm/src/sam34/sam_irq.c +++ b/arch/arm/src/sam34/sam_irq.c @@ -163,7 +163,7 @@ static void sam_dumpnvic(const char *msg, int irq) #endif /**************************************************************************** - * Name: sam_nmi, sam_busfault, sam_usagefault, sam_pendsv, sam_errmonitor, + * Name: sam_nmi, sam_busfault, sam_usagefault, sam_pendsv, sam_dbgmonitor, * sam_pendsv, sam_reserved * * Description: @@ -206,7 +206,7 @@ static int sam_pendsv(int irq, FAR void *context) return 0; } -static int sam_errmonitor(int irq, FAR void *context) +static int sam_dbgmonitor(int irq, FAR void *context) { (void)up_irq_save(); _err("PANIC!!! Debug Monitor received\n"); @@ -466,7 +466,7 @@ void up_irqinitialize(void) irq_attach(SAM_IRQ_BUSFAULT, sam_busfault); irq_attach(SAM_IRQ_USAGEFAULT, sam_usagefault); irq_attach(SAM_IRQ_PENDSV, sam_pendsv); - irq_attach(SAM_IRQ_DBGMONITOR, sam_errmonitor); + irq_attach(SAM_IRQ_DBGMONITOR, sam_dbgmonitor); irq_attach(SAM_IRQ_RESERVED, sam_reserved); #endif diff --git a/arch/arm/src/samdl/sam_irq.c b/arch/arm/src/samdl/sam_irq.c index ea20c689bf..025c200818 100644 --- a/arch/arm/src/samdl/sam_irq.c +++ b/arch/arm/src/samdl/sam_irq.c @@ -84,7 +84,7 @@ volatile uint32_t *g_current_regs[1]; /**************************************************************************** * Name: sam_nmi, sam_busfault, sam_usagefault, sam_pendsv, - * sam_errmonitor, sam_pendsv, sam_reserved + * sam_dbgmonitor, sam_pendsv, sam_reserved * * Description: * Handlers for various execptions. None are handled and all are fatal diff --git a/arch/arm/src/samv7/sam_irq.c b/arch/arm/src/samv7/sam_irq.c index faf021fa47..08537f6597 100644 --- a/arch/arm/src/samv7/sam_irq.c +++ b/arch/arm/src/samv7/sam_irq.c @@ -163,7 +163,7 @@ static void sam_dumpnvic(const char *msg, int irq) #endif /**************************************************************************** - * Name: sam_nmi, sam_busfault, sam_usagefault, sam_pendsv, sam_errmonitor, + * Name: sam_nmi, sam_busfault, sam_usagefault, sam_pendsv, sam_dbgmonitor, * sam_pendsv, sam_reserved * * Description: @@ -206,7 +206,7 @@ static int sam_pendsv(int irq, FAR void *context) return 0; } -static int sam_errmonitor(int irq, FAR void *context) +static int sam_dbgmonitor(int irq, FAR void *context) { (void)up_irq_save(); _err("PANIC!!! Debug Monitor received\n"); @@ -466,7 +466,7 @@ void up_irqinitialize(void) irq_attach(SAM_IRQ_BUSFAULT, sam_busfault); irq_attach(SAM_IRQ_USAGEFAULT, sam_usagefault); irq_attach(SAM_IRQ_PENDSV, sam_pendsv); - irq_attach(SAM_IRQ_DBGMONITOR, sam_errmonitor); + irq_attach(SAM_IRQ_DBGMONITOR, sam_dbgmonitor); irq_attach(SAM_IRQ_RESERVED, sam_reserved); #endif diff --git a/arch/arm/src/stm32/stm32_irq.c b/arch/arm/src/stm32/stm32_irq.c index 1e9570cc90..062d63fb74 100644 --- a/arch/arm/src/stm32/stm32_irq.c +++ b/arch/arm/src/stm32/stm32_irq.c @@ -151,7 +151,7 @@ static void stm32_dumpnvic(const char *msg, int irq) /**************************************************************************** * Name: stm32_nmi, stm32_busfault, stm32_usagefault, stm32_pendsv, - * stm32_errmonitor, stm32_pendsv, stm32_reserved + * stm32_dbgmonitor, stm32_pendsv, stm32_reserved * * Description: * Handlers for various execptions. None are handled and all are fatal @@ -193,7 +193,7 @@ static int stm32_pendsv(int irq, FAR void *context) return 0; } -static int stm32_errmonitor(int irq, FAR void *context) +static int stm32_dbgmonitor(int irq, FAR void *context) { (void)up_irq_save(); _err("PANIC!!! Debug Monitor received\n"); @@ -418,7 +418,7 @@ void up_irqinitialize(void) irq_attach(STM32_IRQ_BUSFAULT, stm32_busfault); irq_attach(STM32_IRQ_USAGEFAULT, stm32_usagefault); irq_attach(STM32_IRQ_PENDSV, stm32_pendsv); - irq_attach(STM32_IRQ_DBGMONITOR, stm32_errmonitor); + irq_attach(STM32_IRQ_DBGMONITOR, stm32_dbgmonitor); irq_attach(STM32_IRQ_RESERVED, stm32_reserved); #endif diff --git a/arch/arm/src/stm32f7/stm32_irq.c b/arch/arm/src/stm32f7/stm32_irq.c index 62c4aee7aa..eb7a8e1b86 100644 --- a/arch/arm/src/stm32f7/stm32_irq.c +++ b/arch/arm/src/stm32f7/stm32_irq.c @@ -175,7 +175,7 @@ static void stm32_dumpnvic(const char *msg, int irq) #endif /**************************************************************************** - * Name: stm32_nmi, stm32_busfault, stm32_usagefault, stm32_pendsv, stm32_errmonitor, + * Name: stm32_nmi, stm32_busfault, stm32_usagefault, stm32_pendsv, stm32_dbgmonitor, * stm32_pendsv, stm32_reserved * * Description: @@ -218,7 +218,7 @@ static int stm32_pendsv(int irq, FAR void *context) return 0; } -static int stm32_errmonitor(int irq, FAR void *context) +static int stm32_dbgmonitor(int irq, FAR void *context) { (void)up_irq_save(); _err("PANIC!!! Debug Monitor received\n"); @@ -500,7 +500,7 @@ void up_irqinitialize(void) irq_attach(STM32_IRQ_BUSFAULT, stm32_busfault); irq_attach(STM32_IRQ_USAGEFAULT, stm32_usagefault); irq_attach(STM32_IRQ_PENDSV, stm32_pendsv); - irq_attach(STM32_IRQ_DBGMONITOR, stm32_errmonitor); + irq_attach(STM32_IRQ_DBGMONITOR, stm32_dbgmonitor); irq_attach(STM32_IRQ_RESERVED, stm32_reserved); #endif diff --git a/arch/arm/src/stm32l4/stm32l4_irq.c b/arch/arm/src/stm32l4/stm32l4_irq.c index 7d5f948c81..4742d5c95b 100644 --- a/arch/arm/src/stm32l4/stm32l4_irq.c +++ b/arch/arm/src/stm32l4/stm32l4_irq.c @@ -150,7 +150,7 @@ static void stm32l4_dumpnvic(const char *msg, int irq) /**************************************************************************** * Name: stm32l4_nmi, stm32l4_busfault, stm32l4_usagefault, stm32l4_pendsv, - * stm32l4_errmonitor, stm32l4_pendsv, stm32l4_reserved + * stm32l4_dbgmonitor, stm32l4_pendsv, stm32l4_reserved * * Description: * Handlers for various execptions. None are handled and all are fatal @@ -192,7 +192,7 @@ static int stm32l4_pendsv(int irq, FAR void *context) return 0; } -static int stm32l4_errmonitor(int irq, FAR void *context) +static int stm32l4_dbgmonitor(int irq, FAR void *context) { (void)up_irq_save(); _err("PANIC!!! Debug Monitor received\n"); @@ -413,7 +413,7 @@ void up_irqinitialize(void) irq_attach(STM32L4_IRQ_BUSFAULT, stm32l4_busfault); irq_attach(STM32L4_IRQ_USAGEFAULT, stm32l4_usagefault); irq_attach(STM32L4_IRQ_PENDSV, stm32l4_pendsv); - irq_attach(STM32L4_IRQ_DBGMONITOR, stm32l4_errmonitor); + irq_attach(STM32L4_IRQ_DBGMONITOR, stm32l4_dbgmonitor); irq_attach(STM32L4_IRQ_RESERVED, stm32l4_reserved); #endif diff --git a/arch/arm/src/tiva/tiva_irq.c b/arch/arm/src/tiva/tiva_irq.c index 8f95e071d9..6771007d59 100644 --- a/arch/arm/src/tiva/tiva_irq.c +++ b/arch/arm/src/tiva/tiva_irq.c @@ -186,7 +186,7 @@ static void tiva_dumpnvic(const char *msg, int irq) /**************************************************************************** * Name: tiva_nmi, tiva_busfault, tiva_usagefault, tiva_pendsv, - * tiva_errmonitor, tiva_pendsv, tiva_reserved + * tiva_dbgmonitor, tiva_pendsv, tiva_reserved * * Description: * Handlers for various execptions. None are handled and all are fatal @@ -228,7 +228,7 @@ static int tiva_pendsv(int irq, FAR void *context) return 0; } -static int tiva_errmonitor(int irq, FAR void *context) +static int tiva_dbgmonitor(int irq, FAR void *context) { (void)up_irq_save(); _err("PANIC!!! Debug Monitor received\n"); @@ -482,7 +482,7 @@ void up_irqinitialize(void) irq_attach(TIVA_IRQ_BUSFAULT, tiva_busfault); irq_attach(TIVA_IRQ_USAGEFAULT, tiva_usagefault); irq_attach(TIVA_IRQ_PENDSV, tiva_pendsv); - irq_attach(TIVA_IRQ_DBGMONITOR, tiva_errmonitor); + irq_attach(TIVA_IRQ_DBGMONITOR, tiva_dbgmonitor); irq_attach(TIVA_IRQ_RESERVED, tiva_reserved); #endif From 219098c5ac543b7f2fb28f26b6f0352cac02a643 Mon Sep 17 00:00:00 2001 From: Gregory Nutt Date: Fri, 17 Jun 2016 07:13:38 -0600 Subject: [PATCH 34/75] Restore some debug output that lost its low-level marking --- arch/arm/src/samv7/sam_emac.c | 6 +++--- arch/arm/src/samv7/sam_hsmci.c | 6 +++--- arch/arm/src/samv7/sam_mcan.c | 10 +++++----- arch/arm/src/samv7/sam_qspi.c | 6 +++--- arch/arm/src/samv7/sam_rswdt.c | 6 +++--- 5 files changed, 17 insertions(+), 17 deletions(-) diff --git a/arch/arm/src/samv7/sam_emac.c b/arch/arm/src/samv7/sam_emac.c index ae1151a04f..8df2561bd9 100644 --- a/arch/arm/src/samv7/sam_emac.c +++ b/arch/arm/src/samv7/sam_emac.c @@ -966,7 +966,7 @@ static bool sam_checkreg(struct sam_emac_s *priv, bool wr, uint32_t regval, { /* Yes... show how many times we did it */ - ninfo("...[Repeats %d times]...\n", priv->ntimes); + nllinfo("...[Repeats %d times]...\n", priv->ntimes); } /* Save information about the new access */ @@ -999,7 +999,7 @@ static uint32_t sam_getreg(struct sam_emac_s *priv, uint16_t offset) #ifdef CONFIG_SAMV7_EMAC_REGDEBUG if (sam_checkreg(priv, false, regval, regaddr)) { - ninfo("%08x->%08x\n", regaddr, regval); + nllinfo("%08x->%08x\n", regaddr, regval); } #endif @@ -1023,7 +1023,7 @@ static void sam_putreg(struct sam_emac_s *priv, uint16_t offset, #ifdef CONFIG_SAMV7_EMAC_REGDEBUG if (sam_checkreg(priv, true, regval, regaddr)) { - ninfo("%08x<-%08x\n", regaddr, regval); + nllinfo("%08x<-%08x\n", regaddr, regval); } #endif diff --git a/arch/arm/src/samv7/sam_hsmci.c b/arch/arm/src/samv7/sam_hsmci.c index bddf8e7f9a..9e24ac9abe 100644 --- a/arch/arm/src/samv7/sam_hsmci.c +++ b/arch/arm/src/samv7/sam_hsmci.c @@ -657,7 +657,7 @@ static bool sam_checkreg(struct sam_dev_s *priv, bool wr, uint32_t value, { /* Yes... show how many times we did it */ - mcinfo("...[Repeats %d times]...\n", priv->ntimes); + mcllinfo("...[Repeats %d times]...\n", priv->ntimes); } /* Save information about the new access */ @@ -690,7 +690,7 @@ static inline uint32_t sam_getreg(struct sam_dev_s *priv, unsigned int offset) #ifdef CONFIG_SAMV7_HSMCI_REGDEBUG if (sam_checkreg(priv, false, value, address)) { - mcinfo("%08x->%08x\n", address, value); + mcllinfo("%08x->%08x\n", address, value); } #endif @@ -713,7 +713,7 @@ static inline void sam_putreg(struct sam_dev_s *priv, uint32_t value, #ifdef CONFIG_SAMV7_HSMCI_REGDEBUG if (sam_checkreg(priv, true, value, address)) { - mcinfo("%08x<-%08x\n", address, value); + mcllinfo("%08x<-%08x\n", address, value); } #endif diff --git a/arch/arm/src/samv7/sam_mcan.c b/arch/arm/src/samv7/sam_mcan.c index adade97363..2853ee5a3b 100644 --- a/arch/arm/src/samv7/sam_mcan.c +++ b/arch/arm/src/samv7/sam_mcan.c @@ -794,7 +794,7 @@ #endif #ifdef CONFIG_SAMV7_MCAN_REGDEBUG -# define reginfo caninfo +# define reginfo canllinfo #else # define reginfo(x...) #endif @@ -1195,7 +1195,7 @@ static uint32_t mcan_getreg(FAR struct sam_mcan_s *priv, int offset) { if (priv->count == 4) { - caninfo("...\n"); + canllinfo("...\n"); } return regval; @@ -1212,7 +1212,7 @@ static uint32_t mcan_getreg(FAR struct sam_mcan_s *priv, int offset) { /* Yes.. then show how many times the value repeated */ - caninfo("[repeats %d more times]\n", priv->count - 3); + canllinfo("[repeats %d more times]\n", priv->count - 3); } /* Save the new address, value, and count */ @@ -1224,7 +1224,7 @@ static uint32_t mcan_getreg(FAR struct sam_mcan_s *priv, int offset) /* Show the register value read */ - caninfo("%08x->%08x\n", regaddr, regval); + canllinfo("%08x->%08x\n", regaddr, regval); return regval; } @@ -1261,7 +1261,7 @@ static void mcan_putreg(FAR struct sam_mcan_s *priv, int offset, uint32_t regval /* Show the register value being written */ - caninfo("%08x<-%08x\n", regaddr, regval); + canllinfo("%08x<-%08x\n", regaddr, regval); /* Write the value */ diff --git a/arch/arm/src/samv7/sam_qspi.c b/arch/arm/src/samv7/sam_qspi.c index b90a515d8b..bbefa3574e 100644 --- a/arch/arm/src/samv7/sam_qspi.c +++ b/arch/arm/src/samv7/sam_qspi.c @@ -378,7 +378,7 @@ static bool qspi_checkreg(struct sam_qspidev_s *priv, bool wr, uint32_t value, { /* Yes... show how many times we did it */ - spiinfo("...[Repeats %d times]...\n", priv->ntimes); + spillinfo("...[Repeats %d times]...\n", priv->ntimes); } /* Save information about the new access */ @@ -412,7 +412,7 @@ static inline uint32_t qspi_getreg(struct sam_qspidev_s *priv, #ifdef CONFIG_SAMV7_QSPI_REGDEBUG if (qspi_checkreg(priv, false, value, address)) { - spiinfo("%08x->%08x\n", address, value); + spillinfo("%08x->%08x\n", address, value); } #endif @@ -435,7 +435,7 @@ static inline void qspi_putreg(struct sam_qspidev_s *priv, uint32_t value, #ifdef CONFIG_SAMV7_QSPI_REGDEBUG if (qspi_checkreg(priv, true, value, address)) { - spiinfo("%08x<-%08x\n", address, value); + spillinfo("%08x<-%08x\n", address, value); } #endif diff --git a/arch/arm/src/samv7/sam_rswdt.c b/arch/arm/src/samv7/sam_rswdt.c index 980ecd5b03..3f13c91199 100644 --- a/arch/arm/src/samv7/sam_rswdt.c +++ b/arch/arm/src/samv7/sam_rswdt.c @@ -190,7 +190,7 @@ static uint32_t sam_getreg(uintptr_t regaddr) { if (count == 4) { - wdinfo("...\n"); + wdllinfo("...\n"); } return regval; @@ -207,7 +207,7 @@ static uint32_t sam_getreg(uintptr_t regaddr) { /* Yes.. then show how many times the value repeated */ - wdinfo("[repeats %d more times]\n", count-3); + wdllinfo("[repeats %d more times]\n", count-3); } /* Save the new address, value, and count */ @@ -219,7 +219,7 @@ static uint32_t sam_getreg(uintptr_t regaddr) /* Show the register value read */ - wdinfo("%08x->%048\n", regaddr, regval); + wdllinfo("%08x->%048\n", regaddr, regval); return regval; } #endif From dbd70a58642d905606fe1d231aba49152e5cf0c3 Mon Sep 17 00:00:00 2001 From: Gregory Nutt Date: Fri, 17 Jun 2016 07:29:58 -0600 Subject: [PATCH 35/75] Restore some debug output that lost its low-level marking --- arch/arm/src/samv7/sam_spi_slave.c | 6 +++--- arch/arm/src/samv7/sam_ssc.c | 10 +++++----- arch/arm/src/samv7/sam_twihs.c | 6 +++--- arch/arm/src/samv7/sam_usbdevhs.c | 4 ++-- arch/arm/src/samv7/sam_wdt.c | 8 ++++---- 5 files changed, 17 insertions(+), 17 deletions(-) diff --git a/arch/arm/src/samv7/sam_spi_slave.c b/arch/arm/src/samv7/sam_spi_slave.c index d2856cd2e9..3f3df57587 100644 --- a/arch/arm/src/samv7/sam_spi_slave.c +++ b/arch/arm/src/samv7/sam_spi_slave.c @@ -252,7 +252,7 @@ static bool spi_checkreg(struct sam_spidev_s *priv, bool wr, uint32_t value, { /* Yes... show how many times we did it */ - spiinfo("...[Repeats %d times]...\n", priv->ntimes); + spillinfo("...[Repeats %d times]...\n", priv->ntimes); } /* Save information about the new access */ @@ -285,7 +285,7 @@ static uint32_t spi_getreg(struct sam_spidev_s *priv, unsigned int offset) #ifdef CONFIG_SAMV7_SPI_REGDEBUG if (spi_checkreg(priv, false, value, address)) { - spiinfo("%08x->%08x\n", address, value); + spillinfo("%08x->%08x\n", address, value); } #endif @@ -308,7 +308,7 @@ static void spi_putreg(struct sam_spidev_s *priv, uint32_t value, #ifdef CONFIG_SAMV7_SPI_REGDEBUG if (spi_checkreg(priv, true, value, address)) { - spiinfo("%08x<-%08x\n", address, value); + spillinfo("%08x<-%08x\n", address, value); } #endif diff --git a/arch/arm/src/samv7/sam_ssc.c b/arch/arm/src/samv7/sam_ssc.c index c07d554258..d28c866b56 100644 --- a/arch/arm/src/samv7/sam_ssc.c +++ b/arch/arm/src/samv7/sam_ssc.c @@ -678,7 +678,7 @@ static bool ssc_checkreg(struct sam_ssc_s *priv, bool wr, uint32_t regval, { /* Yes... show how many times we did it */ - i2sinfo("...[Repeats %d times]...\n", priv->count); + i2sllinfo("...[Repeats %d times]...\n", priv->count); } /* Save information about the new access */ @@ -712,7 +712,7 @@ static inline uint32_t ssc_getreg(struct sam_ssc_s *priv, #ifdef CONFIG_SAMV7_SSC_REGDEBUG if (ssc_checkreg(priv, false, regval, regaddr)) { - i2sinfo("%08x->%08x\n", regaddr, regval); + i2sllinfo("%08x->%08x\n", regaddr, regval); } #endif @@ -735,7 +735,7 @@ static inline void ssc_putreg(struct sam_ssc_s *priv, unsigned int offset, #ifdef CONFIG_SAMV7_SSC_REGDEBUG if (ssc_checkreg(priv, true, regval, regaddr)) { - i2sinfo("%08x<-%08x\n", regaddr, regval); + i2sllinfo("%08x<-%08x\n", regaddr, regval); } #endif @@ -1064,7 +1064,7 @@ static void ssc_dma_sampleinit(struct sam_ssc_s *priv, #if defined(CONFIG_SAMV7_SSC_DMADEBUG) && defined(SSC_HAVE_RX) static void ssc_rxdma_sampledone(struct sam_ssc_s *priv, int result) { - i2sinfo("result: %d\n", result); + i2llsinfo("result: %d\n", result); /* Sample the final registers */ @@ -1129,7 +1129,7 @@ static void ssc_rxdma_sampledone(struct sam_ssc_s *priv, int result) #if defined(CONFIG_SAMV7_SSC_DMADEBUG) && defined(SSC_HAVE_TX) static void ssc_txdma_sampledone(struct sam_ssc_s *priv, int result) { - i2sinfo("result: %d\n", result); + i2sllinfo("result: %d\n", result); /* Sample the final registers */ diff --git a/arch/arm/src/samv7/sam_twihs.c b/arch/arm/src/samv7/sam_twihs.c index 93d59f2a87..82312a65dd 100644 --- a/arch/arm/src/samv7/sam_twihs.c +++ b/arch/arm/src/samv7/sam_twihs.c @@ -353,7 +353,7 @@ static bool twi_checkreg(struct twi_dev_s *priv, bool wr, uint32_t value, { /* Yes... show how many times we did it */ - i2cinfo("...[Repeats %d times]...\n", priv->ntimes); + i2cllinfo("...[Repeats %d times]...\n", priv->ntimes); } /* Save information about the new access */ @@ -385,7 +385,7 @@ static uint32_t twi_getabs(struct twi_dev_s *priv, uintptr_t address) if (twi_checkreg(priv, false, value, address)) { - i2cinfo("%08x->%08x\n", address, value); + i2cllinfo("%08x->%08x\n", address, value); } return value; @@ -406,7 +406,7 @@ static void twi_putabs(struct twi_dev_s *priv, uintptr_t address, { if (twi_checkreg(priv, true, value, address)) { - i2cinfo("%08x<-%08x\n", address, value); + i2cllinfo("%08x<-%08x\n", address, value); } putreg32(value, address); diff --git a/arch/arm/src/samv7/sam_usbdevhs.c b/arch/arm/src/samv7/sam_usbdevhs.c index e7660280b6..ac5dd27034 100644 --- a/arch/arm/src/samv7/sam_usbdevhs.c +++ b/arch/arm/src/samv7/sam_usbdevhs.c @@ -736,7 +736,7 @@ const struct trace_msg_t g_usb_trace_strings_intdecode[] = #ifdef CONFIG_SAMV7_USBHS_REGDEBUG static void sam_printreg(uintptr_t regaddr, uint32_t regval, bool iswrite) { - uinfo("%p%s%08x\n", regaddr, iswrite ? "<-" : "->", regval); + ullinfo("%p%s%08x\n", regaddr, iswrite ? "<-" : "->", regval); } #endif @@ -787,7 +787,7 @@ static void sam_checkreg(uintptr_t regaddr, uint32_t regval, bool iswrite) { /* No.. More than one. */ - uinfo("[repeats %d more times]\n", count); + ullinfo("[repeats %d more times]\n", count); } } diff --git a/arch/arm/src/samv7/sam_wdt.c b/arch/arm/src/samv7/sam_wdt.c index d317bbd74d..345b645ca8 100644 --- a/arch/arm/src/samv7/sam_wdt.c +++ b/arch/arm/src/samv7/sam_wdt.c @@ -190,7 +190,7 @@ static uint32_t sam_getreg(uintptr_t regaddr) { if (count == 4) { - wdinfo("...\n"); + wdllinfo("...\n"); } return regval; @@ -207,7 +207,7 @@ static uint32_t sam_getreg(uintptr_t regaddr) { /* Yes.. then show how many times the value repeated */ - wdinfo("[repeats %d more times]\n", count-3); + wdllinfo("[repeats %d more times]\n", count-3); } /* Save the new address, value, and count */ @@ -219,7 +219,7 @@ static uint32_t sam_getreg(uintptr_t regaddr) /* Show the register value read */ - wdinfo("%08x->%048\n", regaddr, regval); + wdllinfo("%08x->%048\n", regaddr, regval); return regval; } #endif @@ -237,7 +237,7 @@ static void sam_putreg(uint32_t regval, uintptr_t regaddr) { /* Show the register value being written */ - wdinfo("%08x<-%08x\n", regaddr, regval); + wdllinfo("%08x<-%08x\n", regaddr, regval); /* Write the value */ From dd8d212c2693f7beeda15573388c0e8ca152d169 Mon Sep 17 00:00:00 2001 From: Sebastien Lorquet Date: Fri, 17 Jun 2016 07:32:33 -0600 Subject: [PATCH 36/75] Apply same STM32 patch to STM32 L4 --- arch/arm/src/stm32l4/stm32l4_gpio.c | 9 +-------- 1 file changed, 1 insertion(+), 8 deletions(-) diff --git a/arch/arm/src/stm32l4/stm32l4_gpio.c b/arch/arm/src/stm32l4/stm32l4_gpio.c index 8ae6efdb11..d7f3dce3ee 100644 --- a/arch/arm/src/stm32l4/stm32l4_gpio.c +++ b/arch/arm/src/stm32l4/stm32l4_gpio.c @@ -176,6 +176,7 @@ int stm32l4_configgpio(uint32_t cfgset) break; case GPIO_OUTPUT: /* General purpose output mode */ + stm32l4_gpiowrite(cfgset, (cfgset & GPIO_OUTPUT_SET) != 0); /* Set the initial output value */ pinmode = GPIO_MODER_OUTPUT; break; @@ -305,14 +306,6 @@ int stm32l4_configgpio(uint32_t cfgset) putreg32(regval, base + STM32L4_GPIO_OTYPER_OFFSET); - /* If it is an output... set the pin to the correct initial state. */ - - if (pinmode == GPIO_MODER_OUTPUT) - { - bool value = ((cfgset & GPIO_OUTPUT_SET) != 0); - stm32l4_gpiowrite(cfgset, value); - } - /* Otherwise, it is an input pin. Should it configured as an EXTI interrupt? */ else if ((cfgset & GPIO_EXTI) != 0) From 2f24f911f510cdb2addf3f11b1308a8155d8d21b Mon Sep 17 00:00:00 2001 From: Gregory Nutt Date: Fri, 17 Jun 2016 08:13:22 -0600 Subject: [PATCH 37/75] Hook configs/stm32f746-ws into the configuration system --- configs/Kconfig | 15 +- configs/README.txt | 3 + configs/stm32f746-ws/nsh/defconfig | 240 +++++++++++++++++++++++------ 3 files changed, 206 insertions(+), 52 deletions(-) diff --git a/configs/Kconfig b/configs/Kconfig index 98d4b30b2d..de92e92a6a 100644 --- a/configs/Kconfig +++ b/configs/Kconfig @@ -997,7 +997,7 @@ config ARCH_BOARD_STM32F429I_DISCO config ARCH_BOARD_STM32F746G_DISCO bool "STMicro STM32F746G-Discovery board" - depends on ARCH_CHIP_STM32F746 + depends on ARCH_CHIP_STM32F746NG select ARCH_HAVE_LEDS select ARCH_HAVE_BUTTONS select ARCH_HAVE_IRQBUTTONS @@ -1006,6 +1006,15 @@ config ARCH_BOARD_STM32F746G_DISCO MCU. The STM32F746NGH6 is a 216MHz Cortex-M7 operation with 1024Kb Flash memory and 320Kb SRAM. +config ARCH_BOARD_STM32F746_WS + bool "Waveshare STM32F746 board" + depends on ARCH_CHIP_STM32F746IG + select ARCH_HAVE_LEDS + select ARCH_HAVE_BUTTONS + select ARCH_HAVE_IRQBUTTONS + ---help--- + Waveshare STM32F746 development board featuring the STM32F746IG MCU. + config ARCH_BOARD_STM32L476VG_DISCO bool "STMicro STM32F746VG-Discovery board" depends on ARCH_CHIP_STM32L476RG @@ -1438,6 +1447,7 @@ config ARCH_BOARD default "stm32f411e-disco" if ARCH_BOARD_STM32F411E_DISCO default "stm32f429i-disco" if ARCH_BOARD_STM32F429I_DISCO default "stm32f746g-disco" if ARCH_BOARD_STM32F746G_DISCO + default "stm32f746-ws" if ARCH_BOARD_STM32F746_WS default "stm32l476vg-disco" if ARCH_BOARD_STM32L476VG_DISCO default "stm32ldiscovery" if ARCH_BOARD_STM32L_DISCOVERY default "stm32vldiscovery" if ARCH_BOARD_STM32VL_DISCOVERY @@ -1812,6 +1822,9 @@ endif if ARCH_BOARD_STM32F746G_DISCO source "configs/stm32f746g-disco/Kconfig" endif +if ARCH_BOARD_STM32F746_WS +source "configs/stm32f746-ws/Kconfig" +endif if ARCH_BOARD_STM32L476VG_DISCO source "configs/stm32l476vg-disco/Kconfig" endif diff --git a/configs/README.txt b/configs/README.txt index 3e44ef649c..2e4c4aad95 100644 --- a/configs/README.txt +++ b/configs/README.txt @@ -658,6 +658,9 @@ configs/stm32f746g-disco MCU. The STM32F746NGH6 is a 216MHz Cortex-M7 operation with 1024Kb Flash memory and 300Kb SRAM. +configs/stm32f746g-ws + Waveshare STM32F746 development board featuring the STM32F746IG MCU. + configs/stm32l476vg-disco STMicro STM32L476VG_DISCO development board featuring the STM32L476VG MCU. The STM32L476VG is a Cortex-M4 optimised for low-power operation diff --git a/configs/stm32f746-ws/nsh/defconfig b/configs/stm32f746-ws/nsh/defconfig index df3654343f..75e56a0d01 100644 --- a/configs/stm32f746-ws/nsh/defconfig +++ b/configs/stm32f746-ws/nsh/defconfig @@ -16,7 +16,7 @@ CONFIG_HOST_LINUX=y # # Build Configuration # -CONFIG_APPS_DIR="../apps" +# CONFIG_APPS_DIR="../apps" CONFIG_BUILD_FLAT=y # CONFIG_BUILD_2PASS is not set @@ -43,9 +43,10 @@ CONFIG_ARCH_STDARG_H=y # Debug Options # # CONFIG_DEBUG_FEATURES is not set -CONFIG_ARCH_HAVE_HEAPCHECK=y CONFIG_ARCH_HAVE_STACKCHECK=y CONFIG_STACK_COLORATION=y +CONFIG_ARCH_HAVE_HEAPCHECK=y +# CONFIG_HEAP_COLORATION is not set CONFIG_DEBUG_SYMBOLS=y CONFIG_ARCH_HAVE_CUSTOMOPT=y CONFIG_DEBUG_NOOPT=y @@ -124,7 +125,7 @@ CONFIG_ARCH_HAVE_CMNVECTOR=y CONFIG_ARMV7M_CMNVECTOR=y # CONFIG_ARMV7M_LAZYFPU is not set CONFIG_ARCH_HAVE_FPU=y -CONFIG_ARCH_HAVE_DPFPU=y +# CONFIG_ARCH_HAVE_DPFPU is not set CONFIG_ARCH_FPU=y # CONFIG_ARCH_HAVE_TRUSTZONE is not set CONFIG_ARM_HAVE_MPU_UNIFIED=y @@ -151,29 +152,126 @@ CONFIG_ARMV7M_HAVE_STACKCHECK=y # CONFIG_ARMV7M_STACKCHECK is not set # CONFIG_ARMV7M_ITMSYSLOG is not set # CONFIG_SERIAL_TERMIOS is not set +# CONFIG_USART6_RS485 is not set +# CONFIG_SERIAL_DISABLE_REORDERING is not set # # STM32 F7 Configuration Options # - +# CONFIG_ARCH_CHIP_STM32F745VG is not set +# CONFIG_ARCH_CHIP_STM32F745VE is not set +# CONFIG_ARCH_CHIP_STM32F745IG is not set +# CONFIG_ARCH_CHIP_STM32F745IE is not set +# CONFIG_ARCH_CHIP_STM32F745ZE is not set +# CONFIG_ARCH_CHIP_STM32F745ZG is not set +# CONFIG_ARCH_CHIP_STM32F746BG is not set +# CONFIG_ARCH_CHIP_STM32F746VG is not set +# CONFIG_ARCH_CHIP_STM32F746VE is not set +# CONFIG_ARCH_CHIP_STM32F746BE is not set +# CONFIG_ARCH_CHIP_STM32F746ZG is not set +# CONFIG_ARCH_CHIP_STM32F746IE is not set +# CONFIG_ARCH_CHIP_STM32F746NG is not set +# CONFIG_ARCH_CHIP_STM32F746NE is not set +# CONFIG_ARCH_CHIP_STM32F746ZE is not set CONFIG_ARCH_CHIP_STM32F746IG=y -# CONFIG_ARCH_CHIP_STM32F756 is not set +# CONFIG_ARCH_CHIP_STM32F756NG is not set +# CONFIG_ARCH_CHIP_STM32F756BG is not set +# CONFIG_ARCH_CHIP_STM32F756IG is not set +# CONFIG_ARCH_CHIP_STM32F756VG is not set +# CONFIG_ARCH_CHIP_STM32F756ZG is not set +# CONFIG_ARCH_CHIP_STM32F765NI is not set +# CONFIG_ARCH_CHIP_STM32F765VI is not set +# CONFIG_ARCH_CHIP_STM32F765VG is not set +# CONFIG_ARCH_CHIP_STM32F765BI is not set +# CONFIG_ARCH_CHIP_STM32F765NG is not set +# CONFIG_ARCH_CHIP_STM32F765ZG is not set +# CONFIG_ARCH_CHIP_STM32F765ZI is not set +# CONFIG_ARCH_CHIP_STM32F765IG is not set +# CONFIG_ARCH_CHIP_STM32F765BG is not set +# CONFIG_ARCH_CHIP_STM32F765II is not set +# CONFIG_ARCH_CHIP_STM32F767NG is not set +# CONFIG_ARCH_CHIP_STM32F767IG is not set +# CONFIG_ARCH_CHIP_STM32F767VG is not set +# CONFIG_ARCH_CHIP_STM32F767ZG is not set +# CONFIG_ARCH_CHIP_STM32F767NI is not set +# CONFIG_ARCH_CHIP_STM32F767VI is not set +# CONFIG_ARCH_CHIP_STM32F767BG is not set +# CONFIG_ARCH_CHIP_STM32F767ZI is not set +# CONFIG_ARCH_CHIP_STM32F767II is not set +# CONFIG_ARCH_CHIP_STM32F769BI is not set +# CONFIG_ARCH_CHIP_STM32F769II is not set +# CONFIG_ARCH_CHIP_STM32F769BG is not set +# CONFIG_ARCH_CHIP_STM32F769NI is not set +# CONFIG_ARCH_CHIP_STM32F769AI is not set +# CONFIG_ARCH_CHIP_STM32F769NG is not set +# CONFIG_ARCH_CHIP_STM32F769IG is not set +# CONFIG_ARCH_CHIP_STM32F777ZI is not set +# CONFIG_ARCH_CHIP_STM32F777VI is not set +# CONFIG_ARCH_CHIP_STM32F777NI is not set +# CONFIG_ARCH_CHIP_STM32F777BI is not set +# CONFIG_ARCH_CHIP_STM32F777II is not set +# CONFIG_ARCH_CHIP_STM32F778AI is not set +# CONFIG_ARCH_CHIP_STM32F779II is not set +# CONFIG_ARCH_CHIP_STM32F779NI is not set +# CONFIG_ARCH_CHIP_STM32F779BI is not set +# CONFIG_ARCH_CHIP_STM32F779AI is not set CONFIG_STM32F7_STM32F74XX=y # CONFIG_STM32F7_STM32F75XX is not set -# CONFIG_STM32F7_FLASH_512KB is not set -CONFIG_STM32F7_FLASH_1024KB=y +# CONFIG_STM32F7_STM32F76XX is not set +# CONFIG_STM32F7_STM32F77XX is not set +# CONFIG_STM32F7_IO_CONFIG_V is not set +CONFIG_STM32F7_IO_CONFIG_I=y +# CONFIG_STM32F7_IO_CONFIG_Z is not set +# CONFIG_STM32F7_IO_CONFIG_N is not set +# CONFIG_STM32F7_IO_CONFIG_B is not set +# CONFIG_STM32F7_IO_CONFIG_A is not set +# CONFIG_STM32F7_STM32F745XX is not set +CONFIG_STM32F7_STM32F746XX=y +# CONFIG_STM32F7_STM32F756XX is not set +# CONFIG_STM32F7_STM32F765XX is not set +# CONFIG_STM32F7_STM32F767XX is not set +# CONFIG_STM32F7_STM32F768XX is not set +# CONFIG_STM32F7_STM32F768AX is not set +# CONFIG_STM32F7_STM32F769XX is not set +# CONFIG_STM32F7_STM32F769AX is not set +# CONFIG_STM32F7_STM32F777XX is not set +# CONFIG_STM32F7_STM32F778XX is not set +# CONFIG_STM32F7_STM32F778AX is not set +# CONFIG_STM32F7_STM32F779XX is not set +# CONFIG_STM32F7_STM32F779AX is not set +# CONFIG_STM32F7_FLASH_CONFIG_E is not set +# CONFIG_STM32F7_FLASH_CONFIG_I is not set +CONFIG_STM32F7_FLASH_OVERRIDE_DEFAULT=y +# CONFIG_STM32F7_FLASH_OVERRIDE_E is not set +# CONFIG_STM32F7_FLASH_OVERRIDE_G is not set +# CONFIG_STM32F7_FLASH_OVERRIDE_I is not set # # STM32 Peripheral Support # CONFIG_STM32F7_HAVE_LTDC=y -# CONFIG_STM32F7_ADC is not set +CONFIG_STM32F7_HAVE_FSMC=y +CONFIG_STM32F7_HAVE_ETHRNET=y +CONFIG_STM32F7_HAVE_RNG=y +CONFIG_STM32F7_HAVE_SPI5=y +CONFIG_STM32F7_HAVE_SPI6=y +# CONFIG_STM32F7_HAVE_SDMMC2 is not set +# CONFIG_STM32F7_HAVE_CAN3 is not set +CONFIG_STM32F7_HAVE_DCMI=y +# CONFIG_STM32F7_HAVE_DSIHOST is not set +CONFIG_STM32F7_HAVE_DMA2D=y +# CONFIG_STM32F7_HAVE_JPEG is not set +# CONFIG_STM32F7_HAVE_CRYP is not set +# CONFIG_STM32F7_HAVE_HASH is not set +# CONFIG_STM32F7_HAVE_DFSDM1 is not set +CONFIG_STM32F7_ADC=y # CONFIG_STM32F7_CAN is not set # CONFIG_STM32F7_DAC is not set # CONFIG_STM32F7_DMA is not set CONFIG_STM32F7_I2C=y # CONFIG_STM32F7_SAI is not set CONFIG_STM32F7_SPI=y +# CONFIG_STM32F7_TIM is not set CONFIG_STM32F7_USART=y CONFIG_STM32F7_ADC1=y # CONFIG_STM32F7_ADC2 is not set @@ -183,12 +281,12 @@ CONFIG_STM32F7_ADC1=y # CONFIG_STM32F7_CAN2 is not set # CONFIG_STM32F7_CEC is not set # CONFIG_STM32F7_CRC is not set -# CONFIG_STM32F7_CRYP is not set # CONFIG_STM32F7_DMA1 is not set # CONFIG_STM32F7_DMA2 is not set # CONFIG_STM32F7_DAC1 is not set # CONFIG_STM32F7_DAC2 is not set # CONFIG_STM32F7_DCMI is not set +# CONFIG_STM32F7_DMA2D is not set # CONFIG_STM32F7_ETHMAC is not set # CONFIG_STM32F7_FSMC is not set CONFIG_STM32F7_I2C1=y @@ -196,12 +294,11 @@ CONFIG_STM32F7_I2C1=y # CONFIG_STM32F7_I2C3 is not set # CONFIG_STM32F7_LPTIM1 is not set # CONFIG_STM32F7_LTDC is not set -# CONFIG_STM32F7_DMA2D is not set # CONFIG_STM32F7_OTGFS is not set # CONFIG_STM32F7_OTGHS is not set # CONFIG_STM32F7_QUADSPI is not set -# CONFIG_STM32F7_SAI1 is not set # CONFIG_STM32F7_RNG is not set +# CONFIG_STM32F7_SAI1 is not set # CONFIG_STM32F7_SAI2 is not set # CONFIG_STM32F7_SDMMC1 is not set # CONFIG_STM32F7_SPDIFRX is not set @@ -236,6 +333,18 @@ CONFIG_STM32F7_USART6=y # CONFIG_STM32F7_UART8 is not set # CONFIG_STM32F7_IWDG is not set # CONFIG_STM32F7_WWDG is not set + +# +# U[S]ART Configuration +# +# CONFIG_STM32F7_FLOWCONTROL_BROKEN is not set +# CONFIG_STM32F7_USART_BREAKS is not set + +# +# SPI Configuration +# +# CONFIG_STM32F7_SPI_INTERRUPTS is not set +# CONFIG_STM32F7_SPI_DMA is not set # CONFIG_STM32F7_CUSTOM_CLOCKCONFIG is not set # @@ -299,7 +408,6 @@ CONFIG_RAM_SIZE=245760 # # Board Selection # -# CONFIG_ARCH_BOARD_STM32F746G_DISCO is not set CONFIG_ARCH_BOARD_STM32F746_WS=y # CONFIG_ARCH_BOARD_CUSTOM is not set CONFIG_ARCH_BOARD="stm32f746-ws" @@ -307,18 +415,23 @@ CONFIG_ARCH_BOARD="stm32f746-ws" # # Common Board Options # -# CONFIG_ARCH_HAVE_LEDS is not set -# CONFIG_ARCH_LEDS is not set -# CONFIG_ARCH_HAVE_BUTTONS is not set -# CONFIG_ARCH_BUTTONS is not set -# CONFIG_ARCH_HAVE_IRQBUTTONS is not set -# CONFIG_ARCH_IRQBUTTONS is not set +CONFIG_ARCH_HAVE_LEDS=y +CONFIG_ARCH_LEDS=y +CONFIG_ARCH_HAVE_BUTTONS=y +# CONFIG_ARCH_BUTTONS is not set +CONFIG_ARCH_HAVE_IRQBUTTONS=y CONFIG_NSH_MMCSDMINOR=0 # # Board-Specific Options # CONFIG_LIB_BOARDCTL=y +# CONFIG_BOARDCTL_UNIQUEID is not set +# CONFIG_BOARDCTL_TSCTEST is not set +# CONFIG_BOARDCTL_ADCTEST is not set +# CONFIG_BOARDCTL_PWMTEST is not set +# CONFIG_BOARDCTL_GRAPHICS is not set +# CONFIG_BOARDCTL_IOCTL is not set # # RTOS Features @@ -370,6 +483,7 @@ CONFIG_NPTHREAD_KEYS=4 # # CONFIG_SCHED_CPULOAD is not set CONFIG_SCHED_INSTRUMENTATION=y +# CONFIG_SCHED_INSTRUMENTATION_PREEMPTION is not set CONFIG_SCHED_INSTRUMENTATION_BUFFER=y CONFIG_SCHED_NOTE_BUFSIZE=512 @@ -392,6 +506,7 @@ CONFIG_NAME_MAX=32 # CONFIG_SCHED_STARTHOOK is not set # CONFIG_SCHED_ATEXIT is not set # CONFIG_SCHED_ONEXIT is not set +# CONFIG_SIG_EVTHREAD is not set # # Signal Numbers @@ -420,7 +535,6 @@ CONFIG_SCHED_HPWORKSTACKSIZE=1800 CONFIG_SCHED_LPWORK=y CONFIG_SCHED_LPNTHREADS=1 CONFIG_SCHED_LPWORKPRIORITY=50 -CONFIG_SCHED_LPWORKPRIOMAX=176 CONFIG_SCHED_LPWORKPERIOD=50000 CONFIG_SCHED_LPWORKSTACKSIZE=1800 @@ -436,7 +550,7 @@ CONFIG_PTHREAD_STACK_DEFAULT=2048 # # Device Drivers # -#CONFIG_DISABLE_POLL is not set +# CONFIG_DISABLE_POLL is not set CONFIG_DEV_NULL=y # CONFIG_DEV_ZERO is not set # CONFIG_DEV_LOOP is not set @@ -453,7 +567,11 @@ CONFIG_DEV_NULL=y # CONFIG_PWM is not set CONFIG_ARCH_HAVE_I2CRESET=y CONFIG_I2C=y +# CONFIG_I2C_SLAVE is not set +# CONFIG_I2C_POLLED is not set CONFIG_I2C_RESET=y +# CONFIG_I2C_TRACE is not set +CONFIG_I2C_DRIVER=y CONFIG_SPI=y # CONFIG_SPI_SLAVE is not set CONFIG_SPI_EXCHANGE=y @@ -462,22 +580,36 @@ CONFIG_SPI_EXCHANGE=y # CONFIG_SPI_BITBANG is not set # CONFIG_SPI_HWFEATURES is not set # CONFIG_SPI_CRCGENERATION is not set +# CONFIG_SPI_CS_CONTROL is not set +# CONFIG_SPI_CS_DELAY_CONTROL is not set # CONFIG_I2S is not set -CONFIG_ADC=y # # Timer Driver Support # # CONFIG_TIMER is not set +# CONFIG_RTC is not set CONFIG_WATCHDOG=y CONFIG_WATCHDOG_DEVPATH="/dev/watchdog0" -# CONFIG_ANALOG is not set +# CONFIG_TIMERS_CS2100CP is not set +CONFIG_ANALOG=y +CONFIG_ADC=y +CONFIG_ADC_FIFOSIZE=8 +# CONFIG_ADC_ADS1242 is not set +# CONFIG_ADC_ADS125X is not set +# CONFIG_ADC_PGA11X is not set +# CONFIG_DAC is not set # CONFIG_AUDIO_DEVICES is not set # CONFIG_VIDEO_DEVICES is not set # CONFIG_BCH is not set # CONFIG_INPUT is not set # CONFIG_IOEXPANDER is not set + +# +# LCD Driver Support +# # CONFIG_LCD is not set +# CONFIG_SLCD is not set # # LED Support @@ -485,6 +617,7 @@ CONFIG_WATCHDOG_DEVPATH="/dev/watchdog0" # CONFIG_USERLED is not set # CONFIG_RGBLED is not set # CONFIG_PCA9635PW is not set +# CONFIG_NCP5623C is not set # CONFIG_MMCSD is not set # CONFIG_MODEM is not set # CONFIG_MTD is not set @@ -502,7 +635,7 @@ CONFIG_SERIAL=y # CONFIG_UART1_SERIALDRIVER is not set # CONFIG_UART2_SERIALDRIVER is not set # CONFIG_UART3_SERIALDRIVER is not set -# CONFIG_UART4_SERIALDRIVER is not set +# CONFIG_UART4_SERIALDRIVER is not set # CONFIG_UART5_SERIALDRIVER is not set # CONFIG_UART6_SERIALDRIVER is not set # CONFIG_UART7_SERIALDRIVER is not set @@ -515,13 +648,13 @@ CONFIG_SERIAL=y # CONFIG_USART3_SERIALDRIVER is not set # CONFIG_USART4_SERIALDRIVER is not set # CONFIG_USART5_SERIALDRIVER is not set - -# -# USART Configuration -# CONFIG_USART6_SERIALDRIVER=y +# CONFIG_USART7_SERIALDRIVER is not set +# CONFIG_USART8_SERIALDRIVER is not set +# CONFIG_OTHER_UART_SERIALDRIVER is not set CONFIG_MCU_SERIAL=y CONFIG_STANDARD_SERIAL=y +CONFIG_SERIAL_NPOLLWAITERS=2 # CONFIG_SERIAL_IFLOWCONTROL is not set # CONFIG_SERIAL_OFLOWCONTROL is not set # CONFIG_SERIAL_DMA is not set @@ -555,6 +688,7 @@ CONFIG_USART6_2STOP=0 # # CONFIG_RAMLOG is not set # CONFIG_SYSLOG_CONSOLE is not set +# CONFIG_DRIVER_NOTE is not set # # Networking Support @@ -580,6 +714,7 @@ CONFIG_USART6_2STOP=0 # CONFIG_DISABLE_PSEUDOFS_OPERATIONS is not set # CONFIG_FS_READABLE is not set # CONFIG_FS_WRITABLE is not set +# CONFIG_FS_AIO is not set # CONFIG_FS_NAMED_SEMAPHORES is not set CONFIG_FS_MQUEUE_MPATH="/var/mqueue" # CONFIG_FS_RAMMAP is not set @@ -658,6 +793,7 @@ CONFIG_EOL_IS_EITHER_CRLF=y CONFIG_POSIX_SPAWN_PROXY_STACKSIZE=1024 CONFIG_TASK_SPAWN_DEFAULT_STACKSIZE=2048 CONFIG_LIBC_STRERROR=y +# CONFIG_LIBC_STRERROR_SHORT is not set # CONFIG_LIBC_PERROR_STDOUT is not set CONFIG_ARCH_LOWPUTC=y # CONFIG_LIBC_LOCALTIME is not set @@ -672,6 +808,7 @@ CONFIG_ARCH_HAVE_TLS=y # # Non-standard Library Support # +# CONFIG_LIB_CRC64_FAST is not set # CONFIG_LIB_KBDCODEC is not set # CONFIG_LIB_SLCDCODEC is not set @@ -704,7 +841,7 @@ CONFIG_BUILTIN_PROXY_STACKSIZE=1024 # # Examples # -# CONFIG_EXAMPLES_BUTTONS is not set +# CONFIG_EXAMPLES_ADC is not set # CONFIG_EXAMPLES_CHAT is not set # CONFIG_EXAMPLES_CONFIGDATA is not set # CONFIG_EXAMPLES_CPUHOG is not set @@ -715,10 +852,10 @@ CONFIG_BUILTIN_PROXY_STACKSIZE=1024 # CONFIG_EXAMPLES_FTPD is not set # CONFIG_EXAMPLES_HELLO is not set # CONFIG_EXAMPLES_HELLOXX is not set -# CONFIG_EXAMPLES_JSON is not set # CONFIG_EXAMPLES_HIDKBD is not set -# CONFIG_EXAMPLES_KEYPADTEST is not set # CONFIG_EXAMPLES_IGMP is not set +# CONFIG_EXAMPLES_JSON is not set +# CONFIG_EXAMPLES_KEYPADTEST is not set # CONFIG_EXAMPLES_MEDIA is not set # CONFIG_EXAMPLES_MM is not set # CONFIG_EXAMPLES_MODBUS is not set @@ -728,17 +865,17 @@ CONFIG_EXAMPLES_NSH=y # CONFIG_EXAMPLES_NSH_CXXINITIALIZE is not set # CONFIG_EXAMPLES_NULL is not set # CONFIG_EXAMPLES_NX is not set -# CONFIG_EXAMPLES_NXTERM is not set # CONFIG_EXAMPLES_NXFFS is not set # CONFIG_EXAMPLES_NXHELLO is not set # CONFIG_EXAMPLES_NXIMAGE is not set # CONFIG_EXAMPLES_NXLINES is not set +# CONFIG_EXAMPLES_NXTERM is not set # CONFIG_EXAMPLES_NXTEXT is not set # CONFIG_EXAMPLES_OSTEST is not set # CONFIG_EXAMPLES_PCA9635 is not set # CONFIG_EXAMPLES_PIPE is not set -# CONFIG_EXAMPLES_PPPD is not set # CONFIG_EXAMPLES_POSIXSPAWN is not set +# CONFIG_EXAMPLES_PPPD is not set # CONFIG_EXAMPLES_RGBLED is not set # CONFIG_EXAMPLES_RGMP is not set # CONFIG_EXAMPLES_SENDMAIL is not set @@ -746,16 +883,17 @@ CONFIG_EXAMPLES_NSH=y # CONFIG_EXAMPLES_SERIALRX is not set # CONFIG_EXAMPLES_SERLOOP is not set # CONFIG_EXAMPLES_SLCD is not set -# CONFIG_EXAMPLES_SMART_TEST is not set # CONFIG_EXAMPLES_SMART is not set +# CONFIG_EXAMPLES_SMART_TEST is not set # CONFIG_EXAMPLES_SMP is not set # CONFIG_EXAMPLES_TCPECHO is not set # CONFIG_EXAMPLES_TELNETD is not set # CONFIG_EXAMPLES_TIFF is not set # CONFIG_EXAMPLES_TOUCHSCREEN is not set -# CONFIG_EXAMPLES_WEBSERVER is not set +# CONFIG_EXAMPLES_USBSERIAL is not set # CONFIG_EXAMPLES_USBTERM is not set # CONFIG_EXAMPLES_WATCHDOG is not set +# CONFIG_EXAMPLES_WEBSERVER is not set # # File System Utilities @@ -777,8 +915,8 @@ CONFIG_EXAMPLES_NSH=y # Interpreters # # CONFIG_INTERPRETERS_FICL is not set -# CONFIG_INTERPRETERS_PCODE is not set # CONFIG_INTERPRETERS_MICROPYTHON is not set +# CONFIG_INTERPRETERS_PCODE is not set # # FreeModBus @@ -788,7 +926,9 @@ CONFIG_EXAMPLES_NSH=y # # Network Utilities # +# CONFIG_NETUTILS_CHAT is not set # CONFIG_NETUTILS_CODECS is not set +# CONFIG_NETUTILS_ESP8266 is not set # CONFIG_NETUTILS_FTPC is not set # CONFIG_NETUTILS_JSON is not set # CONFIG_NETUTILS_SMTP is not set @@ -872,6 +1012,7 @@ CONFIG_NSH_CMDOPT_DF_H=y CONFIG_NSH_CODECS_BUFSIZE=128 CONFIG_NSH_CMDOPT_HEXDUMP=y CONFIG_NSH_FILEIOSIZE=512 +# CONFIG_NSH_STRERROR is not set # # Scripting Support @@ -901,25 +1042,11 @@ CONFIG_NSH_ARCHINIT=y # # System Libraries and NSH Add-Ons # -# CONFIG_SYSTEM_FREE is not set # CONFIG_SYSTEM_CLE is not set # CONFIG_SYSTEM_CUTERM is not set -# CONFIG_SYSTEM_INSTALL is not set +# CONFIG_SYSTEM_FREE is not set # CONFIG_SYSTEM_HEX2BIN is not set # CONFIG_SYSTEM_HEXED is not set -# CONFIG_SYSTEM_RAMTEST is not set -CONFIG_READLINE_HAVE_EXTMATCH=y -CONFIG_SYSTEM_READLINE=y -CONFIG_READLINE_ECHO=y -# CONFIG_READLINE_TABCOMPLETION is not set -# CONFIG_READLINE_CMD_HISTORY is not set -# CONFIG_SYSTEM_SUDOKU is not set -# CONFIG_SYSTEM_VI is not set -# CONFIG_SYSTEM_UBLOXMODEM is not set -# CONFIG_SYSTEM_ZMODEM is not set - -CONFIG_I2C_DRIVER=y - CONFIG_SYSTEM_I2CTOOL=y CONFIG_I2CTOOL_MINBUS=1 CONFIG_I2CTOOL_MAXBUS=1 @@ -927,4 +1054,15 @@ CONFIG_I2CTOOL_MINADDR=0x03 CONFIG_I2CTOOL_MAXADDR=0x77 CONFIG_I2CTOOL_MAXREGADDR=0xff CONFIG_I2CTOOL_DEFFREQ=100000 - +# CONFIG_SYSTEM_INSTALL is not set +# CONFIG_SYSTEM_RAMTEST is not set +CONFIG_READLINE_HAVE_EXTMATCH=y +CONFIG_SYSTEM_READLINE=y +CONFIG_READLINE_ECHO=y +# CONFIG_READLINE_TABCOMPLETION is not set +# CONFIG_READLINE_CMD_HISTORY is not set +# CONFIG_SYSTEM_STACKMONITOR is not set +# CONFIG_SYSTEM_SUDOKU is not set +# CONFIG_SYSTEM_UBLOXMODEM is not set +# CONFIG_SYSTEM_VI is not set +# CONFIG_SYSTEM_ZMODEM is not set From fb1d83077047c8e7a810ca26f5c5b953137c48dc Mon Sep 17 00:00:00 2001 From: Gregory Nutt Date: Fri, 17 Jun 2016 08:36:23 -0600 Subject: [PATCH 38/75] Fix some errors in STM32F7 ADC and I2C. Also some errors in STM32-WS configuration --- arch/arm/src/stm32f7/stm32_adc.h | 8 ++++---- arch/arm/src/stm32f7/stm32_i2c.c | 4 ++-- configs/Kconfig | 3 --- configs/stm32f746-ws/nsh/defconfig | 6 ------ 4 files changed, 6 insertions(+), 15 deletions(-) diff --git a/arch/arm/src/stm32f7/stm32_adc.h b/arch/arm/src/stm32f7/stm32_adc.h index 89dd750d80..b26a5206b1 100644 --- a/arch/arm/src/stm32f7/stm32_adc.h +++ b/arch/arm/src/stm32f7/stm32_adc.h @@ -103,19 +103,19 @@ /* Up to 3 ADC interfaces are supported */ -#if STM32_NADC < 4 +#if STM32F7_NADC < 4 # undef CONFIG_STM32F7_ADC4 #endif -#if STM32_NADC < 3 +#if STM32F7_NADC < 3 # undef CONFIG_STM32F7_ADC3 #endif -#if STM32_NADC < 2 +#if STM32F7_NADC < 2 # undef CONFIG_STM32F7_ADC2 #endif -#if STM32_NADC < 1 +#if STM32F7_NADC < 1 # undef CONFIG_STM32F7_ADC1 #endif diff --git a/arch/arm/src/stm32f7/stm32_i2c.c b/arch/arm/src/stm32f7/stm32_i2c.c index e6fa309cd7..6d4793fda7 100644 --- a/arch/arm/src/stm32f7/stm32_i2c.c +++ b/arch/arm/src/stm32f7/stm32_i2c.c @@ -2221,8 +2221,8 @@ static int stm32_i2c_process(FAR struct i2c_master_s *dev, FAR struct i2c_msg_s struct stm32_i2c_inst_s *inst = (struct stm32_i2c_inst_s *)dev; FAR struct stm32_i2c_priv_s *priv = inst->priv; uint32_t status = 0; - uint32_t cr1 = 0; - uint32_t cr2 = 0; + uint32_t cr1; + uint32_t cr2; int errval = 0; int waitrc = 0; diff --git a/configs/Kconfig b/configs/Kconfig index de92e92a6a..2cd2d68c44 100644 --- a/configs/Kconfig +++ b/configs/Kconfig @@ -1009,9 +1009,6 @@ config ARCH_BOARD_STM32F746G_DISCO config ARCH_BOARD_STM32F746_WS bool "Waveshare STM32F746 board" depends on ARCH_CHIP_STM32F746IG - select ARCH_HAVE_LEDS - select ARCH_HAVE_BUTTONS - select ARCH_HAVE_IRQBUTTONS ---help--- Waveshare STM32F746 development board featuring the STM32F746IG MCU. diff --git a/configs/stm32f746-ws/nsh/defconfig b/configs/stm32f746-ws/nsh/defconfig index 75e56a0d01..97b867c160 100644 --- a/configs/stm32f746-ws/nsh/defconfig +++ b/configs/stm32f746-ws/nsh/defconfig @@ -415,11 +415,6 @@ CONFIG_ARCH_BOARD="stm32f746-ws" # # Common Board Options # -CONFIG_ARCH_HAVE_LEDS=y -CONFIG_ARCH_LEDS=y -CONFIG_ARCH_HAVE_BUTTONS=y -# CONFIG_ARCH_BUTTONS is not set -CONFIG_ARCH_HAVE_IRQBUTTONS=y CONFIG_NSH_MMCSDMINOR=0 # @@ -614,7 +609,6 @@ CONFIG_ADC_FIFOSIZE=8 # # LED Support # -# CONFIG_USERLED is not set # CONFIG_RGBLED is not set # CONFIG_PCA9635PW is not set # CONFIG_NCP5623C is not set From 6d1cd731b54a087db7cd88a2d83344d7dcac5189 Mon Sep 17 00:00:00 2001 From: Gregory Nutt Date: Fri, 17 Jun 2016 08:43:22 -0600 Subject: [PATCH 39/75] Eliminate a warning --- graphics/vnc/server/vnc_server.c | 14 ++++++++++++-- 1 file changed, 12 insertions(+), 2 deletions(-) diff --git a/graphics/vnc/server/vnc_server.c b/graphics/vnc/server/vnc_server.c index 7c4aa84ad3..513d10c736 100644 --- a/graphics/vnc/server/vnc_server.c +++ b/graphics/vnc/server/vnc_server.c @@ -248,17 +248,25 @@ int vnc_server(int argc, FAR char *argv[]) if (argc != 2) { + /* In this case the start-up logic will probably hang, waiting for the + * display-related semaphore to be set. + */ + gerr("ERROR: Unexpected number of arguments: %d\n", argc); ret = -EINVAL; - goto errout_with_post; + goto errout_with_hang; } display = atoi(argv[1]); if (display < 0 || display >= RFB_MAX_DISPLAYS) { + /* In this case the start-up logic will probably hang, waiting for the + * display-related semaphore to be set. + */ + gerr("ERROR: Invalid display number: %d\n", display); ret = -EINVAL; - goto errout_with_post; + goto errout_with_hang; } ginfo("Server started for Display %d\n", display); @@ -373,5 +381,7 @@ errout_with_fb: errout_with_post: g_fbstartup[display].result = ret; sem_post(&g_fbstartup[display].fbconnect); + +errout_with_hang: return EXIT_FAILURE; } From 3017bf15b106ee87eeb53eb464782b0c28d6181e Mon Sep 17 00:00:00 2001 From: Gregory Nutt Date: Fri, 17 Jun 2016 09:20:20 -0600 Subject: [PATCH 40/75] Fix some errors in newly includes STM32F7 I2C and ADC drivers --- arch/arm/src/stm32f7/stm32_adc.c | 76 ++++++++++++++++++++++++-------- arch/arm/src/stm32f7/stm32_i2c.c | 3 ++ 2 files changed, 61 insertions(+), 18 deletions(-) diff --git a/arch/arm/src/stm32f7/stm32_adc.c b/arch/arm/src/stm32f7/stm32_adc.c index fa357867c8..c01db1e2b6 100644 --- a/arch/arm/src/stm32f7/stm32_adc.c +++ b/arch/arm/src/stm32f7/stm32_adc.c @@ -42,8 +42,10 @@ #include -#include #include +#include + +#include #include #include #include @@ -166,6 +168,7 @@ struct stm32_dev_s { + FAR const struct adc_callback_s *cb; uint8_t irq; /* Interrupt generated by this ADC block */ uint8_t nchannels; /* Number of channels */ uint8_t cchannels; /* Number of configured channels */ @@ -227,11 +230,14 @@ static void tim_dumpregs(FAR struct stm32_dev_s *priv, static void adc_rccreset(FAR struct stm32_dev_s *priv, bool reset); /* ADC Interrupt Handler */ + static int adc_interrupt(FAR struct adc_dev_s *dev); static int adc123_interrupt(int irq, FAR void *context); /* ADC Driver Methods */ +static int adc_bind(FAR struct adc_dev_s *dev, + FAR const struct adc_callback_s *callback); static void adc_reset(FAR struct adc_dev_s *dev); static int adc_setup(FAR struct adc_dev_s *dev); static void adc_shutdown(FAR struct adc_dev_s *dev); @@ -263,6 +269,7 @@ static void adc_startconv(FAR struct stm32_dev_s *priv, bool enable); static const struct adc_ops_s g_adcops = { + .ao_bind = adc_bind, .ao_reset = adc_reset, .ao_setup = adc_setup, .ao_shutdown = adc_shutdown, @@ -1096,15 +1103,22 @@ static void adc_dmaconvcallback(DMA_HANDLE handle, uint8_t isr, FAR void *arg) FAR struct stm32_dev_s *priv = (FAR struct stm32_dev_s *)dev->ad_priv; int i; - for (i = 0; i < priv->nchannels; i++) - { - adc_receive(dev, priv->current, priv->dmabuffer[priv->current]); - priv->current++; - if (priv->current >= priv->nchannels) - { - /* Restart the conversion sequence from the beginning */ + /* Verify that the upper-half driver has bound its callback functions */ - priv->current = 0; + if (priv->cb != NULL) + { + DEBUGASSERT(priv->cb->au_receive != NULL); + + for (i = 0; i < priv->nchannels; i++) + { + priv->cb->au_receive(dev, priv->current, priv->dmabuffer[priv->current]); + priv->current++; + if (priv->current >= priv->nchannels) + { + /* Restart the conversion sequence from the beginning */ + + priv->current = 0; + } } } @@ -1115,6 +1129,25 @@ static void adc_dmaconvcallback(DMA_HANDLE handle, uint8_t isr, FAR void *arg) } #endif +/**************************************************************************** + * Name: adc_bind + * + * Description: + * Bind the upper-half driver callbacks to the lower-half implementation. This + * must be called early in order to receive ADC event notifications. + * + ****************************************************************************/ + +static int adc_bind(FAR struct adc_dev_s *dev, + FAR const struct adc_callback_s *callback) +{ + FAR struct stm32_dev_s *priv = (FAR struct stm32_dev_s *)dev->ad_priv; + + DEBUGASSERT(priv != NULL); + priv->cb = callback; + return OK; +} + /**************************************************************************** * Name: adc_reset * @@ -1138,7 +1171,7 @@ static void adc_reset(FAR struct adc_dev_s *dev) int ret; #endif - allvdbg("intf: %d\n", priv->intf); + allinfo("intf: %d\n", priv->intf); flags = enter_critical_section(); /* Enable ADC reset state */ @@ -1559,15 +1592,21 @@ static int adc_interrupt(FAR struct adc_dev_s *dev) data = adc_getreg(priv, STM32_ADC_DR_OFFSET) & ADC_DR_RDATA_MASK; - /* Give the ADC data to the ADC driver. adc_receive() accepts 3 - * parameters: - * - * 1) The first is the ADC device instance for this ADC block. - * 2) The second is the channel number for the data, and - * 3) The third is the converted data for the channel. - */ + /* Verify that the upper-half driver has bound its callback functions */ - adc_receive(dev, priv->chanlist[priv->current], data); + if (priv->cb != NULL) + { + /* Give the ADC data to the ADC driver. The ADC receive() method + * accepts 3 parameters: + * + * 1) The first is the ADC device instance for this ADC block. + * 2) The second is the channel number for the data, and + * 3) The third is the converted data for the channel. + */ + + DEBUGASSERT(priv->cb->au_receive != NULL); + priv->cb->au_receive(dev, priv->chanlist[priv->current], data); + } /* Set the channel number of the next channel that will complete * conversion. @@ -1686,6 +1725,7 @@ struct adc_dev_s *stm32_adc_initialize(int intf, FAR const uint8_t *chanlist, DEBUGASSERT(cchannels <= ADC_MAX_SAMPLES); + priv->cb = NULL; priv->cchannels = cchannels; memcpy(priv->chanlist, chanlist, cchannels); diff --git a/arch/arm/src/stm32f7/stm32_i2c.c b/arch/arm/src/stm32f7/stm32_i2c.c index 6d4793fda7..6aa9d2fde6 100644 --- a/arch/arm/src/stm32f7/stm32_i2c.c +++ b/arch/arm/src/stm32f7/stm32_i2c.c @@ -2312,6 +2312,9 @@ static int stm32_i2c_process(FAR struct i2c_master_s *dev, FAR struct i2c_msg_s cr1, cr2,status ); } + UNUSED(cr1); + UNUSED(cr2); + i2cinfo("priv->status: 0x%08x\n", priv->status); /* Check for error status conditions */ From 349748dd7ee2df8b05e623b06db5a7d0e558c20d Mon Sep 17 00:00:00 2001 From: Gregory Nutt Date: Fri, 17 Jun 2016 09:40:09 -0600 Subject: [PATCH 41/75] LPC43xx: Convert *err() to either *info() or add ERROR:, depending on if an error is reported --- arch/arm/src/lpc43xx/Kconfig | 4 +- arch/arm/src/lpc43xx/lpc43_dac.c | 2 +- arch/arm/src/lpc43xx/lpc43_ehci.c | 54 +++++++++---------- arch/arm/src/lpc43xx/lpc43_ethernet.c | 78 +++++++++++++-------------- arch/arm/src/lpc43xx/lpc43_i2c.c | 2 +- arch/arm/src/lpc43xx/lpc43_rit.c | 4 +- arch/arm/src/lpc43xx/lpc43_serial.c | 2 +- arch/arm/src/lpc43xx/lpc43_spi.c | 6 +-- arch/arm/src/lpc43xx/lpc43_ssp.c | 8 +-- arch/arm/src/lpc43xx/lpc43_usb0dev.c | 14 ++--- 10 files changed, 87 insertions(+), 87 deletions(-) diff --git a/arch/arm/src/lpc43xx/Kconfig b/arch/arm/src/lpc43xx/Kconfig index 84868ab13f..e7f830ed2b 100644 --- a/arch/arm/src/lpc43xx/Kconfig +++ b/arch/arm/src/lpc43xx/Kconfig @@ -457,9 +457,9 @@ config LPC43_RMII config LPC43_ETHERNET_REGDEBUG bool "Register-Level Debug" default n - depends on DEBUG_FEATURES + depends on DEBUG_NET_INFO ---help--- - Enable very low-level register access debug. Depends on CONFIG_DEBUG_FEATURES. + Enable very low-level register access debug. Depends on CONFIG_DEBUG_NET_INFO. endmenu # Ethernet MAC configuration endif # LPC43_ETHERNET diff --git a/arch/arm/src/lpc43xx/lpc43_dac.c b/arch/arm/src/lpc43xx/lpc43_dac.c index f14186f7d1..51b7000def 100644 --- a/arch/arm/src/lpc43xx/lpc43_dac.c +++ b/arch/arm/src/lpc43xx/lpc43_dac.c @@ -173,7 +173,7 @@ static int dac_send(FAR struct dac_dev_s *dev, FAR struct dac_msg_s *msg) static int dac_ioctl(FAR struct dac_dev_s *dev, int cmd, unsigned long arg) { - _err("Fix me:Not Implemented\n"); + aerr("ERROR: Fix me:Not Implemented\n"); return 0; } diff --git a/arch/arm/src/lpc43xx/lpc43_ehci.c b/arch/arm/src/lpc43xx/lpc43_ehci.c index a0483accd4..b5ed4414d7 100644 --- a/arch/arm/src/lpc43xx/lpc43_ehci.c +++ b/arch/arm/src/lpc43xx/lpc43_ehci.c @@ -105,7 +105,7 @@ /* Debug options */ -#ifndef CONFIG_DEBUG_FEATURES +#ifndef CONFIG_DEBUG_USB_INFO # undef CONFIG_LPC43_EHCI_REGDEBUG #endif @@ -817,7 +817,7 @@ static uint32_t lpc43_swap32(uint32_t value) static void lpc43_printreg(volatile uint32_t *regaddr, uint32_t regval, bool iswrite) { - _llerr("%08x%s%08x\n", (uintptr_t)regaddr, iswrite ? "<-" : "->", regval); + ullinfo("%08x%s%08x\n", (uintptr_t)regaddr, iswrite ? "<-" : "->", regval); } #endif @@ -868,7 +868,7 @@ static void lpc43_checkreg(volatile uint32_t *regaddr, uint32_t regval, bool isw { /* No.. More than one. */ - _llerr("[repeats %d more times]\n", count); + ullinfo("[repeats %d more times]\n", count); } } @@ -1350,13 +1350,13 @@ static int lpc43_qh_discard(struct lpc43_qh_s *qh) #ifdef CONFIG_LPC43_EHCI_REGDEBUG static void lpc43_qtd_print(struct lpc43_qtd_s *qtd) { - uerr(" QTD[%p]:\n", qtd); - uerr(" hw:\n"); - uerr(" nqp: %08x alt: %08x token: %08x\n", - qtd->hw.nqp, qtd->hw.alt, qtd->hw.token); - uerr(" bpl: %08x %08x %08x %08x %08x\n", - qtd->hw.bpl[0], qtd->hw.bpl[1], qtd->hw.bpl[2], - qtd->hw.bpl[3], qtd->hw.bpl[4]); + uinfo(" QTD[%p]:\n", qtd); + uinfo(" hw:\n"); + uinfo(" nqp: %08x alt: %08x token: %08x\n", + qtd->hw.nqp, qtd->hw.alt, qtd->hw.token); + uinfo(" bpl: %08x %08x %08x %08x %08x\n", + qtd->hw.bpl[0], qtd->hw.bpl[1], qtd->hw.bpl[2], + qtd->hw.bpl[3], qtd->hw.bpl[4]); } #endif @@ -1374,30 +1374,30 @@ static void lpc43_qh_print(struct lpc43_qh_s *qh) struct lpc43_epinfo_s *epinfo; struct ehci_overlay_s *overlay; - uerr("QH[%p]:\n", qh); - uerr(" hw:\n"); - uerr(" hlp: %08x epchar: %08x epcaps: %08x cqp: %08x\n", - qh->hw.hlp, qh->hw.epchar, qh->hw.epcaps, qh->hw.cqp); + uinfo("QH[%p]:\n", qh); + uinfo(" hw:\n"); + uinfo(" hlp: %08x epchar: %08x epcaps: %08x cqp: %08x\n", + qh->hw.hlp, qh->hw.epchar, qh->hw.epcaps, qh->hw.cqp); overlay = &qh->hw.overlay; - uerr(" overlay:\n"); - uerr(" nqp: %08x alt: %08x token: %08x\n", - overlay->nqp, overlay->alt, overlay->token); - uerr(" bpl: %08x %08x %08x %08x %08x\n", - overlay->bpl[0], overlay->bpl[1], overlay->bpl[2], - overlay->bpl[3], overlay->bpl[4]); + uinfo(" overlay:\n"); + uinfo(" nqp: %08x alt: %08x token: %08x\n", + overlay->nqp, overlay->alt, overlay->token); + uinfo(" bpl: %08x %08x %08x %08x %08x\n", + overlay->bpl[0], overlay->bpl[1], overlay->bpl[2], + overlay->bpl[3], overlay->bpl[4]); - uerr(" fqp:\n", qh->fqp); + uinfo(" fqp:\n", qh->fqp); epinfo = qh->epinfo; - uerr(" epinfo[%p]:\n", epinfo); + uinfo(" epinfo[%p]:\n", epinfo); if (epinfo) { - uerr(" EP%d DIR=%s FA=%08x TYPE=%d MaxPacket=%d\n", - epinfo->epno, epinfo->dirin ? "IN" : "OUT", epinfo->devaddr, - epinfo->xfrtype, epinfo->maxpacket); - uerr(" Toggle=%d iocwait=%d speed=%d result=%d\n", - epinfo->toggle, epinfo->iocwait, epinfo->speed, epinfo->result); + uinfo(" EP%d DIR=%s FA=%08x TYPE=%d MaxPacket=%d\n", + epinfo->epno, epinfo->dirin ? "IN" : "OUT", epinfo->devaddr, + epinfo->xfrtype, epinfo->maxpacket); + uinfo(" Toggle=%d iocwait=%d speed=%d result=%d\n", + epinfo->toggle, epinfo->iocwait, epinfo->speed, epinfo->result); } } #endif diff --git a/arch/arm/src/lpc43xx/lpc43_ethernet.c b/arch/arm/src/lpc43xx/lpc43_ethernet.c index 13b2983aaf..9c0022b3c4 100644 --- a/arch/arm/src/lpc43xx/lpc43_ethernet.c +++ b/arch/arm/src/lpc43xx/lpc43_ethernet.c @@ -197,7 +197,7 @@ * enabled. */ -#ifndef CONFIG_DEBUG_FEATURES +#ifndef CONFIG_DEBUG_NET_INFO # undef CONFIG_LPC43_ETHMAC_REGDEBUG #endif @@ -559,7 +559,7 @@ static struct lpc43_ethmac_s g_lpc43ethmac; ****************************************************************************/ /* Register operations ******************************************************/ -#if defined(CONFIG_LPC43_ETHMAC_REGDEBUG) && defined(CONFIG_DEBUG_FEATURES) +#ifdef CONFIG_LPC43_ETHMAC_REGDEBUG static uint32_t lpc43_getreg(uint32_t addr); static void lpc43_putreg(uint32_t val, uint32_t addr); static void lpc43_checksetup(void); @@ -683,7 +683,7 @@ static int lpc43_ethconfig(FAR struct lpc43_ethmac_s *priv); * ****************************************************************************/ -#if defined(CONFIG_LPC43_ETHMAC_REGDEBUG) && defined(CONFIG_DEBUG_FEATURES) +#ifdef CONFIG_LPC43_ETHMAC_REGDEBUG static uint32_t lpc43_getreg(uint32_t addr) { static uint32_t prevaddr = 0; @@ -704,7 +704,7 @@ static uint32_t lpc43_getreg(uint32_t addr) { if (count == 4) { - _llerr("...\n"); + nllinfo("...\n"); } return val; @@ -721,7 +721,7 @@ static uint32_t lpc43_getreg(uint32_t addr) { /* Yes.. then show how many times the value repeated */ - _llerr("[repeats %d more times]\n", count-3); + nllinfo("[repeats %d more times]\n", count-3); } /* Save the new address, value, and count */ @@ -733,7 +733,7 @@ static uint32_t lpc43_getreg(uint32_t addr) /* Show the register value read */ - _llerr("%08x->%08x\n", addr, val); + nllinfo("%08x->%08x\n", addr, val); return val; } #endif @@ -755,12 +755,12 @@ static uint32_t lpc43_getreg(uint32_t addr) * ****************************************************************************/ -#if defined(CONFIG_LPC43_ETHMAC_REGDEBUG) && defined(CONFIG_DEBUG_FEATURES) +#ifdef CONFIG_LPC43_ETHMAC_REGDEBUG static void lpc43_putreg(uint32_t val, uint32_t addr) { /* Show the register value being written */ - _llerr("%08x<-%08x\n", addr, val); + nllinfo("%08x<-%08x\n", addr, val); /* Write the value */ @@ -782,7 +782,7 @@ static void lpc43_putreg(uint32_t val, uint32_t addr) * ****************************************************************************/ -#if defined(CONFIG_LPC43_ETHMAC_REGDEBUG) && defined(CONFIG_DEBUG_FEATURES) +#ifdef CONFIG_LPC43_ETHMAC_REGDEBUG static void lpc43_checksetup(void) { } @@ -1440,7 +1440,7 @@ static int lpc43_recvframe(FAR struct lpc43_ethmac_s *priv) if (!lpc43_isfreebuffer(priv)) { - nllerr("No free buffers\n"); + nllerr("ERROR: No free buffers\n"); return -ENOMEM; } @@ -1547,7 +1547,7 @@ static int lpc43_recvframe(FAR struct lpc43_ethmac_s *priv) * scanning logic, and continue scanning with the next frame. */ - nllerr("DROPPED: RX descriptor errors: %08x\n", rxdesc->rdes0); + nllwarn("WARNING: Dropped, RX descriptor errors: %08x\n", rxdesc->rdes0); lpc43_freesegment(priv, rxcurr, priv->segments); } } @@ -1608,7 +1608,7 @@ static void lpc43_receive(FAR struct lpc43_ethmac_s *priv) if (dev->d_len > CONFIG_NET_ETH_MTU) { - nllerr("DROPPED: Too big: %d\n", dev->d_len); + nllwarn("WARNING: Dropped, Too big: %d\n", dev->d_len); /* Free dropped packet buffer */ if (dev->d_buf) @@ -1727,7 +1727,7 @@ static void lpc43_receive(FAR struct lpc43_ethmac_s *priv) else #endif { - nllerr("DROPPED: Unknown type: %04x\n", BUF->type); + nllwarn("WARNING: Dropped, Unknown type: %04x\n", BUF->type); } /* We are finished with the RX buffer. NOTE: If the buffer is @@ -1975,7 +1975,7 @@ static inline void lpc43_interrupt_process(FAR struct lpc43_ethmac_s *priv) { /* Just let the user know what happened */ - nllerr("Abnormal event(s): %08x\n", dmasr); + nllerr("ERROR: Abnormal event(s): %08x\n", dmasr); /* Clear all pending abnormal events */ @@ -2179,7 +2179,7 @@ static void lpc43_txtimeout_expiry(int argc, uint32_t arg, ...) { FAR struct lpc43_ethmac_s *priv = (FAR struct lpc43_ethmac_s *)arg; - nllerr("Timeout!\n"); + nllinfo("Timeout!\n"); #ifdef CONFIG_NET_NOINTS /* Disable further Ethernet interrupts. This will prevent some race @@ -2381,15 +2381,15 @@ static int lpc43_ifup(struct net_driver_s *dev) int ret; #ifdef CONFIG_NET_IPv4 - nerr("Bringing up: %d.%d.%d.%d\n", - dev->d_ipaddr & 0xff, (dev->d_ipaddr >> 8) & 0xff, - (dev->d_ipaddr >> 16) & 0xff, dev->d_ipaddr >> 24); + ninfo("Bringing up: %d.%d.%d.%d\n", + dev->d_ipaddr & 0xff, (dev->d_ipaddr >> 8) & 0xff, + (dev->d_ipaddr >> 16) & 0xff, dev->d_ipaddr >> 24); #endif #ifdef CONFIG_NET_IPv6 - nerr("Bringing up: %04x:%04x:%04x:%04x:%04x:%04x:%04x:%04x\n", - dev->d_ipv6addr[0], dev->d_ipv6addr[1], dev->d_ipv6addr[2], - dev->d_ipv6addr[3], dev->d_ipv6addr[4], dev->d_ipv6addr[5], - dev->d_ipv6addr[6], dev->d_ipv6addr[7]); + ninfo("Bringing up: %04x:%04x:%04x:%04x:%04x:%04x:%04x:%04x\n", + dev->d_ipv6addr[0], dev->d_ipv6addr[1], dev->d_ipv6addr[2], + dev->d_ipv6addr[3], dev->d_ipv6addr[4], dev->d_ipv6addr[5], + dev->d_ipv6addr[6], dev->d_ipv6addr[7]); #endif /* Configure the Ethernet interface for DMA operation. */ @@ -2435,7 +2435,7 @@ static int lpc43_ifdown(struct net_driver_s *dev) FAR struct lpc43_ethmac_s *priv = (FAR struct lpc43_ethmac_s *)dev->d_private; irqstate_t flags; - nerr("Taking the network down\n"); + ninfo("Taking the network down\n"); /* Disable the Ethernet interrupt */ @@ -3065,7 +3065,7 @@ static int lpc43_phyread(uint16_t phydevaddr, uint16_t phyregaddr, uint16_t *val } } - nerr("MII transfer timed out: phydevaddr: %04x phyregaddr: %04x\n", + nerr("ERROR: MII transfer timed out: phydevaddr: %04x phyregaddr: %04x\n", phydevaddr, phyregaddr); return -ETIMEDOUT; @@ -3124,7 +3124,7 @@ static int lpc43_phywrite(uint16_t phydevaddr, uint16_t phyregaddr, uint16_t val } } - nerr("MII transfer timed out: phydevaddr: %04x phyregaddr: %04x value: %04x\n", + nerr("ERROR: MII transfer timed out: phydevaddr: %04x phyregaddr: %04x value: %04x\n", phydevaddr, phyregaddr, value); return -ETIMEDOUT; @@ -3161,7 +3161,7 @@ static inline int lpc43_dm9161(FAR struct lpc43_ethmac_s *priv) ret = lpc43_phyread(CONFIG_LPC43_PHYADDR, MII_PHYID1, &phyval); if (ret < 0) { - nerr("Failed to read the PHY ID1: %d\n", ret); + nerr("ERROR: Failed to read the PHY ID1: %d\n", ret); return ret; } @@ -3179,7 +3179,7 @@ static inline int lpc43_dm9161(FAR struct lpc43_ethmac_s *priv) ret = lpc43_phyread(CONFIG_LPC43_PHYADDR, 16, &phyval); if (ret < 0) { - nerr("Failed to read the PHY Register 0x10: %d\n", ret); + nerr("ERROR: Failed to read the PHY Register 0x10: %d\n", ret); return ret; } @@ -3236,7 +3236,7 @@ static int lpc43_phyinit(FAR struct lpc43_ethmac_s *priv) ret = lpc43_phywrite(CONFIG_LPC43_PHYADDR, MII_MCR, MII_MCR_RESET); if (ret < 0) { - nerr("Failed to reset the PHY: %d\n", ret); + nerr("ERROR: Failed to reset the PHY: %d\n", ret); return ret; } @@ -3248,7 +3248,7 @@ static int lpc43_phyinit(FAR struct lpc43_ethmac_s *priv) ret = lpc43_phy_boardinitialize(0); if (ret < 0) { - nerr("Failed to initialize the PHY: %d\n", ret); + nerr("ERROR: Failed to initialize the PHY: %d\n", ret); return ret; } #endif @@ -3273,7 +3273,7 @@ static int lpc43_phyinit(FAR struct lpc43_ethmac_s *priv) ret = lpc43_phyread(CONFIG_LPC43_PHYADDR, MII_MSR, &phyval); if (ret < 0) { - nerr("Failed to read the PHY MSR: %d\n", ret); + nerr("ERROR: Failed to read the PHY MSR: %d\n", ret); return ret; } else if ((phyval & MII_MSR_LINKSTATUS) != 0) @@ -3284,7 +3284,7 @@ static int lpc43_phyinit(FAR struct lpc43_ethmac_s *priv) if (timeout >= PHY_RETRY_TIMEOUT) { - nerr("Timed out waiting for link status: %04x\n", phyval); + nerr("ERROR: Timed out waiting for link status: %04x\n", phyval); return -ETIMEDOUT; } @@ -3293,7 +3293,7 @@ static int lpc43_phyinit(FAR struct lpc43_ethmac_s *priv) ret = lpc43_phywrite(CONFIG_LPC43_PHYADDR, MII_MCR, MII_MCR_ANENABLE); if (ret < 0) { - nerr("Failed to enable auto-negotiation: %d\n", ret); + nerr("ERROR: Failed to enable auto-negotiation: %d\n", ret); return ret; } @@ -3304,7 +3304,7 @@ static int lpc43_phyinit(FAR struct lpc43_ethmac_s *priv) ret = lpc43_phyread(CONFIG_LPC43_PHYADDR, MII_MSR, &phyval); if (ret < 0) { - nerr("Failed to read the PHY MSR: %d\n", ret); + nerr("ERROR: Failed to read the PHY MSR: %d\n", ret); return ret; } else if ((phyval & MII_MSR_ANEGCOMPLETE) != 0) @@ -3315,7 +3315,7 @@ static int lpc43_phyinit(FAR struct lpc43_ethmac_s *priv) if (timeout >= PHY_RETRY_TIMEOUT) { - nerr("Timed out waiting for auto-negotiation\n"); + nerr("ERROR: Timed out waiting for auto-negotiation\n"); return -ETIMEDOUT; } @@ -3324,7 +3324,7 @@ static int lpc43_phyinit(FAR struct lpc43_ethmac_s *priv) ret = lpc43_phyread(CONFIG_LPC43_PHYADDR, CONFIG_LPC43_PHYSR, &phyval); if (ret < 0) { - nerr("Failed to read PHY status register\n"); + nerr("ERROR: Failed to read PHY status register\n"); return ret; } @@ -3418,7 +3418,7 @@ static int lpc43_phyinit(FAR struct lpc43_ethmac_s *priv) ret = lpc43_phywrite(CONFIG_LPC43_PHYADDR, MII_MCR, phyval); if (ret < 0) { - nerr("Failed to write the PHY MCR: %d\n", ret); + nerr("ERROR: Failed to write the PHY MCR: %d\n", ret); return ret; } @@ -3434,9 +3434,9 @@ static int lpc43_phyinit(FAR struct lpc43_ethmac_s *priv) #endif #endif - nerr("Duplex: %s Speed: %d MBps\n", - priv->fduplex ? "FULL" : "HALF", - priv->mbps100 ? 100 : 10); + ninfo("Duplex: %s Speed: %d MBps\n", + priv->fduplex ? "FULL" : "HALF", + priv->mbps100 ? 100 : 10); return OK; } diff --git a/arch/arm/src/lpc43xx/lpc43_i2c.c b/arch/arm/src/lpc43xx/lpc43_i2c.c index 4ec260760b..fed79db207 100644 --- a/arch/arm/src/lpc43xx/lpc43_i2c.c +++ b/arch/arm/src/lpc43xx/lpc43_i2c.c @@ -464,7 +464,7 @@ struct i2c_master_s *lpc43_i2cbus_initialize(int port) if (port > 1) { - _err("lpc I2C Only support 0,1\n"); + i2cerr("ERROR: lpc I2C Only suppors ports 0 and 1\n"); return NULL; } diff --git a/arch/arm/src/lpc43xx/lpc43_rit.c b/arch/arm/src/lpc43xx/lpc43_rit.c index 7d68c8f58b..044aeda1ff 100644 --- a/arch/arm/src/lpc43xx/lpc43_rit.c +++ b/arch/arm/src/lpc43xx/lpc43_rit.c @@ -201,8 +201,8 @@ void up_timer_initialize(void) mask_bits++; } - _llerr("mask_bits = %d, mask = %X, ticks_per_int = %d\r\n", - mask_bits, (0xffffffff << (32 - mask_bits)), ticks_per_int); + tmrllinfo("mask_bits = %d, mask = %X, ticks_per_int = %d\r\n", + mask_bits, (0xffffffff << (32 - mask_bits)), ticks_per_int); /* Set the mask and compare value so we get interrupts every * RIT_TIMER_RESOLUTION cycles. diff --git a/arch/arm/src/lpc43xx/lpc43_serial.c b/arch/arm/src/lpc43xx/lpc43_serial.c index e423e2c0da..0644622794 100644 --- a/arch/arm/src/lpc43xx/lpc43_serial.c +++ b/arch/arm/src/lpc43xx/lpc43_serial.c @@ -873,7 +873,7 @@ static int up_interrupt(int irq, void *context) default: { - _err("Unexpected IIR: %02x\n", status); + _llerr("ERROR: Unexpected IIR: %02x\n", status); break; } } diff --git a/arch/arm/src/lpc43xx/lpc43_spi.c b/arch/arm/src/lpc43xx/lpc43_spi.c index e686fb5054..e30b39bf25 100644 --- a/arch/arm/src/lpc43xx/lpc43_spi.c +++ b/arch/arm/src/lpc43xx/lpc43_spi.c @@ -259,7 +259,7 @@ static uint32_t spi_setfrequency(FAR struct spi_dev_s *dev, uint32_t frequency) priv->frequency = frequency; priv->actual = actual; - spierr("Frequency %d->%d\n", frequency, actual); + spiinfo("Frequency %d->%d\n", frequency, actual); return actual; } @@ -421,7 +421,7 @@ static void spi_sndblock(FAR struct spi_dev_s *dev, FAR const void *buffer, size FAR uint8_t *ptr = (FAR uint8_t *)buffer; uint8_t data; - spierr("nwords: %d\n", nwords); + spiinfo("nwords: %d\n", nwords); while (nwords) { /* Write the data to transmitted to the SPI Data Register */ @@ -466,7 +466,7 @@ static void spi_recvblock(FAR struct spi_dev_s *dev, FAR void *buffer, size_t nw { FAR uint8_t *ptr = (FAR uint8_t *)buffer; - spierr("nwords: %d\n", nwords); + spiinfo("nwords: %d\n", nwords); while (nwords) { /* Write some dummy data to the SPI Data Register in order to clock the diff --git a/arch/arm/src/lpc43xx/lpc43_ssp.c b/arch/arm/src/lpc43xx/lpc43_ssp.c index 3deb90d503..49f7c5781f 100644 --- a/arch/arm/src/lpc43xx/lpc43_ssp.c +++ b/arch/arm/src/lpc43xx/lpc43_ssp.c @@ -352,7 +352,7 @@ static uint32_t ssp_setfrequency(FAR struct spi_dev_s *dev, uint32_t frequency) priv->frequency = frequency; priv->actual = actual; - spierr("Frequency %d->%d\n", frequency, actual); + spiinfo("Frequency %d->%d\n", frequency, actual); return actual; } @@ -403,7 +403,7 @@ static void ssp_setmode(FAR struct spi_dev_s *dev, enum spi_mode_e mode) break; default: - spierr("Bad mode: %d\n", mode); + spierr("ERROR: Bad mode: %d\n", mode); DEBUGASSERT(FALSE); return; } @@ -491,7 +491,7 @@ static uint16_t ssp_send(FAR struct spi_dev_s *dev, uint16_t wd) /* Get the value from the RX FIFO and return it */ regval = ssp_getreg(priv, LPC43_SSP_DR_OFFSET); - spierr("%04x->%04x\n", wd, regval); + spiinfo("%04x->%04x\n", wd, regval); return (uint16_t)regval; } @@ -538,7 +538,7 @@ static void ssp_exchange(FAR struct spi_dev_s *dev, FAR const void *txbuffer, /* While there is remaining to be sent (and no synchronization error has occurred) */ - spierr("nwords: %d\n", nwords); + spiinfo("nwords: %d\n", nwords); tx.pv = txbuffer; rx.pv = rxbuffer; diff --git a/arch/arm/src/lpc43xx/lpc43_usb0dev.c b/arch/arm/src/lpc43xx/lpc43_usb0dev.c index af5337bda2..0b595abe43 100644 --- a/arch/arm/src/lpc43xx/lpc43_usb0dev.c +++ b/arch/arm/src/lpc43xx/lpc43_usb0dev.c @@ -361,7 +361,7 @@ struct lpc43_usbdev_s /* Register operations ********************************************************/ -#if defined(CONFIG_LPC43_USBDEV_REGDEBUG) && defined(CONFIG_DEBUG_FEATURES) +#ifdef CONFIG_LPC43_USBDEV_REGDEBUG static uint32_t lpc43_getreg(uint32_t addr); static void lpc43_putreg(uint32_t val, uint32_t addr); #else @@ -501,7 +501,7 @@ static const struct usbdev_ops_s g_devops = * ****************************************************************************/ -#if defined(CONFIG_LPC43_USBDEV_REGDEBUG) && defined(CONFIG_DEBUG_FEATURES) +#ifdef CONFIG_LPC43_USBDEV_REGDEBUG static uint32_t lpc43_getreg(uint32_t addr) { static uint32_t prevaddr = 0; @@ -522,7 +522,7 @@ static uint32_t lpc43_getreg(uint32_t addr) { if (count == 4) { - _llerr("...\n"); + usbllinfo("...\n"); } return val; @@ -539,7 +539,7 @@ static uint32_t lpc43_getreg(uint32_t addr) { /* Yes.. then show how many times the value repeated */ - _llerr("[repeats %d more times]\n", count-3); + usbllinfo("[repeats %d more times]\n", count-3); } /* Save the new address, value, and count */ @@ -551,7 +551,7 @@ static uint32_t lpc43_getreg(uint32_t addr) /* Show the register value read */ - _llerr("%08x->%08x\n", addr, val); + usbllinfo("%08x->%08x\n", addr, val); return val; } #endif @@ -564,12 +564,12 @@ static uint32_t lpc43_getreg(uint32_t addr) * ****************************************************************************/ -#if defined(CONFIG_LPC43_USBDEV_REGDEBUG) && defined(CONFIG_DEBUG_FEATURES) +#ifdef CONFIG_LPC43_USBDEV_REGDEBUG static void lpc43_putreg(uint32_t val, uint32_t addr) { /* Show the register value being written */ - _llerr("%08x<-%08x\n", addr, val); + usbllinfo("%08x<-%08x\n", addr, val); /* Write the value */ From 3077cbfc66a58edb6f5ea77b588023f12a306429 Mon Sep 17 00:00:00 2001 From: Gregory Nutt Date: Fri, 17 Jun 2016 10:56:45 -0600 Subject: [PATCH 42/75] LPC31xx: Convert *err() to either *info() or add ERROR:, depending on if an error is reported --- arch/arm/src/lpc31xx/Kconfig | 10 +++--- arch/arm/src/lpc31xx/lpc31_ehci.c | 54 ++++++++++++++--------------- arch/arm/src/lpc31xx/lpc31_serial.c | 2 +- arch/arm/src/lpc31xx/lpc31_spi.c | 16 ++++----- arch/arm/src/lpc31xx/lpc31_usbdev.c | 14 ++++---- 5 files changed, 48 insertions(+), 48 deletions(-) diff --git a/arch/arm/src/lpc31xx/Kconfig b/arch/arm/src/lpc31xx/Kconfig index e89430ec9b..addeaf16e4 100644 --- a/arch/arm/src/lpc31xx/Kconfig +++ b/arch/arm/src/lpc31xx/Kconfig @@ -243,11 +243,11 @@ config LPC31_USBDEV_DMA config LPC31_USBDEV_REGDEBUG bool "Register level debug" - depends on DEBUG_FEATURES + depends on DEBUG_USB_INFO default n ---help--- Output detailed register-level USB device debug information. Requires - also CONFIG_DEBUG_FEATURES. + also CONFIG_DEBUG_USB_INFO. endmenu # USB device driver controller (DCD) options endif # LPC31_USBOTG && USBDEV @@ -301,7 +301,7 @@ config LPC31_EHCI_PREALLOCATE config LPC31_EHCI_REGDEBUG bool "Enable low-level EHCI register debug" default n - depends on DEBUG_FEATURES + depends on DEBUG_USB_INFO endmenu # USB host controller driver (HCD) options endif # LPC31_USBOTG && USBHOST @@ -310,9 +310,9 @@ menu "SPI device driver options" config LPC31_SPI_REGDEBUG bool "SPI Register level debug" - depends on LPC31_SPI && DEBUG_FEATURES + depends on LPC31_SPI && DEBUG_SPI_INFO default n ---help--- - Output detailed register-level SPI device debug information. Requires also CONFIG_DEBUG_FEATURES. + Output detailed register-level SPI device debug information. Requires also CONFIG_DEBUG_SPI_INFO. endmenu # SPI device driver options diff --git a/arch/arm/src/lpc31xx/lpc31_ehci.c b/arch/arm/src/lpc31xx/lpc31_ehci.c index 1532feddbd..cc9ffb4c13 100644 --- a/arch/arm/src/lpc31xx/lpc31_ehci.c +++ b/arch/arm/src/lpc31xx/lpc31_ehci.c @@ -113,7 +113,7 @@ /* Debug options */ -#ifndef CONFIG_DEBUG_FEATURES +#ifndef CONFIG_DEBUG_USB_INFO # undef CONFIG_LPC31_EHCI_REGDEBUG #endif @@ -826,7 +826,7 @@ static uint32_t lpc31_swap32(uint32_t value) static void lpc31_printreg(volatile uint32_t *regaddr, uint32_t regval, bool iswrite) { - _llerr("%08x%s%08x\n", (uintptr_t)regaddr, iswrite ? "<-" : "->", regval); + ullinfo("%08x%s%08x\n", (uintptr_t)regaddr, iswrite ? "<-" : "->", regval); } #endif @@ -877,7 +877,7 @@ static void lpc31_checkreg(volatile uint32_t *regaddr, uint32_t regval, bool isw { /* No.. More than one. */ - _llerr("[repeats %d more times]\n", count); + ullinfo("[repeats %d more times]\n", count); } } @@ -1456,13 +1456,13 @@ static int lpc31_qh_flush(struct lpc31_qh_s *qh) #ifdef CONFIG_LPC31_EHCI_REGDEBUG static void lpc31_qtd_print(struct lpc31_qtd_s *qtd) { - uerr(" QTD[%p]:\n", qtd); - uerr(" hw:\n"); - uerr(" nqp: %08x alt: %08x token: %08x\n", - qtd->hw.nqp, qtd->hw.alt, qtd->hw.token); - uerr(" bpl: %08x %08x %08x %08x %08x\n", - qtd->hw.bpl[0], qtd->hw.bpl[1], qtd->hw.bpl[2], - qtd->hw.bpl[3], qtd->hw.bpl[4]); + uinfo(" QTD[%p]:\n", qtd); + uinfo(" hw:\n"); + uinfo(" nqp: %08x alt: %08x token: %08x\n", + qtd->hw.nqp, qtd->hw.alt, qtd->hw.token); + uinfo(" bpl: %08x %08x %08x %08x %08x\n", + qtd->hw.bpl[0], qtd->hw.bpl[1], qtd->hw.bpl[2], + qtd->hw.bpl[3], qtd->hw.bpl[4]); } #endif @@ -1480,30 +1480,30 @@ static void lpc31_qh_print(struct lpc31_qh_s *qh) struct lpc31_epinfo_s *epinfo; struct ehci_overlay_s *overlay; - uerr("QH[%p]:\n", qh); - uerr(" hw:\n"); - uerr(" hlp: %08x epchar: %08x epcaps: %08x cqp: %08x\n", - qh->hw.hlp, qh->hw.epchar, qh->hw.epcaps, qh->hw.cqp); + uinfo("QH[%p]:\n", qh); + uinfo(" hw:\n"); + uinfo(" hlp: %08x epchar: %08x epcaps: %08x cqp: %08x\n", + qh->hw.hlp, qh->hw.epchar, qh->hw.epcaps, qh->hw.cqp); overlay = &qh->hw.overlay; - uerr(" overlay:\n"); - uerr(" nqp: %08x alt: %08x token: %08x\n", - overlay->nqp, overlay->alt, overlay->token); - uerr(" bpl: %08x %08x %08x %08x %08x\n", - overlay->bpl[0], overlay->bpl[1], overlay->bpl[2], - overlay->bpl[3], overlay->bpl[4]); + uinfo(" overlay:\n"); + uinfo(" nqp: %08x alt: %08x token: %08x\n", + overlay->nqp, overlay->alt, overlay->token); + uinfo(" bpl: %08x %08x %08x %08x %08x\n", + overlay->bpl[0], overlay->bpl[1], overlay->bpl[2], + overlay->bpl[3], overlay->bpl[4]); - uerr(" fqp:\n", qh->fqp); + uinfo(" fqp:\n", qh->fqp); epinfo = qh->epinfo; - uerr(" epinfo[%p]:\n", epinfo); + uinfo(" epinfo[%p]:\n", epinfo); if (epinfo) { - uerr(" EP%d DIR=%s FA=%08x TYPE=%d MaxPacket=%d\n", - epinfo->epno, epinfo->dirin ? "IN" : "OUT", epinfo->devaddr, - epinfo->xfrtype, epinfo->maxpacket); - uerr(" Toggle=%d iocwait=%d speed=%d result=%d\n", - epinfo->toggle, epinfo->iocwait, epinfo->speed, epinfo->result); + uinfo(" EP%d DIR=%s FA=%08x TYPE=%d MaxPacket=%d\n", + epinfo->epno, epinfo->dirin ? "IN" : "OUT", epinfo->devaddr, + epinfo->xfrtype, epinfo->maxpacket); + uinfo(" Toggle=%d iocwait=%d speed=%d result=%d\n", + epinfo->toggle, epinfo->iocwait, epinfo->speed, epinfo->result); } } #endif diff --git a/arch/arm/src/lpc31xx/lpc31_serial.c b/arch/arm/src/lpc31xx/lpc31_serial.c index b46c0598fc..bf5ac8cd58 100644 --- a/arch/arm/src/lpc31xx/lpc31_serial.c +++ b/arch/arm/src/lpc31xx/lpc31_serial.c @@ -560,7 +560,7 @@ static int up_interrupt(int irq, void *context) default: { - _err("Unexpected IIR: %02x\n", status); + _err("ERROR: Unexpected IIR: %02x\n", status); break; } } diff --git a/arch/arm/src/lpc31xx/lpc31_spi.c b/arch/arm/src/lpc31xx/lpc31_spi.c index 074bbe2b7d..88d8ea6c00 100644 --- a/arch/arm/src/lpc31xx/lpc31_spi.c +++ b/arch/arm/src/lpc31xx/lpc31_spi.c @@ -66,7 +66,7 @@ * CONFIG_DEBUG_FEATURES must also be defined */ -#ifndef CONFIG_DEBUG_FEATURES +#ifndef CONFIG_DEBUG_SPI_INFO # undef CONFIG_LPC31_SPI_REGDEBUG #endif @@ -207,7 +207,7 @@ static bool spi_checkreg(bool wr, uint32_t value, uint32_t address) { if (g_ntimes > 0) { - _llerr("...[Repeats %d times]...\n", g_ntimes); + spillinfo("...[Repeats %d times]...\n", g_ntimes); } g_wrlast = wr; @@ -239,7 +239,7 @@ static void spi_putreg(uint32_t value, uint32_t address) { if (spi_checkreg(true, value, address)) { - _llerr("%08x<-%08x\n", address, value); + spillinfo("%08x<-%08x\n", address, value); } putreg32(value, address); } @@ -265,7 +265,7 @@ static uint32_t spi_getreg(uint32_t address) uint32_t value = getreg32(address); if (spi_checkreg(false, value, address)) { - _llerr("%08x->%08x\n", address, value); + spillinfo("%08x->%08x\n", address, value); } return value; } @@ -921,10 +921,10 @@ FAR struct spi_dev_s *lpc31_spibus_initialize(int port) */ #ifdef CONFIG_LPC31_SPI_REGDEBUG - _llerr("PINS: %08x MODE0: %08x MODE1: %08x\n", - spi_getreg(LPC31_IOCONFIG_SPI_PINS), - spi_getreg(LPC31_IOCONFIG_SPI_MODE0), - spi_getreg(LPC31_IOCONFIG_SPI_MODE1)); + spiinfo("PINS: %08x MODE0: %08x MODE1: %08x\n", + spi_getreg(LPC31_IOCONFIG_SPI_PINS), + spi_getreg(LPC31_IOCONFIG_SPI_MODE0), + spi_getreg(LPC31_IOCONFIG_SPI_MODE1)); #endif /* Enable SPI clocks */ diff --git a/arch/arm/src/lpc31xx/lpc31_usbdev.c b/arch/arm/src/lpc31xx/lpc31_usbdev.c index f75eb1aa52..a596915536 100644 --- a/arch/arm/src/lpc31xx/lpc31_usbdev.c +++ b/arch/arm/src/lpc31xx/lpc31_usbdev.c @@ -343,7 +343,7 @@ struct lpc31_usbdev_s /* Register operations ********************************************************/ -#if defined(CONFIG_LPC31_USBDEV_REGDEBUG) && defined(CONFIG_DEBUG_FEATURES) +#ifdef CONFIG_LPC31_USBDEV_REGDEBUG static uint32_t lpc31_getreg(uint32_t addr); static void lpc31_putreg(uint32_t val, uint32_t addr); #else @@ -480,7 +480,7 @@ static const struct usbdev_ops_s g_devops = * ****************************************************************************/ -#if defined(CONFIG_LPC31_USBDEV_REGDEBUG) && defined(CONFIG_DEBUG_FEATURES) +#ifdef CONFIG_LPC31_USBDEV_REGDEBUG static uint32_t lpc31_getreg(uint32_t addr) { static uint32_t prevaddr = 0; @@ -501,7 +501,7 @@ static uint32_t lpc31_getreg(uint32_t addr) { if (count == 4) { - _llerr("...\n"); + ullinfo("...\n"); } return val; @@ -518,7 +518,7 @@ static uint32_t lpc31_getreg(uint32_t addr) { /* Yes.. then show how many times the value repeated */ - _llerr("[repeats %d more times]\n", count-3); + ullinfo("[repeats %d more times]\n", count-3); } /* Save the new address, value, and count */ @@ -530,7 +530,7 @@ static uint32_t lpc31_getreg(uint32_t addr) /* Show the register value read */ - _llerr("%08x->%08x\n", addr, val); + ullinfo("%08x->%08x\n", addr, val); return val; } #endif @@ -543,12 +543,12 @@ static uint32_t lpc31_getreg(uint32_t addr) * ****************************************************************************/ -#if defined(CONFIG_LPC31_USBDEV_REGDEBUG) && defined(CONFIG_DEBUG_FEATURES) +#ifdef CONFIG_LPC31_USBDEV_REGDEBUG static void lpc31_putreg(uint32_t val, uint32_t addr) { /* Show the register value being written */ - _llerr("%08x<-%08x\n", addr, val); + ullinfo("%08x<-%08x\n", addr, val); /* Write the value */ From 1edc9979226ad1566ec1e4d28e86af1fdd787254 Mon Sep 17 00:00:00 2001 From: Gregory Nutt Date: Fri, 17 Jun 2016 11:00:43 -0600 Subject: [PATCH 43/75] LPC2378/LPC214x: Convert *err() to either *info() or add ERROR:, depending on if an error is reported --- arch/arm/src/lpc214x/lpc214x_serial.c | 2 +- arch/arm/src/lpc214x/lpc214x_usbdev.c | 14 +++++++------- arch/arm/src/lpc2378/lpc23xx_i2c.c | 2 +- arch/arm/src/lpc2378/lpc23xx_serial.c | 2 +- arch/arm/src/lpc2378/lpc23xx_spi.c | 6 +++--- 5 files changed, 13 insertions(+), 13 deletions(-) diff --git a/arch/arm/src/lpc214x/lpc214x_serial.c b/arch/arm/src/lpc214x/lpc214x_serial.c index 1f699f5129..e1b3511f9c 100644 --- a/arch/arm/src/lpc214x/lpc214x_serial.c +++ b/arch/arm/src/lpc214x/lpc214x_serial.c @@ -549,7 +549,7 @@ static int up_interrupt(int irq, void *context) default: { - _err("Unexpected IIR: %02x\n", status); + _err("ERROR: Unexpected IIR: %02x\n", status); break; } } diff --git a/arch/arm/src/lpc214x/lpc214x_usbdev.c b/arch/arm/src/lpc214x/lpc214x_usbdev.c index e9ea74f088..7239878148 100644 --- a/arch/arm/src/lpc214x/lpc214x_usbdev.c +++ b/arch/arm/src/lpc214x/lpc214x_usbdev.c @@ -382,7 +382,7 @@ struct lpc214x_usbdev_s /* Register operations ********************************************************/ -#if defined(CONFIG_LPC214X_USBDEV_REGDEBUG) && defined(CONFIG_DEBUG_FEATURES) +#ifdef CONFIG_LPC214X_USBDEV_REGDEBUG static uint32_t lpc214x_getreg(uint32_t addr); static void lpc214x_putreg(uint32_t val, uint32_t addr); #else @@ -518,7 +518,7 @@ static const struct usbdev_ops_s g_devops = * ****************************************************************************/ -#if defined(CONFIG_LPC214X_USBDEV_REGDEBUG) && defined(CONFIG_DEBUG_FEATURES) +#ifdef CONFIG_LPC214X_USBDEV_REGDEBUG static uint32_t lpc214x_getreg(uint32_t addr) { static uint32_t prevaddr = 0; @@ -539,7 +539,7 @@ static uint32_t lpc214x_getreg(uint32_t addr) { if (count == 4) { - _llerr("...\n"); + ullinfo("...\n"); } return val; @@ -556,7 +556,7 @@ static uint32_t lpc214x_getreg(uint32_t addr) { /* Yes.. then show how many times the value repeated */ - _llerr("[repeats %d more times]\n", count-3); + ullinfo("[repeats %d more times]\n", count-3); } /* Save the new address, value, and count */ @@ -568,7 +568,7 @@ static uint32_t lpc214x_getreg(uint32_t addr) /* Show the register value read */ - _llerr("%08x->%08x\n", addr, val); + ullinfo("%08x->%08x\n", addr, val); return val; } #endif @@ -581,12 +581,12 @@ static uint32_t lpc214x_getreg(uint32_t addr) * ****************************************************************************/ -#if defined(CONFIG_LPC214X_USBDEV_REGDEBUG) && defined(CONFIG_DEBUG_FEATURES) +#ifdef CONFIG_LPC214X_USBDEV_REGDEBUG static void lpc214x_putreg(uint32_t val, uint32_t addr) { /* Show the register value being written */ - _llerr("%08x<-%08x\n", addr, val); + ullinfo("%08x<-%08x\n", addr, val); /* Write the value */ diff --git a/arch/arm/src/lpc2378/lpc23xx_i2c.c b/arch/arm/src/lpc2378/lpc23xx_i2c.c index 6932e93210..1c281e8857 100644 --- a/arch/arm/src/lpc2378/lpc23xx_i2c.c +++ b/arch/arm/src/lpc2378/lpc23xx_i2c.c @@ -490,7 +490,7 @@ struct i2c_master_s *lpc2378_i2cbus_initialize(int port) if (port > 1) { - _err("lpc I2C Only support 0,1\n"); + l2cerr("ERROR: lpc I2C Only support 0,1\n"); return NULL; } diff --git a/arch/arm/src/lpc2378/lpc23xx_serial.c b/arch/arm/src/lpc2378/lpc23xx_serial.c index 50aaa662a6..48e322ec15 100644 --- a/arch/arm/src/lpc2378/lpc23xx_serial.c +++ b/arch/arm/src/lpc2378/lpc23xx_serial.c @@ -667,7 +667,7 @@ static int up_interrupt(int irq, void *context) default: { - _err("Unexpected IIR: %02x\n", status); + _err("ERROR: Unexpected IIR: %02x\n", status); break; } } diff --git a/arch/arm/src/lpc2378/lpc23xx_spi.c b/arch/arm/src/lpc2378/lpc23xx_spi.c index 95b0cdcd1d..cf95f63a8b 100644 --- a/arch/arm/src/lpc2378/lpc23xx_spi.c +++ b/arch/arm/src/lpc2378/lpc23xx_spi.c @@ -274,7 +274,7 @@ static uint32_t spi_setfrequency(FAR struct spi_dev_s *dev, uint32_t frequency) priv->frequency = frequency; priv->actual = actual; - spierr("Frequency %d->%d\n", frequency, actual); + spiinfo("Frequency %d->%d\n", frequency, actual); return actual; } @@ -438,7 +438,7 @@ static void spi_sndblock(FAR struct spi_dev_s *dev, FAR const void *buffer, size FAR uint8_t *ptr = (FAR uint8_t *)buffer; uint8_t data; - spierr("nwords: %d\n", nwords); + spiinfo("nwords: %d\n", nwords); while (nwords) { /* Write the data to transmitted to the SPI Data Register */ @@ -483,7 +483,7 @@ static void spi_recvblock(FAR struct spi_dev_s *dev, FAR void *buffer, size_t nw { FAR uint8_t *ptr = (FAR uint8_t *)buffer; - spierr("nwords: %d\n", nwords); + spiinfo("nwords: %d\n", nwords); while (nwords) { /* Write some dummy data to the SPI Data Register in order to clock the From 7ba7de304146414ba9b074b10b2eaf4216014551 Mon Sep 17 00:00:00 2001 From: Gregory Nutt Date: Fri, 17 Jun 2016 11:26:31 -0600 Subject: [PATCH 44/75] LPC11xx/LPC17xx: Convert *err() to either *info() or add ERROR:, depending on if an error is reported --- arch/arm/src/lpc11xx/lpc11_i2c.c | 2 +- arch/arm/src/lpc11xx/lpc11_serial.c | 2 +- arch/arm/src/lpc11xx/lpc11_spi.c | 6 +- arch/arm/src/lpc17xx/Kconfig | 14 ++-- arch/arm/src/lpc17xx/lpc17_can.c | 18 ++--- arch/arm/src/lpc17xx/lpc17_dac.c | 4 +- arch/arm/src/lpc17xx/lpc17_ethernet.c | 96 +++++++++++++-------------- arch/arm/src/lpc17xx/lpc17_gpdma.c | 80 +++++++++++----------- arch/arm/src/lpc17xx/lpc17_gpdma.h | 8 +-- arch/arm/src/lpc17xx/lpc17_i2c.c | 2 +- arch/arm/src/lpc17xx/lpc17_lcd.c | 62 ++++++++--------- arch/arm/src/lpc17xx/lpc17_mcpwm.c | 2 +- arch/arm/src/lpc17xx/lpc17_pwm.c | 2 +- arch/arm/src/lpc17xx/lpc17_sdcard.c | 14 ++-- arch/arm/src/lpc17xx/lpc17_serial.c | 2 +- arch/arm/src/lpc17xx/lpc17_spi.c | 6 +- arch/arm/src/lpc17xx/lpc17_usbdev.c | 9 ++- arch/arm/src/lpc17xx/lpc17_usbhost.c | 30 +++++---- 18 files changed, 183 insertions(+), 176 deletions(-) diff --git a/arch/arm/src/lpc11xx/lpc11_i2c.c b/arch/arm/src/lpc11xx/lpc11_i2c.c index 46011f7508..184290a602 100644 --- a/arch/arm/src/lpc11xx/lpc11_i2c.c +++ b/arch/arm/src/lpc11xx/lpc11_i2c.c @@ -485,7 +485,7 @@ struct i2c_master_s *lpc11_i2cbus_initialize(int port) if (port > 1) { - _err("lpc I2C Only support 0,1\n"); + i2cerr("ERROR: LPC I2C only supports ports 0 and 1\n"); return NULL; } diff --git a/arch/arm/src/lpc11xx/lpc11_serial.c b/arch/arm/src/lpc11xx/lpc11_serial.c index b9365615da..55c05ac517 100644 --- a/arch/arm/src/lpc11xx/lpc11_serial.c +++ b/arch/arm/src/lpc11xx/lpc11_serial.c @@ -638,7 +638,7 @@ static int up_interrupt(int irq, void *context) default: { - _err("Unexpected IIR: %02x\n", status); + _err("ERROR: Unexpected IIR: %02x\n", status); break; } } diff --git a/arch/arm/src/lpc11xx/lpc11_spi.c b/arch/arm/src/lpc11xx/lpc11_spi.c index db01c47ace..c3f9157fe5 100644 --- a/arch/arm/src/lpc11xx/lpc11_spi.c +++ b/arch/arm/src/lpc11xx/lpc11_spi.c @@ -272,7 +272,7 @@ static uint32_t spi_setfrequency(FAR struct spi_dev_s *dev, priv->frequency = frequency; priv->actual = actual; - spierr("Frequency %d->%d\n", frequency, actual); + spiinfo("Frequency %d->%d\n", frequency, actual); return actual; } @@ -436,7 +436,7 @@ static void spi_sndblock(FAR struct spi_dev_s *dev, FAR const void *buffer, FAR uint8_t *ptr = (FAR uint8_t *)buffer; uint8_t data; - spierr("nwords: %d\n", nwords); + spiinfo("nwords: %d\n", nwords); while (nwords) { /* Write the data to transmitted to the SPI Data Register */ @@ -483,7 +483,7 @@ static void spi_recvblock(FAR struct spi_dev_s *dev, FAR void *buffer, { FAR uint8_t *ptr = (FAR uint8_t *)buffer; - spierr("nwords: %d\n", nwords); + spiinfo("nwords: %d\n", nwords); while (nwords) { /* Write some dummy data to the SPI Data Register in order to clock the diff --git a/arch/arm/src/lpc17xx/Kconfig b/arch/arm/src/lpc17xx/Kconfig index 7aea897ba0..abfd205fed 100644 --- a/arch/arm/src/lpc17xx/Kconfig +++ b/arch/arm/src/lpc17xx/Kconfig @@ -704,12 +704,12 @@ config NET_WOL ---help--- Enable Wake-up on Lan (not fully implemented). -config NET_REGDEBUG +config LPC17_NET_REGDEBUG bool "Ethernet register-level debug" - depends on DEBUG_FEATURES + depends on DEBUG_NET_INFO default n ---help--- - Enable low level register debug. Also needs CONFIG_DEBUG_FEATURES. + Enable low level register debug. Also needs CONFIG_DEBUG_NET_INFO. config NET_HASH bool "Hashing" @@ -901,11 +901,11 @@ config LPC17_USBDEV_NOLED config LPC17_USBDEV_REGDEBUG bool "Register level debug" - depends on DEBUG_FEATURES + depends on DEBUG_USB_INFO default n ---help--- Output detailed register-level USB device debug information. Requires - also CONFIG_DEBUG_FEATURES. + also CONFIG_DEBUG_USB_INFO. endmenu @@ -978,10 +978,10 @@ config USBHOST_ISOC_DISABLE config LPC17_USBHOST_REGDEBUG bool "Register level debug" - depends on DEBUG_FEATURES + depends on DEBUG_USB_INFO default n ---help--- Output detailed register-level USB host debug information. Requires - also CONFIG_DEBUG_FEATURES. + also CONFIG_DEBUG_USB_INFO. endmenu diff --git a/arch/arm/src/lpc17xx/lpc17_can.c b/arch/arm/src/lpc17xx/lpc17_can.c index 802fe89ae9..0c2ea65c7e 100644 --- a/arch/arm/src/lpc17xx/lpc17_can.c +++ b/arch/arm/src/lpc17xx/lpc17_can.c @@ -308,7 +308,7 @@ static void can_printreg(uint32_t addr, uint32_t value) { if (count == 4) { - _llerr("...\n"); + canllinfo("...\n"); } return; @@ -325,7 +325,7 @@ static void can_printreg(uint32_t addr, uint32_t value) { /* Yes.. then show how many times the value repeated */ - _llerr("[repeats %d more times]\n", count-3); + canllinfo("[repeats %d more times]\n", count-3); } /* Save the new address, value, and count */ @@ -337,7 +337,7 @@ static void can_printreg(uint32_t addr, uint32_t value) /* Show the register value read */ - _llerr("%08x->%08x\n", addr, value); + canllinfo("%08x->%08x\n", addr, value); } #endif @@ -398,7 +398,7 @@ static void can_putreg(struct up_dev_s *priv, int offset, uint32_t value) /* Show the register value being written */ - _llerr("%08x<-%08x\n", addr, value); + canllinfo("%08x<-%08x\n", addr, value); /* Write the value */ @@ -458,7 +458,7 @@ static void can_putcommon(uint32_t addr, uint32_t value) { /* Show the register value being written */ - _llerr("%08x<-%08x\n", addr, value); + canllinfo("%08x<-%08x\n", addr, value); /* Write the value */ @@ -681,7 +681,7 @@ static void can_txint(FAR struct can_dev_s *dev, bool enable) static int can_ioctl(FAR struct can_dev_s *dev, int cmd, unsigned long arg) { - _err("Fix me:Not Implemented\n"); + canerr("ERROR: Fix me -- Not Implemented\n"); return 0; } @@ -701,7 +701,7 @@ static int can_ioctl(FAR struct can_dev_s *dev, int cmd, unsigned long arg) static int can_remoterequest(FAR struct can_dev_s *dev, uint16_t id) { - _err("Fix me:Not Implemented\n"); + canerr("ERROR: Fix me -- Not Implemented\n"); return 0; } @@ -862,7 +862,7 @@ static int can_send(FAR struct can_dev_s *dev, FAR struct can_msg_s *msg) } else { - canerr("No available transmission buffer, SR: %08x\n", regval); + canerr("ERROR: No available transmission buffer, SR: %08x\n", regval); ret = -EBUSY; } @@ -1283,7 +1283,7 @@ FAR struct can_dev_s *lpc17_caninitialize(int port) else #endif { - canerr("Unsupported port: %d\n", port); + canerr("ERROR: Unsupported port: %d\n", port); leave_critical_section(flags); return NULL; } diff --git a/arch/arm/src/lpc17xx/lpc17_dac.c b/arch/arm/src/lpc17xx/lpc17_dac.c index d936aa0fc5..003d609266 100644 --- a/arch/arm/src/lpc17xx/lpc17_dac.c +++ b/arch/arm/src/lpc17xx/lpc17_dac.c @@ -170,9 +170,9 @@ static int dac_send(FAR struct dac_dev_s *dev, FAR struct dac_msg_s *msg) /* All ioctl calls will be routed through this method */ -static int dac_ioctl(FAR struct dac_dev_s *dev, int cmd, unsigned long arg) +static int dac_ioctl(FAR struct dac_dev_s *dev, int cmd, unsigned long arg) { - _err("Fix me:Not Implemented\n"); + aerr("ERROR: Fix me -- Not Implemented\n"); return 0; } diff --git a/arch/arm/src/lpc17xx/lpc17_ethernet.c b/arch/arm/src/lpc17xx/lpc17_ethernet.c index a7a28a2616..d3f884b976 100644 --- a/arch/arm/src/lpc17xx/lpc17_ethernet.c +++ b/arch/arm/src/lpc17xx/lpc17_ethernet.c @@ -127,17 +127,17 @@ #endif /* Debug Configuration *****************************************************/ -/* Register debug -- can only happen of CONFIG_DEBUG_FEATURES is selected */ +/* Register debug -- can only happen of CONFIG_DEBUG_NET_INFO is selected */ -#ifndef CONFIG_DEBUG_FEATURES -# undef CONFIG_NET_REGDEBUG +#ifndef CONFIG_DEBUG_NET_INFO +# undef CONFIG_LPC17_NET_REGDEBUG #endif /* CONFIG_NET_DUMPPACKET will dump the contents of each packet to the * console. */ -#ifndef CONFIG_DEBUG_FEATURES +#ifndef CONFIG_DEBUG_NET_INFO # undef CONFIG_NET_DUMPPACKET #endif @@ -301,7 +301,7 @@ static const uint16_t g_enetpins[GPIO_NENET_PINS] = /* Register operations */ -#ifdef CONFIG_NET_REGDEBUG +#ifdef CONFIG_LPC17_NET_REGDEBUG static void lpc17_printreg(uint32_t addr, uint32_t val, bool iswrite); static void lpc17_checkreg(uint32_t addr, uint32_t val, bool iswrite); static uint32_t lpc17_getreg(uint32_t addr); @@ -365,7 +365,7 @@ static int lpc17_rmmac(struct net_driver_s *dev, const uint8_t *mac); /* Initialization functions */ -#if defined(CONFIG_NET_REGDEBUG) && defined(CONFIG_DEBUG_GPIO_INFO) +#if defined(CONFIG_LPC17_NET_REGDEBUG) && defined(CONFIG_DEBUG_GPIO_INFO) static void lpc17_showpins(void); #else # define lpc17_showpins() @@ -374,7 +374,7 @@ static void lpc17_showpins(void); /* PHY initialization functions */ #ifdef LPC17_HAVE_PHY -# ifdef CONFIG_NET_REGDEBUG +# ifdef CONFIG_LPC17_NET_REGDEBUG static void lpc17_showmii(uint8_t phyaddr, const char *msg); # else # define lpc17_showmii(phyaddr,msg) @@ -412,10 +412,10 @@ static void lpc17_ethreset(struct lpc17_driver_s *priv); * ****************************************************************************/ -#ifdef CONFIG_NET_REGDEBUG +#ifdef CONFIG_LPC17_NET_REGDEBUG static void lpc17_printreg(uint32_t addr, uint32_t val, bool iswrite) { - _err("%08x%s%08x\n", addr, iswrite ? "<-" : "->", val); + ninfo("%08x%s%08x\n", addr, iswrite ? "<-" : "->", val); } #endif @@ -427,7 +427,7 @@ static void lpc17_printreg(uint32_t addr, uint32_t val, bool iswrite) * ****************************************************************************/ -#ifdef CONFIG_NET_REGDEBUG +#ifdef CONFIG_LPC17_NET_REGDEBUG static void lpc17_checkreg(uint32_t addr, uint32_t val, bool iswrite) { static uint32_t prevaddr = 0; @@ -465,7 +465,7 @@ static void lpc17_checkreg(uint32_t addr, uint32_t val, bool iswrite) { /* No.. More than one. */ - _err("[repeats %d more times]\n", count); + ninfo("[repeats %d more times]\n", count); } } @@ -491,7 +491,7 @@ static void lpc17_checkreg(uint32_t addr, uint32_t val, bool iswrite) * ****************************************************************************/ -#ifdef CONFIG_NET_REGDEBUG +#ifdef CONFIG_LPC17_NET_REGDEBUG static uint32_t lpc17_getreg(uint32_t addr) { /* Read the value from the register */ @@ -513,7 +513,7 @@ static uint32_t lpc17_getreg(uint32_t addr) * ****************************************************************************/ -#ifdef CONFIG_NET_REGDEBUG +#ifdef CONFIG_LPC17_NET_REGDEBUG static void lpc17_putreg(uint32_t val, uint32_t addr) { /* Check if we need to print this value */ @@ -837,7 +837,7 @@ static void lpc17_rxdone_process(struct lpc17_driver_s *priv) if ((*rxstat & RXSTAT_INFO_ERROR) != 0) { - nllerr("Error. considx: %08x prodidx: %08x rxstat: %08x\n", + nllerr("ERROR: considx: %08x prodidx: %08x rxstat: %08x\n", considx, prodidx, *rxstat); NETDEV_RXERRORS(&priv->lp_dev); } @@ -850,21 +850,21 @@ static void lpc17_rxdone_process(struct lpc17_driver_s *priv) /* else */ if (pktlen > CONFIG_NET_ETH_MTU + CONFIG_NET_GUARDSIZE) { - nllerr("Too big. considx: %08x prodidx: %08x pktlen: %d rxstat: %08x\n", - considx, prodidx, pktlen, *rxstat); + nllwarn("WARNING: Too big. considx: %08x prodidx: %08x pktlen: %d rxstat: %08x\n", + considx, prodidx, pktlen, *rxstat); NETDEV_RXERRORS(&priv->lp_dev); } else if ((*rxstat & RXSTAT_INFO_LASTFLAG) == 0) { - nllerr("Fragment. considx: %08x prodidx: %08x pktlen: %d rxstat: %08x\n", - considx, prodidx, pktlen, *rxstat); + nllinfo("Fragment. considx: %08x prodidx: %08x pktlen: %d rxstat: %08x\n", + considx, prodidx, pktlen, *rxstat); NETDEV_RXFRAGMENTS(&priv->lp_dev); fragment = true; } else if (fragment) { - nllerr("Last fragment. considx: %08x prodidx: %08x pktlen: %d rxstat: %08x\n", - considx, prodidx, pktlen, *rxstat); + nllinfo("Last fragment. considx: %08x prodidx: %08x pktlen: %d rxstat: %08x\n", + considx, prodidx, pktlen, *rxstat); NETDEV_RXFRAGMENTS(&priv->lp_dev); fragment = false; } @@ -1202,13 +1202,13 @@ static int lpc17_interrupt(int irq, void *context) { if ((status & ETH_INT_RXOVR) != 0) { - nllerr("RX Overrun. status: %08x\n", status); + nllerr("ERROR: RX Overrun. status: %08x\n", status); NETDEV_RXERRORS(&priv->lp_dev); } if ((status & ETH_INT_TXUNR) != 0) { - nllerr("TX Underrun. status: %08x\n", status); + nllerr("ERROR: TX Underrun. status: %08x\n", status); NETDEV_TXERRORS(&priv->lp_dev); } @@ -1229,7 +1229,7 @@ static int lpc17_interrupt(int irq, void *context) if ((status & ETH_INT_RXERR) != 0) { - nllerr("RX Error. status: %08x\n", status); + nllerr("ERROR: RX ERROR: status: %08x\n", status); NETDEV_RXERRORS(&priv->lp_dev); } @@ -1281,7 +1281,7 @@ static int lpc17_interrupt(int irq, void *context) if ((status & ETH_INT_TXERR) != 0) { - nllerr("TX Error. status: %08x\n", status); + nllerr("ERROR: TX ERROR: status: %08x\n", status); NETDEV_TXERRORS(&priv->lp_dev); } @@ -1720,9 +1720,9 @@ static int lpc17_ifup(struct net_driver_s *dev) uint32_t regval; int ret; - nerr("Bringing up: %d.%d.%d.%d\n", - dev->d_ipaddr & 0xff, (dev->d_ipaddr >> 8) & 0xff, - (dev->d_ipaddr >> 16) & 0xff, dev->d_ipaddr >> 24); + ninfo("Bringing up: %d.%d.%d.%d\n", + dev->d_ipaddr & 0xff, (dev->d_ipaddr >> 8) & 0xff, + (dev->d_ipaddr >> 16) & 0xff, dev->d_ipaddr >> 24); /* Reset the Ethernet controller (again) */ @@ -1733,7 +1733,7 @@ static int lpc17_ifup(struct net_driver_s *dev) ret = lpc17_phyinit(priv); if (ret != 0) { - nerr("lpc17_phyinit failed: %d\n", ret); + nerr("ERROR: lpc17_phyinit failed: %d\n", ret); return ret; } @@ -2292,7 +2292,7 @@ static int lpc17_rmmac(struct net_driver_s *dev, const uint8_t *mac) * ****************************************************************************/ -#if defined(CONFIG_NET_REGDEBUG) && defined(CONFIG_DEBUG_GPIO_INFO) +#if defined(CONFIG_LPC17_NET_REGDEBUG) && defined(CONFIG_DEBUG_GPIO_INFO) static void lpc17_showpins(void) { lpc17_dumpgpio(GPIO_PORT1 | GPIO_PIN0, "P1[1-15]"); @@ -2316,17 +2316,17 @@ static void lpc17_showpins(void) * ****************************************************************************/ -#if defined(CONFIG_NET_REGDEBUG) && defined(LPC17_HAVE_PHY) +#if defined(CONFIG_LPC17_NET_REGDEBUG) && defined(LPC17_HAVE_PHY) static void lpc17_showmii(uint8_t phyaddr, const char *msg) { - _err("PHY " LPC17_PHYNAME ": %s\n", msg); - _err(" MCR: %04x\n", lpc17_phyread(phyaddr, MII_MCR)); - _err(" MSR: %04x\n", lpc17_phyread(phyaddr, MII_MSR)); - _err(" ADVERTISE: %04x\n", lpc17_phyread(phyaddr, MII_ADVERTISE)); - _err(" LPA: %04x\n", lpc17_phyread(phyaddr, MII_LPA)); - _err(" EXPANSION: %04x\n", lpc17_phyread(phyaddr, MII_EXPANSION)); + ninfo("PHY " LPC17_PHYNAME ": %s\n", msg); + ninfo(" MCR: %04x\n", lpc17_phyread(phyaddr, MII_MCR)); + ninfo(" MSR: %04x\n", lpc17_phyread(phyaddr, MII_MSR)); + ninfo(" ADVERTISE: %04x\n", lpc17_phyread(phyaddr, MII_ADVERTISE)); + ninfo(" LPA: %04x\n", lpc17_phyread(phyaddr, MII_LPA)); + ninfo(" EXPANSION: %04x\n", lpc17_phyread(phyaddr, MII_EXPANSION)); #ifdef CONFIG_ETH0_PHY_KS8721 - _err(" 10BTCR: %04x\n", lpc17_phyread(phyaddr, MII_KS8721_10BTCR)); + ninfo(" 10BTCR: %04x\n", lpc17_phyread(phyaddr, MII_KS8721_10BTCR)); #endif } #endif @@ -2462,7 +2462,7 @@ static inline int lpc17_phyreset(uint8_t phyaddr) } } - nerr("Reset failed. MCR: %04x\n", phyreg); + nerr("ERROR: Reset failed. MCR: %04x\n", phyreg); return -ETIMEDOUT; } #endif @@ -2509,7 +2509,7 @@ static inline int lpc17_phyautoneg(uint8_t phyaddr) } } - nerr("Auto-negotiation failed. MSR: %04x\n", phyreg); + nerr("ERROR: Auto-negotiation failed. MSR: %04x\n", phyreg); return -ETIMEDOUT; } #endif @@ -2593,7 +2593,7 @@ static int lpc17_phymode(uint8_t phyaddr, uint8_t mode) #endif } - nerr("Link failed. MSR: %04x\n", phyreg); + nerr("ERROR: Link failed. MSR: %04x\n", phyreg); return -ETIMEDOUT; } #endif @@ -2673,7 +2673,7 @@ static inline int lpc17_phyinit(struct lpc17_driver_s *priv) { /* Failed to find PHY at any location */ - nerr("No PHY detected\n"); + nerr("ERROR: No PHY detected\n"); return -ENODEV; } ninfo("phyaddr: %d\n", phyaddr); @@ -2760,7 +2760,7 @@ static inline int lpc17_phyinit(struct lpc17_driver_s *priv) break; default: - nerr("Unrecognized mode: %04x\n", phyreg); + nerr("ERROR: Unrecognized mode: %04x\n", phyreg); return -ENODEV; } @@ -2788,7 +2788,7 @@ static inline int lpc17_phyinit(struct lpc17_driver_s *priv) break; default: - nerr("Unrecognized mode: %04x\n", phyreg); + nerr("ERROR: Unrecognized mode: %04x\n", phyreg); return -ENODEV; } @@ -2816,7 +2816,7 @@ static inline int lpc17_phyinit(struct lpc17_driver_s *priv) break; default: - nerr("Unrecognized mode: %04x\n", phyreg); + nerr("ERROR: Unrecognized mode: %04x\n", phyreg); return -ENODEV; } @@ -2862,7 +2862,7 @@ static inline int lpc17_phyinit(struct lpc17_driver_s *priv) } else { - nerr("Unrecognized mode: %04x\n", phyreg); + nerr("ERROR: Unrecognized mode: %04x\n", phyreg); return -ENODEV; } } @@ -2871,9 +2871,9 @@ static inline int lpc17_phyinit(struct lpc17_driver_s *priv) # warning "PHY Unknown: speed and duplex are bogus" #endif - nerr("%dBase-T %s duplex\n", - (priv->lp_mode & LPC17_SPEED_MASK) == LPC17_SPEED_100 ? 100 : 10, - (priv->lp_mode & LPC17_DUPLEX_MASK) == LPC17_DUPLEX_FULL ?"full" : "half"); + ninfo("%dBase-T %s duplex\n", + (priv->lp_mode & LPC17_SPEED_MASK) == LPC17_SPEED_100 ? 100 : 10, + (priv->lp_mode & LPC17_DUPLEX_MASK) == LPC17_DUPLEX_FULL ?"full" : "half"); /* Disable auto-configuration. Set the fixed speed/duplex mode. * (probably more than little redundant). diff --git a/arch/arm/src/lpc17xx/lpc17_gpdma.c b/arch/arm/src/lpc17xx/lpc17_gpdma.c index 7b692c2535..2eb2edf16a 100644 --- a/arch/arm/src/lpc17xx/lpc17_gpdma.c +++ b/arch/arm/src/lpc17xx/lpc17_gpdma.c @@ -654,7 +654,7 @@ void lpc17_dmastop(DMA_HANDLE handle) * ****************************************************************************/ -#ifdef CONFIG_DEBUG_DMA +#ifdef CONFIG__DEBUG_DMA_INFO void lpc17_dmasample(DMA_HANDLE handle, struct lpc17_dmaregs_s *regs) { struct lpc17_dmach_s *dmach = (DMA_HANDLE)handle; @@ -686,7 +686,7 @@ void lpc17_dmasample(DMA_HANDLE handle, struct lpc17_dmaregs_s *regs) regs->ch.control = getreg32(base + LPC17_DMACH_CONTROL_OFFSET); regs->ch.config = getreg32(base + LPC17_DMACH_CONFIG_OFFSET); } -#endif /* CONFIG_DEBUG_DMA */ +#endif /* CONFIG__DEBUG_DMA_INFO */ /**************************************************************************** * Name: lpc17_dmadump @@ -696,7 +696,7 @@ void lpc17_dmasample(DMA_HANDLE handle, struct lpc17_dmaregs_s *regs) * ****************************************************************************/ -#ifdef CONFIG_DEBUG_DMA +#ifdef CONFIG__DEBUG_DMA_INFO void lpc17_dmadump(DMA_HANDLE handle, const struct lpc17_dmaregs_s *regs, const char *msg) { @@ -707,49 +707,49 @@ void lpc17_dmadump(DMA_HANDLE handle, const struct lpc17_dmaregs_s *regs, /* Dump the sampled global DMA registers */ - dmaerr("Global GPDMA Registers: %s\n", msg); - dmaerr(" INTST[%08x]: %08x\n", - LPC17_DMA_INTST, regs->gbl.intst); - dmaerr(" INTTCST[%08x]: %08x\n", - LPC17_DMA_INTTCST, regs->gbl.inttcst); - dmaerr(" INTERRST[%08x]: %08x\n", - LPC17_DMA_INTERRST, regs->gbl.interrst); - dmaerr(" RAWINTTCST[%08x]: %08x\n", - LPC17_DMA_RAWINTTCST, regs->gbl.rawinttcst); - dmaerr(" RAWINTERRST[%08x]: %08x\n", - LPC17_DMA_RAWINTERRST, regs->gbl.rawinterrst); - dmaerr(" ENBLDCHNS[%08x]: %08x\n", - LPC17_DMA_ENBLDCHNS, regs->gbl.enbldchns); - dmaerr(" SOFTBREQ[%08x]: %08x\n", - LPC17_DMA_SOFTBREQ, regs->gbl.softbreq); - dmaerr(" SOFTSREQ[%08x]: %08x\n", - LPC17_DMA_SOFTSREQ, regs->gbl.softsreq); - dmaerr(" SOFTLBREQ[%08x]: %08x\n", - LPC17_DMA_SOFTLBREQ, regs->gbl.softlbreq); - dmaerr(" SOFTLSREQ[%08x]: %08x\n", - LPC17_DMA_SOFTLSREQ, regs->gbl.softlsreq); - dmaerr(" CONFIG[%08x]: %08x\n", - LPC17_DMA_CONFIG, regs->gbl.config); - dmaerr(" SYNC[%08x]: %08x\n", - LPC17_DMA_SYNC, regs->gbl.sync); + dmainfo("Global GPDMA Registers: %s\n", msg); + dmainfo(" INTST[%08x]: %08x\n", + LPC17_DMA_INTST, regs->gbl.intst); + dmainfo(" INTTCST[%08x]: %08x\n", + LPC17_DMA_INTTCST, regs->gbl.inttcst); + dmainfo(" INTERRST[%08x]: %08x\n", + LPC17_DMA_INTERRST, regs->gbl.interrst); + dmainfo(" RAWINTTCST[%08x]: %08x\n", + LPC17_DMA_RAWINTTCST, regs->gbl.rawinttcst); + dmainfo(" RAWINTERRST[%08x]: %08x\n", + LPC17_DMA_RAWINTERRST, regs->gbl.rawinterrst); + dmainfo(" ENBLDCHNS[%08x]: %08x\n", + LPC17_DMA_ENBLDCHNS, regs->gbl.enbldchns); + dmainfo(" SOFTBREQ[%08x]: %08x\n", + LPC17_DMA_SOFTBREQ, regs->gbl.softbreq); + dmainfo(" SOFTSREQ[%08x]: %08x\n", + LPC17_DMA_SOFTSREQ, regs->gbl.softsreq); + dmainfo(" SOFTLBREQ[%08x]: %08x\n", + LPC17_DMA_SOFTLBREQ, regs->gbl.softlbreq); + dmainfo(" SOFTLSREQ[%08x]: %08x\n", + LPC17_DMA_SOFTLSREQ, regs->gbl.softlsreq); + dmainfo(" CONFIG[%08x]: %08x\n", + LPC17_DMA_CONFIG, regs->gbl.config); + dmainfo(" SYNC[%08x]: %08x\n", + LPC17_DMA_SYNC, regs->gbl.sync); /* Dump the DMA channel registers */ base = LPC17_DMACH_BASE((uint32_t)dmach->chn); - dmaerr("Channel GPDMA Registers: %d\n", dmach->chn); + dmainfo("Channel GPDMA Registers: %d\n", dmach->chn); - dmaerr(" SRCADDR[%08x]: %08x\n", - base + LPC17_DMACH_SRCADDR_OFFSET, regs->ch.srcaddr); - dmaerr(" DESTADDR[%08x]: %08x\n", - base + LPC17_DMACH_DESTADDR_OFFSET, regs->ch.destaddr); - dmaerr(" LLI[%08x]: %08x\n", - base + LPC17_DMACH_LLI_OFFSET, regs->ch.lli); - dmaerr(" CONTROL[%08x]: %08x\n", - base + LPC17_DMACH_CONTROL_OFFSET, regs->ch.control); - dmaerr(" CONFIG[%08x]: %08x\n", - base + LPC17_DMACH_CONFIG_OFFSET, regs->ch.config); + dmainfo(" SRCADDR[%08x]: %08x\n", + base + LPC17_DMACH_SRCADDR_OFFSET, regs->ch.srcaddr); + dmainfo(" DESTADDR[%08x]: %08x\n", + base + LPC17_DMACH_DESTADDR_OFFSET, regs->ch.destaddr); + dmainfo(" LLI[%08x]: %08x\n", + base + LPC17_DMACH_LLI_OFFSET, regs->ch.lli); + dmainfo(" CONTROL[%08x]: %08x\n", + base + LPC17_DMACH_CONTROL_OFFSET, regs->ch.control); + dmainfo(" CONFIG[%08x]: %08x\n", + base + LPC17_DMACH_CONFIG_OFFSET, regs->ch.config); } -#endif /* CONFIG_DEBUG_DMA */ +#endif /* CONFIG__DEBUG_DMA_INFO */ #endif /* CONFIG_LPC17_GPDMA */ diff --git a/arch/arm/src/lpc17xx/lpc17_gpdma.h b/arch/arm/src/lpc17xx/lpc17_gpdma.h index 4e1e499eb1..a7c0d7009c 100644 --- a/arch/arm/src/lpc17xx/lpc17_gpdma.h +++ b/arch/arm/src/lpc17xx/lpc17_gpdma.h @@ -68,7 +68,7 @@ typedef void (*dma_callback_t)(DMA_HANDLE handle, void *arg, int result); /* The following is used for sampling DMA registers when CONFIG DEBUG_DMA is selected */ -#ifdef CONFIG_DEBUG_DMA +#ifdef CONFIG__DEBUG_DMA_INFO struct lpc17_dmaglobalregs_s { /* Global Registers */ @@ -109,7 +109,7 @@ struct lpc17_dmaregs_s struct lpc17_dmachanregs_s ch; }; -#endif /* CONFIG_DEBUG_DMA */ +#endif /* CONFIG__DEBUG_DMA_INFO */ /**************************************************************************** * Public Data @@ -239,7 +239,7 @@ void lpc17_dmastop(DMA_HANDLE handle); * ****************************************************************************/ -#ifdef CONFIG_DEBUG_DMA +#ifdef CONFIG__DEBUG_DMA_INFO void lpc17_dmasample(DMA_HANDLE handle, struct lpc17_dmaregs_s *regs); #else # define lpc17_dmasample(handle,regs) @@ -253,7 +253,7 @@ void lpc17_dmasample(DMA_HANDLE handle, struct lpc17_dmaregs_s *regs); * ****************************************************************************/ -#ifdef CONFIG_DEBUG_DMA +#ifdef CONFIG__DEBUG_DMA_INFO void lpc17_dmadump(DMA_HANDLE handle, const struct lpc17_dmaregs_s *regs, const char *msg); #else diff --git a/arch/arm/src/lpc17xx/lpc17_i2c.c b/arch/arm/src/lpc17xx/lpc17_i2c.c index a4f817be33..58bb2de898 100644 --- a/arch/arm/src/lpc17xx/lpc17_i2c.c +++ b/arch/arm/src/lpc17xx/lpc17_i2c.c @@ -485,7 +485,7 @@ struct i2c_master_s *lpc17_i2cbus_initialize(int port) if (port > 1) { - _err("lpc I2C Only support 0,1\n"); + i2cerr("ERROR: LPC I2C Only supports ports 0 and 1\n"); return NULL; } diff --git a/arch/arm/src/lpc17xx/lpc17_lcd.c b/arch/arm/src/lpc17xx/lpc17_lcd.c index 5abf5d319e..f8a6c6db6c 100644 --- a/arch/arm/src/lpc17xx/lpc17_lcd.c +++ b/arch/arm/src/lpc17xx/lpc17_lcd.c @@ -202,14 +202,14 @@ struct fb_vtable_s g_fbobject = static int lpc17_getvideoinfo(FAR struct fb_vtable_s *vtable, FAR struct fb_videoinfo_s *vinfo) { - ginfo("vtable=%p vinfo=%p\n", vtable, vinfo); + lcdinfo("vtable=%p vinfo=%p\n", vtable, vinfo); if (vtable && vinfo) { memcpy(vinfo, &g_videoinfo, sizeof(struct fb_videoinfo_s)); return OK; } - gerr("Returning EINVAL\n"); + lcderr("ERROR: Returning EINVAL\n"); return -EINVAL; } @@ -220,14 +220,14 @@ static int lpc17_getvideoinfo(FAR struct fb_vtable_s *vtable, static int lpc17_getplaneinfo(FAR struct fb_vtable_s *vtable, int planeno, FAR struct fb_planeinfo_s *pinfo) { - ginfo("vtable=%p planeno=%d pinfo=%p\n", vtable, planeno, pinfo); + lcdinfo("vtable=%p planeno=%d pinfo=%p\n", vtable, planeno, pinfo); if (vtable && planeno == 0 && pinfo) { memcpy(pinfo, &g_planeinfo, sizeof(struct fb_planeinfo_s)); return OK; } - gerr("Returning EINVAL\n"); + lcderr("ERROR: Returning EINVAL\n"); return -EINVAL; } @@ -244,8 +244,8 @@ static int lpc17_getcmap(FAR struct fb_vtable_s *vtable, int last; int i; - ginfo("vtable=%p cmap=%p first=%d len=%d\n", - vtable, cmap, cmap->first, cmap->len); + lcdinfo("vtable=%p cmap=%p first=%d len=%d\n", + vtable, cmap, cmap->first, cmap->len); DEBUGASSERT(vtable && cmap && cmap->first < 256 && (cmap->first + cmap->len) < 256); @@ -319,8 +319,8 @@ static int lpc17_putcmap(FAR struct fb_vtable_s *vtable, int last; int i; - ginfo("vtable=%p cmap=%p first=%d len=%d\n", - vtable, cmap, cmap->first, cmap->len); + lcdinfo("vtable=%p cmap=%p first=%d len=%d\n", + vtable, cmap, cmap->first, cmap->len); DEBUGASSERT(vtable && cmap); @@ -383,27 +383,27 @@ static int lpc17_putcmap(FAR struct fb_vtable_s *vtable, static int lpc17_getcursor(FAR struct fb_vtable_s *vtable, FAR struct fb_cursorattrib_s *attrib) { - ginfo("vtable=%p attrib=%p\n", vtable, attrib); + lcdinfo("vtable=%p attrib=%p\n", vtable, attrib); if (vtable && attrib) { #ifdef CONFIG_FB_HWCURSORIMAGE attrib->fmt = LPC17_COLOR_FMT; #endif - ginfo("pos: (x=%d, y=%d)\n", g_cpos.x, g_cpos.y); + lcdinfo("pos: (x=%d, y=%d)\n", g_cpos.x, g_cpos.y); attrib->pos = g_cpos; #ifdef CONFIG_FB_HWCURSORSIZE attrib->mxsize.h = CONFIG_LPC17_LCD_VHEIGHT; attrib->mxsize.w = CONFIG_LPC17_LCD_HWIDTH; - ginfo("size: (h=%d, w=%d)\n", g_csize.h, g_csize.w); + lcdinfo("size: (h=%d, w=%d)\n", g_csize.h, g_csize.w); attrib->size = g_csize; #endif return OK; } - gerr("Returning EINVAL\n"); + lcderr("ERROR: Returning EINVAL\n"); return -EINVAL; } #endif @@ -416,34 +416,34 @@ static int lpc17_getcursor(FAR struct fb_vtable_s *vtable, static int lpc17_setcursor(FAR struct fb_vtable_s *vtable, FAR struct fb_setcursor_s *setttings) { - ginfo("vtable=%p setttings=%p\n", vtable, setttings); + lcdinfo("vtable=%p setttings=%p\n", vtable, setttings); if (vtable && setttings) { - ginfo("flags: %02x\n", settings->flags); + lcdinfo("flags: %02x\n", settings->flags); if ((flags & FB_CUR_SETPOSITION) != 0) { g_cpos = settings->pos; - ginfo("pos: (h:%d, w:%d)\n", g_cpos.x, g_cpos.y); + lcdinfo("pos: (h:%d, w:%d)\n", g_cpos.x, g_cpos.y); } #ifdef CONFIG_FB_HWCURSORSIZE if ((flags & FB_CUR_SETSIZE) != 0) { g_csize = settings->size; - ginfo("size: (h:%d, w:%d)\n", g_csize.h, g_csize.w); + lcdinfo("size: (h:%d, w:%d)\n", g_csize.h, g_csize.w); } #endif #ifdef CONFIG_FB_HWCURSORIMAGE if ((flags & FB_CUR_SETIMAGE) != 0) { - ginfo("image: (h:%d, w:%d) @ %p\n", - settings->img.height, settings->img.width, - settings->img.image); + lcdinfo("image: (h:%d, w:%d) @ %p\n", + settings->img.height, settings->img.width, + settings->img.image); } #endif return OK; } - gerr("Returning EINVAL\n"); + lcderr("ERROR: Returning EINVAL\n"); return -EINVAL; } #endif @@ -473,7 +473,7 @@ int up_fbinitialize(int display) uint32_t regval; int i; - ginfo("Entry\n"); + lcdinfo("Entry\n"); /* Give LCD bus priority */ @@ -485,7 +485,7 @@ int up_fbinitialize(int display) /* Configure pins */ /* Video data */ - ginfo("Configuring pins\n"); + lcdinfo("Configuring pins\n"); lpc17_configgpio(GPIO_LCD_VD0); lpc17_configgpio(GPIO_LCD_VD1); @@ -528,7 +528,7 @@ int up_fbinitialize(int display) modifyreg32(LPC17_SYSCON_PCONP, 0, SYSCON_PCONP_PCLCD); - ginfo("Configuring the LCD controller\n"); + lcdinfo("Configuring the LCD controller\n"); /* Disable the cursor */ @@ -686,7 +686,7 @@ int up_fbinitialize(int display) #endif putreg32(0, LPC17_LCD_INTMSK); - ginfo("Enabling the display\n"); + lcdinfo("Enabling the display\n"); for (i = LPC17_LCD_PWREN_DELAY; i; i--); @@ -727,7 +727,7 @@ int up_fbinitialize(int display) FAR struct fb_vtable_s *up_fbgetvplane(int display, int vplane) { - ginfo("vplane: %d\n", vplane); + lcdinfo("vplane: %d\n", vplane); if (vplane == 0) { return &g_fbobject; @@ -801,16 +801,16 @@ void lpc17_lcdclear(nxgl_mxpixel_t color) #if LPC17_BPP > 16 uint32_t *dest = (uint32_t *)CONFIG_LPC17_LCD_VRAMBASE; - ginfo("Clearing display: color=%08x VRAM=%08x size=%d\n", - color, CONFIG_LPC17_LCD_VRAMBASE, - CONFIG_LPC17_LCD_HWIDTH * CONFIG_LPC17_LCD_VHEIGHT * sizeof(uint32_t)); + lcdinfo("Clearing display: color=%08x VRAM=%08x size=%d\n", + color, CONFIG_LPC17_LCD_VRAMBASE, + CONFIG_LPC17_LCD_HWIDTH * CONFIG_LPC17_LCD_VHEIGHT * sizeof(uint32_t)); #else uint16_t *dest = (uint16_t *)CONFIG_LPC17_LCD_VRAMBASE; - ginfo("Clearing display: color=%08x VRAM=%08x size=%d\n", - color, CONFIG_LPC17_LCD_VRAMBASE, - CONFIG_LPC17_LCD_HWIDTH * CONFIG_LPC17_LCD_VHEIGHT * sizeof(uint16_t)); + lcdinfo("Clearing display: color=%08x VRAM=%08x size=%d\n", + color, CONFIG_LPC17_LCD_VRAMBASE, + CONFIG_LPC17_LCD_HWIDTH * CONFIG_LPC17_LCD_VHEIGHT * sizeof(uint16_t)); #endif for (i = 0; i < (CONFIG_LPC17_LCD_HWIDTH * CONFIG_LPC17_LCD_VHEIGHT); i++) diff --git a/arch/arm/src/lpc17xx/lpc17_mcpwm.c b/arch/arm/src/lpc17xx/lpc17_mcpwm.c index d7d70daeaa..be526964c4 100644 --- a/arch/arm/src/lpc17xx/lpc17_mcpwm.c +++ b/arch/arm/src/lpc17xx/lpc17_mcpwm.c @@ -655,7 +655,7 @@ FAR struct pwm_lowerhalf_s *lpc17_mcpwminitialize(int timer) #endif default: - pwmerr("No such timer configured\n"); + pwmerr("ERROR: No such timer configured\n"); return NULL; } diff --git a/arch/arm/src/lpc17xx/lpc17_pwm.c b/arch/arm/src/lpc17xx/lpc17_pwm.c index 5bcbeab20b..dc073fc1a7 100644 --- a/arch/arm/src/lpc17xx/lpc17_pwm.c +++ b/arch/arm/src/lpc17xx/lpc17_pwm.c @@ -626,7 +626,7 @@ FAR struct pwm_lowerhalf_s *lpc17_pwminitialize(int timer) #endif default: - pwmerr("No such timer configured\n"); + pwmerr("ERROR: No such timer configured\n"); return NULL; } diff --git a/arch/arm/src/lpc17xx/lpc17_sdcard.c b/arch/arm/src/lpc17xx/lpc17_sdcard.c index 6fb077c10b..15a15c55c6 100644 --- a/arch/arm/src/lpc17xx/lpc17_sdcard.c +++ b/arch/arm/src/lpc17xx/lpc17_sdcard.c @@ -810,7 +810,7 @@ static void lpc17_dmacallback(DMA_HANDLE handle, void *arg, int status) if (status < 0) { - fllerr("DMA error %d, remaining: %d\n", status, priv->remaining); + dmallerr("ERROR: DMA error %d, remaining: %d\n", status, priv->remaining); result = SDIOWAIT_ERROR; } else @@ -1077,7 +1077,7 @@ static void lpc17_eventtimeout(int argc, uint32_t arg) /* Yes.. wake up any waiting threads */ lpc17_endwait(priv, SDIOWAIT_TIMEOUT); - fllerr("Timeout: remaining: %d\n", priv->remaining); + mcllerr("ERROR: Timeout: remaining: %d\n", priv->remaining); } } @@ -1294,7 +1294,7 @@ static int lpc17_interrupt(int irq, void *context) { /* Terminate the transfer with an error */ - fllerr("ERROR: Data block CRC failure, remaining: %d\n", priv->remaining); + mcllerr("ERROR: Data block CRC failure, remaining: %d\n", priv->remaining); lpc17_endtransfer(priv, SDIOWAIT_TRANSFERDONE | SDIOWAIT_ERROR); } @@ -1304,7 +1304,7 @@ static int lpc17_interrupt(int irq, void *context) { /* Terminate the transfer with an error */ - fllerr("ERROR: Data timeout, remaining: %d\n", priv->remaining); + mcllerr("ERROR: Data timeout, remaining: %d\n", priv->remaining); lpc17_endtransfer(priv, SDIOWAIT_TRANSFERDONE | SDIOWAIT_TIMEOUT); } @@ -1314,7 +1314,7 @@ static int lpc17_interrupt(int irq, void *context) { /* Terminate the transfer with an error */ - fllerr("ERROR: RX FIFO overrun, remaining: %d\n", priv->remaining); + mcllerr("ERROR: RX FIFO overrun, remaining: %d\n", priv->remaining); lpc17_endtransfer(priv, SDIOWAIT_TRANSFERDONE | SDIOWAIT_ERROR); } @@ -1324,7 +1324,7 @@ static int lpc17_interrupt(int irq, void *context) { /* Terminate the transfer with an error */ - fllerr("ERROR: TX FIFO underrun, remaining: %d\n", priv->remaining); + mcllerr("ERROR: TX FIFO underrun, remaining: %d\n", priv->remaining); lpc17_endtransfer(priv, SDIOWAIT_TRANSFERDONE | SDIOWAIT_ERROR); } @@ -1334,7 +1334,7 @@ static int lpc17_interrupt(int irq, void *context) { /* Terminate the transfer with an error */ - fllerr("ERROR: Start bit, remaining: %d\n", priv->remaining); + mcllerr("ERROR: Start bit, remaining: %d\n", priv->remaining); lpc17_endtransfer(priv, SDIOWAIT_TRANSFERDONE | SDIOWAIT_ERROR); } } diff --git a/arch/arm/src/lpc17xx/lpc17_serial.c b/arch/arm/src/lpc17xx/lpc17_serial.c index 0ec62236a6..7062c521f4 100644 --- a/arch/arm/src/lpc17xx/lpc17_serial.c +++ b/arch/arm/src/lpc17xx/lpc17_serial.c @@ -1153,7 +1153,7 @@ static int up_interrupt(int irq, void *context) default: { - _err("Unexpected IIR: %02x\n", status); + _err("ERROR: Unexpected IIR: %02x\n", status); break; } } diff --git a/arch/arm/src/lpc17xx/lpc17_spi.c b/arch/arm/src/lpc17xx/lpc17_spi.c index 7a53a04022..6ddef3951f 100644 --- a/arch/arm/src/lpc17xx/lpc17_spi.c +++ b/arch/arm/src/lpc17xx/lpc17_spi.c @@ -267,7 +267,7 @@ static uint32_t spi_setfrequency(FAR struct spi_dev_s *dev, uint32_t frequency) priv->frequency = frequency; priv->actual = actual; - spierr("Frequency %d->%d\n", frequency, actual); + spiinfo("Frequency %d->%d\n", frequency, actual); return actual; } @@ -429,7 +429,7 @@ static void spi_sndblock(FAR struct spi_dev_s *dev, FAR const void *buffer, size FAR uint8_t *ptr = (FAR uint8_t *)buffer; uint8_t data; - spierr("nwords: %d\n", nwords); + spiinfo("nwords: %d\n", nwords); while (nwords) { /* Write the data to transmitted to the SPI Data Register */ @@ -474,7 +474,7 @@ static void spi_recvblock(FAR struct spi_dev_s *dev, FAR void *buffer, size_t nw { FAR uint8_t *ptr = (FAR uint8_t *)buffer; - spierr("nwords: %d\n", nwords); + spiinfo("nwords: %d\n", nwords); while (nwords) { /* Write some dummy data to the SPI Data Register in order to clock the diff --git a/arch/arm/src/lpc17xx/lpc17_usbdev.c b/arch/arm/src/lpc17xx/lpc17_usbdev.c index d2c4606283..37cc9ab5eb 100644 --- a/arch/arm/src/lpc17xx/lpc17_usbdev.c +++ b/arch/arm/src/lpc17xx/lpc17_usbdev.c @@ -102,10 +102,13 @@ #ifdef CONFIG_DEBUG_USB # define USB_ERROR_INT USBDEV_INT_ERRINT #else -# undef CONFIG_LPC17_USBDEV_REGDEBUG # define USB_ERROR_INT 0 #endif +#ifndef CONFIG_DEBUG_USB_INFO +# undef CONFIG_LPC17_USBDEV_REGDEBUG +#endif + /* CLKCTRL enable bits */ #define LPC17_CLKCTRL_ENABLES (USBDEV_CLK_DEVCLK|USBDEV_CLK_AHBCLK) @@ -531,7 +534,7 @@ static struct lpc17_dmadesc_s g_usbddesc[CONFIG_LPC17_USBDEV_NDMADESCRIPTORS]; #ifdef CONFIG_LPC17_USBDEV_REGDEBUG static void lpc17_printreg(uint32_t addr, uint32_t val, bool iswrite) { - _llerr("%08x%s%08x\n", addr, iswrite ? "<-" : "->", val); + ullinfo("%08x%s%08x\n", addr, iswrite ? "<-" : "->", val); } #endif @@ -581,7 +584,7 @@ static void lpc17_checkreg(uint32_t addr, uint32_t val, bool iswrite) { /* No.. More than one. */ - _llerr("[repeats %d more times]\n", count); + ullinfo("[repeats %d more times]\n", count); } } diff --git a/arch/arm/src/lpc17xx/lpc17_usbhost.c b/arch/arm/src/lpc17xx/lpc17_usbhost.c index 7d707daf79..269f2de253 100644 --- a/arch/arm/src/lpc17xx/lpc17_usbhost.c +++ b/arch/arm/src/lpc17xx/lpc17_usbhost.c @@ -88,6 +88,10 @@ # define CONFIG_LPC17_USBHOST_NPREALLOC 8 #endif +#ifndef CONFIG_DEBUG_USB_INFO +# undef CONFIG_LPC17_USBHOST_REGDEBUG +#endif + /* OHCI Setup ******************************************************************/ /* Frame Interval / Periodic Start */ @@ -114,7 +118,7 @@ /* Dump GPIO registers */ -#if defined(CONFIG_LPC17_USBHOST_REGDEBUG) && defined(CONFIG_DEBUG_GPIO_INFO) +#ifdef CONFIG_LPC17_USBHOST_REGDEBUG # define usbhost_dumpgpio() \ do { \ lpc17_dumpgpio(GPIO_USB_DP, "D+ P0.29; D- P0.30"); \ @@ -456,7 +460,7 @@ static struct lpc17_xfrinfo_s g_xfrbuffers[CONFIG_LPC17_USBHOST_NPREALLOC]; #ifdef CONFIG_LPC17_USBHOST_REGDEBUG static void lpc17_printreg(uint32_t addr, uint32_t val, bool iswrite) { - _llerr("%08x%s%08x\n", addr, iswrite ? "<-" : "->", val); + ullinfo("%08x%s%08x\n", addr, iswrite ? "<-" : "->", val); } #endif @@ -506,7 +510,7 @@ static void lpc17_checkreg(uint32_t addr, uint32_t val, bool iswrite) { /* No.. More than one. */ - _llerr("[repeats %d more times]\n", count); + ullinfo("[repeats %d more times]\n", count); } } @@ -1694,7 +1698,7 @@ static int lpc17_usbinterrupt(int irq, void *context) } else { - ullerr("Spurious status change (connected)\n"); + ullwarn("WARNING: Spurious status change (connected)\n"); } /* The LSDA (Low speed device attached) bit is valid @@ -1750,7 +1754,7 @@ static int lpc17_usbinterrupt(int irq, void *context) } else { - ullerr("Spurious status change (disconnected)\n"); + ullwarn("WARNING: Spurious status change (disconnected)\n"); } } @@ -1967,8 +1971,8 @@ static int lpc17_wait(struct usbhost_connection_s *conn, *hport = connport; leave_critical_section(flags); - uerr("RHport Connected: %s\n", - connport->connected ? "YES" : "NO"); + uinfo("RHport Connected: %s\n", + connport->connected ? "YES" : "NO"); return OK; } @@ -1987,7 +1991,7 @@ static int lpc17_wait(struct usbhost_connection_s *conn, *hport = connport; leave_critical_section(flags); - uerr("Hub port Connected: %s\n", connport->connected ? "YES" : "NO"); + uinfo("Hub port Connected: %s\n", connport->connected ? "YES" : "NO"); return OK; } #endif @@ -2041,7 +2045,7 @@ static int lpc17_rh_enumerate(struct usbhost_connection_s *conn, { /* No, return an error */ - uerr("Not connected\n"); + uwarn("WARNING: Not connected\n"); return -ENODEV; } @@ -3695,7 +3699,7 @@ struct usbhost_connection_s *lpc17_usbhost_initialize(int controller) lpc17_configgpio(GPIO_USB_OVRCR); /* USB port Over-Current status */ usbhost_dumpgpio(); - uerr("Initializing Host Stack\n"); + uinfo("Initializing Host Stack\n"); /* Show AHB SRAM memory map */ @@ -3825,7 +3829,7 @@ struct usbhost_connection_s *lpc17_usbhost_initialize(int controller) if (irq_attach(LPC17_IRQ_USB, lpc17_usbinterrupt) != 0) { - uerr("Failed to attach IRQ\n"); + uerr("ERROR: Failed to attach IRQ\n"); return NULL; } @@ -3850,8 +3854,8 @@ struct usbhost_connection_s *lpc17_usbhost_initialize(int controller) /* Enable interrupts at the interrupt controller */ up_enable_irq(LPC17_IRQ_USB); /* enable USB interrupt */ - uerr("USB host Initialized, Device connected:%s\n", - priv->connected ? "YES" : "NO"); + uinfo("USB host Initialized, Device connected:%s\n", + priv->connected ? "YES" : "NO"); return &g_usbconn; } From 24a9722723369d48fe98304e953a2d0e83428443 Mon Sep 17 00:00:00 2001 From: Gregory Nutt Date: Fri, 17 Jun 2016 11:45:17 -0600 Subject: [PATCH 45/75] KL/Kinetis: Convert *err() to either *info() or add ERROR:, depending on if an error is reported --- arch/arm/src/kinetis/kinetis_enet.c | 14 +-- arch/arm/src/kinetis/kinetis_pwm.c | 6 +- arch/arm/src/kinetis/kinetis_sdhc.c | 150 +++++++++++++------------- arch/arm/src/kinetis/kinetis_serial.c | 2 +- arch/arm/src/kinetis/kinetis_start.c | 4 +- arch/arm/src/kinetis/kinetis_usbdev.c | 103 ++++++++---------- arch/arm/src/kl/kl_pwm.c | 6 +- arch/arm/src/kl/kl_spi.c | 2 +- 8 files changed, 135 insertions(+), 152 deletions(-) diff --git a/arch/arm/src/kinetis/kinetis_enet.c b/arch/arm/src/kinetis/kinetis_enet.c index b8e0ed627e..f31dfd06ba 100644 --- a/arch/arm/src/kinetis/kinetis_enet.c +++ b/arch/arm/src/kinetis/kinetis_enet.c @@ -918,9 +918,9 @@ static int kinetis_ifup(struct net_driver_s *dev) uint8_t *mac = dev->d_mac.ether_addr_octet; uint32_t regval; - nerr("Bringing up: %d.%d.%d.%d\n", - dev->d_ipaddr & 0xff, (dev->d_ipaddr >> 8) & 0xff, - (dev->d_ipaddr >> 16) & 0xff, dev->d_ipaddr >> 24); + ninfo("Bringing up: %d.%d.%d.%d\n", + dev->d_ipaddr & 0xff, (dev->d_ipaddr >> 8) & 0xff, + (dev->d_ipaddr >> 16) & 0xff, dev->d_ipaddr >> 24); /* Initialize ENET buffers */ @@ -1695,7 +1695,7 @@ int kinetis_netinitialize(int intf) { /* We could not attach the ISR to the interrupt */ - nerr("Failed to attach EMACTMR IRQ\n"); + nerr("ERROR: Failed to attach EMACTMR IRQ\n"); return -EAGAIN; } #endif @@ -1706,7 +1706,7 @@ int kinetis_netinitialize(int intf) { /* We could not attach the ISR to the interrupt */ - nerr("Failed to attach EMACTX IRQ\n"); + nerr("ERROR: Failed to attach EMACTX IRQ\n"); return -EAGAIN; } @@ -1716,7 +1716,7 @@ int kinetis_netinitialize(int intf) { /* We could not attach the ISR to the interrupt */ - nerr("Failed to attach EMACRX IRQ\n"); + nerr("ERROR: Failed to attach EMACRX IRQ\n"); return -EAGAIN; } @@ -1726,7 +1726,7 @@ int kinetis_netinitialize(int intf) { /* We could not attach the ISR to the interrupt */ - nerr("Failed to attach EMACMISC IRQ\n"); + nerr("ERROR: Failed to attach EMACMISC IRQ\n"); return -EAGAIN; } diff --git a/arch/arm/src/kinetis/kinetis_pwm.c b/arch/arm/src/kinetis/kinetis_pwm.c index 9ac5afbd95..0730bf8dd8 100644 --- a/arch/arm/src/kinetis/kinetis_pwm.c +++ b/arch/arm/src/kinetis/kinetis_pwm.c @@ -500,7 +500,7 @@ static int pwm_timer(FAR struct kinetis_pwmtimer_s *priv, break; default: - pwmerr("No such channel: %d\n", priv->channel); + pwmerr("ERROR: No such channel: %d\n", priv->channel); return -EINVAL; } @@ -692,7 +692,7 @@ static int pwm_stop(FAR struct pwm_lowerhalf_s *dev) break; default: - pwmerr("No such channel: %d\n", priv->channel); + pwmerr("ERROR: No such channel: %d\n", priv->channel); return -EINVAL; } @@ -779,7 +779,7 @@ FAR struct pwm_lowerhalf_s *kinetis_pwminitialize(int timer) #endif default: - pwmerr("No such timer configured\n"); + pwmerr("ERROR: No such timer configured\n"); return NULL; } diff --git a/arch/arm/src/kinetis/kinetis_sdhc.c b/arch/arm/src/kinetis/kinetis_sdhc.c index 0b2214cb2b..46b4943831 100644 --- a/arch/arm/src/kinetis/kinetis_sdhc.c +++ b/arch/arm/src/kinetis/kinetis_sdhc.c @@ -89,7 +89,7 @@ # define CONFIG_KINETIS_SDHC_DMAPRIO DMA_CCR_PRIMED #endif -#if !defined(CONFIG_DEBUG_FS) || !defined(CONFIG_DEBUG_INFO) +#ifndef CONFIG_DEBUG_MEMCARD_INFO # undef CONFIG_SDIO_XFRDEBUG #endif @@ -574,29 +574,29 @@ static void kinetis_sample(struct kinetis_dev_s *priv, int index) static void kinetis_dumpsample(struct kinetis_dev_s *priv, struct kinetis_sdhcregs_s *regs, const char *msg) { - ferr("SDHC Registers: %s\n", msg); - ferr(" DSADDR[%08x]: %08x\n", KINETIS_SDHC_DSADDR, regs->dsaddr); - ferr(" BLKATTR[%08x]: %08x\n", KINETIS_SDHC_BLKATTR, regs->blkattr); - ferr(" CMDARG[%08x]: %08x\n", KINETIS_SDHC_CMDARG, regs->cmdarg); - ferr(" XFERTY[%08x]: %08x\n", KINETIS_SDHC_XFERTYP, regs->xferty); - ferr(" CMDRSP0[%08x]: %08x\n", KINETIS_SDHC_CMDRSP0, regs->cmdrsp0); - ferr(" CMDRSP1[%08x]: %08x\n", KINETIS_SDHC_CMDRSP1, regs->cmdrsp1); - ferr(" CMDRSP2[%08x]: %08x\n", KINETIS_SDHC_CMDRSP2, regs->cmdrsp2); - ferr(" CMDRSP3[%08x]: %08x\n", KINETIS_SDHC_CMDRSP3, regs->cmdrsp3); - ferr(" PRSSTAT[%08x]: %08x\n", KINETIS_SDHC_PRSSTAT, regs->prsstat); - ferr(" PROCTL[%08x]: %08x\n", KINETIS_SDHC_PROCTL, regs->proctl); - ferr(" SYSCTL[%08x]: %08x\n", KINETIS_SDHC_SYSCTL, regs->sysctl); - ferr(" IRQSTAT[%08x]: %08x\n", KINETIS_SDHC_IRQSTAT, regs->irqstat); - ferr("IRQSTATEN[%08x]: %08x\n", KINETIS_SDHC_IRQSTATEN, regs->irqstaten); - ferr(" IRQSIGEN[%08x]: %08x\n", KINETIS_SDHC_IRQSIGEN, regs->irqsigen); - ferr(" AC12ERR[%08x]: %08x\n", KINETIS_SDHC_AC12ERR, regs->ac12err); - ferr(" HTCAPBLT[%08x]: %08x\n", KINETIS_SDHC_HTCAPBLT, regs->htcapblt); - ferr(" WML[%08x]: %08x\n", KINETIS_SDHC_WML, regs->wml); - ferr(" ADMAES[%08x]: %08x\n", KINETIS_SDHC_ADMAES, regs->admaes); - ferr(" ADSADDR[%08x]: %08x\n", KINETIS_SDHC_ADSADDR, regs->adsaddr); - ferr(" VENDOR[%08x]: %08x\n", KINETIS_SDHC_VENDOR, regs->vendor); - ferr(" MMCBOOT[%08x]: %08x\n", KINETIS_SDHC_MMCBOOT, regs->mmcboot); - ferr(" HOSTVER[%08x]: %08x\n", KINETIS_SDHC_HOSTVER, regs->hostver); + mcinfo("SDHC Registers: %s\n", msg); + mcinfo(" DSADDR[%08x]: %08x\n", KINETIS_SDHC_DSADDR, regs->dsaddr); + mcinfo(" BLKATTR[%08x]: %08x\n", KINETIS_SDHC_BLKATTR, regs->blkattr); + mcinfo(" CMDARG[%08x]: %08x\n", KINETIS_SDHC_CMDARG, regs->cmdarg); + mcinfo(" XFERTY[%08x]: %08x\n", KINETIS_SDHC_XFERTYP, regs->xferty); + mcinfo(" CMDRSP0[%08x]: %08x\n", KINETIS_SDHC_CMDRSP0, regs->cmdrsp0); + mcinfo(" CMDRSP1[%08x]: %08x\n", KINETIS_SDHC_CMDRSP1, regs->cmdrsp1); + mcinfo(" CMDRSP2[%08x]: %08x\n", KINETIS_SDHC_CMDRSP2, regs->cmdrsp2); + mcinfo(" CMDRSP3[%08x]: %08x\n", KINETIS_SDHC_CMDRSP3, regs->cmdrsp3); + mcinfo(" PRSSTAT[%08x]: %08x\n", KINETIS_SDHC_PRSSTAT, regs->prsstat); + mcinfo(" PROCTL[%08x]: %08x\n", KINETIS_SDHC_PROCTL, regs->proctl); + mcinfo(" SYSCTL[%08x]: %08x\n", KINETIS_SDHC_SYSCTL, regs->sysctl); + mcinfo(" IRQSTAT[%08x]: %08x\n", KINETIS_SDHC_IRQSTAT, regs->irqstat); + mcinfo("IRQSTATEN[%08x]: %08x\n", KINETIS_SDHC_IRQSTATEN, regs->irqstaten); + mcinfo(" IRQSIGEN[%08x]: %08x\n", KINETIS_SDHC_IRQSIGEN, regs->irqsigen); + mcinfo(" AC12ERR[%08x]: %08x\n", KINETIS_SDHC_AC12ERR, regs->ac12err); + mcinfo(" HTCAPBLT[%08x]: %08x\n", KINETIS_SDHC_HTCAPBLT, regs->htcapblt); + mcinfo(" WML[%08x]: %08x\n", KINETIS_SDHC_WML, regs->wml); + mcinfo(" ADMAES[%08x]: %08x\n", KINETIS_SDHC_ADMAES, regs->admaes); + mcinfo(" ADSADDR[%08x]: %08x\n", KINETIS_SDHC_ADSADDR, regs->adsaddr); + mcinfo(" VENDOR[%08x]: %08x\n", KINETIS_SDHC_VENDOR, regs->vendor); + mcinfo(" MMCBOOT[%08x]: %08x\n", KINETIS_SDHC_MMCBOOT, regs->mmcboot); + mcinfo(" HOSTVER[%08x]: %08x\n", KINETIS_SDHC_HOSTVER, regs->hostver); } #endif @@ -791,8 +791,8 @@ static void kinetis_transmit(struct kinetis_dev_s *priv) * ready (BWR) */ - fllinfo("Entry: remaining: %d IRQSTAT: %08x\n", - priv->remaining, getreg32(KINETIS_SDHC_IRQSTAT)); + mcllinfo("Entry: remaining: %d IRQSTAT: %08x\n", + priv->remaining, getreg32(KINETIS_SDHC_IRQSTAT)); while (priv->remaining > 0 && (getreg32(KINETIS_SDHC_IRQSTAT) & SDHC_INT_BWR) != 0) @@ -837,9 +837,8 @@ static void kinetis_transmit(struct kinetis_dev_s *priv) putreg32(data.w, KINETIS_SDHC_DATPORT); } - fllinfo("Exit: remaining: %d IRQSTAT: %08x\n", - priv->remaining, getreg32(KINETIS_SDHC_IRQSTAT)); - + mcllinfo("Exit: remaining: %d IRQSTAT: %08x\n", + priv->remaining, getreg32(KINETIS_SDHC_IRQSTAT)); } #endif @@ -877,8 +876,8 @@ static void kinetis_receive(struct kinetis_dev_s *priv) * ready (BRR) */ - fllinfo("Entry: remaining: %d IRQSTAT: %08x\n", - priv->remaining, getreg32(KINETIS_SDHC_IRQSTAT)); + mcllinfo("Entry: remaining: %d IRQSTAT: %08x\n", + priv->remaining, getreg32(KINETIS_SDHC_IRQSTAT)); while (priv->remaining > 0 && (getreg32(KINETIS_SDHC_IRQSTAT) & SDHC_INT_BRR) != 0) @@ -929,10 +928,9 @@ static void kinetis_receive(struct kinetis_dev_s *priv) putreg32(watermark << SDHC_WML_RD_SHIFT, KINETIS_SDHC_WML); - fllinfo("Exit: remaining: %d IRQSTAT: %08x WML: %08x\n", - priv->remaining, getreg32(KINETIS_SDHC_IRQSTAT), - getreg32(KINETIS_SDHC_WML)); - + mcllinfo("Exit: remaining: %d IRQSTAT: %08x WML: %08x\n", + priv->remaining, getreg32(KINETIS_SDHC_IRQSTAT), + getreg32(KINETIS_SDHC_WML)); } #endif @@ -973,7 +971,7 @@ static void kinetis_eventtimeout(int argc, uint32_t arg) /* Wake up any waiting threads */ kinetis_endwait(priv, SDIOWAIT_TIMEOUT); - fllerr("Timeout: remaining: %d\n", priv->remaining); + mcllerr("ERROR: Timeout: remaining: %d\n", priv->remaining); } } @@ -1105,8 +1103,8 @@ static int kinetis_interrupt(int irq, void *context) regval = getreg32(KINETIS_SDHC_IRQSIGEN); enabled = getreg32(KINETIS_SDHC_IRQSTAT) & regval; - fllinfo("IRQSTAT: %08x IRQSIGEN %08x enabled: %08x\n", - getreg32(KINETIS_SDHC_IRQSTAT), regval, enabled); + mcllinfo("IRQSTAT: %08x IRQSIGEN %08x enabled: %08x\n", + getreg32(KINETIS_SDHC_IRQSTAT), regval, enabled); /* Disable card interrupts to clear the card interrupt to the host system. */ @@ -1162,7 +1160,7 @@ static int kinetis_interrupt(int irq, void *context) { /* Terminate the transfer with an error */ - fllerr("ERROR: Data block CRC failure, remaining: %d\n", priv->remaining); + mcllerr("ERROR: Data block CRC failure, remaining: %d\n", priv->remaining); kinetis_endtransfer(priv, SDIOWAIT_TRANSFERDONE | SDIOWAIT_ERROR); } @@ -1172,7 +1170,7 @@ static int kinetis_interrupt(int irq, void *context) { /* Terminate the transfer with an error */ - fllerr("ERROR: Data timeout, remaining: %d\n", priv->remaining); + mcllerr("ERROR: Data timeout, remaining: %d\n", priv->remaining); kinetis_endtransfer(priv, SDIOWAIT_TRANSFERDONE | SDIOWAIT_TIMEOUT); } } @@ -1289,9 +1287,9 @@ static void kinetis_reset(FAR struct sdio_dev_s *dev) putreg32(SDHC_INT_ALL, KINETIS_SDHC_IRQSTATEN); - finfo("SYSCTL: %08x PRSSTAT: %08x IRQSTATEN: %08x\n", - getreg32(KINETIS_SDHC_SYSCTL), getreg32(KINETIS_SDHC_PRSSTAT), - getreg32(KINETIS_SDHC_IRQSTATEN)); + mcinfo("SYSCTL: %08x PRSSTAT: %08x IRQSTATEN: %08x\n", + getreg32(KINETIS_SDHC_SYSCTL), getreg32(KINETIS_SDHC_PRSSTAT), + getreg32(KINETIS_SDHC_IRQSTATEN)); /* The next phase of the hardware reset would be to set the SYSCTRL INITA * bit to send 80 clock ticks for card to power up and then reset the card @@ -1504,7 +1502,7 @@ static void kinetis_frequency(FAR struct sdio_dev_s *dev, uint32_t frequency) regval |= (SDHC_SYSCTL_SDCLKEN | SDHC_SYSCTL_PEREN | SDHC_SYSCTL_HCKEN | SDHC_SYSCTL_IPGEN); putreg32(regval, KINETIS_SDHC_SYSCTL); - finfo("SYSCTRL: %08x\n", getreg32(KINETIS_SDHC_SYSCTL)); + mcinfo("SYSCTRL: %08x\n", getreg32(KINETIS_SDHC_SYSCTL)); } #endif @@ -1538,7 +1536,7 @@ static void kinetis_clock(FAR struct sdio_dev_s *dev, enum sdio_clock_e rate) regval = getreg32(KINETIS_SDHC_SYSCTL); regval &= ~SDHC_SYSCTL_SDCLKEN; putreg32(regval, KINETIS_SDHC_SYSCTL); - finfo("SYSCTRL: %08x\n", getreg32(KINETIS_SDHC_SYSCTL)); + mcinfo("SYSCTRL: %08x\n", getreg32(KINETIS_SDHC_SYSCTL)); switch (rate) { @@ -1552,7 +1550,7 @@ static void kinetis_clock(FAR struct sdio_dev_s *dev, enum sdio_clock_e rate) regval &= ~(SDHC_SYSCTL_IPGEN | SDHC_SYSCTL_HCKEN | SDHC_SYSCTL_PEREN | SDHC_SYSCTL_SDCLKFS_MASK | SDHC_SYSCTL_DVS_MASK); putreg32(regval, KINETIS_SDHC_SYSCTL); - finfo("SYSCTRL: %08x\n", getreg32(KINETIS_SDHC_SYSCTL)); + mcinfo("SYSCTRL: %08x\n", getreg32(KINETIS_SDHC_SYSCTL)); return; } @@ -1593,7 +1591,7 @@ static void kinetis_clock(FAR struct sdio_dev_s *dev, enum sdio_clock_e rate) regval = getreg32(KINETIS_SDHC_SYSCTL); regval &= ~SDHC_SYSCTL_SDCLKEN; putreg32(regval, KINETIS_SDHC_SYSCTL); - finfo("SYSCTRL: %08x\n", getreg32(KINETIS_SDHC_SYSCTL)); + mcinfo("SYSCTRL: %08x\n", getreg32(KINETIS_SDHC_SYSCTL)); /* Clear the old prescaler and divisor values so that new ones can be ORed * in. @@ -1619,7 +1617,7 @@ static void kinetis_clock(FAR struct sdio_dev_s *dev, enum sdio_clock_e rate) regval &= ~(SDHC_SYSCTL_IPGEN | SDHC_SYSCTL_HCKEN | SDHC_SYSCTL_PEREN); putreg32(regval, KINETIS_SDHC_SYSCTL); - finfo("SYSCTRL: %08x\n", getreg32(KINETIS_SDHC_SYSCTL)); + mcinfo("SYSCTRL: %08x\n", getreg32(KINETIS_SDHC_SYSCTL)); return; } @@ -1653,7 +1651,7 @@ static void kinetis_clock(FAR struct sdio_dev_s *dev, enum sdio_clock_e rate) } putreg32(regval, KINETIS_SDHC_SYSCTL); - finfo("SYSCTRL: %08x\n", getreg32(KINETIS_SDHC_SYSCTL)); + mcinfo("SYSCTRL: %08x\n", getreg32(KINETIS_SDHC_SYSCTL)); } #endif @@ -1824,7 +1822,7 @@ static int kinetis_sendcmd(FAR struct sdio_dev_s *dev, uint32_t cmd, uint32_t ar /* Other bits? What about CMDTYP? */ - finfo("cmd: %08x arg: %08x regval: %08x\n", cmd, arg, regval); + mcinfo("cmd: %08x arg: %08x regval: %08x\n", cmd, arg, regval); /* The Command Inhibit (CIHB) bit is set in the PRSSTAT bit immediately * after the transfer type register is written. This bit is cleared when @@ -1840,8 +1838,8 @@ static int kinetis_sendcmd(FAR struct sdio_dev_s *dev, uint32_t cmd, uint32_t ar { if (--timeout <= 0) { - ferr("ERROR: Timeout cmd: %08x PRSSTAT: %08x\n", - cmd, getreg32(KINETIS_SDHC_PRSSTAT)); + mcerr("ERROR: Timeout cmd: %08x PRSSTAT: %08x\n", + cmd, getreg32(KINETIS_SDHC_PRSSTAT)); return -EBUSY; } @@ -2079,8 +2077,8 @@ static int kinetis_waitresponse(FAR struct sdio_dev_s *dev, uint32_t cmd) { if (--timeout <= 0) { - ferr("ERROR: Timeout cmd: %08x IRQSTAT: %08x\n", - cmd, getreg32(KINETIS_SDHC_IRQSTAT)); + mcerr("ERROR: Timeout cmd: %08x IRQSTAT: %08x\n", + cmd, getreg32(KINETIS_SDHC_IRQSTAT)); return -ETIMEDOUT; } @@ -2090,8 +2088,8 @@ static int kinetis_waitresponse(FAR struct sdio_dev_s *dev, uint32_t cmd) if ((getreg32(KINETIS_SDHC_IRQSTAT) & errors) != 0) { - ferr("ERROR: cmd: %08x errors: %08x IRQSTAT: %08x\n", - cmd, errors, getreg32(KINETIS_SDHC_IRQSTAT)); + mcerr("ERROR: cmd: %08x errors: %08x IRQSTAT: %08x\n", + cmd, errors, getreg32(KINETIS_SDHC_IRQSTAT)); ret = -EIO; } @@ -2155,7 +2153,7 @@ static int kinetis_recvshortcrc(FAR struct sdio_dev_s *dev, uint32_t cmd, #ifdef CONFIG_DEBUG_FEATURES if (!rshort) { - ferr("ERROR: rshort=NULL\n"); + mcerr("ERROR: rshort=NULL\n"); ret = -EINVAL; } @@ -2165,7 +2163,7 @@ static int kinetis_recvshortcrc(FAR struct sdio_dev_s *dev, uint32_t cmd, (cmd & MMCSD_RESPONSE_MASK) != MMCSD_R1B_RESPONSE && (cmd & MMCSD_RESPONSE_MASK) != MMCSD_R6_RESPONSE) { - ferr("ERROR: Wrong response CMD=%08x\n", cmd); + mcerr("ERROR: Wrong response CMD=%08x\n", cmd); ret = -EINVAL; } else @@ -2176,12 +2174,12 @@ static int kinetis_recvshortcrc(FAR struct sdio_dev_s *dev, uint32_t cmd, regval = getreg32(KINETIS_SDHC_IRQSTAT); if ((regval & SDHC_INT_CTOE) != 0) { - ferr("ERROR: Command timeout: %08x\n", regval); + mcerr("ERROR: Command timeout: %08x\n", regval); ret = -ETIMEDOUT; } else if ((regval & SDHC_INT_CCE) != 0) { - ferr("ERROR: CRC failure: %08x\n", regval); + mcerr("ERROR: CRC failure: %08x\n", regval); ret = -EIO; } } @@ -2214,7 +2212,7 @@ static int kinetis_recvlong(FAR struct sdio_dev_s *dev, uint32_t cmd, uint32_t r if ((cmd & MMCSD_RESPONSE_MASK) != MMCSD_R2_RESPONSE) { - ferr("ERROR: Wrong response CMD=%08x\n", cmd); + mcerr("ERROR: Wrong response CMD=%08x\n", cmd); ret = -EINVAL; } else @@ -2225,12 +2223,12 @@ static int kinetis_recvlong(FAR struct sdio_dev_s *dev, uint32_t cmd, uint32_t r regval = getreg32(KINETIS_SDHC_IRQSTAT); if (regval & SDHC_INT_CTOE) { - ferr("ERROR: Timeout IRQSTAT: %08x\n", regval); + mcerr("ERROR: Timeout IRQSTAT: %08x\n", regval); ret = -ETIMEDOUT; } else if (regval & SDHC_INT_CCE) { - ferr("ERROR: CRC fail IRQSTAT: %08x\n", regval); + mcerr("ERROR: CRC fail IRQSTAT: %08x\n", regval); ret = -EIO; } } @@ -2267,7 +2265,7 @@ static int kinetis_recvshort(FAR struct sdio_dev_s *dev, uint32_t cmd, uint32_t if ((cmd & MMCSD_RESPONSE_MASK) != MMCSD_R3_RESPONSE && (cmd & MMCSD_RESPONSE_MASK) != MMCSD_R7_RESPONSE) { - ferr("ERROR: Wrong response CMD=%08x\n", cmd); + mcerr("ERROR: Wrong response CMD=%08x\n", cmd); ret = -EINVAL; } else @@ -2280,7 +2278,7 @@ static int kinetis_recvshort(FAR struct sdio_dev_s *dev, uint32_t cmd, uint32_t regval = getreg32(KINETIS_SDHC_IRQSTAT); if (regval & SDHC_INT_CTOE) { - ferr("ERROR: Timeout IRQSTAT: %08x\n", regval); + mcerr("ERROR: Timeout IRQSTAT: %08x\n", regval); ret = -ETIMEDOUT; } } @@ -2416,7 +2414,7 @@ static sdio_eventset_t kinetis_eventwait(FAR struct sdio_dev_s *dev, 1, (uint32_t)priv); if (ret != OK) { - ferr("ERROR: wd_start failed: %d\n", ret); + mcerr("ERROR: wd_start failed: %d\n", ret); } } @@ -2486,7 +2484,7 @@ static void kinetis_callbackenable(FAR struct sdio_dev_s *dev, { struct kinetis_dev_s *priv = (struct kinetis_dev_s *)dev; - finfo("eventset: %02x\n", eventset); + mcinfo("eventset: %02x\n", eventset); DEBUGASSERT(priv != NULL); priv->cbevents = eventset; @@ -2522,7 +2520,7 @@ static int kinetis_registercallback(FAR struct sdio_dev_s *dev, /* Disable callbacks and register this callback and is argument */ - finfo("Register %p(%p)\n", callback, arg); + mcinfo("Register %p(%p)\n", callback, arg); DEBUGASSERT(priv != NULL); priv->cbevents = 0; @@ -2694,8 +2692,8 @@ static void kinetis_callback(void *arg) /* Is a callback registered? */ DEBUGASSERT(priv != NULL); - finfo("Callback %p(%p) cbevents: %02x cdstatus: %02x\n", - priv->callback, priv->cbarg, priv->cbevents, priv->cdstatus); + mcinfo("Callback %p(%p) cbevents: %02x cdstatus: %02x\n", + priv->callback, priv->cbarg, priv->cbevents, priv->cdstatus); if (priv->callback) { @@ -2739,14 +2737,14 @@ static void kinetis_callback(void *arg) { /* Yes.. queue it */ - finfo("Queuing callback to %p(%p)\n", priv->callback, priv->cbarg); + mcinfo("Queuing callback to %p(%p)\n", priv->callback, priv->cbarg); (void)work_queue(HPWORK, &priv->cbwork, (worker_t)priv->callback, priv->cbarg, 0); } else { /* No.. then just call the callback here */ - finfo("Callback to %p(%p)\n", priv->callback, priv->cbarg); + mcinfo("Callback to %p(%p)\n", priv->callback, priv->cbarg); priv->callback(priv->cbarg); } } @@ -2792,7 +2790,7 @@ FAR struct sdio_dev_s *sdhc_initialize(int slotno) regval = getreg32(KINETIS_SIM_SCGC3); regval |= SIM_SCGC3_SDHC; putreg32(regval, KINETIS_SIM_SCGC3); - finfo("SIM_SCGC3: %08x\n", regval); + mcinfo("SIM_SCGC3: %08x\n", regval); /* In addition to the system clock, the SDHC module needs a clock for the * base for the external card clock. There are four possible sources for @@ -2808,7 +2806,7 @@ FAR struct sdio_dev_s *sdhc_initialize(int slotno) regval &= ~SIM_SOPT2_SDHCSRC_MASK; regval |= SIM_SOPT2_SDHCSRC_CORE; putreg32(regval, KINETIS_SIM_SOPT2); - finfo("SIM_SOPT2: %08x\n", regval); + mcinfo("SIM_SOPT2: %08x\n", regval); /* Configure pins for 1 or 4-bit, wide-bus operation (the chip is capable * of 8-bit wide bus operation but D4-D7 are not configured). @@ -2892,7 +2890,7 @@ void sdhc_mediachange(FAR struct sdio_dev_s *dev, bool cardinslot) priv->cdstatus &= ~SDIO_STATUS_PRESENT; } - finfo("cdstatus OLD: %02x NEW: %02x\n", cdstatus, priv->cdstatus); + mcinfo("cdstatus OLD: %02x NEW: %02x\n", cdstatus, priv->cdstatus); /* Perform any requested callback if the status has changed */ @@ -2937,7 +2935,7 @@ void sdhc_wrprotect(FAR struct sdio_dev_s *dev, bool wrprotect) priv->cdstatus &= ~SDIO_STATUS_WRPROTECTED; } - finfo("cdstatus: %02x\n", priv->cdstatus); + mcinfo("cdstatus: %02x\n", priv->cdstatus); leave_critical_section(flags); } #endif /* CONFIG_KINETIS_SDHC */ diff --git a/arch/arm/src/kinetis/kinetis_serial.c b/arch/arm/src/kinetis/kinetis_serial.c index 084204daa9..8f7e2b1595 100644 --- a/arch/arm/src/kinetis/kinetis_serial.c +++ b/arch/arm/src/kinetis/kinetis_serial.c @@ -805,7 +805,7 @@ static int up_interrupt(int irq, void *context) */ regval = up_serialin(priv, KINETIS_UART_S1_OFFSET); - _llerr("S1: %02x\n", regval); + _llinfo("S1: %02x\n", regval); UNUSED(regval); regval = up_serialin(priv, KINETIS_UART_D_OFFSET); diff --git a/arch/arm/src/kinetis/kinetis_start.c b/arch/arm/src/kinetis/kinetis_start.c index 6744012f07..f9665a04c4 100644 --- a/arch/arm/src/kinetis/kinetis_start.c +++ b/arch/arm/src/kinetis/kinetis_start.c @@ -156,8 +156,8 @@ void __start(void) /* Show reset status */ - _err("Reset status: %02x:%02x\n", - getreg8(KINETIS_SMC_SRSH), getreg8(KINETIS_SMC_SRSL)); + _llwarn("Reset status: %02x:%02x\n", + getreg8(KINETIS_SMC_SRSH), getreg8(KINETIS_SMC_SRSL)); /* Then start NuttX */ diff --git a/arch/arm/src/kinetis/kinetis_usbdev.c b/arch/arm/src/kinetis/kinetis_usbdev.c index 406880cb2a..d48757f929 100644 --- a/arch/arm/src/kinetis/kinetis_usbdev.c +++ b/arch/arm/src/kinetis/kinetis_usbdev.c @@ -86,7 +86,7 @@ * enabled. */ -#ifndef CONFIG_DEBUG_FEATURES +#ifndef CONFIG_DEBUG_USB_INFO # undef CONFIG_KHCI_USBDEV_REGDEBUG # undef CONFIG_KHCI_USBDEV_BDTDEBUG #endif @@ -365,42 +365,21 @@ const struct trace_msg_t g_usb_trace_strings_deverror[] = */ #ifdef CONFIG_KHCI_USBDEV_REGDEBUG - # undef CONFIG_KHCI_USBDEV_BDTDEBUG # define CONFIG_KHCI_USBDEV_BDTDEBUG 1 - -# define regerr _llerr -# ifdef CONFIG_DEBUG_INFO -# define reginfo _llerr -# else -# define reginfo(x...) -# endif - #else - # define khci_getreg(addr) getreg8(addr) # define khci_putreg(val,addr) putreg8(val,addr) -# define regerr(x...) -# define reginfo(x...) - #endif /* CONFIG_KHCI_USBDEV_BDTDEBUG dumps most BDT settings */ #ifdef CONFIG_KHCI_USBDEV_BDTDEBUG - -# define bdterr _llerr -# ifdef CONFIG_DEBUG_INFO -# define bdtinfo _llerr -# else -# define bdtinfo(x...) -# endif - +# define bdterr ullerr +# define bdtinfo ullinfo #else - # define bdterr(x...) # define bdtinfo(x...) - #endif /**************************************************************************** @@ -714,7 +693,7 @@ static uint16_t khci_getreg(uint32_t addr) { if (count == 4) { - _llerr("...\n"); + ullinfo("...\n"); } return val; } @@ -730,7 +709,7 @@ static uint16_t khci_getreg(uint32_t addr) { /* Yes.. then show how many times the value repeated */ - _llerr("[repeats %d more times]\n", count-3); + ullinfo("[repeats %d more times]\n", count-3); } /* Save the new address, value, and count */ @@ -742,7 +721,7 @@ static uint16_t khci_getreg(uint32_t addr) /* Show the register value read */ - _llerr("%08x->%04x\n", addr, val); + ullinfo("%08x->%04x\n", addr, val); return val; } #endif @@ -756,7 +735,7 @@ static void khci_putreg(uint32_t val, uint32_t addr) { /* Show the register value being written */ - _llerr("%08x<-%04x\n", addr, val); + ullinfo("%08x<-%04x\n", addr, val); /* Write the value */ @@ -953,8 +932,8 @@ static void khci_epwrite(struct khci_ep_s *privep, /* And, finally, give the BDT to the USB */ - bdterr("EP%d BDT IN [%p] {%08x, %08x}\n", - USB_EPNO(privep->ep.eplog), bdt, status, bdt->addr); + bdtinfo("EP%d BDT IN [%p] {%08x, %08x}\n", + USB_EPNO(privep->ep.eplog), bdt, status, bdt->addr); bdt->status = status; } @@ -994,8 +973,8 @@ static void khci_wrcomplete(struct khci_usbdev_s *priv, epno, privreq->req.len, privreq->req.xfrd, privreq->inflight[0], privreq->inflight[1]); #endif - bdterr("EP%d BDT IN [%p] {%08x, %08x}\n", - epno, bdtin, bdtin->status, bdtin->addr); + bdtinfo("EP%d BDT IN [%p] {%08x, %08x}\n", + epno, bdtin, bdtin->status, bdtin->addr); /* We should own the BDT that just completed. But NULLify the entire BDT IN. * Why? So that we can tell later that the BDT available. No, it is not @@ -1419,8 +1398,8 @@ static int khci_rdcomplete(struct khci_usbdev_s *priv, ullinfo("EP%d: len=%d xfrd=%d\n", epno, privreq->req.len, privreq->req.xfrd); - bdterr("EP%d BDT OUT [%p] {%08x, %08x}\n", - epno, bdtout, bdtout->status, bdtout->addr); + bdtinfo("EP%d BDT OUT [%p] {%08x, %08x}\n", + epno, bdtout, bdtout->status, bdtout->addr); /* We should own the BDT that just completed */ @@ -1563,7 +1542,7 @@ static int khci_ep0rdsetup(struct khci_usbdev_s *priv, uint8_t *dest, /* Then give the BDT to the USB */ - bdterr("EP0 BDT OUT [%p] {%08x, %08x}\n", bdtout, status, bdtout->addr); + bdtinfo("EP0 BDT OUT [%p] {%08x, %08x}\n", bdtout, status, bdtout->addr); bdtout->status = status; priv->ctrlstate = CTRLSTATE_RDREQUEST; @@ -1664,7 +1643,8 @@ static int khci_rdsetup(struct khci_ep_s *privep, uint8_t *dest, int readlen) /* Then give the BDT to the USB */ - bdterr("EP%d BDT OUT [%p] {%08x, %08x}\n", epno, bdtout, status, bdtout->addr); + bdtinfo("EP%d BDT OUT [%p] {%08x, %08x}\n", + epno, bdtout, status, bdtout->addr); bdtout->status = status; return OK; @@ -2676,7 +2656,7 @@ static void khci_ep0transfer(struct khci_usbdev_s *priv, uint16_t ustat) bdt = &g_bdt[index]; priv->eplist[0].bdtout = bdt; - bdterr("EP0 BDT OUT [%p] {%08x, %08x}\n", bdt, bdt->status, bdt->addr); + bdtinfo("EP0 BDT OUT [%p] {%08x, %08x}\n", bdt, bdt->status, bdt->addr); /* Check the current EP0 OUT buffer contains a SETUP packet */ @@ -2913,7 +2893,7 @@ x if ((usbir & USB_INT_ERROR) != 0) { usbtrace(TRACE_INTDECODE(KHCI_TRACEINTID_UERR), usbir); - ullerr("Error: EIR=%04x\n", khci_getreg(KINETIS_USB0_ERRSTAT)); + ullerr("ERROR: EIR=%04x\n", khci_getreg(KINETIS_USB0_ERRSTAT)); /* Clear all pending USB error interrupts */ @@ -3299,7 +3279,8 @@ static int khci_epconfigure(struct usbdev_ep_s *ep, bdt->status = 0; bdt->addr = 0; - bdterr("EP%d BDT IN [%p] {%08x, %08x}\n", epno, bdt, bdt->status, bdt->addr); + bdtinfo("EP%d BDT IN [%p] {%08x, %08x}\n", + epno, bdt, bdt->status, bdt->addr); /* Now do the same for the other buffer. */ @@ -3307,7 +3288,8 @@ static int khci_epconfigure(struct usbdev_ep_s *ep, bdt->status = 0; bdt->addr = 0; - bdterr("EP%d BDT IN [%p] {%08x, %08x}\n", epno, bdt, bdt->status, bdt->addr); + bdtinfo("EP%d BDT IN [%p] {%08x, %08x}\n", + epno, bdt, bdt->status, bdt->addr); } if (!epin || bidi) @@ -3321,7 +3303,8 @@ static int khci_epconfigure(struct usbdev_ep_s *ep, bdt->status = 0; bdt->addr = 0; - bdterr("EP%d BDT OUT [%p] {%08x, %08x}\n", epno, bdt, bdt->status, bdt->addr); + bdtinfo("EP%d BDT OUT [%p] {%08x, %08x}\n", + epno, bdt, bdt->status, bdt->addr); /* Now do the same for the other buffer. */ @@ -3329,7 +3312,8 @@ static int khci_epconfigure(struct usbdev_ep_s *ep, bdt->status = 0; bdt->addr = 0; - bdterr("EP%d BDT OUT [%p] {%08x, %08x}\n", epno, bdt, bdt->status, bdt->addr); + bdtinfo("EP%d BDT OUT [%p] {%08x, %08x}\n", + epno, bdt, bdt->status, bdt->addr); } /* Get the maxpacket size of the endpoint. */ @@ -3467,7 +3451,8 @@ static int khci_epsubmit(struct usbdev_ep_s *ep, struct usbdev_req_s *req) if (!req || !req->callback || !req->buf || !ep) { usbtrace(TRACE_DEVERROR(KHCI_TRACEERR_INVALIDPARMS), 0); - ullerr("ERROR: req=%p callback=%p buf=%p ep=%p\n", req, req->callback, req->buf, ep); + ullerr("ERROR: req=%p callback=%p buf=%p ep=%p\n", + req, req->callback, req->buf, ep); return -EINVAL; } #endif @@ -3666,10 +3651,10 @@ static int khci_epbdtstall(struct usbdev_ep_s *ep, bool resume, bool epin) bdt->addr = (uint8_t *)physaddr; bdt->status = (USB_BDT_UOWN | bytecount); - bdterr("EP0 BDT IN [%p] {%08x, %08x}\n", - bdt, bdt->status, bdt->addr); - bdterr("EP0 BDT IN [%p] {%08x, %08x}\n", - otherbdt, otherbdt->status, otherbdt->addr); + bdtinfo("EP0 BDT IN [%p] {%08x, %08x}\n", + bdt, bdt->status, bdt->addr); + bdtinfo("EP0 BDT IN [%p] {%08x, %08x}\n", + otherbdt, otherbdt->status, otherbdt->addr); } else { @@ -3683,10 +3668,10 @@ static int khci_epbdtstall(struct usbdev_ep_s *ep, bool resume, bool epin) bdt->addr = 0; bdt->status = 0; - bdterr("EP%d BDT %s [%p] {%08x, %08x}\n", - epno, epin ? "IN" : "OUT", bdt, bdt->status, bdt->addr); - bdterr("EP%d BDT %s [%p] {%08x, %08x}\n", - epno, epin ? "IN" : "OUT", otherbdt, otherbdt->status, otherbdt->addr); + bdtinfo("EP%d BDT %s [%p] {%08x, %08x}\n", + epno, epin ? "IN" : "OUT", bdt, bdt->status, bdt->addr); + bdtinfo("EP%d BDT %s [%p] {%08x, %08x}\n", + epno, epin ? "IN" : "OUT", otherbdt, otherbdt->status, otherbdt->addr); /* Restart any queued requests (after a delay so that we can be assured * that the hardware has recovered from the stall -- I don't know of any @@ -3718,10 +3703,10 @@ static int khci_epbdtstall(struct usbdev_ep_s *ep, bool resume, bool epin) khci_rqstop(privep); - bdterr("EP%d BDT %s [%p] {%08x, %08x}\n", - epno, epin ? "IN" : "OUT", bdt, bdt->status, bdt->addr); - bdterr("EP%d BDT %s [%p] {%08x, %08x}\n", - epno, epin ? "IN" : "OUT", otherbdt, otherbdt->status, otherbdt->addr); + bdtinfo("EP%d BDT %s [%p] {%08x, %08x}\n", + epno, epin ? "IN" : "OUT", bdt, bdt->status, bdt->addr); + bdtinfo("EP%d BDT %s [%p] {%08x, %08x}\n", + epno, epin ? "IN" : "OUT", otherbdt, otherbdt->status, otherbdt->addr); } return OK; @@ -4248,10 +4233,10 @@ static void khci_hwreset(struct khci_usbdev_s *priv) khci_putreg((uint8_t)((uint32_t)g_bdt >> 16), KINETIS_USB0_BDTPAGE2); khci_putreg((uint8_t)(((uint32_t)g_bdt >> 8) & USB_BDTPAGE1_MASK), KINETIS_USB0_BDTPAGE1); - ullerr("BDT Address %hhx \n" ,&g_bdt); - ullerr("BDTPAGE3 %hhx\n",khci_getreg(KINETIS_USB0_BDTPAGE3)); - ullerr("BDTPAGE2 %hhx\n",khci_getreg(KINETIS_USB0_BDTPAGE2)); - ullerr("BDTPAGE1 %hhx\n",khci_getreg(KINETIS_USB0_BDTPAGE1)); + ullinfo("BDT Address %hhx \n" ,&g_bdt); + ullinfo("BDTPAGE3 %hhx\n",khci_getreg(KINETIS_USB0_BDTPAGE3)); + ullinfo("BDTPAGE2 %hhx\n",khci_getreg(KINETIS_USB0_BDTPAGE2)); + ullinfo("BDTPAGE1 %hhx\n",khci_getreg(KINETIS_USB0_BDTPAGE1)); /* Clear any pending interrupts */ diff --git a/arch/arm/src/kl/kl_pwm.c b/arch/arm/src/kl/kl_pwm.c index 3da236c34c..6f3f6e4050 100644 --- a/arch/arm/src/kl/kl_pwm.c +++ b/arch/arm/src/kl/kl_pwm.c @@ -464,7 +464,7 @@ static int pwm_timer(FAR struct kl_pwmtimer_s *priv, break; default: - pwmerr("No such channel: %d\n", priv->channel); + pwmerr("ERROR: No such channel: %d\n", priv->channel); return -EINVAL; } @@ -644,7 +644,7 @@ static int pwm_stop(FAR struct pwm_lowerhalf_s *dev) break; default: - pwmerr("No such channel: %d\n", priv->channel); + pwmerr("ERROR: No such channel: %d\n", priv->channel); return -EINVAL; } @@ -731,7 +731,7 @@ FAR struct pwm_lowerhalf_s *kl_pwminitialize(int timer) #endif default: - pwmerr("No such timer configured\n"); + pwmerr("ERROR: No such timer configured\n"); return NULL; } diff --git a/arch/arm/src/kl/kl_spi.c b/arch/arm/src/kl/kl_spi.c index abc587caff..e9fb9947cd 100644 --- a/arch/arm/src/kl/kl_spi.c +++ b/arch/arm/src/kl/kl_spi.c @@ -341,7 +341,7 @@ static uint32_t spi_setfrequency(FAR struct spi_dev_s *dev, uint32_t frequency) priv->frequency = frequency; priv->actual = actual; - spierr("Frequency %d->%d\n", frequency, actual); + spiinfo("Frequency %d->%d\n", frequency, actual); return actual; } From 9e048e167f1a594afcbdd2c6757792f7b3883ed7 Mon Sep 17 00:00:00 2001 From: Gregory Nutt Date: Fri, 17 Jun 2016 12:50:18 -0600 Subject: [PATCH 46/75] EFM32/DM320: Convert *err() to either *info() or add ERROR:, depending on if an error is reported --- arch/arm/src/dm320/dm320_framebuffer.c | 4 +-- arch/arm/src/dm320/dm320_usbdev.c | 42 +++++++++++----------- arch/arm/src/efm32/efm32_adc.c | 4 +-- arch/arm/src/efm32/efm32_dma.c | 48 +++++++++++++------------- arch/arm/src/efm32/efm32_dma.h | 6 ++-- arch/arm/src/efm32/efm32_i2c.c | 8 ++--- arch/arm/src/efm32/efm32_pwm.c | 4 +-- arch/arm/src/efm32/efm32_rmu.c | 12 +++---- arch/arm/src/efm32/efm32_rmu.h | 13 +++---- arch/arm/src/efm32/efm32_usbdev.c | 30 +++++++++------- arch/arm/src/efm32/efm32_usbhost.c | 6 ++-- 11 files changed, 89 insertions(+), 88 deletions(-) diff --git a/arch/arm/src/dm320/dm320_framebuffer.c b/arch/arm/src/dm320/dm320_framebuffer.c index ca81e8a848..dcedcb62e5 100644 --- a/arch/arm/src/dm320/dm320_framebuffer.c +++ b/arch/arm/src/dm320/dm320_framebuffer.c @@ -928,7 +928,7 @@ static void dm320_hwinitialize(void) /* Set up the rectangular cursor with defaults */ #ifdef CONFIG_FB_HWCURSOR - gerr("Initialize rectangular cursor\n"); + lcdinfo("Initialize rectangular cursor\n"); putreg16(0, DM320_OSD_CURXP); putreg16(0, DM320_OSD_CURYP); @@ -1385,7 +1385,7 @@ int up_fbinitialize(int display) ret = dm320_allocvideomemory(); if (ret != 0) { - gerr("Failed to allocate video buffers\n"); + lcderr("ERROR: Failed to allocate video buffers\n"); return ret; } diff --git a/arch/arm/src/dm320/dm320_usbdev.c b/arch/arm/src/dm320/dm320_usbdev.c index ad1641db1f..673eba7e4b 100644 --- a/arch/arm/src/dm320/dm320_usbdev.c +++ b/arch/arm/src/dm320/dm320_usbdev.c @@ -268,7 +268,7 @@ struct dm320_epinfo_s /* Register operations */ -#if defined(CONFIG_DM320_USBDEV_REGDEBUG) && defined(CONFIG_DEBUG_FEATURES) +#ifdef CONFIG_DM320_USBDEV_REGDEBUG static uint32_t dm320_getreg8(uint32_t addr); static uint32_t dm320_getreg16(uint32_t addr); static uint32_t dm320_getreg32(uint32_t addr); @@ -422,7 +422,7 @@ static const struct dm320_epinfo_s g_epinfo[DM320_NENDPOINTS] = * ****************************************************************************/ -#if defined(CONFIG_DM320_USBDEV_REGDEBUG) && defined(CONFIG_DEBUG_FEATURES) +#ifdef CONFIG_DM320_USBDEV_REGDEBUG static uint8_t dm320_getreg8(uint32_t addr) { static uint32_t prevaddr = 0; @@ -443,7 +443,7 @@ static uint8_t dm320_getreg8(uint32_t addr) { if (count == 4) { - _llerr("...\n"); + ullinfo("...\n"); } return val; @@ -460,7 +460,7 @@ static uint8_t dm320_getreg8(uint32_t addr) { /* Yes.. then show how many times the value repeated */ - _llerr("[repeats %d more times]\n", count-3); + ullinfo("[repeats %d more times]\n", count-3); } /* Save the new address, value, and count */ @@ -472,7 +472,7 @@ static uint8_t dm320_getreg8(uint32_t addr) /* Show the register value read */ - _llerr("%08x->%02x\n", addr, val); + ullinfo("%08x->%02x\n", addr, val); return val; } #endif @@ -485,7 +485,7 @@ static uint8_t dm320_getreg8(uint32_t addr) * ****************************************************************************/ -#if defined(CONFIG_DM320_USBDEV_REGDEBUG) && defined(CONFIG_DEBUG_FEATURES) +#ifdef CONFIG_DM320_USBDEV_REGDEBUG static uint32_t dm320_getreg16(uint32_t addr) { static uint32_t prevaddr = 0; @@ -506,7 +506,7 @@ static uint32_t dm320_getreg16(uint32_t addr) { if (count == 4) { - _llerr("...\n"); + ullinfo("...\n"); } return val; @@ -523,7 +523,7 @@ static uint32_t dm320_getreg16(uint32_t addr) { /* Yes.. then show how many times the value repeated */ - _llerr("[repeats %d more times]\n", count-3); + ullinfo("[repeats %d more times]\n", count-3); } /* Save the new address, value, and count */ @@ -535,7 +535,7 @@ static uint32_t dm320_getreg16(uint32_t addr) /* Show the register value read */ - _llerr("%08x->%04x\n", addr, val); + ullinfo("%08x->%04x\n", addr, val); return val; } #endif @@ -548,7 +548,7 @@ static uint32_t dm320_getreg16(uint32_t addr) * ****************************************************************************/ -#if defined(CONFIG_DM320_USBDEV_REGDEBUG) && defined(CONFIG_DEBUG_FEATURES) +#ifdef CONFIG_DM320_USBDEV_REGDEBUG static uint32_t dm320_getreg32(uint32_t addr) { static uint32_t prevaddr = 0; @@ -569,7 +569,7 @@ static uint32_t dm320_getreg32(uint32_t addr) { if (count == 4) { - _llerr("...\n"); + ullinfo("...\n"); } return val; @@ -586,7 +586,7 @@ static uint32_t dm320_getreg32(uint32_t addr) { /* Yes.. then show how many times the value repeated */ - _llerr("[repeats %d more times]\n", count-3); + ullinfo("[repeats %d more times]\n", count-3); } /* Save the new address, value, and count */ @@ -598,7 +598,7 @@ static uint32_t dm320_getreg32(uint32_t addr) /* Show the register value read */ - _llerr("%08x->%08x\n", addr, val); + ullinfo("%08x->%08x\n", addr, val); return val; } #endif @@ -611,12 +611,12 @@ static uint32_t dm320_getreg32(uint32_t addr) * ****************************************************************************/ -#if defined(CONFIG_DM320_USBDEV_REGDEBUG) && defined(CONFIG_DEBUG_FEATURES) +#ifdef CONFIG_DM320_USBDEV_REGDEBUG static void dm320_putreg8(uint8_t val, uint32_t addr) { /* Show the register value being written */ - _llerr("%08x<-%02x\n", addr, val); + ullinfo("%08x<-%02x\n", addr, val); /* Write the value */ @@ -632,12 +632,12 @@ static void dm320_putreg8(uint8_t val, uint32_t addr) * ****************************************************************************/ -#if defined(CONFIG_DM320_USBDEV_REGDEBUG) && defined(CONFIG_DEBUG_FEATURES) +#ifdef CONFIG_DM320_USBDEV_REGDEBUG static void dm320_putreg16(uint16_t val, uint32_t addr) { /* Show the register value being written */ - _llerr("%08x<-%04x\n", addr, val); + ullinfo("%08x<-%04x\n", addr, val); /* Write the value */ @@ -653,12 +653,12 @@ static void dm320_putreg16(uint16_t val, uint32_t addr) * ****************************************************************************/ -#if defined(CONFIG_DM320_USBDEV_REGDEBUG) && defined(CONFIG_DEBUG_FEATURES) +#ifdef CONFIG_DM320_USBDEV_REGDEBUG static void dm320_putreg32(uint32_t val, uint32_t addr) { /* Show the register value being written */ - _llerr("%08x<-%08x\n", addr, val); + ullinfo("%08x<-%08x\n", addr, val); /* Write the value */ @@ -2415,9 +2415,9 @@ void up_usbinitialize(void) memset(priv, 0, sizeof(struct dm320_usbdev_s)); priv->usbdev.ops = &g_devops; -#ifdef CONFIG_DEBUG_USB +#ifdef CONFIG_DEBUG_USB_INFO chiprev = dm320_getreg16(DM320_BUSC_REVR); - ullerr("DM320 revision : %d.%d\n", chiprev >> 4, chiprev & 0x0f); + ullinfo("DM320 revision : %d.%d\n", chiprev >> 4, chiprev & 0x0f); #endif /* Enable USB clock & GIO clock */ diff --git a/arch/arm/src/efm32/efm32_adc.c b/arch/arm/src/efm32/efm32_adc.c index bc652fc59e..20deacf2bc 100644 --- a/arch/arm/src/efm32/efm32_adc.c +++ b/arch/arm/src/efm32/efm32_adc.c @@ -1191,7 +1191,7 @@ static int adc_interrupt(FAR struct adc_dev_s *dev) adcsr = adc_getreg(priv, EFM32_ADC_SR_OFFSET); if ((adcsr & ADC_SR_AWD) != 0) { - allerr("WARNING: Analog Watchdog, Value converted out of range!\n"); + allwarn("WARNING: Analog Watchdog, Value converted out of range!\n"); } /* EOC: End of conversion */ @@ -1298,7 +1298,7 @@ struct adc_dev_s *efm32_adcinitialize(int intf, const uint8_t *chanlist, int nch else #endif { - aerr("No ADC interface defined\n"); + aerr("ERROR: No ADC interface defined\n"); return NULL; } diff --git a/arch/arm/src/efm32/efm32_dma.c b/arch/arm/src/efm32/efm32_dma.c index de260de00d..6677732321 100644 --- a/arch/arm/src/efm32/efm32_dma.c +++ b/arch/arm/src/efm32/efm32_dma.c @@ -745,7 +745,7 @@ void efm32_dmastop(DMA_HANDLE handle) * ****************************************************************************/ -#ifdef CONFIG_DEBUG_DMA +#ifdef CONFIG_DEBUG_DMA_INFO void efm32_dmasample(DMA_HANDLE handle, struct efm32_dmaregs_s *regs) { struct dma_channel_s *dmach = (struct dma_channel_s *)handle; @@ -798,35 +798,35 @@ void efm32_dmasample(DMA_HANDLE handle, struct efm32_dmaregs_s *regs) * ****************************************************************************/ -#ifdef CONFIG_DEBUG_DMA +#ifdef CONFIG_DEBUG_DMA_INFO void efm32_dmadump(DMA_HANDLE handle, const struct efm32_dmaregs_s *regs, const char *msg) { struct dma_channel_s *dmach = (struct dma_channel_s *)handle; - dmaerr("%s\n", msg); - dmaerr(" DMA Registers:\n"); - dmaerr(" STATUS: %08x\n", regs->status); - dmaerr(" CTRLBASE: %08x\n", regs->ctrlbase); - dmaerr(" ALTCTRLBASE: %08x\n", regs->altctrlbase); - dmaerr(" CHWAITSTATUS: %08x\n", regs->chwaitstatus); - dmaerr(" CHUSEBURSTS: %08x\n", regs->chusebursts); - dmaerr(" CHREQMASKS: %08x\n", regs->chreqmasks); - dmaerr(" CHENS: %08x\n", regs->chens); - dmaerr(" CHALTS: %08x\n", regs->chalts); - dmaerr(" CHPRIS: %08x\n", regs->chpris); - dmaerr(" ERRORC: %08x\n", regs->errorc); - dmaerr(" CHREQSTATUS: %08x\n", regs->chreqstatus); - dmaerr(" CHSREQSTATUS: %08x\n", regs->chsreqstatus); - dmaerr(" IEN: %08x\n", regs->ien); + dmainfo("%s\n", msg); + dmainfo(" DMA Registers:\n"); + dmainfo(" STATUS: %08x\n", regs->status); + dmainfo(" CTRLBASE: %08x\n", regs->ctrlbase); + dmainfo(" ALTCTRLBASE: %08x\n", regs->altctrlbase); + dmainfo(" CHWAITSTATUS: %08x\n", regs->chwaitstatus); + dmainfo(" CHUSEBURSTS: %08x\n", regs->chusebursts); + dmainfo(" CHREQMASKS: %08x\n", regs->chreqmasks); + dmainfo(" CHENS: %08x\n", regs->chens); + dmainfo(" CHALTS: %08x\n", regs->chalts); + dmainfo(" CHPRIS: %08x\n", regs->chpris); + dmainfo(" ERRORC: %08x\n", regs->errorc); + dmainfo(" CHREQSTATUS: %08x\n", regs->chreqstatus); + dmainfo(" CHSREQSTATUS: %08x\n", regs->chsreqstatus); + dmainfo(" IEN: %08x\n", regs->ien); #if defined(CONFIG_EFM32_EFM32GG) - dmaerr(" CTRL: %08x\n", regs->ctrl); - dmaerr(" RDS: %08x\n", regs->rds); - dmaerr(" LOOP0: %08x\n", regs->loop0); - dmaerr(" LOOP1: %08x\n", regs->loop1); - dmaerr(" RECT0: %08x\n", regs->rect0); + dmainfo(" CTRL: %08x\n", regs->ctrl); + dmainfo(" RDS: %08x\n", regs->rds); + dmainfo(" LOOP0: %08x\n", regs->loop0); + dmainfo(" LOOP1: %08x\n", regs->loop1); + dmainfo(" RECT0: %08x\n", regs->rect0); #endif - dmaerr(" DMA Channel %d Registers:\n", dmach->chan); - dmaerr(" CHCTRL: %08x\n", regs->chnctrl); + dmainfo(" DMA Channel %d Registers:\n", dmach->chan); + dmainfo(" CHCTRL: %08x\n", regs->chnctrl); } #endif diff --git a/arch/arm/src/efm32/efm32_dma.h b/arch/arm/src/efm32/efm32_dma.h index 2cedb881f3..011a7d9874 100644 --- a/arch/arm/src/efm32/efm32_dma.h +++ b/arch/arm/src/efm32/efm32_dma.h @@ -109,7 +109,7 @@ typedef FAR void *DMA_HANDLE; typedef void (*dma_callback_t)(DMA_HANDLE handle, uint8_t status, void *arg); -#ifdef CONFIG_DEBUG_DMA +#ifdef CONFIG_DEBUG_DMA_INFO struct efm32_dmaregs_s { uint32_t status; /* DMA Status Register */ @@ -282,7 +282,7 @@ void efm32_dmastop(DMA_HANDLE handle); * ************************************************************************************/ -#ifdef CONFIG_DEBUG_DMA +#ifdef CONFIG_DEBUG_DMA_INFO void efm32_dmasample(DMA_HANDLE handle, struct efm32_dmaregs_s *regs); #else # define efm32_dmasample(handle,regs) @@ -299,7 +299,7 @@ void efm32_dmasample(DMA_HANDLE handle, struct efm32_dmaregs_s *regs); * ************************************************************************************/ -#ifdef CONFIG_DEBUG_DMA +#ifdef CONFIG_DEBUG_DMA_INFO void efm32_dmadump(DMA_HANDLE handle, const struct efm32_dmaregs_s *regs, const char *msg); #else diff --git a/arch/arm/src/efm32/efm32_i2c.c b/arch/arm/src/efm32/efm32_i2c.c index c139ea012a..d05f9ae22a 100644 --- a/arch/arm/src/efm32/efm32_i2c.c +++ b/arch/arm/src/efm32/efm32_i2c.c @@ -751,7 +751,7 @@ static void efm32_i2c_tracenew(FAR struct efm32_i2c_priv_s *priv) if (priv->tndx >= (CONFIG_I2C_NTRACE - 1)) { - i2cerr("Trace table overflow\n"); + i2cerr("ERROR: Trace table overflow\n"); return; } @@ -1526,9 +1526,9 @@ static int efm32_i2c_transfer(FAR struct i2c_master_s *dev, { ret = -ETIMEDOUT; - i2cerr("Timed out: I2Cx_STATE: 0x%04x I2Cx_STATUS: 0x%08x\n", - efm32_i2c_getreg(priv, EFM32_I2C_STATE_OFFSET), - efm32_i2c_getreg(priv, EFM32_I2C_STATUS_OFFSET)); + i2cerr("ERROR: Timed out: I2Cx_STATE: 0x%04x I2Cx_STATUS: 0x%08x\n", + efm32_i2c_getreg(priv, EFM32_I2C_STATE_OFFSET), + efm32_i2c_getreg(priv, EFM32_I2C_STATUS_OFFSET)); /* Abort */ diff --git a/arch/arm/src/efm32/efm32_pwm.c b/arch/arm/src/efm32/efm32_pwm.c index 0f149f8dc4..b73c9bbdd8 100644 --- a/arch/arm/src/efm32/efm32_pwm.c +++ b/arch/arm/src/efm32/efm32_pwm.c @@ -395,7 +395,7 @@ static int pwm_timer(FAR struct efm32_pwmtimer_s *priv, if (efm32_timer_set_freq(priv->base, priv->pclk, info->frequency) < 0) { - pwmerr("Cannot set TIMER frequency %dHz from clock %dHz\n", + pwmerr("ERROR: Cannot set TIMER frequency %dHz from clock %dHz\n", info->frequency, priv->pclk); return -EINVAL; } @@ -914,7 +914,7 @@ FAR struct pwm_lowerhalf_s *efm32_pwminitialize(int timer) #endif default: - pwmerr("No such timer configured\n"); + pwmerr("ERROR: No such timer configured\n"); return NULL; } diff --git a/arch/arm/src/efm32/efm32_rmu.c b/arch/arm/src/efm32/efm32_rmu.c index 1d30cb2b40..57d7b0e02b 100644 --- a/arch/arm/src/efm32/efm32_rmu.c +++ b/arch/arm/src/efm32/efm32_rmu.c @@ -63,7 +63,7 @@ * Private Types ************************************************************************************/ -#ifdef CONFIG_EFM32_RMU_DEBUG +#if defined(CONFIG_EFM32_RMU_DEBUG) && defined(CONFIG_DEBUG_WARN) typedef struct { const uint32_t val; @@ -76,7 +76,7 @@ typedef struct * Private Data ************************************************************************************/ -#ifdef CONFIG_EFM32_RMU_DEBUG +#if defined(CONFIG_EFM32_RMU_DEBUG) && defined(CONFIG_DEBUG_WARN) static efm32_reset_cause_list_t efm32_reset_cause_list[] = { { @@ -191,7 +191,7 @@ uint32_t g_efm32_rstcause; * ************************************************************************************/ -#ifdef CONFIG_EFM32_RMU_DEBUG +#if defined(CONFIG_EFM32_RMU_DEBUG) && defined(CONFIG_DEBUG_WARN) const char *efm32_reset_cause_list_str(uint32_t reg, unsigned int *idx) { int len = sizeof(efm32_reset_cause_list)/sizeof(efm32_reset_cause_list[0]); @@ -261,8 +261,8 @@ void efm32_rmu_initialize(void) putreg32(EMU_LOCK_LOCKKEY_LOCK, EMU_LOCK_LOCKKEY_LOCK); } -#ifdef CONFIG_EFM32_RMU_DEBUG - rmuerr("RMU => reg = 0x%08X\n", g_efm32_rstcause); +#if defined(CONFIG_EFM32_RMU_DEBUG) && defined(CONFIG_DEBUG_WARN) + rmuwarn("RMU => reg = 0x%08X\n", g_efm32_rstcause); for (; ; ) { const char *str; @@ -273,7 +273,7 @@ void efm32_rmu_initialize(void) break; } - rmuerr("RMU => %s\n", str); + rmuwarn("RMU => %s\n", str); } #endif } diff --git a/arch/arm/src/efm32/efm32_rmu.h b/arch/arm/src/efm32/efm32_rmu.h index 215f0c85e8..709c53e48d 100644 --- a/arch/arm/src/efm32/efm32_rmu.h +++ b/arch/arm/src/efm32/efm32_rmu.h @@ -50,20 +50,17 @@ ****************************************************************************/ /* Configuration ************************************************************/ -#ifndef CONFIG_DEBUG_FEATURES -# undef CONFIG_DEBUG_INFO +#ifndef CONFIG_DEBUG_ERROR # undef CONFIG_EFM32_RMU_DEBUG #endif #ifdef CONFIG_EFM32_RMU_DEBUG -# define rmuerr _llerr -# ifdef CONFIG_DEBUG_INFO -# define rmuinfo _llerr -# else -# define rmuinfo(x...) -# endif +# define rmuerr _llerr +# define rmuwarn _llwarn +# define rmuinfo _llinfo #else # define rmuerr(x...) +# define rmuwarn(x...) # define rmuinfo(x...) #endif diff --git a/arch/arm/src/efm32/efm32_usbdev.c b/arch/arm/src/efm32/efm32_usbdev.c index 207cce2e94..7bea4d4c4d 100644 --- a/arch/arm/src/efm32/efm32_usbdev.c +++ b/arch/arm/src/efm32/efm32_usbdev.c @@ -114,6 +114,10 @@ # error "FIFO allocations exceed FIFO memory size" #endif +#ifndef CONFIG_DEBUG_USB_INFO +# undef CONFIG_EFM32_USBDEV_REGDEBUG +#endif + /* The actual FIFO addresses that we use must be aligned to 4-byte boundaries; * FIFO sizes must be provided in units of 32-bit words. */ @@ -474,7 +478,7 @@ struct efm32_usbdev_s /* Register operations ********************************************************/ -#if defined(CONFIG_EFM32_USBDEV_REGDEBUG) && defined(CONFIG_DEBUG_FEATURES) +#ifdef CONFIG_EFM32_USBDEV_REGDEBUG static uint32_t efm32_getreg(uint32_t addr); static void efm32_putreg(uint32_t val, uint32_t addr); #else @@ -794,7 +798,7 @@ const struct trace_msg_t g_usb_trace_strings_intdecode[] = * ****************************************************************************/ -#if defined(CONFIG_EFM32_USBDEV_REGDEBUG) && defined(CONFIG_DEBUG_FEATURES) +#ifdef CONFIG_EFM32_USBDEV_REGDEBUG static uint32_t efm32_getreg(uint32_t addr) { static uint32_t prevaddr = 0; @@ -815,7 +819,7 @@ static uint32_t efm32_getreg(uint32_t addr) { if (count == 4) { - _llerr("...\n"); + ullinfo("...\n"); } return val; @@ -832,7 +836,7 @@ static uint32_t efm32_getreg(uint32_t addr) { /* Yes.. then show how many times the value repeated */ - _llerr("[repeats %d more times]\n", count-3); + ullinfo("[repeats %d more times]\n", count-3); } /* Save the new address, value, and count */ @@ -844,7 +848,7 @@ static uint32_t efm32_getreg(uint32_t addr) /* Show the register value read */ - _llerr("%08x->%08x\n", addr, val); + ullinfo("%08x->%08x\n", addr, val); return val; } #endif @@ -857,12 +861,12 @@ static uint32_t efm32_getreg(uint32_t addr) * ****************************************************************************/ -#if defined(CONFIG_EFM32_USBDEV_REGDEBUG) && defined(CONFIG_DEBUG_FEATURES) +#ifdef CONFIG_EFM32_USBDEV_REGDEBUG static void efm32_putreg(uint32_t val, uint32_t addr) { /* Show the register value being written */ - _llerr("%08x<-%08x\n", addr, val); + ullinfo("%08x<-%08x\n", addr, val); /* Write the value */ @@ -2629,7 +2633,7 @@ static inline void efm32_epout_interrupt(FAR struct efm32_usbdev_s *priv) if ((daint & 1) != 0) { regval = efm32_getreg(EFM32_USB_DOEPINT(epno)); - ullerr("DOEPINT(%d) = %08x\n", epno, regval); + ullinfo("DOEPINT(%d) = %08x\n", epno, regval); efm32_putreg(0xFF, EFM32_USB_DOEPINT(epno)); } @@ -2859,8 +2863,8 @@ static inline void efm32_epin_interrupt(FAR struct efm32_usbdev_s *priv) { if ((daint & 1) != 0) { - ullerr("DIEPINT(%d) = %08x\n", - epno, efm32_getreg(EFM32_USB_DIEPINT(epno))); + ullinfo("DIEPINT(%d) = %08x\n", + epno, efm32_getreg(EFM32_USB_DIEPINT(epno))); efm32_putreg(0xFF, EFM32_USB_DIEPINT(epno)); } @@ -3799,7 +3803,7 @@ static int efm32_epout_configure(FAR struct efm32_ep_s *privep, uint8_t eptype, break; default: - uerr("Unsupported maxpacket: %d\n", maxpacket); + uerr("ERROR: Unsupported maxpacket: %d\n", maxpacket); return -EINVAL; } } @@ -3894,7 +3898,7 @@ static int efm32_epin_configure(FAR struct efm32_ep_s *privep, uint8_t eptype, break; default: - uerr("Unsupported maxpacket: %d\n", maxpacket); + uerr("ERROR: Unsupported maxpacket: %d\n", maxpacket); return -EINVAL; } } @@ -5482,7 +5486,7 @@ void up_usbinitialize(void) ret = irq_attach(EFM32_IRQ_USB, efm32_usbinterrupt); if (ret < 0) { - uerr("irq_attach failed\n", ret); + uerr("ERROR: irq_attach failed\n", ret); goto errout; } diff --git a/arch/arm/src/efm32/efm32_usbhost.c b/arch/arm/src/efm32/efm32_usbhost.c index ccfd96e34b..83ee505105 100644 --- a/arch/arm/src/efm32/efm32_usbhost.c +++ b/arch/arm/src/efm32/efm32_usbhost.c @@ -123,7 +123,7 @@ /* Register/packet debug depends on CONFIG_DEBUG_FEATURES */ -#ifndef CONFIG_DEBUG_FEATURES +#ifndef CONFIG_DEBUG_USB_INFO # undef CONFIG_EFM32_USBHOST_REGDEBUG # undef CONFIG_EFM32_USBHOST_PKTDUMP #endif @@ -582,7 +582,7 @@ static const struct efm32_usbhost_trace_s g_trace2[TRACE2_NSTRINGS] = #ifdef CONFIG_EFM32_USBHOST_REGDEBUG static void efm32_printreg(uint32_t addr, uint32_t val, bool iswrite) { - _llerr("%08x%s%08x\n", addr, iswrite ? "<-" : "->", val); + ullinfo("%08x%s%08x\n", addr, iswrite ? "<-" : "->", val); } #endif @@ -632,7 +632,7 @@ static void efm32_checkreg(uint32_t addr, uint32_t val, bool iswrite) { /* No.. More than one. */ - _llerr("[repeats %d more times]\n", count); + ullinfo("[repeats %d more times]\n", count); } } From a56812a3359ce4ba521af47519adb8e6de2c5b1f Mon Sep 17 00:00:00 2001 From: Gregory Nutt Date: Fri, 17 Jun 2016 14:46:02 -0600 Subject: [PATCH 47/75] Spurious 'else' in previous commit removed --- arch/arm/src/stm32l4/stm32l4_gpio.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/src/stm32l4/stm32l4_gpio.c b/arch/arm/src/stm32l4/stm32l4_gpio.c index d7f3dce3ee..0c3432d6e4 100644 --- a/arch/arm/src/stm32l4/stm32l4_gpio.c +++ b/arch/arm/src/stm32l4/stm32l4_gpio.c @@ -308,7 +308,7 @@ int stm32l4_configgpio(uint32_t cfgset) /* Otherwise, it is an input pin. Should it configured as an EXTI interrupt? */ - else if ((cfgset & GPIO_EXTI) != 0) + if ((cfgset & GPIO_EXTI) != 0) { #if 0 /* "In STM32 F1 the selection of the EXTI line source is performed through From ac18dc27ca0f5dffd3c68ba7e625f9f25e23b9bb Mon Sep 17 00:00:00 2001 From: Gregory Nutt Date: Fri, 17 Jun 2016 15:21:07 -0600 Subject: [PATCH 48/75] Common/Calypso/C5471: Convert *err() to either *info() or add ERROR:, depending on if an error is reported --- arch/arm/src/c5471/c5471_ethernet.c | 40 ++++++++++++++-------------- arch/arm/src/c5471/c5471_watchdog.c | 39 ++++++++++++--------------- arch/arm/src/calypso/calypso_spi.c | 12 ++++----- arch/arm/src/calypso/calypso_uwire.c | 8 +++--- arch/arm/src/common/up_exit.c | 32 +++++++++++++--------- arch/arm/src/common/up_initialize.c | 4 +-- arch/arm/src/common/up_internal.h | 4 +++ arch/avr/src/common/up_exit.c | 12 +++++++-- arch/avr/src/common/up_internal.h | 4 +++ arch/hc/src/common/up_exit.c | 10 +++---- arch/hc/src/common/up_internal.h | 4 +++ arch/mips/src/common/up_exit.c | 10 +++---- arch/mips/src/common/up_internal.h | 4 +++ arch/sh/src/common/up_exit.c | 10 +++---- arch/x86/src/common/up_exit.c | 10 +++---- arch/x86/src/common/up_internal.h | 4 +++ arch/z16/src/common/up_exit.c | 12 +++++++-- arch/z16/src/common/up_internal.h | 4 +++ arch/z80/src/common/up_exit.c | 22 +++++++-------- arch/z80/src/common/up_internal.h | 4 +++ 20 files changed, 148 insertions(+), 101 deletions(-) diff --git a/arch/arm/src/c5471/c5471_ethernet.c b/arch/arm/src/c5471/c5471_ethernet.c index 38d894e74e..8d08b48e4a 100644 --- a/arch/arm/src/c5471/c5471_ethernet.c +++ b/arch/arm/src/c5471/c5471_ethernet.c @@ -737,22 +737,22 @@ static int c5471_phyinit (void) phyid = (c5471_mdread(0, MD_PHY_MSB_REG) << 16) | c5471_mdread(0, MD_PHY_LSB_REG); if (phyid != LU3X31_T64_PHYID) { - nerr("Unrecognized PHY ID: %08x\n", phyid); + nerr("ERROR: Unrecognized PHY ID: %08x\n", phyid); return ERROR; } /* Next, Set desired network rate, 10BaseT, 100BaseT, or auto. */ #ifdef CONFIG_C5471_AUTONEGOTIATION - nerr("Setting PHY Transceiver for Autonegotiation\n"); + ninfo("Setting PHY Transceiver for Autonegotiation\n"); c5471_mdwrite(0, MD_PHY_CONTROL_REG, MODE_AUTONEG); #endif #ifdef CONFIG_C5471_BASET100 - nerr("Setting PHY Transceiver for 100BaseT FullDuplex\n"); + ninfo("Setting PHY Transceiver for 100BaseT FullDuplex\n"); c5471_mdwrite(0, MD_PHY_CONTROL_REG, MODE_100MBIT_FULLDUP); #endif #ifdef CONFIG_C5471_BASET10 - nerr("Setting PHY Transceiver for 10BaseT FullDuplex\n"); + ninfo("Setting PHY Transceiver for 10BaseT FullDuplex\n"); c5471_mdwrite(0, MD_PHY_CONTROL_REG, MODE_10MBIT_FULLDUP); #endif @@ -1371,7 +1371,7 @@ static void c5471_receive(struct c5471_driver_s *c5471) { /* Increment the count of dropped packets */ - nerr("Too big! packetlen: %d\n", packetlen); + nwarn("WARNING: Too big! packetlen: %d\n", packetlen); c5471->c_rxdropped++; } #endif @@ -1680,9 +1680,9 @@ static int c5471_ifup(struct net_driver_s *dev) struct c5471_driver_s *c5471 = (struct c5471_driver_s *)dev->d_private; volatile uint32_t clearbits; - nerr("Bringing up: %d.%d.%d.%d\n", - dev->d_ipaddr & 0xff, (dev->d_ipaddr >> 8) & 0xff, - (dev->d_ipaddr >> 16) & 0xff, dev->d_ipaddr >> 24); + ninfo("Bringing up: %d.%d.%d.%d\n", + dev->d_ipaddr & 0xff, (dev->d_ipaddr >> 8) & 0xff, + (dev->d_ipaddr >> 16) & 0xff, dev->d_ipaddr >> 24); /* Initilize Ethernet interface */ @@ -1742,7 +1742,7 @@ static int c5471_ifdown(struct net_driver_s *dev) struct c5471_driver_s *c5471 = (struct c5471_driver_s *)dev->d_private; irqstate_t flags; - nerr("Stopping\n"); + ninfo("Stopping\n"); /* Disable the Ethernet interrupt */ @@ -1798,7 +1798,7 @@ static int c5471_txavail(struct net_driver_s *dev) struct c5471_driver_s *c5471 = (struct c5471_driver_s *)dev->d_private; irqstate_t flags; - nerr("Polling\n"); + ninfo("Polling\n"); flags = enter_critical_section(); /* Ignore the notification if the interface is not yet up */ @@ -1951,7 +1951,7 @@ static void c5471_eimconfig(struct c5471_driver_s *c5471) /* TX ENET 0 */ - nerr("TX ENET0 desc: %08x pbuf: %08x\n", desc, pbuf); + ninfo("TX ENET0 desc: %08x pbuf: %08x\n", desc, pbuf); putreg32((desc & 0x0000ffff), ENET0_TDBA); /* 16-bit offset address */ for (i = NUM_DESC_TX-1; i >= 0; i--) { @@ -1978,7 +1978,7 @@ static void c5471_eimconfig(struct c5471_driver_s *c5471) /* RX ENET 0 */ - nerr("RX ENET0 desc: %08x pbuf: %08x\n", desc, pbuf); + ninfo("RX ENET0 desc: %08x pbuf: %08x\n", desc, pbuf); putreg32((desc & 0x0000ffff), ENET0_RDBA); /* 16-bit offset address */ for (i = NUM_DESC_RX-1; i >= 0; i--) { @@ -2005,7 +2005,7 @@ static void c5471_eimconfig(struct c5471_driver_s *c5471) /* TX CPU */ - nerr("TX CPU desc: %08x pbuf: %08x\n", desc, pbuf); + ninfo("TX CPU desc: %08x pbuf: %08x\n", desc, pbuf); c5471->c_txcpudesc = desc; putreg32((desc & 0x0000ffff), EIM_CPU_TXBA); /* 16-bit offset address */ for (i = NUM_DESC_TX-1; i >= 0; i--) @@ -2035,7 +2035,7 @@ static void c5471_eimconfig(struct c5471_driver_s *c5471) /* RX CPU */ - nerr("RX CPU desc: %08x pbuf: %08x\n", desc, pbuf); + ninfo("RX CPU desc: %08x pbuf: %08x\n", desc, pbuf); c5471->c_rxcpudesc = desc; putreg32((desc & 0x0000ffff), EIM_CPU_RXBA); /* 16-bit offset address */ for (i = NUM_DESC_RX-1; i >= 0; i--) @@ -2063,7 +2063,7 @@ static void c5471_eimconfig(struct c5471_driver_s *c5471) pbuf += sizeof(uint32_t); /* Ether Module's "Buffer Usage Word" */ } - nerr("END desc: %08x pbuf: %08x\n", desc, pbuf); + ninfo("END desc: %08x pbuf: %08x\n", desc, pbuf); /* Save the descriptor packet size */ @@ -2150,13 +2150,13 @@ static void c5471_eimconfig(struct c5471_driver_s *c5471) static void c5471_reset(struct c5471_driver_s *c5471) { #if defined(CONFIG_C5471_PHY_LU3X31T_T64) - nerr("EIM reset\n"); + ninfo("EIM reset\n"); c5471_eimreset(c5471); #endif - nerr("PHY init\n"); + ninfo("PHY init\n"); c5471_phyinit(); - nerr("EIM config\n"); + ninfo("EIM config\n"); c5471_eimconfig(c5471); } @@ -2178,7 +2178,7 @@ static void c5471_macassign(struct c5471_driver_s *c5471) uint8_t *mptr = dev->d_mac.ether_addr_octet; register uint32_t tmp; - nerr("MAC: %0x:%0x:%0x:%0x:%0x:%0x\n", + ninfo("MAC: %0x:%0x:%0x:%0x:%0x:%0x\n", mptr[0], mptr[1], mptr[2], mptr[3], mptr[4], mptr[5]); /* Set CPU port MAC address. S/W will only see incoming packets that match @@ -2241,7 +2241,7 @@ void up_netinitialize(void) { /* We could not attach the ISR to the ISR */ - nllerr("irq_attach() failed\n"); + nllerr("ERROR: irq_attach() failed\n"); return; } diff --git a/arch/arm/src/c5471/c5471_watchdog.c b/arch/arm/src/c5471/c5471_watchdog.c index 51363ec8df..0329d7057c 100644 --- a/arch/arm/src/c5471/c5471_watchdog.c +++ b/arch/arm/src/c5471/c5471_watchdog.c @@ -155,7 +155,7 @@ static inline unsigned int wdt_prescaletoptv(unsigned int prescale) } } - _err("prescale=%d -> ptv=%d\n", prescale, ptv); + wdinfo("prescale=%d -> ptv=%d\n", prescale, ptv); return ptv; } @@ -173,7 +173,7 @@ static int wdt_setusec(uint32_t usec) uint32_t divisor = 1; uint32_t mode; - _err("usec=%d\n", usec); + wdinfo("usec=%d\n", usec); /* Calculate a value of prescaler and divisor that will be able * to count to the usec. It may not be exact or the best @@ -186,7 +186,7 @@ static int wdt_setusec(uint32_t usec) do { divisor = (CLOCK_MHZx2 * usec) / (prescaler * 2); - _err("divisor=0x%x prescaler=0x%x\n", divisor, prescaler); + wdinfo("divisor=0x%x prescaler=0x%x\n", divisor, prescaler); if (divisor >= 0x10000) { @@ -194,7 +194,7 @@ static int wdt_setusec(uint32_t usec) { /* This is the max possible ~2.5 seconds. */ - _err("prescaler=0x%x too big!\n", prescaler); + wderr("ERROR: prescaler=0x%x too big!\n", prescaler); return ERROR; } @@ -207,19 +207,19 @@ static int wdt_setusec(uint32_t usec) } while (divisor >= 0x10000); - _err("prescaler=0x%x divisor=0x%x\n", prescaler, divisor); + wdinfo("prescaler=0x%x divisor=0x%x\n", prescaler, divisor); mode = wdt_prescaletoptv(prescaler); mode &= ~C5471_TIMER_AUTORELOAD; /* One shot mode. */ mode |= divisor << 5; - _err("mode=0x%x\n", mode); + wdinfo("mode=0x%x\n", mode); c5471_wdt_cntl = mode; /* Now start the watchdog */ c5471_wdt_cntl |= C5471_TIMER_STARTBIT; - _err("cntl_timer=0x%x\n", c5471_wdt_cntl); + wdinfo("cntl_timer=0x%x\n", c5471_wdt_cntl); return 0; } @@ -234,17 +234,17 @@ static int wdt_setusec(uint32_t usec) static int wdt_interrupt(int irq, void *context) { - _err("expired\n"); + wdllinfo("expired\n"); #if defined(CONFIG_SOFTWARE_REBOOT) # if defined(CONFIG_SOFTWARE_TEST) - _err(" Test only\n"); + wdllinfo(" Test only\n"); # else - _err(" Re-booting\n"); + wdllinfo(" Re-booting\n"); # warning "Add logic to reset CPU here" # endif #else - _err(" No reboot\n"); + wdllinfo(" No reboot\n"); #endif return OK; } @@ -259,7 +259,7 @@ static ssize_t wdt_read(struct file *filep, char *buffer, size_t buflen) * not work if the user provides a buffer smaller than 18 bytes. */ - _err("buflen=%d\n", buflen); + wdinfo("buflen=%d\n", buflen); if (buflen >= 18) { sprintf(buffer, "%08x %08x\n", c5471_wdt_cntl, c5471_wdt_count); @@ -274,7 +274,7 @@ static ssize_t wdt_read(struct file *filep, char *buffer, size_t buflen) static ssize_t wdt_write(struct file *filep, const char *buffer, size_t buflen) { - _err("buflen=%d\n", buflen); + wdinfo("buflen=%d\n", buflen); if (buflen) { /* Reset the timer to the maximum delay */ @@ -292,7 +292,7 @@ static ssize_t wdt_write(struct file *filep, const char *buffer, size_t buflen) static int wdt_ioctl(FAR struct file *filep, int cmd, unsigned long arg) { - _err("ioctl Call: cmd=0x%x arg=0x%x", cmd, arg); + wdinfo("ioctl Call: cmd=0x%x arg=0x%x", cmd, arg); /* Process the IOCTL command (see arch/watchdog.h) */ @@ -315,8 +315,6 @@ static int wdt_ioctl(FAR struct file *filep, int cmd, unsigned long arg) static int wdt_open(struct file *filep) { - _err(""); - if (g_wdtopen) { return -EBUSY; @@ -339,11 +337,8 @@ static int wdt_open(struct file *filep) static int wdt_close(struct file *filep) { - _err(""); - /* The task controlling the watchdog has terminated. Take the timer - * the - * watchdog in interrupt mode -- we are going to reset unless the + * the watchdog in interrupt mode -- we are going to reset unless the * reopened again soon. */ @@ -367,7 +362,7 @@ int up_wdtinit(void) { int ret; - _err("C547x Watchdog Driver\n"); + wdinfo("C547x Watchdog Driver\n"); /* Register as /dev/wdt */ @@ -379,7 +374,7 @@ int up_wdtinit(void) /* Register for an interrupt level callback through wdt_interrupt */ - _err("Attach to IRQ=%d\n", C5471_IRQ_WATCHDOG); + wdinfo("Attach to IRQ=%d\n", C5471_IRQ_WATCHDOG); /* Make sure that the timer is stopped */ diff --git a/arch/arm/src/calypso/calypso_spi.c b/arch/arm/src/calypso/calypso_spi.c index 6278c32707..36727927c4 100644 --- a/arch/arm/src/calypso/calypso_spi.c +++ b/arch/arm/src/calypso/calypso_spi.c @@ -216,8 +216,8 @@ int spi_xfer(uint8_t dev_idx, uint8_t bitlen, const void *dout, void *din) tmp <<= (32-bitlen); /* align to MSB */ } - _err("spi_xfer(dev_idx=%u, bitlen=%u, data_out=0x%08x): ", - dev_idx, bitlen, tmp); + spiinfo("spi_xfer(dev_idx=%u, bitlen=%u, data_out=0x%08x): ", + dev_idx, bitlen, tmp); /* fill transmit registers */ @@ -236,14 +236,14 @@ int spi_xfer(uint8_t dev_idx, uint8_t bitlen, const void *dout, void *din) } putreg16(reg_ctrl, SPI_REG(REG_CTRL)); - _err("reg_ctrl=0x%04x ", reg_ctrl); + spiinfo("reg_ctrl=0x%04x ", reg_ctrl); /* wait until the transfer is complete */ while (1) { reg_status = getreg16(SPI_REG(REG_STATUS)); - _err("status=0x%04x ", reg_status); + spiinfo("status=0x%04x ", reg_status); if (din && (reg_status & SPI_STATUS_RE)) { break; @@ -262,7 +262,7 @@ int spi_xfer(uint8_t dev_idx, uint8_t bitlen, const void *dout, void *din) { tmp = getreg16(SPI_REG(REG_RX_MSB)) << 16; tmp |= getreg16(SPI_REG(REG_RX_LSB)); - _err("data_in=0x%08x ", tmp); + spiinfo("data_in=0x%08x ", tmp); if (bitlen <= 8) { @@ -278,7 +278,7 @@ int spi_xfer(uint8_t dev_idx, uint8_t bitlen, const void *dout, void *din) } } - _err("\n"); + spiinfo("\n"); return 0; } diff --git a/arch/arm/src/calypso/calypso_uwire.c b/arch/arm/src/calypso/calypso_uwire.c index 7ad9075b1e..fe2c33b7cc 100644 --- a/arch/arm/src/calypso/calypso_uwire.c +++ b/arch/arm/src/calypso/calypso_uwire.c @@ -112,7 +112,7 @@ int uwire_xfer(int cs, int bitlen, const void *dout, void *din) /* FIXME uwire_init always selects CS0 for now */ - _err("uwire_xfer(dev_idx=%u, bitlen=%u\n", cs, bitlen); + _info("uwire_xfer(dev_idx=%u, bitlen=%u\n", cs, bitlen); /* select the chip */ @@ -128,7 +128,7 @@ int uwire_xfer(int cs, int bitlen, const void *dout, void *din) tmp <<= 16 - bitlen; /* align to MSB */ putreg16(tmp, UWIRE_REG(REG_DATA)); - _err(", data_out=0x%04hx", tmp); + _info(", data_out=0x%04hx", tmp); } tmp = (dout ? UWIRE_CSR_BITS_WR(bitlen) : 0) | @@ -142,7 +142,7 @@ int uwire_xfer(int cs, int bitlen, const void *dout, void *din) _uwire_wait(UWIRE_CSR_RDRB, UWIRE_CSR_RDRB); tmp = getreg16(UWIRE_REG(REG_DATA)); - _err(", data_in=0x%08x", tmp); + _info(", data_in=0x%08x", tmp); if (bitlen <= 8) *(uint8_t *)din = tmp & 0xff; @@ -155,7 +155,7 @@ int uwire_xfer(int cs, int bitlen, const void *dout, void *din) putreg16(UWIRE_CSR_IDX(0) | 0, UWIRE_REG(REG_CSR)); _uwire_wait(UWIRE_CSR_CSRB, 0); - _err(")\n"); + _info(")\n"); return 0; } diff --git a/arch/arm/src/common/up_exit.c b/arch/arm/src/common/up_exit.c index be084481fd..4df8bf3463 100644 --- a/arch/arm/src/common/up_exit.c +++ b/arch/arm/src/common/up_exit.c @@ -52,6 +52,14 @@ #include "group/group.h" #include "up_internal.h" +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#ifndef CONFIG_DEBUG_SCHED_INFO +# undef CONFIG_DUMP_ON_EXIT +#endif + /**************************************************************************** * Private Functions ****************************************************************************/ @@ -66,7 +74,7 @@ * ****************************************************************************/ -#if defined(CONFIG_DUMP_ON_EXIT) && defined(CONFIG_DEBUG_FEATURES) +#ifdef CONFIG_DUMP_ON_EXIT static void _up_dumponexit(FAR struct tcb_s *tcb, FAR void *arg) { #if CONFIG_NFILE_DESCRIPTORS > 0 @@ -77,8 +85,8 @@ static void _up_dumponexit(FAR struct tcb_s *tcb, FAR void *arg) int i; #endif - serr(" TCB=%p name=%s pid=%d\n", tcb, tcb->argv[0], tcb->pid); - serr(" priority=%d state=%d\n", tcb->sched_priority, tcb->task_state); + sinfo(" TCB=%p name=%s pid=%d\n", tcb, tcb->argv[0], tcb->pid); + sinfo(" priority=%d state=%d\n", tcb->sched_priority, tcb->task_state); #if CONFIG_NFILE_DESCRIPTORS > 0 filelist = tcb->group->tg_filelist; @@ -87,8 +95,8 @@ static void _up_dumponexit(FAR struct tcb_s *tcb, FAR void *arg) struct inode *inode = filelist->fl_files[i].f_inode; if (inode) { - serr(" fd=%d refcount=%d\n", - i, inode->i_crefs); + sinfo(" fd=%d refcount=%d\n", + i, inode->i_crefssinfo); } } #endif @@ -101,11 +109,11 @@ static void _up_dumponexit(FAR struct tcb_s *tcb, FAR void *arg) if (filep->fs_fd >= 0) { #if CONFIG_STDIO_BUFFER_SIZE > 0 - serr(" fd=%d nbytes=%d\n", - filep->fs_fd, - filep->fs_bufpos - filep->fs_bufstart); + sinfo(" fd=%d nbytes=%d\n", + filep->fs_fd, + filep->fs_bufpos - filep->fs_bufstart); #else - serr(" fd=%d\n", filep->fs_fd); + sinfo(" fd=%d\n", filep->fs_fd); #endif } } @@ -138,10 +146,10 @@ void _exit(int status) (void)up_irq_save(); - sllerr("TCB=%p exiting\n", this_task()); + sllinfo("TCB=%p exiting\n", this_task()); -#if defined(CONFIG_DUMP_ON_EXIT) && defined(CONFIG_DEBUG_FEATURES) - sllerr("Other tasks:\n"); +#ifdef CONFIG_DUMP_ON_EXIT + sllinfo("Other tasks:\n"); sched_foreach(_up_dumponexit, NULL); #endif diff --git a/arch/arm/src/common/up_initialize.c b/arch/arm/src/common/up_initialize.c index 5316eacbb6..f926b7f038 100644 --- a/arch/arm/src/common/up_initialize.c +++ b/arch/arm/src/common/up_initialize.c @@ -77,13 +77,13 @@ static void up_calibratedelay(void) { int i; - _llerr("Beginning 100s delay\n"); + _llwarn("Beginning 100s delay\n"); for (i = 0; i < 100; i++) { up_mdelay(1000); } - _llerr("End 100s delay\n"); + _llwarn("End 100s delay\n"); } #else # define up_calibratedelay() diff --git a/arch/arm/src/common/up_internal.h b/arch/arm/src/common/up_internal.h index 8dccf8a1ef..af3da01e5e 100644 --- a/arch/arm/src/common/up_internal.h +++ b/arch/arm/src/common/up_internal.h @@ -63,6 +63,10 @@ #undef CONFIG_SUPPRESS_UART_CONFIG /* DEFINED: Do not reconfig UART */ #undef CONFIG_DUMP_ON_EXIT /* DEFINED: Dump task state on exit */ +#ifndef CONFIG_DEBUG_SCHED_INFO +# undef CONFIG_DUMP_ON_EXIT /* Needs CONFIG_DEBUG_SCHED_INFO */ +#endif + /* Determine which (if any) console driver to use. If a console is enabled * and no other console device is specified, then a serial console is * assumed. diff --git a/arch/avr/src/common/up_exit.c b/arch/avr/src/common/up_exit.c index 73dd3bb353..4c164aa356 100644 --- a/arch/avr/src/common/up_exit.c +++ b/arch/avr/src/common/up_exit.c @@ -52,6 +52,14 @@ #include "group/group.h" #include "up_internal.h" +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#ifndef CONFIG_DEBUG_SCHED_INFO +# undef CONFIG_DUMP_ON_EXIT +#endif + /**************************************************************************** * Private Functions ****************************************************************************/ @@ -66,7 +74,7 @@ * ****************************************************************************/ -#if defined(CONFIG_DUMP_ON_EXIT) && defined(CONFIG_DEBUG_FEATURES) +#ifdef CONFIG_DUMP_ON_EXIT static void _up_dumponexit(FAR struct tcb_s *tcb, FAR void *arg) { #if CONFIG_NFILE_DESCRIPTORS > 0 @@ -140,7 +148,7 @@ void _exit(int status) sllinfo("TCB=%p exiting\n", this_task()); -#if defined(CONFIG_DUMP_ON_EXIT) && defined(CONFIG_DEBUG_FEATURES) +#ifdef CONFIG_DUMP_ON_EXIT sllinfo("Other tasks:\n"); sched_foreach(_up_dumponexit, NULL); #endif diff --git a/arch/avr/src/common/up_internal.h b/arch/avr/src/common/up_internal.h index 92a160ee90..64eecb658c 100644 --- a/arch/avr/src/common/up_internal.h +++ b/arch/avr/src/common/up_internal.h @@ -67,6 +67,10 @@ #undef CONFIG_SUPPRESS_UART_CONFIG /* DEFINED: Do not reconfig UART */ #undef CONFIG_DUMP_ON_EXIT /* DEFINED: Dump task state on exit */ +#ifndef CONFIG_DEBUG_SCHED_INFO +# undef CONFIG_DUMP_ON_EXIT /* Needs CONFIG_DEBUG_SCHED_INFO */ +#endif + /* Check if an interrupt stack size is configured */ #ifndef CONFIG_ARCH_INTERRUPTSTACK diff --git a/arch/hc/src/common/up_exit.c b/arch/hc/src/common/up_exit.c index 251e91cefc..34688b5a6d 100644 --- a/arch/hc/src/common/up_exit.c +++ b/arch/hc/src/common/up_exit.c @@ -56,9 +56,9 @@ * Pre-processor Definitions ****************************************************************************/ -/**************************************************************************** - * Private Data - ****************************************************************************/ +#ifndef CONFIG_DEBUG_SCHED_INFO +# undef CONFIG_DUMP_ON_EXIT +#endif /**************************************************************************** * Private Functions @@ -74,7 +74,7 @@ * ****************************************************************************/ -#if defined(CONFIG_DUMP_ON_EXIT) && defined(CONFIG_DEBUG_FEATURES) +#ifdef CONFIG_DUMP_ON_EXIT static void _up_dumponexit(FAR struct tcb_s *tcb, FAR void *arg) { #if CONFIG_NFILE_DESCRIPTORS > 0 @@ -148,7 +148,7 @@ void _exit(int status) sllinfo("TCB=%p exiting\n", this_task()); -#if defined(CONFIG_DUMP_ON_EXIT) && defined(CONFIG_DEBUG_FEATURES) +#ifdef CONFIG_DUMP_ON_EXIT sllinfo("Other tasks:\n"); sched_foreach(_up_dumponexit, NULL); #endif diff --git a/arch/hc/src/common/up_internal.h b/arch/hc/src/common/up_internal.h index 1650711f3a..5550790df8 100644 --- a/arch/hc/src/common/up_internal.h +++ b/arch/hc/src/common/up_internal.h @@ -62,6 +62,10 @@ #undef CONFIG_SUPPRESS_UART_CONFIG /* DEFINED: Do not reconfig UART */ #undef CONFIG_DUMP_ON_EXIT /* DEFINED: Dump task state on exit */ +#ifndef CONFIG_DEBUG_SCHED_INFO +# undef CONFIG_DUMP_ON_EXIT /* Needs CONFIG_DEBUG_SCHED_INFO */ +#endif + /* Determine which (if any) console driver to use. If a console is enabled * and no other console device is specified, then a serial console is * assumed. diff --git a/arch/mips/src/common/up_exit.c b/arch/mips/src/common/up_exit.c index d26de05841..3a345a5d66 100644 --- a/arch/mips/src/common/up_exit.c +++ b/arch/mips/src/common/up_exit.c @@ -58,9 +58,9 @@ * Pre-processor Definitions ****************************************************************************/ -/**************************************************************************** - * Private Data - ****************************************************************************/ +#ifndef CONFIG_DEBUG_SCHED_INFO +# undef CONFIG_DUMP_ON_EXIT +#endif /**************************************************************************** * Private Functions @@ -76,7 +76,7 @@ * ****************************************************************************/ -#if defined(CONFIG_DUMP_ON_EXIT) && defined(CONFIG_DEBUG_FEATURES) +#ifdef CONFIG_DUMP_ON_EXIT static void _up_dumponexit(FAR struct tcb_s *tcb, FAR void *arg) { #if CONFIG_NFILE_DESCRIPTORS > 0 @@ -150,7 +150,7 @@ void _exit(int status) sllinfo("TCB=%p exiting\n", this_task()); -#if defined(CONFIG_DUMP_ON_EXIT) && defined(CONFIG_DEBUG_FEATURES) +#ifdef CONFIG_DUMP_ON_EXIT sllinfo("Other tasks:\n"); sched_foreach(_up_dumponexit, NULL); #endif diff --git a/arch/mips/src/common/up_internal.h b/arch/mips/src/common/up_internal.h index 3b2ca4ccbc..f48726606b 100644 --- a/arch/mips/src/common/up_internal.h +++ b/arch/mips/src/common/up_internal.h @@ -60,6 +60,10 @@ #undef CONFIG_SUPPRESS_UART_CONFIG /* DEFINED: Do not reconfig UART */ #undef CONFIG_DUMP_ON_EXIT /* DEFINED: Dump task state on exit */ +#ifndef CONFIG_DEBUG_SCHED_INFO +# undef CONFIG_DUMP_ON_EXIT /* Needs CONFIG_DEBUG_SCHED_INFO */ +#endif + /* Determine which (if any) console driver to use. If a console is enabled * and no other console device is specified, then a serial console is * assumed. diff --git a/arch/sh/src/common/up_exit.c b/arch/sh/src/common/up_exit.c index 4b4ba44337..ddeeecd3aa 100644 --- a/arch/sh/src/common/up_exit.c +++ b/arch/sh/src/common/up_exit.c @@ -57,9 +57,9 @@ * Pre-processor Definitions ****************************************************************************/ -/**************************************************************************** - * Private Data - ****************************************************************************/ +#ifndef CONFIG_DEBUG_SCHED_INFO +# undef CONFIG_DUMP_ON_EXIT +#endif /**************************************************************************** * Private Functions @@ -75,7 +75,7 @@ * ****************************************************************************/ -#if defined(CONFIG_DUMP_ON_EXIT) && defined(CONFIG_DEBUG_FEATURES) +#ifdef CONFIG_DUMP_ON_EXIT static void _up_dumponexit(FAR struct tcb_s *tcb, FAR void *arg) { #if CONFIG_NFILE_DESCRIPTORS > 0 @@ -149,7 +149,7 @@ void _exit(int status) sllinfo("TCB=%p exiting\n", this_task()); -#if defined(CONFIG_DUMP_ON_EXIT) && defined(CONFIG_DEBUG_FEATURES) +#ifdef CONFIG_DUMP_ON_EXIT sllinfo("Other tasks:\n"); sched_foreach(_up_dumponexit, NULL); #endif diff --git a/arch/x86/src/common/up_exit.c b/arch/x86/src/common/up_exit.c index 7e96c48e88..94f982ade0 100644 --- a/arch/x86/src/common/up_exit.c +++ b/arch/x86/src/common/up_exit.c @@ -56,9 +56,9 @@ * Pre-processor Definitions ****************************************************************************/ -/**************************************************************************** - * Private Data - ****************************************************************************/ +#ifndef CONFIG_DEBUG_SCHED_INFO +# undef CONFIG_DUMP_ON_EXIT +#endif /**************************************************************************** * Private Functions @@ -74,7 +74,7 @@ * ****************************************************************************/ -#if defined(CONFIG_DUMP_ON_EXIT) && defined(CONFIG_DEBUG_FEATURES) +#ifdef CONFIG_DUMP_ON_EXIT static void _up_dumponexit(FAR struct tcb_s *tcb, FAR void *arg) { #if CONFIG_NFILE_DESCRIPTORS > 0 @@ -148,7 +148,7 @@ void _exit(int status) sllinfo("TCB=%p exiting\n", this_task()); -#if defined(CONFIG_DUMP_ON_EXIT) && defined(CONFIG_DEBUG_FEATURES) +#ifdef CONFIG_DUMP_ON_EXIT sllinfo("Other tasks:\n"); sched_foreach(_up_dumponexit, NULL); #endif diff --git a/arch/x86/src/common/up_internal.h b/arch/x86/src/common/up_internal.h index d0eb1570c3..2af49eda98 100644 --- a/arch/x86/src/common/up_internal.h +++ b/arch/x86/src/common/up_internal.h @@ -62,6 +62,10 @@ #undef CONFIG_SUPPRESS_UART_CONFIG /* DEFINED: Do not reconfig UART */ #undef CONFIG_DUMP_ON_EXIT /* DEFINED: Dump task state on exit */ +#ifndef CONFIG_DEBUG_SCHED_INFO +# undef CONFIG_DUMP_ON_EXIT /* Needs CONFIG_DEBUG_SCHED_INFO */ +#endif + /* Determine which (if any) console driver to use. If a console is enabled * and no other console device is specified, then a serial console is * assumed. diff --git a/arch/z16/src/common/up_exit.c b/arch/z16/src/common/up_exit.c index df4d62c381..1b20e271e5 100644 --- a/arch/z16/src/common/up_exit.c +++ b/arch/z16/src/common/up_exit.c @@ -53,6 +53,14 @@ #include "sched/sched.h" #include "up_internal.h" +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#ifndef CONFIG_DEBUG_SCHED_INFO +# undef CONFIG_DUMP_ON_EXIT +#endif + /**************************************************************************** * Private Functions ****************************************************************************/ @@ -67,7 +75,7 @@ * ****************************************************************************/ -#if defined(CONFIG_DUMP_ON_EXIT) && defined(CONFIG_DEBUG_FEATURES) +#ifdef CONFIG_DUMP_ON_EXIT static void _up_dumponexit(FAR struct tcb_s *tcb, FAR void *arg) { #if CONFIG_NFILE_DESCRIPTORS > 0 @@ -141,7 +149,7 @@ void _exit(int status) sllinfo("TCB=%p exiting\n", tcb); -#if defined(CONFIG_DUMP_ON_EXIT) && defined(CONFIG_DEBUG_FEATURES) +#ifdef CONFIG_DUMP_ON_EXIT sllinfo("Other tasks:\n"); sched_foreach(_up_dumponexit, NULL); #endif diff --git a/arch/z16/src/common/up_internal.h b/arch/z16/src/common/up_internal.h index 64a5302a42..8203600b79 100644 --- a/arch/z16/src/common/up_internal.h +++ b/arch/z16/src/common/up_internal.h @@ -60,6 +60,10 @@ #undef CONFIG_Z16_LOWPUTC /* Support up_lowputc for debug */ #undef CONFIG_Z16_LOWGETC /* support z16_lowgetc for debug */ +#ifndef CONFIG_DEBUG_SCHED_INFO +# undef CONFIG_DUMP_ON_EXIT /* Needs CONFIG_DEBUG_SCHED_INFO */ +#endif + /* Determine which (if any) console driver to use. If a console is enabled * and no other console device is specified, then a serial console is * assumed. diff --git a/arch/z80/src/common/up_exit.c b/arch/z80/src/common/up_exit.c index a5e9832133..7a8fd8a836 100644 --- a/arch/z80/src/common/up_exit.c +++ b/arch/z80/src/common/up_exit.c @@ -59,9 +59,9 @@ * Pre-processor Definitions ****************************************************************************/ -/**************************************************************************** - * Private Data - ****************************************************************************/ +#ifndef CONFIG_DEBUG_SCHED_INFO +# undef CONFIG_DUMP_ON_EXIT +#endif /**************************************************************************** * Private Functions @@ -77,7 +77,7 @@ * ****************************************************************************/ -#if defined(CONFIG_DUMP_ON_EXIT) && defined(CONFIG_DEBUG_FEATURES) +#ifdef CONFIG_DUMP_ON_EXIT static void _up_dumponexit(FAR struct tcb_s *tcb, FAR void *arg) { #if CONFIG_NFILE_DESCRIPTORS > 0 @@ -88,8 +88,8 @@ static void _up_dumponexit(FAR struct tcb_s *tcb, FAR void *arg) int i; #endif - _llinfo(" TCB=%p name=%s\n", tcb, tcb->argv[0]); - _llinfo(" priority=%d state=%d\n", tcb->sched_priority, tcb->task_state); + sllinfo(" TCB=%p name=%s\n", tcb, tcb->argv[0]); + sllinfo(" priority=%d state=%d\n", tcb->sched_priority, tcb->task_state); #if CONFIG_NFILE_DESCRIPTORS > 0 filelist = tcb->group->tg_filelist; @@ -98,7 +98,7 @@ static void _up_dumponexit(FAR struct tcb_s *tcb, FAR void *arg) struct inode *inode = filelist->fl_files[i].f_inode; if (inode) { - _llinfo(" fd=%d refcount=%d\n", + sllinfo(" fd=%d refcount=%d\n", i, inode->i_crefs); } } @@ -112,11 +112,11 @@ static void _up_dumponexit(FAR struct tcb_s *tcb, FAR void *arg) if (filep->fs_fd >= 0) { #if CONFIG_STDIO_BUFFER_SIZE > 0 - _llinfo(" fd=%d nbytes=%d\n", + sllinfo(" fd=%d nbytes=%d\n", filep->fs_fd, filep->fs_bufpos - filep->fs_bufstart); #else - _llinfo(" fd=%d\n", filep->fs_fd); + sllinfo(" fd=%d\n", filep->fs_fd); #endif } } @@ -151,8 +151,8 @@ void _exit(int status) sllinfo("TCB=%p exiting\n", tcb); -#if defined(CONFIG_DUMP_ON_EXIT) && defined(CONFIG_DEBUG_FEATURES) - _llinfo("Other tasks:\n"); +#ifdef CONFIG_DUMP_ON_EXIT + sllinfo("Other tasks:\n"); sched_foreach(_up_dumponexit, NULL); #endif diff --git a/arch/z80/src/common/up_internal.h b/arch/z80/src/common/up_internal.h index 76deaa34b7..51bb7acf5f 100644 --- a/arch/z80/src/common/up_internal.h +++ b/arch/z80/src/common/up_internal.h @@ -51,6 +51,10 @@ #undef CONFIG_SUPPRESS_UART_CONFIG /* Do not reconfig UART */ #undef CONFIG_DUMP_ON_EXIT /* Dump task state on exit */ +#ifndef CONFIG_DEBUG_SCHED_INFO +# undef CONFIG_DUMP_ON_EXIT /* Needs CONFIG_DEBUG_SCHED_INFO */ +#endif + /**************************************************************************** * Included Files ****************************************************************************/ From d88bbaa1856eae70ba65600f2a6aeed0a1fa996c Mon Sep 17 00:00:00 2001 From: Gregory Nutt Date: Fri, 17 Jun 2016 15:57:52 -0600 Subject: [PATCH 49/75] armv7-r/armv7-m: Convert *err() to either *info() or add ERROR:, depending on if an error is reported --- arch/arm/src/armv7-m/mpu.h | 10 +-- arch/arm/src/armv7-m/up_elf.c | 16 ++--- arch/arm/src/armv7-m/up_hardfault.c | 70 ++++++++------------ arch/arm/src/armv7-m/up_memfault.c | 58 +++++++--------- arch/arm/src/armv7-m/up_releasepending.c | 2 +- arch/arm/src/armv7-m/up_reprioritizertr.c | 2 +- arch/arm/src/armv7-m/up_schedulesigaction.c | 4 +- arch/arm/src/armv7-m/up_sigdeliver.c | 4 +- arch/arm/src/armv7-r/arm_assert.c | 46 ++++++------- arch/arm/src/armv7-r/arm_elf.c | 16 ++--- arch/arm/src/armv7-r/arm_l2cc_pl310.c | 4 +- arch/arm/src/armv7-r/arm_releasepending.c | 2 +- arch/arm/src/armv7-r/arm_reprioritizertr.c | 2 +- arch/arm/src/armv7-r/arm_schedulesigaction.c | 4 +- arch/arm/src/armv7-r/arm_sigdeliver.c | 4 +- arch/arm/src/armv7-r/mpu.h | 10 +-- 16 files changed, 116 insertions(+), 138 deletions(-) diff --git a/arch/arm/src/armv7-m/mpu.h b/arch/arm/src/armv7-m/mpu.h index 3ff96371cb..22348a23a6 100644 --- a/arch/arm/src/armv7-m/mpu.h +++ b/arch/arm/src/armv7-m/mpu.h @@ -219,13 +219,13 @@ uint32_t mpu_subregion(uintptr_t base, size_t size, uint8_t l2size); static inline void mpu_showtype(void) { -#ifdef CONFIG_DEBUG_ERROR +#ifdef CONFIG_DEBUG_SCHED_INFO uint32_t regval = getreg32(MPU_TYPE); - _err("%s MPU Regions: data=%d instr=%d\n", - (regval & MPU_TYPE_SEPARATE) != 0 ? "Separate" : "Unified", - (regval & MPU_TYPE_DREGION_MASK) >> MPU_TYPE_DREGION_SHIFT, - (regval & MPU_TYPE_IREGION_MASK) >> MPU_TYPE_IREGION_SHIFT); + sinfo("%s MPU Regions: data=%d instr=%d\n", + (regval & MPU_TYPE_SEPARATE) != 0 ? "Separate" : "Unified", + (regval & MPU_TYPE_DREGION_MASK) >> MPU_TYPE_DREGION_SHIFT, + (regval & MPU_TYPE_IREGION_MASK) >> MPU_TYPE_IREGION_SHIFT); #endif } diff --git a/arch/arm/src/armv7-m/up_elf.c b/arch/arm/src/armv7-m/up_elf.c index e45e2dbe24..f2e0cdd979 100644 --- a/arch/arm/src/armv7-m/up_elf.c +++ b/arch/arm/src/armv7-m/up_elf.c @@ -82,7 +82,7 @@ bool up_checkarch(FAR const Elf32_Ehdr *ehdr) if (ehdr->e_machine != EM_ARM) { - berr("Not for ARM: e_machine=%04x\n", ehdr->e_machine); + berr("ERROR: Not for ARM: e_machine=%04x\n", ehdr->e_machine); return -ENOEXEC; } @@ -90,7 +90,7 @@ bool up_checkarch(FAR const Elf32_Ehdr *ehdr) if (ehdr->e_ident[EI_CLASS] != ELFCLASS32) { - berr("Need 32-bit objects: e_ident[EI_CLASS]=%02x\n", ehdr->e_ident[EI_CLASS]); + berr("ERROR: Need 32-bit objects: e_ident[EI_CLASS]=%02x\n", ehdr->e_ident[EI_CLASS]); return -ENOEXEC; } @@ -102,7 +102,7 @@ bool up_checkarch(FAR const Elf32_Ehdr *ehdr) if (ehdr->e_ident[EI_DATA] != ELFDATA2LSB) #endif { - berr("Wrong endian-ness: e_ident[EI_DATA]=%02x\n", ehdr->e_ident[EI_DATA]); + berr("ERROR: Wrong endian-ness: e_ident[EI_DATA]=%02x\n", ehdr->e_ident[EI_DATA]); return -ENOEXEC; } @@ -177,7 +177,7 @@ int up_relocate(FAR const Elf32_Rel *rel, FAR const Elf32_Sym *sym, offset += sym->st_value - addr; if (offset & 3 || offset <= (int32_t) 0xfe000000 || offset >= (int32_t) 0x02000000) { - berr(" ERROR: PC24 [%d] relocation out of range, offset=%08lx\n", + berr("ERROR: ERROR: PC24 [%d] relocation out of range, offset=%08lx\n", ELF32_R_TYPE(rel->r_info), offset); return -EINVAL; @@ -298,7 +298,7 @@ int up_relocate(FAR const Elf32_Rel *rel, FAR const Elf32_Sym *sym, if (ELF32_ST_TYPE(sym->st_info) == STT_FUNC && (offset & 1) == 0) { - berr(" ERROR: JUMP24 [%d] requires odd offset, offset=%08lx\n", + berr("ERROR: ERROR: JUMP24 [%d] requires odd offset, offset=%08lx\n", ELF32_R_TYPE(rel->r_info), offset); return -EINVAL; @@ -308,7 +308,7 @@ int up_relocate(FAR const Elf32_Rel *rel, FAR const Elf32_Sym *sym, if (offset <= (int32_t)0xff000000 || offset >= (int32_t)0x01000000) { - berr(" ERROR: JUMP24 [%d] relocation out of range, branch taget=%08lx\n", + berr("ERROR: ERROR: JUMP24 [%d] relocation out of range, branch taget=%08lx\n", ELF32_R_TYPE(rel->r_info), offset); return -EINVAL; @@ -461,7 +461,7 @@ int up_relocate(FAR const Elf32_Rel *rel, FAR const Elf32_Sym *sym, break; default: - berr("Unsupported relocation: %d\n", ELF32_R_TYPE(rel->r_info)); + berr("ERROR: Unsupported relocation: %d\n", ELF32_R_TYPE(rel->r_info)); return -EINVAL; } @@ -471,7 +471,7 @@ int up_relocate(FAR const Elf32_Rel *rel, FAR const Elf32_Sym *sym, int up_relocateadd(FAR const Elf32_Rela *rel, FAR const Elf32_Sym *sym, uintptr_t addr) { - berr("RELA relocation not supported\n"); + berr("ERROR: RELA relocation not supported\n"); return -ENOSYS; } diff --git a/arch/arm/src/armv7-m/up_hardfault.c b/arch/arm/src/armv7-m/up_hardfault.c index 225ca8337e..fe133cc4f3 100644 --- a/arch/arm/src/armv7-m/up_hardfault.c +++ b/arch/arm/src/armv7-m/up_hardfault.c @@ -60,25 +60,13 @@ */ #ifdef CONFIG_DEBUG_HARDFAULT -# define hferr(format, ...) _llerr(format, ##__VA_ARGS__) +# define hfalert(format, ...) _alert(format, ##__VA_ARGS__) #else -# define hferr(x...) +# define hfalert(x...) #endif #define INSN_SVC0 0xdf00 /* insn: svc 0 */ -/**************************************************************************** - * Private Data - ****************************************************************************/ - -/**************************************************************************** - * Public Data - ****************************************************************************/ - -/**************************************************************************** - * Private Functions - ****************************************************************************/ - /**************************************************************************** * Public Functions ****************************************************************************/ @@ -127,7 +115,7 @@ int up_hardfault(int irq, FAR void *context) /* Fetch the instruction that caused the Hard fault */ uint16_t insn = *pc; - hferr(" PC: %p INSN: %04x\n", pc, insn); + hfalert(" PC: %p INSN: %04x\n", pc, insn); /* If this was the instruction 'svc 0', then forward processing * to the SVCall handler @@ -135,7 +123,7 @@ int up_hardfault(int irq, FAR void *context) if (insn == INSN_SVC0) { - hferr("Forward SVCall\n"); + hfalert("Forward SVCall\n"); return up_svcall(irq, context); } } @@ -143,43 +131,43 @@ int up_hardfault(int irq, FAR void *context) /* Dump some hard fault info */ - hferr("Hard Fault:\n"); - hferr(" IRQ: %d regs: %p\n", irq, regs); - hferr(" BASEPRI: %08x PRIMASK: %08x IPSR: %08x CONTROL: %08x\n", - getbasepri(), getprimask(), getipsr(), getcontrol()); - hferr(" CFAULTS: %08x HFAULTS: %08x DFAULTS: %08x BFAULTADDR: %08x AFAULTS: %08x\n", - getreg32(NVIC_CFAULTS), getreg32(NVIC_HFAULTS), - getreg32(NVIC_DFAULTS), getreg32(NVIC_BFAULT_ADDR), - getreg32(NVIC_AFAULTS)); - hferr(" R0: %08x %08x %08x %08x %08x %08x %08x %08x\n", - regs[REG_R0], regs[REG_R1], regs[REG_R2], regs[REG_R3], - regs[REG_R4], regs[REG_R5], regs[REG_R6], regs[REG_R7]); - hferr(" R8: %08x %08x %08x %08x %08x %08x %08x %08x\n", - regs[REG_R8], regs[REG_R9], regs[REG_R10], regs[REG_R11], - regs[REG_R12], regs[REG_R13], regs[REG_R14], regs[REG_R15]); + hfalert("Hard Fault:\n"); + hfalert(" IRQ: %d regs: %p\n", irq, regs); + hfalert(" BASEPRI: %08x PRIMASK: %08x IPSR: %08x CONTROL: %08x\n", + getbasepri(), getprimask(), getipsr(), getcontrol()); + hfalert(" CFAULTS: %08x HFAULTS: %08x DFAULTS: %08x BFAULTADDR: %08x AFAULTS: %08x\n", + getreg32(NVIC_CFAULTS), getreg32(NVIC_HFAULTS), + getreg32(NVIC_DFAULTS), getreg32(NVIC_BFAULT_ADDR), + getreg32(NVIC_AFAULTS)); + hfalert(" R0: %08x %08x %08x %08x %08x %08x %08x %08x\n", + regs[REG_R0], regs[REG_R1], regs[REG_R2], regs[REG_R3], + regs[REG_R4], regs[REG_R5], regs[REG_R6], regs[REG_R7]); + hfalert(" R8: %08x %08x %08x %08x %08x %08x %08x %08x\n", + regs[REG_R8], regs[REG_R9], regs[REG_R10], regs[REG_R11], + regs[REG_R12], regs[REG_R13], regs[REG_R14], regs[REG_R15]); #ifdef CONFIG_ARMV7M_USEBASEPRI # ifdef REG_EXC_RETURN - hferr(" xPSR: %08x BASEPRI: %08x EXC_RETURN: %08x (saved)\n", - CURRENT_REGS[REG_XPSR], CURRENT_REGS[REG_BASEPRI], - CURRENT_REGS[REG_EXC_RETURN]); + hfalert(" xPSR: %08x BASEPRI: %08x EXC_RETURN: %08x (saved)\n", + CURRENT_REGS[REG_XPSR], CURRENT_REGS[REG_BASEPRI], + CURRENT_REGS[REG_EXC_RETURN]); # else - hferr(" xPSR: %08x BASEPRI: %08x (saved)\n", - CURRENT_REGS[REG_XPSR], CURRENT_REGS[REG_BASEPRI]); + hfalert(" xPSR: %08x BASEPRI: %08x (saved)\n", + CURRENT_REGS[REG_XPSR], CURRENT_REGS[REG_BASEPRI]); # endif #else # ifdef REG_EXC_RETURN - hferr(" xPSR: %08x PRIMASK: %08x EXC_RETURN: %08x (saved)\n", - CURRENT_REGS[REG_XPSR], CURRENT_REGS[REG_PRIMASK], - CURRENT_REGS[REG_EXC_RETURN]); + hfalert(" xPSR: %08x PRIMASK: %08x EXC_RETURN: %08x (saved)\n", + CURRENT_REGS[REG_XPSR], CURRENT_REGS[REG_PRIMASK], + CURRENT_REGS[REG_EXC_RETURN]); # else - hferr(" xPSR: %08x PRIMASK: %08x (saved)\n", - CURRENT_REGS[REG_XPSR], CURRENT_REGS[REG_PRIMASK]); + hfalert(" xPSR: %08x PRIMASK: %08x (saved)\n", + CURRENT_REGS[REG_XPSR], CURRENT_REGS[REG_PRIMASK]); # endif #endif (void)up_irq_save(); - _llerr("PANIC!!! Hard fault: %08x\n", getreg32(NVIC_HFAULTS)); + _alert("PANIC!!! Hard fault: %08x\n", getreg32(NVIC_HFAULTS)); PANIC(); return OK; } diff --git a/arch/arm/src/armv7-m/up_memfault.c b/arch/arm/src/armv7-m/up_memfault.c index 4359072e65..f883209b76 100644 --- a/arch/arm/src/armv7-m/up_memfault.c +++ b/arch/arm/src/armv7-m/up_memfault.c @@ -55,23 +55,13 @@ #undef DEBUG_MEMFAULTS /* Define to debug memory management faults */ #ifdef DEBUG_MEMFAULTS -# define mferr(format, ...) _llerr(format, ##__VA_ARGS__) +# define mferr(format, ...) _alert(format, ##__VA_ARGS__) +# define mfinfo(format, ...) _alert(format, ##__VA_ARGS__) #else # define mferr(x...) +# define mfinfo(x...) #endif -/**************************************************************************** - * Private Data - ****************************************************************************/ - -/**************************************************************************** - * Public Data - ****************************************************************************/ - -/**************************************************************************** - * Private Functions - ****************************************************************************/ - /**************************************************************************** * Public Functions ****************************************************************************/ @@ -92,36 +82,36 @@ int up_memfault(int irq, FAR void *context) /* Dump some memory management fault info */ (void)up_irq_save(); - _llerr("PANIC!!! Memory Management Fault:\n"); - mferr(" IRQ: %d context: %p\n", irq, regs); - _llerr(" CFAULTS: %08x MMFAR: %08x\n", + _alert("PANIC!!! Memory Management Fault:\n"); + mfinfo(" IRQ: %d context: %p\n", irq, regs); + _alert(" CFAULTS: %08x MMFAR: %08x\n", getreg32(NVIC_CFAULTS), getreg32(NVIC_MEMMANAGE_ADDR)); - mferr(" BASEPRI: %08x PRIMASK: %08x IPSR: %08x CONTROL: %08x\n", - getbasepri(), getprimask(), getipsr(), getcontrol()); - mferr(" R0: %08x %08x %08x %08x %08x %08x %08x %08x\n", - regs[REG_R0], regs[REG_R1], regs[REG_R2], regs[REG_R3], - regs[REG_R4], regs[REG_R5], regs[REG_R6], regs[REG_R7]); - mferr(" R8: %08x %08x %08x %08x %08x %08x %08x %08x\n", - regs[REG_R8], regs[REG_R9], regs[REG_R10], regs[REG_R11], - regs[REG_R12], regs[REG_R13], regs[REG_R14], regs[REG_R15]); + mfinfo(" BASEPRI: %08x PRIMASK: %08x IPSR: %08x CONTROL: %08x\n", + getbasepri(), getprimask(), getipsr(), getcontrol()); + mfinfo(" R0: %08x %08x %08x %08x %08x %08x %08x %08x\n", + regs[REG_R0], regs[REG_R1], regs[REG_R2], regs[REG_R3], + regs[REG_R4], regs[REG_R5], regs[REG_R6], regs[REG_R7]); + mfinfo(" R8: %08x %08x %08x %08x %08x %08x %08x %08x\n", + regs[REG_R8], regs[REG_R9], regs[REG_R10], regs[REG_R11], + regs[REG_R12], regs[REG_R13], regs[REG_R14], regs[REG_R15]); #ifdef CONFIG_ARMV7M_USEBASEPRI # ifdef REG_EXC_RETURN - mferr(" xPSR: %08x BASEPRI: %08x EXC_RETURN: %08x (saved)\n", - CURRENT_REGS[REG_XPSR], CURRENT_REGS[REG_BASEPRI], - CURRENT_REGS[REG_EXC_RETURN]); + mfinfo(" xPSR: %08x BASEPRI: %08x EXC_RETURN: %08x (saved)\n", + CURRENT_REGS[REG_XPSR], CURRENT_REGS[REG_BASEPRI], + CURRENT_REGS[REG_EXC_RETURN]); # else - mferr(" xPSR: %08x BASEPRI: %08x (saved)\n", - CURRENT_REGS[REG_XPSR], CURRENT_REGS[REG_BASEPRI]); + mfinfo(" xPSR: %08x BASEPRI: %08x (saved)\n", + CURRENT_REGS[REG_XPSR], CURRENT_REGS[REG_BASEPRI]); # endif #else # ifdef REG_EXC_RETURN - mferr(" xPSR: %08x PRIMASK: %08x EXC_RETURN: %08x (saved)\n", - CURRENT_REGS[REG_XPSR], CURRENT_REGS[REG_PRIMASK], - CURRENT_REGS[REG_EXC_RETURN]); + mfinfo(" xPSR: %08x PRIMASK: %08x EXC_RETURN: %08x (saved)\n", + CURRENT_REGS[REG_XPSR], CURRENT_REGS[REG_PRIMASK], + CURRENT_REGS[REG_EXC_RETURN]); # else - mferr(" xPSR: %08x PRIMASK: %08x (saved)\n", - CURRENT_REGS[REG_XPSR], CURRENT_REGS[REG_PRIMASK]); + mfinfo(" xPSR: %08x PRIMASK: %08x (saved)\n", + CURRENT_REGS[REG_XPSR], CURRENT_REGS[REG_PRIMASK]); # endif #endif diff --git a/arch/arm/src/armv7-m/up_releasepending.c b/arch/arm/src/armv7-m/up_releasepending.c index 489e3537e1..683a9864aa 100644 --- a/arch/arm/src/armv7-m/up_releasepending.c +++ b/arch/arm/src/armv7-m/up_releasepending.c @@ -66,7 +66,7 @@ void up_release_pending(void) { struct tcb_s *rtcb = this_task(); - sllerr("From TCB=%p\n", rtcb); + sllinfo("From TCB=%p\n", rtcb); /* Merge the g_pendingtasks list into the ready-to-run task list */ diff --git a/arch/arm/src/armv7-m/up_reprioritizertr.c b/arch/arm/src/armv7-m/up_reprioritizertr.c index 61b592be05..845e7578e4 100644 --- a/arch/arm/src/armv7-m/up_reprioritizertr.c +++ b/arch/arm/src/armv7-m/up_reprioritizertr.c @@ -94,7 +94,7 @@ void up_reprioritize_rtr(struct tcb_s *tcb, uint8_t priority) struct tcb_s *rtcb = this_task(); bool switch_needed; - sllerr("TCB=%p PRI=%d\n", tcb, priority); + sllinfo("TCB=%p PRI=%d\n", tcb, priority); /* Remove the tcb task from the ready-to-run list. * sched_removereadytorun will return true if we just removed the head diff --git a/arch/arm/src/armv7-m/up_schedulesigaction.c b/arch/arm/src/armv7-m/up_schedulesigaction.c index d24906dd3b..cf70662510 100644 --- a/arch/arm/src/armv7-m/up_schedulesigaction.c +++ b/arch/arm/src/armv7-m/up_schedulesigaction.c @@ -95,7 +95,7 @@ void up_schedule_sigaction(struct tcb_s *tcb, sig_deliver_t sigdeliver) { irqstate_t flags; - serr("tcb=0x%p sigdeliver=0x%p\n", tcb, sigdeliver); + sinfo("tcb=0x%p sigdeliver=0x%p\n", tcb, sigdeliver); DEBUGASSERT(tcb != NULL && sigdeliver != NULL); /* Make sure that interrupts are disabled */ @@ -110,7 +110,7 @@ void up_schedule_sigaction(struct tcb_s *tcb, sig_deliver_t sigdeliver) * to the currently executing task. */ - serr("rtcb=0x%p CURRENT_REGS=0x%p\n", this_task(), CURRENT_REGS); + sinfo("rtcb=0x%p CURRENT_REGS=0x%p\n", this_task(), CURRENT_REGS); if (tcb == this_task()) { diff --git a/arch/arm/src/armv7-m/up_sigdeliver.c b/arch/arm/src/armv7-m/up_sigdeliver.c index 16f05b5adc..6169b51279 100644 --- a/arch/arm/src/armv7-m/up_sigdeliver.c +++ b/arch/arm/src/armv7-m/up_sigdeliver.c @@ -95,7 +95,7 @@ void up_sigdeliver(void) board_autoled_on(LED_SIGNAL); - serr("rtcb=%p sigdeliver=%p sigpendactionq.head=%p\n", + sinfo("rtcb=%p sigdeliver=%p sigpendactionq.head=%p\n", rtcb, rtcb->xcp.sigdeliver, rtcb->sigpendactionq.head); ASSERT(rtcb->xcp.sigdeliver != NULL); @@ -138,7 +138,7 @@ void up_sigdeliver(void) * errno that is needed by the user logic (it is probably EINTR). */ - serr("Resuming\n"); + sinfo("Resuming\n"); (void)up_irq_save(); rtcb->pterrno = saved_errno; diff --git a/arch/arm/src/armv7-r/arm_assert.c b/arch/arm/src/armv7-r/arm_assert.c index b6f6b23546..ccf0116045 100644 --- a/arch/arm/src/armv7-r/arm_assert.c +++ b/arch/arm/src/armv7-r/arm_assert.c @@ -98,7 +98,7 @@ static void up_stackdump(uint32_t sp, uint32_t stack_base) for (stack = sp & ~0x1f; stack < stack_base; stack += 32) { uint32_t *ptr = (uint32_t *)stack; - _llerr("%08x: %08x %08x %08x %08x %08x %08x %08x %08x\n", + _alert("%08x: %08x %08x %08x %08x %08x %08x %08x %08x\n", stack, ptr[0], ptr[1], ptr[2], ptr[3], ptr[4], ptr[5], ptr[6], ptr[7]); } @@ -117,11 +117,11 @@ static void up_taskdump(FAR struct tcb_s *tcb, FAR void *arg) /* Dump interesting properties of this task */ #if CONFIG_TASK_NAME_SIZE > 0 - _llerr("%s: PID=%d Stack Used=%lu of %lu\n", + _alert("%s: PID=%d Stack Used=%lu of %lu\n", tcb->name, tcb->pid, (unsigned long)up_check_tcbstack(tcb), (unsigned long)tcb->adj_stack_size); #else - _llerr("PID: %d Stack Used=%lu of %lu\n", + _alert("PID: %d Stack Used=%lu of %lu\n", tcb->pid, (unsigned long)up_check_tcbstack(tcb), (unsigned long)tcb->adj_stack_size); #endif @@ -161,12 +161,12 @@ static inline void up_registerdump(void) for (regs = REG_R0; regs <= REG_R15; regs += 8) { uint32_t *ptr = (uint32_t *)&CURRENT_REGS[regs]; - _llerr("R%d: %08x %08x %08x %08x %08x %08x %08x %08x\n", + _alert("R%d: %08x %08x %08x %08x %08x %08x %08x %08x\n", regs, ptr[0], ptr[1], ptr[2], ptr[3], ptr[4], ptr[5], ptr[6], ptr[7]); } - _llerr("CPSR: %08x\n", CURRENT_REGS[REG_CPSR]); + _alert("CPSR: %08x\n", CURRENT_REGS[REG_CPSR]); } } #else @@ -230,7 +230,7 @@ static void up_dumpstate(void) ustacksize = (uint32_t)rtcb->adj_stack_size; } - _llerr("Current sp: %08x\n", sp); + _alert("Current sp: %08x\n", sp); #if CONFIG_ARCH_INTERRUPTSTACK > 3 /* Get the limits on the interrupt stack memory */ @@ -240,21 +240,21 @@ static void up_dumpstate(void) /* Show interrupt stack info */ - _llerr("Interrupt stack:\n"); - _llerr(" base: %08x\n", istackbase); - _llerr(" size: %08x\n", istacksize); + _alert("Interrupt stack:\n"); + _alert(" base: %08x\n", istackbase); + _alert(" size: %08x\n", istacksize); #ifdef CONFIG_STACK_COLORATION - _llerr(" used: %08x\n", up_check_intstack()); + _alert(" used: %08x\n", up_check_intstack()); #endif #endif /* Show user stack info */ - _llerr("User stack:\n"); - _llerr(" base: %08x\n", ustackbase); - _llerr(" size: %08x\n", ustacksize); + _alert("User stack:\n"); + _alert(" base: %08x\n", ustackbase); + _alert(" size: %08x\n", ustacksize); #ifdef CONFIG_STACK_COLORATION - _llerr(" used: %08x\n", up_check_tcbstack(rtcb)); + _alert(" used: %08x\n", up_check_tcbstack(rtcb)); #endif #ifdef CONFIG_ARCH_KERNEL_STACK @@ -264,9 +264,9 @@ static void up_dumpstate(void) { kstackbase = (uint32_t)rtcb->xcp.kstack + CONFIG_ARCH_KERNEL_STACKSIZE - 4; - _llerr("Kernel stack:\n"); - _llerr(" base: %08x\n", kstackbase); - _llerr(" size: %08x\n", CONFIG_ARCH_KERNEL_STACKSIZE); + _alert("Kernel stack:\n"); + _alert(" base: %08x\n", kstackbase); + _alert(" size: %08x\n", CONFIG_ARCH_KERNEL_STACKSIZE); } #endif @@ -277,7 +277,7 @@ static void up_dumpstate(void) { /* Yes.. dump the interrupt stack */ - _llerr("Interrupt Stack\n", sp); + _alert("Interrupt Stack\n", sp); up_stackdump(sp, istackbase); /* Extract the user stack pointer which should lie @@ -285,7 +285,7 @@ static void up_dumpstate(void) */ sp = g_intstackbase; - _llerr("User sp: %08x\n", sp); + _alert("User sp: %08x\n", sp); } #endif @@ -295,7 +295,7 @@ static void up_dumpstate(void) if (sp > ustackbase - ustacksize && sp < ustackbase) { - _llerr("User Stack\n", sp); + _alert("User Stack\n", sp); up_stackdump(sp, ustackbase); } @@ -306,7 +306,7 @@ static void up_dumpstate(void) if (sp >= (uint32_t)rtcb->xcp.kstack && sp < kstackbase) { - _llerr("Kernel Stack\n", sp); + _alert("Kernel Stack\n", sp); up_stackdump(sp, kstackbase); } #endif @@ -373,10 +373,10 @@ void up_assert(const uint8_t *filename, int lineno) board_autoled_on(LED_ASSERTION); #if CONFIG_TASK_NAME_SIZE > 0 - _llerr("Assertion failed at file:%s line: %d task: %s\n", + _alert("Assertion failed at file:%s line: %d task: %s\n", filename, lineno, rtcb->name); #else - _llerr("Assertion failed at file:%s line: %d\n", + _alert("Assertion failed at file:%s line: %d\n", filename, lineno); #endif up_dumpstate(); diff --git a/arch/arm/src/armv7-r/arm_elf.c b/arch/arm/src/armv7-r/arm_elf.c index 0d7b40cd49..4ab4713b62 100644 --- a/arch/arm/src/armv7-r/arm_elf.c +++ b/arch/arm/src/armv7-r/arm_elf.c @@ -86,7 +86,7 @@ bool up_checkarch(FAR const Elf32_Ehdr *ehdr) if (ehdr->e_machine != EM_ARM) { - berr("Not for ARM: e_machine=%04x\n", ehdr->e_machine); + berr("ERROR: Not for ARM: e_machine=%04x\n", ehdr->e_machine); return -ENOEXEC; } @@ -94,7 +94,7 @@ bool up_checkarch(FAR const Elf32_Ehdr *ehdr) if (ehdr->e_ident[EI_CLASS] != ELFCLASS32) { - berr("Need 32-bit objects: e_ident[EI_CLASS]=%02x\n", ehdr->e_ident[EI_CLASS]); + berr("ERROR: Need 32-bit objects: e_ident[EI_CLASS]=%02x\n", ehdr->e_ident[EI_CLASS]); return -ENOEXEC; } @@ -106,7 +106,7 @@ bool up_checkarch(FAR const Elf32_Ehdr *ehdr) if (ehdr->e_ident[EI_DATA] != ELFDATA2LSB) #endif { - berr("Wrong endian-ness: e_ident[EI_DATA]=%02x\n", ehdr->e_ident[EI_DATA]); + berr("ERROR: Wrong endian-ness: e_ident[EI_DATA]=%02x\n", ehdr->e_ident[EI_DATA]); return -ENOEXEC; } @@ -114,7 +114,7 @@ bool up_checkarch(FAR const Elf32_Ehdr *ehdr) if ((ehdr->e_entry & 3) != 0) { - berr("Entry point is not properly aligned: %08x\n", ehdr->e_entry); + berr("ERROR: Entry point is not properly aligned: %08x\n", ehdr->e_entry); return -ENOEXEC; } @@ -187,8 +187,8 @@ int up_relocate(FAR const Elf32_Rel *rel, FAR const Elf32_Sym *sym, offset += sym->st_value - addr; if (offset & 3 || offset <= (int32_t) 0xfe000000 || offset >= (int32_t) 0x02000000) { - berr(" ERROR: PC24 [%d] relocation out of range, offset=%08lx\n", - ELF32_R_TYPE(rel->r_info), offset); + berr("ERROR: ERROR: PC24 [%d] relocation out of range, offset=%08lx\n", + ELF32_R_TYPE(rel->r_info), offset); return -EINVAL; } @@ -258,7 +258,7 @@ int up_relocate(FAR const Elf32_Rel *rel, FAR const Elf32_Sym *sym, break; default: - berr("Unsupported relocation: %d\n", ELF32_R_TYPE(rel->r_info)); + berr("ERROR: Unsupported relocation: %d\n", ELF32_R_TYPE(rel->r_info)); return -EINVAL; } @@ -268,6 +268,6 @@ int up_relocate(FAR const Elf32_Rel *rel, FAR const Elf32_Sym *sym, int up_relocateadd(FAR const Elf32_Rela *rel, FAR const Elf32_Sym *sym, uintptr_t addr) { - berr("RELA relocation not supported\n"); + berr("ERROR: RELA relocation not supported\n"); return -ENOSYS; } diff --git a/arch/arm/src/armv7-r/arm_l2cc_pl310.c b/arch/arm/src/armv7-r/arm_l2cc_pl310.c index f606dadc8a..d10e205160 100644 --- a/arch/arm/src/armv7-r/arm_l2cc_pl310.c +++ b/arch/arm/src/armv7-r/arm_l2cc_pl310.c @@ -411,8 +411,8 @@ void up_l2ccinitialize(void) putreg32(L2CC_CR_L2CEN, L2CC_CR); } - _llerr("(%d ways) * (%d bytes/way) = %d bytes\n", - PL310_NWAYS, PL310_WAYSIZE, PL310_CACHE_SIZE); + sllinfo("(%d ways) * (%d bytes/way) = %d bytes\n", + PL310_NWAYS, PL310_WAYSIZE, PL310_CACHE_SIZE); } /**************************************************************************** diff --git a/arch/arm/src/armv7-r/arm_releasepending.c b/arch/arm/src/armv7-r/arm_releasepending.c index d65bc75be2..87fa34a366 100644 --- a/arch/arm/src/armv7-r/arm_releasepending.c +++ b/arch/arm/src/armv7-r/arm_releasepending.c @@ -67,7 +67,7 @@ void up_release_pending(void) { struct tcb_s *rtcb = this_task(); - sllerr("From TCB=%p\n", rtcb); + sllinfo("From TCB=%p\n", rtcb); /* Merge the g_pendingtasks list into the ready-to-run task list */ diff --git a/arch/arm/src/armv7-r/arm_reprioritizertr.c b/arch/arm/src/armv7-r/arm_reprioritizertr.c index 192bff007d..af70900b34 100644 --- a/arch/arm/src/armv7-r/arm_reprioritizertr.c +++ b/arch/arm/src/armv7-r/arm_reprioritizertr.c @@ -95,7 +95,7 @@ void up_reprioritize_rtr(struct tcb_s *tcb, uint8_t priority) struct tcb_s *rtcb = this_task(); bool switch_needed; - sllerr("TCB=%p PRI=%d\n", tcb, priority); + sllinfo("TCB=%p PRI=%d\n", tcb, priority); /* Remove the tcb task from the ready-to-run list. * sched_removereadytorun will return true if we just diff --git a/arch/arm/src/armv7-r/arm_schedulesigaction.c b/arch/arm/src/armv7-r/arm_schedulesigaction.c index 3ece5d8acf..a51d660cb4 100644 --- a/arch/arm/src/armv7-r/arm_schedulesigaction.c +++ b/arch/arm/src/armv7-r/arm_schedulesigaction.c @@ -94,7 +94,7 @@ void up_schedule_sigaction(struct tcb_s *tcb, sig_deliver_t sigdeliver) { irqstate_t flags; - serr("tcb=0x%p sigdeliver=0x%p\n", tcb, sigdeliver); + sinfo("tcb=0x%p sigdeliver=0x%p\n", tcb, sigdeliver); /* Make sure that interrupts are disabled */ @@ -108,7 +108,7 @@ void up_schedule_sigaction(struct tcb_s *tcb, sig_deliver_t sigdeliver) * to the currently executing task. */ - serr("rtcb=0x%p CURRENT_REGS=0x%p\n", this_task(), CURRENT_REGS); + sinfo("rtcb=0x%p CURRENT_REGS=0x%p\n", this_task(), CURRENT_REGS); if (tcb == this_task()) { diff --git a/arch/arm/src/armv7-r/arm_sigdeliver.c b/arch/arm/src/armv7-r/arm_sigdeliver.c index 1a4f9b966d..280a5ef9c7 100644 --- a/arch/arm/src/armv7-r/arm_sigdeliver.c +++ b/arch/arm/src/armv7-r/arm_sigdeliver.c @@ -83,7 +83,7 @@ void up_sigdeliver(void) board_autoled_on(LED_SIGNAL); - serr("rtcb=%p sigdeliver=%p sigpendactionq.head=%p\n", + sinfo("rtcb=%p sigdeliver=%p sigpendactionq.head=%p\n", rtcb, rtcb->xcp.sigdeliver, rtcb->sigpendactionq.head); ASSERT(rtcb->xcp.sigdeliver != NULL); @@ -114,7 +114,7 @@ void up_sigdeliver(void) * errno that is needed by the user logic (it is probably EINTR). */ - serr("Resuming\n"); + sinfo("Resuming\n"); (void)up_irq_save(); rtcb->pterrno = saved_errno; diff --git a/arch/arm/src/armv7-r/mpu.h b/arch/arm/src/armv7-r/mpu.h index 07b1969760..e9e29cf13f 100644 --- a/arch/arm/src/armv7-r/mpu.h +++ b/arch/arm/src/armv7-r/mpu.h @@ -359,12 +359,12 @@ static inline void mpu_set_rgnr(unsigned int rgnr) static inline void mpu_showtype(void) { -#ifdef CONFIG_DEBUG_FEATURES +#ifdef CONFIG_DEBUG_SCHED_INFO uint32_t regval = mpu_get_mpuir(); - _err("%s MPU Regions: data=%d instr=%d\n", - (regval & MPUIR_SEPARATE) != 0 ? "Separate" : "Unified", - (regval & MPUIR_DREGION_MASK) >> MPUIR_DREGION_SHIFT, - (regval & MPUIR_IREGION_MASK) >> MPUIR_IREGION_SHIFT); + sinfo("%s MPU Regions: data=%d instr=%d\n", + (regval & MPUIR_SEPARATE) != 0 ? "Separate" : "Unified", + (regval & MPUIR_DREGION_MASK) >> MPUIR_DREGION_SHIFT, + (regval & MPUIR_IREGION_MASK) >> MPUIR_IREGION_SHIFT); #endif } From 2de4ec2a472e768eef0d13d3572b5fb80bb21f23 Mon Sep 17 00:00:00 2001 From: David Sidrane Date: Wed, 15 Jun 2016 10:41:03 -1000 Subject: [PATCH 50/75] Added as an author --- arch/arm/include/stm32f7/chip.h | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/arch/arm/include/stm32f7/chip.h b/arch/arm/include/stm32f7/chip.h index d30937541e..b3beb4e09e 100644 --- a/arch/arm/include/stm32f7/chip.h +++ b/arch/arm/include/stm32f7/chip.h @@ -2,7 +2,8 @@ * arch/arm/include/stm32f7/chip.h * * Copyright (C) 2015-2016 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Authors: Gregory Nutt + * David Sidrane * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions From 27d316ed954a8496a5f49e2fd78f6ff5a3a967b7 Mon Sep 17 00:00:00 2001 From: David Sidrane Date: Wed, 15 Jun 2016 10:58:41 -1000 Subject: [PATCH 51/75] Gix spelling in inclusion guards --- arch/arm/src/stm32f7/chip/stm32_spi.h | 6 +++--- arch/arm/src/stm32f7/chip/stm32f74xx77xx_uart.h | 6 +++--- arch/arm/src/stm32f7/stm32_uart.h | 6 +++--- 3 files changed, 9 insertions(+), 9 deletions(-) diff --git a/arch/arm/src/stm32f7/chip/stm32_spi.h b/arch/arm/src/stm32f7/chip/stm32_spi.h index dbd4d7301e..33e34789fb 100644 --- a/arch/arm/src/stm32f7/chip/stm32_spi.h +++ b/arch/arm/src/stm32f7/chip/stm32_spi.h @@ -34,8 +34,8 @@ * ************************************************************************************/ -#ifndef __ARCH_ARM_STC_STM32F7_CHIP_STM32_SPI_H -#define __ARCH_ARM_STC_STM32F7_CHIP_STM32_SPI_H +#ifndef __ARCH_ARM_SRC_STM32F7_CHIP_STM32_SPI_H +#define __ARCH_ARM_SRC_STM32F7_CHIP_STM32_SPI_H /************************************************************************************ * Included Files @@ -255,4 +255,4 @@ #define SPI_I2SPR_ODD (1 << 8) /* Bit 8: Odd factor for the prescaler */ #define SPI_I2SPR_MCKOE (1 << 9) /* Bit 9: Master clock output enable */ -#endif /* __ARCH_ARM_STC_STM32F7_CHIP_STM32_SPI_H */ +#endif /* __ARCH_ARM_SRC_STM32F7_CHIP_STM32_SPI_H */ diff --git a/arch/arm/src/stm32f7/chip/stm32f74xx77xx_uart.h b/arch/arm/src/stm32f7/chip/stm32f74xx77xx_uart.h index e33030cd8d..4d109bead0 100644 --- a/arch/arm/src/stm32f7/chip/stm32f74xx77xx_uart.h +++ b/arch/arm/src/stm32f7/chip/stm32f74xx77xx_uart.h @@ -34,8 +34,8 @@ * ************************************************************************************/ -#ifndef __ARCH_ARM_STC_STM32F7_CHIP_STM32F74XX77XX_UART_H -#define __ARCH_ARM_STC_STM32F7_CHIP_STM32F74XX77XX_UART_H +#ifndef __ARCH_ARM_SRC_STM32F7_CHIP_STM32F74XX77XX_UART_H +#define __ARCH_ARM_SRC_STM32F7_CHIP_STM32F74XX77XX_UART_H /************************************************************************************ * Included Files @@ -368,4 +368,4 @@ #define USART_TDR_MASK (0x1ff << USART_TDR_SHIFT) #endif /* CONFIG_STM32F7_STM32F74XX || CONFIG_STM32F7_STM32F75XX */ -#endif /* __ARCH_ARM_STC_STM32F7_CHIP_STM32F74XX77XX_UART_H */ +#endif /* __ARCH_ARM_SRC_STM32F7_CHIP_STM32F74XX77XX_UART_H */ diff --git a/arch/arm/src/stm32f7/stm32_uart.h b/arch/arm/src/stm32f7/stm32_uart.h index 9b1bce0b4e..d250eb7761 100644 --- a/arch/arm/src/stm32f7/stm32_uart.h +++ b/arch/arm/src/stm32f7/stm32_uart.h @@ -33,8 +33,8 @@ * ************************************************************************************/ -#ifndef __ARCH_ARM_STC_STM32F7_STM32_UART_H -#define __ARCH_ARM_STC_STM32F7_STM32_UART_H +#ifndef __ARCH_ARM_SRC_STM32F7_STM32_UART_H +#define __ARCH_ARM_SRC_STM32F7_STM32_UART_H /************************************************************************************ * Included Files @@ -342,4 +342,4 @@ void stm32_serial_dma_poll(void); #endif #endif /* __ASSEMBLY__ */ -#endif /* __ARCH_ARM_STC_STM32F7_STM32_UART_H */ +#endif /* __ARCH_ARM_SRC_STM32F7_STM32_UART_H */ From 6f99da07573033d3a317cf3af91971a610baa5a6 Mon Sep 17 00:00:00 2001 From: David Sidrane Date: Wed, 15 Jun 2016 11:02:41 -1000 Subject: [PATCH 52/75] Removed unused/incomplete stm32f74xx75xx_spi.h - SPI is same in all sub families --- .../arm/src/stm32f7/chip/stm32f74xx75xx_spi.h | 207 ------------------ 1 file changed, 207 deletions(-) delete mode 100644 arch/arm/src/stm32f7/chip/stm32f74xx75xx_spi.h diff --git a/arch/arm/src/stm32f7/chip/stm32f74xx75xx_spi.h b/arch/arm/src/stm32f7/chip/stm32f74xx75xx_spi.h deleted file mode 100644 index 57d86d9852..0000000000 --- a/arch/arm/src/stm32f7/chip/stm32f74xx75xx_spi.h +++ /dev/null @@ -1,207 +0,0 @@ -/************************************************************************************ - * arch/arm/src/stm32f7/chip/stm32f74xx75xx_spi.h - * - * Copyright (C) 2016 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - ************************************************************************************/ - -#ifndef __ARCH_ARM_SRC_STM32F7_CHIP_STM32F74XX75XX_SPI_H -#define __ARCH_ARM_SRC_STM32F7_CHIP_STM32F74XX75XX_SPI_H - -/************************************************************************************ - * Included Files - ************************************************************************************/ - -#include -#include "chip.h" - -/************************************************************************************ - * Pre-processor Definitions - ************************************************************************************/ - -/* Maximum allowed speed as per specifications for all SPIs */ - -#define STM32F7_SPI_CLK_MAX 27000000UL - -/* Register Offsets *****************************************************************/ - -#define STM32F7_SPI_CR1_OFFSET 0x0000 /* SPI Control Register 1 (16-bit) */ -#define STM32F7_SPI_CR2_OFFSET 0x0004 /* SPI control register 2 (16-bit) */ -#define STM32F7_SPI_SR_OFFSET 0x0008 /* SPI status register (16-bit) */ -#define STM32F7_SPI_DR_OFFSET 0x000c /* SPI data register (16-bit) */ -#define STM32F7_SPI_CRCPR_OFFSET 0x0010 /* SPI CRC polynomial register (16-bit) */ -#define STM32F7_SPI_RXCRCR_OFFSET 0x0014 /* SPI Rx CRC register (16-bit) */ -#define STM32F7_SPI_TXCRCR_OFFSET 0x0018 /* SPI Tx CRC register (16-bit) */ - -/* Register Addresses ***************************************************************/ - -#if STM32F7_NSPI > 0 -# define STM32F7_SPI1_CR1 (STM32_SPI1_BASE+STM32F7_SPI_CR1_OFFSET) -# define STM32F7_SPI1_CR2 (STM32_SPI1_BASE+STM32F7_SPI_CR2_OFFSET) -# define STM32F7_SPI1_SR (STM32_SPI1_BASE+STM32F7_SPI_SR_OFFSET) -# define STM32F7_SPI1_DR (STM32_SPI1_BASE+STM32F7_SPI_DR_OFFSET) -# define STM32F7_SPI1_CRCPR (STM32_SPI1_BASE+STM32F7_SPI_CRCPR_OFFSET) -# define STM32F7_SPI1_RXCRCR (STM32_SPI1_BASE+STM32F7_SPI_RXCRCR_OFFSET) -# define STM32F7_SPI1_TXCRCR (STM32_SPI1_BASE+STM32F7_SPI_TXCRCR_OFFSET) -#endif - -#if STM32F7_NSPI > 1 -# define STM32F7_SPI2_CR1 (STM32_SPI2_BASE+STM32F7_SPI_CR1_OFFSET) -# define STM32F7_SPI2_CR2 (STM32_SPI2_BASE+STM32F7_SPI_CR2_OFFSET) -# define STM32F7_SPI2_SR (STM32_SPI2_BASE+STM32F7_SPI_SR_OFFSET) -# define STM32F7_SPI2_DR (STM32_SPI2_BASE+STM32F7_SPI_DR_OFFSET) -# define STM32F7_SPI2_CRCPR (STM32_SPI2_BASE+STM32F7_SPI_CRCPR_OFFSET) -# define STM32F7_SPI2_RXCRCR (STM32_SPI2_BASE+STM32F7_SPI_RXCRCR_OFFSET) -# define STM32F7_SPI2_TXCRCR (STM32_SPI2_BASE+STM32F7_SPI_TXCRCR_OFFSET) -#endif - -#if STM32F7_NSPI > 2 -# define STM32F7_SPI3_CR1 (STM32_SPI3_BASE+STM32F7_SPI_CR1_OFFSET) -# define STM32F7_SPI3_CR2 (STM32_SPI3_BASE+STM32F7_SPI_CR2_OFFSET) -# define STM32F7_SPI3_SR (STM32_SPI3_BASE+STM32F7_SPI_SR_OFFSET) -# define STM32F7_SPI3_DR (STM32_SPI3_BASE+STM32F7_SPI_DR_OFFSET) -# define STM32F7_SPI3_CRCPR (STM32_SPI3_BASE+STM32F7_SPI_CRCPR_OFFSET) -# define STM32F7_SPI3_RXCRCR (STM32_SPI3_BASE+STM32F7_SPI_RXCRCR_OFFSET) -# define STM32F7_SPI3_TXCRCR (STM32_SPI3_BASE+STM32F7_SPI_TXCRCR_OFFSET) -#endif - -#if STM32F7_NSPI > 3 -# define STM32F7_SPI4_CR1 (STM32_SPI4_BASE+STM32F7_SPI_CR1_OFFSET) -# define STM32F7_SPI4_CR2 (STM32_SPI4_BASE+STM32F7_SPI_CR2_OFFSET) -# define STM32F7_SPI4_SR (STM32_SPI4_BASE+STM32F7_SPI_SR_OFFSET) -# define STM32F7_SPI4_DR (STM32_SPI4_BASE+STM32F7_SPI_DR_OFFSET) -# define STM32F7_SPI4_CRCPR (STM32_SPI4_BASE+STM32F7_SPI_CRCPR_OFFSET) -# define STM32F7_SPI4_RXCRCR (STM32_SPI4_BASE+STM32F7_SPI_RXCRCR_OFFSET) -# define STM32F7_SPI4_TXCRCR (STM32_SPI4_BASE+STM32F7_SPI_TXCRCR_OFFSET) -#endif - -#if STM32F7_NSPI > 4 -# define STM32F7_SPI5_CR1 (STM32_SPI5_BASE+STM32F7_SPI_CR1_OFFSET) -# define STM32F7_SPI5_CR2 (STM32_SPI5_BASE+STM32F7_SPI_CR2_OFFSET) -# define STM32F7_SPI5_SR (STM32_SPI5_BASE+STM32F7_SPI_SR_OFFSET) -# define STM32F7_SPI5_DR (STM32_SPI5_BASE+STM32F7_SPI_DR_OFFSET) -# define STM32F7_SPI5_CRCPR (STM32_SPI5_BASE+STM32F7_SPI_CRCPR_OFFSET) -# define STM32F7_SPI5_RXCRCR (STM32_SPI5_BASE+STM32F7_SPI_RXCRCR_OFFSET) -# define STM32F7_SPI5_TXCRCR (STM32_SPI5_BASE+STM32F7_SPI_TXCRCR_OFFSET) -#endif - -#if STM32F7_NSPI > 5 -# define STM32F7_SPI6_CR1 (STM32_SPI6_BASE+STM32F7_SPI_CR1_OFFSET) -# define STM32F7_SPI6_CR2 (STM32_SPI6_BASE+STM32F7_SPI_CR2_OFFSET) -# define STM32F7_SPI6_SR (STM32_SPI6_BASE+STM32F7_SPI_SR_OFFSET) -# define STM32F7_SPI6_DR (STM32_SPI6_BASE+STM32F7_SPI_DR_OFFSET) -# define STM32F7_SPI6_CRCPR (STM32_SPI6_BASE+STM32F7_SPI_CRCPR_OFFSET) -# define STM32F7_SPI6_RXCRCR (STM32_SPI6_BASE+STM32F7_SPI_RXCRCR_OFFSET) -# define STM32F7_SPI6_TXCRCR (STM32_SPI6_BASE+STM32F7_SPI_TXCRCR_OFFSET) -#endif - -/* Register Bitfield Definitions ****************************************************/ - -/* SPI Control Register 1 */ - -#define SPI_CR1_CPHA (1 << 0) /* Bit 0: Clock Phase */ -#define SPI_CR1_CPOL (1 << 1) /* Bit 1: Clock Polarity */ -#define SPI_CR1_MSTR (1 << 2) /* Bit 2: Master Selection */ -#define SPI_CR1_BR_SHIFT (3) /* Bits 5:3 Baud Rate Control */ -#define SPI_CR1_BR_MASK (7 << SPI_CR1_BR_SHIFT) -# define SPI_CR1_FPCLCKd2 (0 << SPI_CR1_BR_SHIFT) /* 000: fPCLK/2 */ -# define SPI_CR1_FPCLCKd4 (1 << SPI_CR1_BR_SHIFT) /* 001: fPCLK/4 */ -# define SPI_CR1_FPCLCKd8 (2 << SPI_CR1_BR_SHIFT) /* 010: fPCLK/8 */ -# define SPI_CR1_FPCLCKd16 (3 << SPI_CR1_BR_SHIFT) /* 011: fPCLK/16 */ -# define SPI_CR1_FPCLCKd32 (4 << SPI_CR1_BR_SHIFT) /* 100: fPCLK/32 */ -# define SPI_CR1_FPCLCKd64 (5 << SPI_CR1_BR_SHIFT) /* 101: fPCLK/64 */ -# define SPI_CR1_FPCLCKd128 (6 << SPI_CR1_BR_SHIFT) /* 110: fPCLK/128 */ -# define SPI_CR1_FPCLCKd256 (7 << SPI_CR1_BR_SHIFT) /* 111: fPCLK/256 */ -#define SPI_CR1_SPE (1 << 6) /* Bit 6: SPI Enable */ -#define SPI_CR1_LSBFIRST (1 << 7) /* Bit 7: Frame Format */ -#define SPI_CR1_SSI (1 << 8) /* Bit 8: Internal slave select */ -#define SPI_CR1_SSM (1 << 9) /* Bit 9: Software slave management */ -#define SPI_CR1_RXONLY (1 << 10) /* Bit 10: Receive only */ -#define SPI_CR1_CRCL (1 << 11) /* Bit 11: CRC length */ -#define SPI_CR1_CRCNEXT (1 << 12) /* Bit 12: Transmit CRC next */ -#define SPI_CR1_CRCEN (1 << 13) /* Bit 13: Hardware CRC calculation enable */ -#define SPI_CR1_BIDIOE (1 << 14) /* Bit 14: Output enable in bidirectional mode */ -#define SPI_CR1_BIDIMODE (1 << 15) /* Bit 15: Bidirectional data mode enable */ - -/* SPI Control Register 2 */ - -#define SPI_CR2_RXDMAEN (1 << 0) /* Bit 0: Rx Buffer DMA Enable */ -#define SPI_CR2_TXDMAEN (1 << 1) /* Bit 1: Tx Buffer DMA Enable */ -#define SPI_CR2_SSOE (1 << 2) /* Bit 2: SS Output Enable */ -#define SPI_CR2_NSSP (1 << 3) /* Bit 3: NSS pulse management */ -#define SPI_CR2_FRF (1 << 4) /* Bit 4: Frame format */ -#define SPI_CR2_ERRIE (1 << 5) /* Bit 5: Error interrupt enable */ -#define SPI_CR2_RXNEIE (1 << 6) /* Bit 6: RX buffer not empty interrupt enable */ -#define SPI_CR2_TXEIE (1 << 7) /* Bit 7: Tx buffer empty interrupt enable */ -#define SPI_CR2_DS_SHIFT (8) /* Bits 8-11: Data size */ -#define SPI_CR2_DS_MASK (15 << SPI_CR2_DS_SHIFT) -# define SPI_CR2_DS_VAL(bits) (((uint32_t)(bits)-1) << SPI_CR2_DS_SHIFT) -# define SPI_CR2_DS_4BIT SPI_CR2_DS_VAL( 4) -# define SPI_CR2_DS_5BIT SPI_CR2_DS_VAL( 5) -# define SPI_CR2_DS_6BIT SPI_CR2_DS_VAL( 6) -# define SPI_CR2_DS_7BIT SPI_CR2_DS_VAL( 7) -# define SPI_CR2_DS_8BIT SPI_CR2_DS_VAL( 8) -# define SPI_CR2_DS_9BIT SPI_CR2_DS_VAL( 9) -# define SPI_CR2_DS_10BIT SPI_CR2_DS_VAL(10) -# define SPI_CR2_DS_11BIT SPI_CR2_DS_VAL(11) -# define SPI_CR2_DS_12BIT SPI_CR2_DS_VAL(12) -# define SPI_CR2_DS_13BIT SPI_CR2_DS_VAL(13) -# define SPI_CR2_DS_14BIT SPI_CR2_DS_VAL(14) -# define SPI_CR2_DS_15BIT SPI_CR2_DS_VAL(15) -# define SPI_CR2_DS_16BIT SPI_CR2_DS_VAL(16) -#define SPI_CR2_FRXTH (1 << 12) /* Bit 12: FIFO reception threshold */ -#define SPI_CR2_LDMARX (1 << 13) /* Bit 13: Last DMA transfer for receptione */ -#define SPI_CR2_LDMATX (1 << 14) /* Bit 14: Last DMA transfer for transmission */ - -/* SPI status register */ - -#define SPI_SR_RXNE (1 << 0) /* Bit 0: Receive buffer not empty */ -#define SPI_SR_TXE (1 << 1) /* Bit 1: Transmit buffer empty */ -#define SPI_SR_CRCERR (1 << 4) /* Bit 4: CRC error flag */ -#define SPI_SR_MODF (1 << 5) /* Bit 5: Mode fault */ -#define SPI_SR_OVR (1 << 6) /* Bit 6: Overrun flag */ -#define SPI_SR_BSY (1 << 7) /* Bit 7: Busy flag */ -#define SPI_SR_FRE (1 << 8) /* Bit 8: Frame format error */ -#define SPI_SR_FRLVL_SHIFT (9) /* Bits 9-10: FIFO reception level */ -#define SPI_SR_FRLVL_MASK (3 << SPI_SR_FRLVL_SHIFT) -# define SPI_SR_FRLVL_EMPTY (0 << SPI_SR_FRLVL_SHIFT) /* FIFO empty */ -# define SPI_SR_FRLVL_QUARTER (1 << SPI_SR_FRLVL_SHIFT) /* 1/4 FIFO */ -# define SPI_SR_FRLVL_HALF (2 << SPI_SR_FRLVL_SHIFT) /* 1/2 FIFO */ -# define SPI_SR_FRLVL_FULL (3 << SPI_SR_FRLVL_SHIFT) /* FIFO full */ -#define SPI_SR_FTLVL_SHIFT (11) /* Bits 11-12: FIFO transmission level */ -#define SPI_SR_FTLVL_MASK (3 << SPI_SR_FTLVL_SHIFT) -# define SPI_SR_FTLVL_EMPTY (0 << SPI_SR_FTLVL_SHIFT) /* FIFO empty */ -# define SPI_SR_FTLVL_QUARTER (1 << SPI_SR_FTLVL_SHIFT) /* 1/4 FIFO */ -# define SPI_SR_FTLVL_HALF (2 << SPI_SR_FTLVL_SHIFT) /* 1/2 FIFO */ -# define SPI_SR_FTLVL_FULL (3 << SPI_SR_FTLVL_SHIFT) /* FIFO full */ - -#endif /* __ARCH_ARM_SRC_STM32F7_CHIP_STM32F74XX75XX_SPI_H */ - From bc8d1cdfd8551ddcaf332ca46413db7533be9c3c Mon Sep 17 00:00:00 2001 From: David Sidrane Date: Wed, 15 Jun 2016 11:26:44 -1000 Subject: [PATCH 53/75] Use two level include 74xx77xx SPI --- arch/arm/src/stm32f7/chip/stm32_spi.h | 215 +-------------- .../arm/src/stm32f7/chip/stm32f74xx77xx_spi.h | 258 ++++++++++++++++++ 2 files changed, 263 insertions(+), 210 deletions(-) create mode 100644 arch/arm/src/stm32f7/chip/stm32f74xx77xx_spi.h diff --git a/arch/arm/src/stm32f7/chip/stm32_spi.h b/arch/arm/src/stm32f7/chip/stm32_spi.h index 33e34789fb..1874d88bca 100644 --- a/arch/arm/src/stm32f7/chip/stm32_spi.h +++ b/arch/arm/src/stm32f7/chip/stm32_spi.h @@ -44,215 +44,10 @@ #include #include "chip.h" -/************************************************************************************ - * Pre-processor Definitions - ************************************************************************************/ - -/* Maximum allowed speed as per data sheet for all SPIs (both pclk1 and pclk2)*/ - -#if defined(CONFIG_STM32F7_STM32F74XX) || defined(CONFIG_STM32F7_STM32F75XX) -# define STM32_SPI_CLK_MAX 50000000UL -#elif defined(CONFIG_STM32F7_STM32F76XX) || defined(CONFIG_STM32F7_STM32F77XX) -# define STM32_SPI_CLK_MAX 54000000UL +#if defined(CONFIG_STM32F7_STM32F74XX) || defined(CONFIG_STM32F7_STM32F75XX) || \ + defined(CONFIG_STM32F7_STM32F76XX) || defined(CONFIG_STM32F7_STM32F77XX) +# include "chip/stm32f74xx77xx_spi.h" +#else +# error "Unsupported STM32 F7 sub family" #endif - -/* Register Offsets *****************************************************************/ - -#define STM32_SPI_CR1_OFFSET 0x0000 /* SPI Control Register 1 (16-bit) */ -#define STM32_SPI_CR2_OFFSET 0x0004 /* SPI control register 2 (16-bit) */ -#define STM32_SPI_SR_OFFSET 0x0008 /* SPI status register (16-bit) */ -#define STM32_SPI_DR_OFFSET 0x000c /* SPI data register (16-bit) */ -#define STM32_SPI_CRCPR_OFFSET 0x0010 /* SPI CRC polynomial register (16-bit) */ -#define STM32_SPI_RXCRCR_OFFSET 0x0014 /* SPI Rx CRC register (16-bit) */ -#define STM32_SPI_TXCRCR_OFFSET 0x0018 /* SPI Tx CRC register (16-bit) */ -#define STM32_SPI_I2SCFGR_OFFSET 0x001c /* I2S configuration register */ -#define STM32_SPI_I2SPR_OFFSET 0x0020 /* I2S prescaler register */ - -/* Register Addresses ***************************************************************/ - -#if STM32F7_NSPI > 0 -# define STM32_SPI1_CR1 (STM32_SPI1_BASE+STM32_SPI_CR1_OFFSET) -# define STM32_SPI1_CR2 (STM32_SPI1_BASE+STM32_SPI_CR2_OFFSET) -# define STM32_SPI1_SR (STM32_SPI1_BASE+STM32_SPI_SR_OFFSET) -# define STM32_SPI1_DR (STM32_SPI1_BASE+STM32_SPI_DR_OFFSET) -# define STM32_SPI1_CRCPR (STM32_SPI1_BASE+STM32_SPI_CRCPR_OFFSET) -# define STM32_SPI1_RXCRCR (STM32_SPI1_BASE+STM32_SPI_RXCRCR_OFFSET) -# define STM32_SPI1_TXCRCR (STM32_SPI1_BASE+STM32_SPI_TXCRCR_OFFSET) -#endif - -#if STM32F7_NSPI > 1 -# define STM32_SPI2_CR1 (STM32_SPI2_BASE+STM32_SPI_CR1_OFFSET) -# define STM32_SPI2_CR2 (STM32_SPI2_BASE+STM32_SPI_CR2_OFFSET) -# define STM32_SPI2_SR (STM32_SPI2_BASE+STM32_SPI_SR_OFFSET) -# define STM32_SPI2_DR (STM32_SPI2_BASE+STM32_SPI_DR_OFFSET) -# define STM32_SPI2_CRCPR (STM32_SPI2_BASE+STM32_SPI_CRCPR_OFFSET) -# define STM32_SPI2_RXCRCR (STM32_SPI2_BASE+STM32_SPI_RXCRCR_OFFSET) -# define STM32_SPI2_TXCRCR (STM32_SPI2_BASE+STM32_SPI_TXCRCR_OFFSET) -# define STM32_SPI2_I2SCFGR (STM32_SPI2_BASE+STM32_SPI_I2SCFGR_OFFSET) -# define STM32_SPI2_I2SPR (STM32_SPI2_BASE+STM32_SPI_I2SPR_OFFSET) -#endif - -#if STM32F7_NSPI > 2 -# define STM32_SPI3_CR1 (STM32_SPI3_BASE+STM32_SPI_CR1_OFFSET) -# define STM32_SPI3_CR2 (STM32_SPI3_BASE+STM32_SPI_CR2_OFFSET) -# define STM32_SPI3_SR (STM32_SPI3_BASE+STM32_SPI_SR_OFFSET) -# define STM32_SPI3_DR (STM32_SPI3_BASE+STM32_SPI_DR_OFFSET) -# define STM32_SPI3_CRCPR (STM32_SPI3_BASE+STM32_SPI_CRCPR_OFFSET) -# define STM32_SPI3_RXCRCR (STM32_SPI3_BASE+STM32_SPI_RXCRCR_OFFSET) -# define STM32_SPI3_TXCRCR (STM32_SPI3_BASE+STM32_SPI_TXCRCR_OFFSET) -# define STM32_SPI3_I2SCFGR (STM32_SPI3_BASE+STM32_SPI_I2SCFGR_OFFSET) -# define STM32_SPI3_I2SPR (STM32_SPI3_BASE+STM32_SPI_I2SPR_OFFSET) -#endif - -#if STM32F7_NSPI > 3 -# define STM32_SPI4_CR1 (STM32_SPI4_BASE+STM32_SPI_CR1_OFFSET) -# define STM32_SPI4_CR2 (STM32_SPI4_BASE+STM32_SPI_CR2_OFFSET) -# define STM32_SPI4_SR (STM32_SPI4_BASE+STM32_SPI_SR_OFFSET) -# define STM32_SPI4_DR (STM32_SPI4_BASE+STM32_SPI_DR_OFFSET) -# define STM32_SPI4_CRCPR (STM32_SPI4_BASE+STM32_SPI_CRCPR_OFFSET) -# define STM32_SPI4_RXCRCR (STM32_SPI4_BASE+STM32_SPI_RXCRCR_OFFSET) -# define STM32_SPI4_TXCRCR (STM32_SPI4_BASE+STM32_SPI_TXCRCR_OFFSET) -# define STM32_SPI4_I2SCFGR (STM32_SPI4_BASE+STM32_SPI_I2SCFGR_OFFSET) -# define STM32_SPI4_I2SPR (STM32_SPI4_BASE+STM32_SPI_I2SPR_OFFSET) -#endif - -#if STM32F7_NSPI > 4 -# define STM32_SPI5_CR1 (STM32_SPI5_BASE+STM32_SPI_CR1_OFFSET) -# define STM32_SPI5_CR2 (STM32_SPI5_BASE+STM32_SPI_CR2_OFFSET) -# define STM32_SPI5_SR (STM32_SPI5_BASE+STM32_SPI_SR_OFFSET) -# define STM32_SPI5_DR (STM32_SPI5_BASE+STM32_SPI_DR_OFFSET) -# define STM32_SPI5_CRCPR (STM32_SPI5_BASE+STM32_SPI_CRCPR_OFFSET) -# define STM32_SPI5_RXCRCR (STM32_SPI5_BASE+STM32_SPI_RXCRCR_OFFSET) -# define STM32_SPI5_TXCRCR (STM32_SPI5_BASE+STM32_SPI_TXCRCR_OFFSET) -# define STM32_SPI5_I2SCFGR (STM32_SPI5_BASE+STM32_SPI_I2SCFGR_OFFSET) -# define STM32_SPI5_I2SPR (STM32_SPI5_BASE+STM32_SPI_I2SPR_OFFSET) -#endif - -#if STM32F7_NSPI > 5 -# define STM32_SPI6_CR1 (STM32_SPI6_BASE+STM32_SPI_CR1_OFFSET) -# define STM32_SPI6_CR2 (STM32_SPI6_BASE+STM32_SPI_CR2_OFFSET) -# define STM32_SPI6_SR (STM32_SPI6_BASE+STM32_SPI_SR_OFFSET) -# define STM32_SPI6_DR (STM32_SPI6_BASE+STM32_SPI_DR_OFFSET) -# define STM32_SPI6_CRCPR (STM32_SPI6_BASE+STM32_SPI_CRCPR_OFFSET) -# define STM32_SPI6_RXCRCR (STM32_SPI6_BASE+STM32_SPI_RXCRCR_OFFSET) -# define STM32_SPI6_TXCRCR (STM32_SPI6_BASE+STM32_SPI_TXCRCR_OFFSET) -# define STM32_SPI6_I2SCFGR (STM32_SPI6_BASE+STM32_SPI_I2SCFGR_OFFSET) -# define STM32_SPI6_I2SPR (STM32_SPI6_BASE+STM32_SPI_I2SPR_OFFSET) -#endif - -/* Register Bitfield Definitions ****************************************************/ - -/* SPI Control Register 1 */ - -#define SPI_CR1_CPHA (1 << 0) /* Bit 0: Clock Phase */ -#define SPI_CR1_CPOL (1 << 1) /* Bit 1: Clock Polarity */ -#define SPI_CR1_MSTR (1 << 2) /* Bit 2: Master Selection */ -#define SPI_CR1_BR_SHIFT (3) /* Bits 5:3 Baud Rate Control */ -#define SPI_CR1_BR_MASK (7 << SPI_CR1_BR_SHIFT) -# define SPI_CR1_FPCLCKd2 (0 << SPI_CR1_BR_SHIFT) /* 000: fPCLK/2 */ -# define SPI_CR1_FPCLCKd4 (1 << SPI_CR1_BR_SHIFT) /* 001: fPCLK/4 */ -# define SPI_CR1_FPCLCKd8 (2 << SPI_CR1_BR_SHIFT) /* 010: fPCLK/8 */ -# define SPI_CR1_FPCLCKd16 (3 << SPI_CR1_BR_SHIFT) /* 011: fPCLK/16 */ -# define SPI_CR1_FPCLCKd32 (4 << SPI_CR1_BR_SHIFT) /* 100: fPCLK/32 */ -# define SPI_CR1_FPCLCKd64 (5 << SPI_CR1_BR_SHIFT) /* 101: fPCLK/64 */ -# define SPI_CR1_FPCLCKd128 (6 << SPI_CR1_BR_SHIFT) /* 110: fPCLK/128 */ -# define SPI_CR1_FPCLCKd256 (7 << SPI_CR1_BR_SHIFT) /* 111: fPCLK/256 */ -#define SPI_CR1_SPE (1 << 6) /* Bit 6: SPI Enable */ -#define SPI_CR1_LSBFIRST (1 << 7) /* Bit 7: Frame Format */ -#define SPI_CR1_SSI (1 << 8) /* Bit 8: Internal slave select */ -#define SPI_CR1_SSM (1 << 9) /* Bit 9: Software slave management */ -#define SPI_CR1_RXONLY (1 << 10) /* Bit 10: Receive only */ -#define SPI_CR1_CRCL (1 << 11) /* Bit 11: CRC length */ -#define SPI_CR1_CRCNEXT (1 << 12) /* Bit 12: Transmit CRC next */ -#define SPI_CR1_CRCEN (1 << 13) /* Bit 13: Hardware CRC calculation enable */ -#define SPI_CR1_BIDIOE (1 << 14) /* Bit 14: Output enable in bidirectional mode */ -#define SPI_CR1_BIDIMODE (1 << 15) /* Bit 15: Bidirectional data mode enable */ - -/* SPI Control Register 2 */ - -#define SPI_CR2_RXDMAEN (1 << 0) /* Bit 0: Rx Buffer DMA Enable */ -#define SPI_CR2_TXDMAEN (1 << 1) /* Bit 1: Tx Buffer DMA Enable */ -#define SPI_CR2_SSOE (1 << 2) /* Bit 2: SS Output Enable */ -#define SPI_CR2_NSSP (1 << 3) /* Bit 3 NSSP: NSS pulse management */ -#define SPI_CR2_FRF (1 << 4) /* Bit 4: Frame format */ -#define SPI_CR2_ERRIE (1 << 5) /* Bit 5: Error interrupt enable */ -#define SPI_CR2_RXNEIE (1 << 6) /* Bit 6: RX buffer not empty interrupt enable */ -#define SPI_CR2_TXEIE (1 << 7) /* Bit 7: Tx buffer empty interrupt enable */ -#define SPI_CR2_DS_SHIFT (8) /* Bits 8-11: Data size */ -#define SPI_CR2_DS_MASK (0xf << SPI_CR2_DS_SHIFT) -# define SPI_CR2_DS_VAL(bits) (((bits)-1) << SPI_CR2_DS_SHIFT) -# define SPI_CR2_DS_4BIT SPI_CR2_DS_VAL(4) -# define SPI_CR2_DS_5BIT SPI_CR2_DS_VAL(5) -# define SPI_CR2_DS_6BIT SPI_CR2_DS_VAL(6) -# define SPI_CR2_DS_7BIT SPI_CR2_DS_VAL(7) -# define SPI_CR2_DS_8BIT SPI_CR2_DS_VAL(8) -# define SPI_CR2_DS_9BIT SPI_CR2_DS_VAL(9) -# define SPI_CR2_DS_10BIT SPI_CR2_DS_VAL(10) -# define SPI_CR2_DS_11BIT SPI_CR2_DS_VAL(11) -# define SPI_CR2_DS_12BIT SPI_CR2_DS_VAL(12) -# define SPI_CR2_DS_13BIT SPI_CR2_DS_VAL(13) -# define SPI_CR2_DS_14BIT SPI_CR2_DS_VAL(14) -# define SPI_CR2_DS_15BIT SPI_CR2_DS_VAL(15) -# define SPI_CR2_DS_16BIT SPI_CR2_DS_VAL(16) -#define SPI_CR2_FRXTH (1 << 12) /* Bit 12: FIFO reception threshold */ -#define SPI_CR2_LDMARX (1 << 13) /* Bit 13: Last DMA transfer for receptione */ -#define SPI_CR2_LDMATX (1 << 14) /* Bit 14: Last DMA transfer for transmission */ - -/* SPI status register */ - -#define SPI_SR_RXNE (1 << 0) /* Bit 0: Receive buffer not empty */ -#define SPI_SR_TXE (1 << 1) /* Bit 1: Transmit buffer empty */ -#define SPI_SR_CHSIDE (1 << 2) /* Bit 2: Channel side (i2s) */ -#define SPI_SR_UDR (1 << 3) /* Bit 3: Underrun flag (i2s) */ -#define SPI_SR_CRCERR (1 << 4) /* Bit 4: CRC error flag */ -#define SPI_SR_MODF (1 << 5) /* Bit 5: Mode fault */ -#define SPI_SR_OVR (1 << 6) /* Bit 6: Overrun flag */ -#define SPI_SR_BSY (1 << 7) /* Bit 7: Busy flag */ -#define SPI_SR_FRE (1 << 8) /* Bit 8: Frame format error */ -#define SPI_SR_FRLVL_SHIFT (9) /* Bits 9-10: FIFO reception level */ -#define SPI_SR_FRLVL_MASK (0x3 << SPI_SR_FRLVL_SHIFT) -# define SPI_SR_FRLVL_EMPTY (0 << SPI_SR_FRLVL_SHIFT) /* FIFO empty */ -# define SPI_SR_FRLVL_QUARTER (1 << SPI_SR_FRLVL_SHIFT) /* 1/4 FIFO */ -# define SPI_SR_FRLVL_HALF (2 << SPI_SR_FRLVL_SHIFT) /* 1/2 FIFO */ -# define SPI_SR_FRLVL_FULL (3 << SPI_SR_FRLVL_SHIFT) /* FIFO full */ -#define SPI_SR_FTLVL_SHIFT (11) /* Bits 11-12: FIFO transmission level */ -#define SPI_SR_FTLVL_MASK (0x3 << SPI_SR_FTLVL_SHIFT) -# define SPI_SR_FTLVL_EMPTY (0 << SPI_SR_FTLVL_SHIFT) /* FIFO empty */ -# define SPI_SR_FTLVL_QUARTER (1 << SPI_SR_FTLVL_SHIFT) /* 1/4 FIFO */ -# define SPI_SR_FTLVL_HALF (2 << SPI_SR_FTLVL_SHIFT) /* 1/2 FIFO */ -# define SPI_SR_FTLVL_FULL (3 << SPI_SR_FTLVL_SHIFT) /* FIFO full */ - -/* I2S configuration register */ - -#define SPI_I2SCFGR_CHLEN (1 << 0) /* Bit 0: Channel length (number of bits per audio channel) */ -#define SPI_I2SCFGR_DATLEN_SHIFT (1) /* Bit 1-2: Data length to be transferred */ -#define SPI_I2SCFGR_DATLEN_MASK (3 << SPI_I2SCFGR_DATLEN_SHIFT) -# define SPI_I2SCFGR_DATLEN_16BIT (0 << SPI_I2SCFGR_DATLEN_SHIFT) /* 00: 16-bit data length */ -# define SPI_I2SCFGR_DATLEN_8BIT (1 << SPI_I2SCFGR_DATLEN_SHIFT) /* 01: 24-bit data length */ -# define SPI_I2SCFGR_DATLEN_32BIT (2 << SPI_I2SCFGR_DATLEN_SHIFT) /* 10: 32-bit data length */ -#define SPI_I2SCFGR_CKPOL (1 << 3) /* Bit 3: Steady state clock polarity */ -#define SPI_I2SCFGR_I2SSTD_SHIFT (4) /* Bit 4-5: I2S standard selection */ -#define SPI_I2SCFGR_I2SSTD_MASK (3 << SPI_I2SCFGR_I2SSTD_SHIFT) -# define SPI_I2SCFGR_I2SSTD_PHILLIPS (00 << SPI_I2SCFGR_I2SSTD_SHIFT) /* 00: I2S Phillips standard. */ -# define SPI_I2SCFGR_I2SSTD_MSB (1 << SPI_I2SCFGR_I2SSTD_SHIFT) /* 01: MSB justified standard (left justified) */ -# define SPI_I2SCFGR_I2SSTD_LSB (2 << SPI_I2SCFGR_I2SSTD_SHIFT) /* 10: LSB justified standard (right justified) */ -# define SPI_I2SCFGR_I2SSTD_PCM (3 << SPI_I2SCFGR_I2SSTD_SHIFT) /* 11: PCM standard */ -#define SPI_I2SCFGR_PCMSYNC (1 << 7) /* Bit 7: PCM frame synchronization */ -#define SPI_I2SCFGR_I2SCFG_SHIFT (8) /* Bit 8-9: I2S configuration mode */ -#define SPI_I2SCFGR_I2SCFG_MASK (3 << SPI_I2SCFGR_I2SCFG_SHIFT) -# define SPI_I2SCFGR_I2SCFG_STX (0 << SPI_I2SCFGR_I2SCFG_SHIFT) /* 00: Slave - transmit */ -# define SPI_I2SCFGR_I2SCFG_SRX (1 << SPI_I2SCFGR_I2SCFG_SHIFT) /* 01: Slave - receive */ -# define SPI_I2SCFGR_I2SCFG_MTX (2 << SPI_I2SCFGR_I2SCFG_SHIFT) /* 10: Master - transmit */ -# define SPI_I2SCFGR_I2SCFG_MRX (3 << SPI_I2SCFGR_I2SCFG_SHIFT) /* 11: Master - receive */ -#define SPI_I2SCFGR_I2SE (1 << 10) /* Bit 10: I2S Enable */ -#define SPI_I2SCFGR_I2SMOD (1 << 11) /* Bit 11: I2S mode selection */ -#define SPI_I2SCFGR_ASTRTEN (1 << 12) /* Bit 12: Asynchronous start enable */ - -/* I2S prescaler register */ - -#define SPI_I2SPR_I2SDIV_SHIFT (0) /* Bit 0-7: I2S Linear prescaler */ -#define SPI_I2SPR_I2SDIV_MASK (0xff << SPI_I2SPR_I2SDIV_SHIFT) -#define SPI_I2SPR_ODD (1 << 8) /* Bit 8: Odd factor for the prescaler */ -#define SPI_I2SPR_MCKOE (1 << 9) /* Bit 9: Master clock output enable */ - #endif /* __ARCH_ARM_SRC_STM32F7_CHIP_STM32_SPI_H */ diff --git a/arch/arm/src/stm32f7/chip/stm32f74xx77xx_spi.h b/arch/arm/src/stm32f7/chip/stm32f74xx77xx_spi.h new file mode 100644 index 0000000000..61725763cd --- /dev/null +++ b/arch/arm/src/stm32f7/chip/stm32f74xx77xx_spi.h @@ -0,0 +1,258 @@ +/************************************************************************************ + * arch/arm/src/stm32f7/chip/stm32f74xx77xx_spi.h + *stm32f74xx77xx + * Copyright (C) 2016 Gregory Nutt. All rights reserved. + * Authors: Gregory Nutt + * David Sidrane + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ************************************************************************************/ + +#ifndef __ARCH_ARM_SRC_STM32F7_CHIP_STM32F74XX77XX_SPI_H +#define __ARCH_ARM_SRC_STM32F7_CHIP_STM32F74XX77XX_SPI_H + +/************************************************************************************ + * Included Files + ************************************************************************************/ + +#include +#include "chip.h" + +/************************************************************************************ + * Pre-processor Definitions + ************************************************************************************/ + +/* Maximum allowed speed as per data sheet for all SPIs (both pclk1 and pclk2)*/ + +#if defined(CONFIG_STM32F7_STM32F74XX) || defined(CONFIG_STM32F7_STM32F75XX) +# define STM32_SPI_CLK_MAX 50000000UL +#elif defined(CONFIG_STM32F7_STM32F76XX) || defined(CONFIG_STM32F7_STM32F77XX) +# define STM32_SPI_CLK_MAX 54000000UL +#endif + +/* Register Offsets *****************************************************************/ + +#define STM32_SPI_CR1_OFFSET 0x0000 /* SPI Control Register 1 (16-bit) */ +#define STM32_SPI_CR2_OFFSET 0x0004 /* SPI control register 2 (16-bit) */ +#define STM32_SPI_SR_OFFSET 0x0008 /* SPI status register (16-bit) */ +#define STM32_SPI_DR_OFFSET 0x000c /* SPI data register (16-bit) */ +#define STM32_SPI_CRCPR_OFFSET 0x0010 /* SPI CRC polynomial register (16-bit) */ +#define STM32_SPI_RXCRCR_OFFSET 0x0014 /* SPI Rx CRC register (16-bit) */ +#define STM32_SPI_TXCRCR_OFFSET 0x0018 /* SPI Tx CRC register (16-bit) */ +#define STM32_SPI_I2SCFGR_OFFSET 0x001c /* I2S configuration register */ +#define STM32_SPI_I2SPR_OFFSET 0x0020 /* I2S prescaler register */ + +/* Register Addresses ***************************************************************/ + +#if STM32F7_NSPI > 0 +# define STM32_SPI1_CR1 (STM32_SPI1_BASE+STM32_SPI_CR1_OFFSET) +# define STM32_SPI1_CR2 (STM32_SPI1_BASE+STM32_SPI_CR2_OFFSET) +# define STM32_SPI1_SR (STM32_SPI1_BASE+STM32_SPI_SR_OFFSET) +# define STM32_SPI1_DR (STM32_SPI1_BASE+STM32_SPI_DR_OFFSET) +# define STM32_SPI1_CRCPR (STM32_SPI1_BASE+STM32_SPI_CRCPR_OFFSET) +# define STM32_SPI1_RXCRCR (STM32_SPI1_BASE+STM32_SPI_RXCRCR_OFFSET) +# define STM32_SPI1_TXCRCR (STM32_SPI1_BASE+STM32_SPI_TXCRCR_OFFSET) +#endif + +#if STM32F7_NSPI > 1 +# define STM32_SPI2_CR1 (STM32_SPI2_BASE+STM32_SPI_CR1_OFFSET) +# define STM32_SPI2_CR2 (STM32_SPI2_BASE+STM32_SPI_CR2_OFFSET) +# define STM32_SPI2_SR (STM32_SPI2_BASE+STM32_SPI_SR_OFFSET) +# define STM32_SPI2_DR (STM32_SPI2_BASE+STM32_SPI_DR_OFFSET) +# define STM32_SPI2_CRCPR (STM32_SPI2_BASE+STM32_SPI_CRCPR_OFFSET) +# define STM32_SPI2_RXCRCR (STM32_SPI2_BASE+STM32_SPI_RXCRCR_OFFSET) +# define STM32_SPI2_TXCRCR (STM32_SPI2_BASE+STM32_SPI_TXCRCR_OFFSET) +# define STM32_SPI2_I2SCFGR (STM32_SPI2_BASE+STM32_SPI_I2SCFGR_OFFSET) +# define STM32_SPI2_I2SPR (STM32_SPI2_BASE+STM32_SPI_I2SPR_OFFSET) +#endif + +#if STM32F7_NSPI > 2 +# define STM32_SPI3_CR1 (STM32_SPI3_BASE+STM32_SPI_CR1_OFFSET) +# define STM32_SPI3_CR2 (STM32_SPI3_BASE+STM32_SPI_CR2_OFFSET) +# define STM32_SPI3_SR (STM32_SPI3_BASE+STM32_SPI_SR_OFFSET) +# define STM32_SPI3_DR (STM32_SPI3_BASE+STM32_SPI_DR_OFFSET) +# define STM32_SPI3_CRCPR (STM32_SPI3_BASE+STM32_SPI_CRCPR_OFFSET) +# define STM32_SPI3_RXCRCR (STM32_SPI3_BASE+STM32_SPI_RXCRCR_OFFSET) +# define STM32_SPI3_TXCRCR (STM32_SPI3_BASE+STM32_SPI_TXCRCR_OFFSET) +# define STM32_SPI3_I2SCFGR (STM32_SPI3_BASE+STM32_SPI_I2SCFGR_OFFSET) +# define STM32_SPI3_I2SPR (STM32_SPI3_BASE+STM32_SPI_I2SPR_OFFSET) +#endif + +#if STM32F7_NSPI > 3 +# define STM32_SPI4_CR1 (STM32_SPI4_BASE+STM32_SPI_CR1_OFFSET) +# define STM32_SPI4_CR2 (STM32_SPI4_BASE+STM32_SPI_CR2_OFFSET) +# define STM32_SPI4_SR (STM32_SPI4_BASE+STM32_SPI_SR_OFFSET) +# define STM32_SPI4_DR (STM32_SPI4_BASE+STM32_SPI_DR_OFFSET) +# define STM32_SPI4_CRCPR (STM32_SPI4_BASE+STM32_SPI_CRCPR_OFFSET) +# define STM32_SPI4_RXCRCR (STM32_SPI4_BASE+STM32_SPI_RXCRCR_OFFSET) +# define STM32_SPI4_TXCRCR (STM32_SPI4_BASE+STM32_SPI_TXCRCR_OFFSET) +# define STM32_SPI4_I2SCFGR (STM32_SPI4_BASE+STM32_SPI_I2SCFGR_OFFSET) +# define STM32_SPI4_I2SPR (STM32_SPI4_BASE+STM32_SPI_I2SPR_OFFSET) +#endif + +#if STM32F7_NSPI > 4 +# define STM32_SPI5_CR1 (STM32_SPI5_BASE+STM32_SPI_CR1_OFFSET) +# define STM32_SPI5_CR2 (STM32_SPI5_BASE+STM32_SPI_CR2_OFFSET) +# define STM32_SPI5_SR (STM32_SPI5_BASE+STM32_SPI_SR_OFFSET) +# define STM32_SPI5_DR (STM32_SPI5_BASE+STM32_SPI_DR_OFFSET) +# define STM32_SPI5_CRCPR (STM32_SPI5_BASE+STM32_SPI_CRCPR_OFFSET) +# define STM32_SPI5_RXCRCR (STM32_SPI5_BASE+STM32_SPI_RXCRCR_OFFSET) +# define STM32_SPI5_TXCRCR (STM32_SPI5_BASE+STM32_SPI_TXCRCR_OFFSET) +# define STM32_SPI5_I2SCFGR (STM32_SPI5_BASE+STM32_SPI_I2SCFGR_OFFSET) +# define STM32_SPI5_I2SPR (STM32_SPI5_BASE+STM32_SPI_I2SPR_OFFSET) +#endif + +#if STM32F7_NSPI > 5 +# define STM32_SPI6_CR1 (STM32_SPI6_BASE+STM32_SPI_CR1_OFFSET) +# define STM32_SPI6_CR2 (STM32_SPI6_BASE+STM32_SPI_CR2_OFFSET) +# define STM32_SPI6_SR (STM32_SPI6_BASE+STM32_SPI_SR_OFFSET) +# define STM32_SPI6_DR (STM32_SPI6_BASE+STM32_SPI_DR_OFFSET) +# define STM32_SPI6_CRCPR (STM32_SPI6_BASE+STM32_SPI_CRCPR_OFFSET) +# define STM32_SPI6_RXCRCR (STM32_SPI6_BASE+STM32_SPI_RXCRCR_OFFSET) +# define STM32_SPI6_TXCRCR (STM32_SPI6_BASE+STM32_SPI_TXCRCR_OFFSET) +# define STM32_SPI6_I2SCFGR (STM32_SPI6_BASE+STM32_SPI_I2SCFGR_OFFSET) +# define STM32_SPI6_I2SPR (STM32_SPI6_BASE+STM32_SPI_I2SPR_OFFSET) +#endif + +/* Register Bitfield Definitions ****************************************************/ + +/* SPI Control Register 1 */ + +#define SPI_CR1_CPHA (1 << 0) /* Bit 0: Clock Phase */ +#define SPI_CR1_CPOL (1 << 1) /* Bit 1: Clock Polarity */ +#define SPI_CR1_MSTR (1 << 2) /* Bit 2: Master Selection */ +#define SPI_CR1_BR_SHIFT (3) /* Bits 5:3 Baud Rate Control */ +#define SPI_CR1_BR_MASK (7 << SPI_CR1_BR_SHIFT) +# define SPI_CR1_FPCLCKd2 (0 << SPI_CR1_BR_SHIFT) /* 000: fPCLK/2 */ +# define SPI_CR1_FPCLCKd4 (1 << SPI_CR1_BR_SHIFT) /* 001: fPCLK/4 */ +# define SPI_CR1_FPCLCKd8 (2 << SPI_CR1_BR_SHIFT) /* 010: fPCLK/8 */ +# define SPI_CR1_FPCLCKd16 (3 << SPI_CR1_BR_SHIFT) /* 011: fPCLK/16 */ +# define SPI_CR1_FPCLCKd32 (4 << SPI_CR1_BR_SHIFT) /* 100: fPCLK/32 */ +# define SPI_CR1_FPCLCKd64 (5 << SPI_CR1_BR_SHIFT) /* 101: fPCLK/64 */ +# define SPI_CR1_FPCLCKd128 (6 << SPI_CR1_BR_SHIFT) /* 110: fPCLK/128 */ +# define SPI_CR1_FPCLCKd256 (7 << SPI_CR1_BR_SHIFT) /* 111: fPCLK/256 */ +#define SPI_CR1_SPE (1 << 6) /* Bit 6: SPI Enable */ +#define SPI_CR1_LSBFIRST (1 << 7) /* Bit 7: Frame Format */ +#define SPI_CR1_SSI (1 << 8) /* Bit 8: Internal slave select */ +#define SPI_CR1_SSM (1 << 9) /* Bit 9: Software slave management */ +#define SPI_CR1_RXONLY (1 << 10) /* Bit 10: Receive only */ +#define SPI_CR1_CRCL (1 << 11) /* Bit 11: CRC length */ +#define SPI_CR1_CRCNEXT (1 << 12) /* Bit 12: Transmit CRC next */ +#define SPI_CR1_CRCEN (1 << 13) /* Bit 13: Hardware CRC calculation enable */ +#define SPI_CR1_BIDIOE (1 << 14) /* Bit 14: Output enable in bidirectional mode */ +#define SPI_CR1_BIDIMODE (1 << 15) /* Bit 15: Bidirectional data mode enable */ + +/* SPI Control Register 2 */ + +#define SPI_CR2_RXDMAEN (1 << 0) /* Bit 0: Rx Buffer DMA Enable */ +#define SPI_CR2_TXDMAEN (1 << 1) /* Bit 1: Tx Buffer DMA Enable */ +#define SPI_CR2_SSOE (1 << 2) /* Bit 2: SS Output Enable */ +#define SPI_CR2_NSSP (1 << 3) /* Bit 3 NSSP: NSS pulse management */ +#define SPI_CR2_FRF (1 << 4) /* Bit 4: Frame format */ +#define SPI_CR2_ERRIE (1 << 5) /* Bit 5: Error interrupt enable */ +#define SPI_CR2_RXNEIE (1 << 6) /* Bit 6: RX buffer not empty interrupt enable */ +#define SPI_CR2_TXEIE (1 << 7) /* Bit 7: Tx buffer empty interrupt enable */ +#define SPI_CR2_DS_SHIFT (8) /* Bits 8-11: Data size */ +#define SPI_CR2_DS_MASK (0xf << SPI_CR2_DS_SHIFT) +# define SPI_CR2_DS_VAL(bits) (((bits)-1) << SPI_CR2_DS_SHIFT) +# define SPI_CR2_DS_4BIT SPI_CR2_DS_VAL(4) +# define SPI_CR2_DS_5BIT SPI_CR2_DS_VAL(5) +# define SPI_CR2_DS_6BIT SPI_CR2_DS_VAL(6) +# define SPI_CR2_DS_7BIT SPI_CR2_DS_VAL(7) +# define SPI_CR2_DS_8BIT SPI_CR2_DS_VAL(8) +# define SPI_CR2_DS_9BIT SPI_CR2_DS_VAL(9) +# define SPI_CR2_DS_10BIT SPI_CR2_DS_VAL(10) +# define SPI_CR2_DS_11BIT SPI_CR2_DS_VAL(11) +# define SPI_CR2_DS_12BIT SPI_CR2_DS_VAL(12) +# define SPI_CR2_DS_13BIT SPI_CR2_DS_VAL(13) +# define SPI_CR2_DS_14BIT SPI_CR2_DS_VAL(14) +# define SPI_CR2_DS_15BIT SPI_CR2_DS_VAL(15) +# define SPI_CR2_DS_16BIT SPI_CR2_DS_VAL(16) +#define SPI_CR2_FRXTH (1 << 12) /* Bit 12: FIFO reception threshold */ +#define SPI_CR2_LDMARX (1 << 13) /* Bit 13: Last DMA transfer for receptione */ +#define SPI_CR2_LDMATX (1 << 14) /* Bit 14: Last DMA transfer for transmission */ + +/* SPI status register */ + +#define SPI_SR_RXNE (1 << 0) /* Bit 0: Receive buffer not empty */ +#define SPI_SR_TXE (1 << 1) /* Bit 1: Transmit buffer empty */ +#define SPI_SR_CHSIDE (1 << 2) /* Bit 2: Channel side (i2s) */ +#define SPI_SR_UDR (1 << 3) /* Bit 3: Underrun flag (i2s) */ +#define SPI_SR_CRCERR (1 << 4) /* Bit 4: CRC error flag */ +#define SPI_SR_MODF (1 << 5) /* Bit 5: Mode fault */ +#define SPI_SR_OVR (1 << 6) /* Bit 6: Overrun flag */ +#define SPI_SR_BSY (1 << 7) /* Bit 7: Busy flag */ +#define SPI_SR_FRE (1 << 8) /* Bit 8: Frame format error */ +#define SPI_SR_FRLVL_SHIFT (9) /* Bits 9-10: FIFO reception level */ +#define SPI_SR_FRLVL_MASK (0x3 << SPI_SR_FRLVL_SHIFT) +# define SPI_SR_FRLVL_EMPTY (0 << SPI_SR_FRLVL_SHIFT) /* FIFO empty */ +# define SPI_SR_FRLVL_QUARTER (1 << SPI_SR_FRLVL_SHIFT) /* 1/4 FIFO */ +# define SPI_SR_FRLVL_HALF (2 << SPI_SR_FRLVL_SHIFT) /* 1/2 FIFO */ +# define SPI_SR_FRLVL_FULL (3 << SPI_SR_FRLVL_SHIFT) /* FIFO full */ +#define SPI_SR_FTLVL_SHIFT (11) /* Bits 11-12: FIFO transmission level */ +#define SPI_SR_FTLVL_MASK (0x3 << SPI_SR_FTLVL_SHIFT) +# define SPI_SR_FTLVL_EMPTY (0 << SPI_SR_FTLVL_SHIFT) /* FIFO empty */ +# define SPI_SR_FTLVL_QUARTER (1 << SPI_SR_FTLVL_SHIFT) /* 1/4 FIFO */ +# define SPI_SR_FTLVL_HALF (2 << SPI_SR_FTLVL_SHIFT) /* 1/2 FIFO */ +# define SPI_SR_FTLVL_FULL (3 << SPI_SR_FTLVL_SHIFT) /* FIFO full */ + +/* I2S configuration register */ + +#define SPI_I2SCFGR_CHLEN (1 << 0) /* Bit 0: Channel length (number of bits per audio channel) */ +#define SPI_I2SCFGR_DATLEN_SHIFT (1) /* Bit 1-2: Data length to be transferred */ +#define SPI_I2SCFGR_DATLEN_MASK (3 << SPI_I2SCFGR_DATLEN_SHIFT) +# define SPI_I2SCFGR_DATLEN_16BIT (0 << SPI_I2SCFGR_DATLEN_SHIFT) /* 00: 16-bit data length */ +# define SPI_I2SCFGR_DATLEN_8BIT (1 << SPI_I2SCFGR_DATLEN_SHIFT) /* 01: 24-bit data length */ +# define SPI_I2SCFGR_DATLEN_32BIT (2 << SPI_I2SCFGR_DATLEN_SHIFT) /* 10: 32-bit data length */ +#define SPI_I2SCFGR_CKPOL (1 << 3) /* Bit 3: Steady state clock polarity */ +#define SPI_I2SCFGR_I2SSTD_SHIFT (4) /* Bit 4-5: I2S standard selection */ +#define SPI_I2SCFGR_I2SSTD_MASK (3 << SPI_I2SCFGR_I2SSTD_SHIFT) +# define SPI_I2SCFGR_I2SSTD_PHILLIPS (00 << SPI_I2SCFGR_I2SSTD_SHIFT) /* 00: I2S Phillips standard. */ +# define SPI_I2SCFGR_I2SSTD_MSB (1 << SPI_I2SCFGR_I2SSTD_SHIFT) /* 01: MSB justified standard (left justified) */ +# define SPI_I2SCFGR_I2SSTD_LSB (2 << SPI_I2SCFGR_I2SSTD_SHIFT) /* 10: LSB justified standard (right justified) */ +# define SPI_I2SCFGR_I2SSTD_PCM (3 << SPI_I2SCFGR_I2SSTD_SHIFT) /* 11: PCM standard */ +#define SPI_I2SCFGR_PCMSYNC (1 << 7) /* Bit 7: PCM frame synchronization */ +#define SPI_I2SCFGR_I2SCFG_SHIFT (8) /* Bit 8-9: I2S configuration mode */ +#define SPI_I2SCFGR_I2SCFG_MASK (3 << SPI_I2SCFGR_I2SCFG_SHIFT) +# define SPI_I2SCFGR_I2SCFG_STX (0 << SPI_I2SCFGR_I2SCFG_SHIFT) /* 00: Slave - transmit */ +# define SPI_I2SCFGR_I2SCFG_SRX (1 << SPI_I2SCFGR_I2SCFG_SHIFT) /* 01: Slave - receive */ +# define SPI_I2SCFGR_I2SCFG_MTX (2 << SPI_I2SCFGR_I2SCFG_SHIFT) /* 10: Master - transmit */ +# define SPI_I2SCFGR_I2SCFG_MRX (3 << SPI_I2SCFGR_I2SCFG_SHIFT) /* 11: Master - receive */ +#define SPI_I2SCFGR_I2SE (1 << 10) /* Bit 10: I2S Enable */ +#define SPI_I2SCFGR_I2SMOD (1 << 11) /* Bit 11: I2S mode selection */ +#define SPI_I2SCFGR_ASTRTEN (1 << 12) /* Bit 12: Asynchronous start enable */ + +/* I2S prescaler register */ + +#define SPI_I2SPR_I2SDIV_SHIFT (0) /* Bit 0-7: I2S Linear prescaler */ +#define SPI_I2SPR_I2SDIV_MASK (0xff << SPI_I2SPR_I2SDIV_SHIFT) +#define SPI_I2SPR_ODD (1 << 8) /* Bit 8: Odd factor for the prescaler */ +#define SPI_I2SPR_MCKOE (1 << 9) /* Bit 9: Master clock output enable */ + +#endif /* __ARCH_ARM_SRC_STM32F7_CHIP_STM32F74XX77XX_SPI_H */ From 69e67baedd27fe48ab5ce0ad1c3c3f6478b76279 Mon Sep 17 00:00:00 2001 From: David Sidrane Date: Wed, 15 Jun 2016 11:27:46 -1000 Subject: [PATCH 54/75] Added ADC, UID and DBGMCU defs to 76xx77xx Memory Map --- arch/arm/src/stm32f7/chip/stm32f76xx77xx_memorymap.h | 11 +++++++++-- 1 file changed, 9 insertions(+), 2 deletions(-) diff --git a/arch/arm/src/stm32f7/chip/stm32f76xx77xx_memorymap.h b/arch/arm/src/stm32f7/chip/stm32f76xx77xx_memorymap.h index 204311e000..fd1a41f36d 100644 --- a/arch/arm/src/stm32f7/chip/stm32f76xx77xx_memorymap.h +++ b/arch/arm/src/stm32f7/chip/stm32f76xx77xx_memorymap.h @@ -82,6 +82,7 @@ #define STM32_SYSMEM_AXIM 0x1ff00000 /* 0x1ff00000-0x1ff0edbf: System memory (AXIM) */ +#define STM32_SYSMEM_UID 0x1ff0f420 /* The 96-bit unique device identifier */ #define STM32_OTP_ICTM 0x0010f000 /* 0x0010f000-0x0010edbf: OTP (ITCM) */ #define STM32_OTP_AXIM 0x1ff0f000 /* 0x1ff00000-0x1ff0f41f: OTP (AXIM) */ @@ -145,6 +146,10 @@ #define STM32_USART6_BASE 0x40011400 /* 0x40011400-0x400117ff: USART6 */ #define STM32_SDMMC2_BASE 0x40011c00 /* 0x40011c00-0x40011fff: SDMMC2 */ #define STM32_ADC_BASE 0x40012000 /* 0x40012000-0x400123ff: ADC1 - ADC2 - ADC3 */ +# define STM32_ADC1_BASE 0x40012000 /* ADC1 */ +# define STM32_ADC2_BASE 0x40012100 /* ADC2 */ +# define STM32_ADC3_BASE 0x40012200 /* ADC3 */ +# define STM32_ADCCMN_BASE 0x40012300 /* Common */ #define STM32_SDMMC1_BASE 0x40012c00 /* 0x40012c00-0x40012fff: SDMMC1 */ #define STM32_SPI1_BASE 0x40013000 /* 0x40013000-0x400133ff: SPI1 */ #define STM32_SPI4_BASE 0x40013400 /* 0x40013400-0x400137ff: SPI4 */ @@ -210,5 +215,7 @@ * address range */ -#endif /* CONFIG_STM32F7_STM32F76XX || CONFIG_STM32F7_STM32F77XX */ -#endif /* __ARCH_ARM_SRC_STM32F7_CHIP_STM32F76XXX77XXX_MEMORYMAP_H */ +#define STM32_DEBUGMCU_BASE 0xe0042000 + +#endif /* CONFIG_STM32F7_STM32F74XX || CONFIG_STM32F7_STM32F75XX */ +#endif /* __ARCH_ARM_SRC_STM32F7_CHIP_STM32F74XXX75XXX_MEMORYMAP_H */ From 19e852b282b2f338d28216bc9102caee9c67b0bd Mon Sep 17 00:00:00 2001 From: David Sidrane Date: Wed, 15 Jun 2016 11:58:17 -1000 Subject: [PATCH 55/75] Clean up and Use two level include 74xx77xx I2C --- arch/arm/src/stm32f7/chip/stm32_i2c.h | 10 +- ...32f74xx75xx_i2c.h => stm32f74xx77xx_i2c.h} | 142 ++++++++++-------- arch/arm/src/stm32f7/stm32_i2c.c | 85 ++++++----- 3 files changed, 127 insertions(+), 110 deletions(-) rename arch/arm/src/stm32f7/chip/{stm32f74xx75xx_i2c.h => stm32f74xx77xx_i2c.h} (71%) diff --git a/arch/arm/src/stm32f7/chip/stm32_i2c.h b/arch/arm/src/stm32f7/chip/stm32_i2c.h index d8fd9f8ce6..f615eb6ec1 100644 --- a/arch/arm/src/stm32f7/chip/stm32_i2c.h +++ b/arch/arm/src/stm32f7/chip/stm32_i2c.h @@ -2,7 +2,8 @@ * arch/arm/src/stm32f7/chip/stm32_i2c.h * * Copyright (C) 2016 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Authors: Gregory Nutt + * David Sidrane * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions @@ -43,10 +44,11 @@ #include #include "chip.h" -#if defined(CONFIG_STM32F7_STM32F74XX) || defined(CONFIG_STM32F7_STM32F75XX) -# include "chip/stm32f74xx75xx_i2c.h" +#if defined(CONFIG_STM32F7_STM32F74XX) || defined(CONFIG_STM32F7_STM32F75XX) || \ + defined(CONFIG_STM32F7_STM32F76XX) || defined(CONFIG_STM32F7_STM32F77XX) +# include "chip/stm32f74xx77xx_i2c.h" #else -# error "Unsupported STM32 F7 part" +# error "Unsupported STM32 F7 sub family" #endif #endif /* __ARCH_ARM_SRC_STM32F7_CHIP_STM32_I2C_H */ diff --git a/arch/arm/src/stm32f7/chip/stm32f74xx75xx_i2c.h b/arch/arm/src/stm32f7/chip/stm32f74xx77xx_i2c.h similarity index 71% rename from arch/arm/src/stm32f7/chip/stm32f74xx75xx_i2c.h rename to arch/arm/src/stm32f7/chip/stm32f74xx77xx_i2c.h index 17c8012fdd..28ac30a27c 100644 --- a/arch/arm/src/stm32f7/chip/stm32f74xx75xx_i2c.h +++ b/arch/arm/src/stm32f7/chip/stm32f74xx77xx_i2c.h @@ -1,8 +1,9 @@ /************************************************************************************ - * arch/arm/src/stm32f7/chip/stm32f74xx75xx_i2c.h + * arch/arm/src/stm32f7/chip/stm32f74xx77xx_i2c.h * - * Copyright (C) 2009, 2011, 2013 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Copyright (C) 2016 Gregory Nutt. All rights reserved. + * Authors: Gregory Nutt + * David Sidrane * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions @@ -33,8 +34,8 @@ * ************************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32F7_STM32F74XX75XX_I2C_H -#define __ARCH_ARM_SRC_STM32F7_STM32F74XX75XX_I2C_H +#ifndef __ARCH_ARM_SRC_STM32F7_STM32F74XX77XX_I2C_H +#define __ARCH_ARM_SRC_STM32F7_STM32F74XX77XX_I2C_H /************************************************************************************ * Pre-processor Definitions @@ -42,60 +43,74 @@ /* Register Offsets *****************************************************************/ -#define STM32F7_I2C_CR1_OFFSET 0x0000 /* Control register 1 (32-bit) */ -#define STM32F7_I2C_CR2_OFFSET 0x0004 /* Control register 2 (32-bit) */ -#define STM32F7_I2C_OAR1_OFFSET 0x0008 /* Own address register 1 (16-bit) */ -#define STM32F7_I2C_OAR2_OFFSET 0x000c /* Own address register 2 (16-bit) */ -#define STM32F7_I2C_TIMINGR_OFFSET 0x0010 /* Timing register */ -#define STM32F7_I2C_TIMEOUTR_OFFSET 0x0014 /* Timeout register */ -#define STM32F7_I2C_ISR_OFFSET 0x0018 /* Interrupt and Status register */ -#define STM32F7_I2C_ICR_OFFSET 0x001c /* Interrupt clear register */ -#define STM32F7_I2C_PECR_OFFSET 0x0020 /* Packet error checking register */ -#define STM32F7_I2C_RXDR_OFFSET 0x0024 /* Receive data register */ -#define STM32F7_I2C_TXDR_OFFSET 0x0028 /* Transmit data register */ +#define STM32_I2C_CR1_OFFSET 0x0000 /* Control register 1 (32-bit) */ +#define STM32_I2C_CR2_OFFSET 0x0004 /* Control register 2 (32-bit) */ +#define STM32_I2C_OAR1_OFFSET 0x0008 /* Own address register 1 (16-bit) */ +#define STM32_I2C_OAR2_OFFSET 0x000c /* Own address register 2 (16-bit) */ +#define STM32_I2C_TIMINGR_OFFSET 0x0010 /* Timing register */ +#define STM32_I2C_TIMEOUTR_OFFSET 0x0014 /* Timeout register */ +#define STM32_I2C_ISR_OFFSET 0x0018 /* Interrupt and Status register */ +#define STM32_I2C_ICR_OFFSET 0x001c /* Interrupt clear register */ +#define STM32_I2C_PECR_OFFSET 0x0020 /* Packet error checking register */ +#define STM32_I2C_RXDR_OFFSET 0x0024 /* Receive data register */ +#define STM32_I2C_TXDR_OFFSET 0x0028 /* Transmit data register */ /* Register Addresses ***************************************************************/ #if STM32F7_NI2C > 0 -# define STM32F7_I2C1_CR1 (STM32F7_I2C1_BASE+STM32F7_I2C_CR1_OFFSET) -# define STM32F7_I2C1_CR2 (STM32F7_I2C1_BASE+STM32F7_I2C_CR2_OFFSET) -# define STM32F7_I2C1_OAR1 (STM32F7_I2C1_BASE+STM32F7_I2C_OAR1_OFFSET) -# define STM32F7_I2C1_OAR2 (STM32F7_I2C1_BASE+STM32F7_I2C_OAR2_OFFSET) -# define STM32F7_I2C1_TIMINGR (STM32F7_I2C1_BASE+STM32F7_I2C_TIMINGR_OFFSET) -# define STM32F7_I2C1_TIMEOUTR (STM32F7_I2C1_BASE+STM32F7_I2C_TIMEOUTR_OFFSET) -# define STM32F7_I2C1_ISR (STM32F7_I2C1_BASE+STM32F7_I2C_ISR_OFFSET) -# define STM32F7_I2C1_ICR (STM32F7_I2C1_BASE+STM32F7_I2C_ICR_OFFSET) -# define STM32F7_I2C1_PECR (STM32F7_I2C1_BASE+STM32F7_I2C_PECR_OFFSET) -# define STM32F7_I2C1_RXDR (STM32F7_I2C1_BASE+STM32F7_I2C_RXDR_OFFSET) -# define STM32F7_I2C1_TXDR (STM32F7_I2C1_BASE+STM32F7_I2C_TXDR_OFFSET) +# define STM32_I2C1_CR1 (STM32_I2C1_BASE+STM32_I2C_CR1_OFFSET) +# define STM32_I2C1_CR2 (STM32_I2C1_BASE+STM32_I2C_CR2_OFFSET) +# define STM32_I2C1_OAR1 (STM32_I2C1_BASE+STM32_I2C_OAR1_OFFSET) +# define STM32_I2C1_OAR2 (STM32_I2C1_BASE+STM32_I2C_OAR2_OFFSET) +# define STM32_I2C1_TIMINGR (STM32_I2C1_BASE+STM32_I2C_TIMINGR_OFFSET) +# define STM32_I2C1_TIMEOUTR (STM32_I2C1_BASE+STM32_I2C_TIMEOUTR_OFFSET) +# define STM32_I2C1_ISR (STM32_I2C1_BASE+STM32_I2C_ISR_OFFSET) +# define STM32_I2C1_ICR (STM32_I2C1_BASE+STM32_I2C_ICR_OFFSET) +# define STM32_I2C1_PECR (STM32_I2C1_BASE+STM32_I2C_PECR_OFFSET) +# define STM32_I2C1_RXDR (STM32_I2C1_BASE+STM32_I2C_RXDR_OFFSET) +# define STM32_I2C1_TXDR (STM32_I2C1_BASE+STM32_I2C_TXDR_OFFSET) #endif #if STM32F7_NI2C > 1 -# define STM32F7_I2C2_CR1 (STM32F7_I2C2_BASE+STM32F7_I2C_CR1_OFFSET) -# define STM32F7_I2C2_CR2 (STM32F7_I2C2_BASE+STM32F7_I2C_CR2_OFFSET) -# define STM32F7_I2C2_OAR1 (STM32F7_I2C2_BASE+STM32F7_I2C_OAR1_OFFSET) -# define STM32F7_I2C2_OAR2 (STM32F7_I2C2_BASE+STM32F7_I2C_OAR2_OFFSET) -# define STM32F7_I2C2_TIMINGR (STM32F7_I2C2_BASE+STM32F7_I2C_TIMINGR_OFFSET) -# define STM32F7_I2C2_TIMEOUTR (STM32F7_I2C2_BASE+STM32F7_I2C_TIMEOUTR_OFFSET) -# define STM32F7_I2C2_ISR (STM32F7_I2C2_BASE+STM32F7_I2C_ISR_OFFSET) -# define STM32F7_I2C2_ICR (STM32F7_I2C2_BASE+STM32F7_I2C_ICR_OFFSET) -# define STM32F7_I2C2_PECR (STM32F7_I2C2_BASE+STM32F7_I2C_PECR_OFFSET) -# define STM32F7_I2C2_RXDR (STM32F7_I2C2_BASE+STM32F7_I2C_RXDR_OFFSET) -# define STM32F7_I2C2_TXDR (STM32F7_I2C2_BASE+STM32F7_I2C_TXDR_OFFSET) +# define STM32_I2C2_CR1 (STM32_I2C2_BASE+STM32_I2C_CR1_OFFSET) +# define STM32_I2C2_CR2 (STM32_I2C2_BASE+STM32_I2C_CR2_OFFSET) +# define STM32_I2C2_OAR1 (STM32_I2C2_BASE+STM32_I2C_OAR1_OFFSET) +# define STM32_I2C2_OAR2 (STM32_I2C2_BASE+STM32_I2C_OAR2_OFFSET) +# define STM32_I2C2_TIMINGR (STM32_I2C2_BASE+STM32_I2C_TIMINGR_OFFSET) +# define STM32_I2C2_TIMEOUTR (STM32_I2C2_BASE+STM32_I2C_TIMEOUTR_OFFSET) +# define STM32_I2C2_ISR (STM32_I2C2_BASE+STM32_I2C_ISR_OFFSET) +# define STM32_I2C2_ICR (STM32_I2C2_BASE+STM32_I2C_ICR_OFFSET) +# define STM32_I2C2_PECR (STM32_I2C2_BASE+STM32_I2C_PECR_OFFSET) +# define STM32_I2C2_RXDR (STM32_I2C2_BASE+STM32_I2C_RXDR_OFFSET) +# define STM32_I2C2_TXDR (STM32_I2C2_BASE+STM32_I2C_TXDR_OFFSET) #endif #if STM32F7_NI2C > 2 -# define STM32F7_I2C3_CR1 (STM32F7_I2C3_BASE+STM32F7_I2C_CR1_OFFSET) -# define STM32F7_I2C3_CR2 (STM32F7_I2C3_BASE+STM32F7_I2C_CR2_OFFSET) -# define STM32F7_I2C3_OAR1 (STM32F7_I2C3_BASE+STM32F7_I2C_OAR1_OFFSET) -# define STM32F7_I2C3_OAR2 (STM32F7_I2C3_BASE+STM32F7_I2C_OAR2_OFFSET) -# define STM32F7_I2C3_TIMINGR (STM32F7_I2C3_BASE+STM32F7_I2C_TIMINGR_OFFSET) -# define STM32F7_I2C3_TIMEOUTR (STM32F7_I2C3_BASE+STM32F7_I2C_TIMEOUTR_OFFSET) -# define STM32F7_I2C3_ISR (STM32F7_I2C3_BASE+STM32F7_I2C_ISR_OFFSET) -# define STM32F7_I2C3_ICR (STM32F7_I2C3_BASE+STM32F7_I2C_ICR_OFFSET) -# define STM32F7_I2C3_PECR (STM32F7_I2C3_BASE+STM32F7_I2C_PECR_OFFSET) -# define STM32F7_I2C3_RXDR (STM32F7_I2C3_BASE+STM32F7_I2C_RXDR_OFFSET) -# define STM32F7_I2C3_TXDR (STM32F7_I2C3_BASE+STM32F7_I2C_TXDR_OFFSET) +# define STM32_I2C3_CR1 (STM32_I2C3_BASE+STM32_I2C_CR1_OFFSET) +# define STM32_I2C3_CR2 (STM32_I2C3_BASE+STM32_I2C_CR2_OFFSET) +# define STM32_I2C3_OAR1 (STM32_I2C3_BASE+STM32_I2C_OAR1_OFFSET) +# define STM32_I2C3_OAR2 (STM32_I2C3_BASE+STM32_I2C_OAR2_OFFSET) +# define STM32_I2C3_TIMINGR (STM32_I2C3_BASE+STM32_I2C_TIMINGR_OFFSET) +# define STM32_I2C3_TIMEOUTR (STM32_I2C3_BASE+STM32_I2C_TIMEOUTR_OFFSET) +# define STM32_I2C3_ISR (STM32_I2C3_BASE+STM32_I2C_ISR_OFFSET) +# define STM32_I2C3_ICR (STM32_I2C3_BASE+STM32_I2C_ICR_OFFSET) +# define STM32_I2C3_PECR (STM32_I2C3_BASE+STM32_I2C_PECR_OFFSET) +# define STM32_I2C3_RXDR (STM32_I2C3_BASE+STM32_I2C_RXDR_OFFSET) +# define STM32_I2C3_TXDR (STM32_I2C3_BASE+STM32_I2C_TXDR_OFFSET) +#endif + +#if STM32F7_NI2C > 3 +# define STM32_I2C4_CR1 (STM32_I2C4_BASE+STM32_I2C_CR1_OFFSET) +# define STM32_I2C4_CR2 (STM32_I2C4_BASE+STM32_I2C_CR2_OFFSET) +# define STM32_I2C4_OAR1 (STM32_I2C4_BASE+STM32_I2C_OAR1_OFFSET) +# define STM32_I2C4_OAR2 (STM32_I2C4_BASE+STM32_I2C_OAR2_OFFSET) +# define STM32_I2C4_TIMINGR (STM32_I2C4_BASE+STM32_I2C_TIMINGR_OFFSET) +# define STM32_I2C4_TIMEOUTR (STM32_I2C4_BASE+STM32_I2C_TIMEOUTR_OFFSET) +# define STM32_I2C4_ISR (STM32_I2C4_BASE+STM32_I2C_ISR_OFFSET) +# define STM32_I2C4_ICR (STM32_I2C4_BASE+STM32_I2C_ICR_OFFSET) +# define STM32_I2C4_PECR (STM32_I2C4_BASE+STM32_I2C_PECR_OFFSET) +# define STM32_I2C4_RXDR (STM32_I2C4_BASE+STM32_I2C_RXDR_OFFSET) +# define STM32_I2C4_TXDR (STM32_I2C4_BASE+STM32_I2C_TXDR_OFFSET) #endif /* Register Bitfield Definitions ****************************************************/ @@ -111,7 +126,7 @@ #define I2C_CR1_TCIE (1 << 6) /* Bit 6: Transfer Complete interrupt enable */ #define I2C_CR1_ERRIE (1 << 7) /* Bit 7: Error interrupts enable */ #define I2C_CR1_DNF_SHIFT (8) /* Bits 8-11: Digital noise filter */ -#define I2C_CR1_DNF_MASK (15 << I2C_CR1_DNF_SHIFT) +#define I2C_CR1_DNF_MASK (0xf << I2C_CR1_DNF_SHIFT) # define I2C_CR1_DNF_DISABLE (0 << I2C_CR1_DNF_SHIFT) # define I2C_CR1_DNF(n) ((n) << I2C_CR1_DNF_SHIFT) /* Up to n * Ti2cclk, n=1..15 */ #define I2C_CR1_ANFOFF (1 << 12) /* Bit 12: Analog noise filter OFF */ @@ -203,18 +218,6 @@ # define I2C_TIMEOUTR_B(n) ((n) << I2C_TIMEOUTR_B_SHIFT) #define I2C_TIMEOUTR_TEXTEN (1 << 31) /* Bits 31: Extended clock timeout enable */ -/* Interrupt and Status register and interrupt clear register */ -/* Common interrupt bits */ - -#define I2C_INT_ADDR (1 << 3) /* Bit 3: Address matched (slave) */ -#define I2C_INT_NACK (1 << 4) /* Bit 4: Not Acknowledge received flag */ -#define I2C_INT_STOP (1 << 5) /* Bit 5: Stop detection flag */ -#define I2C_INT_BERR (1 << 8) /* Bit 8: Bus error */ -#define I2C_INT_ARLO (1 << 9) /* Bit 9: Arbitration lost */ -#define I2C_INT_OVR (1 << 10) /* Bit 10: Overrun/Underrun (slave) */ -#define I2C_INT_PECERR (1 << 11) /* Bit 11: PEC Error in reception */ -#define I2C_INT_TIMEOUT (1 << 12) /* Bit 12: Timeout or tLOW detection flag */ -#define I2C_INT_ALERT (1 << 13) /* Bit 13: SMBus alert */ /* Fields unique to the Interrupt and Status register */ @@ -228,6 +231,19 @@ #define I2C_ISR_ADDCODE_SHIFT (17) /* Bits 17-23: Address match code (slave) */ #define I2C_ISR_ADDCODE_MASK (0x7f << I2C_ISR_ADDCODE_SHIFT) +/* Interrupt and Status register and interrupt clear register */ +/* Common interrupt bits */ + +#define I2C_INT_ADDR (1 << 3) /* Bit 3: Address matched (slave) */ +#define I2C_INT_NACK (1 << 4) /* Bit 4: Not Acknowledge received flag */ +#define I2C_INT_STOP (1 << 5) /* Bit 5: Stop detection flag */ +#define I2C_INT_BERR (1 << 8) /* Bit 8: Bus error */ +#define I2C_INT_ARLO (1 << 9) /* Bit 9: Arbitration lost */ +#define I2C_INT_OVR (1 << 10) /* Bit 10: Overrun/Underrun (slave) */ +#define I2C_INT_PECERR (1 << 11) /* Bit 11: PEC Error in reception */ +#define I2C_INT_TIMEOUT (1 << 12) /* Bit 12: Timeout or tLOW detection flag */ +#define I2C_INT_ALERT (1 << 13) /* Bit 13: SMBus alert */ + #define I2C_ISR_ERRORMASK (I2C_INT_BERR | I2C_INT_ARLO | I2C_INT_OVR | I2C_INT_PECERR | I2C_INT_TIMEOUT) #define I2C_ICR_CLEARMASK (I2C_INT_ADDR | I2C_INT_NACK | I2C_INT_STOP | I2C_INT_BERR | I2C_INT_ARLO \ @@ -245,5 +261,5 @@ #define I2C_TXDR_MASK (0xff) -#endif /* __ARCH_ARM_SRC_STM32F7_CHIP_STM32F74XX75XX_I2C_H */ +#endif /* __ARCH_ARM_SRC_STM32F7_CHIP_STM32F74XX77XX_I2C_H */ diff --git a/arch/arm/src/stm32f7/stm32_i2c.c b/arch/arm/src/stm32f7/stm32_i2c.c index 6aa9d2fde6..b643dd9de4 100644 --- a/arch/arm/src/stm32f7/stm32_i2c.c +++ b/arch/arm/src/stm32f7/stm32_i2c.c @@ -1,18 +1,16 @@ /************************************************************************************ - * arch/arm/src/stm32/stm32f3xx_i2c.c - * STM32 F3 I2C Hardware Layer - Device Driver + * arch/arm/src/stm32/stm32f7_i2c.c + * STM32 I2C Hardware Layer - Device Driver * * Copyright (C) 2011 Uros Platise. All rights reserved. * Author: Uros Platise * * With extensions and modifications for the F1, F2, and F4 by: * - * Copyright (C) 2011-2013 Gregory Nutt. All rights reserved. - * Author: Gregroy Nutt - * - * And this version for the STM32 F3 by - * - * Author: John Wharington + * Copyright (C) 2016 Gregory Nutt. All rights reserved. + * Authors: Gregroy Nutt + * John Wharington + * David Sidrane * * Major rewrite of ISR and supporting methods, including support * for NACK and RELOAD by: @@ -51,11 +49,9 @@ /* ------------------------------------------------------------------------------ * - * STM32 F3 I2C Driver + * STM32 F7 I2C Driver * * Supports: - * - STM32 F30xxx - * - Internal Oscillator (HSI) running at 8 Mhz * - Master operation at up to 400Khz (Fast Mode) * - Multiple instances (shared bus) * - Interrupt based operation @@ -712,7 +708,7 @@ static useconds_t stm32_i2c_tousecs(int msgc, FAR struct i2c_msg_s *msgs) #ifndef CONFIG_I2C_POLLED static inline void stm32_i2c_enableinterrupts(struct stm32_i2c_priv_s *priv) { - stm32_i2c_modifyreg32(priv, STM32F7_I2C_CR1_OFFSET, 0, (I2C_CR1_TXRX | I2C_CR1_NACKIE)); + stm32_i2c_modifyreg32(priv, STM32_I2C_CR1_OFFSET, 0, (I2C_CR1_TXRX | I2C_CR1_NACKIE)); } #endif @@ -742,7 +738,7 @@ static inline int stm32_i2c_sem_waitdone(FAR struct stm32_i2c_priv_s *priv) * The remainder of the interrupts, including error-related, are enabled here. */ - stm32_i2c_modifyreg32(priv, STM32F7_I2C_CR1_OFFSET, 0, + stm32_i2c_modifyreg32(priv, STM32_I2C_CR1_OFFSET, 0, (I2C_CR1_ALLINTS & ~I2C_CR1_TXRX)); /* Signal the interrupt handler that we are waiting */ @@ -802,7 +798,7 @@ static inline int stm32_i2c_sem_waitdone(FAR struct stm32_i2c_priv_s *priv) /* Disable I2C interrupts */ - stm32_i2c_modifyreg32(priv, STM32F7_I2C_CR1_OFFSET, I2C_CR1_ALLINTS, 0); + stm32_i2c_modifyreg32(priv, STM32_I2C_CR1_OFFSET, I2C_CR1_ALLINTS, 0); leave_critical_section(flags); return ret; @@ -869,7 +865,7 @@ static inline int stm32_i2c_sem_waitdone(FAR struct stm32_i2c_priv_s *priv) static inline void stm32_i2c_set_7bit_address(FAR struct stm32_i2c_priv_s *priv) { - stm32_i2c_modifyreg32(priv, STM32F7_I2C_CR2_OFFSET, I2C_CR2_SADD7_MASK, + stm32_i2c_modifyreg32(priv, STM32_I2C_CR2_OFFSET, I2C_CR2_SADD7_MASK, ((priv->msgv->addr & 0x7F) << I2C_CR2_SADD7_SHIFT)); } @@ -884,7 +880,7 @@ static inline void stm32_i2c_set_bytes_to_transfer(FAR struct stm32_i2c_priv_s *priv, uint8_t n_bytes) { - stm32_i2c_modifyreg32(priv, STM32F7_I2C_CR2_OFFSET, I2C_CR2_NBYTES_MASK, + stm32_i2c_modifyreg32(priv, STM32_I2C_CR2_OFFSET, I2C_CR2_NBYTES_MASK, (n_bytes << I2C_CR2_NBYTES_SHIFT)); } @@ -898,7 +894,7 @@ stm32_i2c_set_bytes_to_transfer(FAR struct stm32_i2c_priv_s *priv, static inline void stm32_i2c_set_write_transfer_dir(FAR struct stm32_i2c_priv_s *priv) { - stm32_i2c_modifyreg32(priv, STM32F7_I2C_CR2_OFFSET, I2C_CR2_RD_WRN, 0); + stm32_i2c_modifyreg32(priv, STM32_I2C_CR2_OFFSET, I2C_CR2_RD_WRN, 0); } /************************************************************************************ @@ -911,7 +907,7 @@ stm32_i2c_set_write_transfer_dir(FAR struct stm32_i2c_priv_s *priv) static inline void stm32_i2c_set_read_transfer_dir(FAR struct stm32_i2c_priv_s *priv) { - stm32_i2c_modifyreg32(priv, STM32F7_I2C_CR2_OFFSET, 0, I2C_CR2_RD_WRN); + stm32_i2c_modifyreg32(priv, STM32_I2C_CR2_OFFSET, 0, I2C_CR2_RD_WRN); } /************************************************************************************ @@ -924,7 +920,7 @@ stm32_i2c_set_read_transfer_dir(FAR struct stm32_i2c_priv_s *priv) static inline void stm32_i2c_enable_reload(FAR struct stm32_i2c_priv_s *priv) { - stm32_i2c_modifyreg32(priv, STM32F7_I2C_CR2_OFFSET, 0, I2C_CR2_RELOAD); + stm32_i2c_modifyreg32(priv, STM32_I2C_CR2_OFFSET, 0, I2C_CR2_RELOAD); } /************************************************************************************ @@ -937,7 +933,7 @@ stm32_i2c_enable_reload(FAR struct stm32_i2c_priv_s *priv) static inline void stm32_i2c_disable_reload(FAR struct stm32_i2c_priv_s *priv) { - stm32_i2c_modifyreg32(priv, STM32F7_I2C_CR2_OFFSET, I2C_CR2_RELOAD, 0); + stm32_i2c_modifyreg32(priv, STM32_I2C_CR2_OFFSET, I2C_CR2_RELOAD, 0); } @@ -972,7 +968,7 @@ static inline void stm32_i2c_sem_waitstop(FAR struct stm32_i2c_priv_s *priv) { /* Check for STOP condition */ - cr = stm32_i2c_getreg32(priv, STM32F7_I2C_CR2_OFFSET); + cr = stm32_i2c_getreg32(priv, STM32_I2C_CR2_OFFSET); if ((cr & I2C_CR2_STOP) == 0) { return; @@ -980,7 +976,7 @@ static inline void stm32_i2c_sem_waitstop(FAR struct stm32_i2c_priv_s *priv) /* Check for timeout error */ - sr = stm32_i2c_getreg(priv, STM32F7_I2C_ISR_OFFSET); + sr = stm32_i2c_getreg(priv, STM32_I2C_ISR_OFFSET); if ((sr & I2C_INT_TIMEOUT) != 0) { return; @@ -1235,10 +1231,10 @@ static void stm32_i2c_setclock(FAR struct stm32_i2c_priv_s *priv, uint32_t frequ { /* I2C peripheral must be disabled to update clocking configuration */ - pe = (stm32_i2c_getreg32(priv, STM32F7_I2C_CR1_OFFSET) & I2C_CR1_PE); + pe = (stm32_i2c_getreg32(priv, STM32_I2C_CR1_OFFSET) & I2C_CR1_PE); if (pe) { - stm32_i2c_modifyreg32(priv, STM32F7_I2C_CR1_OFFSET, I2C_CR1_PE, 0); + stm32_i2c_modifyreg32(priv, STM32_I2C_CR1_OFFSET, I2C_CR1_PE, 0); } /* TODO: speed/timing calcs, at the moment 45Mhz = STM32_PCLK1_FREQUENCY, analog filter is on, @@ -1277,11 +1273,11 @@ static void stm32_i2c_setclock(FAR struct stm32_i2c_priv_s *priv, uint32_t frequ (scl_h_period << I2C_TIMINGR_SCLH_SHIFT) | (scl_l_period << I2C_TIMINGR_SCLL_SHIFT); - stm32_i2c_putreg32(priv, STM32F7_I2C_TIMINGR_OFFSET, timingr); + stm32_i2c_putreg32(priv, STM32_I2C_TIMINGR_OFFSET, timingr); if (pe) { - stm32_i2c_modifyreg32(priv, STM32F7_I2C_CR1_OFFSET, 0, I2C_CR1_PE); + stm32_i2c_modifyreg32(priv, STM32_I2C_CR1_OFFSET, 0, I2C_CR1_PE); } priv->frequency = frequency; @@ -1410,7 +1406,7 @@ static inline void stm32_i2c_sendstart(FAR struct stm32_i2c_priv_s *priv) i2cinfo("Sending START: dcnt=%i msgc=%i flags=0x%04x\n", priv->dcnt, priv->msgc, priv->flags); - stm32_i2c_modifyreg32(priv, STM32F7_I2C_CR2_OFFSET, 0, I2C_CR2_START); + stm32_i2c_modifyreg32(priv, STM32_I2C_CR2_OFFSET, 0, I2C_CR2_START); } /************************************************************************************ @@ -1430,7 +1426,7 @@ static inline void stm32_i2c_sendstop(FAR struct stm32_i2c_priv_s *priv) i2cinfo("Sending STOP\n"); stm32_i2c_traceevent(priv, I2CEVENT_WRITE_STOP, 0); - stm32_i2c_modifyreg32(priv, STM32F7_I2C_CR2_OFFSET, 0, I2C_CR2_STOP); + stm32_i2c_modifyreg32(priv, STM32_I2C_CR2_OFFSET, 0, I2C_CR2_STOP); } /************************************************************************************ @@ -1443,7 +1439,7 @@ static inline void stm32_i2c_sendstop(FAR struct stm32_i2c_priv_s *priv) static inline uint32_t stm32_i2c_getstatus(FAR struct stm32_i2c_priv_s *priv) { - return getreg32(priv->config->base + STM32F7_I2C_ISR_OFFSET); + return getreg32(priv->config->base + STM32_I2C_ISR_OFFSET); } /************************************************************************************ @@ -1456,7 +1452,7 @@ static inline uint32_t stm32_i2c_getstatus(FAR struct stm32_i2c_priv_s *priv) static inline void stm32_i2c_clearinterrupts(struct stm32_i2c_priv_s *priv) { - stm32_i2c_modifyreg32(priv, STM32F7_I2C_ICR_OFFSET, 0, I2C_ICR_CLEARMASK); + stm32_i2c_modifyreg32(priv, STM32_I2C_ICR_OFFSET, 0, I2C_ICR_CLEARMASK); } /************************************************************************************ @@ -1483,7 +1479,7 @@ static int stm32_i2c_isr(struct stm32_i2c_priv_s *priv) /* Get state of the I2C controller */ - status = stm32_i2c_getreg32(priv, STM32F7_I2C_ISR_OFFSET); + status = stm32_i2c_getreg32(priv, STM32_I2C_ISR_OFFSET); i2cinfo("ENTER: status = 0x%08x\n", status); @@ -1645,7 +1641,7 @@ static int stm32_i2c_isr(struct stm32_i2c_priv_s *priv) /* Transmit current byte */ - stm32_i2c_putreg(priv, STM32F7_I2C_TXDR_OFFSET, *priv->ptr); + stm32_i2c_putreg(priv, STM32_I2C_TXDR_OFFSET, *priv->ptr); /* Advance to next byte */ @@ -1719,7 +1715,7 @@ static int stm32_i2c_isr(struct stm32_i2c_priv_s *priv) #endif /* Receive a byte */ - *priv->ptr = stm32_i2c_getreg(priv, STM32F7_I2C_RXDR_OFFSET); + *priv->ptr = stm32_i2c_getreg(priv, STM32_I2C_RXDR_OFFSET); i2cinfo("RXNE: Read Data 0x%02x\n", *priv->ptr); @@ -1742,7 +1738,7 @@ static int stm32_i2c_isr(struct stm32_i2c_priv_s *priv) stm32_i2c_traceevent(priv, I2CEVENT_READ_ERROR, 0); status = stm32_i2c_getreg(priv, STM32F7_I2C_ISR_OFFSET); i2cerr("ERROR: RXNE Unsupported state detected, dcnt=%i, status 0x%08x\n", - priv->dcnt, status); + priv->dcnt, status); /* Set signals that will terminate ISR and wake waiting thread */ @@ -1997,7 +1993,7 @@ static int stm32_i2c_isr(struct stm32_i2c_priv_s *priv) #else /* Read rest of the state */ - status = stm32_i2c_getreg(priv, STM32F7_I2C_ISR_OFFSET); + status = stm32_i2c_getreg(priv, STM32_I2C_ISR_OFFSET); i2cerr("ERROR: Invalid state detected, status 0x%08x\n", status); @@ -2033,7 +2029,7 @@ static int stm32_i2c_isr(struct stm32_i2c_priv_s *priv) priv->intstate = INTSTATE_DONE; #else - status = stm32_i2c_getreg32(priv, STM32F7_I2C_ISR_OFFSET); + status = stm32_i2c_getreg32(priv, STM32_I2C_ISR_OFFSET); /* Update private state to capture NACK which is used in combination * with the astart flag to report the type of NACK received (address @@ -2046,7 +2042,7 @@ static int stm32_i2c_isr(struct stm32_i2c_priv_s *priv) /* Clear all interrupts */ - stm32_i2c_modifyreg32(priv, STM32F7_I2C_ICR_OFFSET, 0, I2C_ICR_CLEARMASK); + stm32_i2c_modifyreg32(priv, STM32_I2C_ICR_OFFSET, 0, I2C_ICR_CLEARMASK); /* If a thread is waiting then inform it transfer is complete */ @@ -2058,7 +2054,7 @@ static int stm32_i2c_isr(struct stm32_i2c_priv_s *priv) #endif } - status = stm32_i2c_getreg32(priv, STM32F7_I2C_ISR_OFFSET); + status = stm32_i2c_getreg32(priv, STM32_I2C_ISR_OFFSET); i2cinfo("EXIT: status = 0x%08x\n", status); return OK; @@ -2164,7 +2160,7 @@ static int stm32_i2c_init(FAR struct stm32_i2c_priv_s *priv) /* Enable I2C peripheral */ - stm32_i2c_modifyreg32(priv, STM32F7_I2C_CR1_OFFSET, 0, I2C_CR1_PE); + stm32_i2c_modifyreg32(priv, STM32_I2C_CR1_OFFSET, 0, I2C_CR1_PE); return OK; } @@ -2181,7 +2177,7 @@ static int stm32_i2c_deinit(FAR struct stm32_i2c_priv_s *priv) { /* Disable I2C */ - stm32_i2c_putreg32(priv, STM32F7_I2C_CR1_OFFSET, 0); + stm32_i2c_putreg32(priv, STM32_I2C_CR1_OFFSET, 0); /* Unconfigure GPIO pins */ @@ -2279,9 +2275,12 @@ static int stm32_i2c_process(FAR struct i2c_master_s *dev, FAR struct i2c_msg_s waitrc = stm32_i2c_sem_waitdone(priv); - cr1 = stm32_i2c_getreg32(priv, STM32F7_I2C_CR1_OFFSET); - cr2 = stm32_i2c_getreg32(priv, STM32F7_I2C_CR2_OFFSET); - + cr1 = stm32_i2c_getreg32(priv, STM32_I2C_CR1_OFFSET); + cr2 = stm32_i2c_getreg32(priv, STM32_I2C_CR2_OFFSET); +#if !defined(CONFIG_DEBUG_I2C) + UNUSED(cr1); + UNUSED(cr2); +#endif /* Status after a normal / good exit is usually 0x00000001, meaning the TXE * bit is set. That occurs as a result of the I2C_TXDR register being * empty, and it naturally will be after the last byte is transmitted. From e599b1b8a725be20cf0d80f527e0dad062f32c00 Mon Sep 17 00:00:00 2001 From: David Sidrane Date: Wed, 15 Jun 2016 11:59:14 -1000 Subject: [PATCH 56/75] Missing copyright --- arch/arm/src/stm32f7/chip/stm32_uart.h | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm/src/stm32f7/chip/stm32_uart.h b/arch/arm/src/stm32f7/chip/stm32_uart.h index 89177c8987..7669c675cc 100644 --- a/arch/arm/src/stm32f7/chip/stm32_uart.h +++ b/arch/arm/src/stm32f7/chip/stm32_uart.h @@ -1,6 +1,7 @@ /************************************************************************************ * arch/arm/src/stm32f7/chip/stm32_uart.h * + * Copyright (C) 2016 Gregory Nutt. All rights reserved. * Authors: Gregory Nutt * David Sidrane * From 15c260a4288a04f303fefd352f210ef51ed6daaa Mon Sep 17 00:00:00 2001 From: Gregory Nutt Date: Fri, 17 Jun 2016 16:44:50 -0600 Subject: [PATCH 57/75] armv7-a/armv6-m/arm/a1x: Convert *err() to either *info() or add ERROR:, depending on if an error is reported --- arch/arm/src/a1x/a1x_serial.c | 2 +- arch/arm/src/arm/up_dataabort.c | 2 +- arch/arm/src/arm/up_elf.c | 14 ++++---- arch/arm/src/arm/up_prefetchabort.c | 4 +-- arch/arm/src/arm/up_releasepending.c | 2 +- arch/arm/src/arm/up_reprioritizertr.c | 2 +- arch/arm/src/arm/up_schedulesigaction.c | 4 +-- arch/arm/src/arm/up_sigdeliver.c | 4 +-- arch/arm/src/armv6-m/up_elf.c | 16 ++++----- arch/arm/src/armv6-m/up_hardfault.c | 34 ++++++++++---------- arch/arm/src/armv6-m/up_releasepending.c | 2 +- arch/arm/src/armv6-m/up_reprioritizertr.c | 2 +- arch/arm/src/armv6-m/up_schedulesigaction.c | 4 +-- arch/arm/src/armv6-m/up_sigdeliver.c | 4 +-- arch/arm/src/armv7-a/arm_cpustart.c | 10 +++--- arch/arm/src/armv7-a/arm_dataabort.c | 2 +- arch/arm/src/armv7-a/arm_elf.c | 14 ++++---- arch/arm/src/armv7-a/arm_l2cc_pl310.c | 2 +- arch/arm/src/armv7-a/arm_prefetchabort.c | 4 +-- arch/arm/src/armv7-a/arm_releasepending.c | 2 +- arch/arm/src/armv7-a/arm_reprioritizertr.c | 2 +- arch/arm/src/armv7-a/arm_schedulesigaction.c | 4 +-- arch/arm/src/armv7-a/arm_sigdeliver.c | 4 +-- 23 files changed, 70 insertions(+), 70 deletions(-) diff --git a/arch/arm/src/a1x/a1x_serial.c b/arch/arm/src/a1x/a1x_serial.c index 8c28eabb37..a87c3d4ed3 100644 --- a/arch/arm/src/a1x/a1x_serial.c +++ b/arch/arm/src/a1x/a1x_serial.c @@ -1192,7 +1192,7 @@ static int uart_interrupt(struct uart_dev_s *dev) default: { - _llerr("Unexpected IIR: %02x\n", status); + _llerr("ERROR: Unexpected IIR: %02x\n", status); break; } } diff --git a/arch/arm/src/arm/up_dataabort.c b/arch/arm/src/arm/up_dataabort.c index 926352fac4..8cba1aa406 100644 --- a/arch/arm/src/arm/up_dataabort.c +++ b/arch/arm/src/arm/up_dataabort.c @@ -107,7 +107,7 @@ void up_dataabort(uint32_t *regs, uint32_t far, uint32_t fsr) * fatal error. */ - pgllerr("FSR: %08x FAR: %08x\n", fsr, far); + pgllinfo("FSR: %08x FAR: %08x\n", fsr, far); if ((fsr & FSR_MASK) != FSR_PAGE) { goto segfault; diff --git a/arch/arm/src/arm/up_elf.c b/arch/arm/src/arm/up_elf.c index 06c0c5157c..c6d88bdc32 100644 --- a/arch/arm/src/arm/up_elf.c +++ b/arch/arm/src/arm/up_elf.c @@ -86,7 +86,7 @@ bool up_checkarch(FAR const Elf32_Ehdr *ehdr) if (ehdr->e_machine != EM_ARM) { - berr("Not for ARM: e_machine=%04x\n", ehdr->e_machine); + berr("ERROR: Not for ARM: e_machine=%04x\n", ehdr->e_machine); return -ENOEXEC; } @@ -94,7 +94,7 @@ bool up_checkarch(FAR const Elf32_Ehdr *ehdr) if (ehdr->e_ident[EI_CLASS] != ELFCLASS32) { - berr("Need 32-bit objects: e_ident[EI_CLASS]=%02x\n", ehdr->e_ident[EI_CLASS]); + berr("ERROR: Need 32-bit objects: e_ident[EI_CLASS]=%02x\n", ehdr->e_ident[EI_CLASS]); return -ENOEXEC; } @@ -106,7 +106,7 @@ bool up_checkarch(FAR const Elf32_Ehdr *ehdr) if (ehdr->e_ident[EI_DATA] != ELFDATA2LSB) #endif { - berr("Wrong endian-ness: e_ident[EI_DATA]=%02x\n", ehdr->e_ident[EI_DATA]); + berr("ERROR: Wrong endian-ness: e_ident[EI_DATA]=%02x\n", ehdr->e_ident[EI_DATA]); return -ENOEXEC; } @@ -114,7 +114,7 @@ bool up_checkarch(FAR const Elf32_Ehdr *ehdr) if ((ehdr->e_entry & 3) != 0) { - berr("Entry point is not properly aligned: %08x\n", ehdr->e_entry); + berr("ERROR: Entry point is not properly aligned: %08x\n", ehdr->e_entry); return -ENOEXEC } @@ -185,7 +185,7 @@ int up_relocate(FAR const Elf32_Rel *rel, FAR const Elf32_Sym *sym, offset += sym->st_value - addr; if (offset & 3 || offset <= (int32_t) 0xfe000000 || offset >= (int32_t) 0x02000000) { - berr(" ERROR: PC24 [%d] relocation out of range, offset=%08lx\n", + berr("ERROR: PC24 [%d] relocation out of range, offset=%08lx\n", ELF32_R_TYPE(rel->r_info), offset); return -EINVAL; @@ -256,7 +256,7 @@ int up_relocate(FAR const Elf32_Rel *rel, FAR const Elf32_Sym *sym, break; default: - berr("Unsupported relocation: %d\n", ELF32_R_TYPE(rel->r_info)); + berr("ERROR: Unsupported relocation: %d\n", ELF32_R_TYPE(rel->r_info)); return -EINVAL; } @@ -266,6 +266,6 @@ int up_relocate(FAR const Elf32_Rel *rel, FAR const Elf32_Sym *sym, int up_relocateadd(FAR const Elf32_Rela *rel, FAR const Elf32_Sym *sym, uintptr_t addr) { - berr("RELA relocation not supported\n"); + berr("ERROR: RELA relocation not supported\n"); return -ENOSYS; } diff --git a/arch/arm/src/arm/up_prefetchabort.c b/arch/arm/src/arm/up_prefetchabort.c index 070c1ce5d2..c6ec5cccb8 100644 --- a/arch/arm/src/arm/up_prefetchabort.c +++ b/arch/arm/src/arm/up_prefetchabort.c @@ -99,8 +99,8 @@ void up_prefetchabort(uint32_t *regs) * virtual addresses. */ - pgllerr("VADDR: %08x VBASE: %08x VEND: %08x\n", - regs[REG_PC], PG_PAGED_VBASE, PG_PAGED_VEND); + pgllinfo("VADDR: %08x VBASE: %08x VEND: %08x\n", + regs[REG_PC], PG_PAGED_VBASE, PG_PAGED_VEND); if (regs[REG_R15] >= PG_PAGED_VBASE && regs[REG_R15] < PG_PAGED_VEND) { diff --git a/arch/arm/src/arm/up_releasepending.c b/arch/arm/src/arm/up_releasepending.c index 99bf93f6f7..d6d82573d6 100644 --- a/arch/arm/src/arm/up_releasepending.c +++ b/arch/arm/src/arm/up_releasepending.c @@ -67,7 +67,7 @@ void up_release_pending(void) { struct tcb_s *rtcb = this_task(); - sllerr("From TCB=%p\n", rtcb); + sllinfo("From TCB=%p\n", rtcb); /* Merge the g_pendingtasks list into the ready-to-run task list */ diff --git a/arch/arm/src/arm/up_reprioritizertr.c b/arch/arm/src/arm/up_reprioritizertr.c index 7d6015cccb..18c79696e2 100644 --- a/arch/arm/src/arm/up_reprioritizertr.c +++ b/arch/arm/src/arm/up_reprioritizertr.c @@ -95,7 +95,7 @@ void up_reprioritize_rtr(struct tcb_s *tcb, uint8_t priority) struct tcb_s *rtcb = this_task(); bool switch_needed; - sllerr("TCB=%p PRI=%d\n", tcb, priority); + sllinfo("TCB=%p PRI=%d\n", tcb, priority); /* Remove the tcb task from the ready-to-run list. * sched_removereadytorun will return true if we just diff --git a/arch/arm/src/arm/up_schedulesigaction.c b/arch/arm/src/arm/up_schedulesigaction.c index 5b99b2059a..f6f0c655e8 100644 --- a/arch/arm/src/arm/up_schedulesigaction.c +++ b/arch/arm/src/arm/up_schedulesigaction.c @@ -94,7 +94,7 @@ void up_schedule_sigaction(struct tcb_s *tcb, sig_deliver_t sigdeliver) { irqstate_t flags; - serr("tcb=0x%p sigdeliver=0x%p\n", tcb, sigdeliver); + sinfo("tcb=0x%p sigdeliver=0x%p\n", tcb, sigdeliver); /* Make sure that interrupts are disabled */ @@ -108,7 +108,7 @@ void up_schedule_sigaction(struct tcb_s *tcb, sig_deliver_t sigdeliver) * being delivered to the currently executing task. */ - serr("rtcb=0x%p CURRENT_REGS=0x%p\n", this_task(), CURRENT_REGS); + sinfo("rtcb=0x%p CURRENT_REGS=0x%p\n", this_task(), CURRENT_REGS); if (tcb == this_task()) { diff --git a/arch/arm/src/arm/up_sigdeliver.c b/arch/arm/src/arm/up_sigdeliver.c index 0b3b6ea266..29176429f3 100644 --- a/arch/arm/src/arm/up_sigdeliver.c +++ b/arch/arm/src/arm/up_sigdeliver.c @@ -95,7 +95,7 @@ void up_sigdeliver(void) board_autoled_on(LED_SIGNAL); - serr("rtcb=%p sigdeliver=%p sigpendactionq.head=%p\n", + sinfo("rtcb=%p sigdeliver=%p sigpendactionq.head=%p\n", rtcb, rtcb->xcp.sigdeliver, rtcb->sigpendactionq.head); ASSERT(rtcb->xcp.sigdeliver != NULL); @@ -126,7 +126,7 @@ void up_sigdeliver(void) * errno that is needed by the user logic (it is probably EINTR). */ - serr("Resuming\n"); + sinfo("Resuming\n"); (void)up_irq_save(); rtcb->pterrno = saved_errno; diff --git a/arch/arm/src/armv6-m/up_elf.c b/arch/arm/src/armv6-m/up_elf.c index ad0b4d8dad..7bde5d0110 100644 --- a/arch/arm/src/armv6-m/up_elf.c +++ b/arch/arm/src/armv6-m/up_elf.c @@ -86,7 +86,7 @@ bool up_checkarch(FAR const Elf32_Ehdr *ehdr) if (ehdr->e_machine != EM_ARM) { - berr("Not for ARM: e_machine=%04x\n", ehdr->e_machine); + berr("ERROR: Not for ARM: e_machine=%04x\n", ehdr->e_machine); return -ENOEXEC; } @@ -94,7 +94,7 @@ bool up_checkarch(FAR const Elf32_Ehdr *ehdr) if (ehdr->e_ident[EI_CLASS] != ELFCLASS32) { - berr("Need 32-bit objects: e_ident[EI_CLASS]=%02x\n", ehdr->e_ident[EI_CLASS]); + berr("ERROR: Need 32-bit objects: e_ident[EI_CLASS]=%02x\n", ehdr->e_ident[EI_CLASS]); return -ENOEXEC; } @@ -106,7 +106,7 @@ bool up_checkarch(FAR const Elf32_Ehdr *ehdr) if (ehdr->e_ident[EI_DATA] != ELFDATA2LSB) #endif { - berr("Wrong endian-ness: e_ident[EI_DATA]=%02x\n", ehdr->e_ident[EI_DATA]); + berr("ERROR: Wrong endian-ness: e_ident[EI_DATA]=%02x\n", ehdr->e_ident[EI_DATA]); return -ENOEXEC; } @@ -181,7 +181,7 @@ int up_relocate(FAR const Elf32_Rel *rel, FAR const Elf32_Sym *sym, offset += sym->st_value - addr; if (offset & 3 || offset <= (int32_t) 0xfe000000 || offset >= (int32_t) 0x02000000) { - berr(" ERROR: PC24 [%d] relocation out of range, offset=%08lx\n", + berr("ERROR: ERROR: PC24 [%d] relocation out of range, offset=%08lx\n", ELF32_R_TYPE(rel->r_info), offset); return -EINVAL; @@ -290,7 +290,7 @@ int up_relocate(FAR const Elf32_Rel *rel, FAR const Elf32_Sym *sym, if (ELF32_ST_TYPE(sym->st_info) == STT_FUNC && (offset & 1) == 0) { - berr(" ERROR: JUMP24 [%d] requires odd offset, offset=%08lx\n", + berr("ERROR: ERROR: JUMP24 [%d] requires odd offset, offset=%08lx\n", ELF32_R_TYPE(rel->r_info), offset); return -EINVAL; @@ -300,7 +300,7 @@ int up_relocate(FAR const Elf32_Rel *rel, FAR const Elf32_Sym *sym, if (offset <= (int32_t)0xff000000 || offset >= (int32_t)0x01000000) { - berr(" ERROR: JUMP24 [%d] relocation out of range, branch taget=%08lx\n", + berr("ERROR: ERROR: JUMP24 [%d] relocation out of range, branch taget=%08lx\n", ELF32_R_TYPE(rel->r_info), offset); return -EINVAL; @@ -451,7 +451,7 @@ int up_relocate(FAR const Elf32_Rel *rel, FAR const Elf32_Sym *sym, break; default: - berr("Unsupported relocation: %d\n", ELF32_R_TYPE(rel->r_info)); + berr("ERROR: Unsupported relocation: %d\n", ELF32_R_TYPE(rel->r_info)); return -EINVAL; } @@ -461,6 +461,6 @@ int up_relocate(FAR const Elf32_Rel *rel, FAR const Elf32_Sym *sym, int up_relocateadd(FAR const Elf32_Rela *rel, FAR const Elf32_Sym *sym, uintptr_t addr) { - berr("RELA relocation not supported\n"); + berr("ERROR: RELA relocation not supported\n"); return -ENOSYS; } diff --git a/arch/arm/src/armv6-m/up_hardfault.c b/arch/arm/src/armv6-m/up_hardfault.c index ef5c59ba2e..b3c24d8851 100644 --- a/arch/arm/src/armv6-m/up_hardfault.c +++ b/arch/arm/src/armv6-m/up_hardfault.c @@ -55,9 +55,9 @@ ****************************************************************************/ #ifdef CONFIG_DEBUG_HARDFAULT -# define hferr(format, ...) _llerr(format, ##__VA_ARGS__) +# define hfinfo(format, ...) _alert(format, ##__VA_ARGS__) #else -# define hferr(x...) +# define hfinfo(x...) #endif #define INSN_SVC0 0xdf00 /* insn: svc 0 */ @@ -106,7 +106,7 @@ int up_hardfault(int irq, FAR void *context) /* Fetch the instruction that caused the Hard fault */ uint16_t insn = *pc; - hferr(" PC: %p INSN: %04x\n", pc, insn); + hfinfo(" PC: %p INSN: %04x\n", pc, insn); /* If this was the instruction 'svc 0', then forward processing * to the SVCall handler @@ -114,7 +114,7 @@ int up_hardfault(int irq, FAR void *context) if (insn == INSN_SVC0) { - hferr("Forward SVCall\n"); + hfinfo("Forward SVCall\n"); return up_svcall(irq, context); } } @@ -122,22 +122,22 @@ int up_hardfault(int irq, FAR void *context) #if defined(CONFIG_DEBUG_HARDFAULT) /* Dump some hard fault info */ - hferr("\nHard Fault:\n"); - hferr(" IRQ: %d regs: %p\n", irq, regs); - hferr(" PRIMASK: %08x IPSR: %08x\n", - getprimask(), getipsr()); - hferr(" R0: %08x %08x %08x %08x %08x %08x %08x %08x\n", - regs[REG_R0], regs[REG_R1], regs[REG_R2], regs[REG_R3], - regs[REG_R4], regs[REG_R5], regs[REG_R6], regs[REG_R7]); - hferr(" R8: %08x %08x %08x %08x %08x %08x %08x %08x\n", - regs[REG_R8], regs[REG_R9], regs[REG_R10], regs[REG_R11], - regs[REG_R12], regs[REG_R13], regs[REG_R14], regs[REG_R15]); - hferr(" xPSR: %08x PRIMASK: %08x (saved)\n", - CURRENT_REGS[REG_XPSR], CURRENT_REGS[REG_PRIMASK]); + _alert("\nHard Fault:\n"); + _alert(" IRQ: %d regs: %p\n", irq, regs); + _alert(" PRIMASK: %08x IPSR: %08x\n", + getprimask(), getipsr()); + _alert(" R0: %08x %08x %08x %08x %08x %08x %08x %08x\n", + regs[REG_R0], regs[REG_R1], regs[REG_R2], regs[REG_R3], + regs[REG_R4], regs[REG_R5], regs[REG_R6], regs[REG_R7]); + _alert(" R8: %08x %08x %08x %08x %08x %08x %08x %08x\n", + regs[REG_R8], regs[REG_R9], regs[REG_R10], regs[REG_R11], + regs[REG_R12], regs[REG_R13], regs[REG_R14], regs[REG_R15]); + _alert(" xPSR: %08x PRIMASK: %08x (saved)\n", + CURRENT_REGS[REG_XPSR], CURRENT_REGS[REG_PRIMASK]); #endif (void)up_irq_save(); - _llerr("PANIC!!! Hard fault\n"); + _alert("PANIC!!! Hard fault\n"); PANIC(); return OK; /* Won't get here */ } diff --git a/arch/arm/src/armv6-m/up_releasepending.c b/arch/arm/src/armv6-m/up_releasepending.c index 6ac07736b5..8c41277f82 100644 --- a/arch/arm/src/armv6-m/up_releasepending.c +++ b/arch/arm/src/armv6-m/up_releasepending.c @@ -66,7 +66,7 @@ void up_release_pending(void) { struct tcb_s *rtcb = this_task(); - sllerr("From TCB=%p\n", rtcb); + sllinfo("From TCB=%p\n", rtcb); /* Merge the g_pendingtasks list into the ready-to-run task list */ diff --git a/arch/arm/src/armv6-m/up_reprioritizertr.c b/arch/arm/src/armv6-m/up_reprioritizertr.c index ff30d6b590..1b91a105fb 100644 --- a/arch/arm/src/armv6-m/up_reprioritizertr.c +++ b/arch/arm/src/armv6-m/up_reprioritizertr.c @@ -94,7 +94,7 @@ void up_reprioritize_rtr(struct tcb_s *tcb, uint8_t priority) struct tcb_s *rtcb = this_task(); bool switch_needed; - sllerr("TCB=%p PRI=%d\n", tcb, priority); + sllinfo("TCB=%p PRI=%d\n", tcb, priority); /* Remove the tcb task from the ready-to-run list. * sched_removereadytorun will return true if we just removed the head diff --git a/arch/arm/src/armv6-m/up_schedulesigaction.c b/arch/arm/src/armv6-m/up_schedulesigaction.c index bf9fdf1c49..5040582bac 100644 --- a/arch/arm/src/armv6-m/up_schedulesigaction.c +++ b/arch/arm/src/armv6-m/up_schedulesigaction.c @@ -107,7 +107,7 @@ void up_schedule_sigaction(struct tcb_s *tcb, sig_deliver_t sigdeliver) { irqstate_t flags; - serr("tcb=0x%p sigdeliver=0x%p\n", tcb, sigdeliver); + sinfo("tcb=0x%p sigdeliver=0x%p\n", tcb, sigdeliver); /* Make sure that interrupts are disabled */ @@ -121,7 +121,7 @@ void up_schedule_sigaction(struct tcb_s *tcb, sig_deliver_t sigdeliver) * to the currently executing task. */ - serr("rtcb=0x%p CURRENT_REGS=0x%p\n", this_task(), CURRENT_REGS); + sinfo("rtcb=0x%p CURRENT_REGS=0x%p\n", this_task(), CURRENT_REGS); if (tcb == this_task()) { diff --git a/arch/arm/src/armv6-m/up_sigdeliver.c b/arch/arm/src/armv6-m/up_sigdeliver.c index 4f40b97665..c2b3e8675e 100644 --- a/arch/arm/src/armv6-m/up_sigdeliver.c +++ b/arch/arm/src/armv6-m/up_sigdeliver.c @@ -100,7 +100,7 @@ void up_sigdeliver(void) board_autoled_on(LED_SIGNAL); - serr("rtcb=%p sigdeliver=%p sigpendactionq.head=%p\n", + sinfo("rtcb=%p sigdeliver=%p sigpendactionq.head=%p\n", rtcb, rtcb->xcp.sigdeliver, rtcb->sigpendactionq.head); ASSERT(rtcb->xcp.sigdeliver != NULL); @@ -135,7 +135,7 @@ void up_sigdeliver(void) * errno that is needed by the user logic (it is probably EINTR). */ - serr("Resuming\n"); + sinfo("Resuming\n"); (void)up_irq_save(); rtcb->pterrno = saved_errno; diff --git a/arch/arm/src/armv7-a/arm_cpustart.c b/arch/arm/src/armv7-a/arm_cpustart.c index 98aee251ab..8df2ee95a2 100644 --- a/arch/arm/src/armv7-a/arm_cpustart.c +++ b/arch/arm/src/armv7-a/arm_cpustart.c @@ -64,19 +64,19 @@ static inline void arm_registerdump(FAR struct tcb_s *tcb) { int regndx; - _llerr("CPU%d:\n", up_cpu_index()); + _llinfo("CPU%d:\n", up_cpu_index()); /* Dump the startup registers */ for (regndx = REG_R0; regndx <= REG_R15; regndx += 8) { uint32_t *ptr = (uint32_t *)&tcb->xcp.regs[regndx]; - _llerr("R%d: %08x %08x %08x %08x %08x %08x %08x %08x\n", - regndx, ptr[0], ptr[1], ptr[2], ptr[3], - ptr[4], ptr[5], ptr[6], ptr[7]); + _llinfo("R%d: %08x %08x %08x %08x %08x %08x %08x %08x\n", + regndx, ptr[0], ptr[1], ptr[2], ptr[3], + ptr[4], ptr[5], ptr[6], ptr[7]); } - _llerr("CPSR: %08x\n", tcb->xcp.regs[REG_CPSR]); + _llinfo("CPSR: %08x\n", tcb->xcp.regs[REG_CPSR]); } #else # define arm_registerdump(tcb) diff --git a/arch/arm/src/armv7-a/arm_dataabort.c b/arch/arm/src/armv7-a/arm_dataabort.c index dae3b926e0..189b19639e 100644 --- a/arch/arm/src/armv7-a/arm_dataabort.c +++ b/arch/arm/src/armv7-a/arm_dataabort.c @@ -104,7 +104,7 @@ uint32_t *arm_dataabort(uint32_t *regs, uint32_t dfar, uint32_t dfsr) * fatal error. */ - pgllerr("DFSR: %08x DFAR: %08x\n", dfsr, dfar); + pgllinfo("DFSR: %08x DFAR: %08x\n", dfsr, dfar); if ((dfsr & FSR_MASK) != FSR_PAGE) { goto segfault; diff --git a/arch/arm/src/armv7-a/arm_elf.c b/arch/arm/src/armv7-a/arm_elf.c index e262095e5c..8b9528159c 100644 --- a/arch/arm/src/armv7-a/arm_elf.c +++ b/arch/arm/src/armv7-a/arm_elf.c @@ -74,7 +74,7 @@ bool up_checkarch(FAR const Elf32_Ehdr *ehdr) if (ehdr->e_machine != EM_ARM) { - berr("Not for ARM: e_machine=%04x\n", ehdr->e_machine); + berr("ERROR: Not for ARM: e_machine=%04x\n", ehdr->e_machine); return -ENOEXEC; } @@ -82,7 +82,7 @@ bool up_checkarch(FAR const Elf32_Ehdr *ehdr) if (ehdr->e_ident[EI_CLASS] != ELFCLASS32) { - berr("Need 32-bit objects: e_ident[EI_CLASS]=%02x\n", ehdr->e_ident[EI_CLASS]); + berr("ERROR: Need 32-bit objects: e_ident[EI_CLASS]=%02x\n", ehdr->e_ident[EI_CLASS]); return -ENOEXEC; } @@ -94,7 +94,7 @@ bool up_checkarch(FAR const Elf32_Ehdr *ehdr) if (ehdr->e_ident[EI_DATA] != ELFDATA2LSB) #endif { - berr("Wrong endian-ness: e_ident[EI_DATA]=%02x\n", ehdr->e_ident[EI_DATA]); + berr("ERROR: Wrong endian-ness: e_ident[EI_DATA]=%02x\n", ehdr->e_ident[EI_DATA]); return -ENOEXEC; } @@ -102,7 +102,7 @@ bool up_checkarch(FAR const Elf32_Ehdr *ehdr) if ((ehdr->e_entry & 3) != 0) { - berr("Entry point is not properly aligned: %08x\n", ehdr->e_entry); + berr("ERROR: Entry point is not properly aligned: %08x\n", ehdr->e_entry); return -ENOEXEC; } @@ -175,7 +175,7 @@ int up_relocate(FAR const Elf32_Rel *rel, FAR const Elf32_Sym *sym, offset += sym->st_value - addr; if (offset & 3 || offset <= (int32_t) 0xfe000000 || offset >= (int32_t) 0x02000000) { - berr(" ERROR: PC24 [%d] relocation out of range, offset=%08lx\n", + berr("ERROR: PC24 [%d] relocation out of range, offset=%08lx\n", ELF32_R_TYPE(rel->r_info), offset); return -EINVAL; @@ -246,7 +246,7 @@ int up_relocate(FAR const Elf32_Rel *rel, FAR const Elf32_Sym *sym, break; default: - berr("Unsupported relocation: %d\n", ELF32_R_TYPE(rel->r_info)); + berr("ERROR: Unsupported relocation: %d\n", ELF32_R_TYPE(rel->r_info)); return -EINVAL; } @@ -256,6 +256,6 @@ int up_relocate(FAR const Elf32_Rel *rel, FAR const Elf32_Sym *sym, int up_relocateadd(FAR const Elf32_Rela *rel, FAR const Elf32_Sym *sym, uintptr_t addr) { - berr("RELA relocation not supported\n"); + berr("ERROR: RELA relocation not supported\n"); return -ENOSYS; } diff --git a/arch/arm/src/armv7-a/arm_l2cc_pl310.c b/arch/arm/src/armv7-a/arm_l2cc_pl310.c index 94a1a343dc..9d455e40d2 100644 --- a/arch/arm/src/armv7-a/arm_l2cc_pl310.c +++ b/arch/arm/src/armv7-a/arm_l2cc_pl310.c @@ -411,7 +411,7 @@ void up_l2ccinitialize(void) putreg32(L2CC_CR_L2CEN, L2CC_CR); } - _llerr("(%d ways) * (%d bytes/way) = %d bytes\n", + sinfo("(%d ways) * (%d bytes/way) = %d bytes\n", PL310_NWAYS, PL310_WAYSIZE, PL310_CACHE_SIZE); } diff --git a/arch/arm/src/armv7-a/arm_prefetchabort.c b/arch/arm/src/armv7-a/arm_prefetchabort.c index 4e21143642..898a6145ae 100644 --- a/arch/arm/src/armv7-a/arm_prefetchabort.c +++ b/arch/arm/src/armv7-a/arm_prefetchabort.c @@ -86,8 +86,8 @@ uint32_t *arm_prefetchabort(uint32_t *regs, uint32_t ifar, uint32_t ifsr) * virtual addresses. */ - pgllerr("VADDR: %08x VBASE: %08x VEND: %08x\n", - regs[REG_PC], PG_PAGED_VBASE, PG_PAGED_VEND); + pgllinfo("VADDR: %08x VBASE: %08x VEND: %08x\n", + regs[REG_PC], PG_PAGED_VBASE, PG_PAGED_VEND); if (regs[REG_R15] >= PG_PAGED_VBASE && regs[REG_R15] < PG_PAGED_VEND) { diff --git a/arch/arm/src/armv7-a/arm_releasepending.c b/arch/arm/src/armv7-a/arm_releasepending.c index b2e36821b1..5cabfe7a8b 100644 --- a/arch/arm/src/armv7-a/arm_releasepending.c +++ b/arch/arm/src/armv7-a/arm_releasepending.c @@ -67,7 +67,7 @@ void up_release_pending(void) { struct tcb_s *rtcb = this_task(); - sllerr("From TCB=%p\n", rtcb); + sllinfo("From TCB=%p\n", rtcb); /* Merge the g_pendingtasks list into the ready-to-run task list */ diff --git a/arch/arm/src/armv7-a/arm_reprioritizertr.c b/arch/arm/src/armv7-a/arm_reprioritizertr.c index 468e382779..d177510c85 100644 --- a/arch/arm/src/armv7-a/arm_reprioritizertr.c +++ b/arch/arm/src/armv7-a/arm_reprioritizertr.c @@ -95,7 +95,7 @@ void up_reprioritize_rtr(struct tcb_s *tcb, uint8_t priority) struct tcb_s *rtcb = this_task(); bool switch_needed; - sllerr("TCB=%p PRI=%d\n", tcb, priority); + sllinfo("TCB=%p PRI=%d\n", tcb, priority); /* Remove the tcb task from the ready-to-run list. * sched_removereadytorun will return true if we just diff --git a/arch/arm/src/armv7-a/arm_schedulesigaction.c b/arch/arm/src/armv7-a/arm_schedulesigaction.c index 74648c8fa5..89df348ba0 100644 --- a/arch/arm/src/armv7-a/arm_schedulesigaction.c +++ b/arch/arm/src/armv7-a/arm_schedulesigaction.c @@ -94,7 +94,7 @@ void up_schedule_sigaction(struct tcb_s *tcb, sig_deliver_t sigdeliver) { irqstate_t flags; - serr("tcb=0x%p sigdeliver=0x%p\n", tcb, sigdeliver); + sinfo("tcb=0x%p sigdeliver=0x%p\n", tcb, sigdeliver); /* Make sure that interrupts are disabled */ @@ -108,7 +108,7 @@ void up_schedule_sigaction(struct tcb_s *tcb, sig_deliver_t sigdeliver) * to the currently executing task. */ - serr("rtcb=0x%p CURRENT_REGS=0x%p\n", this_task(), CURRENT_REGS); + sinfo("rtcb=0x%p CURRENT_REGS=0x%p\n", this_task(), CURRENT_REGS); if (tcb == this_task()) { diff --git a/arch/arm/src/armv7-a/arm_sigdeliver.c b/arch/arm/src/armv7-a/arm_sigdeliver.c index 8009386492..be720a464c 100644 --- a/arch/arm/src/armv7-a/arm_sigdeliver.c +++ b/arch/arm/src/armv7-a/arm_sigdeliver.c @@ -83,7 +83,7 @@ void up_sigdeliver(void) board_autoled_on(LED_SIGNAL); - serr("rtcb=%p sigdeliver=%p sigpendactionq.head=%p\n", + sinfo("rtcb=%p sigdeliver=%p sigpendactionq.head=%p\n", rtcb, rtcb->xcp.sigdeliver, rtcb->sigpendactionq.head); ASSERT(rtcb->xcp.sigdeliver != NULL); @@ -114,7 +114,7 @@ void up_sigdeliver(void) * errno that is needed by the user logic (it is probably EINTR). */ - serr("Resuming\n"); + sinfo("Resuming\n"); (void)up_irq_save(); rtcb->pterrno = saved_errno; From ae04f259650fe31e5821e88a675ed4f87121d40c Mon Sep 17 00:00:00 2001 From: David Sidrane Date: Wed, 15 Jun 2016 12:44:13 -1000 Subject: [PATCH 58/75] Clean up and Use two level include 74xx77xx ADC --- arch/arm/src/stm32/stm32_adc.c | 1 - arch/arm/src/stm32f7/chip/stm32_adc.h | 461 +---------------- .../arm/src/stm32f7/chip/stm32f74xx77xx_adc.h | 484 ++++++++++++++++++ arch/arm/src/stm32f7/stm32_adc.c | 18 +- arch/arm/src/stm32f7/stm32_adc.h | 7 +- 5 files changed, 511 insertions(+), 460 deletions(-) create mode 100644 arch/arm/src/stm32f7/chip/stm32f74xx77xx_adc.h diff --git a/arch/arm/src/stm32/stm32_adc.c b/arch/arm/src/stm32/stm32_adc.c index 3b541dde8a..70fd1071cd 100644 --- a/arch/arm/src/stm32/stm32_adc.c +++ b/arch/arm/src/stm32/stm32_adc.c @@ -1666,7 +1666,6 @@ static void adc_dmaconvcallback(DMA_HANDLE handle, uint8_t isr, FAR void *arg) priv->current = 0; } } - } /* Restart DMA for the next conversion series */ diff --git a/arch/arm/src/stm32f7/chip/stm32_adc.h b/arch/arm/src/stm32f7/chip/stm32_adc.h index 067301d4c7..7b0861d77e 100644 --- a/arch/arm/src/stm32f7/chip/stm32_adc.h +++ b/arch/arm/src/stm32f7/chip/stm32_adc.h @@ -2,7 +2,8 @@ * arch/arm/src/stm32f7/chip/stm32_adc.h * * Copyright (C) 2016 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Authors: Gregory Nutt + * David Sidrane * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions @@ -33,8 +34,8 @@ * ****************************************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32F_CHIP_STM32_ADC_H -#define __ARCH_ARM_SRC_STM32F_CHIP_STM32_ADC_H +#ifndef __ARCH_ARM_SRC_STM32F7_CHIP_STM32_ADC_H +#define __ARCH_ARM_SRC_STM32F7_CHIP_STM32_ADC_H /**************************************************************************************************** * Included Files @@ -44,452 +45,14 @@ #include "chip.h" -/**************************************************************************************************** - * Pre-processor Definitions - ****************************************************************************************************/ +#include +#include "chip.h" -/* Register Offsets *********************************************************************************/ - -#define STM32_ADC_SR_OFFSET 0x0000 /* ADC status register (32-bit) */ -#define STM32_ADC_CR1_OFFSET 0x0004 /* ADC control register 1 (32-bit) */ -#define STM32_ADC_CR2_OFFSET 0x0008 /* ADC control register 2 (32-bit) */ -#define STM32_ADC_SMPR1_OFFSET 0x000c /* ADC sample time register 1 (32-bit) */ -#define STM32_ADC_SMPR2_OFFSET 0x0010 /* ADC sample time register 2 (32-bit) */ -#define STM32_ADC_JOFR1_OFFSET 0x0014 /* ADC injected channel data offset register 1 (32-bit) */ -#define STM32_ADC_JOFR2_OFFSET 0x0018 /* ADC injected channel data offset register 2 (32-bit) */ -#define STM32_ADC_JOFR3_OFFSET 0x001c /* ADC injected channel data offset register 3 (32-bit) */ -#define STM32_ADC_JOFR4_OFFSET 0x0020 /* ADC injected channel data offset register 4 (32-bit) */ -#define STM32_ADC_HTR_OFFSET 0x0024 /* ADC watchdog high threshold register (32-bit) */ -#define STM32_ADC_LTR_OFFSET 0x0028 /* ADC watchdog low threshold register (32-bit) */ -#define STM32_ADC_SQR1_OFFSET 0x002c /* ADC regular sequence register 1 (32-bit) */ -#define STM32_ADC_SQR2_OFFSET 0x0030 /* ADC regular sequence register 2 (32-bit) */ -#define STM32_ADC_SQR3_OFFSET 0x0034 /* ADC regular sequence register 3 (32-bit) */ -#define STM32_ADC_JSQR_OFFSET 0x0038 /* ADC injected sequence register (32-bit) */ -#define STM32_ADC_JDR1_OFFSET 0x003c /* ADC injected data register 1 (32-bit) */ -#define STM32_ADC_JDR2_OFFSET 0x0040 /* ADC injected data register 1 (32-bit) */ -#define STM32_ADC_JDR3_OFFSET 0x0044 /* ADC injected data register 1 (32-bit) */ -#define STM32_ADC_JDR4_OFFSET 0x0048 /* ADC injected data register 1 (32-bit) */ -#define STM32_ADC_DR_OFFSET 0x004c /* ADC regular data register (32-bit) */ - - -#define STM32_ADC_CSR_OFFSET 0x0000 /* Common status register */ -#define STM32_ADC_CCR_OFFSET 0x0004 /* Common control register */ -#define STM32_ADC_CDR_OFFSET 0x0008 /* Data register for dual and triple modes */ - -/* Register Addresses *******************************************************************************/ - -#if STM32F7_NADC > 0 -# define STM32_ADC1_SR (STM32_ADC1_BASE+STM32_ADC_SR_OFFSET) -# define STM32_ADC1_CR1 (STM32_ADC1_BASE+STM32_ADC_CR1_OFFSET) -# define STM32_ADC1_CR2 (STM32_ADC1_BASE+STM32_ADC_CR2_OFFSET) -# define STM32_ADC1_SMPR1 (STM32_ADC1_BASE+STM32_ADC_SMPR1_OFFSET) -# define STM32_ADC1_SMPR2 (STM32_ADC1_BASE+STM32_ADC_SMPR2_OFFSET) -# define STM32_ADC1_JOFR1 (STM32_ADC1_BASE+STM32_ADC_JOFR1_OFFSET) -# define STM32_ADC1_JOFR2 (STM32_ADC1_BASE+STM32_ADC_JOFR2_OFFSET) -# define STM32_ADC1_JOFR3 (STM32_ADC1_BASE+STM32_ADC_JOFR3_OFFSET) -# define STM32_ADC1_JOFR4 (STM32_ADC1_BASE+STM32_ADC_JOFR4_OFFSET) -# define STM32_ADC1_HTR (STM32_ADC1_BASE+STM32_ADC_HTR_OFFSET) -# define STM32_ADC1_LTR (STM32_ADC1_BASE+STM32_ADC_LTR_OFFSET) -# define STM32_ADC1_SQR1 (STM32_ADC1_BASE+STM32_ADC_SQR1_OFFSET) -# define STM32_ADC1_SQR2 (STM32_ADC1_BASE+STM32_ADC_SQR2_OFFSET) -# define STM32_ADC1_SQR3 (STM32_ADC1_BASE+STM32_ADC_SQR3_OFFSET) -# define STM32_ADC1_JSQR (STM32_ADC1_BASE+STM32_ADC_JSQR_OFFSET) -# define STM32_ADC1_JDR1 (STM32_ADC1_BASE+STM32_ADC_JDR1_OFFSET) -# define STM32_ADC1_JDR2 (STM32_ADC1_BASE+STM32_ADC_JDR2_OFFSET) -# define STM32_ADC1_JDR3 (STM32_ADC1_BASE+STM32_ADC_JDR3_OFFSET) -# define STM32_ADC1_JDR4 (STM32_ADC1_BASE+STM32_ADC_JDR4_OFFSET) -# define STM32_ADC1_DR (STM32_ADC1_BASE+STM32_ADC_DR_OFFSET) +#if defined(CONFIG_STM32F7_STM32F74XX) || defined(CONFIG_STM32F7_STM32F75XX) || \ + defined(CONFIG_STM32F7_STM32F76XX) || defined(CONFIG_STM32F7_STM32F77XX) +# include "chip/stm32f74xx77xx_adc.h" +#else +# error "Unsupported STM32 F7 sub family" #endif -#if STM32F7_NADC > 1 -# define STM32_ADC2_SR (STM32_ADC2_BASE+STM32_ADC_SR_OFFSET) -# define STM32_ADC2_CR1 (STM32_ADC2_BASE+STM32_ADC_CR1_OFFSET) -# define STM32_ADC2_CR2 (STM32_ADC2_BASE+STM32_ADC_CR2_OFFSET) -# define STM32_ADC2_SMPR1 (STM32_ADC2_BASE+STM32_ADC_SMPR1_OFFSET) -# define STM32_ADC2_SMPR2 (STM32_ADC2_BASE+STM32_ADC_SMPR2_OFFSET) -# define STM32_ADC2_JOFR1 (STM32_ADC2_BASE+STM32_ADC_JOFR1_OFFSET) -# define STM32_ADC2_JOFR2 (STM32_ADC2_BASE+STM32_ADC_JOFR2_OFFSET) -# define STM32_ADC2_JOFR3 (STM32_ADC2_BASE+STM32_ADC_JOFR3_OFFSET) -# define STM32_ADC2_JOFR4 (STM32_ADC2_BASE+STM32_ADC_JOFR4_OFFSET) -# define STM32_ADC2_HTR (STM32_ADC2_BASE+STM32_ADC_HTR_OFFSET) -# define STM32_ADC2_LTR (STM32_ADC2_BASE+STM32_ADC_LTR_OFFSET) -# define STM32_ADC2_SQR1 (STM32_ADC2_BASE+STM32_ADC_SQR1_OFFSET) -# define STM32_ADC2_SQR2 (STM32_ADC2_BASE+STM32_ADC_SQR2_OFFSET) -# define STM32_ADC2_SQR3 (STM32_ADC2_BASE+STM32_ADC_SQR3_OFFSET) -# define STM32_ADC2_JSQR (STM32_ADC2_BASE+STM32_ADC_JSQR_OFFSET) -# define STM32_ADC2_JDR1 (STM32_ADC2_BASE+STM32_ADC_JDR1_OFFSET) -# define STM32_ADC2_JDR2 (STM32_ADC2_BASE+STM32_ADC_JDR2_OFFSET) -# define STM32_ADC2_JDR3 (STM32_ADC2_BASE+STM32_ADC_JDR3_OFFSET) -# define STM32_ADC2_JDR4 (STM32_ADC2_BASE+STM32_ADC_JDR4_OFFSET) -# define STM32_ADC2_DR (STM32_ADC2_BASE+STM32_ADC_DR_OFFSET) -#endif - -#if STM32F7_NADC > 2 -# define STM32_ADC3_SR (STM32_ADC3_BASE+STM32_ADC_SR_OFFSET) -# define STM32_ADC3_CR1 (STM32_ADC3_BASE+STM32_ADC_CR1_OFFSET) -# define STM32_ADC3_CR2 (STM32_ADC3_BASE+STM32_ADC_CR2_OFFSET) -# define STM32_ADC3_SMPR1 (STM32_ADC3_BASE+STM32_ADC_SMPR1_OFFSET) -# define STM32_ADC3_SMPR2 (STM32_ADC3_BASE+STM32_ADC_SMPR2_OFFSET) -# define STM32_ADC3_JOFR1 (STM32_ADC3_BASE+STM32_ADC_JOFR1_OFFSET) -# define STM32_ADC3_JOFR2 (STM32_ADC3_BASE+STM32_ADC_JOFR2_OFFSET) -# define STM32_ADC3_JOFR3 (STM32_ADC3_BASE+STM32_ADC_JOFR3_OFFSET) -# define STM32_ADC3_JOFR4 (STM32_ADC3_BASE+STM32_ADC_JOFR4_OFFSET) -# define STM32_ADC3_HTR (STM32_ADC3_BASE+STM32_ADC_HTR_OFFSET) -# define STM32_ADC3_LTR (STM32_ADC3_BASE+STM32_ADC_LTR_OFFSET) -# define STM32_ADC3_SQR1 (STM32_ADC3_BASE+STM32_ADC_SQR1_OFFSET) -# define STM32_ADC3_SQR2 (STM32_ADC3_BASE+STM32_ADC_SQR2_OFFSET) -# define STM32_ADC3_SQR3 (STM32_ADC3_BASE+STM32_ADC_SQR3_OFFSET) -# define STM32_ADC3_JSQR (STM32_ADC3_BASE+STM32_ADC_JSQR_OFFSET) -# define STM32_ADC3_JDR1 (STM32_ADC3_BASE+STM32_ADC_JDR1_OFFSET) -# define STM32_ADC3_JDR2 (STM32_ADC3_BASE+STM32_ADC_JDR2_OFFSET) -# define STM32_ADC3_JDR3 (STM32_ADC3_BASE+STM32_ADC_JDR3_OFFSET) -# define STM32_ADC3_JDR4 (STM32_ADC3_BASE+STM32_ADC_JDR4_OFFSET) -# define STM32_ADC3_DR (STM32_ADC3_BASE+STM32_ADC_DR_OFFSET) -#endif - -#define STM32_ADC_CSR (STM32_ADCCMN_BASE+STM32_ADC_CSR_OFFSET) -#define STM32_ADC_CCR (STM32_ADCCMN_BASE+STM32_ADC_CCR_OFFSET) -#define STM32_ADC_CDR (STM32_ADCCMN_BASE+STM32_ADC_CDR_OFFSET) - -/* Register Bitfield Definitions ********************************************************************/ - -/* ADC status register */ - -#define ADC_SR_AWD (1 << 0) /* Bit 0 : Analog watchdog flag */ -#define ADC_SR_EOC (1 << 1) /* Bit 1 : End of conversion */ -#define ADC_SR_JEOC (1 << 2) /* Bit 2 : Injected channel end of conversion */ -#define ADC_SR_JSTRT (1 << 3) /* Bit 3 : Injected channel Start flag */ -#define ADC_SR_STRT (1 << 4) /* Bit 4 : Regular channel Start flag */ -#define ADC_SR_OVR (1 << 5) /* Bit 5 : Overrun */ - -/* ADC control register 1 */ - -#define ADC_CR1_AWDCH_SHIFT (0) /* Bits 4-0: Analog watchdog channel select bits */ -#define ADC_CR1_AWDCH_MASK (0x1f << ADC_CR1_AWDCH_SHIFT) - -#define ADC_CR1_EOCIE (1 << 5) /* Bit 5: Interrupt enable for EOC */ -#define ADC_CR1_AWDIE (1 << 6) /* Bit 6: Analog Watchdog interrupt enable */ -#define ADC_CR1_JEOCIE (1 << 7) /* Bit 7: Interrupt enable for injected channels */ -#define ADC_CR1_SCAN (1 << 8) /* Bit 8: Scan mode */ -#define ADC_CR1_AWDSGL (1 << 9) /* Bit 9: Enable the watchdog on a single channel in scan mode */ -#define ADC_CR1_JAUTO (1 << 10) /* Bit 10: Automatic Injected Group conversion */ -#define ADC_CR1_DISCEN (1 << 11) /* Bit 11: Discontinuous mode on regular channels */ -#define ADC_CR1_JDISCEN (1 << 12) /* Bit 12: Discontinuous mode on injected channels */ - -#define ADC_CR1_DISCNUM_SHIFT (13) /* Bits 15-13: Discontinuous mode channel count */ -#define ADC_CR1_DISCNUM_MASK (0x07 << ADC_CR1_DISCNUM_SHIFT) - - -#define ADC_CR1_JAWDEN (1 << 22) /* Bit 22: Analog watchdog enable on injected channels */ -#define ADC_CR1_AWDEN (1 << 23) /* Bit 23: Analog watchdog enable on regular channels */ - -#define ADC_CR1_RES_SHIFT (24) /* Bits 24-25: Resolution */ -#define ADC_CR1_RES_MASK (3 << ADC_CR1_RES_SHIFT) -#define ADC_CR1_RES_12BIT (0 << ADC_CR1_RES_SHIFT) /* 15 ADCCLK cycles. For STM32L15XX: 12 ADCCLK cycles */ -#define ADC_CR1_RES_10BIT (1 << ADC_CR1_RES_SHIFT) /* 13 ADCCLK cycles. For STM32L15XX: 11 ADCCLK cycles */ -#define ADC_CR1_RES_8BIT (2 << ADC_CR1_RES_SHIFT) /* 11 ADCCLK cycles. For STM32L15XX: 9 ADCCLK cycles */ -#define ADC_CR1_RES_6BIT (3 << ADC_CR1_RES_SHIFT) /* 9 ADCCLK cycles. For STM32L15XX: 7 ADCCLK cycles */ -#define ADC_CR1_OVRIE (1 << 26) /* Bit 26: Overrun interrupt enable */ - -/* ADC control register 2 */ - -#define ADC_CR2_ADON (1 << 0) /* Bit 0: A/D Converter ON / OFF */ -#define ADC_CR2_CONT (1 << 1) /* Bit 1: Continuous Conversion */ - -#define ADC_CR2_DMA (1 << 8) /* Bit 8: Direct Memory access mode */ - -#define ADC_CR2_DDS (1 << 9) /* Bit 9: DMA disable selection (for single ADC mode) */ -#define ADC_CR2_EOCS (1 << 10) /* Bit 10: End of conversion selection */ - -#define ADC_CR2_ALIGN (1 << 11) /* Bit 11: Data Alignment */ - - /* Bits 12-15: Reserved */ -#define ADC_CR2_JEXTSEL_SHIFT (16) /* Bits 16-19: External event select for injected group */ -#define ADC_CR2_JEXTSEL_MASK (0x0F << ADC_CR2_JEXTSEL_SHIFT) -#define ADC_CR2_JEXTSEL_T1TRGO (0x00 << ADC_CR2_JEXTSEL_SHIFT) /* 0000: Timer 1 TRGO event */ -#define ADC_CR2_JEXTSEL_T1CC4 (0x01 << ADC_CR2_JEXTSEL_SHIFT) /* 0001: Timer 1 CC4 event */ -#define ADC_CR2_JEXTSEL_T2TRGO (0x02 << ADC_CR2_JEXTSEL_SHIFT) /* 0010: Timer 2 TRGO event */ -#define ADC_CR2_JEXTSEL_T2CC1 (0x03 << ADC_CR2_JEXTSEL_SHIFT) /* 0011: Timer 2 CC1 event */ -#define ADC_CR2_JEXTSEL_T3CC4 (0x04 << ADC_CR2_JEXTSEL_SHIFT) /* 0100: Timer 3 CC4 event */ -#define ADC_CR2_JEXTSEL_T4TRGO (0x05 << ADC_CR2_JEXTSEL_SHIFT) /* 0101: Timer 4 TRGO event */ - /* 0110: NA */ -#define ADC_CR2_JEXTSEL_T8CC4 (0x07 << ADC_CR2_JEXTSEL_SHIFT) /* 0111: Timer 8 CC4 event */ -#define ADC_CR2_JEXTSEL_T1TRGO2 (0x08 << ADC_CR2_JEXTSEL_SHIFT) /* 1000: Timer 1 TRGO2 event */ -#define ADC_CR2_JEXTSEL_T8TRGO (0x09 << ADC_CR2_JEXTSEL_SHIFT) /* 1001: Timer 8 TRGO event */ -#define ADC_CR2_JEXTSEL_T8TRGO2 (0x0A << ADC_CR2_JEXTSEL_SHIFT) /* 1010: Timer 8 TRGO2 event */ -#define ADC_CR2_JEXTSEL_T3CC3 (0x0B << ADC_CR2_JEXTSEL_SHIFT) /* 1011: Timer 3 CC3 event */ -#define ADC_CR2_JEXTSEL_T5TRGO (0x0C << ADC_CR2_JEXTSEL_SHIFT) /* 1100: Timer 5 TRGO event */ -#define ADC_CR2_JEXTSEL_T3CC1 (0x0D << ADC_CR2_JEXTSEL_SHIFT) /* 1101: Timer 3 CC1 event */ -#define ADC_CR2_JEXTSEL_T6TRGO (0x0E << ADC_CR2_JEXTSEL_SHIFT) /* 1110: Timer 6 TRGO event */ - /* 1111: NA */ -#define ADC_CR2_JEXTEN_SHIFT (20) /* Bits 20-21: External trigger enable for injected channels */ -#define ADC_CR2_JEXTEN_MASK (3 << ADC_CR2_JEXTEN_SHIFT) -#define ADC_CR2_JEXTEN_NONE (0 << ADC_CR2_JEXTEN_SHIFT) /* 00: Trigger detection disabled */ -#define ADC_CR2_JEXTEN_RISING (1 << ADC_CR2_JEXTEN_SHIFT) /* 01: Trigger detection on the rising edge */ -#define ADC_CR2_JEXTEN_FALLING (2 << ADC_CR2_JEXTEN_SHIFT) /* 10: Trigger detection on the falling edge */ -#define ADC_CR2_JEXTEN_BOTH (3 << ADC_CR2_JEXTEN_SHIFT) /* 11: Trigger detection on both the rising and falling edges */ - -#define ADC_CR2_JSWSTART (1 << 22) /* Bit 22: Start Conversion of injected channels */ - /* Bit 23: Reserved, must be kept at reset value. */ -#define ADC_CR2_EXTSEL_SHIFT (24) /* Bits 24-27: External Event Select for regular group */ -#define ADC_CR2_EXTSEL_MASK (0x0F << ADC_CR2_EXTSEL_SHIFT) -#define ADC_CR2_EXTSEL_T1CC1 (0x0 << ADC_CR2_EXTSEL_SHIFT) /* 0000: Timer 1 CC1 event */ -#define ADC_CR2_EXTSEL_T1CC2 (0x01 << ADC_CR2_EXTSEL_SHIFT) /* 0001: Timer 1 CC2 event */ -#define ADC_CR2_EXTSEL_T1CC3 (0x02 << ADC_CR2_EXTSEL_SHIFT) /* 0010: Timer 1 CC3 event */ -#define ADC_CR2_EXTSEL_T2CC2 (0x03 << ADC_CR2_EXTSEL_SHIFT) /* 0011: Timer 2 CC2 event */ -#define ADC_CR2_EXTSEL_T5TRGO (0x04 << ADC_CR2_EXTSEL_SHIFT) /* 0100: Timer 5 TRGO event */ -#define ADC_CR2_EXTSEL_T4CC4 (0x05 << ADC_CR2_EXTSEL_SHIFT) /* 0101: Timer 4 CC4 event */ -#define ADC_CR2_EXTSEL_T3CC4 (0x06 << ADC_CR2_EXTSEL_SHIFT) /* 0110: Timer 3 CC4 event */ -#define ADC_CR2_EXTSEL_T8TRGO (0x07 << ADC_CR2_EXTSEL_SHIFT) /* 0111: Timer 8 TRGO event */ -#define ADC_CR2_EXTSEL_T8TRGO2 (0x08 << ADC_CR2_EXTSEL_SHIFT) /* 1000: Timer 8 TRGO2 event */ -#define ADC_CR2_EXTSEL_T1TRGO (0x09 << ADC_CR2_EXTSEL_SHIFT) /* 1001: Timer 1 TRGO event */ -#define ADC_CR2_EXTSEL_T1TRGO2 (0x0A << ADC_CR2_EXTSEL_SHIFT) /* 1010: Timer 1 TRGO2 event */ -#define ADC_CR2_EXTSEL_T2TRGO (0x0B << ADC_CR2_EXTSEL_SHIFT) /* 1011: Timer 2 TRGO event */ -#define ADC_CR2_EXTSEL_T4TRGO (0x0C << ADC_CR2_EXTSEL_SHIFT) /* 1100: Timer 4 TRGO event */ -#define ADC_CR2_EXTSEL_T6TRGO (0x0D << ADC_CR2_EXTSEL_SHIFT) /* 1101: Timer 6 TRGO event */ - /* 1110: NA */ -#define ADC_CR2_EXTSEL_EXTI11 (0x0F << ADC_CR2_EXTSEL_SHIFT) /* 1111: EXTI line 11 */ - -#define ADC_CR2_EXTEN_SHIFT (28) /* Bits 28-29: External trigger enable for regular channels */ -#define ADC_CR2_EXTEN_MASK (3 << ADC_CR2_EXTEN_SHIFT) -#define ADC_CR2_EXTEN_NONE (0 << ADC_CR2_EXTEN_SHIFT) /* 00: Trigger detection disabled */ -#define ADC_CR2_EXTEN_RISING (1 << ADC_CR2_EXTEN_SHIFT) /* 01: Trigger detection on the rising edge */ -#define ADC_CR2_EXTEN_FALLING (2 << ADC_CR2_EXTEN_SHIFT) /* 10: Trigger detection on the falling edge */ -#define ADC_CR2_EXTEN_BOTH (3 << ADC_CR2_EXTEN_SHIFT) /* 11: Trigger detection on both the rising and falling edges */ - -# define ADC_CR2_SWSTART (1 << 30) /* Bit 30: Start Conversion of regular channels */ - -/* ADC sample time register 1 */ - -#define ADC_SMPR_3 0 /* 000: 3 cycles */ -#define ADC_SMPR_15 1 /* 001: 15 cycles */ -#define ADC_SMPR_28 2 /* 010: 28 cycles */ -#define ADC_SMPR_56 3 /* 011: 56 cycles */ -#define ADC_SMPR_84 4 /* 100: 84 cycles */ -#define ADC_SMPR_112 5 /* 101: 112 cycles */ -#define ADC_SMPR_144 6 /* 110: 144 cycles */ -#define ADC_SMPR_480 7 /* 111: 480 cycles */ - -#define ADC_SMPR1_SMP10_SHIFT (0) /* Bits 0-2: Channel 10 Sample time selection */ -#define ADC_SMPR1_SMP10_MASK (7 << ADC_SMPR1_SMP10_SHIFT) -#define ADC_SMPR1_SMP11_SHIFT (3) /* Bits 3-5: Channel 11 Sample time selection */ -#define ADC_SMPR1_SMP11_MASK (7 << ADC_SMPR1_SMP11_SHIFT) -#define ADC_SMPR1_SMP12_SHIFT (6) /* Bits 6-8: Channel 12 Sample time selection */ -#define ADC_SMPR1_SMP12_MASK (7 << ADC_SMPR1_SMP12_SHIFT) -#define ADC_SMPR1_SMP13_SHIFT (9) /* Bits 9-11: Channel 13 Sample time selection */ -#define ADC_SMPR1_SMP13_MASK (7 << ADC_SMPR1_SMP13_SHIFT) -#define ADC_SMPR1_SMP14_SHIFT (12) /* Bits 12-14: Channel 14 Sample time selection */ -#define ADC_SMPR1_SMP14_MASK (7 << ADC_SMPR1_SMP14_SHIFT) -#define ADC_SMPR1_SMP15_SHIFT (15) /* Bits 15-17: Channel 15 Sample time selection */ -#define ADC_SMPR1_SMP15_MASK (7 << ADC_SMPR1_SMP15_SHIFT) -#define ADC_SMPR1_SMP16_SHIFT (18) /* Bits 18-20: Channel 16 Sample time selection */ -#define ADC_SMPR1_SMP16_MASK (7 << ADC_SMPR1_SMP16_SHIFT) -#define ADC_SMPR1_SMP17_SHIFT (21) /* Bits 21-23: Channel 17 Sample time selection */ -#define ADC_SMPR1_SMP17_MASK (7 << ADC_SMPR1_SMP17_SHIFT) -#define ADC_SMPR1_SMP18_SHIFT (21) /* Bits 24-26: Channel 18 Sample time selection */ -#define ADC_SMPR1_SMP18_MASK (7 << ADC_SMPR1_SMP17_SHIFT) - - -/* ADC sample time register 2 */ - -#define ADC_SMPR2_SMP0_SHIFT (0) /* Bits 2-0: Channel 0 Sample time selection */ -#define ADC_SMPR2_SMP0_MASK (7 << ADC_SMPR2_SMP0_SHIFT) -#define ADC_SMPR2_SMP1_SHIFT (3) /* Bits 5-3: Channel 1 Sample time selection */ -#define ADC_SMPR2_SMP1_MASK (7 << ADC_SMPR2_SMP1_SHIFT) -#define ADC_SMPR2_SMP2_SHIFT (6) /* Bits 8-6: Channel 2 Sample time selection */ -#define ADC_SMPR2_SMP2_MASK (7 << ADC_SMPR2_SMP2_SHIFT) -#define ADC_SMPR2_SMP3_SHIFT (9) /* Bits 11-9: Channel 3 Sample time selection */ -#define ADC_SMPR2_SMP3_MASK (7 << ADC_SMPR2_SMP3_SHIFT) -#define ADC_SMPR2_SMP4_SHIFT (12) /* Bits 14-12: Channel 4 Sample time selection */ -#define ADC_SMPR2_SMP4_MASK (7 << ADC_SMPR2_SMP4_SHIFT) -#define ADC_SMPR2_SMP5_SHIFT (15) /* Bits 17-15: Channel 5 Sample time selection */ -#define ADC_SMPR2_SMP5_MASK (7 << ADC_SMPR2_SMP5_SHIFT) -#define ADC_SMPR2_SMP6_SHIFT (18) /* Bits 20-18: Channel 6 Sample time selection */ -#define ADC_SMPR2_SMP6_MASK (7 << ADC_SMPR2_SMP6_SHIFT) -#define ADC_SMPR2_SMP7_SHIFT (21) /* Bits 23-21: Channel 7 Sample time selection */ -#define ADC_SMPR2_SMP7_MASK (7 << ADC_SMPR2_SMP7_SHIFT) -#define ADC_SMPR2_SMP8_SHIFT (24) /* Bits 26-24: Channel 8 Sample time selection */ -#define ADC_SMPR2_SMP8_MASK (7 << ADC_SMPR2_SMP8_SHIFT) -#define ADC_SMPR2_SMP9_SHIFT (27) /* Bits 29-27: Channel 9 Sample time selection */ -#define ADC_SMPR2_SMP9_MASK (7 << ADC_SMPR2_SMP9_SHIFT) - - -/* ADC injected channel data offset register 1-4 */ - -#define ADC_JOFR_SHIFT (0) /* Bits 11-0: Data offset for injected channel x */ -#define ADC_JOFR_MASK (0x0fff << ADC_JOFR_SHIFT) - -/* ADC watchdog high threshold register */ - -#define ADC_HTR_SHIFT (0) /* Bits 11-0: Analog watchdog high threshold */ -#define ADC_HTR_MASK (0x0fff << ADC_HTR_SHIFT) - -/* ADC watchdog low threshold register */ - -#define ADC_LTR_SHIFT (0) /* Bits 11-0: Analog watchdog low threshold */ -#define ADC_LTR_MASK (0x0fff << ADC_LTR_SHIFT) - -/* ADC regular sequence register 1 */ - -#define ADC_SQR1_SQ13_SHIFT (0) /* Bits 4-0: 13th conversion in regular sequence */ -#define ADC_SQR1_SQ13_MASK (0x1f << ADC_SQR1_SQ13_SHIFT) -#define ADC_SQR1_SQ14_SHIFT (5) /* Bits 9-5: 14th conversion in regular sequence */ -#define ADC_SQR1_SQ14_MASK (0x1f << ADC_SQR1_SQ14_SHIFT) -#define ADC_SQR1_SQ15_SHIFT (10) /* Bits 14-10: 15th conversion in regular sequence */ -#define ADC_SQR1_SQ15_MASK (0x1f << ADC_SQR1_SQ15_SHIFT) -#define ADC_SQR1_SQ16_SHIFT (15) /* Bits 19-15: 16th conversion in regular sequence */ -#define ADC_SQR1_SQ16_MASK (0x1f << ADC_SQR1_SQ16_SHIFT) -#define ADC_SQR1_L_SHIFT (20) /* Bits 23-20: Regular channel sequence length */ -#define ADC_SQR1_L_MASK (0x0f << ADC_SQR1_L_SHIFT) -#define ADC_SQR1_RESERVED (0xff000000) -#define ADC_SQR1_FIRST (13) -#define ADC_SQR1_LAST (16) -#define ADC_SQR1_SQ_OFFSET (0) - -/* ADC regular sequence register 2 */ - -#define ADC_SQR2_SQ7_SHIFT (0) /* Bits 4-0: 7th conversion in regular sequence */ -#define ADC_SQR2_SQ7_MASK (0x1f << ADC_SQR2_SQ7_SHIFT) -#define ADC_SQR2_SQ8_SHIFT (5) /* Bits 9-5: 8th conversion in regular sequence */ -#define ADC_SQR2_SQ8_MASK (0x1f << ADC_SQR2_SQ8_SHIFT) -#define ADC_SQR2_SQ9_SHIFT (10) /* Bits 14-10: 9th conversion in regular sequence */ -#define ADC_SQR2_SQ9_MASK (0x1f << ADC_SQR2_SQ9_SHIFT) -#define ADC_SQR2_SQ10_SHIFT (15) /* Bits 19-15: 10th conversion in regular sequence */ -#define ADC_SQR2_SQ10_MASK (0x1f << ADC_SQR2_SQ10_SHIFT) -#define ADC_SQR2_SQ11_SHIFT (20) /* Bits 24-20: 11th conversion in regular sequence */ -#define ADC_SQR2_SQ11_MASK (0x1f << ADC_SQR2_SQ11_SHIFT ) -#define ADC_SQR2_SQ12_SHIFT (25) /* Bits 29-25: 12th conversion in regular sequence */ -#define ADC_SQR2_SQ12_MASK (0x1f << ADC_SQR2_SQ12_SHIFT) -#define ADC_SQR2_RESERVED (0xc0000000) -#define ADC_SQR2_FIRST (7) -#define ADC_SQR2_LAST (12) -#define ADC_SQR2_SQ_OFFSET (0) - -/* ADC regular sequence register 3 */ - -#define ADC_SQR3_SQ1_SHIFT (0) /* Bits 4-0: 1st conversion in regular sequence */ -#define ADC_SQR3_SQ1_MASK (0x1f << ADC_SQR3_SQ1_SHIFT) -#define ADC_SQR3_SQ2_SHIFT (5) /* Bits 9-5: 2nd conversion in regular sequence */ -#define ADC_SQR3_SQ2_MASK (0x1f << ADC_SQR3_SQ2_SHIFT) -#define ADC_SQR3_SQ3_SHIFT (10) /* Bits 14-10: 3rd conversion in regular sequence */ -#define ADC_SQR3_SQ3_MASK (0x1f << ADC_SQR3_SQ3_SHIFT) -#define ADC_SQR3_SQ4_SHIFT (15) /* Bits 19-15: 4th conversion in regular sequence */ -#define ADC_SQR3_SQ4_MASK (0x1f << ADC_SQR3_SQ4_SHIFT) -#define ADC_SQR3_SQ5_SHIFT (20) /* Bits 24-20: 5th conversion in regular sequence */ -#define ADC_SQR3_SQ5_MASK (0x1f << ADC_SQR3_SQ5_SHIFT ) -#define ADC_SQR3_SQ6_SHIFT (25) /* Bits 29-25: 6th conversion in regular sequence */ -#define ADC_SQR3_SQ6_MASK (0x1f << ADC_SQR3_SQ6_SHIFT) -#define ADC_SQR3_RESERVED (0xc0000000) -#define ADC_SQR3_FIRST (1) -#define ADC_SQR3_LAST (6) -#define ADC_SQR3_SQ_OFFSET (0) - -/* Offset between SQ bits */ - -#define ADC_SQ_OFFSET (5) - -/* ADC injected sequence register */ - -#define ADC_JSQR_JSQ1_SHIFT (0) /* Bits 4-0: 1st conversion in injected sequence */ -#define ADC_JSQR_JSQ1_MASK (0x1f << ADC_JSQR_JSQ1_SHIFT) -#define ADC_JSQR_JSQ2_SHIFT (5) /* Bits 9-5: 2nd conversion in injected sequence */ -#define ADC_JSQR_JSQ2_MASK (0x1f << ADC_JSQR_JSQ2_SHIFT) -#define ADC_JSQR_JSQ3_SHIFT (10) /* Bits 14-10: 3rd conversion in injected sequence */ -#define ADC_JSQR_JSQ3_MASK (0x1f << ADC_JSQR_JSQ3_SHIFT) -#define ADC_JSQR_JSQ4_SHIFT (15) /* Bits 19-15: 4th conversion in injected sequence */ -#define ADC_JSQR_JSQ4_MASK (0x1f << ADC_JSQR_JSQ4_SHIFT) -#define ADC_JSQR_JL_SHIFT (20) /* Bits 21-20: Injected Sequence length */ -#define ADC_JSQR_JL_MASK (3 << ADC_JSQR_JL_SHIFT) - -/* ADC injected data register 1-4 */ - -#define ADC_JDR_JDATA_SHIFT (0) /* Bits 15-0: Injected data */ -#define ADC_JDR_JDATA_MASK (0xffff << ADC_JDR_JDATA_SHIFT) - -/* ADC regular data register */ - -#define ADC_DR_RDATA_SHIFT (0) /* Bits 15-0 Regular data */ -#define ADC_DR_RDATA_MASK (0xffff << ADC_DR_RDATA_SHIFT) - -/* Common status register */ - -#define ADC_CSR_AWD1 (1 << 0) /* Bit 0: Analog watchdog flag of ADC1 (copy of AWD in ADC1_SR) */ -#define ADC_CSR_EOC1 (1 << 1) /* Bit 1: End of conversion of ADC1 (copy of EOC in ADC1_SR) */ -#define ADC_CSR_JEOC1 (1 << 2) /* Bit 2: Injected channel end of conversion of ADC1 (copy of JEOC in ADC1_SR) */ -#define ADC_CSR_JSTRT1 (1 << 3) /* Bit 3: Injected channel Start flag of ADC1 (copy of JSTRT in ADC1_SR) */ -#define ADC_CSR_STRT1 (1 << 4) /* Bit 4: Regular channel Start flag of ADC1 (copy of STRT in ADC1_SR) */ -#define ADC_CSR_OVR1 (1 << 5) /* Bit 5: Overrun flag of ADC1 (copy of OVR in ADC1_SR) */ - -#define ADC_CSR_AWD2 (1 << 8) /* Bit 8: Analog watchdog flag of ADC2 (copy of AWD in ADC2_SR) */ -#define ADC_CSR_EOC2 (1 << 9) /* Bit 9: End of conversion of ADC2 (copy of EOC in ADC2_SR) */ -#define ADC_CSR_JEOC2 (1 << 10) /* Bit 10: Injected channel end of conversion of ADC2 (copy of JEOC in ADC2_SR) */ -#define ADC_CSR_JSTRT2 (1 << 11) /* Bit 11: Injected channel Start flag of ADC2 (copy of JSTRT in ADC2_SR) */ -#define ADC_CSR_STRT2 (1 << 12) /* Bit 12: Regular channel Start flag of ADC2 (copy of STRT in ADC2_SR) */ -#define ADC_CSR_OVR2 (1 << 13) /* Bit 13: Overrun flag of ADC2 (copy of OVR in ADC2_SR) */ - /* Bits 14-15: Reserved, must be kept at reset value. */ -#define ADC_CSR_AWD3 (1 << 16) /* Bit 16: ADC3 Analog watchdog flag (copy of AWD in ADC3_SR) */ -#define ADC_CSR_EOC3 (1 << 17) /* Bit 17: ADC3 End of conversion (copy of EOC in ADC3_SR) */ -#define ADC_CSR_JEOC3 (1 << 18) /* Bit 18: ADC3 Injected channel end of conversion (copy of JEOC in ADC3_SR) */ -#define ADC_CSR_JSTRT3 (1 << 19) /* Bit 19: ADC3 Injected channel Start flag (copy of JSTRT in ADC3_SR) */ -#define ADC_CSR_STRT3 (1 << 20) /* Bit 20: ADC3 Regular channel Start flag (copy of STRT in ADC3_SR). */ -#define ADC_CSR_OVR3 (1 << 21) /* Bit 21: ADC3 overrun flag (copy of OVR in ADC3_SR). */ - -/* Common control register */ - -# define ADC_CCR_MULTI_SHIFT (0) /* Bits 0-4: Multi ADC mode selection */ -# define ADC_CCR_MULTI_MASK (31 << ADC_CCR_MULTI_SHIFT) -# define ADC_CCR_MULTI_NONE (0 << ADC_CCR_MULTI_SHIFT) /* 00000: Independent mode */ - /* 00001 to 01001: Dual mode (ADC1 and ADC2), ADC3 independent */ -# define ADC_CCR_MULTI_RSISM2 (1 << ADC_CCR_MULTI_SHIFT) /* 00001: Combined regular simultaneous + injected simultaneous mode */ -# define ADC_CCR_MULTI_RSATM2 (2 << ADC_CCR_MULTI_SHIFT) /* 00010: Combined regular simultaneous + alternate trigger mode */ -# define ADC_CCR_MULTI_ISM2 (5 << ADC_CCR_MULTI_SHIFT) /* 00101: Injected simultaneous mode only */ -# define ADC_CCR_MULTI_RSM2 (6 << ADC_CCR_MULTI_SHIFT) /* 00110: Regular simultaneous mode only */ -# define ADC_CCR_MULTI_IM2 (7 << ADC_CCR_MULTI_SHIFT) /* 00111: interleaved mode only */ -# define ADC_CCR_MULTI_ATM2 (9 << ADC_CCR_MULTI_SHIFT) /* 01001: Alternate trigger mode only */ - /* 10001 to 11001: Triple mode (ADC1, 2 and 3) */ -# define ADC_CCR_MULTI_RSISM3 (17 << ADC_CCR_MULTI_SHIFT) /* 10001: Combined regular simultaneous + injected simultaneous mode */ -# define ADC_CCR_MULTI_RSATM3 (18 << ADC_CCR_MULTI_SHIFT) /* 10010: Combined regular simultaneous + alternate trigger mode */ -# define ADC_CCR_MULTI_ISM3 (21 << ADC_CCR_MULTI_SHIFT) /* 10101: Injected simultaneous mode only */ -# define ADC_CCR_MULTI_RSM3 (22 << ADC_CCR_MULTI_SHIFT) /* 10110: Regular simultaneous mode only */ -# define ADC_CCR_MULTI_IM3 (23 << ADC_CCR_MULTI_SHIFT) /* 10111: interleaved mode only */ -# define ADC_CCR_MULTI_ATM3 (25 << ADC_CCR_MULTI_SHIFT) /* 11001: Alternate trigger mode only */ - /* Bits 5-7: Reserved, must be kept at reset value. */ -# define ADC_CCR_DELAY_SHIFT (8) /* Bits 8-11: Delay between 2 sampling phases */ -# define ADC_CCR_DELAY_MASK (15 << ADC_CCR_DELAY_SHIFT) -# define ADC_CCR_DELAY(n) (((n)-5) << ADC_CCR_DELAY_SHIFT) /* n * TADCCLK, n=5-20 */ - /* Bit 12 Reserved, must be kept at reset value. */ -# define ADC_CCR_DDS (1 << 13) /* Bit 13: DMA disable selection (for multi-ADC mode) */ - -# define ADC_CCR_DMA_SHIFT (14) /* Bits 14-15: Direct memory access mode for multi ADC mode */ -# define ADC_CCR_DMA_MASK (3 << ADC_CCR_DMA_SHIFT) -# define ADC_CCR_DMA_DISABLED (0 << ADC_CCR_DMA_SHIFT) /* 00: DMA mode disabled */ -# define ADC_CCR_DMA_MODE1 (1 << ADC_CCR_DMA_SHIFT) /* 01: DMA mode 1 enabled */ -# define ADC_CCR_DMA_MODE2 (2 << ADC_CCR_DMA_SHIFT) /* 10: DMA mode 2 enabled */ -# define ADC_CCR_DMA_MODE3 (3 << ADC_CCR_DMA_SHIFT) /* 11: DMA mode 3 enabled */ - -# define ADC_CCR_ADCPRE_SHIFT (16) /* Bits 16-17: ADC prescaler */ -# define ADC_CCR_ADCPRE_MASK (3 << ADC_CCR_ADCPRE_SHIFT) -# define ADC_CCR_ADCPRE_DIV2 (0 << ADC_CCR_ADCPRE_SHIFT) /* 00: PCLK2 divided by 2 */ -# define ADC_CCR_ADCPRE_DIV4 (1 << ADC_CCR_ADCPRE_SHIFT) /* 01: PCLK2 divided by 4 */ -# define ADC_CCR_ADCPRE_DIV6 (2 << ADC_CCR_ADCPRE_SHIFT) /* 10: PCLK2 divided by 6 */ -# define ADC_CCR_ADCPRE_DIV8 (3 << ADC_CCR_ADCPRE_SHIFT) /* 11: PCLK2 divided by 8 */ - /* Bits 18-21: Reserved, must be kept at reset value. */ -# define ADC_CCR_VBATE (1 << 22) /* Bit 22: VBAT enable */ -# define ADC_CCR_TSVREFE (1 << 23) /* Bit 23: Temperature sensor and VREFINT enable */ - /* Bits 24-31 Reserved, must be kept at reset value. */ - -/* Data register for dual and triple modes (32-bit data with no named fields) */ - -/**************************************************************************************************** - * Public Types - ****************************************************************************************************/ - -/**************************************************************************************************** - * Public Data - ****************************************************************************************************/ - -/**************************************************************************************************** - * Public Function Prototypes - ****************************************************************************************************/ - -#endif /* __ARCH_ARM_SRC_STM32F_CHIP_STM32_ADC_H */ +#endif /* __ARCH_ARM_SRC_STM32F7_CHIP_STM32_ADC_H */ diff --git a/arch/arm/src/stm32f7/chip/stm32f74xx77xx_adc.h b/arch/arm/src/stm32f7/chip/stm32f74xx77xx_adc.h new file mode 100644 index 0000000000..bc79490798 --- /dev/null +++ b/arch/arm/src/stm32f7/chip/stm32f74xx77xx_adc.h @@ -0,0 +1,484 @@ +/**************************************************************************************************** + * arch/arm/src/stm32f7/chip/stm32f74xx77xx_adc.h + * + * Copyright (C) 2016 Gregory Nutt. All rights reserved. + * Authors: Gregory Nutt + * David Sidrane + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************************************/ + +#ifndef __ARCH_ARM_SRC_STM32F7_CHIP_STM32F74XX77XX_ADC_H +#define __ARCH_ARM_SRC_STM32F7_CHIP_STM32F74XX77XX_ADC_H + +/**************************************************************************************************** + * Included Files + ****************************************************************************************************/ + +#include + +#include "chip.h" + +/**************************************************************************************************** + * Pre-processor Definitions + ****************************************************************************************************/ + +/* Register Offsets *********************************************************************************/ + +#define STM32_ADC_SR_OFFSET 0x0000 /* ADC status register (32-bit) */ +#define STM32_ADC_CR1_OFFSET 0x0004 /* ADC control register 1 (32-bit) */ +#define STM32_ADC_CR2_OFFSET 0x0008 /* ADC control register 2 (32-bit) */ +#define STM32_ADC_SMPR1_OFFSET 0x000c /* ADC sample time register 1 (32-bit) */ +#define STM32_ADC_SMPR2_OFFSET 0x0010 /* ADC sample time register 2 (32-bit) */ +#define STM32_ADC_JOFR1_OFFSET 0x0014 /* ADC injected channel data offset register 1 (32-bit) */ +#define STM32_ADC_JOFR2_OFFSET 0x0018 /* ADC injected channel data offset register 2 (32-bit) */ +#define STM32_ADC_JOFR3_OFFSET 0x001c /* ADC injected channel data offset register 3 (32-bit) */ +#define STM32_ADC_JOFR4_OFFSET 0x0020 /* ADC injected channel data offset register 4 (32-bit) */ +#define STM32_ADC_HTR_OFFSET 0x0024 /* ADC watchdog high threshold register (32-bit) */ +#define STM32_ADC_LTR_OFFSET 0x0028 /* ADC watchdog low threshold register (32-bit) */ +#define STM32_ADC_SQR1_OFFSET 0x002c /* ADC regular sequence register 1 (32-bit) */ +#define STM32_ADC_SQR2_OFFSET 0x0030 /* ADC regular sequence register 2 (32-bit) */ +#define STM32_ADC_SQR3_OFFSET 0x0034 /* ADC regular sequence register 3 (32-bit) */ +#define STM32_ADC_JSQR_OFFSET 0x0038 /* ADC injected sequence register (32-bit) */ +#define STM32_ADC_JDR1_OFFSET 0x003c /* ADC injected data register 1 (32-bit) */ +#define STM32_ADC_JDR2_OFFSET 0x0040 /* ADC injected data register 1 (32-bit) */ +#define STM32_ADC_JDR3_OFFSET 0x0044 /* ADC injected data register 1 (32-bit) */ +#define STM32_ADC_JDR4_OFFSET 0x0048 /* ADC injected data register 1 (32-bit) */ +#define STM32_ADC_DR_OFFSET 0x004c /* ADC regular data register (32-bit) */ + + +#define STM32_ADC_CSR_OFFSET 0x0000 /* Common status register */ +#define STM32_ADC_CCR_OFFSET 0x0004 /* Common control register */ +#define STM32_ADC_CDR_OFFSET 0x0008 /* Data register for dual and triple modes */ + +/* Register Addresses *******************************************************************************/ + +#if STM32F7_NADC > 0 +# define STM32_ADC1_SR (STM32_ADC1_BASE+STM32_ADC_SR_OFFSET) +# define STM32_ADC1_CR1 (STM32_ADC1_BASE+STM32_ADC_CR1_OFFSET) +# define STM32_ADC1_CR2 (STM32_ADC1_BASE+STM32_ADC_CR2_OFFSET) +# define STM32_ADC1_SMPR1 (STM32_ADC1_BASE+STM32_ADC_SMPR1_OFFSET) +# define STM32_ADC1_SMPR2 (STM32_ADC1_BASE+STM32_ADC_SMPR2_OFFSET) +# define STM32_ADC1_JOFR1 (STM32_ADC1_BASE+STM32_ADC_JOFR1_OFFSET) +# define STM32_ADC1_JOFR2 (STM32_ADC1_BASE+STM32_ADC_JOFR2_OFFSET) +# define STM32_ADC1_JOFR3 (STM32_ADC1_BASE+STM32_ADC_JOFR3_OFFSET) +# define STM32_ADC1_JOFR4 (STM32_ADC1_BASE+STM32_ADC_JOFR4_OFFSET) +# define STM32_ADC1_HTR (STM32_ADC1_BASE+STM32_ADC_HTR_OFFSET) +# define STM32_ADC1_LTR (STM32_ADC1_BASE+STM32_ADC_LTR_OFFSET) +# define STM32_ADC1_SQR1 (STM32_ADC1_BASE+STM32_ADC_SQR1_OFFSET) +# define STM32_ADC1_SQR2 (STM32_ADC1_BASE+STM32_ADC_SQR2_OFFSET) +# define STM32_ADC1_SQR3 (STM32_ADC1_BASE+STM32_ADC_SQR3_OFFSET) +# define STM32_ADC1_JSQR (STM32_ADC1_BASE+STM32_ADC_JSQR_OFFSET) +# define STM32_ADC1_JDR1 (STM32_ADC1_BASE+STM32_ADC_JDR1_OFFSET) +# define STM32_ADC1_JDR2 (STM32_ADC1_BASE+STM32_ADC_JDR2_OFFSET) +# define STM32_ADC1_JDR3 (STM32_ADC1_BASE+STM32_ADC_JDR3_OFFSET) +# define STM32_ADC1_JDR4 (STM32_ADC1_BASE+STM32_ADC_JDR4_OFFSET) +# define STM32_ADC1_DR (STM32_ADC1_BASE+STM32_ADC_DR_OFFSET) +#endif + +#if STM32F7_NADC > 1 +# define STM32_ADC2_SR (STM32_ADC2_BASE+STM32_ADC_SR_OFFSET) +# define STM32_ADC2_CR1 (STM32_ADC2_BASE+STM32_ADC_CR1_OFFSET) +# define STM32_ADC2_CR2 (STM32_ADC2_BASE+STM32_ADC_CR2_OFFSET) +# define STM32_ADC2_SMPR1 (STM32_ADC2_BASE+STM32_ADC_SMPR1_OFFSET) +# define STM32_ADC2_SMPR2 (STM32_ADC2_BASE+STM32_ADC_SMPR2_OFFSET) +# define STM32_ADC2_JOFR1 (STM32_ADC2_BASE+STM32_ADC_JOFR1_OFFSET) +# define STM32_ADC2_JOFR2 (STM32_ADC2_BASE+STM32_ADC_JOFR2_OFFSET) +# define STM32_ADC2_JOFR3 (STM32_ADC2_BASE+STM32_ADC_JOFR3_OFFSET) +# define STM32_ADC2_JOFR4 (STM32_ADC2_BASE+STM32_ADC_JOFR4_OFFSET) +# define STM32_ADC2_HTR (STM32_ADC2_BASE+STM32_ADC_HTR_OFFSET) +# define STM32_ADC2_LTR (STM32_ADC2_BASE+STM32_ADC_LTR_OFFSET) +# define STM32_ADC2_SQR1 (STM32_ADC2_BASE+STM32_ADC_SQR1_OFFSET) +# define STM32_ADC2_SQR2 (STM32_ADC2_BASE+STM32_ADC_SQR2_OFFSET) +# define STM32_ADC2_SQR3 (STM32_ADC2_BASE+STM32_ADC_SQR3_OFFSET) +# define STM32_ADC2_JSQR (STM32_ADC2_BASE+STM32_ADC_JSQR_OFFSET) +# define STM32_ADC2_JDR1 (STM32_ADC2_BASE+STM32_ADC_JDR1_OFFSET) +# define STM32_ADC2_JDR2 (STM32_ADC2_BASE+STM32_ADC_JDR2_OFFSET) +# define STM32_ADC2_JDR3 (STM32_ADC2_BASE+STM32_ADC_JDR3_OFFSET) +# define STM32_ADC2_JDR4 (STM32_ADC2_BASE+STM32_ADC_JDR4_OFFSET) +# define STM32_ADC2_DR (STM32_ADC2_BASE+STM32_ADC_DR_OFFSET) +#endif + +#if STM32F7_NADC > 2 +# define STM32_ADC3_SR (STM32_ADC3_BASE+STM32_ADC_SR_OFFSET) +# define STM32_ADC3_CR1 (STM32_ADC3_BASE+STM32_ADC_CR1_OFFSET) +# define STM32_ADC3_CR2 (STM32_ADC3_BASE+STM32_ADC_CR2_OFFSET) +# define STM32_ADC3_SMPR1 (STM32_ADC3_BASE+STM32_ADC_SMPR1_OFFSET) +# define STM32_ADC3_SMPR2 (STM32_ADC3_BASE+STM32_ADC_SMPR2_OFFSET) +# define STM32_ADC3_JOFR1 (STM32_ADC3_BASE+STM32_ADC_JOFR1_OFFSET) +# define STM32_ADC3_JOFR2 (STM32_ADC3_BASE+STM32_ADC_JOFR2_OFFSET) +# define STM32_ADC3_JOFR3 (STM32_ADC3_BASE+STM32_ADC_JOFR3_OFFSET) +# define STM32_ADC3_JOFR4 (STM32_ADC3_BASE+STM32_ADC_JOFR4_OFFSET) +# define STM32_ADC3_HTR (STM32_ADC3_BASE+STM32_ADC_HTR_OFFSET) +# define STM32_ADC3_LTR (STM32_ADC3_BASE+STM32_ADC_LTR_OFFSET) +# define STM32_ADC3_SQR1 (STM32_ADC3_BASE+STM32_ADC_SQR1_OFFSET) +# define STM32_ADC3_SQR2 (STM32_ADC3_BASE+STM32_ADC_SQR2_OFFSET) +# define STM32_ADC3_SQR3 (STM32_ADC3_BASE+STM32_ADC_SQR3_OFFSET) +# define STM32_ADC3_JSQR (STM32_ADC3_BASE+STM32_ADC_JSQR_OFFSET) +# define STM32_ADC3_JDR1 (STM32_ADC3_BASE+STM32_ADC_JDR1_OFFSET) +# define STM32_ADC3_JDR2 (STM32_ADC3_BASE+STM32_ADC_JDR2_OFFSET) +# define STM32_ADC3_JDR3 (STM32_ADC3_BASE+STM32_ADC_JDR3_OFFSET) +# define STM32_ADC3_JDR4 (STM32_ADC3_BASE+STM32_ADC_JDR4_OFFSET) +# define STM32_ADC3_DR (STM32_ADC3_BASE+STM32_ADC_DR_OFFSET) +#endif + +#define STM32_ADC_CSR (STM32_ADCCMN_BASE+STM32_ADC_CSR_OFFSET) +#define STM32_ADC_CCR (STM32_ADCCMN_BASE+STM32_ADC_CCR_OFFSET) +#define STM32_ADC_CDR (STM32_ADCCMN_BASE+STM32_ADC_CDR_OFFSET) + +/* Register Bitfield Definitions ********************************************************************/ + +/* ADC status register */ + +#define ADC_SR_AWD (1 << 0) /* Bit 0 : Analog watchdog flag */ +#define ADC_SR_EOC (1 << 1) /* Bit 1 : End of conversion */ +#define ADC_SR_JEOC (1 << 2) /* Bit 2 : Injected channel end of conversion */ +#define ADC_SR_JSTRT (1 << 3) /* Bit 3 : Injected channel Start flag */ +#define ADC_SR_STRT (1 << 4) /* Bit 4 : Regular channel Start flag */ +#define ADC_SR_OVR (1 << 5) /* Bit 5 : Overrun */ + +/* ADC control register 1 */ + +#define ADC_CR1_AWDCH_SHIFT (0) /* Bits 4-0: Analog watchdog channel select bits */ +#define ADC_CR1_AWDCH_MASK (0x1f << ADC_CR1_AWDCH_SHIFT) +#define ADC_CR1_EOCIE (1 << 5) /* Bit 5: Interrupt enable for EOC */ +#define ADC_CR1_AWDIE (1 << 6) /* Bit 6: Analog Watchdog interrupt enable */ +#define ADC_CR1_JEOCIE (1 << 7) /* Bit 7: Interrupt enable for injected channels */ +#define ADC_CR1_SCAN (1 << 8) /* Bit 8: Scan mode */ +#define ADC_CR1_AWDSGL (1 << 9) /* Bit 9: Enable the watchdog on a single channel in scan mode */ +#define ADC_CR1_JAUTO (1 << 10) /* Bit 10: Automatic Injected Group conversion */ +#define ADC_CR1_DISCEN (1 << 11) /* Bit 11: Discontinuous mode on regular channels */ +#define ADC_CR1_JDISCEN (1 << 12) /* Bit 12: Discontinuous mode on injected channels */ +#define ADC_CR1_DISCNUM_SHIFT (13) /* Bits 15-13: Discontinuous mode channel count */ +#define ADC_CR1_DISCNUM_MASK (0x07 << ADC_CR1_DISCNUM_SHIFT) +#define ADC_CR1_JAWDEN (1 << 22) /* Bit 22: Analog watchdog enable on injected channels */ +#define ADC_CR1_AWDEN (1 << 23) /* Bit 23: Analog watchdog enable on regular channels */ +#define ADC_CR1_RES_SHIFT (24) /* Bits 24-25: Resolution */ +#define ADC_CR1_RES_MASK (3 << ADC_CR1_RES_SHIFT) +#define ADC_CR1_RES_12BIT (0 << ADC_CR1_RES_SHIFT) /* 15 ADCCLK cycles. For STM32L15XX: 12 ADCCLK cycles */ +#define ADC_CR1_RES_10BIT (1 << ADC_CR1_RES_SHIFT) /* 13 ADCCLK cycles. For STM32L15XX: 11 ADCCLK cycles */ +#define ADC_CR1_RES_8BIT (2 << ADC_CR1_RES_SHIFT) /* 11 ADCCLK cycles. For STM32L15XX: 9 ADCCLK cycles */ +#define ADC_CR1_RES_6BIT (3 << ADC_CR1_RES_SHIFT) /* 9 ADCCLK cycles. For STM32L15XX: 7 ADCCLK cycles */ +#define ADC_CR1_OVRIE (1 << 26) /* Bit 26: Overrun interrupt enable */ + +/* ADC control register 2 */ + +#define ADC_CR2_ADON (1 << 0) /* Bit 0: A/D Converter ON / OFF */ +#define ADC_CR2_CONT (1 << 1) /* Bit 1: Continuous Conversion */ +#define ADC_CR2_DMA (1 << 8) /* Bit 8: Direct Memory access mode */ +#define ADC_CR2_DDS (1 << 9) /* Bit 9: DMA disable selection (for single ADC mode) */ +#define ADC_CR2_EOCS (1 << 10) /* Bit 10: End of conversion selection */ +#define ADC_CR2_ALIGN (1 << 11) /* Bit 11: Data Alignment */ + /* Bits 12-15: Reserved */ +#define ADC_CR2_JEXTSEL_SHIFT (16) /* Bits 16-19: External event select for injected group */ +#define ADC_CR2_JEXTSEL_MASK (0x0f << ADC_CR2_JEXTSEL_SHIFT) +#define ADC_CR2_JEXTSEL_T1TRGO (0x00 << ADC_CR2_JEXTSEL_SHIFT) /* 0000: Timer 1 TRGO event */ +#define ADC_CR2_JEXTSEL_T1CC4 (0x01 << ADC_CR2_JEXTSEL_SHIFT) /* 0001: Timer 1 CC4 event */ +#define ADC_CR2_JEXTSEL_T2TRGO (0x02 << ADC_CR2_JEXTSEL_SHIFT) /* 0010: Timer 2 TRGO event */ +#define ADC_CR2_JEXTSEL_T2CC1 (0x03 << ADC_CR2_JEXTSEL_SHIFT) /* 0011: Timer 2 CC1 event */ +#define ADC_CR2_JEXTSEL_T3CC4 (0x04 << ADC_CR2_JEXTSEL_SHIFT) /* 0100: Timer 3 CC4 event */ +#define ADC_CR2_JEXTSEL_T4TRGO (0x05 << ADC_CR2_JEXTSEL_SHIFT) /* 0101: Timer 4 TRGO event */ + /* 0110: NA */ +#define ADC_CR2_JEXTSEL_T8CC4 (0x07 << ADC_CR2_JEXTSEL_SHIFT) /* 0111: Timer 8 CC4 event */ +#define ADC_CR2_JEXTSEL_T1TRGO2 (0x08 << ADC_CR2_JEXTSEL_SHIFT) /* 1000: Timer 1 TRGO2 event */ +#define ADC_CR2_JEXTSEL_T8TRGO (0x09 << ADC_CR2_JEXTSEL_SHIFT) /* 1001: Timer 8 TRGO event */ +#define ADC_CR2_JEXTSEL_T8TRGO2 (0x0a << ADC_CR2_JEXTSEL_SHIFT) /* 1010: Timer 8 TRGO2 event */ +#define ADC_CR2_JEXTSEL_T3CC3 (0x0b << ADC_CR2_JEXTSEL_SHIFT) /* 1011: Timer 3 CC3 event */ +#define ADC_CR2_JEXTSEL_T5TRGO (0x0c << ADC_CR2_JEXTSEL_SHIFT) /* 1100: Timer 5 TRGO event */ +#define ADC_CR2_JEXTSEL_T3CC1 (0x0d << ADC_CR2_JEXTSEL_SHIFT) /* 1101: Timer 3 CC1 event */ +#define ADC_CR2_JEXTSEL_T6TRGO (0x0e << ADC_CR2_JEXTSEL_SHIFT) /* 1110: Timer 6 TRGO event */ + /* 1111: Reserved */ +#define ADC_CR2_JEXTEN_SHIFT (20) /* Bits 20-21: External trigger enable for injected channels */ +#define ADC_CR2_JEXTEN_MASK (3 << ADC_CR2_JEXTEN_SHIFT) +#define ADC_CR2_JEXTEN_NONE (0 << ADC_CR2_JEXTEN_SHIFT) /* 00: Trigger detection disabled */ +#define ADC_CR2_JEXTEN_RISING (1 << ADC_CR2_JEXTEN_SHIFT) /* 01: Trigger detection on the rising edge */ +#define ADC_CR2_JEXTEN_FALLING (2 << ADC_CR2_JEXTEN_SHIFT) /* 10: Trigger detection on the falling edge */ +#define ADC_CR2_JEXTEN_BOTH (3 << ADC_CR2_JEXTEN_SHIFT) /* 11: Trigger detection on both the rising and falling edges */ +#define ADC_CR2_JSWSTART (1 << 22) /* Bit 22: Start Conversion of injected channels */ + /* Bit 23: Reserved, must be kept at reset value. */ +#define ADC_CR2_EXTSEL_SHIFT (24) /* Bits 24-27: External Event Select for regular group */ +#define ADC_CR2_EXTSEL_MASK (0x0f << ADC_CR2_EXTSEL_SHIFT) +#define ADC_CR2_EXTSEL_T1CC1 (0x0 << ADC_CR2_EXTSEL_SHIFT) /* 0000: Timer 1 CC1 event */ +#define ADC_CR2_EXTSEL_T1CC2 (0x01 << ADC_CR2_EXTSEL_SHIFT) /* 0001: Timer 1 CC2 event */ +#define ADC_CR2_EXTSEL_T1CC3 (0x02 << ADC_CR2_EXTSEL_SHIFT) /* 0010: Timer 1 CC3 event */ +#define ADC_CR2_EXTSEL_T2CC2 (0x03 << ADC_CR2_EXTSEL_SHIFT) /* 0011: Timer 2 CC2 event */ +#define ADC_CR2_EXTSEL_T5TRGO (0x04 << ADC_CR2_EXTSEL_SHIFT) /* 0100: Timer 5 TRGO event */ +#define ADC_CR2_EXTSEL_T4CC4 (0x05 << ADC_CR2_EXTSEL_SHIFT) /* 0101: Timer 4 CC4 event */ +#define ADC_CR2_EXTSEL_T3CC4 (0x06 << ADC_CR2_EXTSEL_SHIFT) /* 0110: Timer 3 CC4 event */ +#define ADC_CR2_EXTSEL_T8TRGO (0x07 << ADC_CR2_EXTSEL_SHIFT) /* 0111: Timer 8 TRGO event */ +#define ADC_CR2_EXTSEL_T8TRGO2 (0x08 << ADC_CR2_EXTSEL_SHIFT) /* 1000: Timer 8 TRGO2 event */ +#define ADC_CR2_EXTSEL_T1TRGO (0x09 << ADC_CR2_EXTSEL_SHIFT) /* 1001: Timer 1 TRGO event */ +#define ADC_CR2_EXTSEL_T1TRGO2 (0x0a << ADC_CR2_EXTSEL_SHIFT) /* 1010: Timer 1 TRGO2 event */ +#define ADC_CR2_EXTSEL_T2TRGO (0x0b << ADC_CR2_EXTSEL_SHIFT) /* 1011: Timer 2 TRGO event */ +#define ADC_CR2_EXTSEL_T4TRGO (0x0c << ADC_CR2_EXTSEL_SHIFT) /* 1100: Timer 4 TRGO event */ +#define ADC_CR2_EXTSEL_T6TRGO (0x0d << ADC_CR2_EXTSEL_SHIFT) /* 1101: Timer 6 TRGO event */ + /* 1110: NA */ +#define ADC_CR2_EXTSEL_EXTI11 (0x0f << ADC_CR2_EXTSEL_SHIFT) /* 1111: EXTI line 11 */ +#define ADC_CR2_EXTEN_SHIFT (28) /* Bits 28-29: External trigger enable for regular channels */ +#define ADC_CR2_EXTEN_MASK (3 << ADC_CR2_EXTEN_SHIFT) +#define ADC_CR2_EXTEN_NONE (0 << ADC_CR2_EXTEN_SHIFT) /* 00: Trigger detection disabled */ +#define ADC_CR2_EXTEN_RISING (1 << ADC_CR2_EXTEN_SHIFT) /* 01: Trigger detection on the rising edge */ +#define ADC_CR2_EXTEN_FALLING (2 << ADC_CR2_EXTEN_SHIFT) /* 10: Trigger detection on the falling edge */ +#define ADC_CR2_EXTEN_BOTH (3 << ADC_CR2_EXTEN_SHIFT) /* 11: Trigger detection on both the rising and falling edges */ + +# define ADC_CR2_SWSTART (1 << 30) /* Bit 30: Start Conversion of regular channels */ + +/* ADC sample time register 1 */ + +#define ADC_SMPR_3 0 /* 000: 3 cycles */ +#define ADC_SMPR_15 1 /* 001: 15 cycles */ +#define ADC_SMPR_28 2 /* 010: 28 cycles */ +#define ADC_SMPR_56 3 /* 011: 56 cycles */ +#define ADC_SMPR_84 4 /* 100: 84 cycles */ +#define ADC_SMPR_112 5 /* 101: 112 cycles */ +#define ADC_SMPR_144 6 /* 110: 144 cycles */ +#define ADC_SMPR_480 7 /* 111: 480 cycles */ +#define ADC_SMPR1_SMP10_SHIFT (0) /* Bits 0-2: Channel 10 Sample time selection */ +#define ADC_SMPR1_SMP10_MASK (7 << ADC_SMPR1_SMP10_SHIFT) +#define ADC_SMPR1_SMP11_SHIFT (3) /* Bits 3-5: Channel 11 Sample time selection */ +#define ADC_SMPR1_SMP11_MASK (7 << ADC_SMPR1_SMP11_SHIFT) +#define ADC_SMPR1_SMP12_SHIFT (6) /* Bits 6-8: Channel 12 Sample time selection */ +#define ADC_SMPR1_SMP12_MASK (7 << ADC_SMPR1_SMP12_SHIFT) +#define ADC_SMPR1_SMP13_SHIFT (9) /* Bits 9-11: Channel 13 Sample time selection */ +#define ADC_SMPR1_SMP13_MASK (7 << ADC_SMPR1_SMP13_SHIFT) +#define ADC_SMPR1_SMP14_SHIFT (12) /* Bits 12-14: Channel 14 Sample time selection */ +#define ADC_SMPR1_SMP14_MASK (7 << ADC_SMPR1_SMP14_SHIFT) +#define ADC_SMPR1_SMP15_SHIFT (15) /* Bits 15-17: Channel 15 Sample time selection */ +#define ADC_SMPR1_SMP15_MASK (7 << ADC_SMPR1_SMP15_SHIFT) +#define ADC_SMPR1_SMP16_SHIFT (18) /* Bits 18-20: Channel 16 Sample time selection */ +#define ADC_SMPR1_SMP16_MASK (7 << ADC_SMPR1_SMP16_SHIFT) +#define ADC_SMPR1_SMP17_SHIFT (21) /* Bits 21-23: Channel 17 Sample time selection */ +#define ADC_SMPR1_SMP17_MASK (7 << ADC_SMPR1_SMP17_SHIFT) +#define ADC_SMPR1_SMP18_SHIFT (24) /* Bits 24-26: Channel 18 Sample time selection */ +#define ADC_SMPR1_SMP18_MASK (7 << ADC_SMPR1_SMP17_SHIFT) + + +/* ADC sample time register 2 */ + +#define ADC_SMPR2_SMP0_SHIFT (0) /* Bits 2-0: Channel 0 Sample time selection */ +#define ADC_SMPR2_SMP0_MASK (7 << ADC_SMPR2_SMP0_SHIFT) +#define ADC_SMPR2_SMP1_SHIFT (3) /* Bits 5-3: Channel 1 Sample time selection */ +#define ADC_SMPR2_SMP1_MASK (7 << ADC_SMPR2_SMP1_SHIFT) +#define ADC_SMPR2_SMP2_SHIFT (6) /* Bits 8-6: Channel 2 Sample time selection */ +#define ADC_SMPR2_SMP2_MASK (7 << ADC_SMPR2_SMP2_SHIFT) +#define ADC_SMPR2_SMP3_SHIFT (9) /* Bits 11-9: Channel 3 Sample time selection */ +#define ADC_SMPR2_SMP3_MASK (7 << ADC_SMPR2_SMP3_SHIFT) +#define ADC_SMPR2_SMP4_SHIFT (12) /* Bits 14-12: Channel 4 Sample time selection */ +#define ADC_SMPR2_SMP4_MASK (7 << ADC_SMPR2_SMP4_SHIFT) +#define ADC_SMPR2_SMP5_SHIFT (15) /* Bits 17-15: Channel 5 Sample time selection */ +#define ADC_SMPR2_SMP5_MASK (7 << ADC_SMPR2_SMP5_SHIFT) +#define ADC_SMPR2_SMP6_SHIFT (18) /* Bits 20-18: Channel 6 Sample time selection */ +#define ADC_SMPR2_SMP6_MASK (7 << ADC_SMPR2_SMP6_SHIFT) +#define ADC_SMPR2_SMP7_SHIFT (21) /* Bits 23-21: Channel 7 Sample time selection */ +#define ADC_SMPR2_SMP7_MASK (7 << ADC_SMPR2_SMP7_SHIFT) +#define ADC_SMPR2_SMP8_SHIFT (24) /* Bits 26-24: Channel 8 Sample time selection */ +#define ADC_SMPR2_SMP8_MASK (7 << ADC_SMPR2_SMP8_SHIFT) +#define ADC_SMPR2_SMP9_SHIFT (27) /* Bits 29-27: Channel 9 Sample time selection */ +#define ADC_SMPR2_SMP9_MASK (7 << ADC_SMPR2_SMP9_SHIFT) + + +/* ADC injected channel data offset register 1-4 */ + +#define ADC_JOFR_SHIFT (0) /* Bits 11-0: Data offset for injected channel x */ +#define ADC_JOFR_MASK (0x0fff << ADC_JOFR_SHIFT) + +/* ADC watchdog high threshold register */ + +#define ADC_HTR_SHIFT (0) /* Bits 11-0: Analog watchdog high threshold */ +#define ADC_HTR_MASK (0x0fff << ADC_HTR_SHIFT) + +/* ADC watchdog low threshold register */ + +#define ADC_LTR_SHIFT (0) /* Bits 11-0: Analog watchdog low threshold */ +#define ADC_LTR_MASK (0x0fff << ADC_LTR_SHIFT) + +/* ADC regular sequence register 1 */ + +#define ADC_SQR1_SQ13_SHIFT (0) /* Bits 4-0: 13th conversion in regular sequence */ +#define ADC_SQR1_SQ13_MASK (0x1f << ADC_SQR1_SQ13_SHIFT) +#define ADC_SQR1_SQ14_SHIFT (5) /* Bits 9-5: 14th conversion in regular sequence */ +#define ADC_SQR1_SQ14_MASK (0x1f << ADC_SQR1_SQ14_SHIFT) +#define ADC_SQR1_SQ15_SHIFT (10) /* Bits 14-10: 15th conversion in regular sequence */ +#define ADC_SQR1_SQ15_MASK (0x1f << ADC_SQR1_SQ15_SHIFT) +#define ADC_SQR1_SQ16_SHIFT (15) /* Bits 19-15: 16th conversion in regular sequence */ +#define ADC_SQR1_SQ16_MASK (0x1f << ADC_SQR1_SQ16_SHIFT) +#define ADC_SQR1_L_SHIFT (20) /* Bits 23-20: Regular channel sequence length */ +#define ADC_SQR1_L_MASK (0x0f << ADC_SQR1_L_SHIFT) +#define ADC_SQR1_RESERVED (0xff000000) +#define ADC_SQR1_FIRST (13) +#define ADC_SQR1_LAST (16) +#define ADC_SQR1_SQ_OFFSET (0) + +/* ADC regular sequence register 2 */ + +#define ADC_SQR2_SQ7_SHIFT (0) /* Bits 4-0: 7th conversion in regular sequence */ +#define ADC_SQR2_SQ7_MASK (0x1f << ADC_SQR2_SQ7_SHIFT) +#define ADC_SQR2_SQ8_SHIFT (5) /* Bits 9-5: 8th conversion in regular sequence */ +#define ADC_SQR2_SQ8_MASK (0x1f << ADC_SQR2_SQ8_SHIFT) +#define ADC_SQR2_SQ9_SHIFT (10) /* Bits 14-10: 9th conversion in regular sequence */ +#define ADC_SQR2_SQ9_MASK (0x1f << ADC_SQR2_SQ9_SHIFT) +#define ADC_SQR2_SQ10_SHIFT (15) /* Bits 19-15: 10th conversion in regular sequence */ +#define ADC_SQR2_SQ10_MASK (0x1f << ADC_SQR2_SQ10_SHIFT) +#define ADC_SQR2_SQ11_SHIFT (20) /* Bits 24-20: 11th conversion in regular sequence */ +#define ADC_SQR2_SQ11_MASK (0x1f << ADC_SQR2_SQ11_SHIFT ) +#define ADC_SQR2_SQ12_SHIFT (25) /* Bits 29-25: 12th conversion in regular sequence */ +#define ADC_SQR2_SQ12_MASK (0x1f << ADC_SQR2_SQ12_SHIFT) +#define ADC_SQR2_RESERVED (0xc0000000) +#define ADC_SQR2_FIRST (7) +#define ADC_SQR2_LAST (12) +#define ADC_SQR2_SQ_OFFSET (0) + +/* ADC regular sequence register 3 */ + +#define ADC_SQR3_SQ1_SHIFT (0) /* Bits 4-0: 1st conversion in regular sequence */ +#define ADC_SQR3_SQ1_MASK (0x1f << ADC_SQR3_SQ1_SHIFT) +#define ADC_SQR3_SQ2_SHIFT (5) /* Bits 9-5: 2nd conversion in regular sequence */ +#define ADC_SQR3_SQ2_MASK (0x1f << ADC_SQR3_SQ2_SHIFT) +#define ADC_SQR3_SQ3_SHIFT (10) /* Bits 14-10: 3rd conversion in regular sequence */ +#define ADC_SQR3_SQ3_MASK (0x1f << ADC_SQR3_SQ3_SHIFT) +#define ADC_SQR3_SQ4_SHIFT (15) /* Bits 19-15: 4th conversion in regular sequence */ +#define ADC_SQR3_SQ4_MASK (0x1f << ADC_SQR3_SQ4_SHIFT) +#define ADC_SQR3_SQ5_SHIFT (20) /* Bits 24-20: 5th conversion in regular sequence */ +#define ADC_SQR3_SQ5_MASK (0x1f << ADC_SQR3_SQ5_SHIFT ) +#define ADC_SQR3_SQ6_SHIFT (25) /* Bits 29-25: 6th conversion in regular sequence */ +#define ADC_SQR3_SQ6_MASK (0x1f << ADC_SQR3_SQ6_SHIFT) +#define ADC_SQR3_RESERVED (0xc0000000) +#define ADC_SQR3_FIRST (1) +#define ADC_SQR3_LAST (6) +#define ADC_SQR3_SQ_OFFSET (0) + +/* Offset between SQ bits */ + +#define ADC_SQ_OFFSET (5) + +/* ADC injected sequence register */ + +#define ADC_JSQR_JSQ1_SHIFT (0) /* Bits 4-0: 1st conversion in injected sequence */ +#define ADC_JSQR_JSQ1_MASK (0x1f << ADC_JSQR_JSQ1_SHIFT) +#define ADC_JSQR_JSQ2_SHIFT (5) /* Bits 9-5: 2nd conversion in injected sequence */ +#define ADC_JSQR_JSQ2_MASK (0x1f << ADC_JSQR_JSQ2_SHIFT) +#define ADC_JSQR_JSQ3_SHIFT (10) /* Bits 14-10: 3rd conversion in injected sequence */ +#define ADC_JSQR_JSQ3_MASK (0x1f << ADC_JSQR_JSQ3_SHIFT) +#define ADC_JSQR_JSQ4_SHIFT (15) /* Bits 19-15: 4th conversion in injected sequence */ +#define ADC_JSQR_JSQ4_MASK (0x1f << ADC_JSQR_JSQ4_SHIFT) +#define ADC_JSQR_JL_SHIFT (20) /* Bits 21-20: Injected Sequence length */ +#define ADC_JSQR_JL_MASK (3 << ADC_JSQR_JL_SHIFT) + +/* ADC injected data register 1-4 */ + +#define ADC_JDR_JDATA_SHIFT (0) /* Bits 15-0: Injected data */ +#define ADC_JDR_JDATA_MASK (0xffff << ADC_JDR_JDATA_SHIFT) + +/* ADC regular data register */ + +#define ADC_DR_RDATA_SHIFT (0) /* Bits 15-0 Regular data */ +#define ADC_DR_RDATA_MASK (0xffff << ADC_DR_RDATA_SHIFT) + +/* Common status register */ + +#define ADC_CSR_AWD1 (1 << 0) /* Bit 0: Analog watchdog flag of ADC1 (copy of AWD in ADC1_SR) */ +#define ADC_CSR_EOC1 (1 << 1) /* Bit 1: End of conversion of ADC1 (copy of EOC in ADC1_SR) */ +#define ADC_CSR_JEOC1 (1 << 2) /* Bit 2: Injected channel end of conversion of ADC1 (copy of JEOC in ADC1_SR) */ +#define ADC_CSR_JSTRT1 (1 << 3) /* Bit 3: Injected channel Start flag of ADC1 (copy of JSTRT in ADC1_SR) */ +#define ADC_CSR_STRT1 (1 << 4) /* Bit 4: Regular channel Start flag of ADC1 (copy of STRT in ADC1_SR) */ +#define ADC_CSR_OVR1 (1 << 5) /* Bit 5: Overrun flag of ADC1 (copy of OVR in ADC1_SR) */ + +#define ADC_CSR_AWD2 (1 << 8) /* Bit 8: Analog watchdog flag of ADC2 (copy of AWD in ADC2_SR) */ +#define ADC_CSR_EOC2 (1 << 9) /* Bit 9: End of conversion of ADC2 (copy of EOC in ADC2_SR) */ +#define ADC_CSR_JEOC2 (1 << 10) /* Bit 10: Injected channel end of conversion of ADC2 (copy of JEOC in ADC2_SR) */ +#define ADC_CSR_JSTRT2 (1 << 11) /* Bit 11: Injected channel Start flag of ADC2 (copy of JSTRT in ADC2_SR) */ +#define ADC_CSR_STRT2 (1 << 12) /* Bit 12: Regular channel Start flag of ADC2 (copy of STRT in ADC2_SR) */ +#define ADC_CSR_OVR2 (1 << 13) /* Bit 13: Overrun flag of ADC2 (copy of OVR in ADC2_SR) */ + /* Bits 14-15: Reserved, must be kept at reset value. */ +#define ADC_CSR_AWD3 (1 << 16) /* Bit 16: ADC3 Analog watchdog flag (copy of AWD in ADC3_SR) */ +#define ADC_CSR_EOC3 (1 << 17) /* Bit 17: ADC3 End of conversion (copy of EOC in ADC3_SR) */ +#define ADC_CSR_JEOC3 (1 << 18) /* Bit 18: ADC3 Injected channel end of conversion (copy of JEOC in ADC3_SR) */ +#define ADC_CSR_JSTRT3 (1 << 19) /* Bit 19: ADC3 Injected channel Start flag (copy of JSTRT in ADC3_SR) */ +#define ADC_CSR_STRT3 (1 << 20) /* Bit 20: ADC3 Regular channel Start flag (copy of STRT in ADC3_SR). */ +#define ADC_CSR_OVR3 (1 << 21) /* Bit 21: ADC3 overrun flag (copy of OVR in ADC3_SR). */ + +/* Common control register */ + +# define ADC_CCR_MULTI_SHIFT (0) /* Bits 0-4: Multi ADC mode selection */ +# define ADC_CCR_MULTI_MASK (0x1f << ADC_CCR_MULTI_SHIFT) +# define ADC_CCR_MULTI_NONE (0 << ADC_CCR_MULTI_SHIFT) /* 00000: Independent mode */ + /* 00001 to 01001: Dual mode (ADC1 and ADC2), ADC3 independent */ +# define ADC_CCR_MULTI_RSISM2 (1 << ADC_CCR_MULTI_SHIFT) /* 00001: Combined regular simultaneous + injected simultaneous mode */ +# define ADC_CCR_MULTI_RSATM2 (2 << ADC_CCR_MULTI_SHIFT) /* 00010: Combined regular simultaneous + alternate trigger mode */ +# define ADC_CCR_MULTI_ISM2 (5 << ADC_CCR_MULTI_SHIFT) /* 00101: Injected simultaneous mode only */ +# define ADC_CCR_MULTI_RSM2 (6 << ADC_CCR_MULTI_SHIFT) /* 00110: Regular simultaneous mode only */ +# define ADC_CCR_MULTI_IM2 (7 << ADC_CCR_MULTI_SHIFT) /* 00111: interleaved mode only */ +# define ADC_CCR_MULTI_ATM2 (9 << ADC_CCR_MULTI_SHIFT) /* 01001: Alternate trigger mode only */ + /* 10001 to 11001: Triple mode (ADC1, 2 and 3) */ +# define ADC_CCR_MULTI_RSISM3 (17 << ADC_CCR_MULTI_SHIFT) /* 10001: Combined regular simultaneous + injected simultaneous mode */ +# define ADC_CCR_MULTI_RSATM3 (18 << ADC_CCR_MULTI_SHIFT) /* 10010: Combined regular simultaneous + alternate trigger mode */ +# define ADC_CCR_MULTI_ISM3 (21 << ADC_CCR_MULTI_SHIFT) /* 10101: Injected simultaneous mode only */ +# define ADC_CCR_MULTI_RSM3 (22 << ADC_CCR_MULTI_SHIFT) /* 10110: Regular simultaneous mode only */ +# define ADC_CCR_MULTI_IM3 (23 << ADC_CCR_MULTI_SHIFT) /* 10111: interleaved mode only */ +# define ADC_CCR_MULTI_ATM3 (25 << ADC_CCR_MULTI_SHIFT) /* 11001: Alternate trigger mode only */ + /* Bits 5-7: Reserved, must be kept at reset value. */ +# define ADC_CCR_DELAY_SHIFT (8) /* Bits 8-11: Delay between 2 sampling phases */ +# define ADC_CCR_DELAY_MASK (0xf << ADC_CCR_DELAY_SHIFT) +# define ADC_CCR_DELAY(n) (((n)-5) << ADC_CCR_DELAY_SHIFT) /* n * TADCCLK, n=5-20 */ + /* Bit 12 Reserved, must be kept at reset value. */ +# define ADC_CCR_DDS (1 << 13) /* Bit 13: DMA disable selection (for multi-ADC mode) */ + +# define ADC_CCR_DMA_SHIFT (14) /* Bits 14-15: Direct memory access mode for multi ADC mode */ +# define ADC_CCR_DMA_MASK (3 << ADC_CCR_DMA_SHIFT) +# define ADC_CCR_DMA_DISABLED (0 << ADC_CCR_DMA_SHIFT) /* 00: DMA mode disabled */ +# define ADC_CCR_DMA_MODE1 (1 << ADC_CCR_DMA_SHIFT) /* 01: DMA mode 1 enabled */ +# define ADC_CCR_DMA_MODE2 (2 << ADC_CCR_DMA_SHIFT) /* 10: DMA mode 2 enabled */ +# define ADC_CCR_DMA_MODE3 (3 << ADC_CCR_DMA_SHIFT) /* 11: DMA mode 3 enabled */ + +# define ADC_CCR_ADCPRE_SHIFT (16) /* Bits 16-17: ADC prescaler */ +# define ADC_CCR_ADCPRE_MASK (3 << ADC_CCR_ADCPRE_SHIFT) +# define ADC_CCR_ADCPRE_DIV2 (0 << ADC_CCR_ADCPRE_SHIFT) /* 00: PCLK2 divided by 2 */ +# define ADC_CCR_ADCPRE_DIV4 (1 << ADC_CCR_ADCPRE_SHIFT) /* 01: PCLK2 divided by 4 */ +# define ADC_CCR_ADCPRE_DIV6 (2 << ADC_CCR_ADCPRE_SHIFT) /* 10: PCLK2 divided by 6 */ +# define ADC_CCR_ADCPRE_DIV8 (3 << ADC_CCR_ADCPRE_SHIFT) /* 11: PCLK2 divided by 8 */ + /* Bits 18-21: Reserved, must be kept at reset value. */ +# define ADC_CCR_VBATE (1 << 22) /* Bit 22: VBAT enable */ +# define ADC_CCR_TSVREFE (1 << 23) /* Bit 23: Temperature sensor and VREFINT enable */ + /* Bits 24-31 Reserved, must be kept at reset value. */ + +/* Data register for dual and triple modes (32-bit data with no named fields) */ + +/**************************************************************************************************** + * Public Types + ****************************************************************************************************/ + +/**************************************************************************************************** + * Public Data + ****************************************************************************************************/ + +/**************************************************************************************************** + * Public Function Prototypes + ****************************************************************************************************/ + +#endif /* __ARCH_ARM_SRC_STM32F7_CHIP_STM32F74XX77XX_ADC_H */ diff --git a/arch/arm/src/stm32f7/stm32_adc.c b/arch/arm/src/stm32f7/stm32_adc.c index c01db1e2b6..e4a885790d 100644 --- a/arch/arm/src/stm32f7/stm32_adc.c +++ b/arch/arm/src/stm32f7/stm32_adc.c @@ -6,6 +6,7 @@ * Authors: Gregory Nutt * Diego Sanchez * Paul Alexander Patience + * David Sidrane * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions @@ -60,11 +61,14 @@ #include #include #include +#include #include "up_internal.h" #include "up_arch.h" #include "chip.h" +#include "stm32_rcc.h" +#include "stm32_tim.h" #include "stm32_dma.h" #include "stm32_adc.h" @@ -77,9 +81,10 @@ #if defined(CONFIG_STM32F7_ADC1) || defined(CONFIG_STM32F7_ADC2) || \ defined(CONFIG_STM32F7_ADC3) -/* This implementation is for the STM32 F7 only */ +/* This implementation is for the STM32 F7[4-7] only */ -#if defined(CONFIG_STM32F7_STM32F74XX) +#if defined(CONFIG_STM32F7_STM32F74XX) || defined(CONFIG_STM32F7_STM32F75XX) || \ + defined(CONFIG_STM32F7_STM32F76XX) || defined(CONFIG_STM32F7_STM32F77XX) /**************************************************************************** * Pre-processor Definitions @@ -1121,7 +1126,6 @@ static void adc_dmaconvcallback(DMA_HANDLE handle, uint8_t isr, FAR void *arg) } } } - /* Restart DMA for the next conversion series */ adc_modifyreg(priv, STM32_ADC_DMAREG_OFFSET, ADC_DMAREG_DMA, 0); @@ -1723,9 +1727,13 @@ struct adc_dev_s *stm32_adc_initialize(int intf, FAR const uint8_t *chanlist, priv = (FAR struct stm32_dev_s *)dev->ad_priv; - DEBUGASSERT(cchannels <= ADC_MAX_SAMPLES); - priv->cb = NULL; + + DEBUGASSERT(cchannels <= ADC_MAX_SAMPLES); + if (cchannels > ADC_MAX_SAMPLES) + { + cchannels = ADC_MAX_SAMPLES; + } priv->cchannels = cchannels; memcpy(priv->chanlist, chanlist, cchannels); diff --git a/arch/arm/src/stm32f7/stm32_adc.h b/arch/arm/src/stm32f7/stm32_adc.h index b26a5206b1..f07afe42db 100644 --- a/arch/arm/src/stm32f7/stm32_adc.h +++ b/arch/arm/src/stm32f7/stm32_adc.h @@ -5,6 +5,7 @@ * Copyright (C) 2015 Omni Hoverboards Inc. All rights reserved. * Authors: Gregory Nutt * Paul Alexander Patience + * David Sidrane * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions @@ -103,10 +104,6 @@ /* Up to 3 ADC interfaces are supported */ -#if STM32F7_NADC < 4 -# undef CONFIG_STM32F7_ADC4 -#endif - #if STM32F7_NADC < 3 # undef CONFIG_STM32F7_ADC3 #endif @@ -758,7 +755,7 @@ extern "C" ****************************************************************************/ struct adc_dev_s; -struct adc_dev_s *stm32_adc_initialiize(int intf, +struct adc_dev_s *stm32_adc_initialize(int intf, FAR const uint8_t *chanlist, int nchannels); #undef EXTERN From 1c472a5ff01c49b8137aae97d0aa7143eb412306 Mon Sep 17 00:00:00 2001 From: David Sidrane Date: Wed, 15 Jun 2016 12:44:55 -1000 Subject: [PATCH 59/75] STM32 adc heared file error --- arch/arm/src/stm32/chip/stm32_adc.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/src/stm32/chip/stm32_adc.h b/arch/arm/src/stm32/chip/stm32_adc.h index b0990a37be..8a9eb956b6 100644 --- a/arch/arm/src/stm32/chip/stm32_adc.h +++ b/arch/arm/src/stm32/chip/stm32_adc.h @@ -478,7 +478,7 @@ # define ADC_SMPR1_SMP17_SHIFT (21) /* Bits 21-23: Channel 17 Sample time selection */ # define ADC_SMPR1_SMP17_MASK (7 << ADC_SMPR1_SMP17_SHIFT) # if defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F40XX) -# define ADC_SMPR1_SMP18_SHIFT (21) /* Bits 24-26: Channel 18 Sample time selection */ +# define ADC_SMPR1_SMP18_SHIFT (24) /* Bits 24-26: Channel 18 Sample time selection */ # define ADC_SMPR1_SMP18_MASK (7 << ADC_SMPR1_SMP17_SHIFT) # endif #else From 3ffd0e64fdfa9eef20ac998a02cca44a69cf7eca Mon Sep 17 00:00:00 2001 From: David Sidrane Date: Wed, 15 Jun 2016 17:05:17 -1000 Subject: [PATCH 60/75] Clean up and split 74xx75xx and 76xx77xx TIM --- arch/arm/src/stm32f7/Kconfig | 5 - arch/arm/src/stm32f7/chip/stm32_tim.h | 1098 +--------------- .../arm/src/stm32f7/chip/stm32f74xx75xx_tim.h | 1129 ++++++++++++++++ .../arm/src/stm32f7/chip/stm32f76xx77xx_tim.h | 1147 +++++++++++++++++ arch/arm/src/stm32f7/stm32_tim.c | 768 ++++++++--- 5 files changed, 2872 insertions(+), 1275 deletions(-) create mode 100644 arch/arm/src/stm32f7/chip/stm32f74xx75xx_tim.h create mode 100644 arch/arm/src/stm32f7/chip/stm32f76xx77xx_tim.h diff --git a/arch/arm/src/stm32f7/Kconfig b/arch/arm/src/stm32f7/Kconfig index b43c48a9dd..d41356ea2a 100644 --- a/arch/arm/src/stm32f7/Kconfig +++ b/arch/arm/src/stm32f7/Kconfig @@ -1310,11 +1310,6 @@ config STM32F7_TIM14 default n select STM32F7_TIM -config STM32F7_TIM15 - bool "TIM15" - default n - select STM32F7_TIM - config STM32F7_USART1 bool "USART1" default n diff --git a/arch/arm/src/stm32f7/chip/stm32_tim.h b/arch/arm/src/stm32f7/chip/stm32_tim.h index f4e04c39b1..77204d861d 100644 --- a/arch/arm/src/stm32f7/chip/stm32_tim.h +++ b/arch/arm/src/stm32f7/chip/stm32_tim.h @@ -2,7 +2,8 @@ * arch/arm/src/stm32f7/chip/stm32_tim.h * * Copyright (C) 2016 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Authors: Gregory Nutt + * David Sidrane * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions @@ -36,1092 +37,19 @@ #ifndef __ARCH_ARM_SRC_STM32F7_CHIP_STM32_TIM_H #define __ARCH_ARM_SRC_STM32F7_CHIP_STM32_TIM_H -/**************************************************************************************************** - * Pre-processor Definitions - ****************************************************************************************************/ +/************************************************************************************ + * Included Files + ************************************************************************************/ -/* Register Offsets *********************************************************************************/ +#include +#include "chip.h" -/* Basic Timers - TIM6 and TIM7 */ - -#define STM32_BTIM_CR1_OFFSET 0x0000 /* Control register 1 (16-bit) */ -#define STM32_BTIM_CR2_OFFSET 0x0004 /* Control register 2 (16-bit) */ -#define STM32_BTIM_DIER_OFFSET 0x000c /* DMA/Interrupt enable register (16-bit) */ -#define STM32_BTIM_SR_OFFSET 0x0010 /* Status register (16-bit) */ -#define STM32_BTIM_EGR_OFFSET 0x0014 /* Event generation register (16-bit) */ -#define STM32_BTIM_CNT_OFFSET 0x0024 /* Counter (16-bit) */ -#define STM32_BTIM_PSC_OFFSET 0x0028 /* Prescaler (16-bit) */ -#define STM32_BTIM_ARR_OFFSET 0x002c /* Auto-reload register (16-bit) */ - -/* 16-/32-bit General Timers with DMA: TIM2, TM3, TIM4, and TIM5 - * 16-bit General Timers without DMA: TIM9, TIM10, TIM11, TIM12, TIM13, and TIM14 - * For the STM32F10xx all timers are 16-bit. - * For the STM32F20xx and STM32F40xx, TIM2 and 5 are 32-bit - * The STM32 F1 Value Line and the STM32 F3 have variant general purpose registers - * that are not yet fully covered in this header file. - */ - -#define STM32_GTIM_CR1_OFFSET 0x0000 /* Control register 1 (16-bit) */ -#define STM32_GTIM_CR2_OFFSET 0x0004 /* Control register 2 (16-bit, TIM2-5 only) */ -#define STM32_GTIM_SMCR_OFFSET 0x0008 /* Slave mode control register (16-bit, TIM2-5 only) */ -#define STM32_GTIM_DIER_OFFSET 0x000c /* DMA/Interrupt enable register (16-bit) */ -#define STM32_GTIM_SR_OFFSET 0x0010 /* Status register (16-bit) */ -#define STM32_GTIM_EGR_OFFSET 0x0014 /* Event generation register (16-bit) */ -#define STM32_GTIM_CCMR1_OFFSET 0x0018 /* Capture/compare mode register 1 (16-bit) */ -#define STM32_GTIM_CCMR2_OFFSET 0x001c /* Capture/compare mode register 2 (16-bit, TIM2-5 only) */ -#define STM32_GTIM_CCER_OFFSET 0x0020 /* Capture/compare enable register (16-bit) */ -#define STM32_GTIM_CNT_OFFSET 0x0024 /* Counter (16-bit* or 32-bit STM3240 TIM2 and 5 only) */ -#define STM32_GTIM_PSC_OFFSET 0x0028 /* Prescaler (16-bit) */ -#define STM32_GTIM_ARR_OFFSET 0x002c /* Auto-reload register (16-bit) */ -#define STM32_GTIM_CCR1_OFFSET 0x0034 /* Capture/compare register 1 (16-bit or 32-bit STM3240 TIM2/5 only) */ -#define STM32_GTIM_CCR2_OFFSET 0x0038 /* Capture/compare register 2 (16-bit TIM2-5 only or 32-bit STM32 F4 TIM2/5 or STM2 F3 TIM15 only) */ -#define STM32_GTIM_CCR3_OFFSET 0x003c /* Capture/compare register 3 (16-bit TIM2-5 only or 32-bit STM32 F4 TIM2/5 only) */ -#define STM32_GTIM_CCR4_OFFSET 0x0040 /* Capture/compare register 4 (16-bit TIM2-5 only or 32-bit STM32 F4 TIM2/5 only) */ -#define STM32_GTIM_DCR_OFFSET 0x0048 /* DMA control register (16-bit, TIM2-5 only) */ -#define STM32_GTIM_DMAR_OFFSET 0x004c /* DMA address for burst mode (16-bit, TIM2-5 only) */ - -/* The Option register is available on in the - * - * STM32 F1 value line, F2 and F4: TIM2, TIM5, and TIM11 - * STM32 F3 (and possibly the F1 value line): TIM16 - */ - -#define STM32_GTIM_OR_OFFSET 0x0050 /* Timer 2/5/11/16 option register */ - -/* TIM16, and 17 only. - * Only available in the STM32 F1 Value Line and the STM32 F3 family. - */ - -#define STM32_GTIM_RCR_OFFSET 0x002c /* Repetition counter register (TIM16/TIM17) */ -#define STM32_GTIM_BDTR_OFFSET 0x0044 /* Break and dead-time register (TIM16/TIM17) */ - -/* Advanced Timers - TIM1 and TIM8 */ - -#define STM32_ATIM_CR1_OFFSET 0x0000 /* Control register 1 (16-bit) */ -#define STM32_ATIM_CR2_OFFSET 0x0004 /* Control register 2 (16-bit*) */ -#define STM32_ATIM_SMCR_OFFSET 0x0008 /* Slave mode control register (16-bit) */ -#define STM32_ATIM_DIER_OFFSET 0x000c /* DMA/Interrupt enable register (16-bit) */ -#define STM32_ATIM_SR_OFFSET 0x0010 /* Status register (16-bit*) */ -#define STM32_ATIM_EGR_OFFSET 0x0014 /* Event generation register (16-bit) */ -#define STM32_ATIM_CCMR1_OFFSET 0x0018 /* Capture/compare mode register 1 (16-bit*) */ -#define STM32_ATIM_CCMR2_OFFSET 0x001c /* Capture/compare mode register 2 (16-bit*) */ -#define STM32_ATIM_CCER_OFFSET 0x0020 /* Capture/compare enable register (16-bit*) */ -#define STM32_ATIM_CNT_OFFSET 0x0024 /* Counter (16-bit) */ -#define STM32_ATIM_PSC_OFFSET 0x0028 /* Prescaler (16-bit) */ -#define STM32_ATIM_ARR_OFFSET 0x002c /* Auto-reload register (16-bit) */ -#define STM32_ATIM_RCR_OFFSET 0x0030 /* Repetition counter register (16-bit) */ -#define STM32_ATIM_CCR1_OFFSET 0x0034 /* Capture/compare register 1 (16-bit) */ -#define STM32_ATIM_CCR2_OFFSET 0x0038 /* Capture/compare register 2 (16-bit) */ -#define STM32_ATIM_CCR3_OFFSET 0x003c /* Capture/compare register 3 (16-bit) */ -#define STM32_ATIM_CCR4_OFFSET 0x0040 /* Capture/compare register 4 (16-bit) */ -#define STM32_ATIM_BDTR_OFFSET 0x0044 /* Break and dead-time register (16-bit*) */ -#define STM32_ATIM_DCR_OFFSET 0x0048 /* DMA control register (16-bit) */ -#define STM32_ATIM_DMAR_OFFSET 0x004c /* DMA address for burst mode (16-bit) */ - -/* Register Addresses *******************************************************************************/ - -/* Advanced Timers - TIM1 and TIM8 */ - -#if STM32F7_NATIM > 0 -# define STM32_TIM1_CR1 (STM32_TIM1_BASE+STM32_ATIM_CR1_OFFSET) -# define STM32_TIM1_CR2 (STM32_TIM1_BASE+STM32_ATIM_CR2_OFFSET) -# define STM32_TIM1_SMCR (STM32_TIM1_BASE+STM32_ATIM_SMCR_OFFSET) -# define STM32_TIM1_DIER (STM32_TIM1_BASE+STM32_ATIM_DIER_OFFSET) -# define STM32_TIM1_SR (STM32_TIM1_BASE+STM32_ATIM_SR_OFFSET) -# define STM32_TIM1_EGR (STM32_TIM1_BASE+STM32_ATIM_EGR_OFFSET) -# define STM32_TIM1_CCMR1 (STM32_TIM1_BASE+STM32_ATIM_CCMR1_OFFSET) -# define STM32_TIM1_CCMR2 (STM32_TIM1_BASE+STM32_ATIM_CCMR2_OFFSET) -# define STM32_TIM1_CCER (STM32_TIM1_BASE+STM32_ATIM_CCER_OFFSET) -# define STM32_TIM1_CNT (STM32_TIM1_BASE+STM32_ATIM_CNT_OFFSET) -# define STM32_TIM1_PSC (STM32_TIM1_BASE+STM32_ATIM_PSC_OFFSET) -# define STM32_TIM1_ARR (STM32_TIM1_BASE+STM32_ATIM_ARR_OFFSET) -# define STM32_TIM1_RCR (STM32_TIM1_BASE+STM32_ATIM_RCR_OFFSET) -# define STM32_TIM1_CCR1 (STM32_TIM1_BASE+STM32_ATIM_CCR1_OFFSET) -# define STM32_TIM1_CCR2 (STM32_TIM1_BASE+STM32_ATIM_CCR2_OFFSET) -# define STM32_TIM1_CCR3 (STM32_TIM1_BASE+STM32_ATIM_CCR3_OFFSET) -# define STM32_TIM1_CCR4 (STM32_TIM1_BASE+STM32_ATIM_CCR4_OFFSET) -# define STM32_TIM1_BDTR (STM32_TIM1_BASE+STM32_ATIM_BDTR_OFFSET) -# define STM32_TIM1_DCR (STM32_TIM1_BASE+STM32_ATIM_DCR_OFFSET) -# define STM32_TIM1_DMAR (STM32_TIM1_BASE+STM32_ATIM_DMAR_OFFSET) +#if defined(CONFIG_STM32F7_STM32F74XX) || defined(CONFIG_STM32F7_STM32F75XX) +# include "chip/stm32f74xx75xx_tim.h" +#elif defined(CONFIG_STM32F7_STM32F76XX) || defined(CONFIG_STM32F7_STM32F77XX) +# include "chip/stm32f76xx77xx_tim.h" +#else +# error "Unsupported STM32 F7 sub family" #endif -#if STM32F7_NATIM > 1 -# define STM32_TIM8_CR1 (STM32_TIM8_BASE+STM32_ATIM_CR1_OFFSET) -# define STM32_TIM8_CR2 (STM32_TIM8_BASE+STM32_ATIM_CR2_OFFSET) -# define STM32_TIM8_SMCR (STM32_TIM8_BASE+STM32_ATIM_SMCR_OFFSET) -# define STM32_TIM8_DIER (STM32_TIM8_BASE+STM32_ATIM_DIER_OFFSET) -# define STM32_TIM8_SR (STM32_TIM8_BASE+STM32_ATIM_SR_OFFSET) -# define STM32_TIM8_EGR (STM32_TIM8_BASE+STM32_ATIM_EGR_OFFSET) -# define STM32_TIM8_CCMR1 (STM32_TIM8_BASE+STM32_ATIM_CCMR1_OFFSET) -# define STM32_TIM8_CCMR2 (STM32_TIM8_BASE+STM32_ATIM_CCMR2_OFFSET) -# define STM32_TIM8_CCER (STM32_TIM8_BASE+STM32_ATIM_CCER_OFFSET) -# define STM32_TIM8_CNT (STM32_TIM8_BASE+STM32_ATIM_CNT_OFFSET) -# define STM32_TIM8_PSC (STM32_TIM8_BASE+STM32_ATIM_PSC_OFFSET) -# define STM32_TIM8_ARR (STM32_TIM8_BASE+STM32_ATIM_ARR_OFFSET) -# define STM32_TIM8_RCR (STM32_TIM8_BASE+STM32_ATIM_RCR_OFFSET) -# define STM32_TIM8_CCR1 (STM32_TIM8_BASE+STM32_ATIM_CCR1_OFFSET) -# define STM32_TIM8_CCR2 (STM32_TIM8_BASE+STM32_ATIM_CCR2_OFFSET) -# define STM32_TIM8_CCR3 (STM32_TIM8_BASE+STM32_ATIM_CCR3_OFFSET) -# define STM32_TIM8_CCR4 (STM32_TIM8_BASE+STM32_ATIM_CCR4_OFFSET) -# define STM32_TIM8_BDTR (STM32_TIM8_BASE+STM32_ATIM_BDTR_OFFSET) -# define STM32_TIM8_DCR (STM32_TIM8_BASE+STM32_ATIM_DCR_OFFSET) -# define STM32_TIM8_DMAR (STM32_TIM8_BASE+STM32_ATIM_DMAR_OFFSET) -#endif - -/* 16-/32-bit General Timers - TIM2, TIM3, TIM4, and TIM5 with DMA. - * For the STM32F10xx all timers are 16-bit. - * For the STM32F2xx and STM32F40xx, TIM2 and 5 are 32-bit - */ - -#if (STM32F7_NGTIM16+STM32F7_NGTIM32) > 0 -# define STM32_TIM2_CR1 (STM32_TIM2_BASE+STM32_GTIM_CR1_OFFSET) -# define STM32_TIM2_CR2 (STM32_TIM2_BASE+STM32_GTIM_CR2_OFFSET) -# define STM32_TIM2_SMCR (STM32_TIM2_BASE+STM32_GTIM_SMCR_OFFSET) -# define STM32_TIM2_DIER (STM32_TIM2_BASE+STM32_GTIM_DIER_OFFSET) -# define STM32_TIM2_SR (STM32_TIM2_BASE+STM32_GTIM_SR_OFFSET) -# define STM32_TIM2_EGR (STM32_TIM2_BASE+STM32_GTIM_EGR_OFFSET) -# define STM32_TIM2_CCMR1 (STM32_TIM2_BASE+STM32_GTIM_CCMR1_OFFSET) -# define STM32_TIM2_CCMR2 (STM32_TIM2_BASE+STM32_GTIM_CCMR2_OFFSET) -# define STM32_TIM2_CCER (STM32_TIM2_BASE+STM32_GTIM_CCER_OFFSET) -# define STM32_TIM2_CNT (STM32_TIM2_BASE+STM32_GTIM_CNT_OFFSET) -# define STM32_TIM2_PSC (STM32_TIM2_BASE+STM32_GTIM_PSC_OFFSET) -# define STM32_TIM2_ARR (STM32_TIM2_BASE+STM32_GTIM_ARR_OFFSET) -# define STM32_TIM2_CCR1 (STM32_TIM2_BASE+STM32_GTIM_CCR1_OFFSET) -# define STM32_TIM2_CCR2 (STM32_TIM2_BASE+STM32_GTIM_CCR2_OFFSET) -# define STM32_TIM2_CCR3 (STM32_TIM2_BASE+STM32_GTIM_CCR3_OFFSET) -# define STM32_TIM2_CCR4 (STM32_TIM2_BASE+STM32_GTIM_CCR4_OFFSET) -# define STM32_TIM2_DCR (STM32_TIM2_BASE+STM32_GTIM_DCR_OFFSET) -# define STM32_TIM2_DMAR (STM32_TIM2_BASE+STM32_GTIM_DMAR_OFFSET) -#endif - -#if (STM32F7_NGTIM16+STM32F7_NGTIM32) > 1 -# define STM32_TIM3_CR1 (STM32_TIM3_BASE+STM32_GTIM_CR1_OFFSET) -# define STM32_TIM3_CR2 (STM32_TIM3_BASE+STM32_GTIM_CR2_OFFSET) -# define STM32_TIM3_SMCR (STM32_TIM3_BASE+STM32_GTIM_SMCR_OFFSET) -# define STM32_TIM3_DIER (STM32_TIM3_BASE+STM32_GTIM_DIER_OFFSET) -# define STM32_TIM3_SR (STM32_TIM3_BASE+STM32_GTIM_SR_OFFSET) -# define STM32_TIM3_EGR (STM32_TIM3_BASE+STM32_GTIM_EGR_OFFSET) -# define STM32_TIM3_CCMR1 (STM32_TIM3_BASE+STM32_GTIM_CCMR1_OFFSET) -# define STM32_TIM3_CCMR2 (STM32_TIM3_BASE+STM32_GTIM_CCMR2_OFFSET) -# define STM32_TIM3_CCER (STM32_TIM3_BASE+STM32_GTIM_CCER_OFFSET) -# define STM32_TIM3_CNT (STM32_TIM3_BASE+STM32_GTIM_CNT_OFFSET) -# define STM32_TIM3_PSC (STM32_TIM3_BASE+STM32_GTIM_PSC_OFFSET) -# define STM32_TIM3_ARR (STM32_TIM3_BASE+STM32_GTIM_ARR_OFFSET) -# define STM32_TIM3_CCR1 (STM32_TIM3_BASE+STM32_GTIM_CCR1_OFFSET) -# define STM32_TIM3_CCR2 (STM32_TIM3_BASE+STM32_GTIM_CCR2_OFFSET) -# define STM32_TIM3_CCR3 (STM32_TIM3_BASE+STM32_GTIM_CCR3_OFFSET) -# define STM32_TIM3_CCR4 (STM32_TIM3_BASE+STM32_GTIM_CCR4_OFFSET) -# define STM32_TIM3_DCR (STM32_TIM3_BASE+STM32_GTIM_DCR_OFFSET) -# define STM32_TIM3_DMAR (STM32_TIM3_BASE+STM32_GTIM_DMAR_OFFSET) -#endif - -#if (STM32F7_NGTIM16+STM32F7_NGTIM32) > 2 -# define STM32_TIM4_CR1 (STM32_TIM4_BASE+STM32_GTIM_CR1_OFFSET) -# define STM32_TIM4_CR2 (STM32_TIM4_BASE+STM32_GTIM_CR2_OFFSET) -# define STM32_TIM4_SMCR (STM32_TIM4_BASE+STM32_GTIM_SMCR_OFFSET) -# define STM32_TIM4_DIER (STM32_TIM4_BASE+STM32_GTIM_DIER_OFFSET) -# define STM32_TIM4_SR (STM32_TIM4_BASE+STM32_GTIM_SR_OFFSET) -# define STM32_TIM4_EGR (STM32_TIM4_BASE+STM32_GTIM_EGR_OFFSET) -# define STM32_TIM4_CCMR1 (STM32_TIM4_BASE+STM32_GTIM_CCMR1_OFFSET) -# define STM32_TIM4_CCMR2 (STM32_TIM4_BASE+STM32_GTIM_CCMR2_OFFSET) -# define STM32_TIM4_CCER (STM32_TIM4_BASE+STM32_GTIM_CCER_OFFSET) -# define STM32_TIM4_CNT (STM32_TIM4_BASE+STM32_GTIM_CNT_OFFSET) -# define STM32_TIM4_PSC (STM32_TIM4_BASE+STM32_GTIM_PSC_OFFSET) -# define STM32_TIM4_ARR (STM32_TIM4_BASE+STM32_GTIM_ARR_OFFSET) -# define STM32_TIM4_CCR1 (STM32_TIM4_BASE+STM32_GTIM_CCR1_OFFSET) -# define STM32_TIM4_CCR2 (STM32_TIM4_BASE+STM32_GTIM_CCR2_OFFSET) -# define STM32_TIM4_CCR3 (STM32_TIM4_BASE+STM32_GTIM_CCR3_OFFSET) -# define STM32_TIM4_CCR4 (STM32_TIM4_BASE+STM32_GTIM_CCR4_OFFSET) -# define STM32_TIM4_DCR (STM32_TIM4_BASE+STM32_GTIM_DCR_OFFSET) -# define STM32_TIM4_DMAR (STM32_TIM4_BASE+STM32_GTIM_DMAR_OFFSET) -#endif - -#if (STM32F7_NGTIM16+STM32F7_NGTIM32) > 3 -# define STM32_TIM5_CR1 (STM32_TIM5_BASE+STM32_GTIM_CR1_OFFSET) -# define STM32_TIM5_CR2 (STM32_TIM5_BASE+STM32_GTIM_CR2_OFFSET) -# define STM32_TIM5_SMCR (STM32_TIM5_BASE+STM32_GTIM_SMCR_OFFSET) -# define STM32_TIM5_DIER (STM32_TIM5_BASE+STM32_GTIM_DIER_OFFSET) -# define STM32_TIM5_SR (STM32_TIM5_BASE+STM32_GTIM_SR_OFFSET) -# define STM32_TIM5_EGR (STM32_TIM5_BASE+STM32_GTIM_EGR_OFFSET) -# define STM32_TIM5_CCMR1 (STM32_TIM5_BASE+STM32_GTIM_CCMR1_OFFSET) -# define STM32_TIM5_CCMR2 (STM32_TIM5_BASE+STM32_GTIM_CCMR2_OFFSET) -# define STM32_TIM5_CCER (STM32_TIM5_BASE+STM32_GTIM_CCER_OFFSET) -# define STM32_TIM5_CNT (STM32_TIM5_BASE+STM32_GTIM_CNT_OFFSET) -# define STM32_TIM5_PSC (STM32_TIM5_BASE+STM32_GTIM_PSC_OFFSET) -# define STM32_TIM5_ARR (STM32_TIM5_BASE+STM32_GTIM_ARR_OFFSET) -# define STM32_TIM5_CCR1 (STM32_TIM5_BASE+STM32_GTIM_CCR1_OFFSET) -# define STM32_TIM5_CCR2 (STM32_TIM5_BASE+STM32_GTIM_CCR2_OFFSET) -# define STM32_TIM5_CCR3 (STM32_TIM5_BASE+STM32_GTIM_CCR3_OFFSET) -# define STM32_TIM5_CCR4 (STM32_TIM5_BASE+STM32_GTIM_CCR4_OFFSET) -# define STM32_TIM5_DCR (STM32_TIM5_BASE+STM32_GTIM_DCR_OFFSET) -# define STM32_TIM5_DMAR (STM32_TIM5_BASE+STM32_GTIM_DMAR_OFFSET) -# define STM32_TIM2_OR (STM32_TIM2_BASE+STM32_GTIM_OR_OFFSET) -#endif - -#define STM32_TIM15_CR1 (STM32_TIM15_BASE+STM32_GTIM_CR1_OFFSET) -#define STM32_TIM15_CR2 (STM32_TIM15_BASE+STM32_GTIM_CR2_OFFSET) -#define STM32_TIM15_SMCR (STM32_TIM15_BASE+STM32_GTIM_SMCR_OFFSET) -#define STM32_TIM15_DIER (STM32_TIM15_BASE+STM32_GTIM_DIER_OFFSET) -#define STM32_TIM15_SR (STM32_TIM15_BASE+STM32_GTIM_SR_OFFSET) -#define STM32_TIM15_EGR (STM32_TIM15_BASE+STM32_GTIM_EGR_OFFSET) -#define STM32_TIM15_CCMR1 (STM32_TIM15_BASE+STM32_GTIM_CCMR1_OFFSET) -#define STM32_TIM15_CCER (STM32_TIM15_BASE+STM32_GTIM_CCER_OFFSET) -#define STM32_TIM15_CNT (STM32_TIM15_BASE+STM32_GTIM_CNT_OFFSET) -#define STM32_TIM15_PSC (STM32_TIM15_BASE+STM32_GTIM_PSC_OFFSET) -#define STM32_TIM15_ARR (STM32_TIM15_BASE+STM32_GTIM_ARR_OFFSET) -#define STM32_TIM15_RCR (STM32_TIM15_BASE+STM32_GTIM_RCR_OFFSET) -#define STM32_TIM15_CCR1 (STM32_TIM15_BASE+STM32_GTIM_CCR1_OFFSET) -#define STM32_TIM15_CCR2 (STM32_TIM15_BASE+STM32_GTIM_CCR2_OFFSET) -#define STM32_TIM15_BDTR (STM32_TIM15_BASE+STM32_GTIM_BDTR_OFFSET) -#define STM32_TIM15_DCR (STM32_TIM15_BASE+STM32_GTIM_DCR_OFFSET) -#define STM32_TIM15_DMAR (STM32_TIM15_BASE+STM32_GTIM_DMAR_OFFSET) - -#define STM32_TIM16_CR1 (STM32_TIM16_BASE+STM32_GTIM_CR1_OFFSET) -#define STM32_TIM16_CR2 (STM32_TIM16_BASE+STM32_GTIM_CR2_OFFSET) -#define STM32_TIM16_DIER (STM32_TIM16_BASE+STM32_GTIM_DIER_OFFSET) -#define STM32_TIM16_SR (STM32_TIM16_BASE+STM32_GTIM_SR_OFFSET) -#define STM32_TIM16_EGR (STM32_TIM16_BASE+STM32_GTIM_EGR_OFFSET) -#define STM32_TIM16_CCMR1 (STM32_TIM16_BASE+STM32_GTIM_CCMR1_OFFSET) -#define STM32_TIM16_CCMR2 (STM32_TIM16_BASE+STM32_GTIM_CCMR2_OFFSET) -#define STM32_TIM16_CCER (STM32_TIM16_BASE+STM32_GTIM_CCER_OFFSET) -#define STM32_TIM16_CNT (STM32_TIM16_BASE+STM32_GTIM_CNT_OFFSET) -#define STM32_TIM16_PSC (STM32_TIM16_BASE+STM32_GTIM_PSC_OFFSET) -#define STM32_TIM16_ARR (STM32_TIM16_BASE+STM32_GTIM_ARR_OFFSET) -#define STM32_TIM16_RCR (STM32_TIM16_BASE+STM32_GTIM_RCR_OFFSET) -#define STM32_TIM16_CCR1 (STM32_TIM16_BASE+STM32_GTIM_CCR1_OFFSET) -#define STM32_TIM16_BDTR (STM32_TIM16_BASE+STM32_GTIM_BDTR_OFFSET) -#define STM32_TIM16_DCR (STM32_TIM16_BASE+STM32_GTIM_DCR_OFFSET) -#define STM32_TIM16_DMAR (STM32_TIM16_BASE+STM32_GTIM_DMAR_OFFSET) -#define STM32_TIM16_OR (STM32_TIM16_BASE+STM32_GTIM_OR_OFFSET) - -#define STM32_TIM17_CR1 (STM32_TIM17_BASE+STM32_GTIM_CR1_OFFSET) -#define STM32_TIM17_CR2 (STM32_TIM17_BASE+STM32_GTIM_CR2_OFFSET) -#define STM32_TIM17_DIER (STM32_TIM17_BASE+STM32_GTIM_DIER_OFFSET) -#define STM32_TIM17_SR (STM32_TIM17_BASE+STM32_GTIM_SR_OFFSET) -#define STM32_TIM17_EGR (STM32_TIM17_BASE+STM32_GTIM_EGR_OFFSET) -#define STM32_TIM17_CCMR1 (STM32_TIM17_BASE+STM32_GTIM_CCMR1_OFFSET) -#define STM32_TIM17_CCMR2 (STM32_TIM17_BASE+STM32_GTIM_CCMR2_OFFSET) -#define STM32_TIM17_CCER (STM32_TIM17_BASE+STM32_GTIM_CCER_OFFSET) -#define STM32_TIM17_CNT (STM32_TIM17_BASE+STM32_GTIM_CNT_OFFSET) -#define STM32_TIM17_PSC (STM32_TIM17_BASE+STM32_GTIM_PSC_OFFSET) -#define STM32_TIM17_ARR (STM32_TIM17_BASE+STM32_GTIM_ARR_OFFSET) -#define STM32_TIM17_RCR (STM32_TIM17_BASE+STM32_GTIM_RCR_OFFSET) -#define STM32_TIM17_CCR1 (STM32_TIM17_BASE+STM32_GTIM_CCR1_OFFSET) -#define STM32_TIM17_BDTR (STM32_TIM17_BASE+STM32_GTIM_BDTR_OFFSET) -#define STM32_TIM17_DCR (STM32_TIM17_BASE+STM32_GTIM_DCR_OFFSET) -#define STM32_TIM17_DMAR (STM32_TIM17_BASE+STM32_GTIM_DMAR_OFFSET) - -/* 16-bit General Timers - TIM9-14 without DMA. Note that (1) these timers - * support only a subset of the general timer registers are supported, and - * (2) TIM9 and TIM12 differ from the others. - */ - -#if STM32F7_NGTIMNDMA > 0 -# define STM32_TIM9_CR1 (STM32_TIM9_BASE+STM32_GTIM_CR1_OFFSET) -# define STM32_TIM9_CR2 (STM32_TIM9_BASE+STM32_GTIM_CR2_OFFSET) -# define STM32_TIM9_DIER (STM32_TIM9_BASE+STM32_GTIM_DIER_OFFSET) -# define STM32_TIM9_SR (STM32_TIM9_BASE+STM32_GTIM_SR_OFFSET) -# define STM32_TIM9_EGR (STM32_TIM9_BASE+STM32_GTIM_EGR_OFFSET) -# define STM32_TIM9_CCMR1 (STM32_TIM9_BASE+STM32_GTIM_CCMR1_OFFSET) -# define STM32_TIM9_CCER (STM32_TIM9_BASE+STM32_GTIM_CCER_OFFSET) -# define STM32_TIM9_CNT (STM32_TIM9_BASE+STM32_GTIM_CNT_OFFSET) -# define STM32_TIM9_PSC (STM32_TIM9_BASE+STM32_GTIM_PSC_OFFSET) -# define STM32_TIM9_ARR (STM32_TIM9_BASE+STM32_GTIM_ARR_OFFSET) -# define STM32_TIM9_CCR1 (STM32_TIM9_BASE+STM32_GTIM_CCR1_OFFSET) -# define STM32_TIM9_CCR2 (STM32_TIM9_BASE+STM32_GTIM_CCR2_OFFSET) -#endif - -#if STM32F7_NGTIMNDMA > 1 -# define STM32_TIM10_CR1 (STM32_TIM10_BASE+STM32_GTIM_CR1_OFFSET) -# define STM32_TIM10_DIER (STM32_TIM10_BASE+STM32_GTIM_DIER_OFFSET) -# define STM32_TIM10_SR (STM32_TIM10_BASE+STM32_GTIM_SR_OFFSET) -# define STM32_TIM10_EGR (STM32_TIM10_BASE+STM32_GTIM_EGR_OFFSET) -# define STM32_TIM10_CCMR1 (STM32_TIM10_BASE+STM32_GTIM_CCMR1_OFFSET) -# define STM32_TIM10_CCER (STM32_TIM10_BASE+STM32_GTIM_CCER_OFFSET) -# define STM32_TIM10_CNT (STM32_TIM10_BASE+STM32_GTIM_CNT_OFFSET) -# define STM32_TIM10_PSC (STM32_TIM10_BASE+STM32_GTIM_PSC_OFFSET) -# define STM32_TIM10_ARR (STM32_TIM10_BASE+STM32_GTIM_ARR_OFFSET) -# define STM32_TIM10_CCR1 (STM32_TIM10_BASE+STM32_GTIM_CCR1_OFFSET) -#endif - -#if STM32F7_NGTIMNDMA > 2 -# define STM32_TIM11_CR1 (STM32_TIM11_BASE+STM32_GTIM_CR1_OFFSET) -# define STM32_TIM11_DIER (STM32_TIM11_BASE+STM32_GTIM_DIER_OFFSET) -# define STM32_TIM11_SR (STM32_TIM11_BASE+STM32_GTIM_SR_OFFSET) -# define STM32_TIM11_EGR (STM32_TIM11_BASE+STM32_GTIM_EGR_OFFSET) -# define STM32_TIM11_CCMR1 (STM32_TIM11_BASE+STM32_GTIM_CCMR1_OFFSET) -# define STM32_TIM11_CCER (STM32_TIM11_BASE+STM32_GTIM_CCER_OFFSET) -# define STM32_TIM11_CNT (STM32_TIM11_BASE+STM32_GTIM_CNT_OFFSET) -# define STM32_TIM11_PSC (STM32_TIM11_BASE+STM32_GTIM_PSC_OFFSET) -# define STM32_TIM11_ARR (STM32_TIM11_BASE+STM32_GTIM_ARR_OFFSET) -# define STM32_TIM11_CCR1 (STM32_TIM11_BASE+STM32_GTIM_CCR1_OFFSET) -# define STM32_TIM11_OR (STM32_TIM11_BASE+STM32_GTIM_OR_OFFSET) -#endif - -#if STM32F7_NGTIMNDMA > 3 -# define STM32_TIM12_CR1 (STM32_TIM12_BASE+STM32_GTIM_CR1_OFFSET) -# define STM32_TIM12_CR2 (STM32_TIM9_BASE+STM32_GTIM_CR2_OFFSET) -# define STM32_TIM12_DIER (STM32_TIM12_BASE+STM32_GTIM_DIER_OFFSET) -# define STM32_TIM12_SR (STM32_TIM12_BASE+STM32_GTIM_SR_OFFSET) -# define STM32_TIM12_EGR (STM32_TIM12_BASE+STM32_GTIM_EGR_OFFSET) -# define STM32_TIM12_CCMR1 (STM32_TIM12_BASE+STM32_GTIM_CCMR1_OFFSET) -# define STM32_TIM12_CCER (STM32_TIM12_BASE+STM32_GTIM_CCER_OFFSET) -# define STM32_TIM12_CNT (STM32_TIM12_BASE+STM32_GTIM_CNT_OFFSET) -# define STM32_TIM12_PSC (STM32_TIM12_BASE+STM32_GTIM_PSC_OFFSET) -# define STM32_TIM12_ARR (STM32_TIM12_BASE+STM32_GTIM_ARR_OFFSET) -# define STM32_TIM12_CCR1 (STM32_TIM12_BASE+STM32_GTIM_CCR1_OFFSET) -# define STM32_TIM12_CCR2 (STM32_TIM12_BASE+STM32_GTIM_CCR2_OFFSET) -#endif - -#if STM32F7_NGTIMNDMA > 4 -# define STM32_TIM13_CR1 (STM32_TIM13_BASE+STM32_GTIM_CR1_OFFSET) -# define STM32_TIM13_DIER (STM32_TIM13_BASE+STM32_GTIM_DIER_OFFSET) -# define STM32_TIM13_SR (STM32_TIM13_BASE+STM32_GTIM_SR_OFFSET) -# define STM32_TIM13_EGR (STM32_TIM13_BASE+STM32_GTIM_EGR_OFFSET) -# define STM32_TIM13_CCMR1 (STM32_TIM13_BASE+STM32_GTIM_CCMR1_OFFSET) -# define STM32_TIM13_CCER (STM32_TIM13_BASE+STM32_GTIM_CCER_OFFSET) -# define STM32_TIM13_CNT (STM32_TIM13_BASE+STM32_GTIM_CNT_OFFSET) -# define STM32_TIM13_PSC (STM32_TIM13_BASE+STM32_GTIM_PSC_OFFSET) -# define STM32_TIM13_ARR (STM32_TIM13_BASE+STM32_GTIM_ARR_OFFSET) -# define STM32_TIM13_CCR1 (STM32_TIM13_BASE+STM32_GTIM_CCR1_OFFSET) -#endif - -#if STM32F7_NGTIMNDMA > 5 -# define STM32_TIM14_CR1 (STM32_TIM14_BASE+STM32_GTIM_CR1_OFFSET) -# define STM32_TIM14_DIER (STM32_TIM14_BASE+STM32_GTIM_DIER_OFFSET) -# define STM32_TIM14_SR (STM32_TIM14_BASE+STM32_GTIM_SR_OFFSET) -# define STM32_TIM14_EGR (STM32_TIM14_BASE+STM32_GTIM_EGR_OFFSET) -# define STM32_TIM14_CCMR1 (STM32_TIM14_BASE+STM32_GTIM_CCMR1_OFFSET) -# define STM32_TIM14_CCER (STM32_TIM14_BASE+STM32_GTIM_CCER_OFFSET) -# define STM32_TIM14_CNT (STM32_TIM14_BASE+STM32_GTIM_CNT_OFFSET) -# define STM32_TIM14_PSC (STM32_TIM14_BASE+STM32_GTIM_PSC_OFFSET) -# define STM32_TIM14_ARR (STM32_TIM14_BASE+STM32_GTIM_ARR_OFFSET) -# define STM32_TIM14_CCR1 (STM32_TIM14_BASE+STM32_GTIM_CCR1_OFFSET) -#endif - -/* Basic Timers - TIM6 and TIM7 */ - -#if STM32F7_NBTIM > 0 -# define STM32_TIM6_CR1 (STM32_TIM6_BASE+STM32_BTIM_CR1_OFFSET) -# define STM32_TIM6_CR2 (STM32_TIM6_BASE+STM32_BTIM_CR2_OFFSET) -# define STM32_TIM6_DIER (STM32_TIM6_BASE+STM32_BTIM_DIER_OFFSET) -# define STM32_TIM6_SR (STM32_TIM6_BASE+STM32_BTIM_SR_OFFSET) -# define STM32_TIM6_EGR (STM32_TIM6_BASE+STM32_BTIM_EGR_OFFSET) -# define STM32_TIM6_CNT (STM32_TIM6_BASE+STM32_BTIM_CNT_OFFSET) -# define STM32_TIM6_PSC (STM32_TIM6_BASE+STM32_BTIM_PSC_OFFSET) -# define STM32_TIM6_ARR (STM32_TIM6_BASE+STM32_BTIM_ARR_OFFSET) -#endif - -#if STM32F7_NBTIM > 1 -# define STM32_TIM7_CR1 (STM32_TIM7_BASE+STM32_BTIM_CR1_OFFSET) -# define STM32_TIM7_CR2 (STM32_TIM7_BASE+STM32_BTIM_CR2_OFFSET) -# define STM32_TIM7_DIER (STM32_TIM7_BASE+STM32_BTIM_DIER_OFFSET) -# define STM32_TIM7_SR (STM32_TIM7_BASE+STM32_BTIM_SR_OFFSET) -# define STM32_TIM7_EGR (STM32_TIM7_BASE+STM32_BTIM_EGR_OFFSET) -# define STM32_TIM7_CNT (STM32_TIM7_BASE+STM32_BTIM_CNT_OFFSET) -# define STM32_TIM7_PSC (STM32_TIM7_BASE+STM32_BTIM_PSC_OFFSET) -# define STM32_TIM7_ARR (STM32_TIM7_BASE+STM32_BTIM_ARR_OFFSET) -#endif - -/* Register Bitfield Definitions ********************************************************************/ - -/* Control register 1 */ - -#define ATIM_CR1_CEN (1 << 0) /* Bit 0: Counter enable */ -#define ATIM_CR1_UDIS (1 << 1) /* Bit 1: Update disable */ -#define ATIM_CR1_URS (1 << 2) /* Bit 2: Update request source */ -#define ATIM_CR1_OPM (1 << 3) /* Bit 3: One pulse mode */ -#define ATIM_CR1_DIR (1 << 4) /* Bit 4: Direction */ -#define ATIM_CR1_CMS_SHIFT (5) /* Bits 6-5: Center-aligned mode selection */ -#define ATIM_CR1_CMS_MASK (3 << ATIM_CR1_CMS_SHIFT) -# define ATIM_CR1_EDGE (0 << ATIM_CR1_CMS_SHIFT) /* 00: Edge-aligned mode */ -# define ATIM_CR1_CENTER1 (1 << ATIM_CR1_CMS_SHIFT) /* 01: Center-aligned mode 1 */ -# define ATIM_CR1_CENTER2 (2 << ATIM_CR1_CMS_SHIFT) /* 10: Center-aligned mode 2 */ -# define ATIM_CR1_CENTER3 (3 << ATIM_CR1_CMS_SHIFT) /* 11: Center-aligned mode 3 */ -#define ATIM_CR1_ARPE (1 << 7) /* Bit 7: Auto-reload preload enable */ -#define ATIM_CR1_CKD_SHIFT (8) /* Bits 9-8: Clock division */ -#define ATIM_CR1_CKD_MASK (3 << ATIM_CR1_CKD_SHIFT) -# define ATIM_CR1_TCKINT (0 << ATIM_CR1_CKD_SHIFT) /* 00: tDTS=tCK_INT */ -# define ATIM_CR1_2TCKINT (1 << ATIM_CR1_CKD_SHIFT) /* 01: tDTS=2*tCK_INT */ -# define ATIM_CR1_4TCKINT (2 << ATIM_CR1_CKD_SHIFT) /* 10: tDTS=4*tCK_INT */ - -/* Control register 2 */ - -#define ATIM_CR2_CCPC (1 << 0) /* Bit 0: Capture/Compare Preloaded Control */ -#define ATIM_CR2_CCUS (1 << 2) /* Bit 2: Capture/Compare Control Update Selection */ -#define ATIM_CR2_CCDS (1 << 3) /* Bit 3: Capture/Compare DMA Selection */ -#define ATIM_CR2_MMS_SHIFT (4) /* Bits 6-4: Master Mode Selection */ -#define ATIM_CR2_MMS_MASK (7 << ATIM_CR2_MMS_SHIFT) -# define ATIM_CR2_MMS_RESET (0 << ATIM_CR2_MMS_SHIFT) /* 000: Reset - TIMx_EGR UG bit is TRGO */ -# define ATIM_CR2_MMS_ENABLE (1 << ATIM_CR2_MMS_SHIFT) /* 001: Enable - CNT_EN is TRGO */ -# define ATIM_CR2_MMS_UPDATE (2 << ATIM_CR2_MMS_SHIFT) /* 010: Update event is TRGO */ -# define ATIM_CR2_MMS_COMPP (3 << ATIM_CR2_MMS_SHIFT) /* 010: Compare Pulse - CC1IF flag */ -# define ATIM_CR2_MMS_OC1REF (4 << ATIM_CR2_MMS_SHIFT) /* 100: Compare OC1REF is TRGO */ -# define ATIM_CR2_MMS_OC2REF (5 << ATIM_CR2_MMS_SHIFT) /* 101: Compare OC2REF is TRGO */ -# define ATIM_CR2_MMS_OC3REF (6 << ATIM_CR2_MMS_SHIFT) /* 110: Compare OC3REF is TRGO */ -# define ATIM_CR2_MMS_OC4REF (7 << ATIM_CR2_MMS_SHIFT) /* 111: Compare OC4REF is TRGO */ -#define ATIM_CR2_TI1S (1 << 7) /* Bit 7: TI1 Selection */ -#define ATIM_CR2_OIS1 (1 << 8) /* Bit 8: Output Idle state 1 (OC1 output) */ -#define ATIM_CR2_OIS1N (1 << 9) /* Bit 9: Output Idle state 1 (OC1N output) */ -#define ATIM_CR2_OIS2 (1 << 10) /* Bit 10: Output Idle state 2 (OC2 output) */ -#define ATIM_CR2_OIS2N (1 << 11) /* Bit 11: Output Idle state 2 (OC2N output) */ -#define ATIM_CR2_OIS3 (1 << 12) /* Bit 12: Output Idle state 3 (OC3 output) */ -#define ATIM_CR2_OIS3N (1 << 13) /* Bit 13: Output Idle state 3 (OC3N output) */ -#define ATIM_CR2_OIS4 (1 << 14) /* Bit 14: Output Idle state 4 (OC4 output) */ - -/* Slave mode control register */ - -#define ATIM_SMCR_SMS_SHIFT (0) /* Bits 0-2: Slave mode selection */ -#define ATIM_SMCR_SMS_MASK (7 << ATIM_SMCR_SMS_SHIFT) -# define ATIM_SMCR_DISAB (0 << ATIM_SMCR_SMS_SHIFT) /* 000: Slave mode disabled */ -# define ATIM_SMCR_ENCMD1 (1 << ATIM_SMCR_SMS_SHIFT) /* 001: Encoder mode 1 */ -# define ATIM_SMCR_ENCMD2 (2 << ATIM_SMCR_SMS_SHIFT) /* 010: Encoder mode 2 */ -# define ATIM_SMCR_ENCMD3 (3 << ATIM_SMCR_SMS_SHIFT) /* 011: Encoder mode 3 */ -# define ATIM_SMCR_RESET (4 << ATIM_SMCR_SMS_SHIFT) /* 100: Reset Mode */ -# define ATIM_SMCR_GATED (5 << ATIM_SMCR_SMS_SHIFT) /* 101: Gated Mode */ -# define ATIM_SMCR_TRIGGER (6 << ATIM_SMCR_SMS_SHIFT) /* 110: Trigger Mode */ -# define ATIM_SMCR_EXTCLK1 (7 << ATIM_SMCR_SMS_SHIFT) /* 111: External Clock Mode 1 */ -#define ATIM_SMCR_TS_SHIFT (4) /* Bits 4-6: Trigger selection */ -#define ATIM_SMCR_TS_MASK (7 << ATIM_SMCR_TS_SHIFT) -# define ATIM_SMCR_ITR0 (0 << ATIM_SMCR_TS_SHIFT) /* 000: Internal trigger 0 (ITR0) */ -# define ATIM_SMCR_ITR1 (1 << ATIM_SMCR_TS_SHIFT) /* 001: Internal trigger 1 (ITR1) */ -# define ATIM_SMCR_ITR2 (2 << ATIM_SMCR_TS_SHIFT) /* 010: Internal trigger 2 (ITR2) */ -# define ATIM_SMCR_ITR3 (3 << ATIM_SMCR_TS_SHIFT) /* 011: Internal trigger 3 (ITR3) */ -# define ATIM_SMCR_T1FED (4 << ATIM_SMCR_TS_SHIFT) /* 100: TI1 Edge Detector (TI1F_ED) */ -# define ATIM_SMCR_TI1FP1 (5 << ATIM_SMCR_TS_SHIFT) /* 101: Filtered Timer Input 1 (TI1FP1) */ -# define ATIM_SMCR_T12FP2 (6 << ATIM_SMCR_TS_SHIFT) /* 110: Filtered Timer Input 2 (TI2FP2) */ -# define ATIM_SMCR_ETRF (7 << ATIM_SMCR_TS_SHIFT) /* 111: External Trigger input (ETRF) */ -#define ATIM_SMCR_MSM (1 << 7) /* Bit 7: Master/slave mode */ -#define ATIM_SMCR_ETF_SHIFT (8) /* Bits 8-11: External trigger filter */ -#define ATIM_SMCR_ETF_MASK (0x0f << ATIM_SMCR_ETF_SHIFT) -# define ATIM_SMCR_NOFILT (0 << ATIM_SMCR_ETF_SHIFT) /* 0000: No filter, sampling is done at fDTS */ -# define ATIM_SMCR_FCKINT2 (1 << ATIM_SMCR_ETF_SHIFT) /* 0001: fSAMPLING=fCK_INT, N=2 */ -# define ATIM_SMCR_FCKINT4 (2 << ATIM_SMCR_ETF_SHIFT) /* 0010: fSAMPLING=fCK_INT, N=4 */ -# define ATIM_SMCR_FCKINT8 (3 << ATIM_SMCR_ETF_SHIFT) /* 0011: fSAMPLING=fCK_INT, N=8 */ -# define ATIM_SMCR_FDTSd26 (4 << ATIM_SMCR_ETF_SHIFT) /* 0100: fSAMPLING=fDTS/2, N=6 */ -# define ATIM_SMCR_FDTSd28 (5 << ATIM_SMCR_ETF_SHIFT) /* 0101: fSAMPLING=fDTS/2, N=8 */ -# define ATIM_SMCR_FDTSd46 (6 << ATIM_SMCR_ETF_SHIFT) /* 0110: fSAMPLING=fDTS/4, N=6 */ -# define ATIM_SMCR_FDTSd48 (7 << ATIM_SMCR_ETF_SHIFT) /* 0111: fSAMPLING=fDTS/4, N=8 */ -# define ATIM_SMCR_FDTSd86 (8 << ATIM_SMCR_ETF_SHIFT) /* 1000: fSAMPLING=fDTS/8, N=6 */ -# define ATIM_SMCR_FDTSd88 (9 << ATIM_SMCR_ETF_SHIFT) /* 1001: fSAMPLING=fDTS/8, N=8 */ -# define ATIM_SMCR_FDTSd165 (10 << ATIM_SMCR_ETF_SHIFT) /* 1010: fSAMPLING=fDTS/16, N=5 */ -# define ATIM_SMCR_FDTSd166 (11 << ATIM_SMCR_ETF_SHIFT) /* 1011: fSAMPLING=fDTS/16, N=6 */ -# define ATIM_SMCR_FDTSd168 (12 << ATIM_SMCR_ETF_SHIFT) /* 1100: fSAMPLING=fDTS/16, N=8 */ -# define ATIM_SMCR_FDTSd325 (13 << ATIM_SMCR_ETF_SHIFT) /* 1101: fSAMPLING=fDTS/32, N=5 */ -# define ATIM_SMCR_FDTSd326 (14 << ATIM_SMCR_ETF_SHIFT) /* 1110: fSAMPLING=fDTS/32, N=6 */ -# define ATIM_SMCR_FDTSd328 (15 << ATIM_SMCR_ETF_SHIFT) /* 1111: fSAMPLING=fDTS/32, N=8 */ -#define ATIM_SMCR_ETPS_SHIFT (12) /* Bits 12-13: External trigger prescaler */ -#define ATIM_SMCR_ETPS_MASK (3 << ATIM_SMCR_ETPS_SHIFT) -# define ATIM_SMCR_PSCOFF (0 << ATIM_SMCR_ETPS_SHIFT) /* 00: Prescaler OFF */ -# define ATIM_SMCR_ETRPd2 (1 << ATIM_SMCR_ETPS_SHIFT) /* 01: ETRP frequency divided by 2 */ -# define ATIM_SMCR_ETRPd4 (2 << ATIM_SMCR_ETPS_SHIFT) /* 10: ETRP frequency divided by 4 */ -# define ATIM_SMCR_ETRPd8 (3 << ATIM_SMCR_ETPS_SHIFT) /* 11: ETRP frequency divided by 8 */ -#define ATIM_SMCR_ECE (1 << 14) /* Bit 14: External clock enable */ -#define ATIM_SMCR_ETP (1 << 15) /* Bit 15: External trigger polarity */ - -/* DMA/Interrupt enable register */ - -#define ATIM_DIER_UIE (1 << 0) /* Bit 0: Update interrupt enable */ -#define ATIM_DIER_CC1IE (1 << 1) /* Bit 1: Capture/Compare 1 interrupt enable */ -#define ATIM_DIER_CC2IE (1 << 2) /* Bit 2: Capture/Compare 2 interrupt enable */ -#define ATIM_DIER_CC3IE (1 << 3) /* Bit 3: Capture/Compare 3 interrupt enable */ -#define ATIM_DIER_CC4IE (1 << 4) /* Bit 4: Capture/Compare 4 interrupt enable */ - -#define ATIM_DIER_TIE (1 << 6) /* Bit 6: Trigger interrupt enable */ - -#define ATIM_DIER_UDE (1 << 8) /* Bit 8: Update DMA request enable */ -#define ATIM_DIER_CC1DE (1 << 9) /* Bit 9: Capture/Compare 1 DMA request enable */ -#define ATIM_DIER_CC2DE (1 << 10) /* Bit 10: Capture/Compare 2 DMA request enable */ -#define ATIM_DIER_CC3DE (1 << 11) /* Bit 11: Capture/Compare 3 DMA request enable */ -#define ATIM_DIER_CC4DE (1 << 12) /* Bit 12: Capture/Compare 4 DMA request enable */ - -#define ATIM_DIER_TDE (1 << 14) /* Bit 14: Trigger DMA request enable */ - -/* Status register */ - -#define ATIM_SR_UIF (1 << 0) /* Bit 0: Update interrupt Flag */ -#define ATIM_SR_CC1IF (1 << 1) /* Bit 1: Capture/Compare 1 interrupt Flag */ -#define ATIM_SR_CC2IF (1 << 2) /* Bit 2: Capture/Compare 2 interrupt Flag */ -#define ATIM_SR_CC3IF (1 << 3) /* Bit 3: Capture/Compare 3 interrupt Flag */ -#define ATIM_SR_CC4IF (1 << 4) /* Bit 4: Capture/Compare 4 interrupt Flag */ -#define ATIM_SR_COMIF (1 << 5) /* Bit 5: COM interrupt Flag */ -#define ATIM_SR_TIF (1 << 6) /* Bit 6: Trigger interrupt Flag */ - -#define ATIM_SR_CC1OF (1 << 9) /* Bit 9: Capture/Compare 1 Overcapture Flag */ -#define ATIM_SR_CC2OF (1 << 10) /* Bit 10: Capture/Compare 2 Overcapture Flag */ -#define ATIM_SR_CC3OF (1 << 11) /* Bit 11: Capture/Compare 3 Overcapture Flag */ -#define ATIM_SR_CC4OF (1 << 12) /* Bit 12: Capture/Compare 4 Overcapture Flag */ - -/* Event generation register */ - -#define ATIM_EGR_UG (1 << 0) /* Bit 0: Update Generation */ -#define ATIM_EGR_CC1G (1 << 1) /* Bit 1: Capture/Compare 1 Generation */ -#define ATIM_EGR_CC2G (1 << 2) /* Bit 2: Capture/Compare 2 Generation */ -#define ATIM_EGR_CC3G (1 << 3) /* Bit 3: Capture/Compare 3 Generation */ -#define ATIM_EGR_CC4G (1 << 4) /* Bit 4: Capture/Compare 4 Generation */ - -#define ATIM_EGR_TG (1 << 6) /* Bit 6: Trigger Generation */ - -/* Capture/compare mode register 1 -- Output compare mode */ - -#define ATIM_CCMR1_CC1S_SHIFT (0) /* Bits 1-0: Capture/Compare 1 Selection */ -#define ATIM_CCMR1_CC1S_MASK (3 << ATIM_CCMR1_CC1S_SHIFT) - /* (See common (unshifted) bit field definitions below) */ -#define ATIM_CCMR1_OC1FE (1 << 2) /* Bit 2: Output Compare 1 Fast enable */ -#define ATIM_CCMR1_OC1PE (1 << 3) /* Bit 3: Output Compare 1 Preload enable */ -#define ATIM_CCMR1_OC1M_SHIFT (4) /* Bits 6-4: Output Compare 1 Mode */ -#define ATIM_CCMR1_OC1M_MASK (7 << ATIM_CCMR1_OC1M_SHIFT) - /* (See common (unshifted) bit field definitions below) */ -#define ATIM_CCMR1_OC1CE (1 << 7) /* Bit 7: Output Compare 1Clear Enable */ -#define ATIM_CCMR1_CC2S_SHIFT (8) /* Bits 8-9: Capture/Compare 2 Selection */ -#define ATIM_CCMR1_CC2S_MASK (3 << ATIM_CCMR1_CC2S_SHIFT) - /* (See common (unshifted) bit field definitions below) */ -#define ATIM_CCMR1_OC2FE (1 << 10) /* Bit 10: Output Compare 2 Fast enable */ -#define ATIM_CCMR1_OC2PE (1 << 11) /* Bit 11: Output Compare 2 Preload enable */ -#define ATIM_CCMR1_OC2M_SHIFT (12) /* Bits 14-12: Output Compare 2 Mode */ -#define ATIM_CCMR1_OC2M_MASK (7 << ATIM_CCMR1_OC2M_SHIFT) - /* (See common (unshifted) bit field definitions below) */ -#define ATIM_CCMR1_OC2CE (1 << 15) /* Bit 15: Output Compare 2 Clear Enable */ - -/* Common CCMR (unshifted) Capture/Compare Selection bit-field definitions */ - -#define ATIM_CCMR_CCS_CCOUT (0) /* 00: CCx channel output */ -#define ATIM_CCMR_CCS_CCIN1 (1) /* 01: CCx channel input, ICx is TIx */ -#define ATIM_CCMR_CCS_CCIN2 (2) /* 10: CCx channel input, ICx is TIy */ -#define ATIM_CCMR_CCS_CCINTRC (3) /* 11: CCx channel input, ICx is TRC */ - -/* Common CCMR (unshifted) Compare Mode bit field definitions */ - -#define ATIM_CCMR_MODE_FRZN (0) /* 000: Frozen */ -#define ATIM_CCMR_MODE_CHACT (1) /* 001: Channel x active on match */ -#define ATIM_CCMR_MODE_CHINACT (2) /* 010: Channel x inactive on match */ -#define ATIM_CCMR_MODE_OCREFTOG (3) /* 011: OCxREF toggle ATIM_CNT=ATIM_CCRx */ -#define ATIM_CCMR_MODE_OCREFLO (4) /* 100: OCxREF forced low */ -#define ATIM_CCMR_MODE_OCREFHI (5) /* 101: OCxREF forced high */ -#define ATIM_CCMR_MODE_PWM1 (6) /* 110: PWM mode 1 */ -#define ATIM_CCMR_MODE_PWM2 (7) /* 111: PWM mode 2 */ -#define ATIM_CCMR_MODE_COMBINED1 (12) /* 1100: Combined PWM mode 1 */ -#define ATIM_CCMR_MODE_COMBINED2 (13) /* 1101: Combined PWM mode 2 */ -#define ATIM_CCMR_MODE_ASYMMETRIC1 (14) /* 1110: Asymmetric PWM mode 1 */ -#define ATIM_CCMR_MODE_ASYMMETRIC2 (15) /* 1111: Asymmetric PWM mode 2 */ - -/* Capture/compare mode register 1 -- Input capture mode */ - - /* Bits 1-0:(same as output compare mode) */ -#define ATIM_CCMR1_IC1PSC_SHIFT (2) /* Bits 3-2: Input Capture 1 Prescaler */ -#define ATIM_CCMR1_IC1PSC_MASK (3 << ATIM_CCMR1_IC1PSC_SHIFT) - /* (See common (unshifted) bit field definitions below) */ -#define ATIM_CCMR1_IC1F_SHIFT (4) /* Bits 7-4: Input Capture 1 Filter */ -#define ATIM_CCMR1_IC1F_MASK (0x0f << ATIM_CCMR1_IC1F_SHIFT) - /* (See common (unshifted) bit field definitions below) */ - /* Bits 9:8 (same as output compare mode) */ -#define ATIM_CCMR1_IC2PSC_SHIFT (10) /* Bits 11:10: Input Capture 2 Prescaler */ -#define ATIM_CCMR1_IC2PSC_MASK (3 << ATIM_CCMR1_IC2PSC_SHIFT) - /* (See common (unshifted) bit field definitions below) */ -#define ATIM_CCMR1_IC2F_SHIFT (12) /* Bits 15-12: Input Capture 2 Filter */ -#define ATIM_CCMR1_IC2F_MASK (0x0f << ATIM_CCMR1_IC2F_SHIFT) - /* (See common (unshifted) bit field definitions below) */ - -/* Common CCMR (unshifted) Input Capture Prescaler bit-field definitions */ - -#define ATIM_CCMR_ICPSC_NOPSC (0) /* 00: no prescaler, capture each edge */ -#define ATIM_CCMR_ICPSC_EVENTS2 (1) /* 01: capture once every 2 events */ -#define ATIM_CCMR_ICPSC_EVENTS4 (2) /* 10: capture once every 4 events */ -#define ATIM_CCMR_ICPSC_EVENTS8 (3) /* 11: capture once every 8 events */ - -/* Common CCMR (unshifted) Input Capture Filter bit-field definitions */ - -#define ATIM_CCMR_ICF_NOFILT (0) /* 0000: No filter, sampling at fDTS */ -#define ATIM_CCMR_ICF_FCKINT2 (1) /* 0001: fSAMPLING=fCK_INT, N=2 */ -#define ATIM_CCMR_ICF_FCKINT4 (2) /* 0010: fSAMPLING=fCK_INT, N=4 */ -#define ATIM_CCMR_ICF_FCKINT8 (3) /* 0011: fSAMPLING=fCK_INT, N=8 */ -#define ATIM_CCMR_ICF_FDTSd26 (4) /* 0100: fSAMPLING=fDTS/2, N=6 */ -#define ATIM_CCMR_ICF_FDTSd28 (5) /* 0101: fSAMPLING=fDTS/2, N=8 */ -#define ATIM_CCMR_ICF_FDTSd46 (6) /* 0110: fSAMPLING=fDTS/4, N=6 */ -#define ATIM_CCMR_ICF_FDTSd48 (7) /* 0111: fSAMPLING=fDTS/4, N=8 */ -#define ATIM_CCMR_ICF_FDTSd86 (8) /* 1000: fSAMPLING=fDTS/8, N=6 */ -#define ATIM_CCMR_ICF_FDTSd88 (9) /* 1001: fSAMPLING=fDTS/8, N=8 */ -#define ATIM_CCMR_ICF_FDTSd165 (10) /* 1010: fSAMPLING=fDTS/16, N=5 */ -#define ATIM_CCMR_ICF_FDTSd166 (11) /* 1011: fSAMPLING=fDTS/16, N=6 */ -#define ATIM_CCMR_ICF_FDTSd168 (12) /* 1100: fSAMPLING=fDTS/16, N=8 */ -#define ATIM_CCMR_ICF_FDTSd325 (13) /* 1101: fSAMPLING=fDTS/32, N=5 */ -#define ATIM_CCMR_ICF_FDTSd326 (14) /* 1110: fSAMPLING=fDTS/32, N=6 */ -#define ATIM_CCMR_ICF_FDTSd328 (15) /* 1111: fSAMPLING=fDTS/32, N=8 */ - -/* Capture/compare mode register 2 - Output Compare mode */ - -#define ATIM_CCMR2_CC3S_SHIFT (0) /* Bits 1-0: Capture/Compare 3 Selection */ -#define ATIM_CCMR2_CC3S_MASK (3 << ATIM_CCMR2_CC3S_SHIFT) - /* (See common (unshifted) bit field definitions above) */ -#define ATIM_CCMR2_OC3FE (1 << 2) /* Bit 2: Output Compare 3 Fast enable */ -#define ATIM_CCMR2_OC3PE (1 << 3) /* Bit 3: Output Compare 3 Preload enable */ -#define ATIM_CCMR2_OC3M_SHIFT (4) /* Bits 6-4: Output Compare 3 Mode */ -#define ATIM_CCMR2_OC3M_MASK (7 << ATIM_CCMR2_OC3M_SHIFT) - /* (See common (unshifted) bit field definitions above) */ -#define ATIM_CCMR2_OC3CE (1 << 7) /* Bit 7: Output Compare 3 Clear Enable */ -#define ATIM_CCMR2_CC4S_SHIFT (8) /* Bits 9-8: Capture/Compare 4 Selection */ -#define ATIM_CCMR2_CC4S_MASK (3 << ATIM_CCMR2_CC4S_SHIFT) - /* (See common (unshifted) bit field definitions above) */ -#define ATIM_CCMR2_OC4FE (1 << 10) /* Bit 10: Output Compare 4 Fast enable */ -#define ATIM_CCMR2_OC4PE (1 << 11) /* Bit 11: Output Compare 4 Preload enable */ -#define ATIM_CCMR2_OC4M_SHIFT (12) /* Bits 14-12: Output Compare 4 Mode */ -#define ATIM_CCMR2_OC4M_MASK (7 << ATIM_CCMR2_OC4M_SHIFT) - /* (See common (unshifted) bit field definitions above) */ -#define ATIM_CCMR2_OC4CE (1 << 15) /* Bit 15: Output Compare 4 Clear Enable */ - -/* Capture/compare mode register 2 - Input Capture Mode */ - - /* Bits 1-0:(same as output compare mode) */ -#define ATIM_CCMR2_IC3PSC_SHIFT (2) /* Bits 3-2: Input Capture 3 Prescaler */ -#define ATIM_CCMR1_IC3PSC_MASK (3 << ATIM_CCMR2_IC3PSC_SHIFT) - /* (See common (unshifted) bit field definitions above) */ -#define ATIM_CCMR2_IC3F_SHIFT (4) /* Bits 7-4: Input Capture 3 Filter */ -#define ATIM_CCMR2_IC3F_MASK (0x0f << ATIM_CCMR2_IC3F_SHIFT) - /* (See common (unshifted) bit field definitions above) */ - /* Bits 9:8 (same as output compare mode) */ -#define ATIM_CCMR2_IC4PSC_SHIFT (10) /* Bits 11:10: Input Capture 4 Prescaler */ -#define ATIM_CCMR2_IC4PSC_MASK (3 << ATIM_CCMR2_IC4PSC_SHIFT) - /* (See common (unshifted) bit field definitions above) */ -#define ATIM_CCMR2_IC4F_SHIFT (12) /* Bits 15-12: Input Capture 4 Filter */ -#define ATIM_CCMR2_IC4F_MASK (0x0f << ATIM_CCMR2_IC4F_SHIFT) - /* (See common (unshifted) bit field definitions above) */ - -/* Capture/compare enable register */ - -#define ATIM_CCER_CC1E (1 << 0) /* Bit 0: Capture/Compare 1 output enable */ -#define ATIM_CCER_CC1P (1 << 1) /* Bit 1: Capture/Compare 1 output Polarity */ -#define ATIM_CCER_CC1NE (1 << 2) /* Bit 2: Capture/Compare 1 Complementary output enable */ -#define ATIM_CCER_CC1NP (1 << 3) /* Bit 3: Capture/Compare 1 Complementary output polarity */ -#define ATIM_CCER_CC2E (1 << 4) /* Bit 4: Capture/Compare 2 output enable */ -#define ATIM_CCER_CC2P (1 << 5) /* Bit 5: Capture/Compare 2 output Polarity */ -#define ATIM_CCER_CC2NE (1 << 6) /* Bit 6: Capture/Compare 2 Complementary output enable */ -#define ATIM_CCER_CC2NP (1 << 7) /* Bit 7: Capture/Compare 2 Complementary output polarity */ -#define ATIM_CCER_CC3E (1 << 8) /* Bit 8: Capture/Compare 3 output enable */ -#define ATIM_CCER_CC3P (1 << 9) /* Bit 9: Capture/Compare 3 output Polarity */ -#define ATIM_CCER_CC3NE (1 << 10) /* Bit 10: Capture/Compare 3 Complementary output enable */ -#define ATIM_CCER_CC3NP (1 << 11) /* Bit 11: Capture/Compare 3 Complementary output polarity */ -#define ATIM_CCER_CC4E (1 << 12) /* Bit 12: Capture/Compare 4 output enable */ -#define ATIM_CCER_CC4P (1 << 13) /* Bit 13: Capture/Compare 4 output Polarity */ -#define ATIM_CCER_CC4NP (1 << 15) /* Bit 15: Capture/Compare 4 Complementary output polarity */ - - -/* 16-bit counter register */ - -#define ATIM_CNT_SHIFT (0) /* Bits 0-15: Timer counter value */ -#define ATIM_CNT_MASK (0xffff << ATIM_CNT_SHIFT) - -/* Repetition counter register */ - -#define ATIM_RCR_REP_SHIFT (0) /* Bits 0-7: Repetition Counter Value */ -#define ATIM_RCR_REP_MASK (0xff << ATIM_RCR_REP_SHIFT) - -#define ATIM_RCR_REP_MAX 128 - -/* Capture/compare registers (CCR) */ - - -#define ATIM_CCR_MASK (0xffff) - -/* Break and dead-time register */ - -#define ATIM_BDTR_DTG_SHIFT (0) /* Bits 7:0 [7:0]: Dead-Time Generator set-up */ -#define ATIM_BDTR_DTG_MASK (0xff << ATIM_BDTR_DTG_SHIFT) -#define ATIM_BDTR_LOCK_SHIFT (8) /* Bits 9:8 [1:0]: Lock Configuration */ -#define ATIM_BDTR_LOCK_MASK (3 << ATIM_BDTR_LOCK_SHIFT) -# define ATIM_BDTR_LOCKOFF (0 << ATIM_BDTR_LOCK_SHIFT) /* 00: LOCK OFF - No bit is write protected */ -# define ATIM_BDTR_LOCK1 (1 << ATIM_BDTR_LOCK_SHIFT) /* 01: LOCK Level 1 protection */ -# define ATIM_BDTR_LOCK2 (2 << ATIM_BDTR_LOCK_SHIFT) /* 10: LOCK Level 2 protection */ -# define ATIM_BDTR_LOCK3 (3 << ATIM_BDTR_LOCK_SHIFT) /* 11: LOCK Level 3 protection */ */ -#define ATIM_BDTR_OSSI (1 << 10) /* Bit 10: Off-State Selection for Idle mode */ -#define ATIM_BDTR_OSSR (1 << 11) /* Bit 11: Off-State Selection for Run mode */ -#define ATIM_BDTR_BKE (1 << 12) /* Bit 12: Break enable */ -#define ATIM_BDTR_BKP (1 << 13) /* Bit 13: Break Polarity */ -#define ATIM_BDTR_AOE (1 << 14) /* Bit 14: Automatic Output enable */ -#define ATIM_BDTR_MOE (1 << 15) /* Bit 15: Main Output enable */ - -/* DMA control register */ - -#define ATIM_DCR_DBA_SHIFT (0) /* Bits 4-0: DMA Base Address */ -#define ATIM_DCR_DBA_MASK (0x1f << ATIM_DCR_DBA_SHIFT) -#define ATIM_DCR_DBL_SHIFT (8) /* Bits 12-8: DMA Burst Length */ -#define ATIM_DCR_DBL_MASK (0x1f << ATIM_DCR_DBL_SHIFT) -# define ATIM_DCR_DBL(n) (((n)-1) << ATIM_DCR_DBL_SHIFT) /* n transfers, n = 1..18 */ - -/* Control register 1 (TIM2-5 and TIM9-14) */ - -#define GTIM_CR1_CEN (1 << 0) /* Bit 0: Counter enable */ -#define GTIM_CR1_UDIS (1 << 1) /* Bit 1: Update Disable */ -#define GTIM_CR1_URS (1 << 2) /* Bit 2: Update Request Source */ -#define GTIM_CR1_OPM (1 << 3) /* Bit 3: One Pulse Mode (TIM2-5, 9, and 12 only) */ -#define GTIM_CR1_DIR (1 << 4) /* Bit 4: Direction (TIM2-5 only) */ -#define GTIM_CR1_CMS_SHIFT (5) /* Bits 6-5: Center-aligned Mode Selection (TIM2-5 only) */ -#define GTIM_CR1_CMS_MASK (3 << GTIM_CR1_CMS_SHIFT) -# define GTIM_CR1_EDGE (0 << GTIM_CR1_CMS_SHIFT) /* 00: Edge-aligned mode. */ -# define GTIM_CR1_CENTER1 (1 << GTIM_CR1_CMS_SHIFT) /* 01: Center-aligned mode 1 */ -# define GTIM_CR1_CENTER2 (2 << GTIM_CR1_CMS_SHIFT) /* 10: Center-aligned mode 2 */ -# define GTIM_CR1_CENTER3 (3 << GTIM_CR1_CMS_SHIFT) /* 11: Center-aligned mode 3 */ -#define GTIM_CR1_ARPE (1 << 7) /* Bit 7: Auto-Reload Preload enable */ -#define GTIM_CR1_CKD_SHIFT (8) /* Bits 9-8: Clock Division */ -#define GTIM_CR1_CKD_MASK (3 << GTIM_CR1_CKD_SHIFT) -# define GTIM_CR1_TCKINT (0 << GTIM_CR1_CKD_SHIFT) /* 00: tDTS = tCK_INT */ -# define GTIM_CR1_2TCKINT (1 << GTIM_CR1_CKD_SHIFT) /* 01: tDTS = 2 x tCK_INT */ -# define GTIM_CR1_4TCKINT (2 << GTIM_CR1_CKD_SHIFT) /* 10: tDTS = 4 x tCK_INT */ - -/* Control register 2 (TIM2-5, TIM9-12, and TIM15-17 only) */ - -#define GTIM_CR2_CCPC (1 << 0) /* Bit 0: Capture/compare preloaded control (TIM15-17 only) */ -#define GTIM_CR2_CCUS (1 << 2) /* Bit 2: Capture/compare control update selection (TIM15-17 only) */ -#define GTIM_CR2_CCDS (1 << 3) /* Bit 3: Capture/Compare DMA Selection (TIM2-5,1,&16 only) */ -#define GTIM_CR2_MMS_SHIFT (4) /* Bits 6-4: Master Mode Selection (not TIM16) */ -#define GTIM_CR2_MMS_MASK (7 << GTIM_CR2_MMS_SHIFT) -# define GTIM_CR2_MMS_RESET (0 << GTIM_CR2_MMS_SHIFT) /* 000: Reset */ -# define GTIM_CR2_MMS_ENABLE (1 << GTIM_CR2_MMS_SHIFT) /* 001: Enable */ -# define GTIM_CR2_MMS_UPDATE (2 << GTIM_CR2_MMS_SHIFT) /* 010: Update */ -# define GTIM_CR2_MMS_COMPP (3 << GTIM_CR2_MMS_SHIFT) /* 011: Compare Pulse */ -# define GTIM_CR2_MMS_OC1REF (4 << GTIM_CR2_MMS_SHIFT) /* 100: Compare - OC1REF signal is used as trigger output (TRGO) */ -# define GTIM_CR2_MMS_OC2REF (5 << GTIM_CR2_MMS_SHIFT) /* 101: Compare - OC2REF signal is used as trigger output (TRGO) */ -# define GTIM_CR2_MMS_OC3REF (6 << GTIM_CR2_MMS_SHIFT) /* 110: Compare - OC3REF signal is used as trigger output (TRGO, TIM2-5 and TIM15 only) */ -# define GTIM_CR2_MMS_OC4REF (7 << GTIM_CR2_MMS_SHIFT) /* 111: Compare - OC4REF signal is used as trigger output (TRGO, TIM2-5 and TIM15 only) */ -#define GTIM_CR2_TI1S (1 << 7) /* Bit 7: TI1 Selection (not TIM16) */ -#define GTIM_CR2_OIS1 (1 << 8) /* Bit 8: COutput Idle state 1 (OC1 output) (TIM15-17 only) */ -#define GTIM_CR2_OIS1N (1 << 9) /* Bit 9: Output Idle state 1 (OC1N output) (TIM15-17 only) */ -#define GTIM_CR2_OIS2 (1 << 10) /* Bit 10: Output idle state 2 (OC2 output) (TIM15 only) */ - -/* Slave mode control register (TIM2-5 and TIM15 only) */ - -#define GTIM_SMCR_SMS_SHIFT (0) /* Bits 2-0: Slave Mode Selection */ -#define GTIM_SMCR_SMS_MASK (7 << GTIM_SMCR_SMS_SHIFT) -# define GTIM_SMCR_DISAB (0 << GTIM_SMCR_SMS_SHIFT) /* 000: Slave mode disabled */ -# define GTIM_SMCR_ENCMD1 (1 << GTIM_SMCR_SMS_SHIFT) /* 001: Encoder mode 1 */ -# define GTIM_SMCR_ENCMD2 (2 << GTIM_SMCR_SMS_SHIFT) /* 010: Encoder mode 2 */ -# define GTIM_SMCR_ENCMD3 (3 << GTIM_SMCR_SMS_SHIFT) /* 011: Encoder mode 3 */ -# define GTIM_SMCR_RESET (4 << GTIM_SMCR_SMS_SHIFT) /* 100: Reset Mode */ -# define GTIM_SMCR_GATED (5 << GTIM_SMCR_SMS_SHIFT) /* 101: Gated Mode */ -# define GTIM_SMCR_TRIGGER (6 << GTIM_SMCR_SMS_SHIFT) /* 110: Trigger Mode */ -# define GTIM_SMCR_EXTCLK1 (7 << GTIM_SMCR_SMS_SHIFT) /* 111: External Clock Mode 1 */ -#define GTIM_SMCR_TS_SHIFT (4) /* Bits 6-4: Trigger Selection */ -#define GTIM_SMCR_TS_MASK (7 << GTIM_SMCR_TS_SHIFT) -# define GTIM_SMCR_ITR0 (0 << GTIM_SMCR_TS_SHIFT) /* 000: Internal Trigger 0 (ITR0). TIM1 */ -# define GTIM_SMCR_ITR1 (1 << GTIM_SMCR_TS_SHIFT) /* 001: Internal Trigger 1 (ITR1). TIM2 */ -# define GTIM_SMCR_ITR2 (2 << GTIM_SMCR_TS_SHIFT) /* 010: Internal Trigger 2 (ITR2). TIM3 */ -# define GTIM_SMCR_ITR3 (3 << GTIM_SMCR_TS_SHIFT) /* 011: Internal Trigger 3 (ITR3). TIM4 */ -# define GTIM_SMCR_TI1FED (4 << GTIM_SMCR_TS_SHIFT) /* 100: TI1 Edge Detector (TI1F_ED) */ -# define GTIM_SMCR_TI1FP1 (5 << GTIM_SMCR_TS_SHIFT) /* 101: Filtered Timer Input 1 (TI1FP1) */ -# define GTIM_SMCR_TI2FP2 (6 << GTIM_SMCR_TS_SHIFT) /* 110: Filtered Timer Input 2 (TI2FP2) */ -# define GTIM_SMCR_ETRF (7 << GTIM_SMCR_TS_SHIFT) /* 111: External Trigger input (ETRF) */ -#define GTIM_SMCR_MSM (1 << 7) /* Bit 7: Master/Slave mode */ -#define GTIM_SMCR_ETF_SHIFT (8) /* Bits 11-8: External Trigger Filter (not TIM15) */ -#define GTIM_SMCR_ETF_MASK (0x0f << GTIM_SMCR_ETF_SHIFT) -# define GTIM_SMCR_NOFILT (0 << GTIM_SMCR_ETF_SHIFT) /* 0000: No filter, sampling is done at fDTS */ -# define GTIM_SMCR_FCKINT2 (1 << GTIM_SMCR_ETF_SHIFT) /* 0001: fSAMPLING=fCK_INT, N=2 */ -# define GTIM_SMCR_FCKINT4 (2 << GTIM_SMCR_ETF_SHIFT) /* 0010: fSAMPLING=fCK_INT, N=4 */ -# define GTIM_SMCR_FCKINT8 (3 << GTIM_SMCR_ETF_SHIFT) /* 0011: fSAMPLING=fCK_INT, N=8 */ -# define GTIM_SMCR_FDTSd26 (4 << GTIM_SMCR_ETF_SHIFT) /* 0100: fSAMPLING=fDTS/2, N=6 */ -# define GTIM_SMCR_FDTSd28 (5 << GTIM_SMCR_ETF_SHIFT) /* 0101: fSAMPLING=fDTS/2, N=8 */ -# define GTIM_SMCR_FDTSd36 (6 << GTIM_SMCR_ETF_SHIFT) /* 0110: fSAMPLING=fDTS/4, N=6 */ -# define GTIM_SMCR_FDTSd38 (7 << GTIM_SMCR_ETF_SHIFT) /* 0111: fSAMPLING=fDTS/4, N=8 */ -# define GTIM_SMCR_FDTSd86 (8 << GTIM_SMCR_ETF_SHIFT) /* 1000: fSAMPLING=fDTS/8, N=6 */ -# define GTIM_SMCR_FDTSd88 (9 << GTIM_SMCR_ETF_SHIFT) /* 1001: fSAMPLING=fDTS/8, N=8 */ -# define GTIM_SMCR_FDTSd165 (10 << GTIM_SMCR_ETF_SHIFT) /* 1010: fSAMPLING=fDTS/16, N=5 */ -# define GTIM_SMCR_FDTSd166 (11 << GTIM_SMCR_ETF_SHIFT) /* 1011: fSAMPLING=fDTS/16, N=6 */ -# define GTIM_SMCR_FDTSd168 (12 << GTIM_SMCR_ETF_SHIFT) /* 1100: fSAMPLING=fDTS/16, N=8 */ -# define GTIM_SMCR_FDTSd325 (13 << GTIM_SMCR_ETF_SHIFT) /* 1101: fSAMPLING=fDTS/32, N=5 */ -# define GTIM_SMCR_FDTSd326 (14 << GTIM_SMCR_ETF_SHIFT) /* 1110: fSAMPLING=fDTS/32, N=6 */ -# define GTIM_SMCR_FDTSd328 (15 << GTIM_SMCR_ETF_SHIFT) /* 1111: fSAMPLING=fDTS/32, N=8 */ -#define GTIM_SMCR_ETPS_SHIFT (12) /* Bits 13-12: External Trigger Prescaler (not TIM15) */ -#define GTIM_SMCR_ETPS_MASK (3 << GTIM_SMCR_ETPS_SHIFT) -# define GTIM_SMCR_PSCOFF (0 << GTIM_SMCR_ETPS_SHIFT) /* 00: Prescaler OFF */ -# define GTIM_SMCR_ETRPd2 (1 << GTIM_SMCR_ETPS_SHIFT) /* 01: ETRP frequency divided by 2 */ -# define GTIM_SMCR_ETRPd4 (2 << GTIM_SMCR_ETPS_SHIFT) /* 10: ETRP frequency divided by 4 */ -# define GTIM_SMCR_ETRPd8 (3 << GTIM_SMCR_ETPS_SHIFT) /* 11: ETRP frequency divided by 8 */ -#define GTIM_SMCR_ECE (1 << 14) /* Bit 14: External Clock enable */ -#define GTIM_SMCR_ETP (1 << 15) /* Bit 15: External Trigger Polarity */ - -/* DMA/Interrupt enable register (TIM2-5 and TIM9-14) */ - -#define GTIM_DIER_UIE (1 << 0) /* Bit 0: Update interrupt enable */ -#define GTIM_DIER_CC1IE (1 << 1) /* Bit 1: Capture/Compare 1 interrupt enable */ -#define GTIM_DIER_CC2IE (1 << 2) /* Bit 2: Capture/Compare 2 interrupt enable (TIM2-5,9,12,&15 only) */ -#define GTIM_DIER_CC3IE (1 << 3) /* Bit 3: Capture/Compare 3 interrupt enable (TIM2-5 only) */ -#define GTIM_DIER_CC4IE (1 << 4) /* Bit 4: Capture/Compare 4 interrupt enable (TIM2-5 only) */ -#define GTIM_DIER_COMIE (1 << 5) /* Bit 5: COM interrupt enable (TIM15-17 only) */ -#define GTIM_DIER_TIE (1 << 6) /* Bit 6: Trigger interrupt enable (TIM2-5,9,&12 only) */ -#define GTIM_DIER_BIE (1 << 7) /* Bit 7: Break interrupt enable (TIM15-17 only) */ -#define GTIM_DIER_UDE (1 << 8) /* Bit 8: Update DMA request enable (TIM2-5&15-17 only) */ -#define GTIM_DIER_CC1DE (1 << 9) /* Bit 9: Capture/Compare 1 DMA request enable (TIM2-5&15-17 only) */ -#define GTIM_DIER_CC2DE (1 << 10) /* Bit 10: Capture/Compare 2 DMA request enable (TIM2-5&15 only) */ -#define GTIM_DIER_CC3DE (1 << 11) /* Bit 11: Capture/Compare 3 DMA request enable (TIM2-5 only) */ -#define GTIM_DIER_CC4DE (1 << 12) /* Bit 12: Capture/Compare 4 DMA request enable (TIM2-5 only) */ -#define GTIM_DIER_COMDE (1 << 13) /* Bit 13: COM DMA request enable (TIM15-17 only) */ -#define GTIM_DIER_TDE (1 << 14) /* Bit 14: Trigger DMA request enable (TIM2-5&15-17 only) */ - -/* Status register */ - -#define GTIM_SR_UIF (1 << 0) /* Bit 0: Update interrupt flag */ -#define GTIM_SR_CC1IF (1 << 1) /* Bit 1: Capture/compare 1 interrupt flag */ -#define GTIM_SR_CC2IF (1 << 2) /* Bit 2: Capture/Compare 2 interrupt flag (TIM2-5,9,12,&15 only) */ -#define GTIM_SR_CC3IF (1 << 3) /* Bit 3: Capture/Compare 3 interrupt flag (TIM2-5 only) */ -#define GTIM_SR_CC4IF (1 << 4) /* Bit 4: Capture/Compare 4 interrupt flag (TIM2-5 only) */ -#define GTIM_SR_COMIF (1 << 5) /* Bit 5: COM interrupt flag (TIM15-17 only) */ -#define GTIM_SR_TIF (1 << 6) /* Bit 6: Trigger interrupt Flag (TIM2-5,9,12&15-17 only) */ -#define GTIM_SR_BIF (1 << 7) /* Bit 7: Break interrupt flag (TIM15-17 only) */ -#define GTIM_SR_CC1OF (1 << 9) /* Bit 9: Capture/Compare 1 Overcapture flag */ -#define GTIM_SR_CC2OF (1 << 10) /* Bit 10: Capture/Compare 2 Overcapture flag (TIM2-5,9,12&15 only) */ -#define GTIM_SR_CC3OF (1 << 11) /* Bit 11: Capture/Compare 3 Overcapture flag (TIM2-5 only) */ -#define GTIM_SR_CC4OF (1 << 12) /* Bit 12: Capture/Compare 4 Overcapture flag (TIM2-5 only) */ - -/* Event generation register (TIM2-5 and TIM9-14) */ - -#define GTIM_EGR_UG (1 << 0) /* Bit 0: Update generation */ -#define GTIM_EGR_CC1G (1 << 1) /* Bit 1: Capture/compare 1 generation */ -#define GTIM_EGR_CC2G (1 << 2) /* Bit 2: Capture/compare 2 generation (TIM2-5,9,12,&15 only) */ -#define GTIM_EGR_CC3G (1 << 3) /* Bit 3: Capture/compare 3 generation (TIM2-5 only) */ -#define GTIM_EGR_CC4G (1 << 4) /* Bit 4: Capture/compare 4 generation (TIM2-5 only) */ -#define GTIM_EGR_COMIG (1 << 5) /* Bit 5: Capture/Compare control update generation (TIM15-17 only) */ -#define GTIM_EGR_TG (1 << 6) /* Bit 6: Trigger generation (TIM2-5,9,12&16-17 only) */ -#define GTIM_EGR_BG (1 << 7) /* Bit 7: Break generation (TIM15-17 only) */ - -/* Capture/compare mode register 1 - Output compare mode (TIM2-5 and TIM9-14) */ - -#define GTIM_CCMR1_CC1S_SHIFT (0) /* Bits 1-0: Capture/Compare 1 Selection */ -#define GTIM_CCMR1_CC1S_MASK (3 << GTIM_CCMR1_CC1S_SHIFT) - /* (See common CCMR Capture/Compare Selection definitions below) */ -#define GTIM_CCMR1_OC1FE (1 << 2) /* Bit 2: Output Compare 1 Fast enable */ -#define GTIM_CCMR1_OC1PE (1 << 3) /* Bit 3: Output Compare 1 Preload enable */ -#define GTIM_CCMR1_OC1M_SHIFT (4) /* Bits 6-4: Output Compare 1 Mode */ -#define GTIM_CCMR1_OC1M_MASK (7 << GTIM_CCMR1_OC1M_SHIFT) - /* (See common CCMR Output Compare Mode definitions below) */ -#define GTIM_CCMR1_OC1CE (1 << 7) /* Bit 7: Output Compare 1Clear Enable */ -#define GTIM_CCMR1_CC2S_SHIFT (8) /* Bits 9-8: Capture/Compare 2 Selection */ -#define GTIM_CCMR1_CC2S_MASK (3 << GTIM_CCMR1_CC2S_SHIFT) - /* (See common CCMR Capture/Compare Selection definitions below) */ -#define GTIM_CCMR1_OC2FE (1 << 10) /* Bit 10: Output Compare 2 Fast enable */ -#define GTIM_CCMR1_OC2PE (1 << 11) /* Bit 11: Output Compare 2 Preload enable */ -#define GTIM_CCMR1_OC2M_SHIFT (12) /* Bits 14-12: Output Compare 2 Mode */ -#define GTIM_CCMR1_OC2M_MASK (7 << GTIM_CCMR1_OC2M_SHIFT) - /* (See common CCMR Output Compare Mode definitions below) */ -#define GTIM_CCMR1_OC2CE (1 << 15) /* Bit 15: Output Compare 2 Clear Enable */ - -/* Common CCMR (unshifted) Capture/Compare Selection bit-field definitions */ - -#define GTIM_CCMR_CCS_CCOUT (0) /* 00: CCx channel output */ -#define GTIM_CCMR_CCS_CCIN1 (1) /* 01: CCx channel input, ICx is TIx */ -#define GTIM_CCMR_CCS_CCIN2 (2) /* 10: CCx channel input, ICx is TIy */ -#define GTIM_CCMR_CCS_CCINTRC (3) /* 11: CCx channel input, ICx is TRC */ - -/* Common CCMR (unshifted) Compare Mode bit field definitions */ - -#define GTIM_CCMR_MODE_FRZN (0) /* 000: Frozen */ -#define GTIM_CCMR_MODE_CHACT (1) /* 001: Channel x active on match */ -#define GTIM_CCMR_MODE_CHINACT (2) /* 010: Channel x inactive on match */ -#define GTIM_CCMR_MODE_OCREFTOG (3) /* 011: OCxREF toggle ATIM_CNT=ATIM_CCRx */ -#define GTIM_CCMR_MODE_OCREFLO (4) /* 100: OCxREF forced low */ -#define GTIM_CCMR_MODE_OCREFHI (5) /* 101: OCxREF forced high */ -#define GTIM_CCMR_MODE_PWM1 (6) /* 110: PWM mode 1 */ -#define GTIM_CCMR_MODE_PWM2 (7) /* 111: PWM mode 2 */ - -/* Capture/compare mode register 1 - Input capture mode (TIM2-5 and TIM9-14) */ - - /* Bits 1-0 (Same as Output Compare Mode) */ -#define GTIM_CCMR1_IC1PSC_SHIFT (2) /* Bits 3-2: Input Capture 1 Prescaler */ -#define GTIM_CCMR1_IC1PSC_MASK (3 << GTIM_CCMR1_IC1PSC_SHIFT) - /* (See common CCMR Input Capture Prescaler definitions below) */ -#define GTIM_CCMR1_IC1F_SHIFT (4) /* Bits 7-4: Input Capture 1 Filter */ -#define GTIM_CCMR1_IC1F_MASK (0x0f << GTIM_CCMR1_IC1F_SHIFT) - /* (See common CCMR Input Capture Filter definitions below) */ - /* Bits 9-8: (Same as Output Compare Mode) */ -#define GTIM_CCMR1_IC2PSC_SHIFT (10) /* Bits 11-10: Input Capture 2 Prescaler */ -#define GTIM_CCMR1_IC2PSC_MASK (3 << GTIM_CCMR1_IC2PSC_SHIFT) - /* (See common CCMR Input Capture Prescaler definitions below) */ -#define GTIM_CCMR1_IC2F_SHIFT (12) /* Bits 15-12: Input Capture 2 Filter */ -#define GTIM_CCMR1_IC2F_MASK (0x0f << GTIM_CCMR1_IC2F_SHIFT) - /* (See common CCMR Input Capture Filter definitions below) */ - -/* Common CCMR (unshifted) Input Capture Prescaler bit-field definitions */ - -#define GTIM_CCMR_ICPSC_NOPSC (0) /* 00: no prescaler, capture each edge */ -#define GTIM_CCMR_ICPSC_EVENTS2 (1) /* 01: capture once every 2 events */ -#define GTIM_CCMR_ICPSC_EVENTS4 (2) /* 10: capture once every 4 events */ -#define GTIM_CCMR_ICPSC_EVENTS8 (3) /* 11: capture once every 8 events */ - -/* Common CCMR (unshifted) Input Capture Filter bit-field definitions */ - -#define GTIM_CCMR_ICF_NOFILT (0) /* 0000: No filter, sampling at fDTS */ -#define GTIM_CCMR_ICF_FCKINT2 (1) /* 0001: fSAMPLING=fCK_INT, N=2 */ -#define GTIM_CCMR_ICF_FCKINT4 (2) /* 0010: fSAMPLING=fCK_INT, N=4 */ -#define GTIM_CCMR_ICF_FCKINT8 (3) /* 0011: fSAMPLING=fCK_INT, N=8 */ -#define GTIM_CCMR_ICF_FDTSd26 (4) /* 0100: fSAMPLING=fDTS/2, N=6 */ -#define GTIM_CCMR_ICF_FDTSd28 (5) /* 0101: fSAMPLING=fDTS/2, N=8 */ -#define GTIM_CCMR_ICF_FDTSd46 (6) /* 0110: fSAMPLING=fDTS/4, N=6 */ -#define GTIM_CCMR_ICF_FDTSd48 (7) /* 0111: fSAMPLING=fDTS/4, N=8 */ -#define GTIM_CCMR_ICF_FDTSd86 (8) /* 1000: fSAMPLING=fDTS/8, N=6 */ -#define GTIM_CCMR_ICF_FDTSd88 (9) /* 1001: fSAMPLING=fDTS/8, N=8 */ -#define GTIM_CCMR_ICF_FDTSd165 (10) /* 1010: fSAMPLING=fDTS/16, N=5 */ -#define GTIM_CCMR_ICF_FDTSd166 (11) /* 1011: fSAMPLING=fDTS/16, N=6 */ -#define GTIM_CCMR_ICF_FDTSd168 (12) /* 1100: fSAMPLING=fDTS/16, N=8 */ -#define GTIM_CCMR_ICF_FDTSd325 (13) /* 1101: fSAMPLING=fDTS/32, N=5 */ -#define GTIM_CCMR_ICF_FDTSd326 (14) /* 1110: fSAMPLING=fDTS/32, N=6 */ -#define GTIM_CCMR_ICF_FDTSd328 (15) /* 1111: fSAMPLING=fDTS/32, N=8 */ - -/* Capture/compare mode register 2 - Output Compare mode (TIM2-5 only) */ - -#define GTIM_CCMR2_CC3S_SHIFT (0) /* Bits 1-0: Capture/Compare 3 Selection */ -#define GTIM_CCMR2_CC3S_MASK (3 << GTIM_CCMR2_CC3S_SHIFT) - /* (See common CCMR Capture/Compare Selection definitions above) */ -#define GTIM_CCMR2_OC3FE (1 << 2) /* Bit 2: Output Compare 3 Fast enable */ -#define GTIM_CCMR2_OC3PE (1 << 3) /* Bit 3: Output Compare 3 Preload enable */ -#define GTIM_CCMR2_OC3M_SHIFT (4) /* Bits 6-4: Output Compare 3 Mode */ -#define GTIM_CCMR2_OC3M_MASK (7 << GTIM_CCMR2_OC3M_SHIFT) - /* (See common CCMR Output Compare Mode definitions above) */ -#define GTIM_CCMR2_OC3CE (1 << 7) /* Bit 7: Output Compare 3 Clear Enable */ -#define GTIM_CCMR2_CC4S_SHIFT (8) /* Bits 9-8: Capture/Compare 4 Selection */ -#define GTIM_CCMR2_CC4S_MASK (3 << GTIM_CCMR2_CC4S_SHIFT) - /* (See common CCMR Capture/Compare Selection definitions above) */ -#define GTIM_CCMR2_OC4FE (1 << 10) /* Bit 10: Output Compare 4 Fast enable */ -#define GTIM_CCMR2_OC4PE (1 << 11) /* Bit 11: Output Compare 4 Preload enable */ -#define GTIM_CCMR2_OC4M_SHIFT (12) /* Bits 14-12: Output Compare 4 Mode */ -#define GTIM_CCMR2_OC4M_MASK (7 << GTIM_CCMR2_OC4M_SHIFT) - /* (See common CCMR Output Compare Mode definitions above) */ -#define GTIM_CCMR2_OC4CE (1 << 15) /* Bit 15: Output Compare 4 Clear Enable */ - -/* Capture/compare mode register 2 - Input capture mode (TIM2-5 only) */ - - /* Bits 1-0 (Same as Output Compare Mode) */ -#define GTIM_CCMR2_IC3PSC_SHIFT (2) /* Bits 3-2: Input Capture 3 Prescaler */ -#define GTIM_CCMR2_IC3PSC_MASK (3 << GTIM_CCMR2_IC3PSC_SHIFT) - /* (See common CCMR Input Capture Prescaler definitions below) */ -#define GTIM_CCMR2_IC3F_SHIFT (4) /* Bits 7-4: Input Capture 3 Filter */ -#define GTIM_CCMR2_IC3F_MASK (0x0f << GTIM_CCMR2_IC3F_SHIFT) - /* (See common CCMR Input Capture Filter definitions below) */ - /* Bits 9-8: (Same as Output Compare Mode) */ -#define GTIM_CCMR2_IC4PSC_SHIFT (10) /* Bits 11-10: Input Capture 4 Prescaler */ -#define GTIM_CCMR2_IC4PSC_MASK (3 << GTIM_CCMR2_IC4PSC_SHIFT) - /* (See common CCMR Input Capture Prescaler definitions below) */ -#define GTIM_CCMR2_IC4F_SHIFT (12) /* Bits 15-12: Input Capture 4 Filter */ -#define GTIM_CCMR2_IC4F_MASK (0x0f << GTIM_CCMR2_IC4F_SHIFT) - /* (See common CCMR Input Capture Filter definitions below) */ - -/* Capture/compare enable register (TIM1 and TIM8, TIM2-5 and TIM9-14) */ - -#define GTIM_CCER_CC1E (1 << 0) /* Bit 0: Capture/Compare 1 output enable */ -#define GTIM_CCER_CC1P (1 << 1) /* Bit 1: Capture/Compare 1 output polarity */ -#define GTIM_CCER_CC1NE (1 << 2) /* Bit 2: Capture/Compare 1 complementary output enable (TIM1 and TIM8 only) */ -#define GTIM_CCER_CC1NP (1 << 3) /* Bit 3: Capture/Compare 1 output Polarity (F2,F3,F4 and TIM15-17) */ -#define GTIM_CCER_CC2E (1 << 4) /* Bit 4: Capture/Compare 2 output enable (TIM2-5,9&12 only) */ -#define GTIM_CCER_CC2P (1 << 5) /* Bit 5: Capture/Compare 2 output polarity (TIM2-5,9&12 only) */ -#define GTIM_CCER_CC2NE (1 << 6) /* Bit 6: Capture/Compare 2 complementary output enable (TIM1 and TIM8 only) */ -#define GTIM_CCER_CC2NP (1 << 7) /* Bit 7: Capture/Compare 2 output Polarity (F2,F3,F4 and TIM2-5,9,12&15 only) */ -#define GTIM_CCER_CC3E (1 << 8) /* Bit 8: Capture/Compare 3 output enable (TIM2-5 only) */ -#define GTIM_CCER_CC3P (1 << 9) /* Bit 9: Capture/Compare 3 output Polarity (TIM2-5 only) */ -#define GTIM_CCER_CC3NE (1 << 10) /* Bit 10: Capture/Compare 3 complementary output enable (TIM1 and TIM8 only) */ -#define GTIM_CCER_CC3NP (1 << 11) /* Bit 11: Capture/Compare 3 output Polarity (F2,F4 and TIM2-5 only) */ -#define GTIM_CCER_CC4E (1 << 12) /* Bit 12: Capture/Compare 4 output enable (TIM2-5 only) */ -#define GTIM_CCER_CC4P (1 << 13) /* Bit 13: Capture/Compare 4 output Polarity (TIM2-5 only) */ -#define GTIM_CCER_CC4NP (1 << 15) /* Bit 15: Capture/Compare 4 output Polarity */ - -/* 16-bit counter register */ - -#define GTIM_CNT_SHIFT (0) /* Bits 0-15: Timer counter value */ -#define GTIM_CNT_MASK (0xffff << ATIM_CNT_SHIFT) - -/* Repitition counter (TIM15-17 only) */ - -#define GTIM_RCR_REP_SHIFT (0) /* Bits 0-7: Repetition Counter Value */ -#define GTIM_RCR_REP_MASK (0xff << GTIM_RCR_REP_SHIFT) - -#define GTIM_RCR_REP_MAX 128 - -/* Break and dead-time register (TIM15-17 only */ - -#define GTIM_BDTR_DTG_SHIFT (0) /* Bits 7:0 [7:0]: Dead-Time Generator set-up */ -#define GTIM_BDTR_DTG_MASK (0xff << GTIM_BDTR_DTG_SHIFT) -#define GTIM_BDTR_LOCK_SHIFT (8) /* Bits 9:8 [1:0]: Lock Configuration */ -#define GTIM_BDTR_LOCK_MASK (3 << GTIM_BDTR_LOCK_SHIFT) -# define GTIM_BDTR_LOCKOFF (0 << GTIM_BDTR_LOCK_SHIFT) /* 00: LOCK OFF - No bit is write protected */ -# define GTIM_BDTR_LOCK1 (1 << GTIM_BDTR_LOCK_SHIFT) /* 01: LOCK Level 1 protection */ -# define GTIM_BDTR_LOCK2 (2 << GTIM_BDTR_LOCK_SHIFT) /* 10: LOCK Level 2 protection */ -# define GTIM_BDTR_LOCK3 (3 << GTIM_BDTR_LOCK_SHIFT) /* 11: LOCK Level 3 protection */ */ -#define GTIM_BDTR_OSSI (1 << 10) /* Bit 10: Off-State Selection for Idle mode */ -#define GTIM_BDTR_OSSR (1 << 11) /* Bit 11: Off-State Selection for Run mode */ -#define GTIM_BDTR_BKE (1 << 12) /* Bit 12: Break enable */ -#define GTIM_BDTR_BKP (1 << 13) /* Bit 13: Break Polarity */ -#define GTIM_BDTR_AOE (1 << 14) /* Bit 14: Automatic Output enable */ -#define GTIM_BDTR_MOE (1 << 15) /* Bit 15: Main Output enable */ -#define GTIM_BDTR_BKF_SHIFT (16) /* Bits 16-19: Break filter */ -#define GTIM_BDTR_BKF_MASK (15 << GTIM_BDTR_BKF_SHIFT) -# define GTIM_BDTR_BKF_NOFILT (0 << GTIM_BDTR_BKF_SHIFT) /* 0000: No filter, BRK acts asynchronously */ -# define GTIM_BDTR_BKF_FCKINT2 (1 << GTIM_BDTR_BKF_SHIFT) /* 0001: fSAMPLING=fCK_INT, N=2 */ -# define GTIM_BDTR_BKF_FCKINT4 (2 << GTIM_BDTR_BKF_SHIFT) /* 0010: fSAMPLING=fCK_INT, N=4 */ -# define GTIM_BDTR_BKF_FCKINT8 (3 << GTIM_BDTR_BKF_SHIFT) /* 0011: fSAMPLING=fCK_INT, N=8 */ -# define GTIM_BDTR_BKF_FDTSd26 (4 << GTIM_BDTR_BKF_SHIFT) /* 0100: fSAMPLING=fDTS/2, N=6 */ -# define GTIM_BDTR_BKF_FDTSd28 (5 << GTIM_BDTR_BKF_SHIFT) /* 0101: fSAMPLING=fDTS/2, N=8 */ -# define GTIM_BDTR_BKF_FDTSd36 (6 << GTIM_BDTR_BKF_SHIFT) /* 0110: fSAMPLING=fDTS/4, N=6 */ -# define GTIM_BDTR_BKF_FDTSd38 (7 << GTIM_BDTR_BKF_SHIFT) /* 0111: fSAMPLING=fDTS/4, N=8 */ -# define GTIM_BDTR_BKF_FDTSd86 (8 << GTIM_BDTR_BKF_SHIFT) /* 1000: fSAMPLING=fDTS/8, N=6 */ -# define GTIM_BDTR_BKF_FDTSd88 (9 << GTIM_BDTR_BKF_SHIFT) /* 1001: fSAMPLING=fDTS/8, N=8 */ -# define GTIM_BDTR_BKF_FDTSd165 (10 << GTIM_BDTR_BKF_SHIFT) /* 1010: fSAMPLING=fDTS/16, N=5 */ -# define GTIM_BDTR_BKF_FDTSd166 (11 << GTIM_BDTR_BKF_SHIFT) /* 1011: fSAMPLING=fDTS/16, N=6 */ -# define GTIM_BDTR_BKF_FDTSd168 (12 << GTIM_BDTR_BKF_SHIFT) /* 1100: fSAMPLING=fDTS/16, N=8 */ -# define GTIM_BDTR_BKF_FDTSd325 (13 << GTIM_BDTR_BKF_SHIFT) /* 1101: fSAMPLING=fDTS/32, N=5 */ -# define GTIM_BDTR_BKF_FDTSd326 (14 << GTIM_BDTR_BKF_SHIFT) /* 1110: fSAMPLING=fDTS/32, N=6 */ -# define GTIM_BDTR_BKF_FDTSd328 (15 << GTIM_BDTR_BKF_SHIFT) /* 1111: fSAMPLING=fDTS/32, N=8 */ - -/* DMA control register */ - -#define GTIM_DCR_DBA_SHIFT (0) /* Bits 4-0: DMA Base Address */ -#define GTIM_DCR_DBA_MASK (0x1f << GTIM_DCR_DBA_SHIFT) -#define GTIM_DCR_DBL_SHIFT (8) /* Bits 12-8: DMA Burst Length */ -#define GTIM_DCR_DBL_MASK (0x1f << GTIM_DCR_DBL_SHIFT) - -/* Timer 2/5 option register */ - -# define TIM2_OR_ITR1_RMP_SHIFT (10) /* Bits 10-11: Internal trigger 1 remap */ -# define TIM2_OR_ITR1_RMP_MASK (3 << TIM2_OR_ITR1_RMP_SHIFT) -# define TIM2_OR_ITR1_TIM8_TRGOUT (0 << TIM2_OR_ITR1_RMP_SHIFT) /* 00: TIM2_ITR1 input connected to TIM8_TRGOUT */ -# define TIM2_OR_ITR1_PTP (1 << TIM2_OR_ITR1_RMP_SHIFT) /* 01: TIM2_ITR1 input connected to PTP trigger output */ -# define TIM2_OR_ITR1_OTGFSSOF (2 << TIM2_OR_ITR1_RMP_SHIFT) /* 10: TIM2_ITR1 input connected to OTG FS SOF */ -# define TIM2_OR_ITR1_OTGHSSOF (3 << TIM2_OR_ITR1_RMP_SHIFT) /* 11: TIM2_ITR1 input connected to OTG HS SOF */ - -# define TIM5_OR_TI4_RMP_SHIFT (6) /* Bits 6-7: Internal trigger 4 remap */ -# define TIM5_OR_TI4_RMP_MASK (3 << TIM5_OR_TI4_RMP_SHIFT) -# define TIM5_OR_TI4_GPIO (0 << TIM5_OR_TI4_RMP_SHIFT) /* 00: TIM5_CH4 input connected to GPIO */ -# define TIM5_OR_TI4_LSI (1 << TIM5_OR_TI4_RMP_SHIFT) /* 01: TIM5_CH4 input connected to LSI internal clock */ -# define TIM5_OR_TI4_LSE (2 << TIM5_OR_TI4_RMP_SHIFT) /* 10: TIM5_CH4 input connected to LSE internal clock */ -# define TIM5_OR_TI4_RTC (3 << TIM5_OR_TI4_RMP_SHIFT) /* 11: TIM5_CH4 input connected to RTC output event */ - -# define TIM11_OR_TI1_RMP_SHIFT (6) /* Bits 6-7: Internal trigger 4 remap */ -# define TIM11_OR_TI1_RMP_MASK (3 << TIM11_OR_TI1_RMP_SHIFT) -# define TIM11_OR_TI1_GPIO (0 << TIM11_OR_TI1_RMP_SHIFT) /* 00-11: TIM11_CH1 input connected to GPIO */ -# define TIM11_OR_TI1_HSERTC (3 << TIM11_OR_TI1_RMP_SHIFT) /* 11: TIM11_CH1 input connected to HSE_RTC clock */ - - -/* Control register 1 */ - -#define BTIM_CR1_CEN (1 << 0) /* Bit 0: Counter enable */ -#define BTIM_CR1_UDIS (1 << 1) /* Bit 1: Update Disable */ -#define BTIM_CR1_URS (1 << 2) /* Bit 2: Update Request Source */ -#define BTIM_CR1_OPM (1 << 3) /* Bit 3: One Pulse Mode */ -#define BTIM_CR1_ARPE (1 << 7) /* Bit 7: Auto-Reload Preload enable */ - -/* Control register 2 */ - -#define BTIM_CR2_MMS_SHIFT (4) /* Bits 6-4: Master Mode Selection */ -#define BTIM_CR2_MMS_MASK (7 << BTIM_CR2_MMS_SHIFT) -# define BTIM_CR2_RESET (0 << BTIM_CR2_MMS_SHIFT) /* 000: Reset */ -# define BTIM_CR2_ENAB (1 << BTIM_CR2_MMS_SHIFT) /* 001: Enable */ -# define BTIM_CR2_UPDT (2 << BTIM_CR2_MMS_SHIFT) /* 010: Update */ - -/* DMA/Interrupt enable register */ - -#define BTIM_DIER_UIE (1 << 0) /* Bit 0: Update interrupt enable */ -#define BTIM_DIER_UDE (1 << 8) /* Bit 8: Update DMA request enable */ - -/* Status register */ - -#define BTIM_SR_UIF (1 << 0) /* Bit 0: Update interrupt flag */ - -/* Event generation register */ - -#define BTIM_EGR_UG (1 << 0) /* Bit 0: Update generation */ - #endif /* __ARCH_ARM_SRC_STM32F7_CHIP_STM32_TIM_H */ diff --git a/arch/arm/src/stm32f7/chip/stm32f74xx75xx_tim.h b/arch/arm/src/stm32f7/chip/stm32f74xx75xx_tim.h new file mode 100644 index 0000000000..eca76e95aa --- /dev/null +++ b/arch/arm/src/stm32f7/chip/stm32f74xx75xx_tim.h @@ -0,0 +1,1129 @@ +/**************************************************************************************************** + * arch/arm/src/stm32f7/chip/stm32f74xx75xx_tim.h + * + * Copyright (C) 2016 Gregory Nutt. All rights reserved. + * Authors: Gregory Nutt + * David Sidrane + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************************************/ + +#ifndef __ARCH_ARM_SRC_STM32F7_CHIP_STM32F74XX75XX_TIM_H +#define __ARCH_ARM_SRC_STM32F7_CHIP_STM32F74XX75XX_TIM_H + +/**************************************************************************************************** + * Pre-processor Definitions + ****************************************************************************************************/ + +/* Register Offsets *********************************************************************************/ + +/* Basic Timers - TIM6 and TIM7 */ + +#define STM32_BTIM_CR1_OFFSET 0x0000 /* Control register 1 (16-bit) */ +#define STM32_BTIM_CR2_OFFSET 0x0004 /* Control register 2 (16-bit) */ +#define STM32_BTIM_DIER_OFFSET 0x000c /* DMA/Interrupt enable register (16-bit) */ +#define STM32_BTIM_SR_OFFSET 0x0010 /* Status register (16-bit) */ +#define STM32_BTIM_EGR_OFFSET 0x0014 /* Event generation register (16-bit) */ +#define STM32_BTIM_CNT_OFFSET 0x0024 /* Counter (16-bit) */ +#define STM32_BTIM_PSC_OFFSET 0x0028 /* Prescaler (16-bit) */ +#define STM32_BTIM_ARR_OFFSET 0x002c /* Auto-reload register (16-bit) */ + +/* 16-/32-bit General Timers with DMA: TIM2, TM3, TIM4, and TIM5 + * 16-bit General Timers without DMA: TIM9, TIM10, TIM11, TIM12, TIM13, and TIM14 + * timers are 16-bit except for TIM2 and 5 are 32-bit + * timers TIM9 and 12 are different then TIM10, TIM11, TIM13, and TIM14 + */ + +#define STM32_GTIM_CR1_OFFSET 0x0000 /* Control register 1 (16-bit) */ +#define STM32_GTIM_CR2_OFFSET 0x0004 /* Control register 2 (16-bit, TIM2, 5 only) */ +#define STM32_GTIM_SMCR_OFFSET 0x0008 /* Slave mode control register (32-bit, TIM2, 5, 9, 12 only) */ +#define STM32_GTIM_DIER_OFFSET 0x000c /* DMA/Interrupt enable register (16-bit) */ +#define STM32_GTIM_SR_OFFSET 0x0010 /* Status register (16-bit) */ +#define STM32_GTIM_EGR_OFFSET 0x0014 /* Event generation register (16-bit) */ +#define STM32_GTIM_CCMR1_OFFSET 0x0018 /* Capture/compare mode register 1 (32-bit) */ +#define STM32_GTIM_CCMR2_OFFSET 0x001c /* Capture/compare mode register 2 (32-bit on TIM2,5 only) */ +#define STM32_GTIM_CCER_OFFSET 0x0020 /* Capture/compare enable register (16-bit) */ +#define STM32_GTIM_CNT_OFFSET 0x0024 /* Counter (16 bit and 32-bit on TIM2, 5 only) */ +#define STM32_GTIM_PSC_OFFSET 0x0028 /* Prescaler (16-bit) */ +#define STM32_GTIM_ARR_OFFSET 0x002c /* Auto-reload register (16 bit and 32-bit on TIM2, 5 only) */ +#define STM32_GTIM_CCR1_OFFSET 0x0034 /* Capture/compare register 1 (16-bit on all TIMx and 32-bit on TIM2,5 only) */ +#define STM32_GTIM_CCR2_OFFSET 0x0038 /* Capture/compare register 2 (16-bit TIM 3-4, 9, 12 and 32-bit on TIM2,5 only) */ +#define STM32_GTIM_CCR3_OFFSET 0x003c /* Capture/compare register 3 (16-bit TIM 3-4 and 32-bit on TIM2,5 only) */ +#define STM32_GTIM_CCR4_OFFSET 0x0040 /* Capture/compare register 4 (16-bit TIM 3-4 and 32-bit on TIM2,5 only) */ +#define STM32_GTIM_DCR_OFFSET 0x0048 /* DMA control register (16-bit, TIM2-5 only) */ +#define STM32_GTIM_DMAR_OFFSET 0x004c /* DMA address for burst mode (16-bit, TIM2-5 only) */ +#define STM32_GTIM_OR_OFFSET 0x0050 /* Timer 2/5/11 option register */ + +/* Advanced Timers - TIM1 and TIM8 */ + +#define STM32_ATIM_CR1_OFFSET 0x0000 /* Control register 1 (16-bit) */ +#define STM32_ATIM_CR2_OFFSET 0x0004 /* Control register 2 (32-bit*) */ +#define STM32_ATIM_SMCR_OFFSET 0x0008 /* Slave mode control register (32 -bit) */ +#define STM32_ATIM_DIER_OFFSET 0x000c /* DMA/Interrupt enable register (16-bit) */ +#define STM32_ATIM_SR_OFFSET 0x0010 /* Status register (32-bit*) */ +#define STM32_ATIM_EGR_OFFSET 0x0014 /* Event generation register (16-bit) */ +#define STM32_ATIM_CCMR1_OFFSET 0x0018 /* Capture/compare mode register 1 (32-bit*) */ +#define STM32_ATIM_CCMR2_OFFSET 0x001c /* Capture/compare mode register 2 (32-bit*) */ +#define STM32_ATIM_CCER_OFFSET 0x0020 /* Capture/compare enable register (32-bit*) */ +#define STM32_ATIM_CNT_OFFSET 0x0024 /* Counter (32-bit cnt in lower 16 bit ) */ +#define STM32_ATIM_PSC_OFFSET 0x0028 /* Prescaler (16-bit) */ +#define STM32_ATIM_ARR_OFFSET 0x002c /* Auto-reload register (16-bit) */ +#define STM32_ATIM_RCR_OFFSET 0x0030 /* Repetition counter register (16-bit) */ +#define STM32_ATIM_CCR1_OFFSET 0x0034 /* Capture/compare register 1 (16-bit) */ +#define STM32_ATIM_CCR2_OFFSET 0x0038 /* Capture/compare register 2 (16-bit) */ +#define STM32_ATIM_CCR3_OFFSET 0x003c /* Capture/compare register 3 (16-bit) */ +#define STM32_ATIM_CCR4_OFFSET 0x0040 /* Capture/compare register 4 (16-bit) */ +#define STM32_ATIM_BDTR_OFFSET 0x0044 /* Break and dead-time register (32-bit*) */ +#define STM32_ATIM_DCR_OFFSET 0x0048 /* DMA control register (16-bit) */ +#define STM32_ATIM_DMAR_OFFSET 0x004c /* DMA address for burst mode (16-bit) */ +#define STM32_ATIM_CCMR3_OFFSET 0x0054 /* Capture/compare mode register 3 (32-bit) */ +#define STM32_ATIM_CCR5_OFFSET 0x0058 /* Capture/compare register 5 (32-bit) */ +#define STM32_ATIM_CCR6_OFFSET 0x005c /* Capture/compare register 6 (16-bit) */ + +/* Register Addresses *******************************************************************************/ + +/* Advanced Timers - TIM1 and TIM8 */ + +#if STM32F7_NATIM > 0 +# define STM32_TIM1_CR1 (STM32_TIM1_BASE+STM32_ATIM_CR1_OFFSET) +# define STM32_TIM1_CR2 (STM32_TIM1_BASE+STM32_ATIM_CR2_OFFSET) +# define STM32_TIM1_SMCR (STM32_TIM1_BASE+STM32_ATIM_SMCR_OFFSET) +# define STM32_TIM1_DIER (STM32_TIM1_BASE+STM32_ATIM_DIER_OFFSET) +# define STM32_TIM1_SR (STM32_TIM1_BASE+STM32_ATIM_SR_OFFSET) +# define STM32_TIM1_EGR (STM32_TIM1_BASE+STM32_ATIM_EGR_OFFSET) +# define STM32_TIM1_CCMR1 (STM32_TIM1_BASE+STM32_ATIM_CCMR1_OFFSET) +# define STM32_TIM1_CCMR2 (STM32_TIM1_BASE+STM32_ATIM_CCMR2_OFFSET) +# define STM32_TIM1_CCER (STM32_TIM1_BASE+STM32_ATIM_CCER_OFFSET) +# define STM32_TIM1_CNT (STM32_TIM1_BASE+STM32_ATIM_CNT_OFFSET) +# define STM32_TIM1_PSC (STM32_TIM1_BASE+STM32_ATIM_PSC_OFFSET) +# define STM32_TIM1_ARR (STM32_TIM1_BASE+STM32_ATIM_ARR_OFFSET) +# define STM32_TIM1_RCR (STM32_TIM1_BASE+STM32_ATIM_RCR_OFFSET) +# define STM32_TIM1_CCR1 (STM32_TIM1_BASE+STM32_ATIM_CCR1_OFFSET) +# define STM32_TIM1_CCR2 (STM32_TIM1_BASE+STM32_ATIM_CCR2_OFFSET) +# define STM32_TIM1_CCR3 (STM32_TIM1_BASE+STM32_ATIM_CCR3_OFFSET) +# define STM32_TIM1_CCR4 (STM32_TIM1_BASE+STM32_ATIM_CCR4_OFFSET) +# define STM32_TIM1_BDTR (STM32_TIM1_BASE+STM32_ATIM_BDTR_OFFSET) +# define STM32_TIM1_DCR (STM32_TIM1_BASE+STM32_ATIM_DCR_OFFSET) +# define STM32_TIM1_DMAR (STM32_TIM1_BASE+STM32_ATIM_DMAR_OFFSET) +# define STM32_TIM1_CCMR3 (STM32_TIM1_BASE+STM32_ATIM_CCMR3_OFFSET) +# define STM32_TIM1_CCR5 (STM32_TIM1_BASE+STM32_ATIM_CCR5_OFFSET) +# define STM32_TIM1_CCR6 (STM32_TIM1_BASE+STM32_ATIM_CCR6_OFFSET) +#endif + +#if STM32F7_NATIM > 1 +# define STM32_TIM8_CR1 (STM32_TIM8_BASE+STM32_ATIM_CR1_OFFSET) +# define STM32_TIM8_CR2 (STM32_TIM8_BASE+STM32_ATIM_CR2_OFFSET) +# define STM32_TIM8_SMCR (STM32_TIM8_BASE+STM32_ATIM_SMCR_OFFSET) +# define STM32_TIM8_DIER (STM32_TIM8_BASE+STM32_ATIM_DIER_OFFSET) +# define STM32_TIM8_SR (STM32_TIM8_BASE+STM32_ATIM_SR_OFFSET) +# define STM32_TIM8_EGR (STM32_TIM8_BASE+STM32_ATIM_EGR_OFFSET) +# define STM32_TIM8_CCMR1 (STM32_TIM8_BASE+STM32_ATIM_CCMR1_OFFSET) +# define STM32_TIM8_CCMR2 (STM32_TIM8_BASE+STM32_ATIM_CCMR2_OFFSET) +# define STM32_TIM8_CCER (STM32_TIM8_BASE+STM32_ATIM_CCER_OFFSET) +# define STM32_TIM8_CNT (STM32_TIM8_BASE+STM32_ATIM_CNT_OFFSET) +# define STM32_TIM8_PSC (STM32_TIM8_BASE+STM32_ATIM_PSC_OFFSET) +# define STM32_TIM8_ARR (STM32_TIM8_BASE+STM32_ATIM_ARR_OFFSET) +# define STM32_TIM8_RCR (STM32_TIM8_BASE+STM32_ATIM_RCR_OFFSET) +# define STM32_TIM8_CCR1 (STM32_TIM8_BASE+STM32_ATIM_CCR1_OFFSET) +# define STM32_TIM8_CCR2 (STM32_TIM8_BASE+STM32_ATIM_CCR2_OFFSET) +# define STM32_TIM8_CCR3 (STM32_TIM8_BASE+STM32_ATIM_CCR3_OFFSET) +# define STM32_TIM8_CCR4 (STM32_TIM8_BASE+STM32_ATIM_CCR4_OFFSET) +# define STM32_TIM8_BDTR (STM32_TIM8_BASE+STM32_ATIM_BDTR_OFFSET) +# define STM32_TIM8_DCR (STM32_TIM8_BASE+STM32_ATIM_DCR_OFFSET) +# define STM32_TIM8_DMAR (STM32_TIM8_BASE+STM32_ATIM_DMAR_OFFSET) +# define STM32_TIM8_CCMR3 (STM32_TIM8_BASE+STM32_ATIM_CCMR3_OFFSET) +# define STM32_TIM8_CCR5 (STM32_TIM8_BASE+STM32_ATIM_CCR5_OFFSET) +# define STM32_TIM8_CCR6 (STM32_TIM8_BASE+STM32_ATIM_CCR6_OFFSET) +#endif + +/* 16-/32-bit General Timers - TIM2, TIM3, TIM4, and TIM5 with DMA. + * All timers are 16-bit except for TIM2 and 5 are 32-bit + */ + +#if (STM32F7_NGTIM16+STM32F7_NGTIM32) > 0 +# define STM32_TIM2_CR1 (STM32_TIM2_BASE+STM32_GTIM_CR1_OFFSET) +# define STM32_TIM2_CR2 (STM32_TIM2_BASE+STM32_GTIM_CR2_OFFSET) +# define STM32_TIM2_SMCR (STM32_TIM2_BASE+STM32_GTIM_SMCR_OFFSET) +# define STM32_TIM2_DIER (STM32_TIM2_BASE+STM32_GTIM_DIER_OFFSET) +# define STM32_TIM2_SR (STM32_TIM2_BASE+STM32_GTIM_SR_OFFSET) +# define STM32_TIM2_EGR (STM32_TIM2_BASE+STM32_GTIM_EGR_OFFSET) +# define STM32_TIM2_CCMR1 (STM32_TIM2_BASE+STM32_GTIM_CCMR1_OFFSET) +# define STM32_TIM2_CCMR2 (STM32_TIM2_BASE+STM32_GTIM_CCMR2_OFFSET) +# define STM32_TIM2_CCER (STM32_TIM2_BASE+STM32_GTIM_CCER_OFFSET) +# define STM32_TIM2_CNT (STM32_TIM2_BASE+STM32_GTIM_CNT_OFFSET) +# define STM32_TIM2_PSC (STM32_TIM2_BASE+STM32_GTIM_PSC_OFFSET) +# define STM32_TIM2_ARR (STM32_TIM2_BASE+STM32_GTIM_ARR_OFFSET) +# define STM32_TIM2_CCR1 (STM32_TIM2_BASE+STM32_GTIM_CCR1_OFFSET) +# define STM32_TIM2_CCR2 (STM32_TIM2_BASE+STM32_GTIM_CCR2_OFFSET) +# define STM32_TIM2_CCR3 (STM32_TIM2_BASE+STM32_GTIM_CCR3_OFFSET) +# define STM32_TIM2_CCR4 (STM32_TIM2_BASE+STM32_GTIM_CCR4_OFFSET) +# define STM32_TIM2_DCR (STM32_TIM2_BASE+STM32_GTIM_DCR_OFFSET) +# define STM32_TIM2_DMAR (STM32_TIM2_BASE+STM32_GTIM_DMAR_OFFSET) +# define STM32_TIM2_OR (STM32_TIM2_BASE+STM32_GTIM_OR_OFFSET) +#endif + +#if (STM32F7_NGTIM16+STM32F7_NGTIM32) > 1 +# define STM32_TIM3_CR1 (STM32_TIM3_BASE+STM32_GTIM_CR1_OFFSET) +# define STM32_TIM3_CR2 (STM32_TIM3_BASE+STM32_GTIM_CR2_OFFSET) +# define STM32_TIM3_SMCR (STM32_TIM3_BASE+STM32_GTIM_SMCR_OFFSET) +# define STM32_TIM3_DIER (STM32_TIM3_BASE+STM32_GTIM_DIER_OFFSET) +# define STM32_TIM3_SR (STM32_TIM3_BASE+STM32_GTIM_SR_OFFSET) +# define STM32_TIM3_EGR (STM32_TIM3_BASE+STM32_GTIM_EGR_OFFSET) +# define STM32_TIM3_CCMR1 (STM32_TIM3_BASE+STM32_GTIM_CCMR1_OFFSET) +# define STM32_TIM3_CCMR2 (STM32_TIM3_BASE+STM32_GTIM_CCMR2_OFFSET) +# define STM32_TIM3_CCER (STM32_TIM3_BASE+STM32_GTIM_CCER_OFFSET) +# define STM32_TIM3_CNT (STM32_TIM3_BASE+STM32_GTIM_CNT_OFFSET) +# define STM32_TIM3_PSC (STM32_TIM3_BASE+STM32_GTIM_PSC_OFFSET) +# define STM32_TIM3_ARR (STM32_TIM3_BASE+STM32_GTIM_ARR_OFFSET) +# define STM32_TIM3_CCR1 (STM32_TIM3_BASE+STM32_GTIM_CCR1_OFFSET) +# define STM32_TIM3_CCR2 (STM32_TIM3_BASE+STM32_GTIM_CCR2_OFFSET) +# define STM32_TIM3_CCR3 (STM32_TIM3_BASE+STM32_GTIM_CCR3_OFFSET) +# define STM32_TIM3_CCR4 (STM32_TIM3_BASE+STM32_GTIM_CCR4_OFFSET) +# define STM32_TIM3_DCR (STM32_TIM3_BASE+STM32_GTIM_DCR_OFFSET) +# define STM32_TIM3_DMAR (STM32_TIM3_BASE+STM32_GTIM_DMAR_OFFSET) +#endif + +#if (STM32F7_NGTIM16+STM32F7_NGTIM32) > 2 +# define STM32_TIM4_CR1 (STM32_TIM4_BASE+STM32_GTIM_CR1_OFFSET) +# define STM32_TIM4_CR2 (STM32_TIM4_BASE+STM32_GTIM_CR2_OFFSET) +# define STM32_TIM4_SMCR (STM32_TIM4_BASE+STM32_GTIM_SMCR_OFFSET) +# define STM32_TIM4_DIER (STM32_TIM4_BASE+STM32_GTIM_DIER_OFFSET) +# define STM32_TIM4_SR (STM32_TIM4_BASE+STM32_GTIM_SR_OFFSET) +# define STM32_TIM4_EGR (STM32_TIM4_BASE+STM32_GTIM_EGR_OFFSET) +# define STM32_TIM4_CCMR1 (STM32_TIM4_BASE+STM32_GTIM_CCMR1_OFFSET) +# define STM32_TIM4_CCMR2 (STM32_TIM4_BASE+STM32_GTIM_CCMR2_OFFSET) +# define STM32_TIM4_CCER (STM32_TIM4_BASE+STM32_GTIM_CCER_OFFSET) +# define STM32_TIM4_CNT (STM32_TIM4_BASE+STM32_GTIM_CNT_OFFSET) +# define STM32_TIM4_PSC (STM32_TIM4_BASE+STM32_GTIM_PSC_OFFSET) +# define STM32_TIM4_ARR (STM32_TIM4_BASE+STM32_GTIM_ARR_OFFSET) +# define STM32_TIM4_CCR1 (STM32_TIM4_BASE+STM32_GTIM_CCR1_OFFSET) +# define STM32_TIM4_CCR2 (STM32_TIM4_BASE+STM32_GTIM_CCR2_OFFSET) +# define STM32_TIM4_CCR3 (STM32_TIM4_BASE+STM32_GTIM_CCR3_OFFSET) +# define STM32_TIM4_CCR4 (STM32_TIM4_BASE+STM32_GTIM_CCR4_OFFSET) +# define STM32_TIM4_DCR (STM32_TIM4_BASE+STM32_GTIM_DCR_OFFSET) +# define STM32_TIM4_DMAR (STM32_TIM4_BASE+STM32_GTIM_DMAR_OFFSET) +#endif + +#if (STM32F7_NGTIM16+STM32F7_NGTIM32) > 3 +# define STM32_TIM5_CR1 (STM32_TIM5_BASE+STM32_GTIM_CR1_OFFSET) +# define STM32_TIM5_CR2 (STM32_TIM5_BASE+STM32_GTIM_CR2_OFFSET) +# define STM32_TIM5_SMCR (STM32_TIM5_BASE+STM32_GTIM_SMCR_OFFSET) +# define STM32_TIM5_DIER (STM32_TIM5_BASE+STM32_GTIM_DIER_OFFSET) +# define STM32_TIM5_SR (STM32_TIM5_BASE+STM32_GTIM_SR_OFFSET) +# define STM32_TIM5_EGR (STM32_TIM5_BASE+STM32_GTIM_EGR_OFFSET) +# define STM32_TIM5_CCMR1 (STM32_TIM5_BASE+STM32_GTIM_CCMR1_OFFSET) +# define STM32_TIM5_CCMR2 (STM32_TIM5_BASE+STM32_GTIM_CCMR2_OFFSET) +# define STM32_TIM5_CCER (STM32_TIM5_BASE+STM32_GTIM_CCER_OFFSET) +# define STM32_TIM5_CNT (STM32_TIM5_BASE+STM32_GTIM_CNT_OFFSET) +# define STM32_TIM5_PSC (STM32_TIM5_BASE+STM32_GTIM_PSC_OFFSET) +# define STM32_TIM5_ARR (STM32_TIM5_BASE+STM32_GTIM_ARR_OFFSET) +# define STM32_TIM5_CCR1 (STM32_TIM5_BASE+STM32_GTIM_CCR1_OFFSET) +# define STM32_TIM5_CCR2 (STM32_TIM5_BASE+STM32_GTIM_CCR2_OFFSET) +# define STM32_TIM5_CCR3 (STM32_TIM5_BASE+STM32_GTIM_CCR3_OFFSET) +# define STM32_TIM5_CCR4 (STM32_TIM5_BASE+STM32_GTIM_CCR4_OFFSET) +# define STM32_TIM5_DCR (STM32_TIM5_BASE+STM32_GTIM_DCR_OFFSET) +# define STM32_TIM5_DMAR (STM32_TIM5_BASE+STM32_GTIM_DMAR_OFFSET) +# define STM32_TIM5_OR (STM32_TIM5_BASE+STM32_GTIM_OR_OFFSET) +#endif + + +/* 16-bit General Timers - TIM9-14 without DMA. Note that (1) these timers + * support only a subset of the general timer registers are supported, and + * (2) TIM9 and TIM12 differ from the others. + */ + +#if STM32F7_NGTIMNDMA > 0 +# define STM32_TIM9_CR1 (STM32_TIM9_BASE+STM32_GTIM_CR1_OFFSET) +# define STM32_TIM9_CR2 (STM32_TIM9_BASE+STM32_GTIM_CR2_OFFSET) +# define STM32_TIM9_DIER (STM32_TIM9_BASE+STM32_GTIM_DIER_OFFSET) +# define STM32_TIM9_SR (STM32_TIM9_BASE+STM32_GTIM_SR_OFFSET) +# define STM32_TIM9_EGR (STM32_TIM9_BASE+STM32_GTIM_EGR_OFFSET) +# define STM32_TIM9_CCMR1 (STM32_TIM9_BASE+STM32_GTIM_CCMR1_OFFSET) +# define STM32_TIM9_CCER (STM32_TIM9_BASE+STM32_GTIM_CCER_OFFSET) +# define STM32_TIM9_CNT (STM32_TIM9_BASE+STM32_GTIM_CNT_OFFSET) +# define STM32_TIM9_PSC (STM32_TIM9_BASE+STM32_GTIM_PSC_OFFSET) +# define STM32_TIM9_ARR (STM32_TIM9_BASE+STM32_GTIM_ARR_OFFSET) +# define STM32_TIM9_CCR1 (STM32_TIM9_BASE+STM32_GTIM_CCR1_OFFSET) +# define STM32_TIM9_CCR2 (STM32_TIM9_BASE+STM32_GTIM_CCR2_OFFSET) +#endif + +#if STM32F7_NGTIMNDMA > 1 +# define STM32_TIM10_CR1 (STM32_TIM10_BASE+STM32_GTIM_CR1_OFFSET) +# define STM32_TIM10_DIER (STM32_TIM10_BASE+STM32_GTIM_DIER_OFFSET) +# define STM32_TIM10_SR (STM32_TIM10_BASE+STM32_GTIM_SR_OFFSET) +# define STM32_TIM10_EGR (STM32_TIM10_BASE+STM32_GTIM_EGR_OFFSET) +# define STM32_TIM10_CCMR1 (STM32_TIM10_BASE+STM32_GTIM_CCMR1_OFFSET) +# define STM32_TIM10_CCER (STM32_TIM10_BASE+STM32_GTIM_CCER_OFFSET) +# define STM32_TIM10_CNT (STM32_TIM10_BASE+STM32_GTIM_CNT_OFFSET) +# define STM32_TIM10_PSC (STM32_TIM10_BASE+STM32_GTIM_PSC_OFFSET) +# define STM32_TIM10_ARR (STM32_TIM10_BASE+STM32_GTIM_ARR_OFFSET) +# define STM32_TIM10_CCR1 (STM32_TIM10_BASE+STM32_GTIM_CCR1_OFFSET) +#endif + +#if STM32F7_NGTIMNDMA > 2 +# define STM32_TIM11_CR1 (STM32_TIM11_BASE+STM32_GTIM_CR1_OFFSET) +# define STM32_TIM11_DIER (STM32_TIM11_BASE+STM32_GTIM_DIER_OFFSET) +# define STM32_TIM11_SR (STM32_TIM11_BASE+STM32_GTIM_SR_OFFSET) +# define STM32_TIM11_EGR (STM32_TIM11_BASE+STM32_GTIM_EGR_OFFSET) +# define STM32_TIM11_CCMR1 (STM32_TIM11_BASE+STM32_GTIM_CCMR1_OFFSET) +# define STM32_TIM11_CCER (STM32_TIM11_BASE+STM32_GTIM_CCER_OFFSET) +# define STM32_TIM11_CNT (STM32_TIM11_BASE+STM32_GTIM_CNT_OFFSET) +# define STM32_TIM11_PSC (STM32_TIM11_BASE+STM32_GTIM_PSC_OFFSET) +# define STM32_TIM11_ARR (STM32_TIM11_BASE+STM32_GTIM_ARR_OFFSET) +# define STM32_TIM11_CCR1 (STM32_TIM11_BASE+STM32_GTIM_CCR1_OFFSET) +# define STM32_TIM11_OR (STM32_TIM11_BASE+STM32_GTIM_OR_OFFSET) +#endif + +#if STM32F7_NGTIMNDMA > 3 +# define STM32_TIM12_CR1 (STM32_TIM12_BASE+STM32_GTIM_CR1_OFFSET) +# define STM32_TIM12_CR2 (STM32_TIM9_BASE+STM32_GTIM_CR2_OFFSET) +# define STM32_TIM12_DIER (STM32_TIM12_BASE+STM32_GTIM_DIER_OFFSET) +# define STM32_TIM12_SR (STM32_TIM12_BASE+STM32_GTIM_SR_OFFSET) +# define STM32_TIM12_EGR (STM32_TIM12_BASE+STM32_GTIM_EGR_OFFSET) +# define STM32_TIM12_CCMR1 (STM32_TIM12_BASE+STM32_GTIM_CCMR1_OFFSET) +# define STM32_TIM12_CCER (STM32_TIM12_BASE+STM32_GTIM_CCER_OFFSET) +# define STM32_TIM12_CNT (STM32_TIM12_BASE+STM32_GTIM_CNT_OFFSET) +# define STM32_TIM12_PSC (STM32_TIM12_BASE+STM32_GTIM_PSC_OFFSET) +# define STM32_TIM12_ARR (STM32_TIM12_BASE+STM32_GTIM_ARR_OFFSET) +# define STM32_TIM12_CCR1 (STM32_TIM12_BASE+STM32_GTIM_CCR1_OFFSET) +# define STM32_TIM12_CCR2 (STM32_TIM12_BASE+STM32_GTIM_CCR2_OFFSET) +#endif + +#if STM32F7_NGTIMNDMA > 4 +# define STM32_TIM13_CR1 (STM32_TIM13_BASE+STM32_GTIM_CR1_OFFSET) +# define STM32_TIM13_DIER (STM32_TIM13_BASE+STM32_GTIM_DIER_OFFSET) +# define STM32_TIM13_SR (STM32_TIM13_BASE+STM32_GTIM_SR_OFFSET) +# define STM32_TIM13_EGR (STM32_TIM13_BASE+STM32_GTIM_EGR_OFFSET) +# define STM32_TIM13_CCMR1 (STM32_TIM13_BASE+STM32_GTIM_CCMR1_OFFSET) +# define STM32_TIM13_CCER (STM32_TIM13_BASE+STM32_GTIM_CCER_OFFSET) +# define STM32_TIM13_CNT (STM32_TIM13_BASE+STM32_GTIM_CNT_OFFSET) +# define STM32_TIM13_PSC (STM32_TIM13_BASE+STM32_GTIM_PSC_OFFSET) +# define STM32_TIM13_ARR (STM32_TIM13_BASE+STM32_GTIM_ARR_OFFSET) +# define STM32_TIM13_CCR1 (STM32_TIM13_BASE+STM32_GTIM_CCR1_OFFSET) +#endif + +#if STM32F7_NGTIMNDMA > 5 +# define STM32_TIM14_CR1 (STM32_TIM14_BASE+STM32_GTIM_CR1_OFFSET) +# define STM32_TIM14_DIER (STM32_TIM14_BASE+STM32_GTIM_DIER_OFFSET) +# define STM32_TIM14_SR (STM32_TIM14_BASE+STM32_GTIM_SR_OFFSET) +# define STM32_TIM14_EGR (STM32_TIM14_BASE+STM32_GTIM_EGR_OFFSET) +# define STM32_TIM14_CCMR1 (STM32_TIM14_BASE+STM32_GTIM_CCMR1_OFFSET) +# define STM32_TIM14_CCER (STM32_TIM14_BASE+STM32_GTIM_CCER_OFFSET) +# define STM32_TIM14_CNT (STM32_TIM14_BASE+STM32_GTIM_CNT_OFFSET) +# define STM32_TIM14_PSC (STM32_TIM14_BASE+STM32_GTIM_PSC_OFFSET) +# define STM32_TIM14_ARR (STM32_TIM14_BASE+STM32_GTIM_ARR_OFFSET) +# define STM32_TIM14_CCR1 (STM32_TIM14_BASE+STM32_GTIM_CCR1_OFFSET) +#endif + +/* Basic Timers - TIM6 and TIM7 */ + +#if STM32F7_NBTIM > 0 +# define STM32_TIM6_CR1 (STM32_TIM6_BASE+STM32_BTIM_CR1_OFFSET) +# define STM32_TIM6_CR2 (STM32_TIM6_BASE+STM32_BTIM_CR2_OFFSET) +# define STM32_TIM6_DIER (STM32_TIM6_BASE+STM32_BTIM_DIER_OFFSET) +# define STM32_TIM6_SR (STM32_TIM6_BASE+STM32_BTIM_SR_OFFSET) +# define STM32_TIM6_EGR (STM32_TIM6_BASE+STM32_BTIM_EGR_OFFSET) +# define STM32_TIM6_CNT (STM32_TIM6_BASE+STM32_BTIM_CNT_OFFSET) +# define STM32_TIM6_PSC (STM32_TIM6_BASE+STM32_BTIM_PSC_OFFSET) +# define STM32_TIM6_ARR (STM32_TIM6_BASE+STM32_BTIM_ARR_OFFSET) +#endif + +#if STM32F7_NBTIM > 1 +# define STM32_TIM7_CR1 (STM32_TIM7_BASE+STM32_BTIM_CR1_OFFSET) +# define STM32_TIM7_CR2 (STM32_TIM7_BASE+STM32_BTIM_CR2_OFFSET) +# define STM32_TIM7_DIER (STM32_TIM7_BASE+STM32_BTIM_DIER_OFFSET) +# define STM32_TIM7_SR (STM32_TIM7_BASE+STM32_BTIM_SR_OFFSET) +# define STM32_TIM7_EGR (STM32_TIM7_BASE+STM32_BTIM_EGR_OFFSET) +# define STM32_TIM7_CNT (STM32_TIM7_BASE+STM32_BTIM_CNT_OFFSET) +# define STM32_TIM7_PSC (STM32_TIM7_BASE+STM32_BTIM_PSC_OFFSET) +# define STM32_TIM7_ARR (STM32_TIM7_BASE+STM32_BTIM_ARR_OFFSET) +#endif + +/* Register Bitfield Definitions ********************************************************************/ + +/* Control register 1 */ + +#define ATIM_CR1_CEN (1 << 0) /* Bit 0: Counter enable */ +#define ATIM_CR1_UDIS (1 << 1) /* Bit 1: Update disable */ +#define ATIM_CR1_URS (1 << 2) /* Bit 2: Update request source */ +#define ATIM_CR1_OPM (1 << 3) /* Bit 3: One pulse mode */ +#define ATIM_CR1_DIR (1 << 4) /* Bit 4: Direction */ +#define ATIM_CR1_CMS_SHIFT (5) /* Bits 6-5: Center-aligned mode selection */ +#define ATIM_CR1_CMS_MASK (3 << ATIM_CR1_CMS_SHIFT) +# define ATIM_CR1_EDGE (0 << ATIM_CR1_CMS_SHIFT) /* 00: Edge-aligned mode */ +# define ATIM_CR1_CENTER1 (1 << ATIM_CR1_CMS_SHIFT) /* 01: Center-aligned mode 1 */ +# define ATIM_CR1_CENTER2 (2 << ATIM_CR1_CMS_SHIFT) /* 10: Center-aligned mode 2 */ +# define ATIM_CR1_CENTER3 (3 << ATIM_CR1_CMS_SHIFT) /* 11: Center-aligned mode 3 */ +#define ATIM_CR1_ARPE (1 << 7) /* Bit 7: Auto-reload preload enable */ +#define ATIM_CR1_CKD_SHIFT (8) /* Bits 9-8: Clock division */ +#define ATIM_CR1_CKD_MASK (3 << ATIM_CR1_CKD_SHIFT) +# define ATIM_CR1_TCKINT (0 << ATIM_CR1_CKD_SHIFT) /* 00: tDTS=tCK_INT */ +# define ATIM_CR1_2TCKINT (1 << ATIM_CR1_CKD_SHIFT) /* 01: tDTS=2*tCK_INT */ +# define ATIM_CR1_4TCKINT (2 << ATIM_CR1_CKD_SHIFT) /* 10: tDTS=4*tCK_INT */ +#define ATIM_CR1_UIFREMAP (1 << 11) /* Bit 11: UIF status bit remapping */ + +/* Control register 2 */ + +#define ATIM_CR2_CCPC (1 << 0) /* Bit 0: Capture/Compare Preloaded Control */ +#define ATIM_CR2_CCUS (1 << 2) /* Bit 2: Capture/Compare Control Update Selection */ +#define ATIM_CR2_CCDS (1 << 3) /* Bit 3: Capture/Compare DMA Selection */ +#define ATIM_CR2_MMS_SHIFT (4) /* Bits 6-4: Master Mode Selection */ +#define ATIM_CR2_MMS_MASK (7 << ATIM_CR2_MMS_SHIFT) +# define ATIM_CR2_MMS_RESET (0 << ATIM_CR2_MMS_SHIFT) /* 000: Reset - TIMx_EGR UG bit is TRGO */ +# define ATIM_CR2_MMS_ENABLE (1 << ATIM_CR2_MMS_SHIFT) /* 001: Enable - CNT_EN is TRGO */ +# define ATIM_CR2_MMS_UPDATE (2 << ATIM_CR2_MMS_SHIFT) /* 010: Update event is TRGO */ +# define ATIM_CR2_MMS_COMPP (3 << ATIM_CR2_MMS_SHIFT) /* 010: Compare Pulse - CC1IF flag */ +# define ATIM_CR2_MMS_OC1REF (4 << ATIM_CR2_MMS_SHIFT) /* 100: Compare OC1REF is TRGO */ +# define ATIM_CR2_MMS_OC2REF (5 << ATIM_CR2_MMS_SHIFT) /* 101: Compare OC2REF is TRGO */ +# define ATIM_CR2_MMS_OC3REF (6 << ATIM_CR2_MMS_SHIFT) /* 110: Compare OC3REF is TRGO */ +# define ATIM_CR2_MMS_OC4REF (7 << ATIM_CR2_MMS_SHIFT) /* 111: Compare OC4REF is TRGO */ +#define ATIM_CR2_TI1S (1 << 7) /* Bit 7: TI1 Selection */ +#define ATIM_CR2_OIS1 (1 << 8) /* Bit 8: Output Idle state 1 (OC1 output) */ +#define ATIM_CR2_OIS1N (1 << 9) /* Bit 9: Output Idle state 1 (OC1N output) */ +#define ATIM_CR2_OIS2 (1 << 10) /* Bit 10: Output Idle state 2 (OC2 output) */ +#define ATIM_CR2_OIS2N (1 << 11) /* Bit 11: Output Idle state 2 (OC2N output) */ +#define ATIM_CR2_OIS3 (1 << 12) /* Bit 12: Output Idle state 3 (OC3 output) */ +#define ATIM_CR2_OIS3N (1 << 13) /* Bit 13: Output Idle state 3 (OC3N output) */ +#define ATIM_CR2_OIS4 (1 << 14) /* Bit 14: Output Idle state 4 (OC4 output) */ +#define ATIM_CR2_OIS5 (1 << 16) /* Bit 16: OOutput Idle state 5 (OC5 output) */ +#define ATIM_CR2_OIS6 (1 << 18) /* Bit 18: Output Idle state 6 (OC6 output) */ +#define ATIM_CR2_MMS2_SHIFT (20) /* Bits 20-23: Master Mode Selection 2 */ +#define ATIM_CR2_MMS2_MASK (15 << ATIM_CR2_MMS2_SHIFT) +# define ATIM_CR2_MMS2_RESET (0 << ATIM_CR2_MMS2_SHIFT) /* 0000: Reset - TIMx_EGR UG bit is TRG9 */ +# define ATIM_CR2_MMS2_ENABLE (1 << ATIM_CR2_MMS2_SHIFT) /* 0001: Enable - CNT_EN is TRGO2 */ +# define ATIM_CR2_MMS2_UPDATE (2 << ATIM_CR2_MMS2_SHIFT) /* 0010: Update event is TRGH0*/ +# define ATIM_CR2_MMS2_COMPP (3 << ATIM_CR2_MMS2_SHIFT) /* 0010: Compare Pulse - CC1IF flag */ +# define ATIM_CR2_MMS2_OC1REF (4 << ATIM_CR2_MMS2_SHIFT) /* 0100: Compare OC1REF is TRGO2 */ +# define ATIM_CR2_MMS2_OC2REF (5 << ATIM_CR2_MMS2_SHIFT) /* 0101: Compare OC2REF is TRGO2 */ +# define ATIM_CR2_MMS2_OC3REF (6 << ATIM_CR2_MMS2_SHIFT) /* 0110: Compare OC3REF is TRGO2 */ +# define ATIM_CR2_MMS2_OC4REF (7 << ATIM_CR2_MMS2_SHIFT) /* 0111: Compare OC4REF is TRGO2 */ +# define ATIM_CR2_MMS2_OC5REF (8 << ATIM_CR2_MMS2_SHIFT) /* 1000: Compare OC5REF is TRGO2 */ +# define ATIM_CR2_MMS2_OC6REF (9 << ATIM_CR2_MMS2_SHIFT) /* 1001: Compare OC6REF is TRGO2 */ +# define ATIM_CR2_MMS2_CMPOC4 (10 << ATIM_CR2_MMS2_SHIFT) /* 1010: Compare pulse - OC4REF edge is TRGO2 */ +# define ATIM_CR2_MMS2_CMPOC6 (11 << ATIM_CR2_MMS2_SHIFT) /* 1011: Compare pulse - OC6REF edge is TRGO2 */ +# define ATIM_CR2_MMS2_CMPOC4R6R (12 << ATIM_CR2_MMS2_SHIFT) /* 1100: Compare pulse - OC4REF/OC6REF rising */ +# define ATIM_CR2_MMS2_CMPOC4R6F (13 << ATIM_CR2_MMS2_SHIFT) /* 1101: Compare pulse - OC4REF rising/OC6REF falling */ +# define ATIM_CR2_MMS2_CMPOC5R6R (14 << ATIM_CR2_MMS2_SHIFT) /* 1110: Compare pulse - OC5REF/OC6REF rising */ +# define ATIM_CR2_MMS2_CMPOC5R6F (15 << ATIM_CR2_MMS2_SHIFT) /* 1111: Compare pulse - OC5REF rising/OC6REF falling */ + +/* Slave mode control register */ + +#define ATIM_SMCR_SMS_SHIFT (0) /* Bits 0-2: Slave mode selection */ +#define ATIM_SMCR_SMS_MASK (7 << ATIM_SMCR_SMS_SHIFT) +# define ATIM_SMCR_DISAB (0 << ATIM_SMCR_SMS_SHIFT) /* 000: Slave mode disabled */ +# define ATIM_SMCR_ENCMD1 (1 << ATIM_SMCR_SMS_SHIFT) /* 001: Encoder mode 1 */ +# define ATIM_SMCR_ENCMD2 (2 << ATIM_SMCR_SMS_SHIFT) /* 010: Encoder mode 2 */ +# define ATIM_SMCR_ENCMD3 (3 << ATIM_SMCR_SMS_SHIFT) /* 011: Encoder mode 3 */ +# define ATIM_SMCR_RESET (4 << ATIM_SMCR_SMS_SHIFT) /* 100: Reset Mode */ +# define ATIM_SMCR_GATED (5 << ATIM_SMCR_SMS_SHIFT) /* 101: Gated Mode */ +# define ATIM_SMCR_TRIGGER (6 << ATIM_SMCR_SMS_SHIFT) /* 110: Trigger Mode */ +# define ATIM_SMCR_EXTCLK1 (7 << ATIM_SMCR_SMS_SHIFT) /* 111: External Clock Mode 1 */ +#define ATIM_SMCR_TS_SHIFT (4) /* Bits 4-6: Trigger selection */ +#define ATIM_SMCR_TS_MASK (7 << ATIM_SMCR_TS_SHIFT) +# define ATIM_SMCR_ITR0 (0 << ATIM_SMCR_TS_SHIFT) /* 000: Internal trigger 0 (ITR0) */ +# define ATIM_SMCR_ITR1 (1 << ATIM_SMCR_TS_SHIFT) /* 001: Internal trigger 1 (ITR1) */ +# define ATIM_SMCR_ITR2 (2 << ATIM_SMCR_TS_SHIFT) /* 010: Internal trigger 2 (ITR2) */ +# define ATIM_SMCR_ITR3 (3 << ATIM_SMCR_TS_SHIFT) /* 011: Internal trigger 3 (ITR3) */ +# define ATIM_SMCR_T1FED (4 << ATIM_SMCR_TS_SHIFT) /* 100: TI1 Edge Detector (TI1F_ED) */ +# define ATIM_SMCR_TI1FP1 (5 << ATIM_SMCR_TS_SHIFT) /* 101: Filtered Timer Input 1 (TI1FP1) */ +# define ATIM_SMCR_T12FP2 (6 << ATIM_SMCR_TS_SHIFT) /* 110: Filtered Timer Input 2 (TI2FP2) */ +# define ATIM_SMCR_ETRF (7 << ATIM_SMCR_TS_SHIFT) /* 111: External Trigger input (ETRF) */ +#define ATIM_SMCR_MSM (1 << 7) /* Bit 7: Master/slave mode */ +#define ATIM_SMCR_ETF_SHIFT (8) /* Bits 8-11: External trigger filter */ +#define ATIM_SMCR_ETF_MASK (0x0f << ATIM_SMCR_ETF_SHIFT) +# define ATIM_SMCR_NOFILT (0 << ATIM_SMCR_ETF_SHIFT) /* 0000: No filter, sampling is done at fDTS */ +# define ATIM_SMCR_FCKINT2 (1 << ATIM_SMCR_ETF_SHIFT) /* 0001: fSAMPLING=fCK_INT, N=2 */ +# define ATIM_SMCR_FCKINT4 (2 << ATIM_SMCR_ETF_SHIFT) /* 0010: fSAMPLING=fCK_INT, N=4 */ +# define ATIM_SMCR_FCKINT8 (3 << ATIM_SMCR_ETF_SHIFT) /* 0011: fSAMPLING=fCK_INT, N=8 */ +# define ATIM_SMCR_FDTSd26 (4 << ATIM_SMCR_ETF_SHIFT) /* 0100: fSAMPLING=fDTS/2, N=6 */ +# define ATIM_SMCR_FDTSd28 (5 << ATIM_SMCR_ETF_SHIFT) /* 0101: fSAMPLING=fDTS/2, N=8 */ +# define ATIM_SMCR_FDTSd46 (6 << ATIM_SMCR_ETF_SHIFT) /* 0110: fSAMPLING=fDTS/4, N=6 */ +# define ATIM_SMCR_FDTSd48 (7 << ATIM_SMCR_ETF_SHIFT) /* 0111: fSAMPLING=fDTS/4, N=8 */ +# define ATIM_SMCR_FDTSd86 (8 << ATIM_SMCR_ETF_SHIFT) /* 1000: fSAMPLING=fDTS/8, N=6 */ +# define ATIM_SMCR_FDTSd88 (9 << ATIM_SMCR_ETF_SHIFT) /* 1001: fSAMPLING=fDTS/8, N=8 */ +# define ATIM_SMCR_FDTSd165 (10 << ATIM_SMCR_ETF_SHIFT) /* 1010: fSAMPLING=fDTS/16, N=5 */ +# define ATIM_SMCR_FDTSd166 (11 << ATIM_SMCR_ETF_SHIFT) /* 1011: fSAMPLING=fDTS/16, N=6 */ +# define ATIM_SMCR_FDTSd168 (12 << ATIM_SMCR_ETF_SHIFT) /* 1100: fSAMPLING=fDTS/16, N=8 */ +# define ATIM_SMCR_FDTSd325 (13 << ATIM_SMCR_ETF_SHIFT) /* 1101: fSAMPLING=fDTS/32, N=5 */ +# define ATIM_SMCR_FDTSd326 (14 << ATIM_SMCR_ETF_SHIFT) /* 1110: fSAMPLING=fDTS/32, N=6 */ +# define ATIM_SMCR_FDTSd328 (15 << ATIM_SMCR_ETF_SHIFT) /* 1111: fSAMPLING=fDTS/32, N=8 */ +#define ATIM_SMCR_ETPS_SHIFT (12) /* Bits 12-13: External trigger prescaler */ +#define ATIM_SMCR_ETPS_MASK (3 << ATIM_SMCR_ETPS_SHIFT) +# define ATIM_SMCR_PSCOFF (0 << ATIM_SMCR_ETPS_SHIFT) /* 00: Prescaler OFF */ +# define ATIM_SMCR_ETRPd2 (1 << ATIM_SMCR_ETPS_SHIFT) /* 01: ETRP frequency divided by 2 */ +# define ATIM_SMCR_ETRPd4 (2 << ATIM_SMCR_ETPS_SHIFT) /* 10: ETRP frequency divided by 4 */ +# define ATIM_SMCR_ETRPd8 (3 << ATIM_SMCR_ETPS_SHIFT) /* 11: ETRP frequency divided by 8 */ +#define ATIM_SMCR_ECE (1 << 14) /* Bit 14: External clock enable */ +#define ATIM_SMCR_ETP (1 << 15) /* Bit 15: External trigger polarity */ +#define ATIM_SMCR_SMS (1 << 16) /* Bit 16: Slave mode selection - bit 3 */ + +/* DMA/Interrupt enable register */ + +#define ATIM_DIER_UIE (1 << 0) /* Bit 0: Update interrupt enable */ +#define ATIM_DIER_CC1IE (1 << 1) /* Bit 1: Capture/Compare 1 interrupt enable */ +#define ATIM_DIER_CC2IE (1 << 2) /* Bit 2: Capture/Compare 2 interrupt enable */ +#define ATIM_DIER_CC3IE (1 << 3) /* Bit 3: Capture/Compare 3 interrupt enable */ +#define ATIM_DIER_CC4IE (1 << 4) /* Bit 4: Capture/Compare 4 interrupt enable */ +#define ATIM_DIER_COMIE (1 << 5) /* Bit 5: COM interrupt enable */ +#define ATIM_DIER_TIE (1 << 6) /* Bit 6: Trigger interrupt enable */ +#define ATIM_DIER_BIE (1 << 7) /* Bit 7: Break interrupt enable */ +#define ATIM_DIER_UDE (1 << 8) /* Bit 8: Update DMA request enable */ +#define ATIM_DIER_CC1DE (1 << 9) /* Bit 9: Capture/Compare 1 DMA request enable */ +#define ATIM_DIER_CC2DE (1 << 10) /* Bit 10: Capture/Compare 2 DMA request enable */ +#define ATIM_DIER_CC3DE (1 << 11) /* Bit 11: Capture/Compare 3 DMA request enable */ +#define ATIM_DIER_CC4DE (1 << 12) /* Bit 12: Capture/Compare 4 DMA request enable */ +#define ATIM_DIER_COMDE (1 << 13) /* Bit 13: COM DMA request enable */ +#define ATIM_DIER_TDE (1 << 14) /* Bit 14: Trigger DMA request enable */ + +/* Status register */ + +#define ATIM_SR_UIF (1 << 0) /* Bit 0: Update interrupt Flag */ +#define ATIM_SR_CC1IF (1 << 1) /* Bit 1: Capture/Compare 1 interrupt Flag */ +#define ATIM_SR_CC2IF (1 << 2) /* Bit 2: Capture/Compare 2 interrupt Flag */ +#define ATIM_SR_CC3IF (1 << 3) /* Bit 3: Capture/Compare 3 interrupt Flag */ +#define ATIM_SR_CC4IF (1 << 4) /* Bit 4: Capture/Compare 4 interrupt Flag */ +#define ATIM_SR_COMIF (1 << 5) /* Bit 5: COM interrupt Flag */ +#define ATIM_SR_TIF (1 << 6) /* Bit 6: Trigger interrupt Flag */ +#define ATIM_SR_BIF (1 << 7) /* Bit 7: Break interrupt Flag */ +#define ATIM_SR_B2IF (1 << 8) /* Bit 8: Break 2 interrupt Flag */ +#define ATIM_SR_CC1OF (1 << 9) /* Bit 9: Capture/Compare 1 Overcapture Flag */ +#define ATIM_SR_CC2OF (1 << 10) /* Bit 10: Capture/Compare 2 Overcapture Flag */ +#define ATIM_SR_CC3OF (1 << 11) /* Bit 11: Capture/Compare 3 Overcapture Flag */ +#define ATIM_SR_CC4OF (1 << 12) /* Bit 12: Capture/Compare 4 Overcapture Flag */ +#define ATIM_SR_CC5IF (1 << 16) /* Bit 16: Compare 5 interrupt flag */ +#define ATIM_SR_CC6IF (1 << 17) /* Bit 17: Compare 6 interrupt flag */ + +/* Event generation register */ + +#define ATIM_EGR_UG (1 << 0) /* Bit 0: Update Generation */ +#define ATIM_EGR_CC1G (1 << 1) /* Bit 1: Capture/Compare 1 Generation */ +#define ATIM_EGR_CC2G (1 << 2) /* Bit 2: Capture/Compare 2 Generation */ +#define ATIM_EGR_CC3G (1 << 3) /* Bit 3: Capture/Compare 3 Generation */ +#define ATIM_EGR_CC4G (1 << 4) /* Bit 4: Capture/Compare 4 Generation */ +#define ATIM_EGR_COMG (1 << 5) /* Bit 5: Capture/Compare Control Update Generation */ +#define ATIM_EGR_TG (1 << 6) /* Bit 6: Trigger Generation */ +#define ATIM_EGR_BG (1 << 7) /* Bit 7: Break Generation */ +#define ATIM_EGR_B2G (1 << 8) /* Bit 8: Break 2 Generation */ + +/* Capture/compare mode register 1 -- Output compare mode */ + +#define ATIM_CCMR1_CC1S_SHIFT (0) /* Bits 1-0: Capture/Compare 1 Selection */ +#define ATIM_CCMR1_CC1S_MASK (3 << ATIM_CCMR1_CC1S_SHIFT) + /* (See common (unshifted) bit field definitions below) */ +#define ATIM_CCMR1_OC1FE (1 << 2) /* Bit 2: Output Compare 1 Fast enable */ +#define ATIM_CCMR1_OC1PE (1 << 3) /* Bit 3: Output Compare 1 Preload enable */ +#define ATIM_CCMR1_OC1M_SHIFT (4) /* Bits 6-4: Output Compare 1 Mode */ +#define ATIM_CCMR1_OC1M_MASK (7 << ATIM_CCMR1_OC1M_SHIFT) + /* (See common (unshifted) bit field definitions below) */ +#define ATIM_CCMR1_OC1CE (1 << 7) /* Bit 7: Output Compare 1Clear Enable */ +#define ATIM_CCMR1_CC2S_SHIFT (8) /* Bits 8-9: Capture/Compare 2 Selection */ +#define ATIM_CCMR1_CC2S_MASK (3 << ATIM_CCMR1_CC2S_SHIFT) + /* (See common (unshifted) bit field definitions below) */ +#define ATIM_CCMR1_OC2FE (1 << 10) /* Bit 10: Output Compare 2 Fast enable */ +#define ATIM_CCMR1_OC2PE (1 << 11) /* Bit 11: Output Compare 2 Preload enable */ +#define ATIM_CCMR1_OC2M_SHIFT (12) /* Bits 14-12: Output Compare 2 Mode */ +#define ATIM_CCMR1_OC2M_MASK (7 << ATIM_CCMR1_OC2M_SHIFT) + /* (See common (unshifted) bit field definitions below) */ +#define ATIM_CCMR1_OC2CE (1 << 15) /* Bit 15: Output Compare 2 Clear Enable */ +#define ATIM_CCMR1_OC1M (1 << 16) /* Bit 16: Output Compare 1 mode - bit 3 */ +#define ATIM_CCMR1_OC2M (1 << 24) /* Bit 24: Output Compare 2 mode - bit 3 */ + + +/* Common CCMR (unshifted) Capture/Compare Selection bit-field definitions */ + +#define ATIM_CCMR_CCS_CCOUT (0) /* 00: CCx channel output */ +#define ATIM_CCMR_CCS_CCIN1 (1) /* 01: CCx channel input, ICx is TIx */ +#define ATIM_CCMR_CCS_CCIN2 (2) /* 10: CCx channel input, ICx is TIy */ +#define ATIM_CCMR_CCS_CCINTRC (3) /* 11: CCx channel input, ICx is TRC */ + +/* Common CCMR (unshifted) Compare Mode bit field definitions */ + +#define ATIM_CCMR_MODE_FRZN (0) /* 0000: Frozen */ +#define ATIM_CCMR_MODE_CHACT (1) /* 0001: Channel x active on match */ +#define ATIM_CCMR_MODE_CHINACT (2) /* 0010: Channel x inactive on match */ +#define ATIM_CCMR_MODE_OCREFTOG (3) /* 0011: OCxREF toggle ATIM_CNT=ATIM_CCRx */ +#define ATIM_CCMR_MODE_OCREFLO (4) /* 0100: OCxREF forced low */ +#define ATIM_CCMR_MODE_OCREFHI (5) /* 0101: OCxREF forced high */ +#define ATIM_CCMR_MODE_PWM1 (6) /* 0110: PWM mode 1 */ +#define ATIM_CCMR_MODE_PWM2 (7) /* 0111: PWM mode 2 */ +#define ATIM_CCMR_MODE_OPM1 (8) /* 1000: Retrigerrable OPM mode 1 */ +#define ATIM_CCMR_MODE_OPM2 (9) /* 1001: Retrigerrable OPM mode 2 */ +#define ATIM_CCMR_MODE_COMBINED1 (12) /* 1100: Combined PWM mode 1 */ +#define ATIM_CCMR_MODE_COMBINED2 (13) /* 1101: Combined PWM mode 2 */ +#define ATIM_CCMR_MODE_ASYMMETRIC1 (14) /* 1110: Asymmetric PWM mode 1 */ +#define ATIM_CCMR_MODE_ASYMMETRIC2 (15) /* 1111: Asymmetric PWM mode 2 */ + +/* Capture/compare mode register 1 -- Input capture mode */ + + /* Bits 1-0:(same as output compare mode) */ +#define ATIM_CCMR1_IC1PSC_SHIFT (2) /* Bits 3-2: Input Capture 1 Prescaler */ +#define ATIM_CCMR1_IC1PSC_MASK (3 << ATIM_CCMR1_IC1PSC_SHIFT) + /* (See common (unshifted) bit field definitions below) */ +#define ATIM_CCMR1_IC1F_SHIFT (4) /* Bits 7-4: Input Capture 1 Filter */ +#define ATIM_CCMR1_IC1F_MASK (0x0f << ATIM_CCMR1_IC1F_SHIFT) + /* (See common (unshifted) bit field definitions below) */ + /* Bits 9:8 (same as output compare mode) */ +#define ATIM_CCMR1_IC2PSC_SHIFT (10) /* Bits 11:10: Input Capture 2 Prescaler */ +#define ATIM_CCMR1_IC2PSC_MASK (3 << ATIM_CCMR1_IC2PSC_SHIFT) + /* (See common (unshifted) bit field definitions below) */ +#define ATIM_CCMR1_IC2F_SHIFT (12) /* Bits 15-12: Input Capture 2 Filter */ +#define ATIM_CCMR1_IC2F_MASK (0x0f << ATIM_CCMR1_IC2F_SHIFT) + /* (See common (unshifted) bit field definitions below) */ + +/* Common CCMR (unshifted) Input Capture Prescaler bit-field definitions */ + +#define ATIM_CCMR_ICPSC_NOPSC (0) /* 00: no prescaler, capture each edge */ +#define ATIM_CCMR_ICPSC_EVENTS2 (1) /* 01: capture once every 2 events */ +#define ATIM_CCMR_ICPSC_EVENTS4 (2) /* 10: capture once every 4 events */ +#define ATIM_CCMR_ICPSC_EVENTS8 (3) /* 11: capture once every 8 events */ + +/* Common CCMR (unshifted) Input Capture Filter bit-field definitions */ + +#define ATIM_CCMR_ICF_NOFILT (0) /* 0000: No filter, sampling at fDTS */ +#define ATIM_CCMR_ICF_FCKINT2 (1) /* 0001: fSAMPLING=fCK_INT, N=2 */ +#define ATIM_CCMR_ICF_FCKINT4 (2) /* 0010: fSAMPLING=fCK_INT, N=4 */ +#define ATIM_CCMR_ICF_FCKINT8 (3) /* 0011: fSAMPLING=fCK_INT, N=8 */ +#define ATIM_CCMR_ICF_FDTSd26 (4) /* 0100: fSAMPLING=fDTS/2, N=6 */ +#define ATIM_CCMR_ICF_FDTSd28 (5) /* 0101: fSAMPLING=fDTS/2, N=8 */ +#define ATIM_CCMR_ICF_FDTSd46 (6) /* 0110: fSAMPLING=fDTS/4, N=6 */ +#define ATIM_CCMR_ICF_FDTSd48 (7) /* 0111: fSAMPLING=fDTS/4, N=8 */ +#define ATIM_CCMR_ICF_FDTSd86 (8) /* 1000: fSAMPLING=fDTS/8, N=6 */ +#define ATIM_CCMR_ICF_FDTSd88 (9) /* 1001: fSAMPLING=fDTS/8, N=8 */ +#define ATIM_CCMR_ICF_FDTSd165 (10) /* 1010: fSAMPLING=fDTS/16, N=5 */ +#define ATIM_CCMR_ICF_FDTSd166 (11) /* 1011: fSAMPLING=fDTS/16, N=6 */ +#define ATIM_CCMR_ICF_FDTSd168 (12) /* 1100: fSAMPLING=fDTS/16, N=8 */ +#define ATIM_CCMR_ICF_FDTSd325 (13) /* 1101: fSAMPLING=fDTS/32, N=5 */ +#define ATIM_CCMR_ICF_FDTSd326 (14) /* 1110: fSAMPLING=fDTS/32, N=6 */ +#define ATIM_CCMR_ICF_FDTSd328 (15) /* 1111: fSAMPLING=fDTS/32, N=8 */ + +/* Capture/compare mode register 2 - Output Compare mode */ + +#define ATIM_CCMR2_CC3S_SHIFT (0) /* Bits 1-0: Capture/Compare 3 Selection */ +#define ATIM_CCMR2_CC3S_MASK (3 << ATIM_CCMR2_CC3S_SHIFT) + /* (See common (unshifted) bit field definitions above) */ +#define ATIM_CCMR2_OC3FE (1 << 2) /* Bit 2: Output Compare 3 Fast enable */ +#define ATIM_CCMR2_OC3PE (1 << 3) /* Bit 3: Output Compare 3 Preload enable */ +#define ATIM_CCMR2_OC3M_SHIFT (4) /* Bits 6-4: Output Compare 3 Mode */ +#define ATIM_CCMR2_OC3M_MASK (7 << ATIM_CCMR2_OC3M_SHIFT) + /* (See common (unshifted) bit field definitions above) */ +#define ATIM_CCMR2_OC3CE (1 << 7) /* Bit 7: Output Compare 3 Clear Enable */ +#define ATIM_CCMR2_CC4S_SHIFT (8) /* Bits 9-8: Capture/Compare 4 Selection */ +#define ATIM_CCMR2_CC4S_MASK (3 << ATIM_CCMR2_CC4S_SHIFT) + /* (See common (unshifted) bit field definitions above) */ +#define ATIM_CCMR2_OC4FE (1 << 10) /* Bit 10: Output Compare 4 Fast enable */ +#define ATIM_CCMR2_OC4PE (1 << 11) /* Bit 11: Output Compare 4 Preload enable */ +#define ATIM_CCMR2_OC4M_SHIFT (12) /* Bits 14-12: Output Compare 4 Mode */ +#define ATIM_CCMR2_OC4M_MASK (7 << ATIM_CCMR2_OC4M_SHIFT) + /* (See common (unshifted) bit field definitions above) */ +#define ATIM_CCMR2_OC4CE (1 << 15) /* Bit 15: Output Compare 4 Clear Enable */ +#define ATIM_CCMR2_OC3M (1 << 16) /* Bit 16: Output Compare 3 mode - bit 3 */ +#define ATIM_CCMR2_OC4M (1 << 24) /* Bit 24: Output Compare 4 mode - bit 3 */ + +/* Capture/compare mode register 2 - Input Capture Mode */ + + /* Bits 1-0:(same as output compare mode) */ +#define ATIM_CCMR2_IC3PSC_SHIFT (2) /* Bits 3-2: Input Capture 3 Prescaler */ +#define ATIM_CCMR1_IC3PSC_MASK (3 << ATIM_CCMR2_IC3PSC_SHIFT) + /* (See common (unshifted) bit field definitions above) */ +#define ATIM_CCMR2_IC3F_SHIFT (4) /* Bits 7-4: Input Capture 3 Filter */ +#define ATIM_CCMR2_IC3F_MASK (0x0f << ATIM_CCMR2_IC3F_SHIFT) + /* (See common (unshifted) bit field definitions above) */ + /* Bits 9:8 (same as output compare mode) */ +#define ATIM_CCMR2_IC4PSC_SHIFT (10) /* Bits 11:10: Input Capture 4 Prescaler */ +#define ATIM_CCMR2_IC4PSC_MASK (3 << ATIM_CCMR2_IC4PSC_SHIFT) + /* (See common (unshifted) bit field definitions above) */ +#define ATIM_CCMR2_IC4F_SHIFT (12) /* Bits 15-12: Input Capture 4 Filter */ +#define ATIM_CCMR2_IC4F_MASK (0x0f << ATIM_CCMR2_IC4F_SHIFT) + /* (See common (unshifted) bit field definitions above) */ + +/* Capture/compare mode register 3 -- Output compare mode */ + +#define ATIM_CCMR3_OC5FE (1 << 2) /* Bit 2: Output Compare 5 Fast enable */ +#define ATIM_CCMR3_OC5PE (1 << 3) /* Bit 3: Output Compare 5 Preload enable */ +#define ATIM_CCMR3_OC5M_SHIFT (4) /* Bits 6-4: Output Compare 5 Mode */ +#define ATIM_CCMR3_OC5M_MASK (7 << ATIM_CCMR3_OC5M_SHIFT) + /* (See common (unshifted) bit field definitions below) */ +#define ATIM_CCMR3_OC5CE (1 << 7) /* Bit 7: Output Compare 5 Clear Enable */ +#define ATIM_CCMR3_OC6FE (1 << 10) /* Bit 10: Output Compare 6 Fast enable */ +#define ATIM_CCMR3_OC6PE (1 << 11) /* Bit 11: Output Compare 6 Preload enable */ +#define ATIM_CCMR3_OC6M_SHIFT (12) /* Bits 14-12: Output Compare 7 Mode */ +#define ATIM_CCMR3_OC6M_MASK (7 << ATIM_CCMR3_OC6M_SHIFT) + /* (See common (unshifted) bit field definitions below) */ +#define ATIM_CCMR3_OC6CE (1 << 15) /* Bit 15: Output Compare 7 Clear Enable */ +#define ATIM_CCMR3_OC5M (1 << 16) /* Bit 16: Output Compare 5 mode - bit 3 */ +#define ATIM_CCMR3_OC6M (1 << 24) /* Bit 24: Output Compare 6 mode - bit 3 */ + + +/* Capture/compare enable register */ + +#define ATIM_CCER_CC1E (1 << 0) /* Bit 0: Capture/Compare 1 output enable */ +#define ATIM_CCER_CC1P (1 << 1) /* Bit 1: Capture/Compare 1 output Polarity */ +#define ATIM_CCER_CC1NE (1 << 2) /* Bit 2: Capture/Compare 1 Complementary output enable */ +#define ATIM_CCER_CC1NP (1 << 3) /* Bit 3: Capture/Compare 1 Complementary output polarity */ +#define ATIM_CCER_CC2E (1 << 4) /* Bit 4: Capture/Compare 2 output enable */ +#define ATIM_CCER_CC2P (1 << 5) /* Bit 5: Capture/Compare 2 output Polarity */ +#define ATIM_CCER_CC2NE (1 << 6) /* Bit 6: Capture/Compare 2 Complementary output enable */ +#define ATIM_CCER_CC2NP (1 << 7) /* Bit 7: Capture/Compare 2 Complementary output polarity */ +#define ATIM_CCER_CC3E (1 << 8) /* Bit 8: Capture/Compare 3 output enable */ +#define ATIM_CCER_CC3P (1 << 9) /* Bit 9: Capture/Compare 3 output Polarity */ +#define ATIM_CCER_CC3NE (1 << 10) /* Bit 10: Capture/Compare 3 Complementary output enable */ +#define ATIM_CCER_CC3NP (1 << 11) /* Bit 11: Capture/Compare 3 Complementary output polarity */ +#define ATIM_CCER_CC4E (1 << 12) /* Bit 12: Capture/Compare 4 output enable */ +#define ATIM_CCER_CC4P (1 << 13) /* Bit 13: Capture/Compare 4 output Polarity */ +#define ATIM_CCER_CC4NP (1 << 15) /* Bit 15: Capture/Compare 4 Complementary output polarity */ +#define ATIM_CCER_CC5E (1 << 16) /* Bit 16: Capture/Compare 5 output enable */ +#define ATIM_CCER_CC5P (1 << 17) /* Bit 17: Capture/Compare 5 output Polarity */ +#define ATIM_CCER_CC6E (1 << 20) /* Bit 20: Capture/Compare 6 output enable */ +#define ATIM_CCER_CC6P (1 << 21) /* Bit 21: Capture/Compare 6 output Polarity */ + + +/* 16-bit counter register */ + +#define ATIM_CNT_SHIFT (0) /* Bits 0-15: Timer counter value */ +#define ATIM_CNT_MASK (0xffff << ATIM_CNT_SHIFT) + +/* Repetition counter register */ + +#define ATIM_RCR_REP_SHIFT (0) /* Bits 0-15: Repetition Counter Value */ +#define ATIM_RCR_REP_MASK (0xffff << ATIM_RCR_REP_SHIFT) + +#define ATIM_RCR_REP_MAX 65536 + +/* Capture/compare registers (CCR) */ + +#define ATIM_CCR5_GC5C1 (1 << 29) /* Bit 29: Group Channel 5 and Channel 1 */ +#define ATIM_CCR5_GC5C2 (1 << 30) /* Bit 30: Group Channel 5 and Channel 2 */ +#define ATIM_CCR5_GC5C3 (1 << 31) /* Bit 31: Group Channel 5 and Channel 3 */ + +#define ATIM_CCR_MASK (0xffff) + +/* Break and dead-time register */ + +#define ATIM_BDTR_DTG_SHIFT (0) /* Bits 7:0 [7:0]: Dead-Time Generator set-up */ +#define ATIM_BDTR_DTG_MASK (0xff << ATIM_BDTR_DTG_SHIFT) +#define ATIM_BDTR_LOCK_SHIFT (8) /* Bits 9:8 [1:0]: Lock Configuration */ +#define ATIM_BDTR_LOCK_MASK (3 << ATIM_BDTR_LOCK_SHIFT) +# define ATIM_BDTR_LOCKOFF (0 << ATIM_BDTR_LOCK_SHIFT) /* 00: LOCK OFF - No bit is write protected */ +# define ATIM_BDTR_LOCK1 (1 << ATIM_BDTR_LOCK_SHIFT) /* 01: LOCK Level 1 protection */ +# define ATIM_BDTR_LOCK2 (2 << ATIM_BDTR_LOCK_SHIFT) /* 10: LOCK Level 2 protection */ +# define ATIM_BDTR_LOCK3 (3 << ATIM_BDTR_LOCK_SHIFT) /* 11: LOCK Level 3 protection */ */ +#define ATIM_BDTR_OSSI (1 << 10) /* Bit 10: Off-State Selection for Idle mode */ +#define ATIM_BDTR_OSSR (1 << 11) /* Bit 11: Off-State Selection for Run mode */ +#define ATIM_BDTR_BKE (1 << 12) /* Bit 12: Break enable */ +#define ATIM_BDTR_BKP (1 << 13) /* Bit 13: Break Polarity */ +#define ATIM_BDTR_AOE (1 << 14) /* Bit 14: Automatic Output enable */ +#define ATIM_BDTR_MOE (1 << 15) /* Bit 15: Main Output enable */ +#define ATIM_BDTR_BKF_SHIFT (16) /* Bits 16-19: Break filter */ +#define ATIM_BDTR_BKF_MASK (0xf << ATIM_BDTR_BKF_SHIFT) +# define ATIM_BDTR_BKF_NOFILT (0 << ATIM_BDTR_BKF_SHIFT) /* 0000: No filter, BRK acts asynchronously */ +# define ATIM_BDTR_BKF_FCKINT2 (1 << ATIM_BDTR_BKF_SHIFT) /* 0001: fSAMPLING=fCK_INT, N=2 */ +# define ATIM_BDTR_BKF_FCKINT4 (2 << ATIM_BDTR_BKF_SHIFT) /* 0010: fSAMPLING=fCK_INT, N=4 */ +# define ATIM_BDTR_BKF_FCKINT8 (3 << ATIM_BDTR_BKF_SHIFT) /* 0011: fSAMPLING=fCK_INT, N=8 */ +# define ATIM_BDTR_BKF_FDTSd26 (4 << ATIM_BDTR_BKF_SHIFT) /* 0100: fSAMPLING=fDTS/2, N=6 */ +# define ATIM_BDTR_BKF_FDTSd28 (5 << ATIM_BDTR_BKF_SHIFT) /* 0101: fSAMPLING=fDTS/2, N=8 */ +# define ATIM_BDTR_BKF_FDTSd36 (6 << ATIM_BDTR_BKF_SHIFT) /* 0110: fSAMPLING=fDTS/4, N=6 */ +# define ATIM_BDTR_BKF_FDTSd38 (7 << ATIM_BDTR_BKF_SHIFT) /* 0111: fSAMPLING=fDTS/4, N=8 */ +# define ATIM_BDTR_BKF_FDTSd86 (8 << ATIM_BDTR_BKF_SHIFT) /* 1000: fSAMPLING=fDTS/8, N=6 */ +# define ATIM_BDTR_BKF_FDTSd88 (9 << ATIM_BDTR_BKF_SHIFT) /* 1001: fSAMPLING=fDTS/8, N=8 */ +# define ATIM_BDTR_BKF_FDTSd165 (10 << ATIM_BDTR_BKF_SHIFT) /* 1010: fSAMPLING=fDTS/16, N=5 */ +# define ATIM_BDTR_BKF_FDTSd166 (11 << ATIM_BDTR_BKF_SHIFT) /* 1011: fSAMPLING=fDTS/16, N=6 */ +# define ATIM_BDTR_BKF_FDTSd168 (12 << ATIM_BDTR_BKF_SHIFT) /* 1100: fSAMPLING=fDTS/16, N=8 */ +# define ATIM_BDTR_BKF_FDTSd325 (13 << ATIM_BDTR_BKF_SHIFT) /* 1101: fSAMPLING=fDTS/32, N=5 */ +# define ATIM_BDTR_BKF_FDTSd326 (14 << ATIM_BDTR_BKF_SHIFT) /* 1110: fSAMPLING=fDTS/32, N=6 */ +# define ATIM_BDTR_BKF_FDTSd328 (15 << ATIM_BDTR_BKF_SHIFT) /* 1111: fSAMPLING=fDTS/32, N=8 */ +#define ATIM_BDTR_BK2F_SHIFT (20) /* Bits 20-23: Break 2 filter */ +#define ATIM_BDTR_BK2F_MASK (0xf << ATIM_BDTR_BK2F_SHIFT) +# define ATIM_BDTR_BK2F_NOFILT (0 << ATIM_BDTR_BK2F_SHIFT) /* 0000: No filter, BRK 2 acts asynchronously */ +# define ATIM_BDTR_BK2F_FCKINT2 (1 << ATIM_BDTR_BK2F_SHIFT) /* 0001: fSAMPLING=fCK_INT, N=2 */ +# define ATIM_BDTR_BK2F_FCKINT4 (2 << ATIM_BDTR_BK2F_SHIFT) /* 0010: fSAMPLING=fCK_INT, N=4 */ +# define ATIM_BDTR_BK2F_FCKINT8 (3 << ATIM_BDTR_BK2F_SHIFT) /* 0011: fSAMPLING=fCK_INT, N=8 */ +# define ATIM_BDTR_BK2F_FDTSd26 (4 << ATIM_BDTR_BK2F_SHIFT) /* 0100: fSAMPLING=fDTS/2, N=6 */ +# define ATIM_BDTR_BK2F_FDTSd28 (5 << ATIM_BDTR_BK2F_SHIFT) /* 0101: fSAMPLING=fDTS/2, N=8 */ +# define ATIM_BDTR_BK2F_FDTSd36 (6 << ATIM_BDTR_BK2F_SHIFT) /* 0110: fSAMPLING=fDTS/4, N=6 */ +# define ATIM_BDTR_BK2F_FDTSd38 (7 << ATIM_BDTR_BK2F_SHIFT) /* 0111: fSAMPLING=fDTS/4, N=8 */ +# define ATIM_BDTR_BK2F_FDTSd86 (8 << ATIM_BDTR_BK2F_SHIFT) /* 1000: fSAMPLING=fDTS/8, N=6 */ +# define ATIM_BDTR_BK2F_FDTSd88 (9 << ATIM_BDTR_BK2F_SHIFT) /* 1001: fSAMPLING=fDTS/8, N=8 */ +# define ATIM_BDTR_BK2F_FDTSd165 (10 << ATIM_BDTR_BK2F_SHIFT) /* 1010: fSAMPLING=fDTS/16, N=5 */ +# define ATIM_BDTR_BK2F_FDTSd166 (11 << ATIM_BDTR_BK2F_SHIFT) /* 1011: fSAMPLING=fDTS/16, N=6 */ +# define ATIM_BDTR_BK2F_FDTSd168 (12 << ATIM_BDTR_BK2F_SHIFT) /* 1100: fSAMPLING=fDTS/16, N=8 */ +# define ATIM_BDTR_BK2F_FDTSd325 (13 << ATIM_BDTR_BK2F_SHIFT) /* 1101: fSAMPLING=fDTS/32, N=5 */ +# define ATIM_BDTR_BK2F_FDTSd326 (14 << ATIM_BDTR_BK2F_SHIFT) /* 1110: fSAMPLING=fDTS/32, N=6 */ +# define ATIM_BDTR_BK2F_FDTSd328 (15 << ATIM_BDTR_BK2F_SHIFT) /* 1111: fSAMPLING=fDTS/32, N=8 */ +#define ATIM_BDTR_BK2E (1 << 24) /* Bit 24: Break 2 enable */ +#define ATIM_BDTR_BK2P (1 << 1525 /* Bit 25:Break 2 polarity */ + + +/* DMA control register */ + +#define ATIM_DCR_DBA_SHIFT (0) /* Bits 4-0: DMA Base Address */ +#define ATIM_DCR_DBA_MASK (0x1f << ATIM_DCR_DBA_SHIFT) +#define ATIM_DCR_DBL_SHIFT (8) /* Bits 12-8: DMA Burst Length */ +#define ATIM_DCR_DBL_MASK (0x1f << ATIM_DCR_DBL_SHIFT) +# define ATIM_DCR_DBL(n) (((n)-1) << ATIM_DCR_DBL_SHIFT) /* n transfers, n = 1..18 */ + +/* Control register 1 (TIM2-5 and TIM9-14) */ + +#define GTIM_CR1_CEN (1 << 0) /* Bit 0: Counter enable */ +#define GTIM_CR1_UDIS (1 << 1) /* Bit 1: Update Disable */ +#define GTIM_CR1_URS (1 << 2) /* Bit 2: Update Request Source */ +#define GTIM_CR1_OPM (1 << 3) /* Bit 3: One Pulse Mode (TIM2-5, 9, and 12 only) */ +#define GTIM_CR1_DIR (1 << 4) /* Bit 4: Direction (TIM2-5 only) */ +#define GTIM_CR1_CMS_SHIFT (5) /* Bits 6-5: Center-aligned Mode Selection (TIM2-5 only) */ +#define GTIM_CR1_CMS_MASK (3 << GTIM_CR1_CMS_SHIFT) +# define GTIM_CR1_EDGE (0 << GTIM_CR1_CMS_SHIFT) /* 00: Edge-aligned mode. */ +# define GTIM_CR1_CENTER1 (1 << GTIM_CR1_CMS_SHIFT) /* 01: Center-aligned mode 1 */ +# define GTIM_CR1_CENTER2 (2 << GTIM_CR1_CMS_SHIFT) /* 10: Center-aligned mode 2 */ +# define GTIM_CR1_CENTER3 (3 << GTIM_CR1_CMS_SHIFT) /* 11: Center-aligned mode 3 */ +#define GTIM_CR1_ARPE (1 << 7) /* Bit 7: Auto-Reload Preload enable */ +#define GTIM_CR1_CKD_SHIFT (8) /* Bits 9-8: Clock Division */ +#define GTIM_CR1_CKD_MASK (3 << GTIM_CR1_CKD_SHIFT) +# define GTIM_CR1_TCKINT (0 << GTIM_CR1_CKD_SHIFT) /* 00: tDTS = tCK_INT */ +# define GTIM_CR1_2TCKINT (1 << GTIM_CR1_CKD_SHIFT) /* 01: tDTS = 2 x tCK_INT */ +# define GTIM_CR1_4TCKINT (2 << GTIM_CR1_CKD_SHIFT) /* 10: tDTS = 4 x tCK_INT */ +#define GTIM_CR1_UIFREMAP (1 << 11) /* Bit 11: UIF status bit remapping */ + +/* Control register 2 (TIM2-5, TIM9-12) */ + +#define GTIM_CR2_CCPC (1 << 0) /* Bit 0: Capture/compare preloaded control (TIM15-17 only) */ +#define GTIM_CR2_CCUS (1 << 2) /* Bit 2: Capture/compare control update selection (TIM15-17 only) */ +#define GTIM_CR2_CCDS (1 << 3) /* Bit 3: Capture/Compare DMA Selection (TIM2-5,1,&16 only) */ +#define GTIM_CR2_MMS_SHIFT (4) /* Bits 6-4: Master Mode Selection (not TIM16) */ +#define GTIM_CR2_MMS_MASK (7 << GTIM_CR2_MMS_SHIFT) +# define GTIM_CR2_MMS_RESET (0 << GTIM_CR2_MMS_SHIFT) /* 000: Reset */ +# define GTIM_CR2_MMS_ENABLE (1 << GTIM_CR2_MMS_SHIFT) /* 001: Enable */ +# define GTIM_CR2_MMS_UPDATE (2 << GTIM_CR2_MMS_SHIFT) /* 010: Update */ +# define GTIM_CR2_MMS_COMPP (3 << GTIM_CR2_MMS_SHIFT) /* 011: Compare Pulse */ +# define GTIM_CR2_MMS_OC1REF (4 << GTIM_CR2_MMS_SHIFT) /* 100: Compare - OC1REF signal is used as trigger output (TRGO) */ +# define GTIM_CR2_MMS_OC2REF (5 << GTIM_CR2_MMS_SHIFT) /* 101: Compare - OC2REF signal is used as trigger output (TRGO) */ +# define GTIM_CR2_MMS_OC3REF (6 << GTIM_CR2_MMS_SHIFT) /* 110: Compare - OC3REF signal is used as trigger output (TRGO, TIM2-5 and TIM15 only) */ +# define GTIM_CR2_MMS_OC4REF (7 << GTIM_CR2_MMS_SHIFT) /* 111: Compare - OC4REF signal is used as trigger output (TRGO, TIM2-5 and TIM15 only) */ +#define GTIM_CR2_TI1S (1 << 7) /* Bit 7: TI1 Selection (not TIM16) */ +#define GTIM_CR2_OIS1 (1 << 8) /* Bit 8: COutput Idle state 1 (OC1 output) (TIM15-17 only) */ +#define GTIM_CR2_OIS1N (1 << 9) /* Bit 9: Output Idle state 1 (OC1N output) (TIM15-17 only) */ +#define GTIM_CR2_OIS2 (1 << 10) /* Bit 10: Output idle state 2 (OC2 output) (TIM15 only) */ + +/* Slave mode control register (TIM2-5) */ + +#define GTIM_SMCR_SMS_SHIFT (0) /* Bits 2-0: Slave Mode Selection */ +#define GTIM_SMCR_SMS_MASK (7 << GTIM_SMCR_SMS_SHIFT) +# define GTIM_SMCR_DISAB (0 << GTIM_SMCR_SMS_SHIFT) /* 000: Slave mode disabled */ +# define GTIM_SMCR_ENCMD1 (1 << GTIM_SMCR_SMS_SHIFT) /* 001: Encoder mode 1 */ +# define GTIM_SMCR_ENCMD2 (2 << GTIM_SMCR_SMS_SHIFT) /* 010: Encoder mode 2 */ +# define GTIM_SMCR_ENCMD3 (3 << GTIM_SMCR_SMS_SHIFT) /* 011: Encoder mode 3 */ +# define GTIM_SMCR_RESET (4 << GTIM_SMCR_SMS_SHIFT) /* 100: Reset Mode */ +# define GTIM_SMCR_GATED (5 << GTIM_SMCR_SMS_SHIFT) /* 101: Gated Mode */ +# define GTIM_SMCR_TRIGGER (6 << GTIM_SMCR_SMS_SHIFT) /* 110: Trigger Mode */ +# define GTIM_SMCR_EXTCLK1 (7 << GTIM_SMCR_SMS_SHIFT) /* 111: External Clock Mode 1 */ +#define GTIM_SMCR_TS_SHIFT (4) /* Bits 6-4: Trigger Selection */ +#define GTIM_SMCR_TS_MASK (7 << GTIM_SMCR_TS_SHIFT) +# define GTIM_SMCR_ITR0 (0 << GTIM_SMCR_TS_SHIFT) /* 000: Internal Trigger 0 (ITR0). TIM1 */ +# define GTIM_SMCR_ITR1 (1 << GTIM_SMCR_TS_SHIFT) /* 001: Internal Trigger 1 (ITR1). TIM2 */ +# define GTIM_SMCR_ITR2 (2 << GTIM_SMCR_TS_SHIFT) /* 010: Internal Trigger 2 (ITR2). TIM3 */ +# define GTIM_SMCR_ITR3 (3 << GTIM_SMCR_TS_SHIFT) /* 011: Internal Trigger 3 (ITR3). TIM4 */ +# define GTIM_SMCR_TI1FED (4 << GTIM_SMCR_TS_SHIFT) /* 100: TI1 Edge Detector (TI1F_ED) */ +# define GTIM_SMCR_TI1FP1 (5 << GTIM_SMCR_TS_SHIFT) /* 101: Filtered Timer Input 1 (TI1FP1) */ +# define GTIM_SMCR_TI2FP2 (6 << GTIM_SMCR_TS_SHIFT) /* 110: Filtered Timer Input 2 (TI2FP2) */ +# define GTIM_SMCR_ETRF (7 << GTIM_SMCR_TS_SHIFT) /* 111: External Trigger input (ETRF) */ +#define GTIM_SMCR_MSM (1 << 7) /* Bit 7: Master/Slave mode */ +#define GTIM_SMCR_ETF_SHIFT (8) /* Bits 11-8: External Trigger Filter (not TIM15) */ +#define GTIM_SMCR_ETF_MASK (0x0f << GTIM_SMCR_ETF_SHIFT) +# define GTIM_SMCR_NOFILT (0 << GTIM_SMCR_ETF_SHIFT) /* 0000: No filter, sampling is done at fDTS */ +# define GTIM_SMCR_FCKINT2 (1 << GTIM_SMCR_ETF_SHIFT) /* 0001: fSAMPLING=fCK_INT, N=2 */ +# define GTIM_SMCR_FCKINT4 (2 << GTIM_SMCR_ETF_SHIFT) /* 0010: fSAMPLING=fCK_INT, N=4 */ +# define GTIM_SMCR_FCKINT8 (3 << GTIM_SMCR_ETF_SHIFT) /* 0011: fSAMPLING=fCK_INT, N=8 */ +# define GTIM_SMCR_FDTSd26 (4 << GTIM_SMCR_ETF_SHIFT) /* 0100: fSAMPLING=fDTS/2, N=6 */ +# define GTIM_SMCR_FDTSd28 (5 << GTIM_SMCR_ETF_SHIFT) /* 0101: fSAMPLING=fDTS/2, N=8 */ +# define GTIM_SMCR_FDTSd36 (6 << GTIM_SMCR_ETF_SHIFT) /* 0110: fSAMPLING=fDTS/4, N=6 */ +# define GTIM_SMCR_FDTSd38 (7 << GTIM_SMCR_ETF_SHIFT) /* 0111: fSAMPLING=fDTS/4, N=8 */ +# define GTIM_SMCR_FDTSd86 (8 << GTIM_SMCR_ETF_SHIFT) /* 1000: fSAMPLING=fDTS/8, N=6 */ +# define GTIM_SMCR_FDTSd88 (9 << GTIM_SMCR_ETF_SHIFT) /* 1001: fSAMPLING=fDTS/8, N=8 */ +# define GTIM_SMCR_FDTSd165 (10 << GTIM_SMCR_ETF_SHIFT) /* 1010: fSAMPLING=fDTS/16, N=5 */ +# define GTIM_SMCR_FDTSd166 (11 << GTIM_SMCR_ETF_SHIFT) /* 1011: fSAMPLING=fDTS/16, N=6 */ +# define GTIM_SMCR_FDTSd168 (12 << GTIM_SMCR_ETF_SHIFT) /* 1100: fSAMPLING=fDTS/16, N=8 */ +# define GTIM_SMCR_FDTSd325 (13 << GTIM_SMCR_ETF_SHIFT) /* 1101: fSAMPLING=fDTS/32, N=5 */ +# define GTIM_SMCR_FDTSd326 (14 << GTIM_SMCR_ETF_SHIFT) /* 1110: fSAMPLING=fDTS/32, N=6 */ +# define GTIM_SMCR_FDTSd328 (15 << GTIM_SMCR_ETF_SHIFT) /* 1111: fSAMPLING=fDTS/32, N=8 */ +#define GTIM_SMCR_ETPS_SHIFT (12) /* Bits 13-12: External Trigger Prescaler (not TIM15) */ +#define GTIM_SMCR_ETPS_MASK (3 << GTIM_SMCR_ETPS_SHIFT) +# define GTIM_SMCR_PSCOFF (0 << GTIM_SMCR_ETPS_SHIFT) /* 00: Prescaler OFF */ +# define GTIM_SMCR_ETRPd2 (1 << GTIM_SMCR_ETPS_SHIFT) /* 01: ETRP frequency divided by 2 */ +# define GTIM_SMCR_ETRPd4 (2 << GTIM_SMCR_ETPS_SHIFT) /* 10: ETRP frequency divided by 4 */ +# define GTIM_SMCR_ETRPd8 (3 << GTIM_SMCR_ETPS_SHIFT) /* 11: ETRP frequency divided by 8 */ +#define GTIM_SMCR_ECE (1 << 14) /* Bit 14: External Clock enable */ +#define GTIM_SMCR_ETP (1 << 15) /* Bit 15: External Trigger Polarity */ +#define GTIM_SMCR_SMS (1 << 16) /* Bit 16: Slave mode selection - bit 3 */ + +/* DMA/Interrupt enable register (TIM2-5 and TIM9-14) */ + +#define GTIM_DIER_UIE (1 << 0) /* Bit 0: Update interrupt enable */ +#define GTIM_DIER_CC1IE (1 << 1) /* Bit 1: Capture/Compare 1 interrupt enable */ +#define GTIM_DIER_CC2IE (1 << 2) /* Bit 2: Capture/Compare 2 interrupt enable (TIM2-5,9,12,&15 only) */ +#define GTIM_DIER_CC3IE (1 << 3) /* Bit 3: Capture/Compare 3 interrupt enable (TIM2-5 only) */ +#define GTIM_DIER_CC4IE (1 << 4) /* Bit 4: Capture/Compare 4 interrupt enable (TIM2-5 only) */ +#define GTIM_DIER_COMIE (1 << 5) /* Bit 5: COM interrupt enable (TIM15-17 only) */ +#define GTIM_DIER_TIE (1 << 6) /* Bit 6: Trigger interrupt enable (TIM2-5,9,&12 only) */ +#define GTIM_DIER_BIE (1 << 7) /* Bit 7: Break interrupt enable (TIM15-17 only) */ +#define GTIM_DIER_UDE (1 << 8) /* Bit 8: Update DMA request enable (TIM2-5&15-17 only) */ +#define GTIM_DIER_CC1DE (1 << 9) /* Bit 9: Capture/Compare 1 DMA request enable (TIM2-5&15-17 only) */ +#define GTIM_DIER_CC2DE (1 << 10) /* Bit 10: Capture/Compare 2 DMA request enable (TIM2-5&15 only) */ +#define GTIM_DIER_CC3DE (1 << 11) /* Bit 11: Capture/Compare 3 DMA request enable (TIM2-5 only) */ +#define GTIM_DIER_CC4DE (1 << 12) /* Bit 12: Capture/Compare 4 DMA request enable (TIM2-5 only) */ +#define GTIM_DIER_COMDE (1 << 13) /* Bit 13: COM DMA request enable (TIM15-17 only) */ +#define GTIM_DIER_TDE (1 << 14) /* Bit 14: Trigger DMA request enable (TIM2-5&15-17 only) */ + +/* Status register */ + +#define GTIM_SR_UIF (1 << 0) /* Bit 0: Update interrupt flag */ +#define GTIM_SR_CC1IF (1 << 1) /* Bit 1: Capture/compare 1 interrupt flag */ +#define GTIM_SR_CC2IF (1 << 2) /* Bit 2: Capture/Compare 2 interrupt flag (TIM2-5,9,12,&15 only) */ +#define GTIM_SR_CC3IF (1 << 3) /* Bit 3: Capture/Compare 3 interrupt flag (TIM2-5 only) */ +#define GTIM_SR_CC4IF (1 << 4) /* Bit 4: Capture/Compare 4 interrupt flag (TIM2-5 only) */ +#define GTIM_SR_COMIF (1 << 5) /* Bit 5: COM interrupt flag (TIM15-17 only) */ +#define GTIM_SR_TIF (1 << 6) /* Bit 6: Trigger interrupt Flag (TIM2-5,9,12&15-17 only) */ +#define GTIM_SR_BIF (1 << 7) /* Bit 7: Break interrupt flag (TIM15-17 only) */ +#define GTIM_SR_CC1OF (1 << 9) /* Bit 9: Capture/Compare 1 Overcapture flag */ +#define GTIM_SR_CC2OF (1 << 10) /* Bit 10: Capture/Compare 2 Overcapture flag (TIM2-5,9,12&15 only) */ +#define GTIM_SR_CC3OF (1 << 11) /* Bit 11: Capture/Compare 3 Overcapture flag (TIM2-5 only) */ +#define GTIM_SR_CC4OF (1 << 12) /* Bit 12: Capture/Compare 4 Overcapture flag (TIM2-5 only) */ + +/* Event generation register (TIM2-5 and TIM9-14) */ + +#define GTIM_EGR_UG (1 << 0) /* Bit 0: Update generation */ +#define GTIM_EGR_CC1G (1 << 1) /* Bit 1: Capture/compare 1 generation */ +#define GTIM_EGR_CC2G (1 << 2) /* Bit 2: Capture/compare 2 generation (TIM2-5,9,12,&15 only) */ +#define GTIM_EGR_CC3G (1 << 3) /* Bit 3: Capture/compare 3 generation (TIM2-5 only) */ +#define GTIM_EGR_CC4G (1 << 4) /* Bit 4: Capture/compare 4 generation (TIM2-5 only) */ +#define GTIM_EGR_COMIG (1 << 5) /* Bit 5: Capture/Compare control update generation (TIM15-17 only) */ +#define GTIM_EGR_TG (1 << 6) /* Bit 6: Trigger generation (TIM2-5,9,12&16-17 only) */ +#define GTIM_EGR_BG (1 << 7) /* Bit 7: Break generation (TIM15-17 only) */ + +/* Capture/compare mode register 1 - Output compare mode (TIM2-5 and TIM9-14) */ + +#define GTIM_CCMR1_CC1S_SHIFT (0) /* Bits 1-0: Capture/Compare 1 Selection */ +#define GTIM_CCMR1_CC1S_MASK (3 << GTIM_CCMR1_CC1S_SHIFT) + /* (See common CCMR Capture/Compare Selection definitions below) */ +#define GTIM_CCMR1_OC1FE (1 << 2) /* Bit 2: Output Compare 1 Fast enable */ +#define GTIM_CCMR1_OC1PE (1 << 3) /* Bit 3: Output Compare 1 Preload enable */ +#define GTIM_CCMR1_OC1M_SHIFT (4) /* Bits 6-4: Output Compare 1 Mode */ +#define GTIM_CCMR1_OC1M_MASK (7 << GTIM_CCMR1_OC1M_SHIFT) + /* (See common CCMR Output Compare Mode definitions below) */ +#define GTIM_CCMR1_OC1CE (1 << 7) /* Bit 7: Output Compare 1Clear Enable */ +#define GTIM_CCMR1_CC2S_SHIFT (8) /* Bits 9-8: Capture/Compare 2 Selection */ +#define GTIM_CCMR1_CC2S_MASK (3 << GTIM_CCMR1_CC2S_SHIFT) + /* (See common CCMR Capture/Compare Selection definitions below) */ +#define GTIM_CCMR1_OC2FE (1 << 10) /* Bit 10: Output Compare 2 Fast enable */ +#define GTIM_CCMR1_OC2PE (1 << 11) /* Bit 11: Output Compare 2 Preload enable */ +#define GTIM_CCMR1_OC2M_SHIFT (12) /* Bits 14-12: Output Compare 2 Mode */ +#define GTIM_CCMR1_OC2M_MASK (7 << GTIM_CCMR1_OC2M_SHIFT) + /* (See common CCMR Output Compare Mode definitions below) */ +#define GTIM_CCMR1_OC2CE (1 << 15) /* Bit 15: Output Compare 2 Clear Enable */ +#define GTIM_CCMR1_OC1M (1 << 16) /* Bit 16: Output Compare 1 mode - bit 3 */ +#define GTIM_CCMR1_OC2M (1 << 24) /* Bit 24: Output Compare 2 mode - bit 3 */ + +/* Common CCMR (unshifted) Capture/Compare Selection bit-field definitions */ + +#define GTIM_CCMR_CCS_CCOUT (0) /* 00: CCx channel output */ +#define GTIM_CCMR_CCS_CCIN1 (1) /* 01: CCx channel input, ICx is TIx */ +#define GTIM_CCMR_CCS_CCIN2 (2) /* 10: CCx channel input, ICx is TIy */ +#define GTIM_CCMR_CCS_CCINTRC (3) /* 11: CCx channel input, ICx is TRC */ + +/* Common CCMR (unshifted) Compare Mode bit field definitions */ + +#define GTIM_CCMR_MODE_FRZN (0) /* 000: Frozen */ +#define GTIM_CCMR_MODE_CHACT (1) /* 001: Channel x active on match */ +#define GTIM_CCMR_MODE_CHINACT (2) /* 010: Channel x inactive on match */ +#define GTIM_CCMR_MODE_OCREFTOG (3) /* 011: OCxREF toggle ATIM_CNT=ATIM_CCRx */ +#define GTIM_CCMR_MODE_OCREFLO (4) /* 100: OCxREF forced low */ +#define GTIM_CCMR_MODE_OCREFHI (5) /* 101: OCxREF forced high */ +#define GTIM_CCMR_MODE_PWM1 (6) /* 110: PWM mode 1 */ +#define GTIM_CCMR_MODE_PWM2 (7) /* 111: PWM mode 2 */ + +/* Capture/compare mode register 1 - Input capture mode (TIM2-5 and TIM9-14) */ + + /* Bits 1-0 (Same as Output Compare Mode) */ +#define GTIM_CCMR1_IC1PSC_SHIFT (2) /* Bits 3-2: Input Capture 1 Prescaler */ +#define GTIM_CCMR1_IC1PSC_MASK (3 << GTIM_CCMR1_IC1PSC_SHIFT) + /* (See common CCMR Input Capture Prescaler definitions below) */ +#define GTIM_CCMR1_IC1F_SHIFT (4) /* Bits 7-4: Input Capture 1 Filter */ +#define GTIM_CCMR1_IC1F_MASK (0x0f << GTIM_CCMR1_IC1F_SHIFT) + /* (See common CCMR Input Capture Filter definitions below) */ + /* Bits 9-8: (Same as Output Compare Mode) */ +#define GTIM_CCMR1_IC2PSC_SHIFT (10) /* Bits 11-10: Input Capture 2 Prescaler */ +#define GTIM_CCMR1_IC2PSC_MASK (3 << GTIM_CCMR1_IC2PSC_SHIFT) + /* (See common CCMR Input Capture Prescaler definitions below) */ +#define GTIM_CCMR1_IC2F_SHIFT (12) /* Bits 15-12: Input Capture 2 Filter */ +#define GTIM_CCMR1_IC2F_MASK (0x0f << GTIM_CCMR1_IC2F_SHIFT) + /* (See common CCMR Input Capture Filter definitions below) */ + +/* Common CCMR (unshifted) Input Capture Prescaler bit-field definitions */ + +#define GTIM_CCMR_ICPSC_NOPSC (0) /* 00: no prescaler, capture each edge */ +#define GTIM_CCMR_ICPSC_EVENTS2 (1) /* 01: capture once every 2 events */ +#define GTIM_CCMR_ICPSC_EVENTS4 (2) /* 10: capture once every 4 events */ +#define GTIM_CCMR_ICPSC_EVENTS8 (3) /* 11: capture once every 8 events */ + +/* Common CCMR (unshifted) Input Capture Filter bit-field definitions */ + +#define GTIM_CCMR_ICF_NOFILT (0) /* 0000: No filter, sampling at fDTS */ +#define GTIM_CCMR_ICF_FCKINT2 (1) /* 0001: fSAMPLING=fCK_INT, N=2 */ +#define GTIM_CCMR_ICF_FCKINT4 (2) /* 0010: fSAMPLING=fCK_INT, N=4 */ +#define GTIM_CCMR_ICF_FCKINT8 (3) /* 0011: fSAMPLING=fCK_INT, N=8 */ +#define GTIM_CCMR_ICF_FDTSd26 (4) /* 0100: fSAMPLING=fDTS/2, N=6 */ +#define GTIM_CCMR_ICF_FDTSd28 (5) /* 0101: fSAMPLING=fDTS/2, N=8 */ +#define GTIM_CCMR_ICF_FDTSd46 (6) /* 0110: fSAMPLING=fDTS/4, N=6 */ +#define GTIM_CCMR_ICF_FDTSd48 (7) /* 0111: fSAMPLING=fDTS/4, N=8 */ +#define GTIM_CCMR_ICF_FDTSd86 (8) /* 1000: fSAMPLING=fDTS/8, N=6 */ +#define GTIM_CCMR_ICF_FDTSd88 (9) /* 1001: fSAMPLING=fDTS/8, N=8 */ +#define GTIM_CCMR_ICF_FDTSd165 (10) /* 1010: fSAMPLING=fDTS/16, N=5 */ +#define GTIM_CCMR_ICF_FDTSd166 (11) /* 1011: fSAMPLING=fDTS/16, N=6 */ +#define GTIM_CCMR_ICF_FDTSd168 (12) /* 1100: fSAMPLING=fDTS/16, N=8 */ +#define GTIM_CCMR_ICF_FDTSd325 (13) /* 1101: fSAMPLING=fDTS/32, N=5 */ +#define GTIM_CCMR_ICF_FDTSd326 (14) /* 1110: fSAMPLING=fDTS/32, N=6 */ +#define GTIM_CCMR_ICF_FDTSd328 (15) /* 1111: fSAMPLING=fDTS/32, N=8 */ + +/* Capture/compare mode register 2 - Output Compare mode (TIM2-5 only) */ + +#define GTIM_CCMR2_CC3S_SHIFT (0) /* Bits 1-0: Capture/Compare 3 Selection */ +#define GTIM_CCMR2_CC3S_MASK (3 << GTIM_CCMR2_CC3S_SHIFT) + /* (See common CCMR Capture/Compare Selection definitions above) */ +#define GTIM_CCMR2_OC3FE (1 << 2) /* Bit 2: Output Compare 3 Fast enable */ +#define GTIM_CCMR2_OC3PE (1 << 3) /* Bit 3: Output Compare 3 Preload enable */ +#define GTIM_CCMR2_OC3M_SHIFT (4) /* Bits 6-4: Output Compare 3 Mode */ +#define GTIM_CCMR2_OC3M_MASK (7 << GTIM_CCMR2_OC3M_SHIFT) + /* (See common CCMR Output Compare Mode definitions above) */ +#define GTIM_CCMR2_OC3CE (1 << 7) /* Bit 7: Output Compare 3 Clear Enable */ +#define GTIM_CCMR2_CC4S_SHIFT (8) /* Bits 9-8: Capture/Compare 4 Selection */ +#define GTIM_CCMR2_CC4S_MASK (3 << GTIM_CCMR2_CC4S_SHIFT) + /* (See common CCMR Capture/Compare Selection definitions above) */ +#define GTIM_CCMR2_OC4FE (1 << 10) /* Bit 10: Output Compare 4 Fast enable */ +#define GTIM_CCMR2_OC4PE (1 << 11) /* Bit 11: Output Compare 4 Preload enable */ +#define GTIM_CCMR2_OC4M_SHIFT (12) /* Bits 14-12: Output Compare 4 Mode */ +#define GTIM_CCMR2_OC4M_MASK (7 << GTIM_CCMR2_OC4M_SHIFT) + /* (See common CCMR Output Compare Mode definitions above) */ +#define GTIM_CCMR2_OC4CE (1 << 15) /* Bit 15: Output Compare 4 Clear Enable */ + +/* Capture/compare mode register 2 - Input capture mode (TIM2-5 only) */ + + /* Bits 1-0 (Same as Output Compare Mode) */ +#define GTIM_CCMR2_IC3PSC_SHIFT (2) /* Bits 3-2: Input Capture 3 Prescaler */ +#define GTIM_CCMR2_IC3PSC_MASK (3 << GTIM_CCMR2_IC3PSC_SHIFT) + /* (See common CCMR Input Capture Prescaler definitions below) */ +#define GTIM_CCMR2_IC3F_SHIFT (4) /* Bits 7-4: Input Capture 3 Filter */ +#define GTIM_CCMR2_IC3F_MASK (0x0f << GTIM_CCMR2_IC3F_SHIFT) + /* (See common CCMR Input Capture Filter definitions below) */ + /* Bits 9-8: (Same as Output Compare Mode) */ +#define GTIM_CCMR2_IC4PSC_SHIFT (10) /* Bits 11-10: Input Capture 4 Prescaler */ +#define GTIM_CCMR2_IC4PSC_MASK (3 << GTIM_CCMR2_IC4PSC_SHIFT) + /* (See common CCMR Input Capture Prescaler definitions below) */ +#define GTIM_CCMR2_IC4F_SHIFT (12) /* Bits 15-12: Input Capture 4 Filter */ +#define GTIM_CCMR2_IC4F_MASK (0x0f << GTIM_CCMR2_IC4F_SHIFT) + /* (See common CCMR Input Capture Filter definitions below) */ + +/* Capture/compare enable register (TIM1 and TIM8, TIM2-5 and TIM9-14) */ + +#define GTIM_CCER_CC1E (1 << 0) /* Bit 0: Capture/Compare 1 output enable */ +#define GTIM_CCER_CC1P (1 << 1) /* Bit 1: Capture/Compare 1 output polarity */ +#define GTIM_CCER_CC1NE (1 << 2) /* Bit 2: Capture/Compare 1 complementary output enable (TIM1 and TIM8 only) */ +#define GTIM_CCER_CC1NP (1 << 3) /* Bit 3: Capture/Compare 1 output Polarity (F2,F3,F4 and TIM15-17) */ +#define GTIM_CCER_CC2E (1 << 4) /* Bit 4: Capture/Compare 2 output enable (TIM2-5,9&12 only) */ +#define GTIM_CCER_CC2P (1 << 5) /* Bit 5: Capture/Compare 2 output polarity (TIM2-5,9&12 only) */ +#define GTIM_CCER_CC2NE (1 << 6) /* Bit 6: Capture/Compare 2 complementary output enable (TIM1 and TIM8 only) */ +#define GTIM_CCER_CC2NP (1 << 7) /* Bit 7: Capture/Compare 2 output Polarity (F2,F3,F4 and TIM2-5,9,12&15 only) */ +#define GTIM_CCER_CC3E (1 << 8) /* Bit 8: Capture/Compare 3 output enable (TIM2-5 only) */ +#define GTIM_CCER_CC3P (1 << 9) /* Bit 9: Capture/Compare 3 output Polarity (TIM2-5 only) */ +#define GTIM_CCER_CC3NE (1 << 10) /* Bit 10: Capture/Compare 3 complementary output enable (TIM1 and TIM8 only) */ +#define GTIM_CCER_CC3NP (1 << 11) /* Bit 11: Capture/Compare 3 output Polarity (F2,F4 and TIM2-5 only) */ +#define GTIM_CCER_CC4E (1 << 12) /* Bit 12: Capture/Compare 4 output enable (TIM2-5 only) */ +#define GTIM_CCER_CC4P (1 << 13) /* Bit 13: Capture/Compare 4 output Polarity (TIM2-5 only) */ +#define GTIM_CCER_CC4NP (1 << 15) /* Bit 15: Capture/Compare 4 output Polarity */ + +/* 16-bit counter register */ + +#define GTIM_CNT_SHIFT (0) /* Bits 0-15: Timer counter value */ +#define GTIM_CNT_MASK (0xffff << ATIM_CNT_SHIFT) + +/* DMA control register */ + +#define GTIM_DCR_DBA_SHIFT (0) /* Bits 4-0: DMA Base Address */ +#define GTIM_DCR_DBA_MASK (0x1f << GTIM_DCR_DBA_SHIFT) +#define GTIM_DCR_DBL_SHIFT (8) /* Bits 12-8: DMA Burst Length */ +#define GTIM_DCR_DBL_MASK (0x1f << GTIM_DCR_DBL_SHIFT) + +/* Timer 2/5 option register */ + +#define TIM2_OR_ITR1_RMP_SHIFT (10) /* Bits 10-11: Internal trigger 1 remap */ +#define TIM2_OR_ITR1_RMP_MASK (3 << TIM2_OR_ITR1_RMP_SHIFT) +# define TIM2_OR_ITR1_TIM8_TRGOUT (0 << TIM2_OR_ITR1_RMP_SHIFT) /* 00: TIM2_ITR1 input connected to TIM8_TRGOUT */ +# define TIM2_OR_ITR1_PTP (1 << TIM2_OR_ITR1_RMP_SHIFT) /* 01: TIM2_ITR1 input connected to PTP trigger output */ +# define TIM2_OR_ITR1_OTGFSSOF (2 << TIM2_OR_ITR1_RMP_SHIFT) /* 10: TIM2_ITR1 input connected to OTG FS SOF */ +# define TIM2_OR_ITR1_OTGHSSOF (3 << TIM2_OR_ITR1_RMP_SHIFT) /* 11: TIM2_ITR1 input connected to OTG HS SOF */ + +#define TIM5_OR_TI4_RMP_SHIFT (6) /* Bits 6-7: Internal trigger 4 remap */ +#define TIM5_OR_TI4_RMP_MASK (3 << TIM5_OR_TI4_RMP_SHIFT) +# define TIM5_OR_TI4_GPIO (0 << TIM5_OR_TI4_RMP_SHIFT) /* 00: TIM5_CH4 input connected to GPIO */ +# define TIM5_OR_TI4_LSI (1 << TIM5_OR_TI4_RMP_SHIFT) /* 01: TIM5_CH4 input connected to LSI internal clock */ +# define TIM5_OR_TI4_LSE (2 << TIM5_OR_TI4_RMP_SHIFT) /* 10: TIM5_CH4 input connected to LSE internal clock */ +# define TIM5_OR_TI4_RTC (3 << TIM5_OR_TI4_RMP_SHIFT) /* 11: TIM5_CH4 input connected to RTC output event */ + +#define TIM11_OR_TI1_RMP_SHIFT (6) /* Bits 6-7: Internal trigger 4 remap */ +#define TIM11_OR_TI1_RMP_MASK (3 << TIM11_OR_TI1_RMP_SHIFT) +# define TIM11_OR_TI1_GPIO (0 << TIM11_OR_TI1_RMP_SHIFT) /* 00-11: TIM11_CH1 input connected to GPIO */ +# define TIM11_OR_TI1_HSERTC (3 << TIM11_OR_TI1_RMP_SHIFT) /* 11: TIM11_CH1 input connected to HSE_RTC clock */ + + +/* Control register 1 */ + +#define BTIM_CR1_CEN (1 << 0) /* Bit 0: Counter enable */ +#define BTIM_CR1_UDIS (1 << 1) /* Bit 1: Update Disable */ +#define BTIM_CR1_URS (1 << 2) /* Bit 2: Update Request Source */ +#define BTIM_CR1_OPM (1 << 3) /* Bit 3: One Pulse Mode */ +#define BTIM_CR1_ARPE (1 << 7) /* Bit 7: Auto-Reload Preload enable */ + +/* Control register 2 */ + +#define BTIM_CR2_MMS_SHIFT (4) /* Bits 6-4: Master Mode Selection */ +#define BTIM_CR2_MMS_MASK (7 << BTIM_CR2_MMS_SHIFT) +# define BTIM_CR2_RESET (0 << BTIM_CR2_MMS_SHIFT) /* 000: Reset */ +# define BTIM_CR2_ENAB (1 << BTIM_CR2_MMS_SHIFT) /* 001: Enable */ +# define BTIM_CR2_UPDT (2 << BTIM_CR2_MMS_SHIFT) /* 010: Update */ + +/* DMA/Interrupt enable register */ + +#define BTIM_DIER_UIE (1 << 0) /* Bit 0: Update interrupt enable */ +#define BTIM_DIER_UDE (1 << 8) /* Bit 8: Update DMA request enable */ + +/* Status register */ + +#define BTIM_SR_UIF (1 << 0) /* Bit 0: Update interrupt flag */ + +/* Event generation register */ + +#define BTIM_EGR_UG (1 << 0) /* Bit 0: Update generation */ + +#endif /* __ARCH_ARM_SRC_STM32F7_CHIP_STM32F74XX75XX_TIM_H */ diff --git a/arch/arm/src/stm32f7/chip/stm32f76xx77xx_tim.h b/arch/arm/src/stm32f7/chip/stm32f76xx77xx_tim.h new file mode 100644 index 0000000000..bb6a657aa8 --- /dev/null +++ b/arch/arm/src/stm32f7/chip/stm32f76xx77xx_tim.h @@ -0,0 +1,1147 @@ +/**************************************************************************************************** + * arch/arm/src/stm32f7/chip/stm32f76xx77xx_tim.h + * + * Copyright (C) 2016 Gregory Nutt. All rights reserved. + * Authors: Gregory Nutt + * David Sidrane + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************************************/ + +#ifndef __ARCH_ARM_SRC_STM32F7_CHIP_STM32F76XX77XX_TIM_H +#define __ARCH_ARM_SRC_STM32F7_CHIP_STM32F76XX77XX_TIM_H + +/**************************************************************************************************** + * Pre-processor Definitions + ****************************************************************************************************/ + +/* Register Offsets *********************************************************************************/ + +/* Basic Timers - TIM6 and TIM7 */ + +#define STM32_BTIM_CR1_OFFSET 0x0000 /* Control register 1 (16-bit) */ +#define STM32_BTIM_CR2_OFFSET 0x0004 /* Control register 2 (16-bit) */ +#define STM32_BTIM_DIER_OFFSET 0x000c /* DMA/Interrupt enable register (16-bit) */ +#define STM32_BTIM_SR_OFFSET 0x0010 /* Status register (16-bit) */ +#define STM32_BTIM_EGR_OFFSET 0x0014 /* Event generation register (16-bit) */ +#define STM32_BTIM_CNT_OFFSET 0x0024 /* Counter (16-bit) */ +#define STM32_BTIM_PSC_OFFSET 0x0028 /* Prescaler (16-bit) */ +#define STM32_BTIM_ARR_OFFSET 0x002c /* Auto-reload register (16-bit) */ + +/* 16-/32-bit General Timers with DMA: TIM2, TM3, TIM4, and TIM5 + * 16-bit General Timers without DMA: TIM9, TIM10, TIM11, TIM12, TIM13, and TIM14 + * timers are 16-bit except for TIM2 and 5 are 32-bit + * timers TIM9 and 12 are different then TIM10, TIM11, TIM13, and TIM14 + */ + +#define STM32_GTIM_CR1_OFFSET 0x0000 /* Control register 1 (16-bit) */ +#define STM32_GTIM_CR2_OFFSET 0x0004 /* Control register 2 (16-bit, TIM2, 5 only) */ +#define STM32_GTIM_SMCR_OFFSET 0x0008 /* Slave mode control register (32-bit, TIM2, 5, 9, 12 only) */ +#define STM32_GTIM_DIER_OFFSET 0x000c /* DMA/Interrupt enable register (16-bit) */ +#define STM32_GTIM_SR_OFFSET 0x0010 /* Status register (16-bit) */ +#define STM32_GTIM_EGR_OFFSET 0x0014 /* Event generation register (16-bit) */ +#define STM32_GTIM_CCMR1_OFFSET 0x0018 /* Capture/compare mode register 1 (32-bit) */ +#define STM32_GTIM_CCMR2_OFFSET 0x001c /* Capture/compare mode register 2 (32-bit on TIM2,5 only) */ +#define STM32_GTIM_CCER_OFFSET 0x0020 /* Capture/compare enable register (16-bit) */ +#define STM32_GTIM_CNT_OFFSET 0x0024 /* Counter (16 bit and 32-bit on TIM2, 5 only) */ +#define STM32_GTIM_PSC_OFFSET 0x0028 /* Prescaler (16-bit) */ +#define STM32_GTIM_ARR_OFFSET 0x002c /* Auto-reload register (16 bit and 32-bit on TIM2, 5 only) */ +#define STM32_GTIM_CCR1_OFFSET 0x0034 /* Capture/compare register 1 (16-bit on all TIMx and 32-bit on TIM2,5 only) */ +#define STM32_GTIM_CCR2_OFFSET 0x0038 /* Capture/compare register 2 (16-bit TIM 3-4, 9, 12 and 32-bit on TIM2,5 only) */ +#define STM32_GTIM_CCR3_OFFSET 0x003c /* Capture/compare register 3 (16-bit TIM 3-4 and 32-bit on TIM2,5 only) */ +#define STM32_GTIM_CCR4_OFFSET 0x0040 /* Capture/compare register 4 (16-bit TIM 3-4 and 32-bit on TIM2,5 only) */ +#define STM32_GTIM_DCR_OFFSET 0x0048 /* DMA control register (16-bit, TIM2-5 only) */ +#define STM32_GTIM_DMAR_OFFSET 0x004c /* DMA address for burst mode (16-bit, TIM2-5 only) */ +#define STM32_GTIM_OR_OFFSET 0x0050 /* Timer 2/5/11 option register */ + +/* Advanced Timers - TIM1 and TIM8 */ + +#define STM32_ATIM_CR1_OFFSET 0x0000 /* Control register 1 (16-bit) */ +#define STM32_ATIM_CR2_OFFSET 0x0004 /* Control register 2 (32-bit*) */ +#define STM32_ATIM_SMCR_OFFSET 0x0008 /* Slave mode control register (32 -bit) */ +#define STM32_ATIM_DIER_OFFSET 0x000c /* DMA/Interrupt enable register (16-bit) */ +#define STM32_ATIM_SR_OFFSET 0x0010 /* Status register (32-bit*) */ +#define STM32_ATIM_EGR_OFFSET 0x0014 /* Event generation register (16-bit) */ +#define STM32_ATIM_CCMR1_OFFSET 0x0018 /* Capture/compare mode register 1 (32-bit*) */ +#define STM32_ATIM_CCMR2_OFFSET 0x001c /* Capture/compare mode register 2 (32-bit*) */ +#define STM32_ATIM_CCER_OFFSET 0x0020 /* Capture/compare enable register (32-bit*) */ +#define STM32_ATIM_CNT_OFFSET 0x0024 /* Counter (32-bit cnt in lower 16 bit ) */ +#define STM32_ATIM_PSC_OFFSET 0x0028 /* Prescaler (16-bit) */ +#define STM32_ATIM_ARR_OFFSET 0x002c /* Auto-reload register (16-bit) */ +#define STM32_ATIM_RCR_OFFSET 0x0030 /* Repetition counter register (16-bit) */ +#define STM32_ATIM_CCR1_OFFSET 0x0034 /* Capture/compare register 1 (16-bit) */ +#define STM32_ATIM_CCR2_OFFSET 0x0038 /* Capture/compare register 2 (16-bit) */ +#define STM32_ATIM_CCR3_OFFSET 0x003c /* Capture/compare register 3 (16-bit) */ +#define STM32_ATIM_CCR4_OFFSET 0x0040 /* Capture/compare register 4 (16-bit) */ +#define STM32_ATIM_BDTR_OFFSET 0x0044 /* Break and dead-time register (32-bit*) */ +#define STM32_ATIM_DCR_OFFSET 0x0048 /* DMA control register (16-bit) */ +#define STM32_ATIM_DMAR_OFFSET 0x004c /* DMA address for burst mode (16-bit) */ +#define STM32_ATIM_CCMR3_OFFSET 0x0054 /* Capture/compare mode register 3 (32-bit) */ +#define STM32_ATIM_CCR5_OFFSET 0x0058 /* Capture/compare register 5 (32-bit) */ +#define STM32_ATIM_CCR6_OFFSET 0x005c /* Capture/compare register 6 (16-bit) */ +#define STM32_ATIM_AF1_OFFSET 0x0060 /* Alternate function option register 1 (16-bit) */ +#define STM32_ATIM_AF2_OFFSET 0x0064 /* Alternate function option register 2 (16-bit) */ + +/* Register Addresses *******************************************************************************/ + +/* Advanced Timers - TIM1 and TIM8 */ + +#if STM32F7_NATIM > 0 +# define STM32_TIM1_CR1 (STM32_TIM1_BASE+STM32_ATIM_CR1_OFFSET) +# define STM32_TIM1_CR2 (STM32_TIM1_BASE+STM32_ATIM_CR2_OFFSET) +# define STM32_TIM1_SMCR (STM32_TIM1_BASE+STM32_ATIM_SMCR_OFFSET) +# define STM32_TIM1_DIER (STM32_TIM1_BASE+STM32_ATIM_DIER_OFFSET) +# define STM32_TIM1_SR (STM32_TIM1_BASE+STM32_ATIM_SR_OFFSET) +# define STM32_TIM1_EGR (STM32_TIM1_BASE+STM32_ATIM_EGR_OFFSET) +# define STM32_TIM1_CCMR1 (STM32_TIM1_BASE+STM32_ATIM_CCMR1_OFFSET) +# define STM32_TIM1_CCMR2 (STM32_TIM1_BASE+STM32_ATIM_CCMR2_OFFSET) +# define STM32_TIM1_CCER (STM32_TIM1_BASE+STM32_ATIM_CCER_OFFSET) +# define STM32_TIM1_CNT (STM32_TIM1_BASE+STM32_ATIM_CNT_OFFSET) +# define STM32_TIM1_PSC (STM32_TIM1_BASE+STM32_ATIM_PSC_OFFSET) +# define STM32_TIM1_ARR (STM32_TIM1_BASE+STM32_ATIM_ARR_OFFSET) +# define STM32_TIM1_RCR (STM32_TIM1_BASE+STM32_ATIM_RCR_OFFSET) +# define STM32_TIM1_CCR1 (STM32_TIM1_BASE+STM32_ATIM_CCR1_OFFSET) +# define STM32_TIM1_CCR2 (STM32_TIM1_BASE+STM32_ATIM_CCR2_OFFSET) +# define STM32_TIM1_CCR3 (STM32_TIM1_BASE+STM32_ATIM_CCR3_OFFSET) +# define STM32_TIM1_CCR4 (STM32_TIM1_BASE+STM32_ATIM_CCR4_OFFSET) +# define STM32_TIM1_BDTR (STM32_TIM1_BASE+STM32_ATIM_BDTR_OFFSET) +# define STM32_TIM1_DCR (STM32_TIM1_BASE+STM32_ATIM_DCR_OFFSET) +# define STM32_TIM1_DMAR (STM32_TIM1_BASE+STM32_ATIM_DMAR_OFFSET) +# define STM32_TIM1_CCMR3 (STM32_TIM1_BASE+STM32_ATIM_CCMR3_OFFSET) +# define STM32_TIM1_CCR5 (STM32_TIM1_BASE+STM32_ATIM_CCR5_OFFSET) +# define STM32_TIM1_CCR6 (STM32_TIM1_BASE+STM32_ATIM_CCR6_OFFSET) +# define STM32_TIM1_AF1 (STM32_TIM1_BASE+STM32_ATIM_AF1_OFFSET) +# define STM32_TIM1_AF2 (STM32_TIM1_BASE+STM32_ATIM_AF2_OFFSET) +#endif + +#if STM32F7_NATIM > 1 +# define STM32_TIM8_CR1 (STM32_TIM8_BASE+STM32_ATIM_CR1_OFFSET) +# define STM32_TIM8_CR2 (STM32_TIM8_BASE+STM32_ATIM_CR2_OFFSET) +# define STM32_TIM8_SMCR (STM32_TIM8_BASE+STM32_ATIM_SMCR_OFFSET) +# define STM32_TIM8_DIER (STM32_TIM8_BASE+STM32_ATIM_DIER_OFFSET) +# define STM32_TIM8_SR (STM32_TIM8_BASE+STM32_ATIM_SR_OFFSET) +# define STM32_TIM8_EGR (STM32_TIM8_BASE+STM32_ATIM_EGR_OFFSET) +# define STM32_TIM8_CCMR1 (STM32_TIM8_BASE+STM32_ATIM_CCMR1_OFFSET) +# define STM32_TIM8_CCMR2 (STM32_TIM8_BASE+STM32_ATIM_CCMR2_OFFSET) +# define STM32_TIM8_CCER (STM32_TIM8_BASE+STM32_ATIM_CCER_OFFSET) +# define STM32_TIM8_CNT (STM32_TIM8_BASE+STM32_ATIM_CNT_OFFSET) +# define STM32_TIM8_PSC (STM32_TIM8_BASE+STM32_ATIM_PSC_OFFSET) +# define STM32_TIM8_ARR (STM32_TIM8_BASE+STM32_ATIM_ARR_OFFSET) +# define STM32_TIM8_RCR (STM32_TIM8_BASE+STM32_ATIM_RCR_OFFSET) +# define STM32_TIM8_CCR1 (STM32_TIM8_BASE+STM32_ATIM_CCR1_OFFSET) +# define STM32_TIM8_CCR2 (STM32_TIM8_BASE+STM32_ATIM_CCR2_OFFSET) +# define STM32_TIM8_CCR3 (STM32_TIM8_BASE+STM32_ATIM_CCR3_OFFSET) +# define STM32_TIM8_CCR4 (STM32_TIM8_BASE+STM32_ATIM_CCR4_OFFSET) +# define STM32_TIM8_BDTR (STM32_TIM8_BASE+STM32_ATIM_BDTR_OFFSET) +# define STM32_TIM8_DCR (STM32_TIM8_BASE+STM32_ATIM_DCR_OFFSET) +# define STM32_TIM8_DMAR (STM32_TIM8_BASE+STM32_ATIM_DMAR_OFFSET) +# define STM32_TIM8_CCMR3 (STM32_TIM8_BASE+STM32_ATIM_CCMR3_OFFSET) +# define STM32_TIM8_CCR5 (STM32_TIM8_BASE+STM32_ATIM_CCR5_OFFSET) +# define STM32_TIM8_CCR6 (STM32_TIM8_BASE+STM32_ATIM_CCR6_OFFSET) +# define STM32_TIM8_AF1 (STM32_TIM8_BASE+STM32_ATIM_AF1_OFFSET) +# define STM32_TIM8_AF2 (STM32_TIM8_BASE+STM32_ATIM_AF2_OFFSET) +#endif + +/* 16-/32-bit General Timers - TIM2, TIM3, TIM4, and TIM5 with DMA. + * All timers are 16-bit except for TIM2 and 5 are 32-bit + */ + +#if (STM32F7_NGTIM16+STM32F7_NGTIM32) > 0 +# define STM32_TIM2_CR1 (STM32_TIM2_BASE+STM32_GTIM_CR1_OFFSET) +# define STM32_TIM2_CR2 (STM32_TIM2_BASE+STM32_GTIM_CR2_OFFSET) +# define STM32_TIM2_SMCR (STM32_TIM2_BASE+STM32_GTIM_SMCR_OFFSET) +# define STM32_TIM2_DIER (STM32_TIM2_BASE+STM32_GTIM_DIER_OFFSET) +# define STM32_TIM2_SR (STM32_TIM2_BASE+STM32_GTIM_SR_OFFSET) +# define STM32_TIM2_EGR (STM32_TIM2_BASE+STM32_GTIM_EGR_OFFSET) +# define STM32_TIM2_CCMR1 (STM32_TIM2_BASE+STM32_GTIM_CCMR1_OFFSET) +# define STM32_TIM2_CCMR2 (STM32_TIM2_BASE+STM32_GTIM_CCMR2_OFFSET) +# define STM32_TIM2_CCER (STM32_TIM2_BASE+STM32_GTIM_CCER_OFFSET) +# define STM32_TIM2_CNT (STM32_TIM2_BASE+STM32_GTIM_CNT_OFFSET) +# define STM32_TIM2_PSC (STM32_TIM2_BASE+STM32_GTIM_PSC_OFFSET) +# define STM32_TIM2_ARR (STM32_TIM2_BASE+STM32_GTIM_ARR_OFFSET) +# define STM32_TIM2_CCR1 (STM32_TIM2_BASE+STM32_GTIM_CCR1_OFFSET) +# define STM32_TIM2_CCR2 (STM32_TIM2_BASE+STM32_GTIM_CCR2_OFFSET) +# define STM32_TIM2_CCR3 (STM32_TIM2_BASE+STM32_GTIM_CCR3_OFFSET) +# define STM32_TIM2_CCR4 (STM32_TIM2_BASE+STM32_GTIM_CCR4_OFFSET) +# define STM32_TIM2_DCR (STM32_TIM2_BASE+STM32_GTIM_DCR_OFFSET) +# define STM32_TIM2_DMAR (STM32_TIM2_BASE+STM32_GTIM_DMAR_OFFSET) +# define STM32_TIM2_OR (STM32_TIM2_BASE+STM32_GTIM_OR_OFFSET) +#endif + +#if (STM32F7_NGTIM16+STM32F7_NGTIM32) > 1 +# define STM32_TIM3_CR1 (STM32_TIM3_BASE+STM32_GTIM_CR1_OFFSET) +# define STM32_TIM3_CR2 (STM32_TIM3_BASE+STM32_GTIM_CR2_OFFSET) +# define STM32_TIM3_SMCR (STM32_TIM3_BASE+STM32_GTIM_SMCR_OFFSET) +# define STM32_TIM3_DIER (STM32_TIM3_BASE+STM32_GTIM_DIER_OFFSET) +# define STM32_TIM3_SR (STM32_TIM3_BASE+STM32_GTIM_SR_OFFSET) +# define STM32_TIM3_EGR (STM32_TIM3_BASE+STM32_GTIM_EGR_OFFSET) +# define STM32_TIM3_CCMR1 (STM32_TIM3_BASE+STM32_GTIM_CCMR1_OFFSET) +# define STM32_TIM3_CCMR2 (STM32_TIM3_BASE+STM32_GTIM_CCMR2_OFFSET) +# define STM32_TIM3_CCER (STM32_TIM3_BASE+STM32_GTIM_CCER_OFFSET) +# define STM32_TIM3_CNT (STM32_TIM3_BASE+STM32_GTIM_CNT_OFFSET) +# define STM32_TIM3_PSC (STM32_TIM3_BASE+STM32_GTIM_PSC_OFFSET) +# define STM32_TIM3_ARR (STM32_TIM3_BASE+STM32_GTIM_ARR_OFFSET) +# define STM32_TIM3_CCR1 (STM32_TIM3_BASE+STM32_GTIM_CCR1_OFFSET) +# define STM32_TIM3_CCR2 (STM32_TIM3_BASE+STM32_GTIM_CCR2_OFFSET) +# define STM32_TIM3_CCR3 (STM32_TIM3_BASE+STM32_GTIM_CCR3_OFFSET) +# define STM32_TIM3_CCR4 (STM32_TIM3_BASE+STM32_GTIM_CCR4_OFFSET) +# define STM32_TIM3_DCR (STM32_TIM3_BASE+STM32_GTIM_DCR_OFFSET) +# define STM32_TIM3_DMAR (STM32_TIM3_BASE+STM32_GTIM_DMAR_OFFSET) +#endif + +#if (STM32F7_NGTIM16+STM32F7_NGTIM32) > 2 +# define STM32_TIM4_CR1 (STM32_TIM4_BASE+STM32_GTIM_CR1_OFFSET) +# define STM32_TIM4_CR2 (STM32_TIM4_BASE+STM32_GTIM_CR2_OFFSET) +# define STM32_TIM4_SMCR (STM32_TIM4_BASE+STM32_GTIM_SMCR_OFFSET) +# define STM32_TIM4_DIER (STM32_TIM4_BASE+STM32_GTIM_DIER_OFFSET) +# define STM32_TIM4_SR (STM32_TIM4_BASE+STM32_GTIM_SR_OFFSET) +# define STM32_TIM4_EGR (STM32_TIM4_BASE+STM32_GTIM_EGR_OFFSET) +# define STM32_TIM4_CCMR1 (STM32_TIM4_BASE+STM32_GTIM_CCMR1_OFFSET) +# define STM32_TIM4_CCMR2 (STM32_TIM4_BASE+STM32_GTIM_CCMR2_OFFSET) +# define STM32_TIM4_CCER (STM32_TIM4_BASE+STM32_GTIM_CCER_OFFSET) +# define STM32_TIM4_CNT (STM32_TIM4_BASE+STM32_GTIM_CNT_OFFSET) +# define STM32_TIM4_PSC (STM32_TIM4_BASE+STM32_GTIM_PSC_OFFSET) +# define STM32_TIM4_ARR (STM32_TIM4_BASE+STM32_GTIM_ARR_OFFSET) +# define STM32_TIM4_CCR1 (STM32_TIM4_BASE+STM32_GTIM_CCR1_OFFSET) +# define STM32_TIM4_CCR2 (STM32_TIM4_BASE+STM32_GTIM_CCR2_OFFSET) +# define STM32_TIM4_CCR3 (STM32_TIM4_BASE+STM32_GTIM_CCR3_OFFSET) +# define STM32_TIM4_CCR4 (STM32_TIM4_BASE+STM32_GTIM_CCR4_OFFSET) +# define STM32_TIM4_DCR (STM32_TIM4_BASE+STM32_GTIM_DCR_OFFSET) +# define STM32_TIM4_DMAR (STM32_TIM4_BASE+STM32_GTIM_DMAR_OFFSET) +#endif + +#if (STM32F7_NGTIM16+STM32F7_NGTIM32) > 3 +# define STM32_TIM5_CR1 (STM32_TIM5_BASE+STM32_GTIM_CR1_OFFSET) +# define STM32_TIM5_CR2 (STM32_TIM5_BASE+STM32_GTIM_CR2_OFFSET) +# define STM32_TIM5_SMCR (STM32_TIM5_BASE+STM32_GTIM_SMCR_OFFSET) +# define STM32_TIM5_DIER (STM32_TIM5_BASE+STM32_GTIM_DIER_OFFSET) +# define STM32_TIM5_SR (STM32_TIM5_BASE+STM32_GTIM_SR_OFFSET) +# define STM32_TIM5_EGR (STM32_TIM5_BASE+STM32_GTIM_EGR_OFFSET) +# define STM32_TIM5_CCMR1 (STM32_TIM5_BASE+STM32_GTIM_CCMR1_OFFSET) +# define STM32_TIM5_CCMR2 (STM32_TIM5_BASE+STM32_GTIM_CCMR2_OFFSET) +# define STM32_TIM5_CCER (STM32_TIM5_BASE+STM32_GTIM_CCER_OFFSET) +# define STM32_TIM5_CNT (STM32_TIM5_BASE+STM32_GTIM_CNT_OFFSET) +# define STM32_TIM5_PSC (STM32_TIM5_BASE+STM32_GTIM_PSC_OFFSET) +# define STM32_TIM5_ARR (STM32_TIM5_BASE+STM32_GTIM_ARR_OFFSET) +# define STM32_TIM5_CCR1 (STM32_TIM5_BASE+STM32_GTIM_CCR1_OFFSET) +# define STM32_TIM5_CCR2 (STM32_TIM5_BASE+STM32_GTIM_CCR2_OFFSET) +# define STM32_TIM5_CCR3 (STM32_TIM5_BASE+STM32_GTIM_CCR3_OFFSET) +# define STM32_TIM5_CCR4 (STM32_TIM5_BASE+STM32_GTIM_CCR4_OFFSET) +# define STM32_TIM5_DCR (STM32_TIM5_BASE+STM32_GTIM_DCR_OFFSET) +# define STM32_TIM5_DMAR (STM32_TIM5_BASE+STM32_GTIM_DMAR_OFFSET) +# define STM32_TIM5_OR (STM32_TIM5_BASE+STM32_GTIM_OR_OFFSET) +#endif + + +/* 16-bit General Timers - TIM9-14 without DMA. Note that (1) these timers + * support only a subset of the general timer registers are supported, and + * (2) TIM9 and TIM12 differ from the others. + */ + +#if STM32F7_NGTIMNDMA > 0 +# define STM32_TIM9_CR1 (STM32_TIM9_BASE+STM32_GTIM_CR1_OFFSET) +# define STM32_TIM9_CR2 (STM32_TIM9_BASE+STM32_GTIM_CR2_OFFSET) +# define STM32_TIM9_DIER (STM32_TIM9_BASE+STM32_GTIM_DIER_OFFSET) +# define STM32_TIM9_SR (STM32_TIM9_BASE+STM32_GTIM_SR_OFFSET) +# define STM32_TIM9_EGR (STM32_TIM9_BASE+STM32_GTIM_EGR_OFFSET) +# define STM32_TIM9_CCMR1 (STM32_TIM9_BASE+STM32_GTIM_CCMR1_OFFSET) +# define STM32_TIM9_CCER (STM32_TIM9_BASE+STM32_GTIM_CCER_OFFSET) +# define STM32_TIM9_CNT (STM32_TIM9_BASE+STM32_GTIM_CNT_OFFSET) +# define STM32_TIM9_PSC (STM32_TIM9_BASE+STM32_GTIM_PSC_OFFSET) +# define STM32_TIM9_ARR (STM32_TIM9_BASE+STM32_GTIM_ARR_OFFSET) +# define STM32_TIM9_CCR1 (STM32_TIM9_BASE+STM32_GTIM_CCR1_OFFSET) +# define STM32_TIM9_CCR2 (STM32_TIM9_BASE+STM32_GTIM_CCR2_OFFSET) +#endif + +#if STM32F7_NGTIMNDMA > 1 +# define STM32_TIM10_CR1 (STM32_TIM10_BASE+STM32_GTIM_CR1_OFFSET) +# define STM32_TIM10_DIER (STM32_TIM10_BASE+STM32_GTIM_DIER_OFFSET) +# define STM32_TIM10_SR (STM32_TIM10_BASE+STM32_GTIM_SR_OFFSET) +# define STM32_TIM10_EGR (STM32_TIM10_BASE+STM32_GTIM_EGR_OFFSET) +# define STM32_TIM10_CCMR1 (STM32_TIM10_BASE+STM32_GTIM_CCMR1_OFFSET) +# define STM32_TIM10_CCER (STM32_TIM10_BASE+STM32_GTIM_CCER_OFFSET) +# define STM32_TIM10_CNT (STM32_TIM10_BASE+STM32_GTIM_CNT_OFFSET) +# define STM32_TIM10_PSC (STM32_TIM10_BASE+STM32_GTIM_PSC_OFFSET) +# define STM32_TIM10_ARR (STM32_TIM10_BASE+STM32_GTIM_ARR_OFFSET) +# define STM32_TIM10_CCR1 (STM32_TIM10_BASE+STM32_GTIM_CCR1_OFFSET) +#endif + +#if STM32F7_NGTIMNDMA > 2 +# define STM32_TIM11_CR1 (STM32_TIM11_BASE+STM32_GTIM_CR1_OFFSET) +# define STM32_TIM11_DIER (STM32_TIM11_BASE+STM32_GTIM_DIER_OFFSET) +# define STM32_TIM11_SR (STM32_TIM11_BASE+STM32_GTIM_SR_OFFSET) +# define STM32_TIM11_EGR (STM32_TIM11_BASE+STM32_GTIM_EGR_OFFSET) +# define STM32_TIM11_CCMR1 (STM32_TIM11_BASE+STM32_GTIM_CCMR1_OFFSET) +# define STM32_TIM11_CCER (STM32_TIM11_BASE+STM32_GTIM_CCER_OFFSET) +# define STM32_TIM11_CNT (STM32_TIM11_BASE+STM32_GTIM_CNT_OFFSET) +# define STM32_TIM11_PSC (STM32_TIM11_BASE+STM32_GTIM_PSC_OFFSET) +# define STM32_TIM11_ARR (STM32_TIM11_BASE+STM32_GTIM_ARR_OFFSET) +# define STM32_TIM11_CCR1 (STM32_TIM11_BASE+STM32_GTIM_CCR1_OFFSET) +# define STM32_TIM11_OR (STM32_TIM11_BASE+STM32_GTIM_OR_OFFSET) +#endif + +#if STM32F7_NGTIMNDMA > 3 +# define STM32_TIM12_CR1 (STM32_TIM12_BASE+STM32_GTIM_CR1_OFFSET) +# define STM32_TIM12_CR2 (STM32_TIM9_BASE+STM32_GTIM_CR2_OFFSET) +# define STM32_TIM12_DIER (STM32_TIM12_BASE+STM32_GTIM_DIER_OFFSET) +# define STM32_TIM12_SR (STM32_TIM12_BASE+STM32_GTIM_SR_OFFSET) +# define STM32_TIM12_EGR (STM32_TIM12_BASE+STM32_GTIM_EGR_OFFSET) +# define STM32_TIM12_CCMR1 (STM32_TIM12_BASE+STM32_GTIM_CCMR1_OFFSET) +# define STM32_TIM12_CCER (STM32_TIM12_BASE+STM32_GTIM_CCER_OFFSET) +# define STM32_TIM12_CNT (STM32_TIM12_BASE+STM32_GTIM_CNT_OFFSET) +# define STM32_TIM12_PSC (STM32_TIM12_BASE+STM32_GTIM_PSC_OFFSET) +# define STM32_TIM12_ARR (STM32_TIM12_BASE+STM32_GTIM_ARR_OFFSET) +# define STM32_TIM12_CCR1 (STM32_TIM12_BASE+STM32_GTIM_CCR1_OFFSET) +# define STM32_TIM12_CCR2 (STM32_TIM12_BASE+STM32_GTIM_CCR2_OFFSET) +#endif + +#if STM32F7_NGTIMNDMA > 4 +# define STM32_TIM13_CR1 (STM32_TIM13_BASE+STM32_GTIM_CR1_OFFSET) +# define STM32_TIM13_DIER (STM32_TIM13_BASE+STM32_GTIM_DIER_OFFSET) +# define STM32_TIM13_SR (STM32_TIM13_BASE+STM32_GTIM_SR_OFFSET) +# define STM32_TIM13_EGR (STM32_TIM13_BASE+STM32_GTIM_EGR_OFFSET) +# define STM32_TIM13_CCMR1 (STM32_TIM13_BASE+STM32_GTIM_CCMR1_OFFSET) +# define STM32_TIM13_CCER (STM32_TIM13_BASE+STM32_GTIM_CCER_OFFSET) +# define STM32_TIM13_CNT (STM32_TIM13_BASE+STM32_GTIM_CNT_OFFSET) +# define STM32_TIM13_PSC (STM32_TIM13_BASE+STM32_GTIM_PSC_OFFSET) +# define STM32_TIM13_ARR (STM32_TIM13_BASE+STM32_GTIM_ARR_OFFSET) +# define STM32_TIM13_CCR1 (STM32_TIM13_BASE+STM32_GTIM_CCR1_OFFSET) +#endif + +#if STM32F7_NGTIMNDMA > 5 +# define STM32_TIM14_CR1 (STM32_TIM14_BASE+STM32_GTIM_CR1_OFFSET) +# define STM32_TIM14_DIER (STM32_TIM14_BASE+STM32_GTIM_DIER_OFFSET) +# define STM32_TIM14_SR (STM32_TIM14_BASE+STM32_GTIM_SR_OFFSET) +# define STM32_TIM14_EGR (STM32_TIM14_BASE+STM32_GTIM_EGR_OFFSET) +# define STM32_TIM14_CCMR1 (STM32_TIM14_BASE+STM32_GTIM_CCMR1_OFFSET) +# define STM32_TIM14_CCER (STM32_TIM14_BASE+STM32_GTIM_CCER_OFFSET) +# define STM32_TIM14_CNT (STM32_TIM14_BASE+STM32_GTIM_CNT_OFFSET) +# define STM32_TIM14_PSC (STM32_TIM14_BASE+STM32_GTIM_PSC_OFFSET) +# define STM32_TIM14_ARR (STM32_TIM14_BASE+STM32_GTIM_ARR_OFFSET) +# define STM32_TIM14_CCR1 (STM32_TIM14_BASE+STM32_GTIM_CCR1_OFFSET) +#endif + +/* Basic Timers - TIM6 and TIM7 */ + +#if STM32F7_NBTIM > 0 +# define STM32_TIM6_CR1 (STM32_TIM6_BASE+STM32_BTIM_CR1_OFFSET) +# define STM32_TIM6_CR2 (STM32_TIM6_BASE+STM32_BTIM_CR2_OFFSET) +# define STM32_TIM6_DIER (STM32_TIM6_BASE+STM32_BTIM_DIER_OFFSET) +# define STM32_TIM6_SR (STM32_TIM6_BASE+STM32_BTIM_SR_OFFSET) +# define STM32_TIM6_EGR (STM32_TIM6_BASE+STM32_BTIM_EGR_OFFSET) +# define STM32_TIM6_CNT (STM32_TIM6_BASE+STM32_BTIM_CNT_OFFSET) +# define STM32_TIM6_PSC (STM32_TIM6_BASE+STM32_BTIM_PSC_OFFSET) +# define STM32_TIM6_ARR (STM32_TIM6_BASE+STM32_BTIM_ARR_OFFSET) +#endif + +#if STM32F7_NBTIM > 1 +# define STM32_TIM7_CR1 (STM32_TIM7_BASE+STM32_BTIM_CR1_OFFSET) +# define STM32_TIM7_CR2 (STM32_TIM7_BASE+STM32_BTIM_CR2_OFFSET) +# define STM32_TIM7_DIER (STM32_TIM7_BASE+STM32_BTIM_DIER_OFFSET) +# define STM32_TIM7_SR (STM32_TIM7_BASE+STM32_BTIM_SR_OFFSET) +# define STM32_TIM7_EGR (STM32_TIM7_BASE+STM32_BTIM_EGR_OFFSET) +# define STM32_TIM7_CNT (STM32_TIM7_BASE+STM32_BTIM_CNT_OFFSET) +# define STM32_TIM7_PSC (STM32_TIM7_BASE+STM32_BTIM_PSC_OFFSET) +# define STM32_TIM7_ARR (STM32_TIM7_BASE+STM32_BTIM_ARR_OFFSET) +#endif + +/* Register Bitfield Definitions ********************************************************************/ + +/* Control register 1 */ + +#define ATIM_CR1_CEN (1 << 0) /* Bit 0: Counter enable */ +#define ATIM_CR1_UDIS (1 << 1) /* Bit 1: Update disable */ +#define ATIM_CR1_URS (1 << 2) /* Bit 2: Update request source */ +#define ATIM_CR1_OPM (1 << 3) /* Bit 3: One pulse mode */ +#define ATIM_CR1_DIR (1 << 4) /* Bit 4: Direction */ +#define ATIM_CR1_CMS_SHIFT (5) /* Bits 6-5: Center-aligned mode selection */ +#define ATIM_CR1_CMS_MASK (3 << ATIM_CR1_CMS_SHIFT) +# define ATIM_CR1_EDGE (0 << ATIM_CR1_CMS_SHIFT) /* 00: Edge-aligned mode */ +# define ATIM_CR1_CENTER1 (1 << ATIM_CR1_CMS_SHIFT) /* 01: Center-aligned mode 1 */ +# define ATIM_CR1_CENTER2 (2 << ATIM_CR1_CMS_SHIFT) /* 10: Center-aligned mode 2 */ +# define ATIM_CR1_CENTER3 (3 << ATIM_CR1_CMS_SHIFT) /* 11: Center-aligned mode 3 */ +#define ATIM_CR1_ARPE (1 << 7) /* Bit 7: Auto-reload preload enable */ +#define ATIM_CR1_CKD_SHIFT (8) /* Bits 9-8: Clock division */ +#define ATIM_CR1_CKD_MASK (3 << ATIM_CR1_CKD_SHIFT) +# define ATIM_CR1_TCKINT (0 << ATIM_CR1_CKD_SHIFT) /* 00: tDTS=tCK_INT */ +# define ATIM_CR1_2TCKINT (1 << ATIM_CR1_CKD_SHIFT) /* 01: tDTS=2*tCK_INT */ +# define ATIM_CR1_4TCKINT (2 << ATIM_CR1_CKD_SHIFT) /* 10: tDTS=4*tCK_INT */ +#define ATIM_CR1_UIFREMAP (1 << 11) /* Bit 11: UIF status bit remapping */ + +/* Control register 2 */ + +#define ATIM_CR2_CCPC (1 << 0) /* Bit 0: Capture/Compare Preloaded Control */ +#define ATIM_CR2_CCUS (1 << 2) /* Bit 2: Capture/Compare Control Update Selection */ +#define ATIM_CR2_CCDS (1 << 3) /* Bit 3: Capture/Compare DMA Selection */ +#define ATIM_CR2_MMS_SHIFT (4) /* Bits 6-4: Master Mode Selection */ +#define ATIM_CR2_MMS_MASK (7 << ATIM_CR2_MMS_SHIFT) +# define ATIM_CR2_MMS_RESET (0 << ATIM_CR2_MMS_SHIFT) /* 000: Reset - TIMx_EGR UG bit is TRGO */ +# define ATIM_CR2_MMS_ENABLE (1 << ATIM_CR2_MMS_SHIFT) /* 001: Enable - CNT_EN is TRGO */ +# define ATIM_CR2_MMS_UPDATE (2 << ATIM_CR2_MMS_SHIFT) /* 010: Update event is TRGO */ +# define ATIM_CR2_MMS_COMPP (3 << ATIM_CR2_MMS_SHIFT) /* 010: Compare Pulse - CC1IF flag */ +# define ATIM_CR2_MMS_OC1REF (4 << ATIM_CR2_MMS_SHIFT) /* 100: Compare OC1REF is TRGO */ +# define ATIM_CR2_MMS_OC2REF (5 << ATIM_CR2_MMS_SHIFT) /* 101: Compare OC2REF is TRGO */ +# define ATIM_CR2_MMS_OC3REF (6 << ATIM_CR2_MMS_SHIFT) /* 110: Compare OC3REF is TRGO */ +# define ATIM_CR2_MMS_OC4REF (7 << ATIM_CR2_MMS_SHIFT) /* 111: Compare OC4REF is TRGO */ +#define ATIM_CR2_TI1S (1 << 7) /* Bit 7: TI1 Selection */ +#define ATIM_CR2_OIS1 (1 << 8) /* Bit 8: Output Idle state 1 (OC1 output) */ +#define ATIM_CR2_OIS1N (1 << 9) /* Bit 9: Output Idle state 1 (OC1N output) */ +#define ATIM_CR2_OIS2 (1 << 10) /* Bit 10: Output Idle state 2 (OC2 output) */ +#define ATIM_CR2_OIS2N (1 << 11) /* Bit 11: Output Idle state 2 (OC2N output) */ +#define ATIM_CR2_OIS3 (1 << 12) /* Bit 12: Output Idle state 3 (OC3 output) */ +#define ATIM_CR2_OIS3N (1 << 13) /* Bit 13: Output Idle state 3 (OC3N output) */ +#define ATIM_CR2_OIS4 (1 << 14) /* Bit 14: Output Idle state 4 (OC4 output) */ +#define ATIM_CR2_OIS5 (1 << 16) /* Bit 16: OOutput Idle state 5 (OC5 output) */ +#define ATIM_CR2_OIS6 (1 << 18) /* Bit 18: Output Idle state 6 (OC6 output) */ +#define ATIM_CR2_MMS2_SHIFT (20) /* Bits 20-23: Master Mode Selection 2 */ +#define ATIM_CR2_MMS2_MASK (15 << ATIM_CR2_MMS2_SHIFT) +# define ATIM_CR2_MMS2_RESET (0 << ATIM_CR2_MMS2_SHIFT) /* 0000: Reset - TIMx_EGR UG bit is TRG9 */ +# define ATIM_CR2_MMS2_ENABLE (1 << ATIM_CR2_MMS2_SHIFT) /* 0001: Enable - CNT_EN is TRGO2 */ +# define ATIM_CR2_MMS2_UPDATE (2 << ATIM_CR2_MMS2_SHIFT) /* 0010: Update event is TRGH0*/ +# define ATIM_CR2_MMS2_COMPP (3 << ATIM_CR2_MMS2_SHIFT) /* 0010: Compare Pulse - CC1IF flag */ +# define ATIM_CR2_MMS2_OC1REF (4 << ATIM_CR2_MMS2_SHIFT) /* 0100: Compare OC1REF is TRGO2 */ +# define ATIM_CR2_MMS2_OC2REF (5 << ATIM_CR2_MMS2_SHIFT) /* 0101: Compare OC2REF is TRGO2 */ +# define ATIM_CR2_MMS2_OC3REF (6 << ATIM_CR2_MMS2_SHIFT) /* 0110: Compare OC3REF is TRGO2 */ +# define ATIM_CR2_MMS2_OC4REF (7 << ATIM_CR2_MMS2_SHIFT) /* 0111: Compare OC4REF is TRGO2 */ +# define ATIM_CR2_MMS2_OC5REF (8 << ATIM_CR2_MMS2_SHIFT) /* 1000: Compare OC5REF is TRGO2 */ +# define ATIM_CR2_MMS2_OC6REF (9 << ATIM_CR2_MMS2_SHIFT) /* 1001: Compare OC6REF is TRGO2 */ +# define ATIM_CR2_MMS2_CMPOC4 (10 << ATIM_CR2_MMS2_SHIFT) /* 1010: Compare pulse - OC4REF edge is TRGO2 */ +# define ATIM_CR2_MMS2_CMPOC6 (11 << ATIM_CR2_MMS2_SHIFT) /* 1011: Compare pulse - OC6REF edge is TRGO2 */ +# define ATIM_CR2_MMS2_CMPOC4R6R (12 << ATIM_CR2_MMS2_SHIFT) /* 1100: Compare pulse - OC4REF/OC6REF rising */ +# define ATIM_CR2_MMS2_CMPOC4R6F (13 << ATIM_CR2_MMS2_SHIFT) /* 1101: Compare pulse - OC4REF rising/OC6REF falling */ +# define ATIM_CR2_MMS2_CMPOC5R6R (14 << ATIM_CR2_MMS2_SHIFT) /* 1110: Compare pulse - OC5REF/OC6REF rising */ +# define ATIM_CR2_MMS2_CMPOC5R6F (15 << ATIM_CR2_MMS2_SHIFT) /* 1111: Compare pulse - OC5REF rising/OC6REF falling */ + +/* Slave mode control register */ + +#define ATIM_SMCR_SMS_SHIFT (0) /* Bits 0-2: Slave mode selection */ +#define ATIM_SMCR_SMS_MASK (7 << ATIM_SMCR_SMS_SHIFT) +# define ATIM_SMCR_DISAB (0 << ATIM_SMCR_SMS_SHIFT) /* 000: Slave mode disabled */ +# define ATIM_SMCR_ENCMD1 (1 << ATIM_SMCR_SMS_SHIFT) /* 001: Encoder mode 1 */ +# define ATIM_SMCR_ENCMD2 (2 << ATIM_SMCR_SMS_SHIFT) /* 010: Encoder mode 2 */ +# define ATIM_SMCR_ENCMD3 (3 << ATIM_SMCR_SMS_SHIFT) /* 011: Encoder mode 3 */ +# define ATIM_SMCR_RESET (4 << ATIM_SMCR_SMS_SHIFT) /* 100: Reset Mode */ +# define ATIM_SMCR_GATED (5 << ATIM_SMCR_SMS_SHIFT) /* 101: Gated Mode */ +# define ATIM_SMCR_TRIGGER (6 << ATIM_SMCR_SMS_SHIFT) /* 110: Trigger Mode */ +# define ATIM_SMCR_EXTCLK1 (7 << ATIM_SMCR_SMS_SHIFT) /* 111: External Clock Mode 1 */ +#define ATIM_SMCR_TS_SHIFT (4) /* Bits 4-6: Trigger selection */ +#define ATIM_SMCR_TS_MASK (7 << ATIM_SMCR_TS_SHIFT) +# define ATIM_SMCR_ITR0 (0 << ATIM_SMCR_TS_SHIFT) /* 000: Internal trigger 0 (ITR0) */ +# define ATIM_SMCR_ITR1 (1 << ATIM_SMCR_TS_SHIFT) /* 001: Internal trigger 1 (ITR1) */ +# define ATIM_SMCR_ITR2 (2 << ATIM_SMCR_TS_SHIFT) /* 010: Internal trigger 2 (ITR2) */ +# define ATIM_SMCR_ITR3 (3 << ATIM_SMCR_TS_SHIFT) /* 011: Internal trigger 3 (ITR3) */ +# define ATIM_SMCR_T1FED (4 << ATIM_SMCR_TS_SHIFT) /* 100: TI1 Edge Detector (TI1F_ED) */ +# define ATIM_SMCR_TI1FP1 (5 << ATIM_SMCR_TS_SHIFT) /* 101: Filtered Timer Input 1 (TI1FP1) */ +# define ATIM_SMCR_T12FP2 (6 << ATIM_SMCR_TS_SHIFT) /* 110: Filtered Timer Input 2 (TI2FP2) */ +# define ATIM_SMCR_ETRF (7 << ATIM_SMCR_TS_SHIFT) /* 111: External Trigger input (ETRF) */ +#define ATIM_SMCR_MSM (1 << 7) /* Bit 7: Master/slave mode */ +#define ATIM_SMCR_ETF_SHIFT (8) /* Bits 8-11: External trigger filter */ +#define ATIM_SMCR_ETF_MASK (0x0f << ATIM_SMCR_ETF_SHIFT) +# define ATIM_SMCR_NOFILT (0 << ATIM_SMCR_ETF_SHIFT) /* 0000: No filter, sampling is done at fDTS */ +# define ATIM_SMCR_FCKINT2 (1 << ATIM_SMCR_ETF_SHIFT) /* 0001: fSAMPLING=fCK_INT, N=2 */ +# define ATIM_SMCR_FCKINT4 (2 << ATIM_SMCR_ETF_SHIFT) /* 0010: fSAMPLING=fCK_INT, N=4 */ +# define ATIM_SMCR_FCKINT8 (3 << ATIM_SMCR_ETF_SHIFT) /* 0011: fSAMPLING=fCK_INT, N=8 */ +# define ATIM_SMCR_FDTSd26 (4 << ATIM_SMCR_ETF_SHIFT) /* 0100: fSAMPLING=fDTS/2, N=6 */ +# define ATIM_SMCR_FDTSd28 (5 << ATIM_SMCR_ETF_SHIFT) /* 0101: fSAMPLING=fDTS/2, N=8 */ +# define ATIM_SMCR_FDTSd46 (6 << ATIM_SMCR_ETF_SHIFT) /* 0110: fSAMPLING=fDTS/4, N=6 */ +# define ATIM_SMCR_FDTSd48 (7 << ATIM_SMCR_ETF_SHIFT) /* 0111: fSAMPLING=fDTS/4, N=8 */ +# define ATIM_SMCR_FDTSd86 (8 << ATIM_SMCR_ETF_SHIFT) /* 1000: fSAMPLING=fDTS/8, N=6 */ +# define ATIM_SMCR_FDTSd88 (9 << ATIM_SMCR_ETF_SHIFT) /* 1001: fSAMPLING=fDTS/8, N=8 */ +# define ATIM_SMCR_FDTSd165 (10 << ATIM_SMCR_ETF_SHIFT) /* 1010: fSAMPLING=fDTS/16, N=5 */ +# define ATIM_SMCR_FDTSd166 (11 << ATIM_SMCR_ETF_SHIFT) /* 1011: fSAMPLING=fDTS/16, N=6 */ +# define ATIM_SMCR_FDTSd168 (12 << ATIM_SMCR_ETF_SHIFT) /* 1100: fSAMPLING=fDTS/16, N=8 */ +# define ATIM_SMCR_FDTSd325 (13 << ATIM_SMCR_ETF_SHIFT) /* 1101: fSAMPLING=fDTS/32, N=5 */ +# define ATIM_SMCR_FDTSd326 (14 << ATIM_SMCR_ETF_SHIFT) /* 1110: fSAMPLING=fDTS/32, N=6 */ +# define ATIM_SMCR_FDTSd328 (15 << ATIM_SMCR_ETF_SHIFT) /* 1111: fSAMPLING=fDTS/32, N=8 */ +#define ATIM_SMCR_ETPS_SHIFT (12) /* Bits 12-13: External trigger prescaler */ +#define ATIM_SMCR_ETPS_MASK (3 << ATIM_SMCR_ETPS_SHIFT) +# define ATIM_SMCR_PSCOFF (0 << ATIM_SMCR_ETPS_SHIFT) /* 00: Prescaler OFF */ +# define ATIM_SMCR_ETRPd2 (1 << ATIM_SMCR_ETPS_SHIFT) /* 01: ETRP frequency divided by 2 */ +# define ATIM_SMCR_ETRPd4 (2 << ATIM_SMCR_ETPS_SHIFT) /* 10: ETRP frequency divided by 4 */ +# define ATIM_SMCR_ETRPd8 (3 << ATIM_SMCR_ETPS_SHIFT) /* 11: ETRP frequency divided by 8 */ +#define ATIM_SMCR_ECE (1 << 14) /* Bit 14: External clock enable */ +#define ATIM_SMCR_ETP (1 << 15) /* Bit 15: External trigger polarity */ +#define ATIM_SMCR_SMS (1 << 16) /* Bit 16: Slave mode selection - bit 3 */ + +/* DMA/Interrupt enable register */ + +#define ATIM_DIER_UIE (1 << 0) /* Bit 0: Update interrupt enable */ +#define ATIM_DIER_CC1IE (1 << 1) /* Bit 1: Capture/Compare 1 interrupt enable */ +#define ATIM_DIER_CC2IE (1 << 2) /* Bit 2: Capture/Compare 2 interrupt enable */ +#define ATIM_DIER_CC3IE (1 << 3) /* Bit 3: Capture/Compare 3 interrupt enable */ +#define ATIM_DIER_CC4IE (1 << 4) /* Bit 4: Capture/Compare 4 interrupt enable */ +#define ATIM_DIER_COMIE (1 << 5) /* Bit 5: COM interrupt enable */ +#define ATIM_DIER_TIE (1 << 6) /* Bit 6: Trigger interrupt enable */ +#define ATIM_DIER_BIE (1 << 7) /* Bit 7: Break interrupt enable */ +#define ATIM_DIER_UDE (1 << 8) /* Bit 8: Update DMA request enable */ +#define ATIM_DIER_CC1DE (1 << 9) /* Bit 9: Capture/Compare 1 DMA request enable */ +#define ATIM_DIER_CC2DE (1 << 10) /* Bit 10: Capture/Compare 2 DMA request enable */ +#define ATIM_DIER_CC3DE (1 << 11) /* Bit 11: Capture/Compare 3 DMA request enable */ +#define ATIM_DIER_CC4DE (1 << 12) /* Bit 12: Capture/Compare 4 DMA request enable */ +#define ATIM_DIER_COMDE (1 << 13) /* Bit 13: COM DMA request enable */ +#define ATIM_DIER_TDE (1 << 14) /* Bit 14: Trigger DMA request enable */ + +/* Status register */ + +#define ATIM_SR_UIF (1 << 0) /* Bit 0: Update interrupt Flag */ +#define ATIM_SR_CC1IF (1 << 1) /* Bit 1: Capture/Compare 1 interrupt Flag */ +#define ATIM_SR_CC2IF (1 << 2) /* Bit 2: Capture/Compare 2 interrupt Flag */ +#define ATIM_SR_CC3IF (1 << 3) /* Bit 3: Capture/Compare 3 interrupt Flag */ +#define ATIM_SR_CC4IF (1 << 4) /* Bit 4: Capture/Compare 4 interrupt Flag */ +#define ATIM_SR_COMIF (1 << 5) /* Bit 5: COM interrupt Flag */ +#define ATIM_SR_TIF (1 << 6) /* Bit 6: Trigger interrupt Flag */ +#define ATIM_SR_BIF (1 << 7) /* Bit 7: Break interrupt Flag */ +#define ATIM_SR_B2IF (1 << 8) /* Bit 8: Break 2 interrupt Flag */ +#define ATIM_SR_CC1OF (1 << 9) /* Bit 9: Capture/Compare 1 Overcapture Flag */ +#define ATIM_SR_CC2OF (1 << 10) /* Bit 10: Capture/Compare 2 Overcapture Flag */ +#define ATIM_SR_CC3OF (1 << 11) /* Bit 11: Capture/Compare 3 Overcapture Flag */ +#define ATIM_SR_CC4OF (1 << 12) /* Bit 12: Capture/Compare 4 Overcapture Flag */ +#define ATIM_SR_CC5IF (1 << 16) /* Bit 16: Compare 5 interrupt flag */ +#define ATIM_SR_CC6IF (1 << 17) /* Bit 17: Compare 6 interrupt flag */ + +/* Event generation register */ + +#define ATIM_EGR_UG (1 << 0) /* Bit 0: Update Generation */ +#define ATIM_EGR_CC1G (1 << 1) /* Bit 1: Capture/Compare 1 Generation */ +#define ATIM_EGR_CC2G (1 << 2) /* Bit 2: Capture/Compare 2 Generation */ +#define ATIM_EGR_CC3G (1 << 3) /* Bit 3: Capture/Compare 3 Generation */ +#define ATIM_EGR_CC4G (1 << 4) /* Bit 4: Capture/Compare 4 Generation */ +#define ATIM_EGR_COMG (1 << 5) /* Bit 5: Capture/Compare Control Update Generation */ +#define ATIM_EGR_TG (1 << 6) /* Bit 6: Trigger Generation */ +#define ATIM_EGR_BG (1 << 7) /* Bit 7: Break Generation */ +#define ATIM_EGR_B2G (1 << 8) /* Bit 8: Break 2 Generation */ + +/* Capture/compare mode register 1 -- Output compare mode */ + +#define ATIM_CCMR1_CC1S_SHIFT (0) /* Bits 1-0: Capture/Compare 1 Selection */ +#define ATIM_CCMR1_CC1S_MASK (3 << ATIM_CCMR1_CC1S_SHIFT) + /* (See common (unshifted) bit field definitions below) */ +#define ATIM_CCMR1_OC1FE (1 << 2) /* Bit 2: Output Compare 1 Fast enable */ +#define ATIM_CCMR1_OC1PE (1 << 3) /* Bit 3: Output Compare 1 Preload enable */ +#define ATIM_CCMR1_OC1M_SHIFT (4) /* Bits 6-4: Output Compare 1 Mode */ +#define ATIM_CCMR1_OC1M_MASK (7 << ATIM_CCMR1_OC1M_SHIFT) + /* (See common (unshifted) bit field definitions below) */ +#define ATIM_CCMR1_OC1CE (1 << 7) /* Bit 7: Output Compare 1Clear Enable */ +#define ATIM_CCMR1_CC2S_SHIFT (8) /* Bits 8-9: Capture/Compare 2 Selection */ +#define ATIM_CCMR1_CC2S_MASK (3 << ATIM_CCMR1_CC2S_SHIFT) + /* (See common (unshifted) bit field definitions below) */ +#define ATIM_CCMR1_OC2FE (1 << 10) /* Bit 10: Output Compare 2 Fast enable */ +#define ATIM_CCMR1_OC2PE (1 << 11) /* Bit 11: Output Compare 2 Preload enable */ +#define ATIM_CCMR1_OC2M_SHIFT (12) /* Bits 14-12: Output Compare 2 Mode */ +#define ATIM_CCMR1_OC2M_MASK (7 << ATIM_CCMR1_OC2M_SHIFT) + /* (See common (unshifted) bit field definitions below) */ +#define ATIM_CCMR1_OC2CE (1 << 15) /* Bit 15: Output Compare 2 Clear Enable */ +#define ATIM_CCMR1_OC1M (1 << 16) /* Bit 16: Output Compare 1 mode - bit 3 */ +#define ATIM_CCMR1_OC2M (1 << 24) /* Bit 24: Output Compare 2 mode - bit 3 */ + + +/* Common CCMR (unshifted) Capture/Compare Selection bit-field definitions */ + +#define ATIM_CCMR_CCS_CCOUT (0) /* 00: CCx channel output */ +#define ATIM_CCMR_CCS_CCIN1 (1) /* 01: CCx channel input, ICx is TIx */ +#define ATIM_CCMR_CCS_CCIN2 (2) /* 10: CCx channel input, ICx is TIy */ +#define ATIM_CCMR_CCS_CCINTRC (3) /* 11: CCx channel input, ICx is TRC */ + +/* Common CCMR (unshifted) Compare Mode bit field definitions */ + +#define ATIM_CCMR_MODE_FRZN (0) /* 0000: Frozen */ +#define ATIM_CCMR_MODE_CHACT (1) /* 0001: Channel x active on match */ +#define ATIM_CCMR_MODE_CHINACT (2) /* 0010: Channel x inactive on match */ +#define ATIM_CCMR_MODE_OCREFTOG (3) /* 0011: OCxREF toggle ATIM_CNT=ATIM_CCRx */ +#define ATIM_CCMR_MODE_OCREFLO (4) /* 0100: OCxREF forced low */ +#define ATIM_CCMR_MODE_OCREFHI (5) /* 0101: OCxREF forced high */ +#define ATIM_CCMR_MODE_PWM1 (6) /* 0110: PWM mode 1 */ +#define ATIM_CCMR_MODE_PWM2 (7) /* 0111: PWM mode 2 */ +#define ATIM_CCMR_MODE_OPM1 (8) /* 1000: Retrigerrable OPM mode 1 */ +#define ATIM_CCMR_MODE_OPM2 (9) /* 1001: Retrigerrable OPM mode 2 */ +#define ATIM_CCMR_MODE_COMBINED1 (12) /* 1100: Combined PWM mode 1 */ +#define ATIM_CCMR_MODE_COMBINED2 (13) /* 1101: Combined PWM mode 2 */ +#define ATIM_CCMR_MODE_ASYMMETRIC1 (14) /* 1110: Asymmetric PWM mode 1 */ +#define ATIM_CCMR_MODE_ASYMMETRIC2 (15) /* 1111: Asymmetric PWM mode 2 */ + +/* Capture/compare mode register 1 -- Input capture mode */ + + /* Bits 1-0:(same as output compare mode) */ +#define ATIM_CCMR1_IC1PSC_SHIFT (2) /* Bits 3-2: Input Capture 1 Prescaler */ +#define ATIM_CCMR1_IC1PSC_MASK (3 << ATIM_CCMR1_IC1PSC_SHIFT) + /* (See common (unshifted) bit field definitions below) */ +#define ATIM_CCMR1_IC1F_SHIFT (4) /* Bits 7-4: Input Capture 1 Filter */ +#define ATIM_CCMR1_IC1F_MASK (0x0f << ATIM_CCMR1_IC1F_SHIFT) + /* (See common (unshifted) bit field definitions below) */ + /* Bits 9:8 (same as output compare mode) */ +#define ATIM_CCMR1_IC2PSC_SHIFT (10) /* Bits 11:10: Input Capture 2 Prescaler */ +#define ATIM_CCMR1_IC2PSC_MASK (3 << ATIM_CCMR1_IC2PSC_SHIFT) + /* (See common (unshifted) bit field definitions below) */ +#define ATIM_CCMR1_IC2F_SHIFT (12) /* Bits 15-12: Input Capture 2 Filter */ +#define ATIM_CCMR1_IC2F_MASK (0x0f << ATIM_CCMR1_IC2F_SHIFT) + /* (See common (unshifted) bit field definitions below) */ + +/* Common CCMR (unshifted) Input Capture Prescaler bit-field definitions */ + +#define ATIM_CCMR_ICPSC_NOPSC (0) /* 00: no prescaler, capture each edge */ +#define ATIM_CCMR_ICPSC_EVENTS2 (1) /* 01: capture once every 2 events */ +#define ATIM_CCMR_ICPSC_EVENTS4 (2) /* 10: capture once every 4 events */ +#define ATIM_CCMR_ICPSC_EVENTS8 (3) /* 11: capture once every 8 events */ + +/* Common CCMR (unshifted) Input Capture Filter bit-field definitions */ + +#define ATIM_CCMR_ICF_NOFILT (0) /* 0000: No filter, sampling at fDTS */ +#define ATIM_CCMR_ICF_FCKINT2 (1) /* 0001: fSAMPLING=fCK_INT, N=2 */ +#define ATIM_CCMR_ICF_FCKINT4 (2) /* 0010: fSAMPLING=fCK_INT, N=4 */ +#define ATIM_CCMR_ICF_FCKINT8 (3) /* 0011: fSAMPLING=fCK_INT, N=8 */ +#define ATIM_CCMR_ICF_FDTSd26 (4) /* 0100: fSAMPLING=fDTS/2, N=6 */ +#define ATIM_CCMR_ICF_FDTSd28 (5) /* 0101: fSAMPLING=fDTS/2, N=8 */ +#define ATIM_CCMR_ICF_FDTSd46 (6) /* 0110: fSAMPLING=fDTS/4, N=6 */ +#define ATIM_CCMR_ICF_FDTSd48 (7) /* 0111: fSAMPLING=fDTS/4, N=8 */ +#define ATIM_CCMR_ICF_FDTSd86 (8) /* 1000: fSAMPLING=fDTS/8, N=6 */ +#define ATIM_CCMR_ICF_FDTSd88 (9) /* 1001: fSAMPLING=fDTS/8, N=8 */ +#define ATIM_CCMR_ICF_FDTSd165 (10) /* 1010: fSAMPLING=fDTS/16, N=5 */ +#define ATIM_CCMR_ICF_FDTSd166 (11) /* 1011: fSAMPLING=fDTS/16, N=6 */ +#define ATIM_CCMR_ICF_FDTSd168 (12) /* 1100: fSAMPLING=fDTS/16, N=8 */ +#define ATIM_CCMR_ICF_FDTSd325 (13) /* 1101: fSAMPLING=fDTS/32, N=5 */ +#define ATIM_CCMR_ICF_FDTSd326 (14) /* 1110: fSAMPLING=fDTS/32, N=6 */ +#define ATIM_CCMR_ICF_FDTSd328 (15) /* 1111: fSAMPLING=fDTS/32, N=8 */ + +/* Capture/compare mode register 2 - Output Compare mode */ + +#define ATIM_CCMR2_CC3S_SHIFT (0) /* Bits 1-0: Capture/Compare 3 Selection */ +#define ATIM_CCMR2_CC3S_MASK (3 << ATIM_CCMR2_CC3S_SHIFT) + /* (See common (unshifted) bit field definitions above) */ +#define ATIM_CCMR2_OC3FE (1 << 2) /* Bit 2: Output Compare 3 Fast enable */ +#define ATIM_CCMR2_OC3PE (1 << 3) /* Bit 3: Output Compare 3 Preload enable */ +#define ATIM_CCMR2_OC3M_SHIFT (4) /* Bits 6-4: Output Compare 3 Mode */ +#define ATIM_CCMR2_OC3M_MASK (7 << ATIM_CCMR2_OC3M_SHIFT) + /* (See common (unshifted) bit field definitions above) */ +#define ATIM_CCMR2_OC3CE (1 << 7) /* Bit 7: Output Compare 3 Clear Enable */ +#define ATIM_CCMR2_CC4S_SHIFT (8) /* Bits 9-8: Capture/Compare 4 Selection */ +#define ATIM_CCMR2_CC4S_MASK (3 << ATIM_CCMR2_CC4S_SHIFT) + /* (See common (unshifted) bit field definitions above) */ +#define ATIM_CCMR2_OC4FE (1 << 10) /* Bit 10: Output Compare 4 Fast enable */ +#define ATIM_CCMR2_OC4PE (1 << 11) /* Bit 11: Output Compare 4 Preload enable */ +#define ATIM_CCMR2_OC4M_SHIFT (12) /* Bits 14-12: Output Compare 4 Mode */ +#define ATIM_CCMR2_OC4M_MASK (7 << ATIM_CCMR2_OC4M_SHIFT) + /* (See common (unshifted) bit field definitions above) */ +#define ATIM_CCMR2_OC4CE (1 << 15) /* Bit 15: Output Compare 4 Clear Enable */ +#define ATIM_CCMR2_OC3M (1 << 16) /* Bit 16: Output Compare 3 mode - bit 3 */ +#define ATIM_CCMR2_OC4M (1 << 24) /* Bit 24: Output Compare 4 mode - bit 3 */ + +/* Capture/compare mode register 2 - Input Capture Mode */ + + /* Bits 1-0:(same as output compare mode) */ +#define ATIM_CCMR2_IC3PSC_SHIFT (2) /* Bits 3-2: Input Capture 3 Prescaler */ +#define ATIM_CCMR1_IC3PSC_MASK (3 << ATIM_CCMR2_IC3PSC_SHIFT) + /* (See common (unshifted) bit field definitions above) */ +#define ATIM_CCMR2_IC3F_SHIFT (4) /* Bits 7-4: Input Capture 3 Filter */ +#define ATIM_CCMR2_IC3F_MASK (0x0f << ATIM_CCMR2_IC3F_SHIFT) + /* (See common (unshifted) bit field definitions above) */ + /* Bits 9:8 (same as output compare mode) */ +#define ATIM_CCMR2_IC4PSC_SHIFT (10) /* Bits 11:10: Input Capture 4 Prescaler */ +#define ATIM_CCMR2_IC4PSC_MASK (3 << ATIM_CCMR2_IC4PSC_SHIFT) + /* (See common (unshifted) bit field definitions above) */ +#define ATIM_CCMR2_IC4F_SHIFT (12) /* Bits 15-12: Input Capture 4 Filter */ +#define ATIM_CCMR2_IC4F_MASK (0x0f << ATIM_CCMR2_IC4F_SHIFT) + /* (See common (unshifted) bit field definitions above) */ + +/* Capture/compare mode register 3 -- Output compare mode */ + +#define ATIM_CCMR3_OC5FE (1 << 2) /* Bit 2: Output Compare 5 Fast enable */ +#define ATIM_CCMR3_OC5PE (1 << 3) /* Bit 3: Output Compare 5 Preload enable */ +#define ATIM_CCMR3_OC5M_SHIFT (4) /* Bits 6-4: Output Compare 5 Mode */ +#define ATIM_CCMR3_OC5M_MASK (7 << ATIM_CCMR3_OC5M_SHIFT) + /* (See common (unshifted) bit field definitions below) */ +#define ATIM_CCMR3_OC5CE (1 << 7) /* Bit 7: Output Compare 5 Clear Enable */ +#define ATIM_CCMR3_OC6FE (1 << 10) /* Bit 10: Output Compare 6 Fast enable */ +#define ATIM_CCMR3_OC6PE (1 << 11) /* Bit 11: Output Compare 6 Preload enable */ +#define ATIM_CCMR3_OC6M_SHIFT (12) /* Bits 14-12: Output Compare 7 Mode */ +#define ATIM_CCMR3_OC6M_MASK (7 << ATIM_CCMR3_OC6M_SHIFT) + /* (See common (unshifted) bit field definitions below) */ +#define ATIM_CCMR3_OC6CE (1 << 15) /* Bit 15: Output Compare 7 Clear Enable */ +#define ATIM_CCMR3_OC5M (1 << 16) /* Bit 16: Output Compare 5 mode - bit 3 */ +#define ATIM_CCMR3_OC6M (1 << 24) /* Bit 24: Output Compare 6 mode - bit 3 */ + + +/* Capture/compare enable register */ + +#define ATIM_CCER_CC1E (1 << 0) /* Bit 0: Capture/Compare 1 output enable */ +#define ATIM_CCER_CC1P (1 << 1) /* Bit 1: Capture/Compare 1 output Polarity */ +#define ATIM_CCER_CC1NE (1 << 2) /* Bit 2: Capture/Compare 1 Complementary output enable */ +#define ATIM_CCER_CC1NP (1 << 3) /* Bit 3: Capture/Compare 1 Complementary output polarity */ +#define ATIM_CCER_CC2E (1 << 4) /* Bit 4: Capture/Compare 2 output enable */ +#define ATIM_CCER_CC2P (1 << 5) /* Bit 5: Capture/Compare 2 output Polarity */ +#define ATIM_CCER_CC2NE (1 << 6) /* Bit 6: Capture/Compare 2 Complementary output enable */ +#define ATIM_CCER_CC2NP (1 << 7) /* Bit 7: Capture/Compare 2 Complementary output polarity */ +#define ATIM_CCER_CC3E (1 << 8) /* Bit 8: Capture/Compare 3 output enable */ +#define ATIM_CCER_CC3P (1 << 9) /* Bit 9: Capture/Compare 3 output Polarity */ +#define ATIM_CCER_CC3NE (1 << 10) /* Bit 10: Capture/Compare 3 Complementary output enable */ +#define ATIM_CCER_CC3NP (1 << 11) /* Bit 11: Capture/Compare 3 Complementary output polarity */ +#define ATIM_CCER_CC4E (1 << 12) /* Bit 12: Capture/Compare 4 output enable */ +#define ATIM_CCER_CC4P (1 << 13) /* Bit 13: Capture/Compare 4 output Polarity */ +#define ATIM_CCER_CC4NP (1 << 15) /* Bit 15: Capture/Compare 4 Complementary output polarity */ +#define ATIM_CCER_CC5E (1 << 16) /* Bit 16: Capture/Compare 5 output enable */ +#define ATIM_CCER_CC5P (1 << 17) /* Bit 17: Capture/Compare 5 output Polarity */ +#define ATIM_CCER_CC6E (1 << 20) /* Bit 20: Capture/Compare 6 output enable */ +#define ATIM_CCER_CC6P (1 << 21) /* Bit 21: Capture/Compare 6 output Polarity */ + + +/* 16-bit counter register */ + +#define ATIM_CNT_SHIFT (0) /* Bits 0-15: Timer counter value */ +#define ATIM_CNT_MASK (0xffff << ATIM_CNT_SHIFT) + +/* Repetition counter register */ + +#define ATIM_RCR_REP_SHIFT (0) /* Bits 0-15: Repetition Counter Value */ +#define ATIM_RCR_REP_MASK (0xffff << ATIM_RCR_REP_SHIFT) + +#define ATIM_RCR_REP_MAX 65536 + +/* Capture/compare registers (CCR) */ + +#define ATIM_CCR5_GC5C1 (1 << 29) /* Bit 29: Group Channel 5 and Channel 1 */ +#define ATIM_CCR5_GC5C2 (1 << 30) /* Bit 30: Group Channel 5 and Channel 2 */ +#define ATIM_CCR5_GC5C3 (1 << 31) /* Bit 31: Group Channel 5 and Channel 3 */ + +#define ATIM_CCR_MASK (0xffff) + +/* Alternate function option register 1 (TIMx_AF1) */ + +#define ATIM_AF1_BKINE (1 << 0) /* Bit 0: BRK BKIN input enable */ +#define ATIM_AF1_BKDFBKE (1 << 8) /* Bit 8: BRK DFSDM_BREAK[0] enable */ +#define ATIM_AF1_BKINP (1 << 9) /* Bit 9: BRK BKIN input polarity */ + +/* Alternate function option register 2 (TIMx_AF2) */ + +#define ATIM_AF1_BK2INE (1 << 0) /* Bit 0: BRK2 BKIN input enable */ +#define ATIM_AF1_BK2DFBKE (1 << 8) /* Bit 8: BRK2 DFSDM_BREAK enable */ +#define ATIM_AF1_BK2INP (1 << 9) /* Bit 9: BRK2 BKIN2 input polarity */ + +/* Break and dead-time register */ + +#define ATIM_BDTR_DTG_SHIFT (0) /* Bits 7:0 [7:0]: Dead-Time Generator set-up */ +#define ATIM_BDTR_DTG_MASK (0xff << ATIM_BDTR_DTG_SHIFT) +#define ATIM_BDTR_LOCK_SHIFT (8) /* Bits 9:8 [1:0]: Lock Configuration */ +#define ATIM_BDTR_LOCK_MASK (3 << ATIM_BDTR_LOCK_SHIFT) +# define ATIM_BDTR_LOCKOFF (0 << ATIM_BDTR_LOCK_SHIFT) /* 00: LOCK OFF - No bit is write protected */ +# define ATIM_BDTR_LOCK1 (1 << ATIM_BDTR_LOCK_SHIFT) /* 01: LOCK Level 1 protection */ +# define ATIM_BDTR_LOCK2 (2 << ATIM_BDTR_LOCK_SHIFT) /* 10: LOCK Level 2 protection */ +# define ATIM_BDTR_LOCK3 (3 << ATIM_BDTR_LOCK_SHIFT) /* 11: LOCK Level 3 protection */ */ +#define ATIM_BDTR_OSSI (1 << 10) /* Bit 10: Off-State Selection for Idle mode */ +#define ATIM_BDTR_OSSR (1 << 11) /* Bit 11: Off-State Selection for Run mode */ +#define ATIM_BDTR_BKE (1 << 12) /* Bit 12: Break enable */ +#define ATIM_BDTR_BKP (1 << 13) /* Bit 13: Break Polarity */ +#define ATIM_BDTR_AOE (1 << 14) /* Bit 14: Automatic Output enable */ +#define ATIM_BDTR_MOE (1 << 15) /* Bit 15: Main Output enable */ +#define ATIM_BDTR_BKF_SHIFT (16) /* Bits 16-19: Break filter */ +#define ATIM_BDTR_BKF_MASK (0xf << ATIM_BDTR_BKF_SHIFT) +# define ATIM_BDTR_BKF_NOFILT (0 << ATIM_BDTR_BKF_SHIFT) /* 0000: No filter, BRK acts asynchronously */ +# define ATIM_BDTR_BKF_FCKINT2 (1 << ATIM_BDTR_BKF_SHIFT) /* 0001: fSAMPLING=fCK_INT, N=2 */ +# define ATIM_BDTR_BKF_FCKINT4 (2 << ATIM_BDTR_BKF_SHIFT) /* 0010: fSAMPLING=fCK_INT, N=4 */ +# define ATIM_BDTR_BKF_FCKINT8 (3 << ATIM_BDTR_BKF_SHIFT) /* 0011: fSAMPLING=fCK_INT, N=8 */ +# define ATIM_BDTR_BKF_FDTSd26 (4 << ATIM_BDTR_BKF_SHIFT) /* 0100: fSAMPLING=fDTS/2, N=6 */ +# define ATIM_BDTR_BKF_FDTSd28 (5 << ATIM_BDTR_BKF_SHIFT) /* 0101: fSAMPLING=fDTS/2, N=8 */ +# define ATIM_BDTR_BKF_FDTSd36 (6 << ATIM_BDTR_BKF_SHIFT) /* 0110: fSAMPLING=fDTS/4, N=6 */ +# define ATIM_BDTR_BKF_FDTSd38 (7 << ATIM_BDTR_BKF_SHIFT) /* 0111: fSAMPLING=fDTS/4, N=8 */ +# define ATIM_BDTR_BKF_FDTSd86 (8 << ATIM_BDTR_BKF_SHIFT) /* 1000: fSAMPLING=fDTS/8, N=6 */ +# define ATIM_BDTR_BKF_FDTSd88 (9 << ATIM_BDTR_BKF_SHIFT) /* 1001: fSAMPLING=fDTS/8, N=8 */ +# define ATIM_BDTR_BKF_FDTSd165 (10 << ATIM_BDTR_BKF_SHIFT) /* 1010: fSAMPLING=fDTS/16, N=5 */ +# define ATIM_BDTR_BKF_FDTSd166 (11 << ATIM_BDTR_BKF_SHIFT) /* 1011: fSAMPLING=fDTS/16, N=6 */ +# define ATIM_BDTR_BKF_FDTSd168 (12 << ATIM_BDTR_BKF_SHIFT) /* 1100: fSAMPLING=fDTS/16, N=8 */ +# define ATIM_BDTR_BKF_FDTSd325 (13 << ATIM_BDTR_BKF_SHIFT) /* 1101: fSAMPLING=fDTS/32, N=5 */ +# define ATIM_BDTR_BKF_FDTSd326 (14 << ATIM_BDTR_BKF_SHIFT) /* 1110: fSAMPLING=fDTS/32, N=6 */ +# define ATIM_BDTR_BKF_FDTSd328 (15 << ATIM_BDTR_BKF_SHIFT) /* 1111: fSAMPLING=fDTS/32, N=8 */ +#define ATIM_BDTR_BK2F_SHIFT (20) /* Bits 20-23: Break 2 filter */ +#define ATIM_BDTR_BK2F_MASK (0xf << ATIM_BDTR_BK2F_SHIFT) +# define ATIM_BDTR_BK2F_NOFILT (0 << ATIM_BDTR_BK2F_SHIFT) /* 0000: No filter, BRK 2 acts asynchronously */ +# define ATIM_BDTR_BK2F_FCKINT2 (1 << ATIM_BDTR_BK2F_SHIFT) /* 0001: fSAMPLING=fCK_INT, N=2 */ +# define ATIM_BDTR_BK2F_FCKINT4 (2 << ATIM_BDTR_BK2F_SHIFT) /* 0010: fSAMPLING=fCK_INT, N=4 */ +# define ATIM_BDTR_BK2F_FCKINT8 (3 << ATIM_BDTR_BK2F_SHIFT) /* 0011: fSAMPLING=fCK_INT, N=8 */ +# define ATIM_BDTR_BK2F_FDTSd26 (4 << ATIM_BDTR_BK2F_SHIFT) /* 0100: fSAMPLING=fDTS/2, N=6 */ +# define ATIM_BDTR_BK2F_FDTSd28 (5 << ATIM_BDTR_BK2F_SHIFT) /* 0101: fSAMPLING=fDTS/2, N=8 */ +# define ATIM_BDTR_BK2F_FDTSd36 (6 << ATIM_BDTR_BK2F_SHIFT) /* 0110: fSAMPLING=fDTS/4, N=6 */ +# define ATIM_BDTR_BK2F_FDTSd38 (7 << ATIM_BDTR_BK2F_SHIFT) /* 0111: fSAMPLING=fDTS/4, N=8 */ +# define ATIM_BDTR_BK2F_FDTSd86 (8 << ATIM_BDTR_BK2F_SHIFT) /* 1000: fSAMPLING=fDTS/8, N=6 */ +# define ATIM_BDTR_BK2F_FDTSd88 (9 << ATIM_BDTR_BK2F_SHIFT) /* 1001: fSAMPLING=fDTS/8, N=8 */ +# define ATIM_BDTR_BK2F_FDTSd165 (10 << ATIM_BDTR_BK2F_SHIFT) /* 1010: fSAMPLING=fDTS/16, N=5 */ +# define ATIM_BDTR_BK2F_FDTSd166 (11 << ATIM_BDTR_BK2F_SHIFT) /* 1011: fSAMPLING=fDTS/16, N=6 */ +# define ATIM_BDTR_BK2F_FDTSd168 (12 << ATIM_BDTR_BK2F_SHIFT) /* 1100: fSAMPLING=fDTS/16, N=8 */ +# define ATIM_BDTR_BK2F_FDTSd325 (13 << ATIM_BDTR_BK2F_SHIFT) /* 1101: fSAMPLING=fDTS/32, N=5 */ +# define ATIM_BDTR_BK2F_FDTSd326 (14 << ATIM_BDTR_BK2F_SHIFT) /* 1110: fSAMPLING=fDTS/32, N=6 */ +# define ATIM_BDTR_BK2F_FDTSd328 (15 << ATIM_BDTR_BK2F_SHIFT) /* 1111: fSAMPLING=fDTS/32, N=8 */ +#define ATIM_BDTR_BK2E (1 << 24) /* Bit 24: Break 2 enable */ +#define ATIM_BDTR_BK2P (1 << 1525 /* Bit 25:Break 2 polarity */ + + +/* DMA control register */ + +#define ATIM_DCR_DBA_SHIFT (0) /* Bits 4-0: DMA Base Address */ +#define ATIM_DCR_DBA_MASK (0x1f << ATIM_DCR_DBA_SHIFT) +#define ATIM_DCR_DBL_SHIFT (8) /* Bits 12-8: DMA Burst Length */ +#define ATIM_DCR_DBL_MASK (0x1f << ATIM_DCR_DBL_SHIFT) +# define ATIM_DCR_DBL(n) (((n)-1) << ATIM_DCR_DBL_SHIFT) /* n transfers, n = 1..18 */ + +/* Control register 1 (TIM2-5 and TIM9-14) */ + +#define GTIM_CR1_CEN (1 << 0) /* Bit 0: Counter enable */ +#define GTIM_CR1_UDIS (1 << 1) /* Bit 1: Update Disable */ +#define GTIM_CR1_URS (1 << 2) /* Bit 2: Update Request Source */ +#define GTIM_CR1_OPM (1 << 3) /* Bit 3: One Pulse Mode (TIM2-5, 9, and 12 only) */ +#define GTIM_CR1_DIR (1 << 4) /* Bit 4: Direction (TIM2-5 only) */ +#define GTIM_CR1_CMS_SHIFT (5) /* Bits 6-5: Center-aligned Mode Selection (TIM2-5 only) */ +#define GTIM_CR1_CMS_MASK (3 << GTIM_CR1_CMS_SHIFT) +# define GTIM_CR1_EDGE (0 << GTIM_CR1_CMS_SHIFT) /* 00: Edge-aligned mode. */ +# define GTIM_CR1_CENTER1 (1 << GTIM_CR1_CMS_SHIFT) /* 01: Center-aligned mode 1 */ +# define GTIM_CR1_CENTER2 (2 << GTIM_CR1_CMS_SHIFT) /* 10: Center-aligned mode 2 */ +# define GTIM_CR1_CENTER3 (3 << GTIM_CR1_CMS_SHIFT) /* 11: Center-aligned mode 3 */ +#define GTIM_CR1_ARPE (1 << 7) /* Bit 7: Auto-Reload Preload enable */ +#define GTIM_CR1_CKD_SHIFT (8) /* Bits 9-8: Clock Division */ +#define GTIM_CR1_CKD_MASK (3 << GTIM_CR1_CKD_SHIFT) +# define GTIM_CR1_TCKINT (0 << GTIM_CR1_CKD_SHIFT) /* 00: tDTS = tCK_INT */ +# define GTIM_CR1_2TCKINT (1 << GTIM_CR1_CKD_SHIFT) /* 01: tDTS = 2 x tCK_INT */ +# define GTIM_CR1_4TCKINT (2 << GTIM_CR1_CKD_SHIFT) /* 10: tDTS = 4 x tCK_INT */ +#define GTIM_CR1_UIFREMAP (1 << 11) /* Bit 11: UIF status bit remapping */ + +/* Control register 2 (TIM2-5, TIM9-12) */ + +#define GTIM_CR2_CCPC (1 << 0) /* Bit 0: Capture/compare preloaded control (TIM15-17 only) */ +#define GTIM_CR2_CCUS (1 << 2) /* Bit 2: Capture/compare control update selection (TIM15-17 only) */ +#define GTIM_CR2_CCDS (1 << 3) /* Bit 3: Capture/Compare DMA Selection (TIM2-5,1,&16 only) */ +#define GTIM_CR2_MMS_SHIFT (4) /* Bits 6-4: Master Mode Selection (not TIM16) */ +#define GTIM_CR2_MMS_MASK (7 << GTIM_CR2_MMS_SHIFT) +# define GTIM_CR2_MMS_RESET (0 << GTIM_CR2_MMS_SHIFT) /* 000: Reset */ +# define GTIM_CR2_MMS_ENABLE (1 << GTIM_CR2_MMS_SHIFT) /* 001: Enable */ +# define GTIM_CR2_MMS_UPDATE (2 << GTIM_CR2_MMS_SHIFT) /* 010: Update */ +# define GTIM_CR2_MMS_COMPP (3 << GTIM_CR2_MMS_SHIFT) /* 011: Compare Pulse */ +# define GTIM_CR2_MMS_OC1REF (4 << GTIM_CR2_MMS_SHIFT) /* 100: Compare - OC1REF signal is used as trigger output (TRGO) */ +# define GTIM_CR2_MMS_OC2REF (5 << GTIM_CR2_MMS_SHIFT) /* 101: Compare - OC2REF signal is used as trigger output (TRGO) */ +# define GTIM_CR2_MMS_OC3REF (6 << GTIM_CR2_MMS_SHIFT) /* 110: Compare - OC3REF signal is used as trigger output (TRGO, TIM2-5 and TIM15 only) */ +# define GTIM_CR2_MMS_OC4REF (7 << GTIM_CR2_MMS_SHIFT) /* 111: Compare - OC4REF signal is used as trigger output (TRGO, TIM2-5 and TIM15 only) */ +#define GTIM_CR2_TI1S (1 << 7) /* Bit 7: TI1 Selection (not TIM16) */ +#define GTIM_CR2_OIS1 (1 << 8) /* Bit 8: COutput Idle state 1 (OC1 output) (TIM15-17 only) */ +#define GTIM_CR2_OIS1N (1 << 9) /* Bit 9: Output Idle state 1 (OC1N output) (TIM15-17 only) */ +#define GTIM_CR2_OIS2 (1 << 10) /* Bit 10: Output idle state 2 (OC2 output) (TIM15 only) */ + +/* Slave mode control register (TIM2-5) */ + +#define GTIM_SMCR_SMS_SHIFT (0) /* Bits 2-0: Slave Mode Selection */ +#define GTIM_SMCR_SMS_MASK (7 << GTIM_SMCR_SMS_SHIFT) +# define GTIM_SMCR_DISAB (0 << GTIM_SMCR_SMS_SHIFT) /* 000: Slave mode disabled */ +# define GTIM_SMCR_ENCMD1 (1 << GTIM_SMCR_SMS_SHIFT) /* 001: Encoder mode 1 */ +# define GTIM_SMCR_ENCMD2 (2 << GTIM_SMCR_SMS_SHIFT) /* 010: Encoder mode 2 */ +# define GTIM_SMCR_ENCMD3 (3 << GTIM_SMCR_SMS_SHIFT) /* 011: Encoder mode 3 */ +# define GTIM_SMCR_RESET (4 << GTIM_SMCR_SMS_SHIFT) /* 100: Reset Mode */ +# define GTIM_SMCR_GATED (5 << GTIM_SMCR_SMS_SHIFT) /* 101: Gated Mode */ +# define GTIM_SMCR_TRIGGER (6 << GTIM_SMCR_SMS_SHIFT) /* 110: Trigger Mode */ +# define GTIM_SMCR_EXTCLK1 (7 << GTIM_SMCR_SMS_SHIFT) /* 111: External Clock Mode 1 */ +#define GTIM_SMCR_TS_SHIFT (4) /* Bits 6-4: Trigger Selection */ +#define GTIM_SMCR_TS_MASK (7 << GTIM_SMCR_TS_SHIFT) +# define GTIM_SMCR_ITR0 (0 << GTIM_SMCR_TS_SHIFT) /* 000: Internal Trigger 0 (ITR0). TIM1 */ +# define GTIM_SMCR_ITR1 (1 << GTIM_SMCR_TS_SHIFT) /* 001: Internal Trigger 1 (ITR1). TIM2 */ +# define GTIM_SMCR_ITR2 (2 << GTIM_SMCR_TS_SHIFT) /* 010: Internal Trigger 2 (ITR2). TIM3 */ +# define GTIM_SMCR_ITR3 (3 << GTIM_SMCR_TS_SHIFT) /* 011: Internal Trigger 3 (ITR3). TIM4 */ +# define GTIM_SMCR_TI1FED (4 << GTIM_SMCR_TS_SHIFT) /* 100: TI1 Edge Detector (TI1F_ED) */ +# define GTIM_SMCR_TI1FP1 (5 << GTIM_SMCR_TS_SHIFT) /* 101: Filtered Timer Input 1 (TI1FP1) */ +# define GTIM_SMCR_TI2FP2 (6 << GTIM_SMCR_TS_SHIFT) /* 110: Filtered Timer Input 2 (TI2FP2) */ +# define GTIM_SMCR_ETRF (7 << GTIM_SMCR_TS_SHIFT) /* 111: External Trigger input (ETRF) */ +#define GTIM_SMCR_MSM (1 << 7) /* Bit 7: Master/Slave mode */ +#define GTIM_SMCR_ETF_SHIFT (8) /* Bits 11-8: External Trigger Filter (not TIM15) */ +#define GTIM_SMCR_ETF_MASK (0x0f << GTIM_SMCR_ETF_SHIFT) +# define GTIM_SMCR_NOFILT (0 << GTIM_SMCR_ETF_SHIFT) /* 0000: No filter, sampling is done at fDTS */ +# define GTIM_SMCR_FCKINT2 (1 << GTIM_SMCR_ETF_SHIFT) /* 0001: fSAMPLING=fCK_INT, N=2 */ +# define GTIM_SMCR_FCKINT4 (2 << GTIM_SMCR_ETF_SHIFT) /* 0010: fSAMPLING=fCK_INT, N=4 */ +# define GTIM_SMCR_FCKINT8 (3 << GTIM_SMCR_ETF_SHIFT) /* 0011: fSAMPLING=fCK_INT, N=8 */ +# define GTIM_SMCR_FDTSd26 (4 << GTIM_SMCR_ETF_SHIFT) /* 0100: fSAMPLING=fDTS/2, N=6 */ +# define GTIM_SMCR_FDTSd28 (5 << GTIM_SMCR_ETF_SHIFT) /* 0101: fSAMPLING=fDTS/2, N=8 */ +# define GTIM_SMCR_FDTSd36 (6 << GTIM_SMCR_ETF_SHIFT) /* 0110: fSAMPLING=fDTS/4, N=6 */ +# define GTIM_SMCR_FDTSd38 (7 << GTIM_SMCR_ETF_SHIFT) /* 0111: fSAMPLING=fDTS/4, N=8 */ +# define GTIM_SMCR_FDTSd86 (8 << GTIM_SMCR_ETF_SHIFT) /* 1000: fSAMPLING=fDTS/8, N=6 */ +# define GTIM_SMCR_FDTSd88 (9 << GTIM_SMCR_ETF_SHIFT) /* 1001: fSAMPLING=fDTS/8, N=8 */ +# define GTIM_SMCR_FDTSd165 (10 << GTIM_SMCR_ETF_SHIFT) /* 1010: fSAMPLING=fDTS/16, N=5 */ +# define GTIM_SMCR_FDTSd166 (11 << GTIM_SMCR_ETF_SHIFT) /* 1011: fSAMPLING=fDTS/16, N=6 */ +# define GTIM_SMCR_FDTSd168 (12 << GTIM_SMCR_ETF_SHIFT) /* 1100: fSAMPLING=fDTS/16, N=8 */ +# define GTIM_SMCR_FDTSd325 (13 << GTIM_SMCR_ETF_SHIFT) /* 1101: fSAMPLING=fDTS/32, N=5 */ +# define GTIM_SMCR_FDTSd326 (14 << GTIM_SMCR_ETF_SHIFT) /* 1110: fSAMPLING=fDTS/32, N=6 */ +# define GTIM_SMCR_FDTSd328 (15 << GTIM_SMCR_ETF_SHIFT) /* 1111: fSAMPLING=fDTS/32, N=8 */ +#define GTIM_SMCR_ETPS_SHIFT (12) /* Bits 13-12: External Trigger Prescaler (not TIM15) */ +#define GTIM_SMCR_ETPS_MASK (3 << GTIM_SMCR_ETPS_SHIFT) +# define GTIM_SMCR_PSCOFF (0 << GTIM_SMCR_ETPS_SHIFT) /* 00: Prescaler OFF */ +# define GTIM_SMCR_ETRPd2 (1 << GTIM_SMCR_ETPS_SHIFT) /* 01: ETRP frequency divided by 2 */ +# define GTIM_SMCR_ETRPd4 (2 << GTIM_SMCR_ETPS_SHIFT) /* 10: ETRP frequency divided by 4 */ +# define GTIM_SMCR_ETRPd8 (3 << GTIM_SMCR_ETPS_SHIFT) /* 11: ETRP frequency divided by 8 */ +#define GTIM_SMCR_ECE (1 << 14) /* Bit 14: External Clock enable */ +#define GTIM_SMCR_ETP (1 << 15) /* Bit 15: External Trigger Polarity */ +#define GTIM_SMCR_SMS (1 << 16) /* Bit 16: Slave mode selection - bit 3 */ + +/* DMA/Interrupt enable register (TIM2-5 and TIM9-14) */ + +#define GTIM_DIER_UIE (1 << 0) /* Bit 0: Update interrupt enable */ +#define GTIM_DIER_CC1IE (1 << 1) /* Bit 1: Capture/Compare 1 interrupt enable */ +#define GTIM_DIER_CC2IE (1 << 2) /* Bit 2: Capture/Compare 2 interrupt enable (TIM2-5,9,12,&15 only) */ +#define GTIM_DIER_CC3IE (1 << 3) /* Bit 3: Capture/Compare 3 interrupt enable (TIM2-5 only) */ +#define GTIM_DIER_CC4IE (1 << 4) /* Bit 4: Capture/Compare 4 interrupt enable (TIM2-5 only) */ +#define GTIM_DIER_COMIE (1 << 5) /* Bit 5: COM interrupt enable (TIM15-17 only) */ +#define GTIM_DIER_TIE (1 << 6) /* Bit 6: Trigger interrupt enable (TIM2-5,9,&12 only) */ +#define GTIM_DIER_BIE (1 << 7) /* Bit 7: Break interrupt enable (TIM15-17 only) */ +#define GTIM_DIER_UDE (1 << 8) /* Bit 8: Update DMA request enable (TIM2-5&15-17 only) */ +#define GTIM_DIER_CC1DE (1 << 9) /* Bit 9: Capture/Compare 1 DMA request enable (TIM2-5&15-17 only) */ +#define GTIM_DIER_CC2DE (1 << 10) /* Bit 10: Capture/Compare 2 DMA request enable (TIM2-5&15 only) */ +#define GTIM_DIER_CC3DE (1 << 11) /* Bit 11: Capture/Compare 3 DMA request enable (TIM2-5 only) */ +#define GTIM_DIER_CC4DE (1 << 12) /* Bit 12: Capture/Compare 4 DMA request enable (TIM2-5 only) */ +#define GTIM_DIER_COMDE (1 << 13) /* Bit 13: COM DMA request enable (TIM15-17 only) */ +#define GTIM_DIER_TDE (1 << 14) /* Bit 14: Trigger DMA request enable (TIM2-5&15-17 only) */ + +/* Status register */ + +#define GTIM_SR_UIF (1 << 0) /* Bit 0: Update interrupt flag */ +#define GTIM_SR_CC1IF (1 << 1) /* Bit 1: Capture/compare 1 interrupt flag */ +#define GTIM_SR_CC2IF (1 << 2) /* Bit 2: Capture/Compare 2 interrupt flag (TIM2-5,9,12,&15 only) */ +#define GTIM_SR_CC3IF (1 << 3) /* Bit 3: Capture/Compare 3 interrupt flag (TIM2-5 only) */ +#define GTIM_SR_CC4IF (1 << 4) /* Bit 4: Capture/Compare 4 interrupt flag (TIM2-5 only) */ +#define GTIM_SR_COMIF (1 << 5) /* Bit 5: COM interrupt flag (TIM15-17 only) */ +#define GTIM_SR_TIF (1 << 6) /* Bit 6: Trigger interrupt Flag (TIM2-5,9,12&15-17 only) */ +#define GTIM_SR_BIF (1 << 7) /* Bit 7: Break interrupt flag (TIM15-17 only) */ +#define GTIM_SR_CC1OF (1 << 9) /* Bit 9: Capture/Compare 1 Overcapture flag */ +#define GTIM_SR_CC2OF (1 << 10) /* Bit 10: Capture/Compare 2 Overcapture flag (TIM2-5,9,12&15 only) */ +#define GTIM_SR_CC3OF (1 << 11) /* Bit 11: Capture/Compare 3 Overcapture flag (TIM2-5 only) */ +#define GTIM_SR_CC4OF (1 << 12) /* Bit 12: Capture/Compare 4 Overcapture flag (TIM2-5 only) */ + +/* Event generation register (TIM2-5 and TIM9-14) */ + +#define GTIM_EGR_UG (1 << 0) /* Bit 0: Update generation */ +#define GTIM_EGR_CC1G (1 << 1) /* Bit 1: Capture/compare 1 generation */ +#define GTIM_EGR_CC2G (1 << 2) /* Bit 2: Capture/compare 2 generation (TIM2-5,9,12,&15 only) */ +#define GTIM_EGR_CC3G (1 << 3) /* Bit 3: Capture/compare 3 generation (TIM2-5 only) */ +#define GTIM_EGR_CC4G (1 << 4) /* Bit 4: Capture/compare 4 generation (TIM2-5 only) */ +#define GTIM_EGR_COMIG (1 << 5) /* Bit 5: Capture/Compare control update generation (TIM15-17 only) */ +#define GTIM_EGR_TG (1 << 6) /* Bit 6: Trigger generation (TIM2-5,9,12&16-17 only) */ +#define GTIM_EGR_BG (1 << 7) /* Bit 7: Break generation (TIM15-17 only) */ + +/* Capture/compare mode register 1 - Output compare mode (TIM2-5 and TIM9-14) */ + +#define GTIM_CCMR1_CC1S_SHIFT (0) /* Bits 1-0: Capture/Compare 1 Selection */ +#define GTIM_CCMR1_CC1S_MASK (3 << GTIM_CCMR1_CC1S_SHIFT) + /* (See common CCMR Capture/Compare Selection definitions below) */ +#define GTIM_CCMR1_OC1FE (1 << 2) /* Bit 2: Output Compare 1 Fast enable */ +#define GTIM_CCMR1_OC1PE (1 << 3) /* Bit 3: Output Compare 1 Preload enable */ +#define GTIM_CCMR1_OC1M_SHIFT (4) /* Bits 6-4: Output Compare 1 Mode */ +#define GTIM_CCMR1_OC1M_MASK (7 << GTIM_CCMR1_OC1M_SHIFT) + /* (See common CCMR Output Compare Mode definitions below) */ +#define GTIM_CCMR1_OC1CE (1 << 7) /* Bit 7: Output Compare 1Clear Enable */ +#define GTIM_CCMR1_CC2S_SHIFT (8) /* Bits 9-8: Capture/Compare 2 Selection */ +#define GTIM_CCMR1_CC2S_MASK (3 << GTIM_CCMR1_CC2S_SHIFT) + /* (See common CCMR Capture/Compare Selection definitions below) */ +#define GTIM_CCMR1_OC2FE (1 << 10) /* Bit 10: Output Compare 2 Fast enable */ +#define GTIM_CCMR1_OC2PE (1 << 11) /* Bit 11: Output Compare 2 Preload enable */ +#define GTIM_CCMR1_OC2M_SHIFT (12) /* Bits 14-12: Output Compare 2 Mode */ +#define GTIM_CCMR1_OC2M_MASK (7 << GTIM_CCMR1_OC2M_SHIFT) + /* (See common CCMR Output Compare Mode definitions below) */ +#define GTIM_CCMR1_OC2CE (1 << 15) /* Bit 15: Output Compare 2 Clear Enable */ +#define GTIM_CCMR1_OC1M (1 << 16) /* Bit 16: Output Compare 1 mode - bit 3 */ +#define GTIM_CCMR1_OC2M (1 << 24) /* Bit 24: Output Compare 2 mode - bit 3 */ + +/* Common CCMR (unshifted) Capture/Compare Selection bit-field definitions */ + +#define GTIM_CCMR_CCS_CCOUT (0) /* 00: CCx channel output */ +#define GTIM_CCMR_CCS_CCIN1 (1) /* 01: CCx channel input, ICx is TIx */ +#define GTIM_CCMR_CCS_CCIN2 (2) /* 10: CCx channel input, ICx is TIy */ +#define GTIM_CCMR_CCS_CCINTRC (3) /* 11: CCx channel input, ICx is TRC */ + +/* Common CCMR (unshifted) Compare Mode bit field definitions */ + +#define GTIM_CCMR_MODE_FRZN (0) /* 000: Frozen */ +#define GTIM_CCMR_MODE_CHACT (1) /* 001: Channel x active on match */ +#define GTIM_CCMR_MODE_CHINACT (2) /* 010: Channel x inactive on match */ +#define GTIM_CCMR_MODE_OCREFTOG (3) /* 011: OCxREF toggle ATIM_CNT=ATIM_CCRx */ +#define GTIM_CCMR_MODE_OCREFLO (4) /* 100: OCxREF forced low */ +#define GTIM_CCMR_MODE_OCREFHI (5) /* 101: OCxREF forced high */ +#define GTIM_CCMR_MODE_PWM1 (6) /* 110: PWM mode 1 */ +#define GTIM_CCMR_MODE_PWM2 (7) /* 111: PWM mode 2 */ + +/* Capture/compare mode register 1 - Input capture mode (TIM2-5 and TIM9-14) */ + + /* Bits 1-0 (Same as Output Compare Mode) */ +#define GTIM_CCMR1_IC1PSC_SHIFT (2) /* Bits 3-2: Input Capture 1 Prescaler */ +#define GTIM_CCMR1_IC1PSC_MASK (3 << GTIM_CCMR1_IC1PSC_SHIFT) + /* (See common CCMR Input Capture Prescaler definitions below) */ +#define GTIM_CCMR1_IC1F_SHIFT (4) /* Bits 7-4: Input Capture 1 Filter */ +#define GTIM_CCMR1_IC1F_MASK (0x0f << GTIM_CCMR1_IC1F_SHIFT) + /* (See common CCMR Input Capture Filter definitions below) */ + /* Bits 9-8: (Same as Output Compare Mode) */ +#define GTIM_CCMR1_IC2PSC_SHIFT (10) /* Bits 11-10: Input Capture 2 Prescaler */ +#define GTIM_CCMR1_IC2PSC_MASK (3 << GTIM_CCMR1_IC2PSC_SHIFT) + /* (See common CCMR Input Capture Prescaler definitions below) */ +#define GTIM_CCMR1_IC2F_SHIFT (12) /* Bits 15-12: Input Capture 2 Filter */ +#define GTIM_CCMR1_IC2F_MASK (0x0f << GTIM_CCMR1_IC2F_SHIFT) + /* (See common CCMR Input Capture Filter definitions below) */ + +/* Common CCMR (unshifted) Input Capture Prescaler bit-field definitions */ + +#define GTIM_CCMR_ICPSC_NOPSC (0) /* 00: no prescaler, capture each edge */ +#define GTIM_CCMR_ICPSC_EVENTS2 (1) /* 01: capture once every 2 events */ +#define GTIM_CCMR_ICPSC_EVENTS4 (2) /* 10: capture once every 4 events */ +#define GTIM_CCMR_ICPSC_EVENTS8 (3) /* 11: capture once every 8 events */ + +/* Common CCMR (unshifted) Input Capture Filter bit-field definitions */ + +#define GTIM_CCMR_ICF_NOFILT (0) /* 0000: No filter, sampling at fDTS */ +#define GTIM_CCMR_ICF_FCKINT2 (1) /* 0001: fSAMPLING=fCK_INT, N=2 */ +#define GTIM_CCMR_ICF_FCKINT4 (2) /* 0010: fSAMPLING=fCK_INT, N=4 */ +#define GTIM_CCMR_ICF_FCKINT8 (3) /* 0011: fSAMPLING=fCK_INT, N=8 */ +#define GTIM_CCMR_ICF_FDTSd26 (4) /* 0100: fSAMPLING=fDTS/2, N=6 */ +#define GTIM_CCMR_ICF_FDTSd28 (5) /* 0101: fSAMPLING=fDTS/2, N=8 */ +#define GTIM_CCMR_ICF_FDTSd46 (6) /* 0110: fSAMPLING=fDTS/4, N=6 */ +#define GTIM_CCMR_ICF_FDTSd48 (7) /* 0111: fSAMPLING=fDTS/4, N=8 */ +#define GTIM_CCMR_ICF_FDTSd86 (8) /* 1000: fSAMPLING=fDTS/8, N=6 */ +#define GTIM_CCMR_ICF_FDTSd88 (9) /* 1001: fSAMPLING=fDTS/8, N=8 */ +#define GTIM_CCMR_ICF_FDTSd165 (10) /* 1010: fSAMPLING=fDTS/16, N=5 */ +#define GTIM_CCMR_ICF_FDTSd166 (11) /* 1011: fSAMPLING=fDTS/16, N=6 */ +#define GTIM_CCMR_ICF_FDTSd168 (12) /* 1100: fSAMPLING=fDTS/16, N=8 */ +#define GTIM_CCMR_ICF_FDTSd325 (13) /* 1101: fSAMPLING=fDTS/32, N=5 */ +#define GTIM_CCMR_ICF_FDTSd326 (14) /* 1110: fSAMPLING=fDTS/32, N=6 */ +#define GTIM_CCMR_ICF_FDTSd328 (15) /* 1111: fSAMPLING=fDTS/32, N=8 */ + +/* Capture/compare mode register 2 - Output Compare mode (TIM2-5 only) */ + +#define GTIM_CCMR2_CC3S_SHIFT (0) /* Bits 1-0: Capture/Compare 3 Selection */ +#define GTIM_CCMR2_CC3S_MASK (3 << GTIM_CCMR2_CC3S_SHIFT) + /* (See common CCMR Capture/Compare Selection definitions above) */ +#define GTIM_CCMR2_OC3FE (1 << 2) /* Bit 2: Output Compare 3 Fast enable */ +#define GTIM_CCMR2_OC3PE (1 << 3) /* Bit 3: Output Compare 3 Preload enable */ +#define GTIM_CCMR2_OC3M_SHIFT (4) /* Bits 6-4: Output Compare 3 Mode */ +#define GTIM_CCMR2_OC3M_MASK (7 << GTIM_CCMR2_OC3M_SHIFT) + /* (See common CCMR Output Compare Mode definitions above) */ +#define GTIM_CCMR2_OC3CE (1 << 7) /* Bit 7: Output Compare 3 Clear Enable */ +#define GTIM_CCMR2_CC4S_SHIFT (8) /* Bits 9-8: Capture/Compare 4 Selection */ +#define GTIM_CCMR2_CC4S_MASK (3 << GTIM_CCMR2_CC4S_SHIFT) + /* (See common CCMR Capture/Compare Selection definitions above) */ +#define GTIM_CCMR2_OC4FE (1 << 10) /* Bit 10: Output Compare 4 Fast enable */ +#define GTIM_CCMR2_OC4PE (1 << 11) /* Bit 11: Output Compare 4 Preload enable */ +#define GTIM_CCMR2_OC4M_SHIFT (12) /* Bits 14-12: Output Compare 4 Mode */ +#define GTIM_CCMR2_OC4M_MASK (7 << GTIM_CCMR2_OC4M_SHIFT) + /* (See common CCMR Output Compare Mode definitions above) */ +#define GTIM_CCMR2_OC4CE (1 << 15) /* Bit 15: Output Compare 4 Clear Enable */ + +/* Capture/compare mode register 2 - Input capture mode (TIM2-5 only) */ + + /* Bits 1-0 (Same as Output Compare Mode) */ +#define GTIM_CCMR2_IC3PSC_SHIFT (2) /* Bits 3-2: Input Capture 3 Prescaler */ +#define GTIM_CCMR2_IC3PSC_MASK (3 << GTIM_CCMR2_IC3PSC_SHIFT) + /* (See common CCMR Input Capture Prescaler definitions below) */ +#define GTIM_CCMR2_IC3F_SHIFT (4) /* Bits 7-4: Input Capture 3 Filter */ +#define GTIM_CCMR2_IC3F_MASK (0x0f << GTIM_CCMR2_IC3F_SHIFT) + /* (See common CCMR Input Capture Filter definitions below) */ + /* Bits 9-8: (Same as Output Compare Mode) */ +#define GTIM_CCMR2_IC4PSC_SHIFT (10) /* Bits 11-10: Input Capture 4 Prescaler */ +#define GTIM_CCMR2_IC4PSC_MASK (3 << GTIM_CCMR2_IC4PSC_SHIFT) + /* (See common CCMR Input Capture Prescaler definitions below) */ +#define GTIM_CCMR2_IC4F_SHIFT (12) /* Bits 15-12: Input Capture 4 Filter */ +#define GTIM_CCMR2_IC4F_MASK (0x0f << GTIM_CCMR2_IC4F_SHIFT) + /* (See common CCMR Input Capture Filter definitions below) */ + +/* Capture/compare enable register (TIM1 and TIM8, TIM2-5 and TIM9-14) */ + +#define GTIM_CCER_CC1E (1 << 0) /* Bit 0: Capture/Compare 1 output enable */ +#define GTIM_CCER_CC1P (1 << 1) /* Bit 1: Capture/Compare 1 output polarity */ +#define GTIM_CCER_CC1NE (1 << 2) /* Bit 2: Capture/Compare 1 complementary output enable (TIM1 and TIM8 only) */ +#define GTIM_CCER_CC1NP (1 << 3) /* Bit 3: Capture/Compare 1 output Polarity (F2,F3,F4 and TIM15-17) */ +#define GTIM_CCER_CC2E (1 << 4) /* Bit 4: Capture/Compare 2 output enable (TIM2-5,9&12 only) */ +#define GTIM_CCER_CC2P (1 << 5) /* Bit 5: Capture/Compare 2 output polarity (TIM2-5,9&12 only) */ +#define GTIM_CCER_CC2NE (1 << 6) /* Bit 6: Capture/Compare 2 complementary output enable (TIM1 and TIM8 only) */ +#define GTIM_CCER_CC2NP (1 << 7) /* Bit 7: Capture/Compare 2 output Polarity (F2,F3,F4 and TIM2-5,9,12&15 only) */ +#define GTIM_CCER_CC3E (1 << 8) /* Bit 8: Capture/Compare 3 output enable (TIM2-5 only) */ +#define GTIM_CCER_CC3P (1 << 9) /* Bit 9: Capture/Compare 3 output Polarity (TIM2-5 only) */ +#define GTIM_CCER_CC3NE (1 << 10) /* Bit 10: Capture/Compare 3 complementary output enable (TIM1 and TIM8 only) */ +#define GTIM_CCER_CC3NP (1 << 11) /* Bit 11: Capture/Compare 3 output Polarity (F2,F4 and TIM2-5 only) */ +#define GTIM_CCER_CC4E (1 << 12) /* Bit 12: Capture/Compare 4 output enable (TIM2-5 only) */ +#define GTIM_CCER_CC4P (1 << 13) /* Bit 13: Capture/Compare 4 output Polarity (TIM2-5 only) */ +#define GTIM_CCER_CC4NP (1 << 15) /* Bit 15: Capture/Compare 4 output Polarity */ + +/* 16-bit counter register */ + +#define GTIM_CNT_SHIFT (0) /* Bits 0-15: Timer counter value */ +#define GTIM_CNT_MASK (0xffff << ATIM_CNT_SHIFT) + +/* DMA control register */ + +#define GTIM_DCR_DBA_SHIFT (0) /* Bits 4-0: DMA Base Address */ +#define GTIM_DCR_DBA_MASK (0x1f << GTIM_DCR_DBA_SHIFT) +#define GTIM_DCR_DBL_SHIFT (8) /* Bits 12-8: DMA Burst Length */ +#define GTIM_DCR_DBL_MASK (0x1f << GTIM_DCR_DBL_SHIFT) + +/* Timer 2/5 option register */ + +#define TIM2_OR_ITR1_RMP_SHIFT (10) /* Bits 10-11: Internal trigger 1 remap */ +#define TIM2_OR_ITR1_RMP_MASK (3 << TIM2_OR_ITR1_RMP_SHIFT) +# define TIM2_OR_ITR1_TIM8_TRGOUT (0 << TIM2_OR_ITR1_RMP_SHIFT) /* 00: TIM2_ITR1 input connected to TIM8_TRGOUT */ +# define TIM2_OR_ITR1_PTP (1 << TIM2_OR_ITR1_RMP_SHIFT) /* 01: TIM2_ITR1 input connected to PTP trigger output */ +# define TIM2_OR_ITR1_OTGFSSOF (2 << TIM2_OR_ITR1_RMP_SHIFT) /* 10: TIM2_ITR1 input connected to OTG FS SOF */ +# define TIM2_OR_ITR1_OTGHSSOF (3 << TIM2_OR_ITR1_RMP_SHIFT) /* 11: TIM2_ITR1 input connected to OTG HS SOF */ + +#define TIM5_OR_TI4_RMP_SHIFT (6) /* Bits 6-7: Internal trigger 4 remap */ +#define TIM5_OR_TI4_RMP_MASK (3 << TIM5_OR_TI4_RMP_SHIFT) +# define TIM5_OR_TI4_GPIO (0 << TIM5_OR_TI4_RMP_SHIFT) /* 00: TIM5_CH4 input connected to GPIO */ +# define TIM5_OR_TI4_LSI (1 << TIM5_OR_TI4_RMP_SHIFT) /* 01: TIM5_CH4 input connected to LSI internal clock */ +# define TIM5_OR_TI4_LSE (2 << TIM5_OR_TI4_RMP_SHIFT) /* 10: TIM5_CH4 input connected to LSE internal clock */ +# define TIM5_OR_TI4_RTC (3 << TIM5_OR_TI4_RMP_SHIFT) /* 11: TIM5_CH4 input connected to RTC output event */ + +#define TIM11_OR_TI1_RMP_SHIFT (6) /* Bits 6-7: Internal trigger 4 remap */ +#define TIM11_OR_TI1_RMP_MASK (3 << TIM11_OR_TI1_RMP_SHIFT) +# define TIM11_OR_TI1_GPIO (0 << TIM11_OR_TI1_RMP_SHIFT) /* 00-11: TIM11_CH1 input connected to GPIO */ +# define TIM11_OR_TI1_HSERTC (3 << TIM11_OR_TI1_RMP_SHIFT) /* 11: TIM11_CH1 input connected to HSE_RTC clock */ + + +/* Control register 1 */ + +#define BTIM_CR1_CEN (1 << 0) /* Bit 0: Counter enable */ +#define BTIM_CR1_UDIS (1 << 1) /* Bit 1: Update Disable */ +#define BTIM_CR1_URS (1 << 2) /* Bit 2: Update Request Source */ +#define BTIM_CR1_OPM (1 << 3) /* Bit 3: One Pulse Mode */ +#define BTIM_CR1_ARPE (1 << 7) /* Bit 7: Auto-Reload Preload enable */ + +/* Control register 2 */ + +#define BTIM_CR2_MMS_SHIFT (4) /* Bits 6-4: Master Mode Selection */ +#define BTIM_CR2_MMS_MASK (7 << BTIM_CR2_MMS_SHIFT) +# define BTIM_CR2_RESET (0 << BTIM_CR2_MMS_SHIFT) /* 000: Reset */ +# define BTIM_CR2_ENAB (1 << BTIM_CR2_MMS_SHIFT) /* 001: Enable */ +# define BTIM_CR2_UPDT (2 << BTIM_CR2_MMS_SHIFT) /* 010: Update */ + +/* DMA/Interrupt enable register */ + +#define BTIM_DIER_UIE (1 << 0) /* Bit 0: Update interrupt enable */ +#define BTIM_DIER_UDE (1 << 8) /* Bit 8: Update DMA request enable */ + +/* Status register */ + +#define BTIM_SR_UIF (1 << 0) /* Bit 0: Update interrupt flag */ + +/* Event generation register */ + +#define BTIM_EGR_UG (1 << 0) /* Bit 0: Update generation */ + +#endif /* __ARCH_ARM_SRC_STM32F7_CHIP_STM32F76XX77XX_TIM_H */ diff --git a/arch/arm/src/stm32f7/stm32_tim.c b/arch/arm/src/stm32f7/stm32_tim.c index 7605a14a7f..84934db13d 100644 --- a/arch/arm/src/stm32f7/stm32_tim.c +++ b/arch/arm/src/stm32f7/stm32_tim.c @@ -6,8 +6,9 @@ * * With modifications and updates by: * - * Copyright (C) 2011-2012 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Copyright (C) 2016 Gregory Nutt. All rights reserved. + * Authors: Gregory Nutt + * David Sidrane * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions @@ -144,56 +145,101 @@ # undef CONFIG_STM32F7_TIM14 #endif -#if defined(CONFIG_STM32F7_TIM1) +#if defined(CONFIG_STM32F7_TIM1) # if defined(GPIO_TIM1_CH1OUT) ||defined(GPIO_TIM1_CH2OUT)||\ defined(GPIO_TIM1_CH3OUT) ||defined(GPIO_TIM1_CH4OUT) # define HAVE_TIM1_GPIOCONFIG 1 #endif #endif -#if defined(CONFIG_STM32F7_TIM2) +#if defined(CONFIG_STM32F7_TIM2) # if defined(GPIO_TIM2_CH1OUT) ||defined(GPIO_TIM2_CH2OUT)||\ defined(GPIO_TIM2_CH3OUT) ||defined(GPIO_TIM2_CH4OUT) # define HAVE_TIM2_GPIOCONFIG 1 #endif #endif -#if defined(CONFIG_STM32F7_TIM3) +#if defined(CONFIG_STM32F7_TIM3) # if defined(GPIO_TIM3_CH1OUT) ||defined(GPIO_TIM3_CH2OUT)||\ defined(GPIO_TIM3_CH3OUT) ||defined(GPIO_TIM3_CH4OUT) # define HAVE_TIM3_GPIOCONFIG 1 #endif #endif -#if defined(CONFIG_STM32F7_TIM4) +#if defined(CONFIG_STM32F7_TIM4) # if defined(GPIO_TIM4_CH1OUT) ||defined(GPIO_TIM4_CH2OUT)||\ defined(GPIO_TIM4_CH3OUT) ||defined(GPIO_TIM4_CH4OUT) # define HAVE_TIM4_GPIOCONFIG 1 #endif #endif -#if defined(CONFIG_STM32F7_TIM5) +#if defined(CONFIG_STM32F7_TIM5) # if defined(GPIO_TIM5_CH1OUT) ||defined(GPIO_TIM5_CH2OUT)||\ defined(GPIO_TIM5_CH3OUT) ||defined(GPIO_TIM5_CH4OUT) # define HAVE_TIM5_GPIOCONFIG 1 #endif #endif -#if defined(CONFIG_STM32F7_TIM8) +#if defined(CONFIG_STM32F7_TIM8) # if defined(GPIO_TIM8_CH1OUT) ||defined(GPIO_TIM8_CH2OUT)||\ defined(GPIO_TIM8_CH3OUT) ||defined(GPIO_TIM8_CH4OUT) # define HAVE_TIM8_GPIOCONFIG 1 #endif #endif +#if defined(CONFIG_STM32F7_TIM9) +# if defined(GPIO_TIM9_CH1OUT) ||defined(GPIO_TIM9_CH2OUT)||\ + defined(GPIO_TIM9_CH3OUT) ||defined(GPIO_TIM9_CH4OUT) +# define HAVE_TIM9_GPIOCONFIG 1 +#endif +#endif + +#if defined(CONFIG_STM32F7_TIM10) +# if defined(GPIO_TIM10_CH1OUT) ||defined(GPIO_TIM10_CH2OUT)||\ + defined(GPIO_TIM10_CH3OUT) ||defined(GPIO_TIM10_CH4OUT) +# define HAVE_TIM10_GPIOCONFIG 1 +#endif +#endif + +#if defined(CONFIG_STM32F7_TIM11) +# if defined(GPIO_TIM11_CH1OUT) ||defined(GPIO_TIM11_CH2OUT)||\ + defined(GPIO_TIM11_CH3OUT) ||defined(GPIO_TIM11_CH4OUT) +# define HAVE_TIM11_GPIOCONFIG 1 +#endif +#endif + +#if defined(CONFIG_STM32F7_TIM12) +# if defined(GPIO_TIM12_CH1OUT) ||defined(GPIO_TIM12_CH2OUT)||\ + defined(GPIO_TIM12_CH3OUT) ||defined(GPIO_TIM12_CH4OUT) +# define HAVE_TIM12_GPIOCONFIG 1 +#endif +#endif + +#if defined(CONFIG_STM32F7_TIM13) +# if defined(GPIO_TIM13_CH1OUT) ||defined(GPIO_TIM13_CH2OUT)||\ + defined(GPIO_TIM13_CH3OUT) ||defined(GPIO_TIM13_CH4OUT) +# define HAVE_TIM13_GPIOCONFIG 1 +#endif +#endif + +#if defined(CONFIG_STM32F7_TIM14) +# if defined(GPIO_TIM14_CH1OUT) ||defined(GPIO_TIM14_CH2OUT)||\ + defined(GPIO_TIM14_CH3OUT) ||defined(GPIO_TIM14_CH4OUT) +# define HAVE_TIM14_GPIOCONFIG 1 +#endif +#endif /* This module then only compiles if there are enabled timers that are not intended for * some other purpose. */ -#if defined(CONFIG_STM32F7_TIM1) || defined(CONFIG_STM32F7_TIM2) || defined(CONFIG_STM32F7_TIM3) || \ - defined(CONFIG_STM32F7_TIM4) || defined(CONFIG_STM32F7_TIM5) || defined(CONFIG_STM32F7_TIM6) || \ - defined(CONFIG_STM32F7_TIM7) || defined(CONFIG_STM32F7_TIM8) +#if defined(CONFIG_STM32F7_TIM1) || defined(CONFIG_STM32F7_TIM2) || \ + defined(CONFIG_STM32F7_TIM3) || defined(CONFIG_STM32F7_TIM4) || \ + defined(CONFIG_STM32F7_TIM5) || defined(CONFIG_STM32F7_TIM6) || \ + defined(CONFIG_STM32F7_TIM7) || defined(CONFIG_STM32F7_TIM8) || \ + defined(CONFIG_STM32F7_TIM9) || defined(CONFIG_STM32F7_TIM10) || \ + defined(CONFIG_STM32F7_TIM11) || defined(CONFIG_STM32F7_TIM12) || \ + defined(CONFIG_STM32F7_TIM13) || defined(CONFIG_STM32F7_TIM14) /************************************************************************************ * Private Types @@ -311,9 +357,10 @@ static void stm32_tim_gpioconfig(uint32_t cfg, stm32_tim_channel_t mode) static int stm32_tim_setclock(FAR struct stm32_tim_dev_s *dev, uint32_t freq) { + uint32_t freqin; int prescaler; - ASSERT(dev); + DEBUGASSERT(dev != NULL); /* Disable Timer? */ @@ -323,20 +370,96 @@ static int stm32_tim_setclock(FAR struct stm32_tim_dev_s *dev, uint32_t freq) return 0; } -#if STM32F7_NATIM > 0 - if (((struct stm32_tim_priv_s *)dev)->base == STM32_TIM1_BASE || - ((struct stm32_tim_priv_s *)dev)->base == STM32_TIM8_BASE) + /* Get the input clock frequency for this timer. These vary with + * different timer clock sources, MCU-specific timer configuration, and + * board-specific clock configuration. The correct input clock frequency + * must be defined in the board.h header file. + */ + + switch (((struct stm32_tim_priv_s *)dev)->base) { - prescaler = STM32_TIM18_FREQUENCY / freq; - } - else +#ifdef CONFIG_STM32F7_TIM1 + case STM32_TIM1_BASE: + freqin = STM32_APB2_TIM1_CLKIN; + break; #endif - { - prescaler = STM32_TIM27_FREQUENCY / freq; +#ifdef CONFIG_STM32F7_TIM2 + case STM32_TIM2_BASE: + freqin = STM32_APB1_TIM2_CLKIN; + break; +#endif +#ifdef CONFIG_STM32F7_TIM3 + case STM32_TIM3_BASE: + freqin = STM32_APB1_TIM3_CLKIN; + break; +#endif +#ifdef CONFIG_STM32F7_TIM4 + case STM32_TIM4_BASE: + freqin = STM32_APB1_TIM4_CLKIN; + break; +#endif +#ifdef CONFIG_STM32F7_TIM5 + case STM32_TIM5_BASE: + freqin = STM32_APB1_TIM5_CLKIN; + break; +#endif +#ifdef CONFIG_STM32F7_TIM6 + case STM32_TIM6_BASE: + freqin = STM32_APB1_TIM6_CLKIN; + break; +#endif +#ifdef CONFIG_STM32F7_TIM7 + case STM32_TIM7_BASE: + freqin = STM32_APB1_TIM7_CLKIN; + break; +#endif +#ifdef CONFIG_STM32F7_TIM8 + case STM32_TIM8_BASE: + freqin = STM32_APB2_TIM8_CLKIN; + break; +#endif +#ifdef CONFIG_STM32F7_TIM9 + case STM32_TIM9_BASE: + freqin = STM32_APB2_TIM9_CLKIN; + break; +#endif +#ifdef CONFIG_STM32F7_TIM10 + case STM32_TIM10_BASE: + freqin = STM32_APB2_TIM10_CLKIN; + break; +#endif +#ifdef CONFIG_STM32F7_TIM11 + case STM32_TIM11_BASE: + freqin = STM32_APB2_TIM11_CLKIN; + break; +#endif +#ifdef CONFIG_STM32F7_TIM12 + case STM32_TIM12_BASE: + freqin = STM32_APB1_TIM12_CLKIN; + break; +#endif +#ifdef CONFIG_STM32F7_TIM13 + case STM32_TIM13_BASE: + freqin = STM32_APB1_TIM13_CLKIN; + break; +#endif +#ifdef CONFIG_STM32F7_TIM14 + case STM32_TIM14_BASE: + freqin = STM32_APB1_TIM14_CLKIN; + break; +#endif + default: + return -EINVAL; } - /* We need to decrement value for '1', but only, if we are allowed to - * not to cause underflow. Check for overflow. + /* Select a pre-scaler value for this timer using the input clock + * frequency. + */ + + prescaler = freqin / freq; + + /* We need to decrement value for '1', but only, if that will not to + * cause underflow. */ if (prescaler > 0) @@ -344,6 +467,8 @@ static int stm32_tim_setclock(FAR struct stm32_tim_dev_s *dev, uint32_t freq) prescaler--; } + /* Check for overflow as well. */ + if (prescaler > 0xffff) { prescaler = 0xffff; @@ -358,7 +483,7 @@ static int stm32_tim_setclock(FAR struct stm32_tim_dev_s *dev, uint32_t freq) static void stm32_tim_setperiod(FAR struct stm32_tim_dev_s *dev, uint32_t period) { - ASSERT(dev); + DEBUGASSERT(dev != NULL); stm32_putreg32(dev, STM32_BTIM_ARR_OFFSET, period); } @@ -368,11 +493,16 @@ static int stm32_tim_setisr(FAR struct stm32_tim_dev_s *dev, { int vectorno; - ASSERT(dev); - ASSERT(source == 0); + DEBUGASSERT(dev != NULL); + DEBUGASSERT(source == 0); switch (((struct stm32_tim_priv_s *)dev)->base) { +#ifdef CONFIG_STM32F7_TIM1 + case STM32_TIM1_BASE: + vectorno = STM32_IRQ_TIM1UP; + break; +#endif #ifdef CONFIG_STM32F7_TIM2 case STM32_TIM2_BASE: vectorno = STM32_IRQ_TIM2; @@ -393,36 +523,54 @@ static int stm32_tim_setisr(FAR struct stm32_tim_dev_s *dev, vectorno = STM32_IRQ_TIM5; break; #endif -#if STM32F7_NBTIM > 0 #ifdef CONFIG_STM32F7_TIM6 case STM32_TIM6_BASE: vectorno = STM32_IRQ_TIM6; break; #endif -#endif -#if STM32F7_NBTIM > 1 #ifdef CONFIG_STM32F7_TIM7 case STM32_TIM7_BASE: vectorno = STM32_IRQ_TIM7; break; #endif -#endif -#if STM32F7_NATIM > 0 - /* TODO: add support for multiple sources and callbacks */ - -#ifdef CONFIG_STM32F7_TIM1 - case STM32_TIM1_BASE: - vectorno = STM32_IRQ_TIM1UP; - break; -#endif #ifdef CONFIG_STM32F7_TIM8 case STM32_TIM8_BASE: vectorno = STM32_IRQ_TIM8UP; break; #endif +#ifdef CONFIG_STM32F7_TIM9 + case STM32_TIM9_BASE: + vectorno = STM32_IRQ_TIM9; + break; #endif +#ifdef CONFIG_STM32F7_TIM10 + case STM32_TIM10_BASE: + vectorno = STM32_IRQ_TIM10; + break; +#endif +#ifdef CONFIG_STM32F7_TIM11 + case STM32_TIM11_BASE: + vectorno = STM32_IRQ_TIM11; + break; +#endif +#ifdef CONFIG_STM32F7_TIM12 + case STM32_TIM12_BASE: + vectorno = STM32_IRQ_TIM12; + break; +#endif +#ifdef CONFIG_STM32F7_TIM13 + case STM32_TIM13_BASE: + vectorno = STM32_IRQ_TIM13; + break; +#endif +#ifdef CONFIG_STM32F7_TIM14 + case STM32_TIM14_BASE: + vectorno = STM32_IRQ_TIM14; + break; +#endif + default: - return ERROR; + return -EINVAL; } /* Disable interrupt when callback is removed */ @@ -450,13 +598,13 @@ static int stm32_tim_setisr(FAR struct stm32_tim_dev_s *dev, static void stm32_tim_enableint(FAR struct stm32_tim_dev_s *dev, int source) { - ASSERT(dev); + DEBUGASSERT(dev != NULL); stm32_modifyreg16(dev, STM32_BTIM_DIER_OFFSET, 0, ATIM_DIER_UIE); } static void stm32_tim_disableint(FAR struct stm32_tim_dev_s *dev, int source) { - ASSERT(dev); + DEBUGASSERT(dev != NULL); stm32_modifyreg16(dev, STM32_BTIM_DIER_OFFSET, ATIM_DIER_UIE, 0); } @@ -473,24 +621,17 @@ static int stm32_tim_setmode(FAR struct stm32_tim_dev_s *dev, stm32_tim_mode_t m { uint16_t val = ATIM_CR1_CEN | ATIM_CR1_ARPE; - ASSERT(dev); + DEBUGASSERT(dev != NULL); /* This function is not supported on basic timers. To enable or * disable it, simply set its clock to valid frequency or zero. */ -#if STM32F7_NBTIM > 0 - if (((struct stm32_tim_priv_s *)dev)->base == STM32_TIM6_BASE -#endif -#if STM32F7_NBTIM > 1 - || ((struct stm32_tim_priv_s *)dev)->base == STM32_TIM7_BASE -#endif -#if STM32F7_NBTIM > 0 - ) + if (((struct stm32_tim_priv_s *)dev)->base == STM32_TIM6_BASE || \ + ((struct stm32_tim_priv_s *)dev)->base == STM32_TIM7_BASE) { - return ERROR; + return -EINVAL; } -#endif /* Decode operational modes */ @@ -516,13 +657,12 @@ static int stm32_tim_setmode(FAR struct stm32_tim_dev_s *dev, stm32_tim_mode_t m break; default: - return ERROR; + return -EINVAL; } stm32_tim_reload_counter(dev); stm32_putreg16(dev, STM32_BTIM_CR1_OFFSET, val); -#if STM32F7_NATIM > 0 /* Advanced registers require Main Output Enable */ if (((struct stm32_tim_priv_s *)dev)->base == STM32_TIM1_BASE || @@ -530,7 +670,6 @@ static int stm32_tim_setmode(FAR struct stm32_tim_dev_s *dev, stm32_tim_mode_t m { stm32_modifyreg16(dev, STM32_ATIM_BDTR_OFFSET, 0, ATIM_BDTR_MOE); } -#endif return OK; } @@ -544,13 +683,13 @@ static int stm32_tim_setchannel(FAR struct stm32_tim_dev_s *dev, uint8_t channel uint16_t ccer_val = stm32_getreg16(dev, STM32_GTIM_CCER_OFFSET); uint8_t ccmr_offset = STM32_GTIM_CCMR1_OFFSET; - ASSERT(dev); + DEBUGASSERT(dev != NULL); /* Further we use range as 0..3; if channel=0 it will also overflow here */ if (--channel > 4) { - return ERROR; + return -EINVAL; } /* Assume that channel is disabled and polarity is active high */ @@ -561,18 +700,12 @@ static int stm32_tim_setchannel(FAR struct stm32_tim_dev_s *dev, uint8_t channel * disable it, simply set its clock to valid frequency or zero. */ -#if STM32F7_NBTIM > 0 - if (((struct stm32_tim_priv_s *)dev)->base == STM32_TIM6_BASE -#endif -#if STM32F7_NBTIM > 1 - || ((struct stm32_tim_priv_s *)dev)->base == STM32_TIM7_BASE -#endif -#if STM32F7_NBTIM > 0 - ) + if (((struct stm32_tim_priv_s *)dev)->base == STM32_TIM6_BASE || \ + ((struct stm32_tim_priv_s *)dev)->base == STM32_TIM7_BASE) { - return ERROR; + return -EINVAL; } -#endif + /* Decode configuration */ @@ -587,7 +720,7 @@ static int stm32_tim_setchannel(FAR struct stm32_tim_dev_s *dev, uint8_t channel break; default: - return ERROR; + return -EINVAL; } /* Set polarity */ @@ -620,32 +753,57 @@ static int stm32_tim_setchannel(FAR struct stm32_tim_dev_s *dev, uint8_t channel switch (((struct stm32_tim_priv_s *)dev)->base) { +#ifdef CONFIG_STM32F7_TIM1 + case STM32_TIM1_BASE: + switch (channel) + { +# if defined(GPIO_TIM1_CH1OUT) + case 0: + stm32_tim_gpioconfig(GPIO_TIM1_CH1OUT, mode); break; +# endif +# if defined(GPIO_TIM1_CH2OUT) + case 1: + stm32_tim_gpioconfig(GPIO_TIM1_CH2OUT, mode); break; +# endif +# if defined(GPIO_TIM1_CH3OUT) + case 2: + stm32_tim_gpioconfig(GPIO_TIM1_CH3OUT, mode); break; +# endif +# if defined(GPIO_TIM1_CH4OUT) + case 3: + stm32_tim_gpioconfig(GPIO_TIM1_CH4OUT, mode); break; +# endif + default: + return -EINVAL; + } + break; +#endif #ifdef CONFIG_STM32F7_TIM2 case STM32_TIM2_BASE: switch (channel) { -#if defined(GPIO_TIM2_CH1OUT) +# if defined(GPIO_TIM2_CH1OUT) case 0: stm32_tim_gpioconfig(GPIO_TIM2_CH1OUT, mode); break; -#endif -#if defined(GPIO_TIM2_CH2OUT) +# endif +# if defined(GPIO_TIM2_CH2OUT) case 1: stm32_tim_gpioconfig(GPIO_TIM2_CH2OUT, mode); break; -#endif -#if defined(GPIO_TIM2_CH3OUT) +# endif +# if defined(GPIO_TIM2_CH3OUT) case 2: stm32_tim_gpioconfig(GPIO_TIM2_CH3OUT, mode); break; -#endif -#if defined(GPIO_TIM2_CH4OUT) +# endif +# if defined(GPIO_TIM2_CH4OUT) case 3: stm32_tim_gpioconfig(GPIO_TIM2_CH4OUT, mode); break; #endif default: - return ERROR; + return -EINVAL; } break; #endif @@ -653,28 +811,28 @@ static int stm32_tim_setchannel(FAR struct stm32_tim_dev_s *dev, uint8_t channel case STM32_TIM3_BASE: switch (channel) { -#if defined(GPIO_TIM3_CH1OUT) +# if defined(GPIO_TIM3_CH1OUT) case 0: stm32_tim_gpioconfig(GPIO_TIM3_CH1OUT, mode); break; -#endif -#if defined(GPIO_TIM3_CH2OUT) +# endif +# if defined(GPIO_TIM3_CH2OUT) case 1: stm32_tim_gpioconfig(GPIO_TIM3_CH2OUT, mode); break; -#endif -#if defined(GPIO_TIM3_CH3OUT) +# endif +# if defined(GPIO_TIM3_CH3OUT) case 2: stm32_tim_gpioconfig(GPIO_TIM3_CH3OUT, mode); break; -#endif -#if defined(GPIO_TIM3_CH4OUT) +# endif +# if defined(GPIO_TIM3_CH4OUT) case 3: stm32_tim_gpioconfig(GPIO_TIM3_CH4OUT, mode); break; #endif default: - return ERROR; + return -EINVAL; } break; #endif @@ -682,28 +840,28 @@ static int stm32_tim_setchannel(FAR struct stm32_tim_dev_s *dev, uint8_t channel case STM32_TIM4_BASE: switch (channel) { -#if defined(GPIO_TIM4_CH1OUT) +# if defined(GPIO_TIM4_CH1OUT) case 0: stm32_tim_gpioconfig(GPIO_TIM4_CH1OUT, mode); break; -#endif -#if defined(GPIO_TIM4_CH2OUT) +# endif +# if defined(GPIO_TIM4_CH2OUT) case 1: stm32_tim_gpioconfig(GPIO_TIM4_CH2OUT, mode); break; -#endif -#if defined(GPIO_TIM4_CH3OUT) +# endif +# if defined(GPIO_TIM4_CH3OUT) case 2: stm32_tim_gpioconfig(GPIO_TIM4_CH3OUT, mode); break; -#endif -#if defined(GPIO_TIM4_CH4OUT) +# endif +# if defined(GPIO_TIM4_CH4OUT) case 3: stm32_tim_gpioconfig(GPIO_TIM4_CH4OUT, mode); break; -#endif +# endif default: - return ERROR; + return -EINVAL; } break; #endif @@ -711,55 +869,28 @@ static int stm32_tim_setchannel(FAR struct stm32_tim_dev_s *dev, uint8_t channel case STM32_TIM5_BASE: switch (channel) { -#if defined(GPIO_TIM5_CH1OUT) +# if defined(GPIO_TIM5_CH1OUT) case 0: stm32_tim_gpioconfig(GPIO_TIM5_CH1OUT, mode); break; -#endif -#if defined(GPIO_TIM5_CH2OUT) +# endif +# if defined(GPIO_TIM5_CH2OUT) case 1: stm32_tim_gpioconfig(GPIO_TIM5_CH2OUT, mode); break; -#endif -#if defined(GPIO_TIM5_CH3OUT) +# endif +# if defined(GPIO_TIM5_CH3OUT) case 2: stm32_tim_gpioconfig(GPIO_TIM5_CH3OUT, mode); break; -#endif -#if defined(GPIO_TIM5_CH4OUT) +# endif +# if defined(GPIO_TIM5_CH4OUT) case 3: stm32_tim_gpioconfig(GPIO_TIM5_CH4OUT, mode); break; -#endif +# endif default: - return ERROR; - } - break; -#endif - -#if STM32F7_NATIM > 0 -#ifdef CONFIG_STM32F7_TIM1 - case STM32_TIM1_BASE: - switch (channel) - { -#if defined(GPIO_TIM1_CH1OUT) - case 0: - stm32_tim_gpioconfig(GPIO_TIM1_CH1OUT, mode); break; -#endif -#if defined(GPIO_TIM1_CH2OUT) - case 1: - stm32_tim_gpioconfig(GPIO_TIM1_CH2OUT, mode); break; -#endif -#if defined(GPIO_TIM1_CH3OUT) - case 2: - stm32_tim_gpioconfig(GPIO_TIM1_CH3OUT, mode); break; -#endif -#if defined(GPIO_TIM1_CH4OUT) - case 3: - stm32_tim_gpioconfig(GPIO_TIM1_CH4OUT, mode); break; -#endif - default: - return ERROR; + return -EINVAL; } break; #endif @@ -767,39 +898,209 @@ static int stm32_tim_setchannel(FAR struct stm32_tim_dev_s *dev, uint8_t channel case STM32_TIM8_BASE: switch (channel) { -#if defined(GPIO_TIM8_CH1OUT) +# if defined(GPIO_TIM8_CH1OUT) case 0: stm32_tim_gpioconfig(GPIO_TIM8_CH1OUT, mode); break; -#endif -#if defined(GPIO_TIM8_CH2OUT) +# endif +# if defined(GPIO_TIM8_CH2OUT) case 1: stm32_tim_gpioconfig(GPIO_TIM8_CH2OUT, mode); break; -#endif -#if defined(GPIO_TIM8_CH3OUT) +# endif +# if defined(GPIO_TIM8_CH3OUT) case 2: stm32_tim_gpioconfig(GPIO_TIM8_CH3OUT, mode); break; -#endif -#if defined(GPIO_TIM8_CH4OUT) +# endif +# if defined(GPIO_TIM8_CH4OUT) case 3: stm32_tim_gpioconfig(GPIO_TIM8_CH4OUT, mode); break; -#endif +# endif default: - return ERROR; + return -EINVAL; } break; #endif -#endif +# ifdef CONFIG_STM32F7_TIM9 + case STM32_TIM9_BASE: + switch (channel) + { +# if defined(GPIO_TIM9_CH1OUT) + case 0: + stm32_tim_gpioconfig(GPIO_TIM9_CH1OUT, mode); + break; +# endif +# if defined(GPIO_TIM9_CH2OUT) + case 1: + stm32_tim_gpioconfig(GPIO_TIM9_CH2OUT, mode); + break; +# endif +# if defined(GPIO_TIM9_CH3OUT) + case 2: + stm32_tim_gpioconfig(GPIO_TIM9_CH3OUT, mode); + break; +# endif +# if defined(GPIO_TIM9_CH4OUT) + case 3: + stm32_tim_gpioconfig(GPIO_TIM9_CH4OUT, mode); + break; +# endif default: - return ERROR; + return -EINVAL; + } + break; +#endif +#ifdef CONFIG_STM32F7_TIM10 + case STM32_TIM10_BASE: + switch (channel) + { +# if defined(GPIO_TIM10_CH1OUT) + case 0: + stm32_tim_gpioconfig(GPIO_TIM10_CH1OUT, mode); + break; +# endif +# if defined(GPIO_TIM10_CH2OUT) + case 1: + stm32_tim_gpioconfig(GPIO_TIM10_CH2OUT, mode); + break; +# endif +# if defined(GPIO_TIM10_CH3OUT) + case 2: + stm32_tim_gpioconfig(GPIO_TIM10_CH3OUT, mode); + break; +# endif +# if defined(GPIO_TIM10_CH4OUT) + case 3: + stm32_tim_gpioconfig(GPIO_TIM10_CH4OUT, mode); + break; +# endif + default: + return -EINVAL; + } + break; +#endif +#ifdef CONFIG_STM32F7_TIM11 + case STM32_TIM11_BASE: + switch (channel) + { +# if defined(GPIO_TIM11_CH1OUT) + case 0: + stm32_tim_gpioconfig(GPIO_TIM11_CH1OUT, mode); + break; +# endif +# if defined(GPIO_TIM11_CH2OUT) + case 1: + stm32_tim_gpioconfig(GPIO_TIM11_CH2OUT, mode); + break; +# endif +# if defined(GPIO_TIM11_CH3OUT) + case 2: + stm32_tim_gpioconfig(GPIO_TIM11_CH3OUT, mode); + break; +# endif +# if defined(GPIO_TIM11_CH4OUT) + case 3: + stm32_tim_gpioconfig(GPIO_TIM11_CH4OUT, mode); + break; +# endif + default: + return -EINVAL; + } + break; +#endif +#ifdef CONFIG_STM32F7_TIM12 + case STM32_TIM12_BASE: + switch (channel) + { +# if defined(GPIO_TIM12_CH1OUT) + case 0: + stm32_tim_gpioconfig(GPIO_TIM12_CH1OUT, mode); + break; +# endif +# if defined(GPIO_TIM12_CH2OUT) + case 1: + stm32_tim_gpioconfig(GPIO_TIM12_CH2OUT, mode); + break; +# endif +# if defined(GPIO_TIM12_CH3OUT) + case 2: + stm32_tim_gpioconfig(GPIO_TIM12_CH3OUT, mode); + break; +# endif +# if defined(GPIO_TIM12_CH4OUT) + case 3: + stm32_tim_gpioconfig(GPIO_TIM12_CH4OUT, mode); + break; +# endif + default: + return -EINVAL; + } + break; +#endif +#ifdef CONFIG_STM32F7_TIM13 + case STM32_TIM13_BASE: + switch (channel) + { +# if defined(GPIO_TIM13_CH1OUT) + case 0: + stm32_tim_gpioconfig(GPIO_TIM13_CH1OUT, mode); + break; +# endif +# if defined(GPIO_TIM13_CH2OUT) + case 1: + stm32_tim_gpioconfig(GPIO_TIM13_CH2OUT, mode); + break; +# endif +# if defined(GPIO_TIM13_CH3OUT) + case 2: + stm32_tim_gpioconfig(GPIO_TIM13_CH3OUT, mode); + break; +# endif +# if defined(GPIO_TIM13_CH4OUT) + case 3: + stm32_tim_gpioconfig(GPIO_TIM13_CH4OUT, mode); + break; +# endif + default: + return -EINVAL; + } + break; +#endif +#ifdef CONFIG_STM32F7_TIM14 + case STM32_TIM14_BASE: + switch (channel) + { +# if defined(GPIO_TIM14_CH1OUT) + case 0: + stm32_tim_gpioconfig(GPIO_TIM14_CH1OUT, mode); + break; +# endif +# if defined(GPIO_TIM14_CH2OUT) + case 1: + stm32_tim_gpioconfig(GPIO_TIM14_CH2OUT, mode); + break; +# endif +# if defined(GPIO_TIM14_CH3OUT) + case 2: + stm32_tim_gpioconfig(GPIO_TIM14_CH3OUT, mode); + break; +# endif +# if defined(GPIO_TIM14_CH4OUT) + case 3: + stm32_tim_gpioconfig(GPIO_TIM14_CH4OUT, mode); + break; +# endif + default: + return -EINVAL; + } + break; +#endif } - return OK; } static int stm32_tim_setcompare(FAR struct stm32_tim_dev_s *dev, uint8_t channel, uint32_t compare) { - ASSERT(dev); + DEBUGASSERT(dev != NULL); switch (channel) { @@ -816,14 +1117,14 @@ static int stm32_tim_setcompare(FAR struct stm32_tim_dev_s *dev, uint8_t channel stm32_putreg32(dev, STM32_GTIM_CCR4_OFFSET, compare); break; default: - return ERROR; + return -EINVAL; } return OK; } static int stm32_tim_getcapture(FAR struct stm32_tim_dev_s *dev, uint8_t channel) { - ASSERT(dev); + DEBUGASSERT(dev != NULL); switch (channel) { @@ -837,7 +1138,7 @@ static int stm32_tim_getcapture(FAR struct stm32_tim_dev_s *dev, uint8_t channel return stm32_getreg32(dev, STM32_GTIM_CCR4_OFFSET); } - return ERROR; + return -EINVAL; } /************************************************************************************ @@ -864,6 +1165,14 @@ struct stm32_tim_ops_s stm32_tim_ops = .ackint = &stm32_tim_ackint }; +#ifdef CONFIG_STM32F7_TIM1 +struct stm32_tim_priv_s stm32_tim1_priv = +{ + .ops = &stm32_tim_ops, + .mode = STM32_TIM_MODE_UNUSED, + .base = STM32_TIM1_BASE, +}; +#endif #ifdef CONFIG_STM32F7_TIM2 struct stm32_tim_priv_s stm32_tim2_priv = { @@ -900,7 +1209,6 @@ struct stm32_tim_priv_s stm32_tim5_priv = }; #endif -#if STM32F7_NBTIM > 0 #ifdef CONFIG_STM32F7_TIM6 struct stm32_tim_priv_s stm32_tim6_priv = { @@ -909,9 +1217,7 @@ struct stm32_tim_priv_s stm32_tim6_priv = .base = STM32_TIM6_BASE, }; #endif -#endif -#if STM32F7_NBTIM > 1 #ifdef CONFIG_STM32F7_TIM7 struct stm32_tim_priv_s stm32_tim7_priv = { @@ -920,18 +1226,6 @@ struct stm32_tim_priv_s stm32_tim7_priv = .base = STM32_TIM7_BASE, }; #endif -#endif - -#if STM32F7_NATIM > 0 - -#ifdef CONFIG_STM32F7_TIM1 -struct stm32_tim_priv_s stm32_tim1_priv = -{ - .ops = &stm32_tim_ops, - .mode = STM32_TIM_MODE_UNUSED, - .base = STM32_TIM1_BASE, -}; -#endif #ifdef CONFIG_STM32F7_TIM8 struct stm32_tim_priv_s stm32_tim8_priv = @@ -942,8 +1236,61 @@ struct stm32_tim_priv_s stm32_tim8_priv = }; #endif +#ifdef CONFIG_STM32F7_TIM9 +struct stm32_tim_priv_s stm32_tim9_priv = +{ + .ops = &stm32_tim_ops, + .mode = STM32_TIM_MODE_UNUSED, + .base = STM32_TIM9_BASE, +}; #endif +#ifdef CONFIG_STM32F7_TIM10 +struct stm32_tim_priv_s stm32_tim10_priv = +{ + .ops = &stm32_tim_ops, + .mode = STM32_TIM_MODE_UNUSED, + .base = STM32_TIM10_BASE, +}; +#endif + +#ifdef CONFIG_STM32F7_TIM11 +struct stm32_tim_priv_s stm32_tim11_priv = +{ + .ops = &stm32_tim_ops, + .mode = STM32_TIM_MODE_UNUSED, + .base = STM32_TIM11_BASE, +}; +#endif + +#ifdef CONFIG_STM32F7_TIM12 +struct stm32_tim_priv_s stm32_tim12_priv = +{ + .ops = &stm32_tim_ops, + .mode = STM32_TIM_MODE_UNUSED, + .base = STM32_TIM12_BASE, +}; +#endif + +#ifdef CONFIG_STM32F7_TIM13 +struct stm32_tim_priv_s stm32_tim13_priv = +{ + .ops = &stm32_tim_ops, + .mode = STM32_TIM_MODE_UNUSED, + .base = STM32_TIM13_BASE, +}; +#endif + +#ifdef CONFIG_STM32F7_TIM14 +struct stm32_tim_priv_s stm32_tim14_priv = +{ + .ops = &stm32_tim_ops, + .mode = STM32_TIM_MODE_UNUSED, + .base = STM32_TIM14_BASE, +}; +#endif + + /************************************************************************************ * Public Function - Initialization ************************************************************************************/ @@ -956,6 +1303,12 @@ FAR struct stm32_tim_dev_s *stm32_tim_init(int timer) switch (timer) { +#ifdef CONFIG_STM32F7_TIM1 + case 1: + dev = (struct stm32_tim_dev_s *)&stm32_tim1_priv; + modifyreg32(STM32_RCC_APB2ENR, 0, RCC_APB2ENR_TIM1EN); + break; +#endif #ifdef CONFIG_STM32F7_TIM2 case 2: dev = (struct stm32_tim_dev_s *)&stm32_tim2_priv; @@ -980,37 +1333,59 @@ FAR struct stm32_tim_dev_s *stm32_tim_init(int timer) modifyreg32(STM32_RCC_APB1ENR, 0, RCC_APB1ENR_TIM5EN); break; #endif - -#if STM32F7_NBTIM > 0 #ifdef CONFIG_STM32F7_TIM6 case 6: dev = (struct stm32_tim_dev_s *)&stm32_tim6_priv; modifyreg32(STM32_RCC_APB1ENR, 0, RCC_APB1ENR_TIM6EN); break; #endif -#endif -#if STM32F7_NBTIM > 1 #ifdef CONFIG_STM32F7_TIM7 case 7: dev = (struct stm32_tim_dev_s *)&stm32_tim7_priv; modifyreg32(STM32_RCC_APB1ENR, 0, RCC_APB1ENR_TIM7EN); break; #endif -#endif - -#if STM32F7_NATIM > 0 -#ifdef CONFIG_STM32F7_TIM1 - case 1: - dev = (struct stm32_tim_dev_s *)&stm32_tim1_priv; - modifyreg32(STM32_RCC_APB2ENR, 0, RCC_APB2ENR_TIM1EN); - break; -#endif #ifdef CONFIG_STM32F7_TIM8 case 8: dev = (struct stm32_tim_dev_s *)&stm32_tim8_priv; modifyreg32(STM32_RCC_APB2ENR, 0, RCC_APB2ENR_TIM8EN); break; #endif +#ifdef CONFIG_STM32F7_TIM9 + case 9: + dev = (struct stm32_tim_dev_s *)&stm32_tim9_priv; + modifyreg32(STM32_RCC_APB2ENR, 0, RCC_APB2ENR_TIM9EN); + break; +#endif +#ifdef CONFIG_STM32F7_TIM10 + case 10: + dev = (struct stm32_tim_dev_s *)&stm32_tim10_priv; + modifyreg32(STM32_RCC_APB2ENR, 0, RCC_APB2ENR_TIM10EN); + break; +#endif +#ifdef CONFIG_STM32F7_TIM11 + case 11: + dev = (struct stm32_tim_dev_s *)&stm32_tim11_priv; + modifyreg32(STM32_RCC_APB2ENR, 0, RCC_APB2ENR_TIM11EN); + break; +#endif +#ifdef CONFIG_STM32F7_TIM12 + case 12: + dev = (struct stm32_tim_dev_s *)&stm32_tim12_priv; + modifyreg32(STM32_RCC_APB1ENR, 0, RCC_APB1ENR_TIM12EN); + break; +#endif +#ifdef CONFIG_STM32F7_TIM13 + case 13: + dev = (struct stm32_tim_dev_s *)&stm32_tim13_priv; + modifyreg32(STM32_RCC_APB1ENR, 0, RCC_APB1ENR_TIM13EN); + break; +#endif +#ifdef CONFIG_STM32F7_TIM14 + case 14: + dev = (struct stm32_tim_dev_s *)&stm32_tim14_priv; + modifyreg32(STM32_RCC_APB1ENR, 0, RCC_APB1ENR_TIM14EN); + break; #endif default: return NULL; @@ -1032,12 +1407,17 @@ FAR struct stm32_tim_dev_s *stm32_tim_init(int timer) int stm32_tim_deinit(FAR struct stm32_tim_dev_s * dev) { - ASSERT(dev); + DEBUGASSERT(dev != NULL); /* Disable power */ switch (((struct stm32_tim_priv_s *)dev)->base) { +#ifdef CONFIG_STM32F7_TIM1 + case STM32_TIM1_BASE: + modifyreg32(STM32_RCC_APB2ENR, RCC_APB2ENR_TIM1EN, 0); + break; +#endif #ifdef CONFIG_STM32F7_TIM2 case STM32_TIM2_BASE: modifyreg32(STM32_RCC_APB1ENR, RCC_APB1ENR_TIM2EN, 0); @@ -1058,35 +1438,53 @@ int stm32_tim_deinit(FAR struct stm32_tim_dev_s * dev) modifyreg32(STM32_RCC_APB1ENR, RCC_APB1ENR_TIM5EN, 0); break; #endif -#if STM32F7_NBTIM > 0 #ifdef CONFIG_STM32F7_TIM6 case STM32_TIM6_BASE: modifyreg32(STM32_RCC_APB1ENR, RCC_APB1ENR_TIM6EN, 0); break; #endif -#endif -#if STM32F7_NBTIM > 1 #ifdef CONFIG_STM32F7_TIM7 case STM32_TIM7_BASE: modifyreg32(STM32_RCC_APB1ENR, RCC_APB1ENR_TIM7EN, 0); break; #endif -#endif - -#if STM32F7_NATIM > 0 -#ifdef CONFIG_STM32F7_TIM1 - case STM32_TIM1_BASE: - modifyreg32(STM32_RCC_APB2ENR, RCC_APB2ENR_TIM1EN, 0); - break; -#endif #ifdef CONFIG_STM32F7_TIM8 case STM32_TIM8_BASE: modifyreg32(STM32_RCC_APB2ENR, RCC_APB2ENR_TIM8EN, 0); break; #endif +#ifdef CONFIG_STM32F7_TIM9 + case STM32_TIM9_BASE: + modifyreg32(STM32_RCC_APB2ENR, RCC_APB2ENR_TIM9EN, 0); + break; +#endif +#ifdef CONFIG_STM32F7_TIM10 + case STM32_TIM10_BASE: + modifyreg32(STM32_RCC_APB2ENR, RCC_APB2ENR_TIM10EN, 0); + break; +#endif +#ifdef CONFIG_STM32F7_TIM11 + case STM32_TIM11_BASE: + modifyreg32(STM32_RCC_APB2ENR, RCC_APB2ENR_TIM11EN, 0); + break; +#endif +#ifdef CONFIG_STM32F7_TIM12 + case STM32_TIM12_BASE: + modifyreg32(STM32_RCC_APB1ENR, RCC_APB1ENR_TIM12EN, 0); + break; +#endif +#ifdef CONFIG_STM32F7_TIM13 + case STM32_TIM13_BASE: + modifyreg32(STM32_RCC_APB1ENR, RCC_APB1ENR_TIM13EN, 0); + break; +#endif +#ifdef CONFIG_STM32F7_TIM14 + case STM32_TIM14_BASE: + modifyreg32(STM32_RCC_APB1ENR, RCC_APB1ENR_TIM14EN, 0); + break; #endif default: - return ERROR; + return -EINVAL; } /* Mark it as free */ From 49de80909661e321f4a4399a20120da363f1211e Mon Sep 17 00:00:00 2001 From: David Sidrane Date: Thu, 16 Jun 2016 12:47:21 -1000 Subject: [PATCH 61/75] Proper ADC and Timer Control --- arch/arm/src/stm32f7/Kconfig | 2774 +++++++++++++++++++++++++++++++- arch/arm/src/stm32f7/Make.defs | 4 +- 2 files changed, 2770 insertions(+), 8 deletions(-) diff --git a/arch/arm/src/stm32f7/Kconfig b/arch/arm/src/stm32f7/Kconfig index d41356ea2a..1526d47825 100644 --- a/arch/arm/src/stm32f7/Kconfig +++ b/arch/arm/src/stm32f7/Kconfig @@ -916,6 +916,19 @@ config STM32F7_HAVE_SDMMC2 bool default n +config STM32F7_HAVE_ADC1_DMA + bool + default n + +config STM32F7_HAVE_ADC2_DMA + bool + default n + +config STM32F7_HAVE_ADC3_DMA + bool + default n + + config STM32F7_HAVE_CAN3 bool default n @@ -993,20 +1006,27 @@ config STM32F7_USART # These are the peripheral selections proper + config STM32F7_ADC1 bool "ADC1" default n select STM32F7_ADC + select STM32F7_HAVE_ADC1_DMA if STM32F7_DMA1 + select STM32F7_HAVE_ADC1_DMA if STM32F7_DMA2 config STM32F7_ADC2 bool "ADC2" default n select STM32F7_ADC + depends on STM32F7_HAVE_ADC2 + select STM32F7_HAVE_ADC2_DMA if STM32F7_DMA2 config STM32F7_ADC3 bool "ADC3" default n select STM32F7_ADC + select STM32F7_HAVE_ADC1_DMA if STM32F7_DMA1 + select STM32F7_HAVE_ADC1_DMA if STM32F7_DMA2 config STM32F7_BKPSRAM bool "Enable BKP RAM Domain" @@ -1124,15 +1144,15 @@ config STM32F7_HASH depends on STM32F7_HAVE_HASH select ARCH_HAVE_HASH +config STM32F7_CEC + bool "HDMI-CEC" + default n + config STM32F7_I2C1 bool "I2C1" default n select STM32F7_I2C -config STM32F7_CEC - bool "HDMI-CEC" - default n - config STM32F7_I2C2 bool "I2C2" default n @@ -1664,14 +1684,2756 @@ config STM32F7_DTCM_PROCFS config STM32F7_DMACAPABLE bool "Workaround non-DMA capable memory" depends on ARCH_DMA - default y if !STM32_CCMEXCLUDE - default n if STM32_CCMEXCLUDE + default y if !STM32F7_CCMEXCLUDE + default n if STM32F7_CCMEXCLUDE ---help--- This option enables the DMA interface stm32_dmacapable that can be used to check if it is possible to do DMA from the selected address. Drivers then may use this information to determine if they should attempt the DMA or fall back to a different transfer method. +menu "Timer Configuration" + +config STM32F7_TIM1_PWM + bool "TIM1 PWM" + default n + depends on STM32F7_TIM1 + select ARCH_HAVE_PWM_PULSECOUNT + ---help--- + Reserve timer 1 for use by PWM + + Timer devices may be used for different purposes. One special purpose is + to generate modulated outputs for such things as motor control. If STM32F7_TIM1 + is defined then THIS following may also be defined to indicate that + the timer is intended to be used for pulsed output modulation. + +if STM32F7_TIM1_PWM + +config STM32F7_TIM1_MODE + int "TIM1 Mode" + default 0 + range 0 4 + ---help--- + Specifies the timer mode. + +if STM32F7_PWM_MULTICHAN + +config STM32F7_TIM1_CHANNEL1 + bool "TIM1 Channel 1" + default n + ---help--- + Enables channel 1. + +if STM32F7_TIM1_CHANNEL1 + +config STM32F7_TIM1_CH1MODE + int "TIM1 Channel 1 Mode" + default 0 + range 0 5 + ---help--- + Specifies the channel mode. + +config STM32F7_TIM1_CH1OUT + bool "TIM1 Channel 1 Output" + default n + ---help--- + Enables channel 1 output. + +endif # STM32F7_TIM1_CHANNEL1 + +config STM32F7_TIM1_CHANNEL2 + bool "TIM1 Channel 2" + default n + ---help--- + Enables channel 2. + +if STM32F7_TIM1_CHANNEL2 + +config STM32F7_TIM1_CH2MODE + int "TIM1 Channel 2 Mode" + default 0 + range 0 5 + ---help--- + Specifies the channel mode. + +config STM32F7_TIM1_CH2OUT + bool "TIM1 Channel 2 Output" + default n + ---help--- + Enables channel 2 output. + +endif # STM32F7_TIM1_CHANNEL2 + +config STM32F7_TIM1_CHANNEL3 + bool "TIM1 Channel 3" + default n + ---help--- + Enables channel 3. + +if STM32F7_TIM1_CHANNEL3 + +config STM32F7_TIM1_CH3MODE + int "TIM1 Channel 3 Mode" + default 0 + range 0 5 + ---help--- + Specifies the channel mode. + +config STM32F7_TIM1_CH3OUT + bool "TIM1 Channel 3 Output" + default n + ---help--- + Enables channel 3 output. + +endif # STM32F7_TIM1_CHANNEL3 + +config STM32F7_TIM1_CHANNEL4 + bool "TIM1 Channel 4" + default n + ---help--- + Enables channel 4. + +if STM32F7_TIM1_CHANNEL4 + +config STM32F7_TIM1_CH4MODE + int "TIM1 Channel 4 Mode" + default 0 + range 0 5 + ---help--- + Specifies the channel mode. + +config STM32F7_TIM1_CH4OUT + bool "TIM1 Channel 4 Output" + default n + ---help--- + Enables channel 4 output. + +endif # STM32F7_TIM1_CHANNEL4 + +endif # STM32F7_PWM_MULTICHAN + +if !STM32F7_PWM_MULTICHAN + +config STM32F7_TIM1_CHANNEL + int "TIM1 PWM Output Channel" + default 1 + range 1 4 + ---help--- + If TIM1 is enabled for PWM usage, you also need specifies the timer output + channel {1,..,4} + +config STM32F7_TIM1_CHMODE + int "TIM1 Channel Mode" + default 0 + range 0 5 + ---help--- + Specifies the channel mode. + +endif # !STM32F7_PWM_MULTICHAN + +endif # STM32F7_TIM1_PWM + +config STM32F7_TIM2_PWM + bool "TIM2 PWM" + default n + depends on STM32F7_TIM2 + select ARCH_HAVE_PWM_PULSECOUNT + ---help--- + Reserve timer 2 for use by PWM + + Timer devices may be used for different purposes. One special purpose is + to generate modulated outputs for such things as motor control. If STM32F7_TIM2 + is defined then THIS following may also be defined to indicate that + the timer is intended to be used for pulsed output modulation. + +if STM32F7_TIM2_PWM + +config STM32F7_TIM2_MODE + int "TIM2 Mode" + default 0 + range 0 4 + ---help--- + Specifies the timer mode. + +if STM32F7_PWM_MULTICHAN + +config STM32F7_TIM2_CHANNEL1 + bool "TIM2 Channel 1" + default n + ---help--- + Enables channel 1. + +if STM32F7_TIM2_CHANNEL1 + +config STM32F7_TIM2_CH1MODE + int "TIM2 Channel 1 Mode" + default 0 + range 0 5 + ---help--- + Specifies the channel mode. + +config STM32F7_TIM2_CH1OUT + bool "TIM2 Channel 1 Output" + default n + ---help--- + Enables channel 1 output. + +endif # STM32F7_TIM2_CHANNEL1 + +config STM32F7_TIM2_CHANNEL2 + bool "TIM2 Channel 2" + default n + ---help--- + Enables channel 2. + +if STM32F7_TIM2_CHANNEL2 + +config STM32F7_TIM2_CH2MODE + int "TIM2 Channel 2 Mode" + default 0 + range 0 5 + ---help--- + Specifies the channel mode. + +config STM32F7_TIM2_CH2OUT + bool "TIM2 Channel 2 Output" + default n + ---help--- + Enables channel 2 output. + +endif # STM32F7_TIM2_CHANNEL2 + +config STM32F7_TIM2_CHANNEL3 + bool "TIM2 Channel 3" + default n + ---help--- + Enables channel 3. + +if STM32F7_TIM2_CHANNEL3 + +config STM32F7_TIM2_CH3MODE + int "TIM2 Channel 3 Mode" + default 0 + range 0 5 + ---help--- + Specifies the channel mode. + +config STM32F7_TIM2_CH3OUT + bool "TIM2 Channel 3 Output" + default n + ---help--- + Enables channel 3 output. + +endif # STM32F7_TIM2_CHANNEL3 + +config STM32F7_TIM2_CHANNEL4 + bool "TIM2 Channel 4" + default n + ---help--- + Enables channel 4. + +if STM32F7_TIM2_CHANNEL4 + +config STM32F7_TIM2_CH4MODE + int "TIM2 Channel 4 Mode" + default 0 + range 0 5 + ---help--- + Specifies the channel mode. + +config STM32F7_TIM2_CH4OUT + bool "TIM2 Channel 4 Output" + default n + ---help--- + Enables channel 4 output. + +endif # STM32F7_TIM2_CHANNEL4 + +endif # STM32F7_PWM_MULTICHAN + +if !STM32F7_PWM_MULTICHAN + +config STM32F7_TIM2_CHANNEL + int "TIM2 PWM Output Channel" + default 1 + range 1 4 + ---help--- + If TIM2 is enabled for PWM usage, you also need specifies the timer output + channel {1,..,4} + +config STM32F7_TIM2_CHMODE + int "TIM2 Channel Mode" + default 0 + range 0 5 + ---help--- + Specifies the channel mode. + +endif # !STM32F7_PWM_MULTICHAN + +endif # STM32F7_TIM2_PWM + +config STM32F7_TIM3_PWM + bool "TIM3 PWM" + default n + depends on STM32F7_TIM3 + select ARCH_HAVE_PWM_PULSECOUNT + ---help--- + Reserve timer 3 for use by PWM + + Timer devices may be used for different purposes. One special purpose is + to generate modulated outputs for such things as motor control. If STM32F7_TIM3 + is defined then THIS following may also be defined to indicate that + the timer is intended to be used for pulsed output modulation. + +if STM32F7_TIM3_PWM + +config STM32F7_TIM3_MODE + int "TIM3 Mode" + default 0 + range 0 4 + ---help--- + Specifies the timer mode. + +if STM32F7_PWM_MULTICHAN + +config STM32F7_TIM3_CHANNEL1 + bool "TIM3 Channel 1" + default n + ---help--- + Enables channel 1. + +if STM32F7_TIM3_CHANNEL1 + +config STM32F7_TIM3_CH1MODE + int "TIM3 Channel 1 Mode" + default 0 + range 0 5 + ---help--- + Specifies the channel mode. + +config STM32F7_TIM3_CH1OUT + bool "TIM3 Channel 1 Output" + default n + ---help--- + Enables channel 1 output. + +endif # STM32F7_TIM3_CHANNEL1 + +config STM32F7_TIM3_CHANNEL2 + bool "TIM3 Channel 2" + default n + ---help--- + Enables channel 2. + +if STM32F7_TIM3_CHANNEL2 + +config STM32F7_TIM3_CH2MODE + int "TIM3 Channel 2 Mode" + default 0 + range 0 5 + ---help--- + Specifies the channel mode. + +config STM32F7_TIM3_CH2OUT + bool "TIM3 Channel 2 Output" + default n + ---help--- + Enables channel 2 output. + +endif # STM32F7_TIM3_CHANNEL2 + +config STM32F7_TIM3_CHANNEL3 + bool "TIM3 Channel 3" + default n + ---help--- + Enables channel 3. + +if STM32F7_TIM3_CHANNEL3 + +config STM32F7_TIM3_CH3MODE + int "TIM3 Channel 3 Mode" + default 0 + range 0 5 + ---help--- + Specifies the channel mode. + +config STM32F7_TIM3_CH3OUT + bool "TIM3 Channel 3 Output" + default n + ---help--- + Enables channel 3 output. + +endif # STM32F7_TIM3_CHANNEL3 + +config STM32F7_TIM3_CHANNEL4 + bool "TIM3 Channel 4" + default n + ---help--- + Enables channel 4. + +if STM32F7_TIM3_CHANNEL4 + +config STM32F7_TIM3_CH4MODE + int "TIM3 Channel 4 Mode" + default 0 + range 0 5 + ---help--- + Specifies the channel mode. + +config STM32F7_TIM3_CH4OUT + bool "TIM3 Channel 4 Output" + default n + ---help--- + Enables channel 4 output. + +endif # STM32F7_TIM3_CHANNEL4 + +endif # STM32F7_PWM_MULTICHAN + +if !STM32F7_PWM_MULTICHAN + +config STM32F7_TIM3_CHANNEL + int "TIM3 PWM Output Channel" + default 1 + range 1 4 + ---help--- + If TIM3 is enabled for PWM usage, you also need specifies the timer output + channel {1,..,4} + +config STM32F7_TIM3_CHMODE + int "TIM3 Channel Mode" + default 0 + range 0 5 + ---help--- + Specifies the channel mode. + +endif # !STM32F7_PWM_MULTICHAN + +endif # STM32F7_TIM3_PWM + +config STM32F7_TIM4_PWM + bool "TIM4 PWM" + default n + depends on STM32F7_TIM4 + select ARCH_HAVE_PWM_PULSECOUNT + ---help--- + Reserve timer 4 for use by PWM + + Timer devices may be used for different purposes. One special purpose is + to generate modulated outputs for such things as motor control. If STM32F7_TIM4 + is defined then THIS following may also be defined to indicate that + the timer is intended to be used for pulsed output modulation. + +if STM32F7_TIM4_PWM + +config STM32F7_TIM4_MODE + int "TIM4 Mode" + default 0 + range 0 4 + ---help--- + Specifies the timer mode. + +if STM32F7_PWM_MULTICHAN + +config STM32F7_TIM4_CHANNEL1 + bool "TIM4 Channel 1" + default n + ---help--- + Enables channel 1. + +if STM32F7_TIM4_CHANNEL1 + +config STM32F7_TIM4_CH1MODE + int "TIM4 Channel 1 Mode" + default 0 + range 0 5 + ---help--- + Specifies the channel mode. + +config STM32F7_TIM4_CH1OUT + bool "TIM4 Channel 1 Output" + default n + ---help--- + Enables channel 1 output. + +endif # STM32F7_TIM4_CHANNEL1 + +config STM32F7_TIM4_CHANNEL2 + bool "TIM4 Channel 2" + default n + ---help--- + Enables channel 2. + +if STM32F7_TIM4_CHANNEL2 + +config STM32F7_TIM4_CH2MODE + int "TIM4 Channel 2 Mode" + default 0 + range 0 5 + ---help--- + Specifies the channel mode. + +config STM32F7_TIM4_CH2OUT + bool "TIM4 Channel 2 Output" + default n + ---help--- + Enables channel 2 output. + +endif # STM32F7_TIM4_CHANNEL2 + +config STM32F7_TIM4_CHANNEL3 + bool "TIM4 Channel 3" + default n + ---help--- + Enables channel 3. + +if STM32F7_TIM4_CHANNEL3 + +config STM32F7_TIM4_CH3MODE + int "TIM4 Channel 3 Mode" + default 0 + range 0 5 + ---help--- + Specifies the channel mode. + +config STM32F7_TIM4_CH3OUT + bool "TIM4 Channel 3 Output" + default n + ---help--- + Enables channel 3 output. + +endif # STM32F7_TIM4_CHANNEL3 + +config STM32F7_TIM4_CHANNEL4 + bool "TIM4 Channel 4" + default n + ---help--- + Enables channel 4. + +if STM32F7_TIM4_CHANNEL4 + +config STM32F7_TIM4_CH4MODE + int "TIM4 Channel 4 Mode" + default 0 + range 0 5 + ---help--- + Specifies the channel mode. + +config STM32F7_TIM4_CH4OUT + bool "TIM4 Channel 4 Output" + default n + ---help--- + Enables channel 4 output. + +endif # STM32F7_TIM4_CHANNEL4 + +endif # STM32F7_PWM_MULTICHAN + +if !STM32F7_PWM_MULTICHAN + +config STM32F7_TIM4_CHANNEL + int "TIM4 PWM Output Channel" + default 1 + range 1 4 + ---help--- + If TIM4 is enabled for PWM usage, you also need specifies the timer output + channel {1,..,4} + +config STM32F7_TIM4_CHMODE + int "TIM4 Channel Mode" + default 0 + range 0 5 + ---help--- + Specifies the channel mode. + +endif # !STM32F7_PWM_MULTICHAN + +endif # STM32F7_TIM4_PWM + +config STM32F7_TIM5_PWM + bool "TIM5 PWM" + default n + depends on STM32F7_TIM5 + select ARCH_HAVE_PWM_PULSECOUNT + ---help--- + Reserve timer 5 for use by PWM + + Timer devices may be used for different purposes. One special purpose is + to generate modulated outputs for such things as motor control. If STM32F7_TIM5 + is defined then THIS following may also be defined to indicate that + the timer is intended to be used for pulsed output modulation. + +if STM32F7_TIM5_PWM + +config STM32F7_TIM5_MODE + int "TIM5 Mode" + default 0 + range 0 4 + ---help--- + Specifies the timer mode. + +if STM32F7_PWM_MULTICHAN + +config STM32F7_TIM5_CHANNEL1 + bool "TIM5 Channel 1" + default n + ---help--- + Enables channel 1. + +if STM32F7_TIM5_CHANNEL1 + +config STM32F7_TIM5_CH1MODE + int "TIM5 Channel 1 Mode" + default 0 + range 0 5 + ---help--- + Specifies the channel mode. + +config STM32F7_TIM5_CH1OUT + bool "TIM5 Channel 1 Output" + default n + ---help--- + Enables channel 1 output. + +endif # STM32F7_TIM5_CHANNEL1 + +config STM32F7_TIM5_CHANNEL2 + bool "TIM5 Channel 2" + default n + ---help--- + Enables channel 2. + +if STM32F7_TIM5_CHANNEL2 + +config STM32F7_TIM5_CH2MODE + int "TIM5 Channel 2 Mode" + default 0 + range 0 5 + ---help--- + Specifies the channel mode. + +config STM32F7_TIM5_CH2OUT + bool "TIM5 Channel 2 Output" + default n + ---help--- + Enables channel 2 output. + +endif # STM32F7_TIM5_CHANNEL2 + +config STM32F7_TIM5_CHANNEL3 + bool "TIM5 Channel 3" + default n + ---help--- + Enables channel 3. + +if STM32F7_TIM5_CHANNEL3 + +config STM32F7_TIM5_CH3MODE + int "TIM5 Channel 3 Mode" + default 0 + range 0 5 + ---help--- + Specifies the channel mode. + +config STM32F7_TIM5_CH3OUT + bool "TIM5 Channel 3 Output" + default n + ---help--- + Enables channel 3 output. + +endif # STM32F7_TIM5_CHANNEL3 + +config STM32F7_TIM5_CHANNEL4 + bool "TIM5 Channel 4" + default n + ---help--- + Enables channel 4. + +if STM32F7_TIM5_CHANNEL4 + +config STM32F7_TIM5_CH4MODE + int "TIM5 Channel 4 Mode" + default 0 + range 0 5 + ---help--- + Specifies the channel mode. + +config STM32F7_TIM5_CH4OUT + bool "TIM5 Channel 4 Output" + default n + ---help--- + Enables channel 4 output. + +endif # STM32F7_TIM5_CHANNEL4 + +endif # STM32F7_PWM_MULTICHAN + +if !STM32F7_PWM_MULTICHAN + +config STM32F7_TIM5_CHANNEL + int "TIM5 PWM Output Channel" + default 1 + range 1 4 + ---help--- + If TIM5 is enabled for PWM usage, you also need specifies the timer output + channel {1,..,4} + +config STM32F7_TIM5_CHMODE + int "TIM5 Channel Mode" + default 0 + range 0 5 + ---help--- + Specifies the channel mode. + +endif # !STM32F7_PWM_MULTICHAN + +endif # STM32F7_TIM5_PWM + +config STM32F7_TIM8_PWM + bool "TIM8 PWM" + default n + depends on STM32F7_TIM8 + select ARCH_HAVE_PWM_PULSECOUNT + ---help--- + Reserve timer 8 for use by PWM + + Timer devices may be used for different purposes. One special purpose is + to generate modulated outputs for such things as motor control. If STM32F7_TIM8 + is defined then THIS following may also be defined to indicate that + the timer is intended to be used for pulsed output modulation. + +if STM32F7_TIM8_PWM + +config STM32F7_TIM8_MODE + int "TIM8 Mode" + default 0 + range 0 4 + ---help--- + Specifies the timer mode. + +if STM32F7_PWM_MULTICHAN + +config STM32F7_TIM8_CHANNEL1 + bool "TIM8 Channel 1" + default n + ---help--- + Enables channel 1. + +if STM32F7_TIM8_CHANNEL1 + +config STM32F7_TIM8_CH1MODE + int "TIM8 Channel 1 Mode" + default 0 + range 0 5 + ---help--- + Specifies the channel mode. + +config STM32F7_TIM8_CH1OUT + bool "TIM8 Channel 1 Output" + default n + ---help--- + Enables channel 1 output. + +endif # STM32F7_TIM8_CHANNEL1 + +config STM32F7_TIM8_CHANNEL2 + bool "TIM8 Channel 2" + default n + ---help--- + Enables channel 2. + +if STM32F7_TIM8_CHANNEL2 + +config STM32F7_TIM8_CH2MODE + int "TIM8 Channel 2 Mode" + default 0 + range 0 5 + ---help--- + Specifies the channel mode. + +config STM32F7_TIM8_CH2OUT + bool "TIM8 Channel 2 Output" + default n + ---help--- + Enables channel 2 output. + +endif # STM32F7_TIM8_CHANNEL2 + +config STM32F7_TIM8_CHANNEL3 + bool "TIM8 Channel 3" + default n + ---help--- + Enables channel 3. + +if STM32F7_TIM8_CHANNEL3 + +config STM32F7_TIM8_CH3MODE + int "TIM8 Channel 3 Mode" + default 0 + range 0 5 + ---help--- + Specifies the channel mode. + +config STM32F7_TIM8_CH3OUT + bool "TIM8 Channel 3 Output" + default n + ---help--- + Enables channel 3 output. + +endif # STM32F7_TIM8_CHANNEL3 + +config STM32F7_TIM8_CHANNEL4 + bool "TIM8 Channel 4" + default n + ---help--- + Enables channel 4. + +if STM32F7_TIM8_CHANNEL4 + +config STM32F7_TIM8_CH4MODE + int "TIM8 Channel 4 Mode" + default 0 + range 0 5 + ---help--- + Specifies the channel mode. + +config STM32F7_TIM8_CH4OUT + bool "TIM8 Channel 4 Output" + default n + ---help--- + Enables channel 4 output. + +endif # STM32F7_TIM8_CHANNEL4 + +endif # STM32F7_PWM_MULTICHAN + +if !STM32F7_PWM_MULTICHAN + +config STM32F7_TIM8_CHANNEL + int "TIM8 PWM Output Channel" + default 1 + range 1 4 + ---help--- + If TIM8 is enabled for PWM usage, you also need specifies the timer output + channel {1,..,4} + +config STM32F7_TIM8_CHMODE + int "TIM8 Channel Mode" + default 0 + range 0 5 + ---help--- + Specifies the channel mode. + +endif # !STM32F7_PWM_MULTICHAN + +endif # STM32F7_TIM8_PWM + +config STM32F7_TIM9_PWM + bool "TIM9 PWM" + default n + depends on STM32F7_TIM9 + select ARCH_HAVE_PWM_PULSECOUNT + ---help--- + Reserve timer 9 for use by PWM + + Timer devices may be used for different purposes. One special purpose is + to generate modulated outputs for such things as motor control. If STM32F7_TIM9 + is defined then THIS following may also be defined to indicate that + the timer is intended to be used for pulsed output modulation. + +if STM32F7_TIM9_PWM + +if STM32F7_PWM_MULTICHAN + +config STM32F7_TIM9_CHANNEL1 + bool "TIM9 Channel 1" + default n + ---help--- + Enables channel 1. + +if STM32F7_TIM9_CHANNEL1 + +config STM32F7_TIM9_CH1MODE + int "TIM9 Channel 1 Mode" + default 0 + range 0 5 + ---help--- + Specifies the channel mode. + +config STM32F7_TIM9_CH1OUT + bool "TIM9 Channel 1 Output" + default n + ---help--- + Enables channel 1 output. + +endif # STM32F7_TIM9_CHANNEL1 + +config STM32F7_TIM9_CHANNEL2 + bool "TIM9 Channel 2" + default n + ---help--- + Enables channel 2. + +if STM32F7_TIM9_CHANNEL2 + +config STM32F7_TIM9_CH2MODE + int "TIM9 Channel 2 Mode" + default 0 + range 0 5 + ---help--- + Specifies the channel mode. + +config STM32F7_TIM9_CH2OUT + bool "TIM9 Channel 2 Output" + default n + ---help--- + Enables channel 2 output. + +endif # STM32F7_TIM9_CHANNEL2 + +config STM32F7_TIM9_CHANNEL3 + bool "TIM9 Channel 3" + default n + ---help--- + Enables channel 3. + +if STM32F7_TIM9_CHANNEL3 + +config STM32F7_TIM9_CH3MODE + int "TIM9 Channel 3 Mode" + default 0 + range 0 5 + ---help--- + Specifies the channel mode. + +config STM32F7_TIM9_CH3OUT + bool "TIM9 Channel 3 Output" + default n + ---help--- + Enables channel 3 output. + +endif # STM32F7_TIM9_CHANNEL3 + +config STM32F7_TIM9_CHANNEL4 + bool "TIM9 Channel 4" + default n + ---help--- + Enables channel 4. + +if STM32F7_TIM9_CHANNEL4 + +config STM32F7_TIM9_CH4MODE + int "TIM9 Channel 4 Mode" + default 0 + range 0 5 + ---help--- + Specifies the channel mode. + +config STM32F7_TIM9_CH4OUT + bool "TIM9 Channel 4 Output" + default n + ---help--- + Enables channel 4 output. + +endif # STM32F7_TIM9_CHANNEL4 + +endif # STM32F7_PWM_MULTICHAN + +if !STM32F7_PWM_MULTICHAN + +config STM32F7_TIM9_CHANNEL + int "TIM9 PWM Output Channel" + default 1 + range 1 4 + ---help--- + If TIM9 is enabled for PWM usage, you also need specifies the timer output + channel {1,..,4} + +config STM32F7_TIM9_CHMODE + int "TIM9 Channel Mode" + default 0 + range 0 5 + ---help--- + Specifies the channel mode. + +endif # !STM32F7_PWM_MULTICHAN + +endif # STM32F7_TIM9_PWM + +config STM32F7_TIM10_PWM + bool "TIM10 PWM" + default n + depends on STM32F7_TIM10 + select ARCH_HAVE_PWM_PULSECOUNT + ---help--- + Reserve timer 10 for use by PWM + + Timer devices may be used for different purposes. One special purpose is + to generate modulated outputs for such things as motor control. If STM32F7_TIM10 + is defined then THIS following may also be defined to indicate that + the timer is intended to be used for pulsed output modulation. + +if STM32F7_TIM10_PWM + +if STM32F7_PWM_MULTICHAN + +config STM32F7_TIM10_CHANNEL1 + bool "TIM10 Channel 1" + default n + ---help--- + Enables channel 1. + +if STM32F7_TIM10_CHANNEL1 + +config STM32F7_TIM10_CH1MODE + int "TIM10 Channel 1 Mode" + default 0 + range 0 5 + ---help--- + Specifies the channel mode. + +config STM32F7_TIM10_CH1OUT + bool "TIM10 Channel 1 Output" + default n + ---help--- + Enables channel 1 output. + +endif # STM32F7_TIM10_CHANNEL1 + +config STM32F7_TIM10_CHANNEL2 + bool "TIM10 Channel 2" + default n + ---help--- + Enables channel 2. + +if STM32F7_TIM10_CHANNEL2 + +config STM32F7_TIM10_CH2MODE + int "TIM10 Channel 2 Mode" + default 0 + range 0 5 + ---help--- + Specifies the channel mode. + +config STM32F7_TIM10_CH2OUT + bool "TIM10 Channel 2 Output" + default n + ---help--- + Enables channel 2 output. + +endif # STM32F7_TIM10_CHANNEL2 + +config STM32F7_TIM10_CHANNEL3 + bool "TIM10 Channel 3" + default n + ---help--- + Enables channel 3. + +if STM32F7_TIM10_CHANNEL3 + +config STM32F7_TIM10_CH3MODE + int "TIM10 Channel 3 Mode" + default 0 + range 0 5 + ---help--- + Specifies the channel mode. + +config STM32F7_TIM10_CH3OUT + bool "TIM10 Channel 3 Output" + default n + ---help--- + Enables channel 3 output. + +endif # STM32F7_TIM10_CHANNEL3 + +config STM32F7_TIM10_CHANNEL4 + bool "TIM10 Channel 4" + default n + ---help--- + Enables channel 4. + +if STM32F7_TIM10_CHANNEL4 + +config STM32F7_TIM10_CH4MODE + int "TIM10 Channel 4 Mode" + default 0 + range 0 5 + ---help--- + Specifies the channel mode. + +config STM32F7_TIM10_CH4OUT + bool "TIM10 Channel 4 Output" + default n + ---help--- + Enables channel 4 output. + +endif # STM32F7_TIM10_CHANNEL4 + +endif # STM32F7_PWM_MULTICHAN + +if !STM32F7_PWM_MULTICHAN + +config STM32F7_TIM10_CHANNEL + int "TIM10 PWM Output Channel" + default 1 + range 1 4 + ---help--- + If TIM10 is enabled for PWM usage, you also need specifies the timer output + channel {1,..,4} + +config STM32F7_TIM10_CHMODE + int "TIM10 Channel Mode" + default 0 + range 0 5 + ---help--- + Specifies the channel mode. + +endif # !STM32F7_PWM_MULTICHAN + +endif # STM32F7_TIM10_PWM + +config STM32F7_TIM11_PWM + bool "TIM11 PWM" + default n + depends on STM32F7_TIM11 + select ARCH_HAVE_PWM_PULSECOUNT + ---help--- + Reserve timer 11 for use by PWM + + Timer devices may be used for different purposes. One special purpose is + to generate modulated outputs for such things as motor control. If STM32F7_TIM11 + is defined then THIS following may also be defined to indicate that + the timer is intended to be used for pulsed output modulation. + +if STM32F7_TIM11_PWM + +if STM32F7_PWM_MULTICHAN + +config STM32F7_TIM11_CHANNEL1 + bool "TIM11 Channel 1" + default n + ---help--- + Enables channel 1. + +if STM32F7_TIM11_CHANNEL1 + +config STM32F7_TIM11_CH1MODE + int "TIM11 Channel 1 Mode" + default 0 + range 0 5 + ---help--- + Specifies the channel mode. + +config STM32F7_TIM11_CH1OUT + bool "TIM11 Channel 1 Output" + default n + ---help--- + Enables channel 1 output. + +endif # STM32F7_TIM11_CHANNEL1 + +config STM32F7_TIM11_CHANNEL2 + bool "TIM11 Channel 2" + default n + ---help--- + Enables channel 2. + +if STM32F7_TIM11_CHANNEL2 + +config STM32F7_TIM11_CH2MODE + int "TIM11 Channel 2 Mode" + default 0 + range 0 5 + ---help--- + Specifies the channel mode. + +config STM32F7_TIM11_CH2OUT + bool "TIM11 Channel 2 Output" + default n + ---help--- + Enables channel 2 output. + +endif # STM32F7_TIM11_CHANNEL2 + +config STM32F7_TIM11_CHANNEL3 + bool "TIM11 Channel 3" + default n + ---help--- + Enables channel 3. + +if STM32F7_TIM11_CHANNEL3 + +config STM32F7_TIM11_CH3MODE + int "TIM11 Channel 3 Mode" + default 0 + range 0 5 + ---help--- + Specifies the channel mode. + +config STM32F7_TIM11_CH3OUT + bool "TIM11 Channel 3 Output" + default n + ---help--- + Enables channel 3 output. + +endif # STM32F7_TIM11_CHANNEL3 + +config STM32F7_TIM11_CHANNEL4 + bool "TIM11 Channel 4" + default n + ---help--- + Enables channel 4. + +if STM32F7_TIM11_CHANNEL4 + +config STM32F7_TIM11_CH4MODE + int "TIM11 Channel 4 Mode" + default 0 + range 0 5 + ---help--- + Specifies the channel mode. + +config STM32F7_TIM11_CH4OUT + bool "TIM11 Channel 4 Output" + default n + ---help--- + Enables channel 4 output. + +endif # STM32F7_TIM11_CHANNEL4 + +endif # STM32F7_PWM_MULTICHAN + +if !STM32F7_PWM_MULTICHAN + +config STM32F7_TIM11_CHANNEL + int "TIM11 PWM Output Channel" + default 1 + range 1 4 + ---help--- + If TIM11 is enabled for PWM usage, you also need specifies the timer output + channel {1,..,4} + +config STM32F7_TIM11_CHMODE + int "TIM11 Channel Mode" + default 0 + range 0 5 + ---help--- + Specifies the channel mode. + +endif # !STM32F7_PWM_MULTICHAN + +endif # STM32F7_TIM11_PWM + +config STM32F7_TIM12_PWM + bool "TIM12 PWM" + default n + depends on STM32F7_TIM12 + select ARCH_HAVE_PWM_PULSECOUNT + ---help--- + Reserve timer 12 for use by PWM + + Timer devices may be used for different purposes. One special purpose is + to generate modulated outputs for such things as motor control. If STM32F7_TIM12 + is defined then THIS following may also be defined to indicate that + the timer is intended to be used for pulsed output modulation. + +if STM32F7_TIM12_PWM + +if STM32F7_PWM_MULTICHAN + +config STM32F7_TIM12_CHANNEL1 + bool "TIM12 Channel 1" + default n + ---help--- + Enables channel 1. + +if STM32F7_TIM12_CHANNEL1 + +config STM32F7_TIM12_CH1MODE + int "TIM12 Channel 1 Mode" + default 0 + range 0 5 + ---help--- + Specifies the channel mode. + +config STM32F7_TIM12_CH1OUT + bool "TIM12 Channel 1 Output" + default n + ---help--- + Enables channel 1 output. + +endif # STM32F7_TIM12_CHANNEL1 + +config STM32F7_TIM12_CHANNEL2 + bool "TIM12 Channel 2" + default n + ---help--- + Enables channel 2. + +if STM32F7_TIM12_CHANNEL2 + +config STM32F7_TIM12_CH2MODE + int "TIM12 Channel 2 Mode" + default 0 + range 0 5 + ---help--- + Specifies the channel mode. + +config STM32F7_TIM12_CH2OUT + bool "TIM12 Channel 2 Output" + default n + ---help--- + Enables channel 2 output. + +endif # STM32F7_TIM12_CHANNEL2 + +config STM32F7_TIM12_CHANNEL3 + bool "TIM12 Channel 3" + default n + ---help--- + Enables channel 3. + +if STM32F7_TIM12_CHANNEL3 + +config STM32F7_TIM12_CH3MODE + int "TIM12 Channel 3 Mode" + default 0 + range 0 5 + ---help--- + Specifies the channel mode. + +config STM32F7_TIM12_CH3OUT + bool "TIM12 Channel 3 Output" + default n + ---help--- + Enables channel 3 output. + +endif # STM32F7_TIM12_CHANNEL3 + +config STM32F7_TIM12_CHANNEL4 + bool "TIM12 Channel 4" + default n + ---help--- + Enables channel 4. + +if STM32F7_TIM12_CHANNEL4 + +config STM32F7_TIM12_CH4MODE + int "TIM12 Channel 4 Mode" + default 0 + range 0 5 + ---help--- + Specifies the channel mode. + +config STM32F7_TIM12_CH4OUT + bool "TIM12 Channel 4 Output" + default n + ---help--- + Enables channel 4 output. + +endif # STM32F7_TIM12_CHANNEL4 + +endif # STM32F7_PWM_MULTICHAN + +if !STM32F7_PWM_MULTICHAN + +config STM32F7_TIM12_CHANNEL + int "TIM12 PWM Output Channel" + default 1 + range 1 4 + ---help--- + If TIM12 is enabled for PWM usage, you also need specifies the timer output + channel {1,..,4} + +config STM32F7_TIM12_CHMODE + int "TIM12 Channel Mode" + default 0 + range 0 5 + ---help--- + Specifies the channel mode. + +endif # !STM32F7_PWM_MULTICHAN + +endif # STM32F7_TIM12_PWM + +config STM32F7_TIM13_PWM + bool "TIM13 PWM" + default n + depends on STM32F7_TIM13 + select ARCH_HAVE_PWM_PULSECOUNT + ---help--- + Reserve timer 13 for use by PWM + + Timer devices may be used for different purposes. One special purpose is + to generate modulated outputs for such things as motor control. If STM32F7_TIM13 + is defined then THIS following may also be defined to indicate that + the timer is intended to be used for pulsed output modulation. + +if STM32F7_TIM13_PWM + +if STM32F7_PWM_MULTICHAN + +config STM32F7_TIM13_CHANNEL1 + bool "TIM13 Channel 1" + default n + ---help--- + Enables channel 1. + +if STM32F7_TIM13_CHANNEL1 + +config STM32F7_TIM13_CH1MODE + int "TIM13 Channel 1 Mode" + default 0 + range 0 5 + ---help--- + Specifies the channel mode. + +config STM32F7_TIM13_CH1OUT + bool "TIM13 Channel 1 Output" + default n + ---help--- + Enables channel 1 output. + +endif # STM32F7_TIM13_CHANNEL1 + +config STM32F7_TIM13_CHANNEL2 + bool "TIM13 Channel 2" + default n + ---help--- + Enables channel 2. + +if STM32F7_TIM13_CHANNEL2 + +config STM32F7_TIM13_CH2MODE + int "TIM13 Channel 2 Mode" + default 0 + range 0 5 + ---help--- + Specifies the channel mode. + +config STM32F7_TIM13_CH2OUT + bool "TIM13 Channel 2 Output" + default n + ---help--- + Enables channel 2 output. + +endif # STM32F7_TIM13_CHANNEL2 + +config STM32F7_TIM13_CHANNEL3 + bool "TIM13 Channel 3" + default n + ---help--- + Enables channel 3. + +if STM32F7_TIM13_CHANNEL3 + +config STM32F7_TIM13_CH3MODE + int "TIM13 Channel 3 Mode" + default 0 + range 0 5 + ---help--- + Specifies the channel mode. + +config STM32F7_TIM13_CH3OUT + bool "TIM13 Channel 3 Output" + default n + ---help--- + Enables channel 3 output. + +endif # STM32F7_TIM13_CHANNEL3 + +config STM32F7_TIM13_CHANNEL4 + bool "TIM13 Channel 4" + default n + ---help--- + Enables channel 4. + +if STM32F7_TIM13_CHANNEL4 + +config STM32F7_TIM13_CH4MODE + int "TIM13 Channel 4 Mode" + default 0 + range 0 5 + ---help--- + Specifies the channel mode. + +config STM32F7_TIM13_CH4OUT + bool "TIM13 Channel 4 Output" + default n + ---help--- + Enables channel 4 output. + +endif # STM32F7_TIM13_CHANNEL4 + +endif # STM32F7_PWM_MULTICHAN + +if !STM32F7_PWM_MULTICHAN + +config STM32F7_TIM13_CHANNEL + int "TIM13 PWM Output Channel" + default 1 + range 1 4 + ---help--- + If TIM13 is enabled for PWM usage, you also need specifies the timer output + channel {1,..,4} + +config STM32F7_TIM13_CHMODE + int "TIM13 Channel Mode" + default 0 + range 0 5 + ---help--- + Specifies the channel mode. + +endif # !STM32F7_PWM_MULTICHAN + +endif # STM32F7_TIM13_PWM + +config STM32F7_TIM14_PWM + bool "TIM14 PWM" + default n + depends on STM32F7_TIM14 + select ARCH_HAVE_PWM_PULSECOUNT + ---help--- + Reserve timer 14 for use by PWM + + Timer devices may be used for different purposes. One special purpose is + to generate modulated outputs for such things as motor control. If STM32F7_TIM14 + is defined then THIS following may also be defined to indicate that + the timer is intended to be used for pulsed output modulation. + +if STM32F7_TIM14_PWM + +if STM32F7_PWM_MULTICHAN + +config STM32F7_TIM14_CHANNEL1 + bool "TIM14 Channel 1" + default n + ---help--- + Enables channel 1. + +if STM32F7_TIM14_CHANNEL1 + +config STM32F7_TIM14_CH1MODE + int "TIM14 Channel 1 Mode" + default 0 + range 0 5 + ---help--- + Specifies the channel mode. + +config STM32F7_TIM14_CH1OUT + bool "TIM14 Channel 1 Output" + default n + ---help--- + Enables channel 1 output. + +endif # STM32F7_TIM14_CHANNEL1 + +config STM32F7_TIM14_CHANNEL2 + bool "TIM14 Channel 2" + default n + ---help--- + Enables channel 2. + +if STM32F7_TIM14_CHANNEL2 + +config STM32F7_TIM14_CH2MODE + int "TIM14 Channel 2 Mode" + default 0 + range 0 5 + ---help--- + Specifies the channel mode. + +config STM32F7_TIM14_CH2OUT + bool "TIM14 Channel 2 Output" + default n + ---help--- + Enables channel 2 output. + +endif # STM32F7_TIM14_CHANNEL2 + +config STM32F7_TIM14_CHANNEL3 + bool "TIM14 Channel 3" + default n + ---help--- + Enables channel 3. + +if STM32F7_TIM14_CHANNEL3 + +config STM32F7_TIM14_CH3MODE + int "TIM14 Channel 3 Mode" + default 0 + range 0 5 + ---help--- + Specifies the channel mode. + +config STM32F7_TIM14_CH3OUT + bool "TIM14 Channel 3 Output" + default n + ---help--- + Enables channel 3 output. + +endif # STM32F7_TIM14_CHANNEL3 + +config STM32F7_TIM14_CHANNEL4 + bool "TIM14 Channel 4" + default n + ---help--- + Enables channel 4. + +if STM32F7_TIM14_CHANNEL4 + +config STM32F7_TIM14_CH4MODE + int "TIM14 Channel 4 Mode" + default 0 + range 0 5 + ---help--- + Specifies the channel mode. + +config STM32F7_TIM14_CH4OUT + bool "TIM14 Channel 4 Output" + default n + ---help--- + Enables channel 4 output. + +endif # STM32F7_TIM14_CHANNEL4 + +endif # STM32F7_PWM_MULTICHAN + +if !STM32F7_PWM_MULTICHAN + +config STM32F7_TIM14_CHANNEL + int "TIM14 PWM Output Channel" + default 1 + range 1 4 + ---help--- + If TIM14 is enabled for PWM usage, you also need specifies the timer output + channel {1,..,4} + +config STM32F7_TIM14_CHMODE + int "TIM14 Channel Mode" + default 0 + range 0 5 + ---help--- + Specifies the channel mode. + +endif # !STM32F7_PWM_MULTICHAN + +endif # STM32F7_TIM14_PWM + +config STM32F7_TIM15_PWM + bool "TIM15 PWM" + default n + depends on STM32F7_TIM15 + ---help--- + Reserve timer 15 for use by PWM + + Timer devices may be used for different purposes. One special purpose is + to generate modulated outputs for such things as motor control. If STM32F7_TIM15 + is defined then THIS following may also be defined to indicate that + the timer is intended to be used for pulsed output modulation. + +if STM32F7_TIM15_PWM + +if STM32F7_PWM_MULTICHAN + +config STM32F7_TIM15_CHANNEL1 + bool "TIM15 Channel 1" + default n + ---help--- + Enables channel 1. + +if STM32F7_TIM15_CHANNEL1 + +config STM32F7_TIM15_CH1MODE + int "TIM15 Channel 1 Mode" + default 0 + range 0 3 if STM32F7_STM32F30XX + range 0 1 if !STM32F7_STM32F30XX + ---help--- + Specifies the channel mode. + +config STM32F7_TIM15_CH1OUT + bool "TIM15 Channel 1 Output" + default n + ---help--- + Enables channel 1 output. + +endif # STM32F7_TIM15_CHANNEL1 + +config STM32F7_TIM15_CHANNEL2 + bool "TIM15 Channel 2" + default n + ---help--- + Enables channel 2. + +if STM32F7_TIM15_CHANNEL2 + +config STM32F7_TIM15_CH2MODE + int "TIM15 Channel 2 Mode" + default 0 + range 0 3 if STM32F7_STM32F30XX + range 0 1 if !STM32F7_STM32F30XX + ---help--- + Specifies the channel mode. + +config STM32F7_TIM15_CH2OUT + bool "TIM15 Channel 2 Output" + default n + ---help--- + Enables channel 2 output. + +endif # STM32F7_TIM15_CHANNEL2 + +endif # STM32F7_PWM_MULTICHAN + +if !STM32F7_PWM_MULTICHAN + +config STM32F7_TIM15_CHANNEL + int "TIM15 PWM Output Channel" + default 1 + range 1 2 + ---help--- + If TIM15 is enabled for PWM usage, you also need specifies the timer output + channel {1,2} + +config STM32F7_TIM15_CHMODE + int "TIM15 Channel Mode" + default 0 + range 0 3 if STM32F7_STM32F30XX + range 0 1 if !STM32F7_STM32F30XX + ---help--- + Specifies the channel mode. + +endif # !STM32F7_PWM_MULTICHAN + +endif # STM32F7_TIM15_PWM + +config STM32F7_TIM16_PWM + bool "TIM16 PWM" + default n + depends on STM32F7_TIM16 + ---help--- + Reserve timer 16 for use by PWM + + Timer devices may be used for different purposes. One special purpose is + to generate modulated outputs for such things as motor control. If STM32F7_TIM16 + is defined then THIS following may also be defined to indicate that + the timer is intended to be used for pulsed output modulation. + +if STM32F7_TIM16_PWM + +if STM32F7_PWM_MULTICHAN + +config STM32F7_TIM16_CHANNEL1 + bool "TIM16 Channel 1" + default n + ---help--- + Enables channel 1. + +if STM32F7_TIM16_CHANNEL1 + +config STM32F7_TIM16_CH1MODE + int "TIM16 Channel 1 Mode" + default 0 + range 0 1 + ---help--- + Specifies the channel mode. + +config STM32F7_TIM16_CH1OUT + bool "TIM16 Channel 1 Output" + default n + ---help--- + Enables channel 1 output. + +endif # STM32F7_TIM16_CHANNEL1 + +endif # STM32F7_PWM_MULTICHAN + +if !STM32F7_PWM_MULTICHAN + +config STM32F7_TIM16_CHANNEL + int "TIM16 PWM Output Channel" + default 1 + range 1 1 + ---help--- + If TIM16 is enabled for PWM usage, you also need specifies the timer output + channel {1} + +config STM32F7_TIM16_CHMODE + int "TIM16 Channel Mode" + default 0 + range 0 1 + ---help--- + Specifies the channel mode. + +endif # !STM32F7_PWM_MULTICHAN + +endif # STM32F7_TIM16_PWM + +config STM32F7_TIM17_PWM + bool "TIM17 PWM" + default n + depends on STM32F7_TIM17 + ---help--- + Reserve timer 17 for use by PWM + + Timer devices may be used for different purposes. One special purpose is + to generate modulated outputs for such things as motor control. If STM32F7_TIM17 + is defined then THIS following may also be defined to indicate that + the timer is intended to be used for pulsed output modulation. + +if STM32F7_TIM17_PWM + +if STM32F7_PWM_MULTICHAN + +config STM32F7_TIM17_CHANNEL1 + bool "TIM17 Channel 1" + default n + ---help--- + Enables channel 1. + +if STM32F7_TIM17_CHANNEL1 + +config STM32F7_TIM17_CH1MODE + int "TIM17 Channel 1 Mode" + default 0 + range 0 1 + ---help--- + Specifies the channel mode. + +config STM32F7_TIM17_CH1OUT + bool "TIM17 Channel 1 Output" + default n + ---help--- + Enables channel 1 output. + +endif # STM32F7_TIM17_CHANNEL1 + +endif # STM32F7_PWM_MULTICHAN + +if !STM32F7_PWM_MULTICHAN + +config STM32F7_TIM17_CHANNEL + int "TIM17 PWM Output Channel" + default 1 + range 1 1 + ---help--- + If TIM17 is enabled for PWM usage, you also need specifies the timer output + channel {1} + +config STM32F7_TIM17_CHMODE + int "TIM17 Channel Mode" + default 0 + range 0 1 + ---help--- + Specifies the channel mode. + +endif # !STM32F7_PWM_MULTICHAN + +endif # STM32F7_TIM17_PWM + +config STM32F7_PWM_MULTICHAN + bool "PWM Multiple Output Channels" + default n + depends on STM32F7_TIM1_PWM || STM32F7_TIM2_PWM || STM32F7_TIM3_PWM || STM32F7_TIM4_PWM || STM32F7_TIM5_PWM || STM32F7_TIM8_PWM || STM32F7_TIM9_PWM || STM32F7_TIM10_PWM || STM32F7_TIM11_PWM || STM32F7_TIM12_PWM || STM32F7_TIM13_PWM || STM32F7_TIM14_PWM || STM32F7_TIM15_PWM || STM32F7_TIM16_PWM || STM32F7_TIM17_PWM + select ARCH_HAVE_PWM_MULTICHAN + ---help--- + Specifies that the PWM driver supports multiple output + channels per timer. + +config STM32F7_TIM1_ADC + bool "TIM1 ADC" + default n + depends on STM32F7_TIM1 && STM32F7_ADC + ---help--- + Reserve timer 1 for use by ADC + + Timer devices may be used for different purposes. If STM32F7_TIM1 is + defined then the following may also be defined to indicate that the + timer is intended to be used for ADC conversion. Note that ADC usage + requires two definition: Not only do you have to assign the timer + for used by the ADC, but then you also have to configure which ADC + channel it is assigned to. + +choice + prompt "Select TIM1 ADC channel" + default STM32F7_TIM1_ADC1 + depends on STM32F7_TIM1_ADC + +config STM32F7_TIM1_ADC1 + bool "TIM1 ADC channel 1" + depends on STM32F7_ADC1 + select HAVE_ADC1_TIMER + ---help--- + Reserve TIM1 to trigger ADC1 + +config STM32F7_TIM1_ADC2 + bool "TIM1 ADC channel 2" + depends on STM32F7_ADC2 + select HAVE_ADC2_TIMER + ---help--- + Reserve TIM1 to trigger ADC2 + +config STM32F7_TIM1_ADC3 + bool "TIM1 ADC channel 3" + depends on STM32F7_ADC3 + select HAVE_ADC3_TIMER + ---help--- + Reserve TIM1 to trigger ADC3 + +endchoice + +config STM32F7_TIM2_ADC + bool "TIM2 ADC" + default n + depends on STM32F7_TIM2 && STM32F7_ADC + ---help--- + Reserve timer 1 for use by ADC + + Timer devices may be used for different purposes. If STM32F7_TIM2 is + defined then the following may also be defined to indicate that the + timer is intended to be used for ADC conversion. Note that ADC usage + requires two definition: Not only do you have to assign the timer + for used by the ADC, but then you also have to configure which ADC + channel it is assigned to. + +choice + prompt "Select TIM2 ADC channel" + default STM32F7_TIM2_ADC1 + depends on STM32F7_TIM2_ADC + +config STM32F7_TIM2_ADC1 + bool "TIM2 ADC channel 1" + depends on STM32F7_ADC1 + select HAVE_ADC1_TIMER + ---help--- + Reserve TIM2 to trigger ADC1 + +config STM32F7_TIM2_ADC2 + bool "TIM2 ADC channel 2" + depends on STM32F7_ADC2 + select HAVE_ADC2_TIMER + ---help--- + Reserve TIM2 to trigger ADC2 + +config STM32F7_TIM2_ADC3 + bool "TIM2 ADC channel 3" + depends on STM32F7_ADC3 + select HAVE_ADC3_TIMER + ---help--- + Reserve TIM2 to trigger ADC3 + +endchoice + +config STM32F7_TIM3_ADC + bool "TIM3 ADC" + default n + depends on STM32F7_TIM3 && STM32F7_ADC + ---help--- + Reserve timer 1 for use by ADC + + Timer devices may be used for different purposes. If STM32F7_TIM3 is + defined then the following may also be defined to indicate that the + timer is intended to be used for ADC conversion. Note that ADC usage + requires two definition: Not only do you have to assign the timer + for used by the ADC, but then you also have to configure which ADC + channel it is assigned to. + +choice + prompt "Select TIM3 ADC channel" + default STM32F7_TIM3_ADC1 + depends on STM32F7_TIM3_ADC + +config STM32F7_TIM3_ADC1 + bool "TIM3 ADC channel 1" + depends on STM32F7_ADC1 + select HAVE_ADC1_TIMER + ---help--- + Reserve TIM3 to trigger ADC1 + +config STM32F7_TIM3_ADC2 + bool "TIM3 ADC channel 2" + depends on STM32F7_ADC2 + select HAVE_ADC2_TIMER + ---help--- + Reserve TIM3 to trigger ADC2 + +config STM32F7_TIM3_ADC3 + bool "TIM3 ADC channel 3" + depends on STM32F7_ADC3 + select HAVE_ADC3_TIMER + ---help--- + Reserve TIM3 to trigger ADC3 + +endchoice + +config STM32F7_TIM4_ADC + bool "TIM4 ADC" + default n + depends on STM32F7_TIM4 && STM32F7_ADC + ---help--- + Reserve timer 1 for use by ADC + + Timer devices may be used for different purposes. If STM32F7_TIM4 is + defined then the following may also be defined to indicate that the + timer is intended to be used for ADC conversion. Note that ADC usage + requires two definition: Not only do you have to assign the timer + for used by the ADC, but then you also have to configure which ADC + channel it is assigned to. + +choice + prompt "Select TIM4 ADC channel" + default STM32F7_TIM4_ADC1 + depends on STM32F7_TIM4_ADC + +config STM32F7_TIM4_ADC1 + bool "TIM4 ADC channel 1" + depends on STM32F7_ADC1 + select HAVE_ADC1_TIMER + ---help--- + Reserve TIM4 to trigger ADC1 + +config STM32F7_TIM4_ADC2 + bool "TIM4 ADC channel 2" + depends on STM32F7_ADC2 + select HAVE_ADC2_TIMER + ---help--- + Reserve TIM4 to trigger ADC2 + +config STM32F7_TIM4_ADC3 + bool "TIM4 ADC channel 3" + depends on STM32F7_ADC3 + select HAVE_ADC3_TIMER + ---help--- + Reserve TIM4 to trigger ADC3 + +endchoice + +config STM32F7_TIM5_ADC + bool "TIM5 ADC" + default n + depends on STM32F7_TIM5 && STM32F7_ADC + ---help--- + Reserve timer 1 for use by ADC + + Timer devices may be used for different purposes. If STM32F7_TIM5 is + defined then the following may also be defined to indicate that the + timer is intended to be used for ADC conversion. Note that ADC usage + requires two definition: Not only do you have to assign the timer + for used by the ADC, but then you also have to configure which ADC + channel it is assigned to. + +choice + prompt "Select TIM5 ADC channel" + default STM32F7_TIM5_ADC1 + depends on STM32F7_TIM5_ADC + +config STM32F7_TIM5_ADC1 + bool "TIM5 ADC channel 1" + depends on STM32F7_ADC1 + select HAVE_ADC1_TIMER + ---help--- + Reserve TIM5 to trigger ADC1 + +config STM32F7_TIM5_ADC2 + bool "TIM5 ADC channel 2" + depends on STM32F7_ADC2 + select HAVE_ADC2_TIMER + ---help--- + Reserve TIM5 to trigger ADC2 + +config STM32F7_TIM5_ADC3 + bool "TIM5 ADC channel 3" + depends on STM32F7_ADC3 + select HAVE_ADC3_TIMER + ---help--- + Reserve TIM5 to trigger ADC3 + +endchoice + +config STM32F7_TIM8_ADC + bool "TIM8 ADC" + default n + depends on STM32F7_TIM8 && STM32F7_ADC + ---help--- + Reserve timer 1 for use by ADC + + Timer devices may be used for different purposes. If STM32F7_TIM8 is + defined then the following may also be defined to indicate that the + timer is intended to be used for ADC conversion. Note that ADC usage + requires two definition: Not only do you have to assign the timer + for used by the ADC, but then you also have to configure which ADC + channel it is assigned to. + +choice + prompt "Select TIM8 ADC channel" + default STM32F7_TIM8_ADC1 + depends on STM32F7_TIM8_ADC + +config STM32F7_TIM8_ADC1 + bool "TIM8 ADC channel 1" + depends on STM32F7_ADC1 + select HAVE_ADC1_TIMER + ---help--- + Reserve TIM8 to trigger ADC1 + +config STM32F7_TIM8_ADC2 + bool "TIM8 ADC channel 2" + depends on STM32F7_ADC2 + select HAVE_ADC2_TIMER + ---help--- + Reserve TIM8 to trigger ADC2 + +config STM32F7_TIM8_ADC3 + bool "TIM8 ADC channel 3" + depends on STM32F7_ADC3 + select HAVE_ADC3_TIMER + ---help--- + Reserve TIM8 to trigger ADC3 + +endchoice + +config HAVE_ADC1_TIMER + bool + +config HAVE_ADC2_TIMER + bool + +config HAVE_ADC3_TIMER + bool + +config STM32F7_ADC1_SAMPLE_FREQUENCY + int "ADC1 Sampling Frequency" + default 100 + depends on HAVE_ADC1_TIMER + ---help--- + ADC1 sampling frequency. Default: 100Hz + +config STM32F7_ADC1_TIMTRIG + int "ADC1 Timer Trigger" + default 0 + range 0 4 + depends on HAVE_ADC1_TIMER + ---help--- + Values 0:CC1 1:CC2 2:CC3 3:CC4 4:TRGO + +config STM32F7_ADC2_SAMPLE_FREQUENCY + int "ADC2 Sampling Frequency" + default 100 + depends on HAVE_ADC2_TIMER + ---help--- + ADC2 sampling frequency. Default: 100Hz + +config STM32F7_ADC2_TIMTRIG + int "ADC2 Timer Trigger" + default 0 + range 0 4 + depends on HAVE_ADC2_TIMER + ---help--- + Values 0:CC1 1:CC2 2:CC3 3:CC4 4:TRGO + +config STM32F7_ADC3_SAMPLE_FREQUENCY + int "ADC3 Sampling Frequency" + default 100 + depends on HAVE_ADC3_TIMER + ---help--- + ADC3 sampling frequency. Default: 100Hz + +config STM32F7_ADC3_TIMTRIG + int "ADC3 Timer Trigger" + default 0 + range 0 4 + depends on HAVE_ADC3_TIMER + ---help--- + Values 0:CC1 1:CC2 2:CC3 3:CC4 4:TRGO + +config STM32F7_TIM1_DAC + bool "TIM1 DAC" + default n + depends on STM32F7_TIM1 && STM32F7_DAC + ---help--- + Reserve timer 1 for use by DAC + + Timer devices may be used for different purposes. If STM32F7_TIM1 is + defined then the following may also be defined to indicate that the + timer is intended to be used for DAC conversion. Note that DAC usage + requires two definition: Not only do you have to assign the timer + for used by the DAC, but then you also have to configure which DAC + channel it is assigned to. + +choice + prompt "Select TIM1 DAC channel" + default STM32F7_TIM1_DAC1 + depends on STM32F7_TIM1_DAC + +config STM32F7_TIM1_DAC1 + bool "TIM1 DAC channel 1" + ---help--- + Reserve TIM1 to trigger DAC1 + +config STM32F7_TIM1_DAC2 + bool "TIM1 DAC channel 2" + ---help--- + Reserve TIM1 to trigger DAC2 + +endchoice + +config STM32F7_TIM2_DAC + bool "TIM2 DAC" + default n + depends on STM32F7_TIM2 && STM32F7_DAC + ---help--- + Reserve timer 2 for use by DAC + + Timer devices may be used for different purposes. If STM32F7_TIM2 is + defined then the following may also be defined to indicate that the + timer is intended to be used for DAC conversion. Note that DAC usage + requires two definition: Not only do you have to assign the timer + for used by the DAC, but then you also have to configure which DAC + channel it is assigned to. + +choice + prompt "Select TIM2 DAC channel" + default STM32F7_TIM2_DAC1 + depends on STM32F7_TIM2_DAC + +config STM32F7_TIM2_DAC1 + bool "TIM2 DAC channel 1" + ---help--- + Reserve TIM2 to trigger DAC1 + +config STM32F7_TIM2_DAC2 + bool "TIM2 DAC channel 2" + ---help--- + Reserve TIM2 to trigger DAC2 + +endchoice + +config STM32F7_TIM3_DAC + bool "TIM3 DAC" + default n + depends on STM32F7_TIM3 && STM32F7_DAC + ---help--- + Reserve timer 3 for use by DAC + + Timer devices may be used for different purposes. If STM32F7_TIM3 is + defined then the following may also be defined to indicate that the + timer is intended to be used for DAC conversion. Note that DAC usage + requires two definition: Not only do you have to assign the timer + for used by the DAC, but then you also have to configure which DAC + channel it is assigned to. + +choice + prompt "Select TIM3 DAC channel" + default STM32F7_TIM3_DAC1 + depends on STM32F7_TIM3_DAC + +config STM32F7_TIM3_DAC1 + bool "TIM3 DAC channel 1" + ---help--- + Reserve TIM3 to trigger DAC1 + +config STM32F7_TIM3_DAC2 + bool "TIM3 DAC channel 2" + ---help--- + Reserve TIM3 to trigger DAC2 + +endchoice + +config STM32F7_TIM4_DAC + bool "TIM4 DAC" + default n + depends on STM32F7_TIM4 && STM32F7_DAC + ---help--- + Reserve timer 4 for use by DAC + + Timer devices may be used for different purposes. If STM32F7_TIM4 is + defined then the following may also be defined to indicate that the + timer is intended to be used for DAC conversion. Note that DAC usage + requires two definition: Not only do you have to assign the timer + for used by the DAC, but then you also have to configure which DAC + channel it is assigned to. + +choice + prompt "Select TIM4 DAC channel" + default STM32F7_TIM4_DAC1 + depends on STM32F7_TIM4_DAC + +config STM32F7_TIM4_DAC1 + bool "TIM4 DAC channel 1" + ---help--- + Reserve TIM4 to trigger DAC1 + +config STM32F7_TIM4_DAC2 + bool "TIM4 DAC channel 2" + ---help--- + Reserve TIM4 to trigger DAC2 + +endchoice + +config STM32F7_TIM5_DAC + bool "TIM5 DAC" + default n + depends on STM32F7_TIM5 && STM32F7_DAC + ---help--- + Reserve timer 5 for use by DAC + + Timer devices may be used for different purposes. If STM32F7_TIM5 is + defined then the following may also be defined to indicate that the + timer is intended to be used for DAC conversion. Note that DAC usage + requires two definition: Not only do you have to assign the timer + for used by the DAC, but then you also have to configure which DAC + channel it is assigned to. + +choice + prompt "Select TIM5 DAC channel" + default STM32F7_TIM5_DAC1 + depends on STM32F7_TIM5_DAC + +config STM32F7_TIM5_DAC1 + bool "TIM5 DAC channel 1" + ---help--- + Reserve TIM5 to trigger DAC1 + +config STM32F7_TIM5_DAC2 + bool "TIM5 DAC channel 2" + ---help--- + Reserve TIM5 to trigger DAC2 + +endchoice + +config STM32F7_TIM6_DAC + bool "TIM6 DAC" + default n + depends on STM32F7_TIM6 && STM32F7_DAC + ---help--- + Reserve timer 6 for use by DAC + + Timer devices may be used for different purposes. If STM32F7_TIM6 is + defined then the following may also be defined to indicate that the + timer is intended to be used for DAC conversion. Note that DAC usage + requires two definition: Not only do you have to assign the timer + for used by the DAC, but then you also have to configure which DAC + channel it is assigned to. + +choice + prompt "Select TIM6 DAC channel" + default STM32F7_TIM6_DAC1 + depends on STM32F7_TIM6_DAC + +config STM32F7_TIM6_DAC1 + bool "TIM6 DAC channel 1" + ---help--- + Reserve TIM6 to trigger DAC1 + +config STM32F7_TIM6_DAC2 + bool "TIM6 DAC channel 2" + ---help--- + Reserve TIM6 to trigger DAC2 + +endchoice + +config STM32F7_TIM7_DAC + bool "TIM7 DAC" + default n + depends on STM32F7_TIM7 && STM32F7_DAC + ---help--- + Reserve timer 7 for use by DAC + + Timer devices may be used for different purposes. If STM32F7_TIM7 is + defined then the following may also be defined to indicate that the + timer is intended to be used for DAC conversion. Note that DAC usage + requires two definition: Not only do you have to assign the timer + for used by the DAC, but then you also have to configure which DAC + channel it is assigned to. + +choice + prompt "Select TIM7 DAC channel" + default STM32F7_TIM7_DAC1 + depends on STM32F7_TIM7_DAC + +config STM32F7_TIM7_DAC1 + bool "TIM7 DAC channel 1" + ---help--- + Reserve TIM7 to trigger DAC1 + +config STM32F7_TIM7_DAC2 + bool "TIM7 DAC channel 2" + ---help--- + Reserve TIM7 to trigger DAC2 + +endchoice + +config STM32F7_TIM8_DAC + bool "TIM8 DAC" + default n + depends on STM32F7_TIM8 && STM32F7_DAC + ---help--- + Reserve timer 8 for use by DAC + + Timer devices may be used for different purposes. If STM32F7_TIM8 is + defined then the following may also be defined to indicate that the + timer is intended to be used for DAC conversion. Note that DAC usage + requires two definition: Not only do you have to assign the timer + for used by the DAC, but then you also have to configure which DAC + channel it is assigned to. + +choice + prompt "Select TIM8 DAC channel" + default STM32F7_TIM8_DAC1 + depends on STM32F7_TIM8_DAC + +config STM32F7_TIM8_DAC1 + bool "TIM8 DAC channel 1" + ---help--- + Reserve TIM8 to trigger DAC1 + +config STM32F7_TIM8_DAC2 + bool "TIM8 DAC channel 2" + ---help--- + Reserve TIM8 to trigger DAC2 + +endchoice + +config STM32F7_TIM9_DAC + bool "TIM9 DAC" + default n + depends on STM32F7_TIM9 && STM32F7_DAC + ---help--- + Reserve timer 9 for use by DAC + + Timer devices may be used for different purposes. If STM32F7_TIM9 is + defined then the following may also be defined to indicate that the + timer is intended to be used for DAC conversion. Note that DAC usage + requires two definition: Not only do you have to assign the timer + for used by the DAC, but then you also have to configure which DAC + channel it is assigned to. + +choice + prompt "Select TIM9 DAC channel" + default STM32F7_TIM9_DAC1 + depends on STM32F7_TIM9_DAC + +config STM32F7_TIM9_DAC1 + bool "TIM9 DAC channel 1" + ---help--- + Reserve TIM9 to trigger DAC1 + +config STM32F7_TIM9_DAC2 + bool "TIM9 DAC channel 2" + ---help--- + Reserve TIM9 to trigger DAC2 + +endchoice + +config STM32F7_TIM10_DAC + bool "TIM10 DAC" + default n + depends on STM32F7_TIM10 && STM32F7_DAC + ---help--- + Reserve timer 10 for use by DAC + + Timer devices may be used for different purposes. If STM32F7_TIM10 is + defined then the following may also be defined to indicate that the + timer is intended to be used for DAC conversion. Note that DAC usage + requires two definition: Not only do you have to assign the timer + for used by the DAC, but then you also have to configure which DAC + channel it is assigned to. + +choice + prompt "Select TIM10 DAC channel" + default STM32F7_TIM10_DAC1 + depends on STM32F7_TIM10_DAC + +config STM32F7_TIM10_DAC1 + bool "TIM10 DAC channel 1" + ---help--- + Reserve TIM10 to trigger DAC1 + +config STM32F7_TIM10_DAC2 + bool "TIM10 DAC channel 2" + ---help--- + Reserve TIM10 to trigger DAC2 + +endchoice + +config STM32F7_TIM11_DAC + bool "TIM11 DAC" + default n + depends on STM32F7_TIM11 && STM32F7_DAC + ---help--- + Reserve timer 11 for use by DAC + + Timer devices may be used for different purposes. If STM32F7_TIM11 is + defined then the following may also be defined to indicate that the + timer is intended to be used for DAC conversion. Note that DAC usage + requires two definition: Not only do you have to assign the timer + for used by the DAC, but then you also have to configure which DAC + channel it is assigned to. + +choice + prompt "Select TIM11 DAC channel" + default STM32F7_TIM11_DAC1 + depends on STM32F7_TIM11_DAC + +config STM32F7_TIM11_DAC1 + bool "TIM11 DAC channel 1" + ---help--- + Reserve TIM11 to trigger DAC1 + +config STM32F7_TIM11_DAC2 + bool "TIM11 DAC channel 2" + ---help--- + Reserve TIM11 to trigger DAC2 + +endchoice + +config STM32F7_TIM12_DAC + bool "TIM12 DAC" + default n + depends on STM32F7_TIM12 && STM32F7_DAC + ---help--- + Reserve timer 12 for use by DAC + + Timer devices may be used for different purposes. If STM32F7_TIM12 is + defined then the following may also be defined to indicate that the + timer is intended to be used for DAC conversion. Note that DAC usage + requires two definition: Not only do you have to assign the timer + for used by the DAC, but then you also have to configure which DAC + channel it is assigned to. + +choice + prompt "Select TIM12 DAC channel" + default STM32F7_TIM12_DAC1 + depends on STM32F7_TIM12_DAC + +config STM32F7_TIM12_DAC1 + bool "TIM12 DAC channel 1" + ---help--- + Reserve TIM12 to trigger DAC1 + +config STM32F7_TIM12_DAC2 + bool "TIM12 DAC channel 2" + ---help--- + Reserve TIM12 to trigger DAC2 + +endchoice + +config STM32F7_TIM13_DAC + bool "TIM13 DAC" + default n + depends on STM32F7_TIM13 && STM32F7_DAC + ---help--- + Reserve timer 13 for use by DAC + + Timer devices may be used for different purposes. If STM32F7_TIM13 is + defined then the following may also be defined to indicate that the + timer is intended to be used for DAC conversion. Note that DAC usage + requires two definition: Not only do you have to assign the timer + for used by the DAC, but then you also have to configure which DAC + channel it is assigned to. + +choice + prompt "Select TIM13 DAC channel" + default STM32F7_TIM13_DAC1 + depends on STM32F7_TIM13_DAC + +config STM32F7_TIM13_DAC1 + bool "TIM13 DAC channel 1" + ---help--- + Reserve TIM13 to trigger DAC1 + +config STM32F7_TIM13_DAC2 + bool "TIM13 DAC channel 2" + ---help--- + Reserve TIM13 to trigger DAC2 + +endchoice + +config STM32F7_TIM14_DAC + bool "TIM14 DAC" + default n + depends on STM32F7_TIM14 && STM32F7_DAC + ---help--- + Reserve timer 14 for use by DAC + + Timer devices may be used for different purposes. If STM32F7_TIM14 is + defined then the following may also be defined to indicate that the + timer is intended to be used for DAC conversion. Note that DAC usage + requires two definition: Not only do you have to assign the timer + for used by the DAC, but then you also have to configure which DAC + channel it is assigned to. + +choice + prompt "Select TIM14 DAC channel" + default STM32F7_TIM14_DAC1 + depends on STM32F7_TIM14_DAC + +config STM32F7_TIM14_DAC1 + bool "TIM14 DAC channel 1" + ---help--- + Reserve TIM14 to trigger DAC1 + +config STM32F7_TIM14_DAC2 + bool "TIM14 DAC channel 2" + ---help--- + Reserve TIM14 to trigger DAC2 + +endchoice + +config STM32F7_TIM1_CAP + bool "TIM1 Capture" + default n + depends on STM32F7_HAVE_TIM1 + ---help--- + Reserve timer 1 for use by Capture + + Timer devices may be used for different purposes. One special purpose is + to capture input. + +config STM32F7_TIM2_CAP + bool "TIM2 Capture" + default n + depends on STM32F7_HAVE_TIM2 + ---help--- + Reserve timer 2 for use by Capture + + Timer devices may be used for different purposes. One special purpose is + to capture input. + +config STM32F7_TIM3_CAP + bool "TIM3 Capture" + default n + depends on STM32F7_HAVE_TIM3 + ---help--- + Reserve timer 3 for use by Capture + + Timer devices may be used for different purposes. One special purpose is + to capture input. + +config STM32F7_TIM4_CAP + bool "TIM4 Capture" + default n + depends on STM32F7_HAVE_TIM4 + ---help--- + Reserve timer 4 for use by Capture + + Timer devices may be used for different purposes. One special purpose is + to capture input. + +config STM32F7_TIM5_CAP + bool "TIM5 Capture" + default n + depends on STM32F7_HAVE_TIM5 + ---help--- + Reserve timer 5 for use by Capture + + Timer devices may be used for different purposes. One special purpose is + to capture input. + +config STM32F7_TIM8_CAP + bool "TIM8 Capture" + default n + depends on STM32F7_HAVE_TIM8 + ---help--- + Reserve timer 8 for use by Capture + + Timer devices may be used for different purposes. One special purpose is + to capture input. + +config STM32F7_TIM9_CAP + bool "TIM9 Capture" + default n + depends on STM32F7_HAVE_TIM9 + ---help--- + Reserve timer 9 for use by Capture + + Timer devices may be used for different purposes. One special purpose is + to capture input. + +config STM32F7_TIM10_CAP + bool "TIM10 Capture" + default n + depends on STM32F7_HAVE_TIM10 + ---help--- + Reserve timer 10 for use by Capture + + Timer devices may be used for different purposes. One special purpose is + to capture input. + +config STM32F7_TIM11_CAP + bool "TIM11 Capture" + default n + depends on STM32F7_HAVE_TIM11 + ---help--- + Reserve timer 11 for use by Capture + + Timer devices may be used for different purposes. One special purpose is + to capture input. + +config STM32F7_TIM12_CAP + bool "TIM12 Capture" + default n + depends on STM32F7_HAVE_TIM12 + ---help--- + Reserve timer 12 for use by Capture + + Timer devices may be used for different purposes. One special purpose is + to capture input. + +config STM32F7_TIM13_CAP + bool "TIM13 Capture" + default n + depends on STM32F7_HAVE_TIM13 + ---help--- + Reserve timer 13 for use by Capture + + Timer devices may be used for different purposes. One special purpose is + to capture input. + +config STM32F7_TIM14_CAP + bool "TIM14 Capture" + default n + depends on STM32F7_HAVE_TIM14 + ---help--- + Reserve timer 14 for use by Capture + + Timer devices may be used for different purposes. One special purpose is + to capture input. + +endmenu # Timer Configuration + +menu "ADC Configuration" + depends on STM32F7_ADC + +config STM32F7_ADC1_DMA + bool "ADC1 DMA" + depends on STM32F7_ADC1 && STM32F7_HAVE_ADC1_DMA + default n + ---help--- + If DMA is selected, then the ADC may be configured to support + DMA transfer, which is necessary if multiple channels are read + or if very high trigger frequencies are used. + +config STM32F7_ADC2_DMA + bool "ADC2 DMA" + depends on STM32F7_ADC2 && STM32F7_HAVE_ADC2_DMA + default n + ---help--- + If DMA is selected, then the ADC may be configured to support + DMA transfer, which is necessary if multiple channels are read + or if very high trigger frequencies are used. + +config STM32F7_ADC3_DMA + bool "ADC3 DMA" + depends on STM32F7_ADC3 && STM32F7_HAVE_ADC3_DMA + default n + ---help--- + If DMA is selected, then the ADC may be configured to support + DMA transfer, which is necessary if multiple channels are read + or if very high trigger frequencies are used. + +endmenu # "ADC Configuration" if STM32F7_ETHMAC menu "Ethernet MAC configuration" diff --git a/arch/arm/src/stm32f7/Make.defs b/arch/arm/src/stm32f7/Make.defs index 07aa380ebd..0680d17cfb 100644 --- a/arch/arm/src/stm32f7/Make.defs +++ b/arch/arm/src/stm32f7/Make.defs @@ -151,11 +151,11 @@ ifeq ($(CONFIG_STM32F7_TIM),y) CHIP_CSRCS += stm32_tim.c endif -ifeq ($(CONFIG_ADC),y) +ifeq ($(CONFIG_STM32F7_ADC),y) CHIP_CSRCS += stm32_adc.c endif -ifeq ($(CONFIG_RTC),y) +ifeq ($(CONFIG_STM32F7_RTC),y) ifeq ($(CONFIG_RTC_ALARM),y) CHIP_CSRCS += stm32_exti_alarm.c endif From 9447316162742c4cb61784175d994bfd8bf213e8 Mon Sep 17 00:00:00 2001 From: David Sidrane Date: Thu, 16 Jun 2016 13:06:39 -1000 Subject: [PATCH 62/75] Nucleo-144 ADC --- configs/nucleo-144/include/board.h | 7 ++ configs/nucleo-144/src/Makefile | 3 + configs/nucleo-144/src/nucleo-144.h | 14 +++ configs/nucleo-144/src/stm32_adc.c | 188 ++++++++++++++++++++++++++++ 4 files changed, 212 insertions(+) create mode 100644 configs/nucleo-144/src/stm32_adc.c diff --git a/configs/nucleo-144/include/board.h b/configs/nucleo-144/include/board.h index ea4e2efbe2..07f4a3c515 100644 --- a/configs/nucleo-144/include/board.h +++ b/configs/nucleo-144/include/board.h @@ -311,6 +311,13 @@ * USART8: has no remap */ +/* DMA channels *************************************************************/ +/* ADC */ + +#define ADC1_DMA_CHAN DMAMAP_ADC1_1 +#define ADC2_DMA_CHAN DMAMAP_ADC2_1 +#define ADC3_DMA_CHAN DMAMAP_ADC3_1 + /* SPI * * diff --git a/configs/nucleo-144/src/Makefile b/configs/nucleo-144/src/Makefile index e179c34a7b..e4e02750bd 100644 --- a/configs/nucleo-144/src/Makefile +++ b/configs/nucleo-144/src/Makefile @@ -56,6 +56,9 @@ endif ifeq ($(CONFIG_SPI),y) CSRCS += stm32_spi.c endif +ifeq ($(CONFIG_ADC),y) +CSRCS += stm32_adc.c +endif ifeq ($(HAVE_SDIO),y) CSRCS += stm32_sdio.c diff --git a/configs/nucleo-144/src/nucleo-144.h b/configs/nucleo-144/src/nucleo-144.h index 8737deee61..9747de3015 100644 --- a/configs/nucleo-144/src/nucleo-144.h +++ b/configs/nucleo-144/src/nucleo-144.h @@ -185,5 +185,19 @@ void stm32_dma_alloc_init(void); int stm32_dma_alloc_init(void); #endif +/**************************************************************************** + * Name: stm32_adc_initialize + * + * Description: + * Called at application startup time to initialize the ADC functionality. + * + ****************************************************************************/ + +#ifdef CONFIG_ADC +int board_adc_initialize(void); +#endif + + + #endif /* __ASSEMBLY__ */ #endif /* __CONFIGS_NUCLEO_144_SRC_NUCLEO_144_H */ diff --git a/configs/nucleo-144/src/stm32_adc.c b/configs/nucleo-144/src/stm32_adc.c new file mode 100644 index 0000000000..b079ebc738 --- /dev/null +++ b/configs/nucleo-144/src/stm32_adc.c @@ -0,0 +1,188 @@ +/************************************************************************************ + * configs/nucleo-144/src/stm32_adc.c + * + * Copyright (C) 2016 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ************************************************************************************/ + +/************************************************************************************ + * Included Files + ************************************************************************************/ + +#include + +#include +#include + +#include +#include +#include + +#include "chip.h" +#include "stm32_gpio.h" +#include "stm32_adc.h" +#include "nucleo-144.h" + +#ifdef CONFIG_ADC + +/************************************************************************************ + * Pre-processor Definitions + ************************************************************************************/ + +/* Configuration ********************************************************************/ +/* Up to 3 ADC interfaces are supported */ + +#if STM32F7_NADC < 3 +# undef CONFIG_STM32F7_ADC3 +#endif + +#if STM32F7_NADC < 2 +# undef CONFIG_STM32F7_ADC2 +#endif + +#if STM32F7_NADC < 1 +# undef CONFIG_STM32F7_ADC1 +#endif + +#if defined(CONFIG_STM32F7_ADC1) || defined(CONFIG_STM32F7_ADC2) || defined(CONFIG_STM32F7_ADC3) +#ifndef CONFIG_STM32F7_ADC1 +# warning "Channel information only available for ADC1" +#endif + +/* The number of ADC channels in the conversion list */ + +#define ADC1_NCHANNELS 1 + +/************************************************************************************ + * Private Data + ************************************************************************************/ +/* The Olimex STM32-P405 has a 10 Kohm potentiometer AN_TR connected to PC0 + * ADC123_IN10 + */ + +/* Identifying number of each ADC channel: Variable Resistor. + * + * {1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 15}; + */ + +#ifdef CONFIG_STM32F7_ADC1 +static const uint8_t g_chanlist[ADC1_NCHANNELS] = {1}; + +/* Configurations of pins used byte each ADC channels + * + * {GPIO_ADC1_IN1, GPIO_ADC1_IN2, GPIO_ADC1_IN3, GPIO_ADC1_IN4, GPIO_ADC1_IN5, + * GPIO_ADC1_IN6, GPIO_ADC1_IN7, GPIO_ADC1_IN8, GPIO_ADC1_IN9, GPIO_ADC1_IN10, + * GPIO_ADC1_IN11, GPIO_ADC1_IN12, GPIO_ADC1_IN13, GPIO_ADC1_IN15}; + */ + +static const uint32_t g_pinlist[ADC1_NCHANNELS] = {GPIO_ADC1_IN0}; +#endif + +/************************************************************************************ + * Private Functions + ************************************************************************************/ + +/************************************************************************************ + * Public Functions + ************************************************************************************/ + +/************************************************************************************ + * Name: board_adc_setup + * + * Description: + * All STM32 architectures must provide the following interface to work with + * examples/adc. + * + ************************************************************************************/ + +int board_adc_setup(void) +{ + return board_adc_initialize(); +} + +/************************************************************************************ + * Name: stm32_adc_initialize + * + * Description: + * Called at application startup time to initialize the ADC functionality. + * + ************************************************************************************/ + +int board_adc_initialize(void) +{ +#ifdef CONFIG_STM32F7_ADC1 + static bool initialized = false; + struct adc_dev_s *adc; + int ret; + int i; + + /* Check if we have already initialized */ + + if (!initialized) + { + /* Configure the pins as analog inputs for the selected channels */ + + for (i = 0; i < ADC1_NCHANNELS; i++) + { + stm32_configgpio(g_pinlist[i]); + } + + /* Call stm32_adcinitialize() to get an instance of the ADC interface */ + + adc = stm32_adc_initialize(1, g_chanlist, ADC1_NCHANNELS); + if (adc == NULL) + { + aerr("ERROR: Failed to get ADC interface\n"); + return -ENODEV; + } + + /* Register the ADC driver at "/dev/adc0" */ + + ret = adc_register("/dev/adc0", adc); + if (ret < 0) + { + aerr("ERROR: adc_register failed: %d\n", ret); + return ret; + } + + /* Now we are initialized */ + + initialized = true; + } + + return OK; +#else + return -ENOSYS; +#endif +} + +#endif /* CONFIG_STM32F7_ADC1 || CONFIG_STM32F7_ADC2 || CONFIG_STM32F7_ADC3 */ +#endif /* CONFIG_ADC */ From 003fd604d15c6780a6f7c70878b3e8bed75f46c1 Mon Sep 17 00:00:00 2001 From: David Sidrane Date: Thu, 16 Jun 2016 14:59:44 -1000 Subject: [PATCH 63/75] Nucleo-144 I2C pinout --- configs/nucleo-144/include/board.h | 23 +++++++++++++++++++++++ 1 file changed, 23 insertions(+) diff --git a/configs/nucleo-144/include/board.h b/configs/nucleo-144/include/board.h index 07f4a3c515..b31d7b5a8b 100644 --- a/configs/nucleo-144/include/board.h +++ b/configs/nucleo-144/include/board.h @@ -346,6 +346,29 @@ #define GPIO_SPI3_MOSI GPIO_SPI3_MOSI_2 #define GPIO_SPI3_SCK GPIO_SPI3_SCK_1 +/* I2C + * + * + * PB8 I2C1_SCL CN12-3 + * PB9 I2C1_SDA CN12-5 + + * PF1 I2C2_SCL CN11-51 + * PF0 I2C2_SDA CN11-53 + * + * PA8 I2C3_SCL CN12-23 + * PC9 I2C3_SDA CN12-1 + * + */ + +#define GPIO_I2C1_SCL GPIO_I2C1_SCL_2 +#define GPIO_I2C1_SDA GPIO_I2C1_SDA_2 + +#define GPIO_I2C2_SCL GPIO_I2C2_SCL_2 +#define GPIO_I2C2_SDA GPIO_I2C2_SDA_2 + +#define GPIO_I2C3_SCL GPIO_I2C3_SCL_1 +#define GPIO_I2C3_SDA GPIO_I2C3_SDA_1 + /* The STM32 F7 connects to a SMSC LAN8742A PHY using these pins: * * STM32 F7 BOARD LAN8742A From 8289e3eb7cfd36bc96b9a4001610a2bfe5594159 Mon Sep 17 00:00:00 2001 From: David Sidrane Date: Fri, 17 Jun 2016 10:30:27 -1000 Subject: [PATCH 64/75] Updated F7 RCC to support all pll and config registers --- .../arm/src/stm32f7/chip/stm32f74xx75xx_rcc.h | 7 +- .../arm/src/stm32f7/chip/stm32f76xx77xx_rcc.h | 2 +- arch/arm/src/stm32f7/stm32f74xx75xx_rcc.c | 101 +++++++++++++++-- arch/arm/src/stm32f7/stm32f76xx77xx_rcc.c | 102 ++++++++++++++++-- 4 files changed, 193 insertions(+), 19 deletions(-) diff --git a/arch/arm/src/stm32f7/chip/stm32f74xx75xx_rcc.h b/arch/arm/src/stm32f7/chip/stm32f74xx75xx_rcc.h index 0cdc92c727..881f17dc56 100644 --- a/arch/arm/src/stm32f7/chip/stm32f74xx75xx_rcc.h +++ b/arch/arm/src/stm32f7/chip/stm32f74xx75xx_rcc.h @@ -1,8 +1,9 @@ /**************************************************************************************************** * arch/arm/src/stm32f7/chip/stm32f74xx75xx_rcc.h * - * Copyright (C) 2015 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Copyright (C) 2015-2016 Gregory Nutt. All rights reserved. + * Authors: Gregory Nutt + * David Sidrane * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions @@ -616,7 +617,7 @@ #define RCC_DCKCFGR1_SAI2SEL_SHIFT (22) /* Bits 22-23: SAI 2 clock source selection */ #define RCC_DCKCFGR1_SAI2SEL_MASK (0x3 << RCC_DCKCFGR1_SAI2SEL_SHIFT) # define RCC_DCKCFGR1_SAI2SEL(n) ((n) << RCC_DCKCFGR1_SAI2SEL_SHIFT) -#define RCC_DCKCFGR1_TIMPRE (1 << 24) /* Bit 24: Timer clock prescaler selection */ +#define RCC_DCKCFGR1_TIMPRESEL (1 << 24) /* Bit 24: Timer clock prescaler selection */ /* Dedicated clocks configuration register 2 */ diff --git a/arch/arm/src/stm32f7/chip/stm32f76xx77xx_rcc.h b/arch/arm/src/stm32f7/chip/stm32f76xx77xx_rcc.h index 23c8b2db0b..a63cc1911a 100644 --- a/arch/arm/src/stm32f7/chip/stm32f76xx77xx_rcc.h +++ b/arch/arm/src/stm32f7/chip/stm32f76xx77xx_rcc.h @@ -638,7 +638,7 @@ #define RCC_DCKCFGR1_SAI2SEL_SHIFT (22) /* Bits 22-23: SAI 2 clock source selection */ #define RCC_DCKCFGR1_SAI2SEL_MASK (0x3 << RCC_DCKCFGR1_SAI2SEL_SHIFT) # define RCC_DCKCFGR1_SAI2SEL(n) ((n) << RCC_DCKCFGR1_SAI2SEL_SHIFT) -#define RCC_DCKCFGR1_TIMPRE (1 << 24) /* Bit 24: Timer clock prescaler selection */ +#define RCC_DCKCFGR1_TIMPRESEL (1 << 24) /* Bit 24: Timer clock prescaler selection */ #define RCC_DCKCFGR1_DFSDM1SEL (1 << 25) /* Bit 25: DFSDM1 clock prescaler selection */ #define RCC_DCKCFGR1_ADFSDM1SEL (1 << 26) /* Bit 26: DFSDM1 AUDIO clock prescaler selection */ diff --git a/arch/arm/src/stm32f7/stm32f74xx75xx_rcc.c b/arch/arm/src/stm32f7/stm32f74xx75xx_rcc.c index 1db43d2551..7ae301548a 100644 --- a/arch/arm/src/stm32f7/stm32f74xx75xx_rcc.c +++ b/arch/arm/src/stm32f7/stm32f74xx75xx_rcc.c @@ -1,8 +1,9 @@ /**************************************************************************** * arch/arm/src/stm32f7/stm32f74xxx75xx_rcc.c * - * Copyright (C) 2015 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Copyright (C) 2016 Gregory Nutt. All rights reserved. + * Authors: Gregory Nutt + * David Sidrane * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions @@ -827,18 +828,38 @@ static void stm32_stdclockconfig(void) { } -#ifdef CONFIG_STM32F7_LTDC - /* Configure PLLSAI */ +#if defined(CONFIG_STM32F7_LTDC) || defined(CONFIG_STM32F7_PLLSAI) + + /* Configure PLLSAI */ regval = getreg32(STM32_RCC_PLLSAICFGR); + regval &= ~( RCC_PLLSAICFGR_PLLSAIN_MASK + | RCC_PLLSAICFGR_PLLSAIP_MASK + | RCC_PLLSAICFGR_PLLSAIQ_MASK + | RCC_PLLSAICFGR_PLLSAIR_MASK); regval |= (STM32_RCC_PLLSAICFGR_PLLSAIN - | STM32_RCC_PLLSAICFGR_PLLSAIR - | STM32_RCC_PLLSAICFGR_PLLSAIQ); + | STM32_RCC_PLLSAICFGR_PLLSAIP + | STM32_RCC_PLLSAICFGR_PLLSAIQ + | STM32_RCC_PLLSAICFGR_PLLSAIR); putreg32(regval, STM32_RCC_PLLSAICFGR); - regval = getreg32(STM32_RCC_DCKCFGR); - regval |= STM32_RCC_DCKCFGR_PLLSAIDIVR; - putreg32(regval, STM32_RCC_DCKCFGR); + regval = getreg32(STM32_RCC_DCKCFGR1); + regval &= ~(RCC_DCKCFGR1_PLLI2SDIVQ_MASK + | RCC_DCKCFGR1_PLLSAIDIVQ_MASK + | RCC_DCKCFGR1_PLLSAIDIVR_MASK + | RCC_DCKCFGR1_SAI1SEL_MASK + | RCC_DCKCFGR1_SAI2SEL_MASK + | RCC_DCKCFGR1_TIMPRESEL); + + regval |= (STM32_RCC_DCKCFGR1_PLLI2SDIVQ + | STM32_RCC_DCKCFGR1_PLLSAIDIVQ + | STM32_RCC_DCKCFGR1_PLLSAIDIVR + | STM32_RCC_DCKCFGR1_SAI1SRC + | STM32_RCC_DCKCFGR1_SAI2SRC + | STM32_RCC_DCKCFGR1_TIMPRESRC); + + putreg32(regval, STM32_RCC_DCKCFGR1); + /* Enable PLLSAI */ @@ -852,6 +873,68 @@ static void stm32_stdclockconfig(void) { } #endif +#if defined(CONFIG_STM32F7_LTDC) || defined(CONFIG_STM32F7_PLLI2S) + + /* Configure PLLI2S */ + + regval = getreg32(STM32_RCC_PLLI2SCFGR); + regval &= ~( RCC_PLLI2SCFGR_PLLI2SN_MASK + | RCC_PLLI2SCFGR_PLLI2SP_MASK + | RCC_PLLI2SCFGR_PLLI2SQ_MASK + | RCC_PLLI2SCFGR_PLLI2SR_MASK); + regval |= (STM32_RCC_PLLSAICFGR_PLLSAIN + | STM32_RCC_PLLSAICFGR_PLLSAIP + | STM32_RCC_PLLSAICFGR_PLLSAIQ + | STM32_RCC_PLLSAICFGR_PLLSAIR); + putreg32(regval, STM32_RCC_PLLI2SCFGR); + + regval = getreg32(STM32_RCC_DCKCFGR2); + regval &= ~( RCC_DCKCFGR2_USART1SEL_MASK + | RCC_DCKCFGR2_USART2SEL_MASK + | RCC_DCKCFGR2_UART4SEL_MASK + | RCC_DCKCFGR2_UART5SEL_MASK + | RCC_DCKCFGR2_USART6SEL_MASK + | RCC_DCKCFGR2_UART7SEL_MASK + | RCC_DCKCFGR2_UART8SEL_MASK + | RCC_DCKCFGR2_I2C1SEL_MASK + | RCC_DCKCFGR2_I2C2SEL_MASK + | RCC_DCKCFGR2_I2C3SEL_MASK + | RCC_DCKCFGR2_I2C4SEL_MASK + | RCC_DCKCFGR2_LPTIM1SEL_MASK + | RCC_DCKCFGR2_CECSEL_MASK + | RCC_DCKCFGR2_CK48MSEL_MASK + | RCC_DCKCFGR2_SDMMCSEL_MASK); + + regval |= ( STM32_RCC_DCKCFGR2_USART1SRC + | STM32_RCC_DCKCFGR2_USART2SRC + | STM32_RCC_DCKCFGR2_UART4SRC + | STM32_RCC_DCKCFGR2_UART5SRC + | STM32_RCC_DCKCFGR2_USART6SRC + | STM32_RCC_DCKCFGR2_UART7SRC + | STM32_RCC_DCKCFGR2_UART8SRC + | STM32_RCC_DCKCFGR2_I2C1SRC + | STM32_RCC_DCKCFGR2_I2C2SRC + | STM32_RCC_DCKCFGR2_I2C3SRC + | STM32_RCC_DCKCFGR2_I2C4SRC + | STM32_RCC_DCKCFGR2_LPTIM1SRC + | STM32_RCC_DCKCFGR2_CECSRC + | STM32_RCC_DCKCFGR2_CK48MSRC + | STM32_RCC_DCKCFGR2_SDMMCSRC); + + putreg32(regval, STM32_RCC_DCKCFGR2); + + /* Enable PLLI2S */ + + regval = getreg32(STM32_RCC_CR); + regval |= RCC_CR_PLLI2SON; + putreg32(regval, STM32_RCC_CR); + + /* Wait until the PLLI2S is ready */ + + while ((getreg32(STM32_RCC_CR) & RCC_CR_PLLI2SRDY) == 0) + { + } +#endif #if defined(CONFIG_STM32F7_IWDG) || defined(CONFIG_RTC_LSICLOCK) /* Low speed internal clock source LSI */ diff --git a/arch/arm/src/stm32f7/stm32f76xx77xx_rcc.c b/arch/arm/src/stm32f7/stm32f76xx77xx_rcc.c index 74d58b52ad..d24705d5fd 100644 --- a/arch/arm/src/stm32f7/stm32f76xx77xx_rcc.c +++ b/arch/arm/src/stm32f7/stm32f76xx77xx_rcc.c @@ -224,6 +224,7 @@ static inline void rcc_enableahb1(void) /* USB OTG HS */ regval |= RCC_AHB1ENR_OTGHSEN; + #endif /* CONFIG_STM32F7_OTGHS */ putreg32(regval, STM32_RCC_AHB1ENR); /* Enable peripherals */ @@ -823,18 +824,41 @@ static void stm32_stdclockconfig(void) { } -#ifdef CONFIG_STM32F7_LTDC +#if defined(CONFIG_STM32F7_LTDC) || defined(CONFIG_STM32F7_PLLSAI) + /* Configure PLLSAI */ regval = getreg32(STM32_RCC_PLLSAICFGR); + regval &= ~( RCC_PLLSAICFGR_PLLSAIN_MASK + | RCC_PLLSAICFGR_PLLSAIP_MASK + | RCC_PLLSAICFGR_PLLSAIQ_MASK + | RCC_PLLSAICFGR_PLLSAIR_MASK); regval |= (STM32_RCC_PLLSAICFGR_PLLSAIN - | STM32_RCC_PLLSAICFGR_PLLSAIR - | STM32_RCC_PLLSAICFGR_PLLSAIQ); + | STM32_RCC_PLLSAICFGR_PLLSAIP + | STM32_RCC_PLLSAICFGR_PLLSAIQ + | STM32_RCC_PLLSAICFGR_PLLSAIR); putreg32(regval, STM32_RCC_PLLSAICFGR); - regval = getreg32(STM32_RCC_DCKCFGR); - regval |= STM32_RCC_DCKCFGR_PLLSAIDIVR; - putreg32(regval, STM32_RCC_DCKCFGR); + regval = getreg32(STM32_RCC_DCKCFGR1); + regval &= ~(RCC_DCKCFGR1_PLLI2SDIVQ_MASK + | RCC_DCKCFGR1_PLLSAIDIVQ_MASK + | RCC_DCKCFGR1_PLLSAIDIVR_MASK + | RCC_DCKCFGR1_SAI1SEL_MASK + | RCC_DCKCFGR1_SAI2SEL_MASK + | RCC_DCKCFGR1_TIMPRESEL + | RCC_DCKCFGR1_DFSDM1SEL + | RCC_DCKCFGR1_ADFSDM1SEL); + + regval |= (STM32_RCC_DCKCFGR1_PLLI2SDIVQ + | STM32_RCC_DCKCFGR1_PLLSAIDIVQ + | STM32_RCC_DCKCFGR1_PLLSAIDIVR + | STM32_RCC_DCKCFGR1_SAI1SRC + | STM32_RCC_DCKCFGR1_SAI2SRC + | STM32_RCC_DCKCFGR1_TIMPRESRC + | STM32_RCC_DCKCFGR1_DFSDM1SRC + | STM32_RCC_DCKCFGR1_ADFSDM1SRC); + + putreg32(regval, STM32_RCC_DCKCFGR1); /* Enable PLLSAI */ @@ -848,6 +872,72 @@ static void stm32_stdclockconfig(void) { } #endif +#if defined(CONFIG_STM32F7_LTDC) || defined(CONFIG_STM32F7_PLLI2S) + + /* Configure PLLI2S */ + + regval = getreg32(STM32_RCC_PLLI2SCFGR); + regval &= ~( RCC_PLLI2SCFGR_PLLI2SN_MASK + | RCC_PLLI2SCFGR_PLLI2SP_MASK + | RCC_PLLI2SCFGR_PLLI2SQ_MASK + | RCC_PLLI2SCFGR_PLLI2SR_MASK); + regval |= (STM32_RCC_PLLSAICFGR_PLLSAIN + | STM32_RCC_PLLSAICFGR_PLLSAIP + | STM32_RCC_PLLSAICFGR_PLLSAIQ + | STM32_RCC_PLLSAICFGR_PLLSAIR); + putreg32(regval, STM32_RCC_PLLI2SCFGR); + + regval = getreg32(STM32_RCC_DCKCFGR2); + regval &= ~( RCC_DCKCFGR2_USART1SEL_MASK + | RCC_DCKCFGR2_USART2SEL_MASK + | RCC_DCKCFGR2_UART4SEL_MASK + | RCC_DCKCFGR2_UART5SEL_MASK + | RCC_DCKCFGR2_USART6SEL_MASK + | RCC_DCKCFGR2_UART7SEL_MASK + | RCC_DCKCFGR2_UART8SEL_MASK + | RCC_DCKCFGR2_I2C1SEL_MASK + | RCC_DCKCFGR2_I2C2SEL_MASK + | RCC_DCKCFGR2_I2C3SEL_MASK + | RCC_DCKCFGR2_I2C4SEL_MASK + | RCC_DCKCFGR2_LPTIM1SEL_MASK + | RCC_DCKCFGR2_CECSEL_MASK + | RCC_DCKCFGR2_CK48MSEL_MASK + | RCC_DCKCFGR2_SDMMCSEL_MASK + | RCC_DCKCFGR2_SDMMC2SEL_MASK + | RCC_DCKCFGR2_DSISELL_MASK); + + regval |= ( STM32_RCC_DCKCFGR2_USART1SRC + | STM32_RCC_DCKCFGR2_USART2SRC + | STM32_RCC_DCKCFGR2_UART4SRC + | STM32_RCC_DCKCFGR2_UART5SRC + | STM32_RCC_DCKCFGR2_USART6SRC + | STM32_RCC_DCKCFGR2_UART7SRC + | STM32_RCC_DCKCFGR2_UART8SRC + | STM32_RCC_DCKCFGR2_I2C1SRC + | STM32_RCC_DCKCFGR2_I2C2SRC + | STM32_RCC_DCKCFGR2_I2C3SRC + | STM32_RCC_DCKCFGR2_I2C4SRC + | STM32_RCC_DCKCFGR2_LPTIM1SRC + | STM32_RCC_DCKCFGR2_CECSRC + | STM32_RCC_DCKCFGR2_CK48MSRC + | STM32_RCC_DCKCFGR2_SDMMCSRC + | STM32_RCC_DCKCFGR2_SDMMC2SRC + | STM32_RCC_DCKCFGR2_DSISRC); + + putreg32(regval, STM32_RCC_DCKCFGR2); + + /* Enable PLLI2S */ + + regval = getreg32(STM32_RCC_CR); + regval |= RCC_CR_PLLI2SON; + putreg32(regval, STM32_RCC_CR); + + /* Wait until the PLLI2S is ready */ + + while ((getreg32(STM32_RCC_CR) & RCC_CR_PLLI2SRDY) == 0) + { + } +#endif #if defined(CONFIG_STM32F7_IWDG) || defined(CONFIG_RTC_LSICLOCK) /* Low speed internal clock source LSI */ From da51b4ecc024e06a7b8d522f05bde9cade4d0117 Mon Sep 17 00:00:00 2001 From: David Sidrane Date: Fri, 17 Jun 2016 10:32:11 -1000 Subject: [PATCH 65/75] Updated F7 I2C to support 4 devices and proper timing and configurations --- arch/arm/src/stm32f7/Kconfig | 45 +++ .../arm/src/stm32f7/chip/stm32f74xx77xx_i2c.h | 7 +- arch/arm/src/stm32f7/stm32_i2c.c | 273 ++++++++++++------ 3 files changed, 228 insertions(+), 97 deletions(-) diff --git a/arch/arm/src/stm32f7/Kconfig b/arch/arm/src/stm32f7/Kconfig index 1526d47825..5bcd7e55ab 100644 --- a/arch/arm/src/stm32f7/Kconfig +++ b/arch/arm/src/stm32f7/Kconfig @@ -1163,6 +1163,11 @@ config STM32F7_I2C3 default n select STM32F7_I2C +config STM32F7_I2C4 + bool "I2C4" + default n + select STM32F7_I2C + config STM32F7_LPTIM1 bool "Low-power timer 1" default n @@ -1666,6 +1671,46 @@ config STM32F7_SPI_DMA endmenu # "SPI Configuration" +menu "I2C Configuration" + depends on STM32F7_I2C + +config STM32F7_I2C_DYNTIMEO + bool "Use dynamic timeouts" + default n + depends on STM32F7_I2C + +config STM32F7_I2C_DYNTIMEO_USECPERBYTE + int "Timeout Microseconds per Byte" + default 500 + depends on STM32F7_I2C_DYNTIMEO + +config STM32F7_I2C_DYNTIMEO_STARTSTOP + int "Timeout for Start/Stop (Milliseconds)" + default 1000 + depends on STM32F7_I2C_DYNTIMEO + +config STM32F7_I2CTIMEOSEC + int "Timeout seconds" + default 0 + depends on STM32F7_I2C + +config STM32F7_I2CTIMEOMS + int "Timeout Milliseconds" + default 500 + depends on STM32F7_I2C && !STM32F7_I2C_DYNTIMEO + +config STM32F7_I2CTIMEOTICKS + int "Timeout for Done and Stop (ticks)" + default 500 + depends on STM32F7_I2C && !STM32F7_I2C_DYNTIMEO + +config STM32F7_I2C_DUTY16_9 + bool "Frequency with Tlow/Thigh = 16/9 " + default n + depends on STM32F7_I2C + +endmenu # "I2C Configuration" + config STM32F7_CUSTOM_CLOCKCONFIG bool "Custom clock configuration" default n diff --git a/arch/arm/src/stm32f7/chip/stm32f74xx77xx_i2c.h b/arch/arm/src/stm32f7/chip/stm32f74xx77xx_i2c.h index 28ac30a27c..7e76567001 100644 --- a/arch/arm/src/stm32f7/chip/stm32f74xx77xx_i2c.h +++ b/arch/arm/src/stm32f7/chip/stm32f74xx77xx_i2c.h @@ -134,7 +134,6 @@ #define I2C_CR1_RXDMAEN (1 << 15) /* Bit 15: DMA reception requests enable */ #define I2C_CR1_SBC (1 << 16) /* Bit 16: Slave byte control */ #define I2C_CR1_NOSTRETCH (1 << 17) /* Bit 17: Clock stretching disable */ -#define I2C_CR1_WUPEN (1 << 18) /* Bit 18: Wakeup from STOP enable */ #define I2C_CR1_GCEN (1 << 19) /* Bit 19: General call enable */ #define I2C_CR1_SMBHEN (1 << 20) /* Bit 20: SMBus Host address enable */ #define I2C_CR1_SMBDEN (1 << 21) /* Bit 21: SMBus Device Default address enable */ @@ -195,15 +194,15 @@ # define I2C_TIMINGR_SCLH(n) (((n)-1) << I2C_TIMINGR_SCLH_SHIFT) /* tSCLH = n x tPRESC */ #define I2C_TIMINGR_SDADEL_SHIFT (16) /* Bits 16-19: Data hold time */ -#define I2C_TIMINGR_SDADEL_MASK (15 << I2C_TIMINGR_SDADEL_SHIFT) +#define I2C_TIMINGR_SDADEL_MASK (0xf << I2C_TIMINGR_SDADEL_SHIFT) # define I2C_TIMINGR_SDADEL(n) ((n) << I2C_TIMINGR_SDADEL_SHIFT) /* tSDADEL= n x tPRESC */ #define I2C_TIMINGR_SCLDEL_SHIFT (20) /* Bits 20-23: Data setup time */ -#define I2C_TIMINGR_SCLDEL_MASK (15 << I2C_TIMINGR_SCLDEL_SHIFT) +#define I2C_TIMINGR_SCLDEL_MASK (0xf << I2C_TIMINGR_SCLDEL_SHIFT) # define I2C_TIMINGR_SCLDEL(n) (((n)-1) << I2C_TIMINGR_SCLDEL_SHIFT) /* tSCLDEL = n x tPRESC */ #define I2C_TIMINGR_PRESC_SHIFT (28) /* Bits 28-31: Timing prescaler */ -#define I2C_TIMINGR_PRESC_MASK (15 << I2C_TIMINGR_PRESC_SHIFT) +#define I2C_TIMINGR_PRESC_MASK (0xf << I2C_TIMINGR_PRESC_SHIFT) # define I2C_TIMINGR_PRESC(n) (((n)-1) << I2C_TIMINGR_PRESC_SHIFT) /* tPRESC = n x tI2CCLK */ /* Timeout register */ diff --git a/arch/arm/src/stm32f7/stm32_i2c.c b/arch/arm/src/stm32f7/stm32_i2c.c index b643dd9de4..53c144ca2b 100644 --- a/arch/arm/src/stm32f7/stm32_i2c.c +++ b/arch/arm/src/stm32f7/stm32_i2c.c @@ -52,17 +52,22 @@ * STM32 F7 I2C Driver * * Supports: - * - Master operation at up to 400Khz (Fast Mode) + * - Master operation: + * Standard-mode (up to 100 kHz) + * Fast-mode (up to 400 kHz) + * Fast-mode Plus (up to 1 MHz) + * fI2CCLK clock source selection is based on STM32_RCC_DCKCFGR2_I2CxSRC + * being set to HSI and the calulations are based on STM32_HSI_FREQUENCY + * of 16mHz + * * - Multiple instances (shared bus) * - Interrupt based operation * - RELOAD support * * Unsupported, possible future work: * - More effective error reporting to higher layers - * - Fast mode plus (1Mhz) * - Slave operation - * - Peripheral clock source selection (SYSCLK vs HSI) - * - Support of SYSCLK frequencies other than 8Mhz + * - Support of fI2CCLK frequencies other than 16Mhz * - Polled operation (code present but untested) * - SMBus support * - Multi-master support @@ -70,8 +75,7 @@ * * Test Environment: * - * - STM32F303VC on ST F3 Discovery Board (ST Part STM32F3DISCOVERY) - * 256K Flash, 40K SRAM available for all operations, 8K SRAM CCM + * - STM32F7676ZI on ST Nucleo-144 Board (ST Part STM32F429ZIT6) * * Operational Status: * @@ -83,18 +87,18 @@ * payloads has not been tested as the author lacked access to a real * device supporting these types of transfers. * - * Performance Benchmarks: + * Performance Benchmarks: TBD * * Time to transfer two messages, each a byte in length, in addition to the * START condition, in interrupt mode: * - * DEBUG enabled (development): 80ms + * DEBUG enabled (development): TBDms * Excessive delay here is caused by printing to the console and * is of no concern. * - * DEBUG disabled (production): 120us - * Between Messages: 38us - * Between Bytes: 7us + * DEBUG disabled (production): TBSus + * Between Messages: TBDus + * Between Bytes: TBDus * * Implementation: * @@ -153,48 +157,55 @@ * * To use this driver, enable the following configuration variable: * - * CONFIG_STM32F7_STM32F30XX + * One of: + * + * CONFIG_STM32F7_STM32F74XX + * CONFIG_STM32F7_STM32F75XX + * CONFIG_STM32F7_STM32F76XX + * CONFIG_STM32F7_STM32F77XX + * * * and one or more interfaces: * * CONFIG_STM32F7_I2C1 * CONFIG_STM32F7_I2C2 * CONFIG_STM32F7_I2C3 + * CONFIG_STM32F7_I2C4 * - * To configure the ISR timeout using fixed values (STM32_I2C_DYNTIMEO=n): + * To configure the ISR timeout using fixed values (CONFIG_STM32F7_I2C_DYNTIMEO=n): * - * CONFIG_STM32F7_I2CTIMEOMS (Timeout in milliseconds) * CONFIG_STM32F7_I2CTIMEOSEC (Timeout in seconds) + * CONFIG_STM32F7_I2CTIMEOMS (Timeout in milliseconds) * CONFIG_STM32F7_I2CTIMEOTICKS (Timeout in ticks) * - * To configure the ISR timeout using dynamic values (STM32_I2C_DYNTIMEO=y): + * To configure the ISR timeout using dynamic values (CONFIG_STM32F7_I2C_DYNTIMEO=y): * - * STM32_I2C_DYNTIMEO_USECPERBYTE (Timeout in microseconds per byte) - * STM32_I2C_DYNTIMEO_STARTSTOP (Timeout for start/stop in milliseconds) + * CONFIG_STM32F7_I2C_DYNTIMEO_USECPERBYTE (Timeout in microseconds per byte) + * CONFIG_STM32F7_I2C_DYNTIMEO_STARTSTOP (Timeout for start/stop in milliseconds) * * Debugging output enabled with: * - * CONFIG_DEBUG_I2C_INFO + * CONFIG_DEBUG_FEATURES and CONFIG_DEBUG_I2C_{ERROR|WARN|INFO} * * ISR Debugging output may be enabled with: * - * CONFIG_DEBUG_VERBOSE + * CONFIG_DEBUG_FEATURES and CONFIG_DEBUG_I2C_INFO * * ------------------------------------------------------------------------------ * * References: * * RM0316: - * ST STM32F303xB/C/D/E, etc. Reference Manual - * Document ID: DM00043574, Revision 6, August 2015. + * ST STM32F76xxx and STM32F77xxx Reference Manual + * Document ID: DocID028270 Revision 2, April 2016. * * DATASHEET: - * ST STM32F303xB/STM32F303xC Datasheet - * Document ID: DM00058181, Revision 12, December 2015. + * ST STM32F777xx/STM32F778Ax/STM32F779x Datasheet + * Document ID: DocID028294, Revision 3, May 2016. * - * 303ZYERRATA: - * STM32F303xB/C Rev Z and Y device limitations - * Document ID: DM00063985, Revision 7, September 2015. + * ERRATA: + * STM32F76xxx/STM32F77xxx Errata sheet Rev A device limitations + * Document ID: DocID028806, Revision 2, April 2016. * * I2CSPEC: * I2C Bus Specification and User Manual @@ -235,14 +246,40 @@ /* At least one I2C peripheral must be enabled */ -#if defined(CONFIG_STM32F7_I2C1) || defined(CONFIG_STM32F7_I2C2) || defined(CONFIG_STM32F7_I2C3) -/* This implementation is for the STM32 F1, F2, and F4 only */ - +#if defined(CONFIG_STM32F7_I2C1) || defined(CONFIG_STM32F7_I2C2) || \ + defined(CONFIG_STM32F7_I2C3) || defined(CONFIG_STM32F7_I2C4) /************************************************************************************ * Pre-processor Definitions ************************************************************************************/ +#undef INVALID_CLOCK_SOURCE + +#ifdef CONFIG_STM32F7_I2C1 +# if STM32_RCC_DCKCFGR2_I2C1SRC != RCC_DCKCFGR2_I2C1SEL_HSI +# warning "Clock Source STM32_RCC_DCKCFGR2_I2C1SRC must be HSI" +# define INVALID_CLOCK_SOURCE +# endif +#endif +#ifdef CONFIG_STM32F7_I2C1 +# if STM32_RCC_DCKCFGR2_I2C2SRC != RCC_DCKCFGR2_I2C2SEL_HSI +# warning "Clock Source STM32_RCC_DCKCFGR2_I2C2SRC must be HSI" +# define INVALID_CLOCK_SOURCE +# endif +#endif +#ifdef CONFIG_STM32F7_I2C3 +# if STM32_RCC_DCKCFGR2_I2C3SRC != RCC_DCKCFGR2_I2C3SEL_HSI +# warning "Clock Source STM32_RCC_DCKCFGR2_I2C3SRC must be HSI" +# define INVALID_CLOCK_SOURCE +# endif +#endif +#ifdef CONFIG_STM32F7_I2C4 +# if STM32_RCC_DCKCFGR2_I2C4SRC != RCC_DCKCFGR2_I2C4SEL_HSI +# warning "Clock Source STM32_RCC_DCKCFGR2_I2C4SRC must be HSI" +# define INVALID_CLOCK_SOURCE +# endif +#endif + /* CONFIG_I2C_POLLED may be set so that I2C interrupts will not be used. Instead, * CPU-intensive polling will be used. */ @@ -252,6 +289,7 @@ #if !defined(CONFIG_STM32F7_I2CTIMEOSEC) && !defined(CONFIG_STM32F7_I2CTIMEOMS) # define CONFIG_STM32F7_I2CTIMEOSEC 0 # define CONFIG_STM32F7_I2CTIMEOMS 500 /* Default is 500 milliseconds */ +# warning "Using Defualt 500 Ms Timeout" #elif !defined(CONFIG_STM32F7_I2CTIMEOSEC) # define CONFIG_STM32F7_I2CTIMEOSEC 0 /* User provided milliseconds */ #elif !defined(CONFIG_STM32F7_I2CTIMEOMS) @@ -276,12 +314,8 @@ #define MKI2C_OUTPUT(p) (((p) & (GPIO_PORT_MASK | GPIO_PIN_MASK)) | I2C_OUTPUT) -/* Register setting unique to the STM32F30xx */ - -#define I2C_CR1_TXRX \ - (I2C_CR1_RXIE | I2C_CR1_TXIE) -#define I2C_CR1_ALLINTS \ - (I2C_CR1_TXRX | I2C_CR1_TCIE | I2C_CR1_ERRIE) +#define I2C_CR1_TXRX (I2C_CR1_RXIE | I2C_CR1_TXIE) +#define I2C_CR1_ALLINTS (I2C_CR1_TXRX | I2C_CR1_TCIE | I2C_CR1_ERRIE) /* I2C event tracing * @@ -451,15 +485,18 @@ static inline void stm32_i2c_sendstop(FAR struct stm32_i2c_priv_s *priv); static inline uint32_t stm32_i2c_getstatus(FAR struct stm32_i2c_priv_s *priv); static int stm32_i2c_isr(struct stm32_i2c_priv_s * priv); #ifndef CONFIG_I2C_POLLED -#ifdef CONFIG_STM32F7_I2C1 +# ifdef CONFIG_STM32F7_I2C1 static int stm32_i2c1_isr(int irq, void *context); -#endif -#ifdef CONFIG_STM32F7_I2C2 +# endif +# ifdef CONFIG_STM32F7_I2C2 static int stm32_i2c2_isr(int irq, void *context); -#endif -#ifdef CONFIG_STM32F7_I2C3 +# endif +# ifdef CONFIG_STM32F7_I2C3 static int stm32_i2c3_isr(int irq, void *context); -#endif +# endif +# ifdef CONFIG_STM32F7_I2C4 +static int stm32_i2c4_isr(int irq, void *context); +# endif #endif static int stm32_i2c_init(FAR struct stm32_i2c_priv_s *priv); static int stm32_i2c_deinit(FAR struct stm32_i2c_priv_s *priv); @@ -566,6 +603,36 @@ struct stm32_i2c_priv_s stm32_i2c3_priv = }; #endif +#ifdef CONFIG_STM32F7_I2C4 +static const struct stm32_i2c_config_s stm32_i2c4_config = +{ + .base = STM32_I2C4_BASE, + .clk_bit = RCC_APB1ENR_I2C4EN, + .reset_bit = RCC_APB1RSTR_I2C4RST, + .scl_pin = GPIO_I2C4_SCL, + .sda_pin = GPIO_I2C4_SDA, +#ifndef CONFIG_I2C_POLLED + .isr = stm32_i2c4_isr, + .ev_irq = STM32_IRQ_I2C4EV, + .er_irq = STM32_IRQ_I2C4ER +#endif +}; + +struct stm32_i2c_priv_s stm32_i2c4_priv = +{ + .config = &stm32_i2c4_config, + .refs = 0, + .intstate = INTSTATE_IDLE, + .msgc = 0, + .msgv = NULL, + .ptr = NULL, + .frequency = 0, + .dcnt = 0, + .flags = 0, + .status = 0 +}; +#endif + /* Device Structures, Instantiation */ struct i2c_ops_s stm32_i2c_ops = @@ -1167,10 +1234,10 @@ static void stm32_i2c_tracedump(FAR struct stm32_i2c_priv_s *priv) * * This function supports bus clock frequencies of: * - * 500Khz - * 400Khz - * 100Khz - * 10Khz + * 1000Khz (Fast Mode+) + * 400Khz (Fast Mode) + * 100Khz (Standard Mode) + * 10Khz (Standard Mode) * * Attempts to set a different frequency will quietly provision the default * of 10Khz. @@ -1186,15 +1253,15 @@ static void stm32_i2c_tracedump(FAR struct stm32_i2c_priv_s *priv) * * Clock Selection: * - * The I2C peripheral clock can be provided by either SYSCLK or the HSI. + * The I2C peripheral clock can be provided by either PCLK1, SYSCLK or the HSI. * - * SYSCLK >------|\ I2CCLK - * | |---------> + * PCLK1 >------|\ I2CCLK + * SYSCLK >------| |---------> * HSI >------|/ * - * HSI is the default and is always 8Mhz. + * HSI is the default and is always 16Mhz. * - * SYSCLK can, in turn, be derived from the HSI, PLL or HSE. + * SYSCLK can, in turn, be derived from the HSI, HSE, PPLCLK. * * HSI >------|\ * | | SYSCLK @@ -1202,19 +1269,10 @@ static void stm32_i2c_tracedump(FAR struct stm32_i2c_priv_s *priv) * | | * HSE >------|/ * - * The ability to select the I2C peripheral clock source is not yet supported - * so all of this really only works at 8Mhz. The values provided are copied - * directly from the 8Mhz example table in RM0316 (See References). - * - * TODO: - * - * - Add support for peripheral clock source selection (SYSCLK vs HSI). - * - Calculate values for a given SYSCLK frequency. - * - Add support for Fast Mode Plus (up to 1Mhz) * * References: * - * RM0316: Section: 28.4.9: I2C_TIMINGR register configuration examples + * App Note AN4235 and the associated software STSW-STM32126. * ************************************************************************************/ @@ -1237,33 +1295,46 @@ static void stm32_i2c_setclock(FAR struct stm32_i2c_priv_s *priv, uint32_t frequ stm32_i2c_modifyreg32(priv, STM32_I2C_CR1_OFFSET, I2C_CR1_PE, 0); } - /* TODO: speed/timing calcs, at the moment 45Mhz = STM32_PCLK1_FREQUENCY, analog filter is on, - digital off from STM32F0-F3_AN4235_V1.0.1 */ + /* The Sppeed and timing calculation are based on the following + * fI2CCLK = HSI and is 16Mhz + * Analog filter is on, + * Digital filter off + * Rise Time is 120 ns and fall is 10ns + * Mode is FastMode + */ if (frequency == 100000) { - presc = 0x06; - scl_delay = 0x02; - sda_delay = 0x00; - scl_h_period = 0x1e; - scl_l_period = 0x2b; + presc = 0; + scl_delay = 3; + sda_delay = 0; + scl_h_period = 30; + scl_l_period = 120; } - else if (frequency == 400000) - { - presc = 0x00; - scl_delay = 0x0A; - sda_delay = 0x00; - scl_h_period = 0x1b; - scl_l_period = 0x5b; - } + else if (frequency == 400000) + { + presc = 0; + scl_delay = 3; + sda_delay = 9; + scl_h_period = 6; + scl_l_period = 24; + } + else if (frequency == 1000000) + { + presc = 0; + scl_delay = 2; + sda_delay = 0; + scl_h_period = 1; + scl_l_period = 5; + } else { - presc = 0x00; - scl_delay = 0x08; - sda_delay = 0x00; - scl_h_period = 0x09; - scl_l_period = 0x1c; + presc = 7; + scl_delay = 0; + sda_delay = 0; + scl_h_period = 35; + scl_l_period = 162; } uint32_t timingr = @@ -2069,12 +2140,12 @@ static int stm32_i2c_isr(struct stm32_i2c_priv_s *priv) ************************************************************************************/ #ifndef CONFIG_I2C_POLLED -#ifdef CONFIG_STM32F7_I2C1 +# ifdef CONFIG_STM32F7_I2C1 static int stm32_i2c1_isr(int irq, void *context) { return stm32_i2c_isr(&stm32_i2c1_priv); } -#endif +# endif /************************************************************************************ * Name: stm32_i2c2_isr @@ -2084,12 +2155,12 @@ static int stm32_i2c1_isr(int irq, void *context) * ************************************************************************************/ -#ifdef CONFIG_STM32F7_I2C2 +# ifdef CONFIG_STM32F7_I2C2 static int stm32_i2c2_isr(int irq, void *context) { return stm32_i2c_isr(&stm32_i2c2_priv); } -#endif +# endif /************************************************************************************ * Name: stm32_i2c3_isr @@ -2099,12 +2170,27 @@ static int stm32_i2c2_isr(int irq, void *context) * ************************************************************************************/ -#ifdef CONFIG_STM32F7_I2C3 +# ifdef CONFIG_STM32F7_I2C3 static int stm32_i2c3_isr(int irq, void *context) { return stm32_i2c_isr(&stm32_i2c3_priv); } -#endif +# endif + +/************************************************************************************ + * Name: stm32_i2c4_isr + * + * Description: + * I2C2 interrupt service routine + * + ************************************************************************************/ + +# ifdef CONFIG_STM32F7_I2C4 +static int stm32_i2c4_isr(int irq, void *context) +{ + return stm32_i2c_isr(&stm32_i2c4_priv); +} +# endif #endif /************************************************************************************ @@ -2465,13 +2551,9 @@ FAR struct i2c_master_s *stm32_i2cbus_initialize(int port) struct stm32_i2c_inst_s * inst = NULL; /* device, single instance */ int irqs; -#if STM32_PCLK1_FREQUENCY < 4000000 -# warning STM32_I2C_INIT: Peripheral clock must be at least 4 MHz to support 400 kHz operation. -#endif - -#if STM32_PCLK1_FREQUENCY < 2000000 -# warning STM32_I2C_INIT: Peripheral clock must be at least 2 MHz to support 100 kHz operation. - return NULL; +#if STM32_HSI_FREQUENCY != 16000000 || defined(INVALID_CLOCK_SOURCE) +# warning STM32_I2C_INIT: Peripheral clock is HSI and it must be 16mHz or the speed/timing calculations need to be redone. + return NULL; #endif /* Get I2C private structure */ @@ -2492,6 +2574,11 @@ FAR struct i2c_master_s *stm32_i2cbus_initialize(int port) case 3: priv = (struct stm32_i2c_priv_s *)&stm32_i2c3_priv; break; +#endif +#ifdef CONFIG_STM32F7_I2C4 + case 4: + priv = (struct stm32_i2c_priv_s *)&stm32_i2c4_priv; + break; #endif default: return NULL; From 540728af42294368ddea94a455babfe33f2e875a Mon Sep 17 00:00:00 2001 From: David Sidrane Date: Fri, 17 Jun 2016 10:38:51 -1000 Subject: [PATCH 66/75] Nucleo-144 update RCC and I2C --- configs/nucleo-144/include/board.h | 72 +++++++++++++++++++----------- 1 file changed, 45 insertions(+), 27 deletions(-) diff --git a/configs/nucleo-144/include/board.h b/configs/nucleo-144/include/board.h index b31d7b5a8b..fe10e5ebdd 100644 --- a/configs/nucleo-144/include/board.h +++ b/configs/nucleo-144/include/board.h @@ -111,7 +111,7 @@ * * PLL_VCO = (8,000,000 / 4) * 216 = 432 MHz * SYSCLK = 432 MHz / 2 = 216 MHz - * USB OTG FS, SDMMC and RNG Clock = 432 MHz / 9 = 48MHz + * USB OTG FS, SDMMC and RNG Clock = 432 MHz / 9 = 48 MHz */ #define STM32_PLLCFG_PLLM RCC_PLLCFG_PLLM(4) @@ -125,6 +125,7 @@ /* Configure factors for PLLSAI clock */ +#define CONFIG_STM32F7_PLLSAI 1 #define STM32_RCC_PLLSAICFGR_PLLSAIN RCC_PLLSAICFGR_PLLSAIN(192) #define STM32_RCC_PLLSAICFGR_PLLSAIP RCC_PLLSAICFGR_PLLSAIP(2) #define STM32_RCC_PLLSAICFGR_PLLSAIQ RCC_PLLSAICFGR_PLLSAIQ(2) @@ -132,16 +133,20 @@ /* Configure Dedicated Clock Configuration Register */ -#define STM32_RCC_DCKCFGR_PLLI2SDIVQ RCC_DCKCFGR_PLLI2SDIVQ(1) -#define STM32_RCC_DCKCFGR_PLLSAIDIVQ RCC_DCKCFGR_PLLSAIDIVQ(1) -#define STM32_RCC_DCKCFGR_SAI1SRC RCC_DCKCFGR_SAI1SRC_PLLSAI -#define STM32_RCC_DCKCFGR_SAI2SRC RCC_DCKCFGR_SAI2SRC_PLLSAI -#define STM32_RCC_DCKCFGR_TIMPRE 0 -#define STM32_RCC_DCKCFGR_I2S1SRC RCC_DCKCFGR_SAI1SRC_PLL -#define STM32_RCC_DCKCFGR_I2S2SRC RCC_DCKCFGR_SAI2SRC_PLL +#define STM32_RCC_DCKCFGR1_PLLI2SDIVQ RCC_DCKCFGR1_PLLI2SDIVQ(1) +#define STM32_RCC_DCKCFGR1_PLLSAIDIVQ RCC_DCKCFGR1_PLLSAIDIVQ(1) +#define STM32_RCC_DCKCFGR1_PLLSAIDIVR RCC_DCKCFGR1_PLLSAIDIVR(0) +#define STM32_RCC_DCKCFGR1_SAI1SRC RCC_DCKCFGR1_SAI1SEL(0) +#define STM32_RCC_DCKCFGR1_SAI2SRC RCC_DCKCFGR1_SAI2SEL(0) +#define STM32_RCC_DCKCFGR1_TIMPRESRC 0 +#define STM32_RCC_DCKCFGR1_DFSDM1SRC 0 +#define STM32_RCC_DCKCFGR1_ADFSDM1SRC 0 + + /* Configure factors for PLLI2S clock */ +#define CONFIG_STM32F7_PLLI2S 1 #define STM32_RCC_PLLI2SCFGR_PLLI2SN RCC_PLLI2SCFGR_PLLI2SN(192) #define STM32_RCC_PLLI2SCFGR_PLLI2SP RCC_PLLI2SCFGR_PLLI2SP(2) #define STM32_RCC_PLLI2SCFGR_PLLI2SQ RCC_PLLI2SCFGR_PLLI2SQ(2) @@ -149,11 +154,24 @@ /* Configure Dedicated Clock Configuration Register 2 */ -#define STM32_RCC_DCKCFGR2_FMPI2C1SEL RCC_DCKCFGR2_FMPI2C1SEL_APB -#define STM32_RCC_DCKCFGR2_CECSEL RCC_DCKCFGR2_CECSEL_HSI -#define STM32_RCC_DCKCFGR2_CK48MSEL RCC_DCKCFGR2_CK48MSEL_PLLSAI -#define STM32_RCC_DCKCFGR2_SDIOSEL RCC_DCKCFGR2_SDIOSEL_48MHZ -#define STM32_RCC_DCKCFGR2_SPDIFRXSEL RCC_DCKCFGR2_SPDIFRXSEL_PLL +#define STM32_RCC_DCKCFGR2_USART1SRC RCC_DCKCFGR2_USART1SEL_APB +#define STM32_RCC_DCKCFGR2_USART2SRC RCC_DCKCFGR2_USART2SEL_APB +#define STM32_RCC_DCKCFGR2_UART4SRC RCC_DCKCFGR2_UART4SEL_APB +#define STM32_RCC_DCKCFGR2_UART5SRC RCC_DCKCFGR2_UART5SEL_APB +#define STM32_RCC_DCKCFGR2_USART6SRC RCC_DCKCFGR2_USART6SEL_APB +#define STM32_RCC_DCKCFGR2_UART7SRC RCC_DCKCFGR2_UART7SEL_APB +#define STM32_RCC_DCKCFGR2_UART8SRC RCC_DCKCFGR2_UART8SEL_APB +#define STM32_RCC_DCKCFGR2_I2C1SRC RCC_DCKCFGR2_I2C1SEL_HSI +#define STM32_RCC_DCKCFGR2_I2C2SRC RCC_DCKCFGR2_I2C2SEL_HSI +#define STM32_RCC_DCKCFGR2_I2C3SRC RCC_DCKCFGR2_I2C3SEL_HSI +#define STM32_RCC_DCKCFGR2_I2C4SRC RCC_DCKCFGR2_I2C4SEL_HSI +#define STM32_RCC_DCKCFGR2_LPTIM1SRC RCC_DCKCFGR2_LPTIM1SEL_APB +#define STM32_RCC_DCKCFGR2_CECSRC RCC_DCKCFGR2_CECSEL_HSI +#define STM32_RCC_DCKCFGR2_CK48MSRC RCC_DCKCFGR2_CK48MSEL_PLLSAI +#define STM32_RCC_DCKCFGR2_SDMMCSRC RCC_DCKCFGR2_SDMMCSEL_48MHZ +#define STM32_RCC_DCKCFGR2_SDMMC2SRC RCC_DCKCFGR2_SDMMC2SEL_48MHZ +#define STM32_RCC_DCKCFGR2_DSISRC RCC_DCKCFGR2_DSISEL_48MHZ + /* Several prescalers allow the configuration of the two AHB buses, the * high-speed APB (APB2) and the low-speed APB (APB1) domains. The maximum @@ -321,17 +339,17 @@ /* SPI * * - * PA6 MISO CN12-13 - * PA7 MOSI CN12-15 - * PA5 SCK CN12-11 + * PA6 SPI1_MISO CN12-13 + * PA7 SPI1_MOSI CN12-15 + * PA5 SPI1_SCK CN12-11 * - * PB14 MISO CN12-28 - * PB15 MOSI CN12-26 - * PB10 SCK CN12-25 + * PB14 SPI2_MISO CN12-28 + * PB15 SPI2_MOSI CN12-26 + * PB13 SPI2_SCK CN12-30 * - * PB4 MISO CN12-27 - * PB5 MOSI CN12-29 - * PB3 SCK CN12-31 + * PB4 SPI3_MISO CN12-27 + * PB5 SPI3_MOSI CN12-29 + * PB3 SPI3_SCK CN12-31 */ #define GPIO_SPI1_MISO GPIO_SPI1_MISO_1 @@ -340,7 +358,7 @@ #define GPIO_SPI2_MISO GPIO_SPI2_MISO_1 #define GPIO_SPI2_MOSI GPIO_SPI2_MOSI_1 -#define GPIO_SPI2_SCK GPIO_SPI2_SCK_2 +#define GPIO_SPI2_SCK GPIO_SPI2_SCK_3 #define GPIO_SPI3_MISO GPIO_SPI3_MISO_1 #define GPIO_SPI3_MOSI GPIO_SPI3_MOSI_2 @@ -352,8 +370,8 @@ * PB8 I2C1_SCL CN12-3 * PB9 I2C1_SDA CN12-5 - * PF1 I2C2_SCL CN11-51 - * PF0 I2C2_SDA CN11-53 + * PB10 I2C2_SCL CN11-51 + * PB11 I2C2_SDA CN12-18 * * PA8 I2C3_SCL CN12-23 * PC9 I2C3_SDA CN12-1 @@ -363,8 +381,8 @@ #define GPIO_I2C1_SCL GPIO_I2C1_SCL_2 #define GPIO_I2C1_SDA GPIO_I2C1_SDA_2 -#define GPIO_I2C2_SCL GPIO_I2C2_SCL_2 -#define GPIO_I2C2_SDA GPIO_I2C2_SDA_2 +#define GPIO_I2C2_SCL GPIO_I2C2_SCL_1 +#define GPIO_I2C2_SDA GPIO_I2C2_SDA_1 #define GPIO_I2C3_SCL GPIO_I2C3_SCL_1 #define GPIO_I2C3_SDA GPIO_I2C3_SDA_1 From 63a3e2031026913e4b7db2eddf7336cc1bed3825 Mon Sep 17 00:00:00 2001 From: David Sidrane Date: Fri, 17 Jun 2016 11:16:16 -1000 Subject: [PATCH 67/75] Add RCC PLLs and CFG - Not tested --- configs/stm32f746-ws/include/board.h | 57 ++++++++++++++++++++++++---- 1 file changed, 49 insertions(+), 8 deletions(-) diff --git a/configs/stm32f746-ws/include/board.h b/configs/stm32f746-ws/include/board.h index 1f5e3f030c..6beed6753b 100644 --- a/configs/stm32f746-ws/include/board.h +++ b/configs/stm32f746-ws/include/board.h @@ -122,6 +122,55 @@ #define STM32_SYSCLK_FREQUENCY (STM32_VCO_FREQUENCY / 2) #define STM32_OTGFS_FREQUENCY (STM32_VCO_FREQUENCY / 9) +/* Configure factors for PLLSAI clock */ + + +#define STM32_RCC_PLLSAICFGR_PLLSAIN RCC_PLLSAICFGR_PLLSAIN(192) +#define STM32_RCC_PLLSAICFGR_PLLSAIP RCC_PLLSAICFGR_PLLSAIP(2) +#define STM32_RCC_PLLSAICFGR_PLLSAIQ RCC_PLLSAICFGR_PLLSAIQ(2) +#define STM32_RCC_PLLSAICFGR_PLLSAIR RCC_PLLSAICFGR_PLLSAIR(2) + +/* Configure Dedicated Clock Configuration Register */ + +#define STM32_RCC_DCKCFGR1_PLLI2SDIVQ RCC_DCKCFGR1_PLLI2SDIVQ(1) +#define STM32_RCC_DCKCFGR1_PLLSAIDIVQ RCC_DCKCFGR1_PLLSAIDIVQ(1) +#define STM32_RCC_DCKCFGR1_PLLSAIDIVR RCC_DCKCFGR1_PLLSAIDIVR(0) +#define STM32_RCC_DCKCFGR1_SAI1SRC RCC_DCKCFGR1_SAI1SEL(0) +#define STM32_RCC_DCKCFGR1_SAI2SRC RCC_DCKCFGR1_SAI2SEL(0) +#define STM32_RCC_DCKCFGR1_TIMPRESRC 0 +#define STM32_RCC_DCKCFGR1_DFSDM1SRC 0 +#define STM32_RCC_DCKCFGR1_ADFSDM1SRC 0 + + + +/* Configure factors for PLLI2S clock */ + +#define STM32_RCC_PLLI2SCFGR_PLLI2SN RCC_PLLI2SCFGR_PLLI2SN(192) +#define STM32_RCC_PLLI2SCFGR_PLLI2SP RCC_PLLI2SCFGR_PLLI2SP(2) +#define STM32_RCC_PLLI2SCFGR_PLLI2SQ RCC_PLLI2SCFGR_PLLI2SQ(2) +#define STM32_RCC_PLLI2SCFGR_PLLI2SR RCC_PLLI2SCFGR_PLLI2SR(2) + +/* Configure Dedicated Clock Configuration Register 2 */ + +#define STM32_RCC_DCKCFGR2_USART1SRC RCC_DCKCFGR2_USART1SEL_APB +#define STM32_RCC_DCKCFGR2_USART2SRC RCC_DCKCFGR2_USART2SEL_APB +#define STM32_RCC_DCKCFGR2_UART4SRC RCC_DCKCFGR2_UART4SEL_APB +#define STM32_RCC_DCKCFGR2_UART5SRC RCC_DCKCFGR2_UART5SEL_APB +#define STM32_RCC_DCKCFGR2_USART6SRC RCC_DCKCFGR2_USART6SEL_APB +#define STM32_RCC_DCKCFGR2_UART7SRC RCC_DCKCFGR2_UART7SEL_APB +#define STM32_RCC_DCKCFGR2_UART8SRC RCC_DCKCFGR2_UART8SEL_APB +#define STM32_RCC_DCKCFGR2_I2C1SRC RCC_DCKCFGR2_I2C1SEL_HSI +#define STM32_RCC_DCKCFGR2_I2C2SRC RCC_DCKCFGR2_I2C2SEL_HSI +#define STM32_RCC_DCKCFGR2_I2C3SRC RCC_DCKCFGR2_I2C3SEL_HSI +#define STM32_RCC_DCKCFGR2_I2C4SRC RCC_DCKCFGR2_I2C4SEL_HSI +#define STM32_RCC_DCKCFGR2_LPTIM1SRC RCC_DCKCFGR2_LPTIM1SEL_APB +#define STM32_RCC_DCKCFGR2_CECSRC RCC_DCKCFGR2_CECSEL_HSI +#define STM32_RCC_DCKCFGR2_CK48MSRC RCC_DCKCFGR2_CK48MSEL_PLLSAI +#define STM32_RCC_DCKCFGR2_SDMMCSRC RCC_DCKCFGR2_SDMMCSEL_48MHZ +#define STM32_RCC_DCKCFGR2_SDMMC2SRC RCC_DCKCFGR2_SDMMC2SEL_48MHZ +#define STM32_RCC_DCKCFGR2_DSISRC RCC_DCKCFGR2_DSISEL_48MHZ + + /* Several prescalers allow the configuration of the two AHB buses, the * high-speed APB (APB2) and the low-speed APB (APB1) domains. The maximum * frequency of the two AHB buses is 216 MHz while the maximum frequency of @@ -165,14 +214,6 @@ #define STM32_APB2_TIM10_CLKIN (2*STM32_PCLK2_FREQUENCY) #define STM32_APB2_TIM11_CLKIN (2*STM32_PCLK2_FREQUENCY) -/* Timer Frequencies, if APBx is set to 1, frequency is same to APBx - * otherwise frequency is 2xAPBx. - * Note: TIM1,8 are on APB2, others on APB1 - */ - -#define STM32_TIM18_FREQUENCY (2*STM32_PCLK2_FREQUENCY) -#define STM32_TIM27_FREQUENCY (2*STM32_PCLK1_FREQUENCY) - /* FLASH wait states * * --------- ---------- ----------- From 86374ed3e5c4ce741ec130912736883b8855012d Mon Sep 17 00:00:00 2001 From: David Sidrane Date: Fri, 17 Jun 2016 11:16:24 -1000 Subject: [PATCH 68/75] Add RCC PLLs and CFG - Not tested --- configs/stm32f746g-disco/include/board.h | 47 ++++++++++++++++++++++++ 1 file changed, 47 insertions(+) diff --git a/configs/stm32f746g-disco/include/board.h b/configs/stm32f746g-disco/include/board.h index 6e9da62de0..9482371499 100644 --- a/configs/stm32f746g-disco/include/board.h +++ b/configs/stm32f746g-disco/include/board.h @@ -154,6 +154,53 @@ #define STM32_OTGFS_FREQUENCY (STM32_VCO_FREQUENCY / 10) #endif +/* Configure factors for PLLSAI clock */ + +#define STM32_RCC_PLLSAICFGR_PLLSAIN RCC_PLLSAICFGR_PLLSAIN(192) +#define STM32_RCC_PLLSAICFGR_PLLSAIP RCC_PLLSAICFGR_PLLSAIP(2) +#define STM32_RCC_PLLSAICFGR_PLLSAIQ RCC_PLLSAICFGR_PLLSAIQ(2) +#define STM32_RCC_PLLSAICFGR_PLLSAIR RCC_PLLSAICFGR_PLLSAIR(2) + +/* Configure Dedicated Clock Configuration Register */ + +#define STM32_RCC_DCKCFGR1_PLLI2SDIVQ RCC_DCKCFGR1_PLLI2SDIVQ(1) +#define STM32_RCC_DCKCFGR1_PLLSAIDIVQ RCC_DCKCFGR1_PLLSAIDIVQ(1) +#define STM32_RCC_DCKCFGR1_PLLSAIDIVR RCC_DCKCFGR1_PLLSAIDIVR(0) +#define STM32_RCC_DCKCFGR1_SAI1SRC RCC_DCKCFGR1_SAI1SEL(0) +#define STM32_RCC_DCKCFGR1_SAI2SRC RCC_DCKCFGR1_SAI2SEL(0) +#define STM32_RCC_DCKCFGR1_TIMPRESRC 0 +#define STM32_RCC_DCKCFGR1_DFSDM1SRC 0 +#define STM32_RCC_DCKCFGR1_ADFSDM1SRC 0 + + + +/* Configure factors for PLLI2S clock */ + +#define STM32_RCC_PLLI2SCFGR_PLLI2SN RCC_PLLI2SCFGR_PLLI2SN(192) +#define STM32_RCC_PLLI2SCFGR_PLLI2SP RCC_PLLI2SCFGR_PLLI2SP(2) +#define STM32_RCC_PLLI2SCFGR_PLLI2SQ RCC_PLLI2SCFGR_PLLI2SQ(2) +#define STM32_RCC_PLLI2SCFGR_PLLI2SR RCC_PLLI2SCFGR_PLLI2SR(2) + +/* Configure Dedicated Clock Configuration Register 2 */ + +#define STM32_RCC_DCKCFGR2_USART1SRC RCC_DCKCFGR2_USART1SEL_APB +#define STM32_RCC_DCKCFGR2_USART2SRC RCC_DCKCFGR2_USART2SEL_APB +#define STM32_RCC_DCKCFGR2_UART4SRC RCC_DCKCFGR2_UART4SEL_APB +#define STM32_RCC_DCKCFGR2_UART5SRC RCC_DCKCFGR2_UART5SEL_APB +#define STM32_RCC_DCKCFGR2_USART6SRC RCC_DCKCFGR2_USART6SEL_APB +#define STM32_RCC_DCKCFGR2_UART7SRC RCC_DCKCFGR2_UART7SEL_APB +#define STM32_RCC_DCKCFGR2_UART8SRC RCC_DCKCFGR2_UART8SEL_APB +#define STM32_RCC_DCKCFGR2_I2C1SRC RCC_DCKCFGR2_I2C1SEL_HSI +#define STM32_RCC_DCKCFGR2_I2C2SRC RCC_DCKCFGR2_I2C2SEL_HSI +#define STM32_RCC_DCKCFGR2_I2C3SRC RCC_DCKCFGR2_I2C3SEL_HSI +#define STM32_RCC_DCKCFGR2_I2C4SRC RCC_DCKCFGR2_I2C4SEL_HSI +#define STM32_RCC_DCKCFGR2_LPTIM1SRC RCC_DCKCFGR2_LPTIM1SEL_APB +#define STM32_RCC_DCKCFGR2_CECSRC RCC_DCKCFGR2_CECSEL_HSI +#define STM32_RCC_DCKCFGR2_CK48MSRC RCC_DCKCFGR2_CK48MSEL_PLLSAI +#define STM32_RCC_DCKCFGR2_SDMMCSRC RCC_DCKCFGR2_SDMMCSEL_48MHZ +#define STM32_RCC_DCKCFGR2_SDMMC2SRC RCC_DCKCFGR2_SDMMC2SEL_48MHZ +#define STM32_RCC_DCKCFGR2_DSISRC RCC_DCKCFGR2_DSISEL_48MHZ + /* Several prescalers allow the configuration of the two AHB buses, the * high-speed APB (APB2) and the low-speed APB (APB1) domains. The maximum * frequency of the two AHB buses is 216 MHz while the maximum frequency of From 64b1d4e31466ca7a3caed505a253c8e0252ec008 Mon Sep 17 00:00:00 2001 From: David Sidrane Date: Fri, 17 Jun 2016 11:38:21 -1000 Subject: [PATCH 69/75] Updated For STM32F746G-DISCO --- configs/Kconfig | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/configs/Kconfig b/configs/Kconfig index 2cd2d68c44..75014db5fd 100644 --- a/configs/Kconfig +++ b/configs/Kconfig @@ -1013,7 +1013,7 @@ config ARCH_BOARD_STM32F746_WS Waveshare STM32F746 development board featuring the STM32F746IG MCU. config ARCH_BOARD_STM32L476VG_DISCO - bool "STMicro STM32F746VG-Discovery board" + bool "STMicro STM32L476VG -Discovery board" depends on ARCH_CHIP_STM32L476RG select ARCH_HAVE_LEDS select ARCH_HAVE_BUTTONS From 4416561c46b9234e2cc9a999216772305154d533 Mon Sep 17 00:00:00 2001 From: David Sidrane Date: Fri, 17 Jun 2016 11:39:55 -1000 Subject: [PATCH 70/75] Refreashed STM32F746G-DISCO config --- configs/stm32f746g-disco/nsh/defconfig | 180 ++++++++++++++++++++----- 1 file changed, 150 insertions(+), 30 deletions(-) diff --git a/configs/stm32f746g-disco/nsh/defconfig b/configs/stm32f746g-disco/nsh/defconfig index 564d647ad2..421cf40372 100644 --- a/configs/stm32f746g-disco/nsh/defconfig +++ b/configs/stm32f746g-disco/nsh/defconfig @@ -20,7 +20,7 @@ CONFIG_WINDOWS_CYGWIN=y # # Build Configuration # -# CONFIG_APPS_DIR="../apps" +CONFIG_APPS_DIR="../apps" CONFIG_BUILD_FLAT=y # CONFIG_BUILD_2PASS is not set @@ -80,6 +80,7 @@ CONFIG_ARCH="arm" # CONFIG_ARCH_CHIP_DM320 is not set # CONFIG_ARCH_CHIP_EFM32 is not set # CONFIG_ARCH_CHIP_IMX1 is not set +# CONFIG_ARCH_CHIP_IMX6 is not set # CONFIG_ARCH_CHIP_KINETIS is not set # CONFIG_ARCH_CHIP_KL is not set # CONFIG_ARCH_CHIP_LM is not set @@ -98,6 +99,7 @@ CONFIG_ARCH="arm" # CONFIG_ARCH_CHIP_SAMV7 is not set # CONFIG_ARCH_CHIP_STM32 is not set CONFIG_ARCH_CHIP_STM32F7=y +# CONFIG_ARCH_CHIP_STM32L4 is not set # CONFIG_ARCH_CHIP_STR71X is not set # CONFIG_ARCH_CHIP_TMS570 is not set # CONFIG_ARCH_CHIP_MOXART is not set @@ -119,14 +121,16 @@ CONFIG_ARCH_CORTEXM7=y # CONFIG_ARCH_CORTEXR7F is not set CONFIG_ARCH_FAMILY="armv7-m" CONFIG_ARCH_CHIP="stm32f7" +# CONFIG_ARM_TOOLCHAIN_IAR is not set CONFIG_ARM_TOOLCHAIN_GNU=y # CONFIG_ARMV7M_USEBASEPRI is not set CONFIG_ARCH_HAVE_CMNVECTOR=y CONFIG_ARMV7M_CMNVECTOR=y # CONFIG_ARMV7M_LAZYFPU is not set CONFIG_ARCH_HAVE_FPU=y -CONFIG_ARCH_HAVE_DPFPU=y +# CONFIG_ARCH_HAVE_DPFPU is not set # CONFIG_ARCH_FPU is not set +# CONFIG_ARCH_HAVE_TRUSTZONE is not set CONFIG_ARM_HAVE_MPU_UNIFIED=y # CONFIG_ARM_MPU is not set @@ -142,34 +146,134 @@ CONFIG_ARMV7M_HAVE_ITCM=y CONFIG_ARMV7M_HAVE_DTCM=y # CONFIG_ARMV7M_ITCM is not set CONFIG_ARMV7M_DTCM=y +# CONFIG_ARMV7M_TOOLCHAIN_IARW is not set # CONFIG_ARMV7M_TOOLCHAIN_ATOLLIC is not set # CONFIG_ARMV7M_TOOLCHAIN_BUILDROOT is not set # CONFIG_ARMV7M_TOOLCHAIN_CODEREDW is not set # CONFIG_ARMV7M_TOOLCHAIN_CODESOURCERYW is not set # CONFIG_ARMV7M_TOOLCHAIN_DEVKITARM is not set -# CONFIG_ARMV7M_TOOLCHAIN_GNU_EABIL is not set -CONFIG_ARMV7M_TOOLCHAIN_GNU_EABIW=y +CONFIG_ARMV7M_TOOLCHAIN_GNU_EABIL=y +# CONFIG_ARMV7M_TOOLCHAIN_GNU_EABIW is not set # CONFIG_ARMV7M_TOOLCHAIN_RAISONANCE is not set CONFIG_ARMV7M_HAVE_STACKCHECK=y # CONFIG_ARMV7M_STACKCHECK is not set # CONFIG_ARMV7M_ITMSYSLOG is not set # CONFIG_SERIAL_TERMIOS is not set +# CONFIG_USART6_RS485 is not set +# CONFIG_SERIAL_DISABLE_REORDERING is not set # # STM32 F7 Configuration Options # -# CONFIG_ARCH_CHIP_STM32F745 is not set -CONFIG_ARCH_CHIP_STM32F746=y -# CONFIG_ARCH_CHIP_STM32F756 is not set +# CONFIG_ARCH_CHIP_STM32F745VG is not set +# CONFIG_ARCH_CHIP_STM32F745VE is not set +# CONFIG_ARCH_CHIP_STM32F745IG is not set +# CONFIG_ARCH_CHIP_STM32F745IE is not set +# CONFIG_ARCH_CHIP_STM32F745ZE is not set +# CONFIG_ARCH_CHIP_STM32F745ZG is not set +# CONFIG_ARCH_CHIP_STM32F746BG is not set +# CONFIG_ARCH_CHIP_STM32F746VG is not set +# CONFIG_ARCH_CHIP_STM32F746VE is not set +# CONFIG_ARCH_CHIP_STM32F746BE is not set +# CONFIG_ARCH_CHIP_STM32F746ZG is not set +# CONFIG_ARCH_CHIP_STM32F746IE is not set +CONFIG_ARCH_CHIP_STM32F746NG=y +# CONFIG_ARCH_CHIP_STM32F746NE is not set +# CONFIG_ARCH_CHIP_STM32F746ZE is not set +# CONFIG_ARCH_CHIP_STM32F746IG is not set +# CONFIG_ARCH_CHIP_STM32F756NG is not set +# CONFIG_ARCH_CHIP_STM32F756BG is not set +# CONFIG_ARCH_CHIP_STM32F756IG is not set +# CONFIG_ARCH_CHIP_STM32F756VG is not set +# CONFIG_ARCH_CHIP_STM32F756ZG is not set +# CONFIG_ARCH_CHIP_STM32F765NI is not set +# CONFIG_ARCH_CHIP_STM32F765VI is not set +# CONFIG_ARCH_CHIP_STM32F765VG is not set +# CONFIG_ARCH_CHIP_STM32F765BI is not set +# CONFIG_ARCH_CHIP_STM32F765NG is not set +# CONFIG_ARCH_CHIP_STM32F765ZG is not set +# CONFIG_ARCH_CHIP_STM32F765ZI is not set +# CONFIG_ARCH_CHIP_STM32F765IG is not set +# CONFIG_ARCH_CHIP_STM32F765BG is not set +# CONFIG_ARCH_CHIP_STM32F765II is not set +# CONFIG_ARCH_CHIP_STM32F767NG is not set +# CONFIG_ARCH_CHIP_STM32F767IG is not set +# CONFIG_ARCH_CHIP_STM32F767VG is not set +# CONFIG_ARCH_CHIP_STM32F767ZG is not set +# CONFIG_ARCH_CHIP_STM32F767NI is not set +# CONFIG_ARCH_CHIP_STM32F767VI is not set +# CONFIG_ARCH_CHIP_STM32F767BG is not set +# CONFIG_ARCH_CHIP_STM32F767ZI is not set +# CONFIG_ARCH_CHIP_STM32F767II is not set +# CONFIG_ARCH_CHIP_STM32F769BI is not set +# CONFIG_ARCH_CHIP_STM32F769II is not set +# CONFIG_ARCH_CHIP_STM32F769BG is not set +# CONFIG_ARCH_CHIP_STM32F769NI is not set +# CONFIG_ARCH_CHIP_STM32F769AI is not set +# CONFIG_ARCH_CHIP_STM32F769NG is not set +# CONFIG_ARCH_CHIP_STM32F769IG is not set +# CONFIG_ARCH_CHIP_STM32F777ZI is not set +# CONFIG_ARCH_CHIP_STM32F777VI is not set +# CONFIG_ARCH_CHIP_STM32F777NI is not set +# CONFIG_ARCH_CHIP_STM32F777BI is not set +# CONFIG_ARCH_CHIP_STM32F777II is not set +# CONFIG_ARCH_CHIP_STM32F778AI is not set +# CONFIG_ARCH_CHIP_STM32F779II is not set +# CONFIG_ARCH_CHIP_STM32F779NI is not set +# CONFIG_ARCH_CHIP_STM32F779BI is not set +# CONFIG_ARCH_CHIP_STM32F779AI is not set CONFIG_STM32F7_STM32F74XX=y # CONFIG_STM32F7_STM32F75XX is not set -# CONFIG_STM32F7_FLASH_512KB is not set -CONFIG_STM32F7_FLASH_1024KB=y +# CONFIG_STM32F7_STM32F76XX is not set +# CONFIG_STM32F7_STM32F77XX is not set +# CONFIG_STM32F7_IO_CONFIG_V is not set +# CONFIG_STM32F7_IO_CONFIG_I is not set +# CONFIG_STM32F7_IO_CONFIG_Z is not set +CONFIG_STM32F7_IO_CONFIG_N=y +# CONFIG_STM32F7_IO_CONFIG_B is not set +# CONFIG_STM32F7_IO_CONFIG_A is not set +# CONFIG_STM32F7_STM32F745XX is not set +CONFIG_STM32F7_STM32F746XX=y +# CONFIG_STM32F7_STM32F756XX is not set +# CONFIG_STM32F7_STM32F765XX is not set +# CONFIG_STM32F7_STM32F767XX is not set +# CONFIG_STM32F7_STM32F768XX is not set +# CONFIG_STM32F7_STM32F768AX is not set +# CONFIG_STM32F7_STM32F769XX is not set +# CONFIG_STM32F7_STM32F769AX is not set +# CONFIG_STM32F7_STM32F777XX is not set +# CONFIG_STM32F7_STM32F778XX is not set +# CONFIG_STM32F7_STM32F778AX is not set +# CONFIG_STM32F7_STM32F779XX is not set +# CONFIG_STM32F7_STM32F779AX is not set +# CONFIG_STM32F7_FLASH_CONFIG_E is not set +# CONFIG_STM32F7_FLASH_CONFIG_I is not set +CONFIG_STM32F7_FLASH_OVERRIDE_DEFAULT=y +# CONFIG_STM32F7_FLASH_OVERRIDE_E is not set +# CONFIG_STM32F7_FLASH_OVERRIDE_G is not set +# CONFIG_STM32F7_FLASH_OVERRIDE_I is not set # # STM32 Peripheral Support # CONFIG_STM32F7_HAVE_LTDC=y +CONFIG_STM32F7_HAVE_FSMC=y +CONFIG_STM32F7_HAVE_ETHRNET=y +CONFIG_STM32F7_HAVE_RNG=y +CONFIG_STM32F7_HAVE_SPI5=y +CONFIG_STM32F7_HAVE_SPI6=y +# CONFIG_STM32F7_HAVE_SDMMC2 is not set +# CONFIG_STM32F7_HAVE_ADC1_DMA is not set +# CONFIG_STM32F7_HAVE_ADC2_DMA is not set +# CONFIG_STM32F7_HAVE_ADC3_DMA is not set +# CONFIG_STM32F7_HAVE_CAN3 is not set +CONFIG_STM32F7_HAVE_DCMI=y +# CONFIG_STM32F7_HAVE_DSIHOST is not set +CONFIG_STM32F7_HAVE_DMA2D=y +# CONFIG_STM32F7_HAVE_JPEG is not set +# CONFIG_STM32F7_HAVE_CRYP is not set +# CONFIG_STM32F7_HAVE_HASH is not set +# CONFIG_STM32F7_HAVE_DFSDM1 is not set # CONFIG_STM32F7_ADC is not set # CONFIG_STM32F7_CAN is not set # CONFIG_STM32F7_DAC is not set @@ -177,34 +281,34 @@ CONFIG_STM32F7_HAVE_LTDC=y # CONFIG_STM32F7_I2C is not set # CONFIG_STM32F7_SAI is not set # CONFIG_STM32F7_SPI is not set +# CONFIG_STM32F7_TIM is not set CONFIG_STM32F7_USART=y # CONFIG_STM32F7_ADC1 is not set -# CONFIG_STM32F7_ADC2 is not set # CONFIG_STM32F7_ADC3 is not set # CONFIG_STM32F7_BKPSRAM is not set # CONFIG_STM32F7_CAN1 is not set # CONFIG_STM32F7_CAN2 is not set # CONFIG_STM32F7_CEC is not set # CONFIG_STM32F7_CRC is not set -# CONFIG_STM32F7_CRYP is not set # CONFIG_STM32F7_DMA1 is not set # CONFIG_STM32F7_DMA2 is not set # CONFIG_STM32F7_DAC1 is not set # CONFIG_STM32F7_DAC2 is not set # CONFIG_STM32F7_DCMI is not set +# CONFIG_STM32F7_DMA2D is not set # CONFIG_STM32F7_ETHMAC is not set # CONFIG_STM32F7_FSMC is not set # CONFIG_STM32F7_I2C1 is not set # CONFIG_STM32F7_I2C2 is not set # CONFIG_STM32F7_I2C3 is not set +# CONFIG_STM32F7_I2C4 is not set # CONFIG_STM32F7_LPTIM1 is not set # CONFIG_STM32F7_LTDC is not set -# CONFIG_STM32F7_DMA2D is not set # CONFIG_STM32F7_OTGFS is not set # CONFIG_STM32F7_OTGHS is not set # CONFIG_STM32F7_QUADSPI is not set -# CONFIG_STM32F7_SAI1 is not set # CONFIG_STM32F7_RNG is not set +# CONFIG_STM32F7_SAI1 is not set # CONFIG_STM32F7_SAI2 is not set # CONFIG_STM32F7_SDMMC1 is not set # CONFIG_STM32F7_SPDIFRX is not set @@ -228,7 +332,6 @@ CONFIG_STM32F7_USART=y # CONFIG_STM32F7_TIM12 is not set # CONFIG_STM32F7_TIM13 is not set # CONFIG_STM32F7_TIM14 is not set -# CONFIG_STM32F7_TIM15 is not set # CONFIG_STM32F7_USART1 is not set # CONFIG_STM32F7_USART2 is not set # CONFIG_STM32F7_USART3 is not set @@ -239,8 +342,18 @@ CONFIG_STM32F7_USART6=y # CONFIG_STM32F7_UART8 is not set # CONFIG_STM32F7_IWDG is not set # CONFIG_STM32F7_WWDG is not set + +# +# U[S]ART Configuration +# +# CONFIG_STM32F7_FLOWCONTROL_BROKEN is not set +# CONFIG_STM32F7_USART_BREAKS is not set # CONFIG_STM32F7_CUSTOM_CLOCKCONFIG is not set +# +# Timer Configuration +# + # # Architecture Options # @@ -452,6 +565,8 @@ CONFIG_SPI_EXCHANGE=y # CONFIG_SPI_BITBANG is not set # CONFIG_SPI_HWFEATURES is not set # CONFIG_SPI_CRCGENERATION is not set +# CONFIG_SPI_CS_CONTROL is not set +# CONFIG_SPI_CS_DELAY_CONTROL is not set # CONFIG_I2S is not set # @@ -466,7 +581,12 @@ CONFIG_SPI_EXCHANGE=y # CONFIG_BCH is not set # CONFIG_INPUT is not set # CONFIG_IOEXPANDER is not set + +# +# LCD Driver Support +# # CONFIG_LCD is not set +# CONFIG_SLCD is not set # # LED Support @@ -474,6 +594,7 @@ CONFIG_SPI_EXCHANGE=y # CONFIG_USERLED is not set # CONFIG_RGBLED is not set # CONFIG_PCA9635PW is not set +# CONFIG_NCP5623C is not set # CONFIG_MMCSD is not set # CONFIG_MODEM is not set # CONFIG_MTD is not set @@ -508,10 +629,6 @@ CONFIG_USART6_SERIALDRIVER=y # CONFIG_USART7_SERIALDRIVER is not set # CONFIG_USART8_SERIALDRIVER is not set # CONFIG_OTHER_UART_SERIALDRIVER is not set - -# -# USART Configuration -# CONFIG_MCU_SERIAL=y CONFIG_STANDARD_SERIAL=y # CONFIG_SERIAL_IFLOWCONTROL is not set @@ -655,11 +772,14 @@ CONFIG_ARCH_LOWPUTC=y CONFIG_LIB_SENDFILE_BUFSIZE=512 # CONFIG_ARCH_ROMGETC is not set # CONFIG_ARCH_OPTIMIZED_FUNCTIONS is not set +CONFIG_ARCH_HAVE_TLS=y +# CONFIG_TLS is not set # CONFIG_LIBC_NETDB is not set # # Non-standard Library Support # +# CONFIG_LIB_CRC64_FAST is not set # CONFIG_LIB_KBDCODEC is not set # CONFIG_LIB_SLCDCODEC is not set @@ -703,10 +823,10 @@ CONFIG_BUILTIN_PROXY_STACKSIZE=1024 # CONFIG_EXAMPLES_FTPD is not set # CONFIG_EXAMPLES_HELLO is not set # CONFIG_EXAMPLES_HELLOXX is not set -# CONFIG_EXAMPLES_JSON is not set # CONFIG_EXAMPLES_HIDKBD is not set -# CONFIG_EXAMPLES_KEYPADTEST is not set # CONFIG_EXAMPLES_IGMP is not set +# CONFIG_EXAMPLES_JSON is not set +# CONFIG_EXAMPLES_KEYPADTEST is not set # CONFIG_EXAMPLES_MEDIA is not set # CONFIG_EXAMPLES_MM is not set # CONFIG_EXAMPLES_MODBUS is not set @@ -715,18 +835,18 @@ CONFIG_BUILTIN_PROXY_STACKSIZE=1024 CONFIG_EXAMPLES_NSH=y CONFIG_EXAMPLES_NSH_CXXINITIALIZE=y # CONFIG_EXAMPLES_NULL is not set -# CONFIG_EXAMPLES_NX is not set -# CONFIG_EXAMPLES_NXTERM is not set # CONFIG_EXAMPLES_NXFFS is not set # CONFIG_EXAMPLES_NXHELLO is not set # CONFIG_EXAMPLES_NXIMAGE is not set +# CONFIG_EXAMPLES_NX is not set # CONFIG_EXAMPLES_NXLINES is not set +# CONFIG_EXAMPLES_NXTERM is not set # CONFIG_EXAMPLES_NXTEXT is not set # CONFIG_EXAMPLES_OSTEST is not set # CONFIG_EXAMPLES_PCA9635 is not set # CONFIG_EXAMPLES_PIPE is not set -# CONFIG_EXAMPLES_PPPD is not set # CONFIG_EXAMPLES_POSIXSPAWN is not set +# CONFIG_EXAMPLES_PPPD is not set # CONFIG_EXAMPLES_RGBLED is not set # CONFIG_EXAMPLES_RGMP is not set # CONFIG_EXAMPLES_SENDMAIL is not set @@ -734,17 +854,16 @@ CONFIG_EXAMPLES_NSH_CXXINITIALIZE=y # CONFIG_EXAMPLES_SERIALRX is not set # CONFIG_EXAMPLES_SERLOOP is not set # CONFIG_EXAMPLES_SLCD is not set -# CONFIG_EXAMPLES_SMART_TEST is not set # CONFIG_EXAMPLES_SMART is not set +# CONFIG_EXAMPLES_SMART_TEST is not set # CONFIG_EXAMPLES_SMP is not set # CONFIG_EXAMPLES_TCPECHO is not set # CONFIG_EXAMPLES_TELNETD is not set # CONFIG_EXAMPLES_TIFF is not set # CONFIG_EXAMPLES_TOUCHSCREEN is not set -# CONFIG_EXAMPLES_WEBSERVER is not set -# CONFIG_EXAMPLES_USBSERIAL is not set # CONFIG_EXAMPLES_USBTERM is not set # CONFIG_EXAMPLES_WATCHDOG is not set +# CONFIG_EXAMPLES_WEBSERVER is not set # # File System Utilities @@ -766,8 +885,8 @@ CONFIG_EXAMPLES_NSH_CXXINITIALIZE=y # Interpreters # # CONFIG_INTERPRETERS_FICL is not set -# CONFIG_INTERPRETERS_PCODE is not set # CONFIG_INTERPRETERS_MICROPYTHON is not set +# CONFIG_INTERPRETERS_PCODE is not set # # FreeModBus @@ -778,6 +897,7 @@ CONFIG_EXAMPLES_NSH_CXXINITIALIZE=y # Network Utilities # # CONFIG_NETUTILS_CODECS is not set +# CONFIG_NETUTILS_ESP8266 is not set # CONFIG_NETUTILS_FTPC is not set # CONFIG_NETUTILS_JSON is not set # CONFIG_NETUTILS_SMTP is not set @@ -890,12 +1010,12 @@ CONFIG_NSH_CONSOLE=y # # System Libraries and NSH Add-Ons # -# CONFIG_SYSTEM_FREE is not set # CONFIG_SYSTEM_CLE is not set # CONFIG_SYSTEM_CUTERM is not set -# CONFIG_SYSTEM_INSTALL is not set +# CONFIG_SYSTEM_FREE is not set # CONFIG_SYSTEM_HEX2BIN is not set # CONFIG_SYSTEM_HEXED is not set +# CONFIG_SYSTEM_INSTALL is not set # CONFIG_SYSTEM_RAMTEST is not set CONFIG_READLINE_HAVE_EXTMATCH=y CONFIG_SYSTEM_READLINE=y @@ -903,6 +1023,6 @@ CONFIG_READLINE_ECHO=y # CONFIG_READLINE_TABCOMPLETION is not set # CONFIG_READLINE_CMD_HISTORY is not set # CONFIG_SYSTEM_SUDOKU is not set -# CONFIG_SYSTEM_VI is not set # CONFIG_SYSTEM_UBLOXMODEM is not set +# CONFIG_SYSTEM_VI is not set # CONFIG_SYSTEM_ZMODEM is not set From 0660e6378eb38fc3ee588da54c917a5277e630ce Mon Sep 17 00:00:00 2001 From: David Sidrane Date: Fri, 17 Jun 2016 12:26:23 -1000 Subject: [PATCH 71/75] Missing ADC2 --- arch/arm/src/stm32f7/Kconfig | 1 - 1 file changed, 1 deletion(-) diff --git a/arch/arm/src/stm32f7/Kconfig b/arch/arm/src/stm32f7/Kconfig index 5bcd7e55ab..0f2f65f84a 100644 --- a/arch/arm/src/stm32f7/Kconfig +++ b/arch/arm/src/stm32f7/Kconfig @@ -1018,7 +1018,6 @@ config STM32F7_ADC2 bool "ADC2" default n select STM32F7_ADC - depends on STM32F7_HAVE_ADC2 select STM32F7_HAVE_ADC2_DMA if STM32F7_DMA2 config STM32F7_ADC3 From a0980c610bce8d6bfc4af620fff5874a7f82d1f4 Mon Sep 17 00:00:00 2001 From: David Sidrane Date: Fri, 17 Jun 2016 13:07:41 -1000 Subject: [PATCH 72/75] Merge fix --- arch/arm/src/stm32f7/stm32_i2c.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm/src/stm32f7/stm32_i2c.c b/arch/arm/src/stm32f7/stm32_i2c.c index 53c144ca2b..4bc5213b34 100644 --- a/arch/arm/src/stm32f7/stm32_i2c.c +++ b/arch/arm/src/stm32f7/stm32_i2c.c @@ -1807,7 +1807,7 @@ static int stm32_i2c_isr(struct stm32_i2c_priv_s *priv) /* Unsupported state */ stm32_i2c_traceevent(priv, I2CEVENT_READ_ERROR, 0); - status = stm32_i2c_getreg(priv, STM32F7_I2C_ISR_OFFSET); + status = stm32_i2c_getreg(priv, STM32_I2C_ISR_OFFSET); i2cerr("ERROR: RXNE Unsupported state detected, dcnt=%i, status 0x%08x\n", priv->dcnt, status); @@ -2042,7 +2042,7 @@ static int stm32_i2c_isr(struct stm32_i2c_priv_s *priv) else if (priv->dcnt == -1 && priv->msgc == 0) { - status = stm32_i2c_getreg(priv, STM32F7_I2C_ISR_OFFSET); + status = stm32_i2c_getreg(priv, STM32_I2C_ISR_OFFSET); i2cwarn("WARNING: EMPTY CALL: Stopping ISR: status 0x%08x\n", status); stm32_i2c_traceevent(priv, I2CEVENT_ISR_EMPTY_CALL, 0); } From e65bcccaa28a69ad76dea38e0efe227c24c00788 Mon Sep 17 00:00:00 2001 From: Gregory Nutt Date: Fri, 17 Jun 2016 17:30:05 -0600 Subject: [PATCH 73/75] Costmetic changes from the review of the last PR --- .../arm/src/stm32f7/chip/stm32f74xx77xx_i2c.h | 202 +++++++++--------- .../arm/src/stm32f7/chip/stm32f74xx77xx_spi.h | 62 +++--- arch/arm/src/stm32f7/stm32_i2c.c | 19 +- configs/nucleo-144/include/board.h | 6 +- configs/nucleo-144/src/nucleo-144.h | 7 +- configs/stm32f746-ws/include/board.h | 5 +- configs/stm32f746g-disco/nsh/defconfig | 2 +- 7 files changed, 153 insertions(+), 150 deletions(-) diff --git a/arch/arm/src/stm32f7/chip/stm32f74xx77xx_i2c.h b/arch/arm/src/stm32f7/chip/stm32f74xx77xx_i2c.h index 7e76567001..7e2d801dc9 100644 --- a/arch/arm/src/stm32f7/chip/stm32f74xx77xx_i2c.h +++ b/arch/arm/src/stm32f7/chip/stm32f74xx77xx_i2c.h @@ -117,131 +117,131 @@ /* Control register 1 */ -#define I2C_CR1_PE (1 << 0) /* Bit 0: Peripheral Enable */ -#define I2C_CR1_TXIE (1 << 1) /* Bit 1: TX Interrupt enable */ -#define I2C_CR1_RXIE (1 << 2) /* Bit 2: RX Interrupt enable */ -#define I2C_CR1_ADDRIE (1 << 3) /* Bit 3: Address match interrupt enable (slave) */ -#define I2C_CR1_NACKIE (1 << 4) /* Bit 4: Not acknowledge received interrupt enable */ -#define I2C_CR1_STOPIE (1 << 5) /* Bit 5: STOP detection interrupt enable */ -#define I2C_CR1_TCIE (1 << 6) /* Bit 6: Transfer Complete interrupt enable */ -#define I2C_CR1_ERRIE (1 << 7) /* Bit 7: Error interrupts enable */ -#define I2C_CR1_DNF_SHIFT (8) /* Bits 8-11: Digital noise filter */ -#define I2C_CR1_DNF_MASK (0xf << I2C_CR1_DNF_SHIFT) -# define I2C_CR1_DNF_DISABLE (0 << I2C_CR1_DNF_SHIFT) -# define I2C_CR1_DNF(n) ((n) << I2C_CR1_DNF_SHIFT) /* Up to n * Ti2cclk, n=1..15 */ -#define I2C_CR1_ANFOFF (1 << 12) /* Bit 12: Analog noise filter OFF */ -#define I2C_CR1_TXDMAEN (1 << 14) /* Bit 14: DMA transmission requests enable */ -#define I2C_CR1_RXDMAEN (1 << 15) /* Bit 15: DMA reception requests enable */ -#define I2C_CR1_SBC (1 << 16) /* Bit 16: Slave byte control */ -#define I2C_CR1_NOSTRETCH (1 << 17) /* Bit 17: Clock stretching disable */ -#define I2C_CR1_GCEN (1 << 19) /* Bit 19: General call enable */ -#define I2C_CR1_SMBHEN (1 << 20) /* Bit 20: SMBus Host address enable */ -#define I2C_CR1_SMBDEN (1 << 21) /* Bit 21: SMBus Device Default address enable */ -#define I2C_CR1_ALERTEN (1 << 22) /* Bit 22: SMBus alert enable */ -#define I2C_CR1_PECEN (1 << 23) /* Bit 23: PEC enable */ +#define I2C_CR1_PE (1 << 0) /* Bit 0: Peripheral Enable */ +#define I2C_CR1_TXIE (1 << 1) /* Bit 1: TX Interrupt enable */ +#define I2C_CR1_RXIE (1 << 2) /* Bit 2: RX Interrupt enable */ +#define I2C_CR1_ADDRIE (1 << 3) /* Bit 3: Address match interrupt enable (slave) */ +#define I2C_CR1_NACKIE (1 << 4) /* Bit 4: Not acknowledge received interrupt enable */ +#define I2C_CR1_STOPIE (1 << 5) /* Bit 5: STOP detection interrupt enable */ +#define I2C_CR1_TCIE (1 << 6) /* Bit 6: Transfer Complete interrupt enable */ +#define I2C_CR1_ERRIE (1 << 7) /* Bit 7: Error interrupts enable */ +#define I2C_CR1_DNF_SHIFT (8) /* Bits 8-11: Digital noise filter */ +#define I2C_CR1_DNF_MASK (0xf << I2C_CR1_DNF_SHIFT) +# define I2C_CR1_DNF_DISABLE (0 << I2C_CR1_DNF_SHIFT) +# define I2C_CR1_DNF(n) ((n) << I2C_CR1_DNF_SHIFT) /* Up to n * Ti2cclk, n=1..15 */ +#define I2C_CR1_ANFOFF (1 << 12) /* Bit 12: Analog noise filter OFF */ +#define I2C_CR1_TXDMAEN (1 << 14) /* Bit 14: DMA transmission requests enable */ +#define I2C_CR1_RXDMAEN (1 << 15) /* Bit 15: DMA reception requests enable */ +#define I2C_CR1_SBC (1 << 16) /* Bit 16: Slave byte control */ +#define I2C_CR1_NOSTRETCH (1 << 17) /* Bit 17: Clock stretching disable */ +#define I2C_CR1_GCEN (1 << 19) /* Bit 19: General call enable */ +#define I2C_CR1_SMBHEN (1 << 20) /* Bit 20: SMBus Host address enable */ +#define I2C_CR1_SMBDEN (1 << 21) /* Bit 21: SMBus Device Default address enable */ +#define I2C_CR1_ALERTEN (1 << 22) /* Bit 22: SMBus alert enable */ +#define I2C_CR1_PECEN (1 << 23) /* Bit 23: PEC enable */ /* Control register 2 */ -#define I2C_CR2_SADD10_SHIFT (0) /* Bits 0-9: Slave 10-bit address (master) */ -#define I2C_CR2_SADD10_MASK (0x3ff << I2C_CR2_SADD10_SHIFT) -#define I2C_CR2_SADD7_SHIFT (1) /* Bits 1-7: Slave 7-bit address (master) */ -#define I2C_CR2_SADD7_MASK (0x7f << I2C_CR2_SADD7_SHIFT) -#define I2C_CR2_RD_WRN (1 << 10) /* Bit 10: Transfer direction (master) */ -#define I2C_CR2_ADD10 (1 << 11) /* Bit 11: 10-bit addressing mode (master) */ -#define I2C_CR2_HEAD10R (1 << 12) /* Bit 12: 10-bit address header only read direction (master) */ -#define I2C_CR2_START (1 << 13) /* Bit 13: Start generation */ -#define I2C_CR2_STOP (1 << 14) /* Bit 14: Stop generation (master) */ -#define I2C_CR2_NACK (1 << 15) /* Bit 15: NACK generation (slave) */ -#define I2C_CR2_NBYTES_SHIFT (16) /* Bits 16-23: Number of bytes */ -#define I2C_CR2_NBYTES_MASK (0xff << I2C_CR2_NBYTES_SHIFT) -#define I2C_CR2_RELOAD (1 << 24) /* Bit 24: NBYTES reload mode */ -#define I2C_CR2_AUTOEND (1 << 25) /* Bit 25: Automatic end mode (master) */ -#define I2C_CR2_PECBYTE (1 << 26) /* Bit 26: Packet error checking byte */ +#define I2C_CR2_SADD10_SHIFT (0) /* Bits 0-9: Slave 10-bit address (master) */ +#define I2C_CR2_SADD10_MASK (0x3ff << I2C_CR2_SADD10_SHIFT) +#define I2C_CR2_SADD7_SHIFT (1) /* Bits 1-7: Slave 7-bit address (master) */ +#define I2C_CR2_SADD7_MASK (0x7f << I2C_CR2_SADD7_SHIFT) +#define I2C_CR2_RD_WRN (1 << 10) /* Bit 10: Transfer direction (master) */ +#define I2C_CR2_ADD10 (1 << 11) /* Bit 11: 10-bit addressing mode (master) */ +#define I2C_CR2_HEAD10R (1 << 12) /* Bit 12: 10-bit address header only read direction (master) */ +#define I2C_CR2_START (1 << 13) /* Bit 13: Start generation */ +#define I2C_CR2_STOP (1 << 14) /* Bit 14: Stop generation (master) */ +#define I2C_CR2_NACK (1 << 15) /* Bit 15: NACK generation (slave) */ +#define I2C_CR2_NBYTES_SHIFT (16) /* Bits 16-23: Number of bytes */ +#define I2C_CR2_NBYTES_MASK (0xff << I2C_CR2_NBYTES_SHIFT) +#define I2C_CR2_RELOAD (1 << 24) /* Bit 24: NBYTES reload mode */ +#define I2C_CR2_AUTOEND (1 << 25) /* Bit 25: Automatic end mode (master) */ +#define I2C_CR2_PECBYTE (1 << 26) /* Bit 26: Packet error checking byte */ /* Own address register 1 */ -#define I2C_OAR1_OA1_10_SHIFT (0) /* Bits 0-9: 10-bit interface address */ -#define I2C_OAR1_OA1_10_MASK (0x3ff << I2C_OAR1_OA1_10_SHIFT) -#define I2C_OAR1_OA1_7_SHIFT (1) /* Bits 1-7: 7-bit interface address */ -#define I2C_OAR1_OA1_7_MASK (0x7f << I2C_OAR1_OA1_7_SHIFT) -#define I2C_OAR1_OA1MODE (1 << 10) /* Bit 10: Own Address 1 10-bit mode */ -#define I2C_OAR1_OA1EN (1 << 15) /* Bit 15: Own Address 1 enable */ +#define I2C_OAR1_OA1_10_SHIFT (0) /* Bits 0-9: 10-bit interface address */ +#define I2C_OAR1_OA1_10_MASK (0x3ff << I2C_OAR1_OA1_10_SHIFT) +#define I2C_OAR1_OA1_7_SHIFT (1) /* Bits 1-7: 7-bit interface address */ +#define I2C_OAR1_OA1_7_MASK (0x7f << I2C_OAR1_OA1_7_SHIFT) +#define I2C_OAR1_OA1MODE (1 << 10) /* Bit 10: Own Address 1 10-bit mode */ +#define I2C_OAR1_OA1EN (1 << 15) /* Bit 15: Own Address 1 enable */ /* Own address register 2 */ -#define I2C_OAR2_OA2_SHIFT (1) /* Bits 1-7: 7-bit interface address */ -#define I2C_OAR2_OA2_MASK (0x7f << I2C_OAR2_OA2_SHIFT) -#define I2C_OAR2_OA2MSK_SHIFT (8) /* Bits 8-10: Own Address 2 masks */ -#define I2C_OAR2_OA2MSK_MASK (7 << I2C_OAR2_OA2MSK_SHIFT) -# define I2C_OAR2_OA2MSK_NONE (0 << I2C_OAR2_OA2MSK_SHIFT) /* No mask */ -# define I2C_OAR2_OA2MSK_2_7 (1 << I2C_OAR2_OA2MSK_SHIFT) /* Only OA2[7:2] are compared */ -# define I2C_OAR2_OA2MSK_3_7 (2 << I2C_OAR2_OA2MSK_SHIFT) /* Only OA2[7:3] are compared */ -# define I2C_OAR2_OA2MSK_4_7 (3 << I2C_OAR2_OA2MSK_SHIFT) /* Only OA2[7:4] are compared */ -# define I2C_OAR2_OA2MSK_5_7 (4 << I2C_OAR2_OA2MSK_SHIFT) /* Only OA2[7:5] are compared */ -# define I2C_OAR2_OA2MSK_6_7 (5 << I2C_OAR2_OA2MSK_SHIFT) /* Only OA2[7:6] are compared */ -# define I2C_OAR2_OA2MSK_7 (6 << I2C_OAR2_OA2MSK_SHIFT) /* Only OA2[7] is compared */ -# define I2C_OAR2_OA2MSK_ALL (7 << I2C_OAR2_OA2MSK_SHIFT) /* All 7-bit addresses acknowledged */ -#define I2C_OAR2_OA2EN (1 << 15) /* Bit 15: Own Address 2 enable */ +#define I2C_OAR2_OA2_SHIFT (1) /* Bits 1-7: 7-bit interface address */ +#define I2C_OAR2_OA2_MASK (0x7f << I2C_OAR2_OA2_SHIFT) +#define I2C_OAR2_OA2MSK_SHIFT (8) /* Bits 8-10: Own Address 2 masks */ +#define I2C_OAR2_OA2MSK_MASK (7 << I2C_OAR2_OA2MSK_SHIFT) +# define I2C_OAR2_OA2MSK_NONE (0 << I2C_OAR2_OA2MSK_SHIFT) /* No mask */ +# define I2C_OAR2_OA2MSK_2_7 (1 << I2C_OAR2_OA2MSK_SHIFT) /* Only OA2[7:2] are compared */ +# define I2C_OAR2_OA2MSK_3_7 (2 << I2C_OAR2_OA2MSK_SHIFT) /* Only OA2[7:3] are compared */ +# define I2C_OAR2_OA2MSK_4_7 (3 << I2C_OAR2_OA2MSK_SHIFT) /* Only OA2[7:4] are compared */ +# define I2C_OAR2_OA2MSK_5_7 (4 << I2C_OAR2_OA2MSK_SHIFT) /* Only OA2[7:5] are compared */ +# define I2C_OAR2_OA2MSK_6_7 (5 << I2C_OAR2_OA2MSK_SHIFT) /* Only OA2[7:6] are compared */ +# define I2C_OAR2_OA2MSK_7 (6 << I2C_OAR2_OA2MSK_SHIFT) /* Only OA2[7] is compared */ +# define I2C_OAR2_OA2MSK_ALL (7 << I2C_OAR2_OA2MSK_SHIFT) /* All 7-bit addresses acknowledged */ +#define I2C_OAR2_OA2EN (1 << 15) /* Bit 15: Own Address 2 enable */ /* Timing register */ -#define I2C_TIMINGR_SCLL_SHIFT (0) /* Bits 0-7: SCL low period (master) */ -#define I2C_TIMINGR_SCLL_MASK (0xff << I2C_TIMINGR_SCLL_SHIFT) -# define I2C_TIMINGR_SCLL(n) (((n)-1) << I2C_TIMINGR_SCLL_SHIFT) /* tSCLL = n x tPRESC */ +#define I2C_TIMINGR_SCLL_SHIFT (0) /* Bits 0-7: SCL low period (master) */ +#define I2C_TIMINGR_SCLL_MASK (0xff << I2C_TIMINGR_SCLL_SHIFT) +# define I2C_TIMINGR_SCLL(n) (((n)-1) << I2C_TIMINGR_SCLL_SHIFT) /* tSCLL = n x tPRESC */ -#define I2C_TIMINGR_SCLH_SHIFT (8) /* Bits 8-15: SCL high period (master) */ -#define I2C_TIMINGR_SCLH_MASK (0xff << I2C_TIMINGR_SCLH_SHIFT) -# define I2C_TIMINGR_SCLH(n) (((n)-1) << I2C_TIMINGR_SCLH_SHIFT) /* tSCLH = n x tPRESC */ +#define I2C_TIMINGR_SCLH_SHIFT (8) /* Bits 8-15: SCL high period (master) */ +#define I2C_TIMINGR_SCLH_MASK (0xff << I2C_TIMINGR_SCLH_SHIFT) +# define I2C_TIMINGR_SCLH(n) (((n)-1) << I2C_TIMINGR_SCLH_SHIFT) /* tSCLH = n x tPRESC */ -#define I2C_TIMINGR_SDADEL_SHIFT (16) /* Bits 16-19: Data hold time */ -#define I2C_TIMINGR_SDADEL_MASK (0xf << I2C_TIMINGR_SDADEL_SHIFT) -# define I2C_TIMINGR_SDADEL(n) ((n) << I2C_TIMINGR_SDADEL_SHIFT) /* tSDADEL= n x tPRESC */ +#define I2C_TIMINGR_SDADEL_SHIFT (16) /* Bits 16-19: Data hold time */ +#define I2C_TIMINGR_SDADEL_MASK (0xf << I2C_TIMINGR_SDADEL_SHIFT) +# define I2C_TIMINGR_SDADEL(n) ((n) << I2C_TIMINGR_SDADEL_SHIFT) /* tSDADEL= n x tPRESC */ -#define I2C_TIMINGR_SCLDEL_SHIFT (20) /* Bits 20-23: Data setup time */ -#define I2C_TIMINGR_SCLDEL_MASK (0xf << I2C_TIMINGR_SCLDEL_SHIFT) -# define I2C_TIMINGR_SCLDEL(n) (((n)-1) << I2C_TIMINGR_SCLDEL_SHIFT) /* tSCLDEL = n x tPRESC */ +#define I2C_TIMINGR_SCLDEL_SHIFT (20) /* Bits 20-23: Data setup time */ +#define I2C_TIMINGR_SCLDEL_MASK (0xf << I2C_TIMINGR_SCLDEL_SHIFT) +# define I2C_TIMINGR_SCLDEL(n) (((n)-1) << I2C_TIMINGR_SCLDEL_SHIFT) /* tSCLDEL = n x tPRESC */ -#define I2C_TIMINGR_PRESC_SHIFT (28) /* Bits 28-31: Timing prescaler */ -#define I2C_TIMINGR_PRESC_MASK (0xf << I2C_TIMINGR_PRESC_SHIFT) -# define I2C_TIMINGR_PRESC(n) (((n)-1) << I2C_TIMINGR_PRESC_SHIFT) /* tPRESC = n x tI2CCLK */ +#define I2C_TIMINGR_PRESC_SHIFT (28) /* Bits 28-31: Timing prescaler */ +#define I2C_TIMINGR_PRESC_MASK (0xf << I2C_TIMINGR_PRESC_SHIFT) +# define I2C_TIMINGR_PRESC(n) (((n)-1) << I2C_TIMINGR_PRESC_SHIFT) /* tPRESC = n x tI2CCLK */ /* Timeout register */ -#define I2C_TIMEOUTR_A_SHIFT (0) /* Bits 0-11: Bus Timeout A */ -#define I2C_TIMEOUTR_A_MASK (0x0fff << I2C_TIMEOUTR_A_SHIFT) -# define I2C_TIMEOUTR_A(n) ((n) << I2C_TIMEOUTR_A_SHIFT) -#define I2C_TIMEOUTR_TIDLE (1 << 12) /* Bit 12: Idle clock timeout detection */ -#define I2C_TIMEOUTR_TIMOUTEN (1 << 15) /* Bit 15: Clock timeout enable */ -#define I2C_TIMEOUTR_B_SHIFT (16) /* Bits 16-27: Bus Timeout B */ -#define I2C_TIMEOUTR_B_MASK (0x0fff << I2C_TIMEOUTR_B_SHIFT) -# define I2C_TIMEOUTR_B(n) ((n) << I2C_TIMEOUTR_B_SHIFT) -#define I2C_TIMEOUTR_TEXTEN (1 << 31) /* Bits 31: Extended clock timeout enable */ +#define I2C_TIMEOUTR_A_SHIFT (0) /* Bits 0-11: Bus Timeout A */ +#define I2C_TIMEOUTR_A_MASK (0x0fff << I2C_TIMEOUTR_A_SHIFT) +# define I2C_TIMEOUTR_A(n) ((n) << I2C_TIMEOUTR_A_SHIFT) +#define I2C_TIMEOUTR_TIDLE (1 << 12) /* Bit 12: Idle clock timeout detection */ +#define I2C_TIMEOUTR_TIMOUTEN (1 << 15) /* Bit 15: Clock timeout enable */ +#define I2C_TIMEOUTR_B_SHIFT (16) /* Bits 16-27: Bus Timeout B */ +#define I2C_TIMEOUTR_B_MASK (0x0fff << I2C_TIMEOUTR_B_SHIFT) +# define I2C_TIMEOUTR_B(n) ((n) << I2C_TIMEOUTR_B_SHIFT) +#define I2C_TIMEOUTR_TEXTEN (1 << 31) /* Bits 31: Extended clock timeout enable */ /* Fields unique to the Interrupt and Status register */ -#define I2C_ISR_TXE (1 << 0) /* Bit 0: Transmit data register empty (transmitters) */ -#define I2C_ISR_TXIS (1 << 1) /* Bit 1: Transmit interrupt status (transmitters) */ -#define I2C_ISR_RXNE (1 << 2) /* Bit 2: Receive data register not empty (receivers) */ -#define I2C_ISR_TC (1 << 6) /* Bit 6: Transfer Complete (master) */ -#define I2C_ISR_TCR (1 << 7) /* Bit 7: Transfer Complete Reload */ -#define I2C_ISR_BUSY (1 << 15) /* Bit 15: Bus busy */ -#define I2C_ISR_DIR (1 << 16) /* Bit 16: Transfer direction (slave) */ -#define I2C_ISR_ADDCODE_SHIFT (17) /* Bits 17-23: Address match code (slave) */ -#define I2C_ISR_ADDCODE_MASK (0x7f << I2C_ISR_ADDCODE_SHIFT) +#define I2C_ISR_TXE (1 << 0) /* Bit 0: Transmit data register empty (transmitters) */ +#define I2C_ISR_TXIS (1 << 1) /* Bit 1: Transmit interrupt status (transmitters) */ +#define I2C_ISR_RXNE (1 << 2) /* Bit 2: Receive data register not empty (receivers) */ +#define I2C_ISR_TC (1 << 6) /* Bit 6: Transfer Complete (master) */ +#define I2C_ISR_TCR (1 << 7) /* Bit 7: Transfer Complete Reload */ +#define I2C_ISR_BUSY (1 << 15) /* Bit 15: Bus busy */ +#define I2C_ISR_DIR (1 << 16) /* Bit 16: Transfer direction (slave) */ +#define I2C_ISR_ADDCODE_SHIFT (17) /* Bits 17-23: Address match code (slave) */ +#define I2C_ISR_ADDCODE_MASK (0x7f << I2C_ISR_ADDCODE_SHIFT) /* Interrupt and Status register and interrupt clear register */ /* Common interrupt bits */ -#define I2C_INT_ADDR (1 << 3) /* Bit 3: Address matched (slave) */ -#define I2C_INT_NACK (1 << 4) /* Bit 4: Not Acknowledge received flag */ -#define I2C_INT_STOP (1 << 5) /* Bit 5: Stop detection flag */ -#define I2C_INT_BERR (1 << 8) /* Bit 8: Bus error */ -#define I2C_INT_ARLO (1 << 9) /* Bit 9: Arbitration lost */ -#define I2C_INT_OVR (1 << 10) /* Bit 10: Overrun/Underrun (slave) */ -#define I2C_INT_PECERR (1 << 11) /* Bit 11: PEC Error in reception */ -#define I2C_INT_TIMEOUT (1 << 12) /* Bit 12: Timeout or tLOW detection flag */ -#define I2C_INT_ALERT (1 << 13) /* Bit 13: SMBus alert */ +#define I2C_INT_ADDR (1 << 3) /* Bit 3: Address matched (slave) */ +#define I2C_INT_NACK (1 << 4) /* Bit 4: Not Acknowledge received flag */ +#define I2C_INT_STOP (1 << 5) /* Bit 5: Stop detection flag */ +#define I2C_INT_BERR (1 << 8) /* Bit 8: Bus error */ +#define I2C_INT_ARLO (1 << 9) /* Bit 9: Arbitration lost */ +#define I2C_INT_OVR (1 << 10) /* Bit 10: Overrun/Underrun (slave) */ +#define I2C_INT_PECERR (1 << 11) /* Bit 11: PEC Error in reception */ +#define I2C_INT_TIMEOUT (1 << 12) /* Bit 12: Timeout or tLOW detection flag */ +#define I2C_INT_ALERT (1 << 13) /* Bit 13: SMBus alert */ #define I2C_ISR_ERRORMASK (I2C_INT_BERR | I2C_INT_ARLO | I2C_INT_OVR | I2C_INT_PECERR | I2C_INT_TIMEOUT) @@ -250,15 +250,15 @@ /* Packet error checking register */ -#define I2C_PECR_MASK (0xff) +#define I2C_PECR_MASK (0xff) /* Receive data register */ -#define I2C_RXDR_MASK (0xff) +#define I2C_RXDR_MASK (0xff) /* Transmit data register */ -#define I2C_TXDR_MASK (0xff) +#define I2C_TXDR_MASK (0xff) #endif /* __ARCH_ARM_SRC_STM32F7_CHIP_STM32F74XX77XX_I2C_H */ diff --git a/arch/arm/src/stm32f7/chip/stm32f74xx77xx_spi.h b/arch/arm/src/stm32f7/chip/stm32f74xx77xx_spi.h index 61725763cd..fe8c899c56 100644 --- a/arch/arm/src/stm32f7/chip/stm32f74xx77xx_spi.h +++ b/arch/arm/src/stm32f7/chip/stm32f74xx77xx_spi.h @@ -51,22 +51,22 @@ /* Maximum allowed speed as per data sheet for all SPIs (both pclk1 and pclk2)*/ #if defined(CONFIG_STM32F7_STM32F74XX) || defined(CONFIG_STM32F7_STM32F75XX) -# define STM32_SPI_CLK_MAX 50000000UL +# define STM32_SPI_CLK_MAX 50000000UL #elif defined(CONFIG_STM32F7_STM32F76XX) || defined(CONFIG_STM32F7_STM32F77XX) -# define STM32_SPI_CLK_MAX 54000000UL +# define STM32_SPI_CLK_MAX 54000000UL #endif /* Register Offsets *****************************************************************/ -#define STM32_SPI_CR1_OFFSET 0x0000 /* SPI Control Register 1 (16-bit) */ -#define STM32_SPI_CR2_OFFSET 0x0004 /* SPI control register 2 (16-bit) */ -#define STM32_SPI_SR_OFFSET 0x0008 /* SPI status register (16-bit) */ -#define STM32_SPI_DR_OFFSET 0x000c /* SPI data register (16-bit) */ -#define STM32_SPI_CRCPR_OFFSET 0x0010 /* SPI CRC polynomial register (16-bit) */ -#define STM32_SPI_RXCRCR_OFFSET 0x0014 /* SPI Rx CRC register (16-bit) */ -#define STM32_SPI_TXCRCR_OFFSET 0x0018 /* SPI Tx CRC register (16-bit) */ -#define STM32_SPI_I2SCFGR_OFFSET 0x001c /* I2S configuration register */ -#define STM32_SPI_I2SPR_OFFSET 0x0020 /* I2S prescaler register */ +#define STM32_SPI_CR1_OFFSET 0x0000 /* SPI Control Register 1 (16-bit) */ +#define STM32_SPI_CR2_OFFSET 0x0004 /* SPI control register 2 (16-bit) */ +#define STM32_SPI_SR_OFFSET 0x0008 /* SPI status register (16-bit) */ +#define STM32_SPI_DR_OFFSET 0x000c /* SPI data register (16-bit) */ +#define STM32_SPI_CRCPR_OFFSET 0x0010 /* SPI CRC polynomial register (16-bit) */ +#define STM32_SPI_RXCRCR_OFFSET 0x0014 /* SPI Rx CRC register (16-bit) */ +#define STM32_SPI_TXCRCR_OFFSET 0x0018 /* SPI Tx CRC register (16-bit) */ +#define STM32_SPI_I2SCFGR_OFFSET 0x001c /* I2S configuration register */ +#define STM32_SPI_I2SPR_OFFSET 0x0020 /* I2S prescaler register */ /* Register Addresses ***************************************************************/ @@ -209,18 +209,18 @@ #define SPI_SR_OVR (1 << 6) /* Bit 6: Overrun flag */ #define SPI_SR_BSY (1 << 7) /* Bit 7: Busy flag */ #define SPI_SR_FRE (1 << 8) /* Bit 8: Frame format error */ -#define SPI_SR_FRLVL_SHIFT (9) /* Bits 9-10: FIFO reception level */ -#define SPI_SR_FRLVL_MASK (0x3 << SPI_SR_FRLVL_SHIFT) -# define SPI_SR_FRLVL_EMPTY (0 << SPI_SR_FRLVL_SHIFT) /* FIFO empty */ -# define SPI_SR_FRLVL_QUARTER (1 << SPI_SR_FRLVL_SHIFT) /* 1/4 FIFO */ -# define SPI_SR_FRLVL_HALF (2 << SPI_SR_FRLVL_SHIFT) /* 1/2 FIFO */ -# define SPI_SR_FRLVL_FULL (3 << SPI_SR_FRLVL_SHIFT) /* FIFO full */ -#define SPI_SR_FTLVL_SHIFT (11) /* Bits 11-12: FIFO transmission level */ -#define SPI_SR_FTLVL_MASK (0x3 << SPI_SR_FTLVL_SHIFT) -# define SPI_SR_FTLVL_EMPTY (0 << SPI_SR_FTLVL_SHIFT) /* FIFO empty */ -# define SPI_SR_FTLVL_QUARTER (1 << SPI_SR_FTLVL_SHIFT) /* 1/4 FIFO */ -# define SPI_SR_FTLVL_HALF (2 << SPI_SR_FTLVL_SHIFT) /* 1/2 FIFO */ -# define SPI_SR_FTLVL_FULL (3 << SPI_SR_FTLVL_SHIFT) /* FIFO full */ +#define SPI_SR_FRLVL_SHIFT (9) /* Bits 9-10: FIFO reception level */ +#define SPI_SR_FRLVL_MASK (3 << SPI_SR_FRLVL_SHIFT) +# define SPI_SR_FRLVL_EMPTY (0 << SPI_SR_FRLVL_SHIFT) /* FIFO empty */ +# define SPI_SR_FRLVL_QUARTER (1 << SPI_SR_FRLVL_SHIFT) /* 1/4 FIFO */ +# define SPI_SR_FRLVL_HALF (2 << SPI_SR_FRLVL_SHIFT) /* 1/2 FIFO */ +# define SPI_SR_FRLVL_FULL (3 << SPI_SR_FRLVL_SHIFT) /* FIFO full */ +#define SPI_SR_FTLVL_SHIFT (11) /* Bits 11-12: FIFO transmission level */ +#define SPI_SR_FTLVL_MASK (3 << SPI_SR_FTLVL_SHIFT) +# define SPI_SR_FTLVL_EMPTY (0 << SPI_SR_FTLVL_SHIFT) /* FIFO empty */ +# define SPI_SR_FTLVL_QUARTER (1 << SPI_SR_FTLVL_SHIFT) /* 1/4 FIFO */ +# define SPI_SR_FTLVL_HALF (2 << SPI_SR_FTLVL_SHIFT) /* 1/2 FIFO */ +# define SPI_SR_FTLVL_FULL (3 << SPI_SR_FTLVL_SHIFT) /* FIFO full */ /* I2S configuration register */ @@ -233,10 +233,10 @@ #define SPI_I2SCFGR_CKPOL (1 << 3) /* Bit 3: Steady state clock polarity */ #define SPI_I2SCFGR_I2SSTD_SHIFT (4) /* Bit 4-5: I2S standard selection */ #define SPI_I2SCFGR_I2SSTD_MASK (3 << SPI_I2SCFGR_I2SSTD_SHIFT) -# define SPI_I2SCFGR_I2SSTD_PHILLIPS (00 << SPI_I2SCFGR_I2SSTD_SHIFT) /* 00: I2S Phillips standard. */ -# define SPI_I2SCFGR_I2SSTD_MSB (1 << SPI_I2SCFGR_I2SSTD_SHIFT) /* 01: MSB justified standard (left justified) */ -# define SPI_I2SCFGR_I2SSTD_LSB (2 << SPI_I2SCFGR_I2SSTD_SHIFT) /* 10: LSB justified standard (right justified) */ -# define SPI_I2SCFGR_I2SSTD_PCM (3 << SPI_I2SCFGR_I2SSTD_SHIFT) /* 11: PCM standard */ +# define SPI_I2SCFGR_I2SSTD_PHILLIPS (0 << SPI_I2SCFGR_I2SSTD_SHIFT) /* 00: I2S Phillips standard. */ +# define SPI_I2SCFGR_I2SSTD_MSB (1 << SPI_I2SCFGR_I2SSTD_SHIFT) /* 01: MSB justified standard (left justified) */ +# define SPI_I2SCFGR_I2SSTD_LSB (2 << SPI_I2SCFGR_I2SSTD_SHIFT) /* 10: LSB justified standard (right justified) */ +# define SPI_I2SCFGR_I2SSTD_PCM (3 << SPI_I2SCFGR_I2SSTD_SHIFT) /* 11: PCM standard */ #define SPI_I2SCFGR_PCMSYNC (1 << 7) /* Bit 7: PCM frame synchronization */ #define SPI_I2SCFGR_I2SCFG_SHIFT (8) /* Bit 8-9: I2S configuration mode */ #define SPI_I2SCFGR_I2SCFG_MASK (3 << SPI_I2SCFGR_I2SCFG_SHIFT) @@ -250,9 +250,9 @@ /* I2S prescaler register */ -#define SPI_I2SPR_I2SDIV_SHIFT (0) /* Bit 0-7: I2S Linear prescaler */ -#define SPI_I2SPR_I2SDIV_MASK (0xff << SPI_I2SPR_I2SDIV_SHIFT) -#define SPI_I2SPR_ODD (1 << 8) /* Bit 8: Odd factor for the prescaler */ -#define SPI_I2SPR_MCKOE (1 << 9) /* Bit 9: Master clock output enable */ +#define SPI_I2SPR_I2SDIV_SHIFT (0) /* Bit 0-7: I2S Linear prescaler */ +#define SPI_I2SPR_I2SDIV_MASK (0xff << SPI_I2SPR_I2SDIV_SHIFT) +#define SPI_I2SPR_ODD (1 << 8) /* Bit 8: Odd factor for the prescaler */ +#define SPI_I2SPR_MCKOE (1 << 9) /* Bit 9: Master clock output enable */ #endif /* __ARCH_ARM_SRC_STM32F7_CHIP_STM32F74XX77XX_SPI_H */ diff --git a/arch/arm/src/stm32f7/stm32_i2c.c b/arch/arm/src/stm32f7/stm32_i2c.c index 4bc5213b34..3786e7d52c 100644 --- a/arch/arm/src/stm32f7/stm32_i2c.c +++ b/arch/arm/src/stm32f7/stm32_i2c.c @@ -1445,11 +1445,14 @@ static inline void stm32_i2c_sendstart(FAR struct stm32_i2c_priv_s *priv) * exceed the hardware maximum allowed. */ - if (priv->dcnt > 255) { + if (priv->dcnt > 255) + { stm32_i2c_set_bytes_to_transfer(priv, 255); - } else { + } + else + { stm32_i2c_set_bytes_to_transfer(priv, priv->dcnt); - } + } /* Set the (7 bit) address. * 10 bit addressing is not yet supported. @@ -1475,7 +1478,7 @@ static inline void stm32_i2c_sendstart(FAR struct stm32_i2c_priv_s *priv) */ i2cinfo("Sending START: dcnt=%i msgc=%i flags=0x%04x\n", - priv->dcnt, priv->msgc, priv->flags); + priv->dcnt, priv->msgc, priv->flags); stm32_i2c_modifyreg32(priv, STM32_I2C_CR2_OFFSET, 0, I2C_CR2_START); } @@ -2019,7 +2022,7 @@ static int stm32_i2c_isr(struct stm32_i2c_priv_s *priv) * we receive a TC event next time which will allow us to * either RESTART and continue sending the contents of the * next message or send a STOP condition and exit the ISR. - */ + */ i2cinfo("TCR: DISABLE RELOAD: NBYTES = dcnt = %i msgc = %i\n", priv->dcnt, priv->msgc); @@ -2057,7 +2060,7 @@ static int stm32_i2c_isr(struct stm32_i2c_priv_s *priv) * in one of the supported states when polled. */ - else + else { #ifdef CONFIG_I2C_POLLED stm32_i2c_traceevent(priv, I2CEVENT_POLL_DEV_NOT_RDY, 0); @@ -2107,7 +2110,8 @@ static int stm32_i2c_isr(struct stm32_i2c_priv_s *priv) * vs data) to the upper layers once we exit the ISR. * * Note: We do this prior to clearing interrupts because the NACKF - * flag will naturally be cleared by that process. */ + * flag will naturally be cleared by that process. + */ priv->status = status; @@ -2367,6 +2371,7 @@ static int stm32_i2c_process(FAR struct i2c_master_s *dev, FAR struct i2c_msg_s UNUSED(cr1); UNUSED(cr2); #endif + /* Status after a normal / good exit is usually 0x00000001, meaning the TXE * bit is set. That occurs as a result of the I2C_TXDR register being * empty, and it naturally will be after the last byte is transmitted. diff --git a/configs/nucleo-144/include/board.h b/configs/nucleo-144/include/board.h index fe10e5ebdd..1561ad8cc6 100644 --- a/configs/nucleo-144/include/board.h +++ b/configs/nucleo-144/include/board.h @@ -360,9 +360,9 @@ #define GPIO_SPI2_MOSI GPIO_SPI2_MOSI_1 #define GPIO_SPI2_SCK GPIO_SPI2_SCK_3 -#define GPIO_SPI3_MISO GPIO_SPI3_MISO_1 -#define GPIO_SPI3_MOSI GPIO_SPI3_MOSI_2 -#define GPIO_SPI3_SCK GPIO_SPI3_SCK_1 +#define GPIO_SPI3_MISO GPIO_SPI3_MISO_1 +#define GPIO_SPI3_MOSI GPIO_SPI3_MOSI_2 +#define GPIO_SPI3_SCK GPIO_SPI3_SCK_1 /* I2C * diff --git a/configs/nucleo-144/src/nucleo-144.h b/configs/nucleo-144/src/nucleo-144.h index 9747de3015..48a6f9f11a 100644 --- a/configs/nucleo-144/src/nucleo-144.h +++ b/configs/nucleo-144/src/nucleo-144.h @@ -95,9 +95,8 @@ #define GPIO_BTN_USER (GPIO_INPUT | GPIO_FLOAT | GPIO_EXTI | GPIO_PORTC | GPIO_PIN13) -/* SPI *************************************************************************** - * - */ +/* SPI ***************************************************************************/ + #define GPIO_SPI_CS (GPIO_OUTPUT | GPIO_PUSHPULL | GPIO_SPEED_50MHz | \ GPIO_OUTPUT_SET) @@ -197,7 +196,5 @@ int stm32_dma_alloc_init(void); int board_adc_initialize(void); #endif - - #endif /* __ASSEMBLY__ */ #endif /* __CONFIGS_NUCLEO_144_SRC_NUCLEO_144_H */ diff --git a/configs/stm32f746-ws/include/board.h b/configs/stm32f746-ws/include/board.h index 6beed6753b..2a64e967fe 100644 --- a/configs/stm32f746-ws/include/board.h +++ b/configs/stm32f746-ws/include/board.h @@ -251,12 +251,13 @@ #define GPIO_SPI1_MISO GPIO_SPI1_MISO_1 #define GPIO_SPI1_MOSI GPIO_SPI1_MOSI_1 -#define GPIO_I2C1_SCL GPIO_I2C1_SCL_1 -#define GPIO_I2C1_SDA GPIO_I2C1_SDA_1 +#define GPIO_I2C1_SCL GPIO_I2C1_SCL_1 +#define GPIO_I2C1_SDA GPIO_I2C1_SDA_1 /************************************************************************************ * Public Data ************************************************************************************/ + #ifndef __ASSEMBLY__ #undef EXTERN diff --git a/configs/stm32f746g-disco/nsh/defconfig b/configs/stm32f746g-disco/nsh/defconfig index 421cf40372..6d7e819e4e 100644 --- a/configs/stm32f746g-disco/nsh/defconfig +++ b/configs/stm32f746g-disco/nsh/defconfig @@ -20,7 +20,7 @@ CONFIG_WINDOWS_CYGWIN=y # # Build Configuration # -CONFIG_APPS_DIR="../apps" +# CONFIG_APPS_DIR="../apps" CONFIG_BUILD_FLAT=y # CONFIG_BUILD_2PASS is not set From 0fe5c726b5f00d570d1fa1fe56e500583d0d1428 Mon Sep 17 00:00:00 2001 From: Gregory Nutt Date: Fri, 17 Jun 2016 17:53:02 -0600 Subject: [PATCH 74/75] Update ChangeLog --- ChangeLog | 29 +++++++++++++++++++++++++++++ 1 file changed, 29 insertions(+) diff --git a/ChangeLog b/ChangeLog index d4085fd5db..557174fe7a 100755 --- a/ChangeLog +++ b/ChangeLog @@ -12045,3 +12045,32 @@ - escape LASTXFER: this suppresses the LASTXFER bit at the end of the next transfer. The "escape"-Flag is reset automatically. From Frank Benkert (2016-06-14) + * Many CONFIG_DEBUG_* options did not have matching macros defined in + include/debug.h. Rather, there were various definitions scattered + throughout the sourse tree. These were collected together and + centralized with single macro definitions in include/debug.h + (2016-06-15) + * STM32F7: Add SPI, I2C, and ADC drivers. From Lok Tep (2016-06-15). + * err(), warn(), info(), and alert() renamed to include leading '_'. + This was done to avoid some naming collisions (2-06-16 + * STM32: Move backup domain reset to to earlier in the initialization + sequence (stm32_rcc.c() in order to avoid disabling LSE during RTC + initialiation. From Alan Carvalho de Assis (2016-06-16). + * SYSLOG: syslog() will now automatically redirect output to lowsyslog() + if called from an interrupt handler (2016-06-16). + * STM32: When configuring a GPIO via stm32_configgpio() the function + will first set the mode to output and then set the initial state of + the gpio later on. If you have an application with an externaly + pulled-up pin, this would lead to a glitch on the line that may be + dangerous in some applications (e.G. Reset Line for other chips, + etc). This changes sets the output state before configuring the pin + as an output. From Pascal Speck (2016-06-17). + * STM32 F7: Apply Pascal Speck's GPIO STM32 change to STM32 L4 + (2016-06-17). + * STM32 L4: Apply Pascal Speck's GPIO STM32 change to STM32 L4. + From Sebastien Lorquet (2016-06-17). + * Review all uses of *err(). These macro family should indicate only + error conditions. Convert *err() to either *info() or add ERROR:, + depending on if an error is reported (2016-06-17). + * STM32F7: Review, correct, and update I2C, SPI, and ADC drivers. From + David Sidrane (2016-06-17). From 3fa41c0f183dfec4ab7a054553dca48409162f0d Mon Sep 17 00:00:00 2001 From: Gregory Nutt Date: Fri, 17 Jun 2016 19:30:19 -0600 Subject: [PATCH 75/75] Kconfig files: Fix some dependencies that have CONFIG_ in the variable name --- arch/arm/src/sam34/Kconfig | 4 ++-- arch/arm/src/sama5/Kconfig | 4 ++-- arch/arm/src/samv7/Kconfig | 4 ++-- binfmt/libelf/Kconfig | 2 +- binfmt/libnxflat/Kconfig | 2 +- binfmt/libpcode/Kconfig | 2 +- drivers/input/Kconfig | 2 +- sched/Kconfig | 2 +- 8 files changed, 11 insertions(+), 11 deletions(-) diff --git a/arch/arm/src/sam34/Kconfig b/arch/arm/src/sam34/Kconfig index bc191c88df..8e764dff40 100644 --- a/arch/arm/src/sam34/Kconfig +++ b/arch/arm/src/sam34/Kconfig @@ -1369,7 +1369,7 @@ config SAM34_HSMCI_WRPROOF config SAM34_HSMCI_XFRDEBUG bool "HSMCI transfer debug" - depends on DEBUG_FS && CONFIG_DEBUG_INFO + depends on DEBUG_FS_INFO default n ---help--- Enable special debug instrumentation analyze HSMCI data transfers. @@ -1381,7 +1381,7 @@ config SAM34_HSMCI_XFRDEBUG config SAM34_HSMCI_CMDDEBUG bool "HSMCI command debug" - depends on DEBUG_FS && CONFIG_DEBUG_INFO + depends on DEBUG_FS_INFO default n ---help--- Enable special debug instrumentation analyze HSMCI commands. This diff --git a/arch/arm/src/sama5/Kconfig b/arch/arm/src/sama5/Kconfig index 4f7b2371db..11aa7179f1 100644 --- a/arch/arm/src/sama5/Kconfig +++ b/arch/arm/src/sama5/Kconfig @@ -2857,7 +2857,7 @@ config SAMA5_HSMCI_WRPROOF config SAMA5_HSMCI_XFRDEBUG bool "HSMCI transfer debug" - depends on DEBUG_FS && CONFIG_DEBUG_INFO + depends on DEBUG_FS_INFO default n ---help--- Enable special debug instrumentation analyze HSMCI data transfers. @@ -2869,7 +2869,7 @@ config SAMA5_HSMCI_XFRDEBUG config SAMA5_HSMCI_CMDDEBUG bool "HSMCI command debug" - depends on DEBUG_FS && CONFIG_DEBUG_INFO + depends on DEBUG_FS_INFO default n ---help--- Enable special debug instrumentation analyze HSMCI commands. This diff --git a/arch/arm/src/samv7/Kconfig b/arch/arm/src/samv7/Kconfig index 1f217e5d4a..55eb92d485 100644 --- a/arch/arm/src/samv7/Kconfig +++ b/arch/arm/src/samv7/Kconfig @@ -1634,7 +1634,7 @@ config SAMV7_HSMCI_UNALIGNED config SAMV7_HSMCI_XFRDEBUG bool "HSMCI transfer debug" - depends on DEBUG_FS && CONFIG_DEBUG_INFO + depends on DEBUG_FS_INFO default n ---help--- Enable special debug instrumentation analyze HSMCI data transfers. @@ -1646,7 +1646,7 @@ config SAMV7_HSMCI_XFRDEBUG config SAMV7_HSMCI_CMDDEBUG bool "HSMCI command debug" - depends on DEBUG_FS && CONFIG_DEBUG_INFO + depends on DEBUG_FS_INFO default n ---help--- Enable special debug instrumentation analyze HSMCI commands. This diff --git a/binfmt/libelf/Kconfig b/binfmt/libelf/Kconfig index 684eaba8be..5580a70a47 100644 --- a/binfmt/libelf/Kconfig +++ b/binfmt/libelf/Kconfig @@ -35,7 +35,7 @@ config ELF_BUFFERINCR config ELF_DUMPBUFFER bool "Dump ELF buffers" default n - depends on DEBUG_FEATURES && CONFIG_DEBUG_INFO + depends on DEBUG_INFO ---help--- Dump various ELF buffers for debug purposes diff --git a/binfmt/libnxflat/Kconfig b/binfmt/libnxflat/Kconfig index 6929b04296..66c0031528 100644 --- a/binfmt/libnxflat/Kconfig +++ b/binfmt/libnxflat/Kconfig @@ -6,4 +6,4 @@ config NXFLAT_DUMPBUFFER bool "Dump NXFLAT buffers" default n - depends on DEBUG_FEATURES && CONFIG_DEBUG_INFO + depends on DEBUG_INFO diff --git a/binfmt/libpcode/Kconfig b/binfmt/libpcode/Kconfig index c767aca790..046dc71c55 100644 --- a/binfmt/libpcode/Kconfig +++ b/binfmt/libpcode/Kconfig @@ -64,6 +64,6 @@ endif # PCODE_TEST_FS config PCODE_DUMPBUFFER bool "Dump P-code buffers" default n - depends on DEBUG_FEATURES && CONFIG_DEBUG_INFO + depends on DEBUG_INFO ---help--- Dump various P-code buffers for debug purposes diff --git a/drivers/input/Kconfig b/drivers/input/Kconfig index e28d053af7..0fc96d6c91 100644 --- a/drivers/input/Kconfig +++ b/drivers/input/Kconfig @@ -179,7 +179,7 @@ config MXT_NPOLLWAITERS config MXT_DISABLE_CONFIG_DEBUG_INFO bool "Disable verbose debug output" default y - depends on CONFIG_DEBUG_INFO && DEBUG_INPUT + depends on DEBUG_INPUT_INFO ---help--- The maXTouch tends to generate interrupts at a high rate during the contact. If verbose debug is enabled in this driver, you may not diff --git a/sched/Kconfig b/sched/Kconfig index 69b4945fd1..864220286a 100644 --- a/sched/Kconfig +++ b/sched/Kconfig @@ -1013,7 +1013,7 @@ config MODULE_BUFFERINCR config MODULE_DUMPBUFFER bool "Dump module buffers" default n - depends on DEBUG_FEATURES && CONFIG_DEBUG_INFO + depends on DEBUG_INFO ---help--- Dump various module buffers for debug purposes