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STM32F0: Fixes to get STM32F0-Discovery build again after changes to support the STM32F07x

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This commit is contained in:
Gregory Nutt 2017-04-17 17:13:32 -06:00
parent 2c01aaad59
commit 8b157b034d
4 changed files with 14 additions and 27 deletions
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6
arch/arm/include/stm32f0/chip.h
View File

@ -68,7 +68,7 @@
# define STM32F0_NCAP 13 /* Capacitive sensing channels (14 on UFQFPN32)) */
# define STM32F0_NPORTS 6 /* Six GPIO ports, GPIOA-F */
#if defined(CONFIG_ARCH_CHIP_SSTM32F072C8) || defined(CONFIG_ARCH_CHIP_SSTM32F072CB)
#elif defined(CONFIG_ARCH_CHIP_SSTM32F072C8) || defined(CONFIG_ARCH_CHIP_SSTM32F072CB)
# undef STM32F051x /* Not STM32F051x family */
# define STM32F072x 1 /* STM32F072x family */
@ -99,7 +99,7 @@
# define STM32F0_NCAP 17 /* Capacitive sensing channels */
# define STM32F0_NPORTS 6 /* Six GPIO ports, GPIOA-F */
#if defined(CONFIG_ARCH_CHIP_SSTM32F072R8) || defined(CONFIG_ARCH_CHIP_SSTM32F072RB)
#elif defined(CONFIG_ARCH_CHIP_SSTM32F072R8) || defined(CONFIG_ARCH_CHIP_SSTM32F072RB)
# undef STM32F051x /* Not STM32F051x family */
# define STM32F072x 1 /* STM32F072x family */
@ -130,7 +130,7 @@
# define STM32F0_NCAP 18 /* Capacitive sensing channels */
# define STM32F0_NPORTS 6 /* Six GPIO ports, GPIOA-F */
#if defined(CONFIG_ARCH_CHIP_SSTM32F072V8) || defined(CONFIG_ARCH_CHIP_SSTM32F072VB)
#elif defined(CONFIG_ARCH_CHIP_SSTM32F072V8) || defined(CONFIG_ARCH_CHIP_SSTM32F072VB)
# undef STM32F051x /* Not STM32F051x family */
# define STM32F072x 1 /* STM32F072x family */

6
arch/arm/src/stm32f0/chip/stm32f0_pinmap.h
View File

@ -43,8 +43,10 @@
#include <nuttx/config.h>
#include "chip.h"
#if defined(CONFIG_STM32F0_STM32F05X) || defined(CONFIG_STM32F0_STM32F07X)
# include "chip/stm32f05xr_pinmap.h"
#if defined(CONFIG_STM32F0_STM32F05X)
# include "chip/stm32f05x_pinmap.h"
#elif defined(CONFIG_STM32F0_STM32F07X)
# include "chip/stm32f07x_pinmap.h"
#else
# error "Unsupported STM32F0 pin map"
#endif

25
arch/arm/src/stm32f0/stm32f0_gpio.h
View File

@ -54,12 +54,7 @@
#include <arch/stm32f0/chip.h>
#include "chip.h"
#if defined(CONFIG_STM32F0_STM32F05X)
# include "chip/stm32f05xr_pinmap.h"
#else
# error "Unsupported STM32F0 chip"
#endif
#include "chip/stm32f0_pinmap.h"
/************************************************************************************
* Pre-Processor Declarations
@ -84,7 +79,7 @@
* ---- ---- ---- ---- ----
* Inputs: MMUU .... ...X PPPP BBBB
* Outputs: MMUU .... FFOV PPPP BBBB
* Alternate Functions: MMUU AAAA FFO. PPPP BBBB
* Alternate Functions: MMUU .AAA FFO. PPPP BBBB
* Analog: MM.. .... .... PPPP BBBB
*/
@ -122,11 +117,11 @@
* 1111 1111 1100 0000 0000
* 9876 5432 1098 7654 3210
* ---- ---- ---- ---- ----
* .... AAAA .... .... ....
* .... .AAA .... .... ....
*/
#define GPIO_AF_SHIFT (12) /* Bits 12-15: Alternate function */
#define GPIO_AF_MASK (15 << GPIO_AF_SHIFT)
#define GPIO_AF_SHIFT (12) /* Bits 12-14: Alternate function */
#define GPIO_AF_MASK (7 << GPIO_AF_SHIFT)
# define GPIO_AF(n) ((n) << GPIO_AF_SHIFT)
# define GPIO_AF0 (0 << GPIO_AF_SHIFT)
# define GPIO_AF1 (1 << GPIO_AF_SHIFT)
@ -136,14 +131,6 @@
# define GPIO_AF5 (5 << GPIO_AF_SHIFT)
# define GPIO_AF6 (6 << GPIO_AF_SHIFT)
# define GPIO_AF7 (7 << GPIO_AF_SHIFT)
# define GPIO_AF8 (8 << GPIO_AF_SHIFT)
# define GPIO_AF9 (9 << GPIO_AF_SHIFT)
# define GPIO_AF10 (10 << GPIO_AF_SHIFT)
# define GPIO_AF11 (11 << GPIO_AF_SHIFT)
# define GPIO_AF12 (12 << GPIO_AF_SHIFT)
# define GPIO_AF13 (13 << GPIO_AF_SHIFT)
# define GPIO_AF14 (14 << GPIO_AF_SHIFT)
# define GPIO_AF15 (15 << GPIO_AF_SHIFT)
/* Output/Alt function frequency selection:
*
@ -209,8 +196,6 @@
# define GPIO_PORTD (3 << GPIO_PORT_SHIFT) /* GPIOD */
# define GPIO_PORTE (4 << GPIO_PORT_SHIFT) /* GPIOE */
# define GPIO_PORTF (5 << GPIO_PORT_SHIFT) /* GPIOF */
# define GPIO_PORTG (6 << GPIO_PORT_SHIFT) /* GPIOG */
# define GPIO_PORTH (7 << GPIO_PORT_SHIFT) /* GPIOH */
/* This identifies the bit in the port:
*

4
arch/arm/src/stm32f0/stm32f0_lowputc.c
View File

@ -296,8 +296,8 @@ void stm32f0_lowsetup(void)
#if defined(HAVE_UART)
#if defined(HAVE_CONSOLE) && !defined(CONFIG_SUPPRESS_UART_CONFIG)
uint32_t cr;
uint32_t clken;
#endif
uint32_t clken;
#if defined(HAVE_CONSOLE)
/* Enable USART APB1/2 clock */
@ -305,7 +305,7 @@ void stm32f0_lowsetup(void)
modifyreg32(STM32F0_CONSOLE_APBREG, 0, STM32F0_CONSOLE_APBEN);
#endif
/* Enable the console USART and configure GPIO pins needed for rx/tx. */
/* Enable all GPIO modules */
clken = getreg32(STM32F0_RCC_AHBENR);
clken |= RCC_AHBENR_IOPAEN | RCC_AHBENR_IOPAEN | RCC_AHBENR_IOPAEN |\