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arch/risc-v: Update outdated comments

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Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
This commit is contained in:
Huang Qi 2022-02-25 15:21:41 +08:00 committed by Xiang Xiao
parent 7c99bce16e
commit 8b66280b4f
6 changed files with 6 additions and 17 deletions
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4
arch/README.txt
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@ -250,14 +250,12 @@ arch/risc-v
This directory is dedicated to ports to the RISC-V family.
Architecture Support
arch/risc-v/include/rv32im
arch/risc-v/include and arch/risc-v/common
MCU support
arch/risc-v/include/fe310 and arch/risc-v/src/fe310
arch/risc-v/include/k210 and arch/risc-v/src/k210
arch/risc-v/include/litex and arch/risc-v/src/litex
arch/risc-v/include/rv32im and arch/risc-v/src/rv32im
arch/risc-v/include/rv64gc and arch/risc-v/src/rv64gc
arch/x86 - Intel x86 architectures
This directory holds related, 32- and 64-bit architectures from

2
arch/risc-v/include/syscall.h
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@ -54,7 +54,7 @@
/* Configuration ************************************************************/
/* SYS call 1 and 2 are defined for internal use by the RISC-V port (see
* arch/risc-v/include/rv64gc/syscall.h). In addition, SYS call 3 is the
* arch/risc-v/include/syscall.h). In addition, SYS call 3 is the
* return from a SYS call in kernel mode. The first four syscall values must,
* therefore, be reserved (0 is not used).
*/

9
arch/risc-v/src/Makefile
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@ -24,19 +24,10 @@ ifeq ($(CONFIG_OPENSBI),y)
include opensbi/Make.defs
endif
# TODO: Merge these implementaions into one
ifeq ($(CONFIG_ARCH_RV32),y)
ARCH_SUBDIR = rv32im
else ifeq ($(CONFIG_ARCH_RV64),y)
ARCH_SUBDIR = rv64gc
endif
ARCH_SRCDIR = $(TOPDIR)$(DELIM)arch$(DELIM)$(CONFIG_ARCH)$(DELIM)src
INCLUDES += ${shell $(INCDIR) "$(CC)" $(ARCH_SRCDIR)$(DELIM)chip}
INCLUDES += ${shell $(INCDIR) "$(CC)" $(ARCH_SRCDIR)$(DELIM)common}
INCLUDES += ${shell $(INCDIR) "$(CC)" $(ARCH_SRCDIR)$(DELIM)$(ARCH_SUBDIR)}
INCLUDES += ${shell $(INCDIR) "$(CC)" $(TOPDIR)$(DELIM)sched}
ifeq ($(CONFIG_OPENSBI),y)
INCLUDES += $(shell $(INCDIR) "$(CC)" $(ARCH_SRCDIR)$(DELIM)opensbi$(DELIM)opensbi-3rdparty$(DELIM)include)

4
arch/risc-v/src/common/riscv_signal_dispatch.c
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@ -1,5 +1,5 @@
/****************************************************************************
* arch/risc-v/src/rv64gc/riscv_signal_dispatch.c
* arch/risc-v/src/common/riscv_signal_dispatch.c
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
@ -46,7 +46,7 @@
*
* Normally the user-mode signaling handling stub will also execute
* before the ultimate signal handler is called. See
* arch/risc-v/src/rv64gc/up_signal_handler.S. This function is the
* arch/risc-v/src/common/riscv_signal_handler.S. This function is the
* user-space, signal handler trampoline function. It is called from
* up_signal_dispatch() in user-mode.
*

2
arch/risc-v/src/common/riscv_signal_handler.S
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@ -1,5 +1,5 @@
/****************************************************************************
* arch/risc-v/src/rv64gc/riscv_signal_handler.S
* arch/risc-v/src/common/riscv_signal_handler.S
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with

2
arch/risc-v/src/common/svcall.h
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@ -59,7 +59,7 @@
# endif
#endif
/* RV64GC system calls ******************************************************/
/* RISC-V system calls ******************************************************/
/* SYS call 0:
*