arch: x86_64: Check only XSAVE and rename __eanble_sse3 to __enable_sse_avx
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@ -580,7 +580,7 @@ extern volatile struct gdt_entry_s *gdt64;
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int up_map_region(void *base, int size, int flags);
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void x86_64_check_and_enable_capability(void);
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extern void __enable_sse3(void);
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extern void __enable_sse_avx(void);
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extern void __revoke_low_memory(void);
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extern void __enable_pcid(void);
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@ -34,11 +34,12 @@ config ARCH_INTEL64_APIC_FREQ_KHZ
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endif
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config ARCH_INTEL64_HAVE_SSE3
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bool "SSE3 support"
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config ARCH_INTEL64_HAVE_XSAVE
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bool "XSAVE support"
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default y
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---help---
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Select to enable the use of SSE3 and FPU functions of x86_64
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Select to enable the use of XSAVE and FPU/SSE/AVX functions
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of x86_64
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config ARCH_INTEL64_HAVE_PCID
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bool "PCID support"
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@ -67,8 +67,7 @@ void x86_64_check_and_enable_capability(void)
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require |= X86_64_CPUID_01_TSCDEA;
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#endif
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#ifdef CONFIG_ARCH_INTEL64_HAVE_SSE3
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require |= X86_64_CPUID_01_SSE3;
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#ifdef CONFIG_ARCH_INTEL64_HAVE_XSAVE
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require |= X86_64_CPUID_01_XSAVE;
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#endif
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@ -90,8 +89,8 @@ void x86_64_check_and_enable_capability(void)
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goto err;
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}
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#ifdef CONFIG_ARCH_INTEL64_HAVE_SSE3
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__enable_sse3();
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#ifdef CONFIG_ARCH_INTEL64_HAVE_XSAVE
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__enable_sse_avx();
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#endif
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#ifdef CONFIG_ARCH_INTEL64_HAVE_PCID
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@ -63,7 +63,7 @@
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****************************************************************************/
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.global __pmode_entry /* The 32bit protected mode entry */
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.global __nxstart
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.global __enable_sse3
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.global __enable_sse_avx
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.global __enable_pcid
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.global __revoke_low_memory
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.global nx_start /* nx_start is defined elsewhere */
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@ -302,16 +302,16 @@ npd_loop:
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.size __revoke_low_memory, . - __revoke_low_memory
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/****************************************************************************
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* Name: __enable_sse3
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* Name: __enable_sse_avx
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*
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* Description:
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* Do low-level initialization SSE related processor setting
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*
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****************************************************************************/
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.type __enable_sse3, @function
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.type __enable_sse_avx, @function
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__enable_sse3:
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__enable_sse_avx:
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// Enable SSE
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mov %cr0, %rax
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mov $(X86_CR0_EM), %rbx
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@ -330,7 +330,7 @@ __enable_sse3:
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ret
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.size __enable_sse3, . - __enable_sse3
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.size __enable_sse_avx, . - __enable_sse_avx
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/****************************************************************************
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