Various fixes for errors ound while debugging OTG on L496
STM32, STM32 L4, and STM32 M4: USB OTGFS DMA trace output fix STM32: Add dump buffer feature to stm32 F4 series STM32 and STM32 L4: Fix bad USB OTGFS register address STM32 L4: Fix typo in USB OTGFS register usage STM32 L4: Add check in USB OTGFS driver to assure that SYSCFG is enabled Nucleo-L496ZG: Make HSE on Nucleo-L496ZG default to enable USB
This commit is contained in:
Miha Vrhovnik
Gregory Nutt
parent
b9bb2253b6
commit
8bb54368c8
@ -79,7 +79,7 @@
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#define STM32_OTGHS_CID_OFFSET 0x003c /* Core ID register */
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#define STM32_OTGHS_HPTXFSIZ_OFFSET 0x0100 /* Host periodic transmit FIFO size register */
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#define STM32_OTGHS_DIEPTXF_OFFSET(n) (104+(((n)-1) << 2))
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#define STM32_OTGHS_DIEPTXF_OFFSET(n) (0x0104+(((n)-1) << 2))
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#define STM32_OTGHS_DIEPTXF1_OFFSET 0x0104 /* Device IN endpoint transmit FIFO1 size register */
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#define STM32_OTGHS_DIEPTXF2_OFFSET 0x0108 /* Device IN endpoint transmit FIFO2 size register */
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#define STM32_OTGHS_DIEPTXF3_OFFSET 0x010c /* Device IN endpoint transmit FIFO3 size register */
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@ -78,7 +78,7 @@
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#define STM32_OTGFS_CID_OFFSET 0x003c /* Core ID register */
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#define STM32_OTGFS_HPTXFSIZ_OFFSET 0x0100 /* Host periodic transmit FIFO size register */
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#define STM32_OTGFS_DIEPTXF_OFFSET(n) (104+(((n)-1) << 2))
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#define STM32_OTGFS_DIEPTXF_OFFSET(n) (0x0104+(((n)-1) << 2))
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#define STM32_OTGFS_DIEPTXF1_OFFSET 0x0104 /* Device IN endpoint transmit FIFO1 size register */
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#define STM32_OTGFS_DIEPTXF2_OFFSET 0x0108 /* Device IN endpoint transmit FIFO2 size register */
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#define STM32_OTGFS_DIEPTXF3_OFFSET 0x010c /* Device IN endpoint transmit FIFO3 size register */
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@ -64,7 +64,6 @@
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#include "stm32_otgfs.h"
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#if defined(CONFIG_USBDEV) && (defined(CONFIG_STM32_OTGFS))
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/****************************************************************************
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* Pre-processor Definitions
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****************************************************************************/
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@ -284,6 +283,16 @@
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#define STM32_TRACEINTID_SETUPDONE (90 + 3)
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#define STM32_TRACEINTID_SETUPRECVD (90 + 4)
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/* CONFIG_USB_DUMPBUFFER will dump the contents of buffers to the console. */
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#undef CONFIG_USB_DUMPBUFFER
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#ifdef CONFIG_USB_DUMPBUFFER
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# define usb_dumpbuffer(t,b,l) uinfodumpbuffer(t,b,l)
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#else
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# define usb_dumpbuffer(t,b,l)
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#endif
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/* Endpoints ******************************************************************/
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/* Number of endpoints */
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@ -1081,6 +1090,8 @@ static void stm32_txfifo_write(FAR struct stm32_ep_s *privep,
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int nwords;
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int i;
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usb_dumpbuffer(">>>", buf, nbytes);
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/* Convert the number of bytes to words */
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nwords = (nbytes + 3) >> 2;
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@ -1469,6 +1480,8 @@ static void stm32_rxfifo_read(FAR struct stm32_ep_s *privep,
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*dest++ = data.b[2];
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*dest++ = data.b[3];
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}
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usb_dumpbuffer("<<<", dest-len, len);
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}
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/****************************************************************************
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@ -4337,7 +4350,7 @@ static void stm32_ep_freereq(FAR struct usbdev_ep_s *ep, FAR struct usbdev_req_s
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#ifdef CONFIG_USBDEV_DMA
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static void *stm32_ep_allocbuffer(FAR struct usbdev_ep_s *ep, unsigned bytes)
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{
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usbtrace(TRACE_EPALLOCBUFFER, privep->epphy);
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usbtrace(TRACE_EPALLOCBUFFER, ((FAR struct stm32_ep_s *)ep)->epphy);
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#ifdef CONFIG_USBDEV_DMAMEMORY
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return usbdev_dma_alloc(bytes);
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@ -4358,7 +4371,7 @@ static void *stm32_ep_allocbuffer(FAR struct usbdev_ep_s *ep, unsigned bytes)
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#ifdef CONFIG_USBDEV_DMA
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static void stm32_ep_freebuffer(FAR struct usbdev_ep_s *ep, FAR void *buf)
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{
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usbtrace(TRACE_EPFREEBUFFER, privep->epphy);
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usbtrace(TRACE_EPALLOCBUFFER, ((FAR struct stm32_ep_s *)ep)->epphy);
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#ifdef CONFIG_USBDEV_DMAMEMORY
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usbdev_dma_free(buf);
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@ -4358,7 +4358,7 @@ static void stm32_ep_freereq(FAR struct usbdev_ep_s *ep, FAR struct usbdev_req_s
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#ifdef CONFIG_USBDEV_DMA
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static void *stm32_ep_allocbuffer(FAR struct usbdev_ep_s *ep, unsigned bytes)
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{
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usbtrace(TRACE_EPALLOCBUFFER, privep->epphy);
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usbtrace(TRACE_EPALLOCBUFFER, ((FAR struct stm32_ep_s *)ep)->epphy);
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#ifdef CONFIG_USBDEV_DMAMEMORY
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return usbdev_dma_alloc(bytes);
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@ -4379,7 +4379,7 @@ static void *stm32_ep_allocbuffer(FAR struct usbdev_ep_s *ep, unsigned bytes)
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#ifdef CONFIG_USBDEV_DMA
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static void stm32_ep_freebuffer(FAR struct usbdev_ep_s *ep, FAR void *buf)
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{
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usbtrace(TRACE_EPFREEBUFFER, privep->epphy);
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usbtrace(TRACE_EPALLOCBUFFER, ((FAR struct stm32_ep_s *)ep)->epphy);
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#ifdef CONFIG_USBDEV_DMAMEMORY
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usbdev_dma_free(buf);
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@ -81,7 +81,7 @@
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#define STM32L4_OTGFS_GADPCTL_OFSSET 0x005c /* ADP timer, control and status register */
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#define STM32L4_OTGFS_HPTXFSIZ_OFFSET 0x0100 /* Host periodic transmit FIFO size register */
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#define STM32L4_OTGFS_DIEPTXF_OFFSET(n) (104+(((n)-1) << 2))
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#define STM32L4_OTGFS_DIEPTXF_OFFSET(n) (0x0104+(((n)-1) << 2))
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/* Host-mode control and status registers */
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@ -81,7 +81,7 @@
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#define STM32L4_OTGFS_GADPCTL_OFSSET 0x005c /* ADP timer, control and status register */
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#define STM32L4_OTGFS_HPTXFSIZ_OFFSET 0x0100 /* Host periodic transmit FIFO size register */
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#define STM32L4_OTGFS_DIEPTXF_OFFSET(n) (104+(((n)-1) << 2))
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#define STM32L4_OTGFS_DIEPTXF_OFFSET(n) (0x0104+(((n)-1) << 2))
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/* Host-mode control and status registers */
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@ -71,6 +71,10 @@
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****************************************************************************/
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/* Configuration ***************************************************************/
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#ifndef CONFIG_STM32L4_SYSCFG
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# error "CONFIG_STM32L4_SYSCFG is required"
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#endif
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#ifndef CONFIG_USBDEV_EP0_MAXSIZE
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# define CONFIG_USBDEV_EP0_MAXSIZE 64
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#endif
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@ -4404,7 +4408,7 @@ static void stm32l4_ep_freereq(FAR struct usbdev_ep_s *ep, FAR struct usbdev_req
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#ifdef CONFIG_USBDEV_DMA
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static void *stm32l4_ep_allocbuffer(FAR struct usbdev_ep_s *ep, unsigned bytes)
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{
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usbtrace(TRACE_EPALLOCBUFFER, privep->epphy);
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usbtrace(TRACE_EPALLOCBUFFER, ((FAR struct stm32l4_ep_s *)ep)->epphy);
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#ifdef CONFIG_USBDEV_DMAMEMORY
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return usbdev_dma_alloc(bytes);
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@ -4425,7 +4429,7 @@ static void *stm32l4_ep_allocbuffer(FAR struct usbdev_ep_s *ep, unsigned bytes)
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#ifdef CONFIG_USBDEV_DMA
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static void stm32l4_ep_freebuffer(FAR struct usbdev_ep_s *ep, FAR void *buf)
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{
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usbtrace(TRACE_EPFREEBUFFER, privep->epphy);
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usbtrace(TRACE_EPFREEBUFFER, ((FAR struct stm32l4_ep_s *)ep)->epphy);
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#ifdef CONFIG_USBDEV_DMAMEMORY
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usbdev_dma_free(buf);
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@ -5357,7 +5361,7 @@ static void stm32l4_hwinitialize(FAR struct stm32l4_usbdev_s *priv)
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address = STM32L4_RXFIFO_WORDS;
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regval = (address << OTGFS_DIEPTXF0_TX0FD_SHIFT) |
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(STM32L4_EP0_TXFIFO_WORDS << OTGFS_DIEPTXF0_TX0FSA_SHIFT);
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stm32l4_putreg(regval, STM32L4_OTGFS_DIEPTXF(0));
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stm32l4_putreg(regval, STM32L4_OTGFS_DIEPTXF0);
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#endif
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#if STM32L4_NENDPOINTS > 1
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@ -79,7 +79,7 @@
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#define STM32L4_HSE_FREQUENCY 8000000ul /* 8 MHz from MCO output */
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#define STM32L4_LSE_FREQUENCY 32768
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#define HSI_CLOCK_CONFIG
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#define HSE_CLOCK_CONFIG
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#if defined(HSI_CLOCK_CONFIG)
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@ -187,7 +187,212 @@
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#elif defined(HSE_CLOCK_CONFIG)
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# error "Not implemented"
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#define STM32L4_BOARD_USEHSE
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/* Prescaler common to all PLL inputs; will be 1 */
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#define STM32L4_PLLCFG_PLLM RCC_PLLCFG_PLLM(1)
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/* 'main' PLL config; we use this to generate our system clock via the R
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* output. We set it up as 8 MHz / 1 * 20 / 2 = 80 MHz
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*
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* XXX NOTE: currently the main PLL is implicitly turned on and is implicitly
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* the system clock; this should be configurable since not all applications may
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* want things done this way.
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*/
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#define STM32L4_PLLCFG_PLLN RCC_PLLCFG_PLLN(20)
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#define STM32L4_PLLCFG_PLLP 0
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#undef STM32L4_PLLCFG_PLLP_ENABLED
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#define STM32L4_PLLCFG_PLLQ RCC_PLLCFG_PLLQ_2
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#define STM32L4_PLLCFG_PLLQ_ENABLED
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#define STM32L4_PLLCFG_PLLR RCC_PLLCFG_PLLR_2
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#define STM32L4_PLLCFG_PLLR_ENABLED
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/* 'SAIPLL1' is used to generate the 48 MHz clock, since we can't
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* do that with the main PLL's N value. We set N = 12, and enable
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* the Q output (ultimately for CLK48) with /4. So,
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* 8 MHz / 1 * 12 / 2 = 48 MHz
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*
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* XXX NOTE: currently the SAIPLL /must/ be explicitly selected in the
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* menuconfig, or else all this is a moot point, and the various 48 MHz
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* peripherals will not work (RNG at present). I would suggest removing
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* that option from Kconfig altogether, and simply making it an option
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* that is selected via a #define here, like all these other params.
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*/
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#define STM32L4_PLLSAI1CFG_PLLN RCC_PLLSAI1CFG_PLLN(12)
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#define STM32L4_PLLSAI1CFG_PLLP 0
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#undef STM32L4_PLLSAI1CFG_PLLP_ENABLED
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#define STM32L4_PLLSAI1CFG_PLLQ RCC_PLLSAI1CFG_PLLQ_2
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#define STM32L4_PLLSAI1CFG_PLLQ_ENABLED
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#define STM32L4_PLLSAI1CFG_PLLR 0
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#undef STM32L4_PLLSAI1CFG_PLLR_ENABLED
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/* 'SAIPLL2' is not used in this application */
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#define STM32L4_PLLSAI2CFG_PLLN RCC_PLLSAI2CFG_PLLN(8)
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#define STM32L4_PLLSAI2CFG_PLLP 0
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#undef STM32L4_PLLSAI2CFG_PLLP_ENABLED
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#define STM32L4_PLLSAI2CFG_PLLR 0
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#undef STM32L4_PLLSAI2CFG_PLLR_ENABLED
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#define STM32L4_SYSCLK_FREQUENCY 80000000ul
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/* CLK48 will come from PLLSAI1 (implicitly Q) */
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#define STM32L4_USE_CLK48 1
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#define STM32L4_CLK48_SEL RCC_CCIPR_CLK48SEL_PLLSAI1
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/* Enable the LSE oscillator, used automatically trim the MSI, and for RTC */
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#define STM32L4_USE_LSE 1
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/* AHB clock (HCLK) is SYSCLK (80MHz) */
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#define STM32L4_RCC_CFGR_HPRE RCC_CFGR_HPRE_SYSCLK /* HCLK = SYSCLK / 1 */
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#define STM32L4_HCLK_FREQUENCY STM32L4_SYSCLK_FREQUENCY
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#define STM32L4_BOARD_HCLK STM32L4_HCLK_FREQUENCY /* Same as above, to satisfy compiler */
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/* APB1 clock (PCLK1) is HCLK/1 (80MHz) */
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#define STM32L4_RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_HCLK /* PCLK1 = HCLK / 1 */
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#define STM32L4_PCLK1_FREQUENCY (STM32L4_HCLK_FREQUENCY/1)
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/* Timers driven from APB1 will be twice PCLK1 */
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/* REVISIT : this can be configured */
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#define STM32L4_APB1_TIM2_CLKIN (2*STM32L4_PCLK1_FREQUENCY)
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#define STM32L4_APB1_TIM3_CLKIN (2*STM32L4_PCLK1_FREQUENCY)
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#define STM32L4_APB1_TIM4_CLKIN (2*STM32L4_PCLK1_FREQUENCY)
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#define STM32L4_APB1_TIM5_CLKIN (2*STM32L4_PCLK1_FREQUENCY)
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#define STM32L4_APB1_TIM6_CLKIN (2*STM32L4_PCLK1_FREQUENCY)
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#define STM32L4_APB1_TIM7_CLKIN (2*STM32L4_PCLK1_FREQUENCY)
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/* APB2 clock (PCLK2) is HCLK (80MHz) */
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#define STM32L4_RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_HCLK /* PCLK2 = HCLK / 1 */
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#define STM32L4_PCLK2_FREQUENCY (STM32L4_HCLK_FREQUENCY/1)
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/* Timers driven from APB2 will be twice PCLK2 */
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/* REVISIT : this can be configured */
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#define STM32L4_APB2_TIM1_CLKIN (2*STM32L4_PCLK2_FREQUENCY)
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#define STM32L4_APB2_TIM8_CLKIN (2*STM32L4_PCLK2_FREQUENCY)
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#define STM32L4_APB2_TIM15_CLKIN (2*STM32L4_PCLK2_FREQUENCY)
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#define STM32L4_APB2_TIM16_CLKIN (2*STM32L4_PCLK2_FREQUENCY)
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#define STM32L4_APB2_TIM17_CLKIN (2*STM32L4_PCLK2_FREQUENCY)
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/* Timer Frequencies, if APBx is set to 1, frequency is same to APBx
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* otherwise frequency is 2xAPBx.
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* Note: TIM1,8,15,16,17 are on APB2, others on APB1
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*/
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/* REVISIT : this can be configured */
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#elif defined(MSI_CLOCK_CONFIG)
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#define STM32L4_BOARD_USEMSI
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#define STM32L4_BOARD_MSIRANGE RCC_CR_MSIRANGE_4M
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/* Prescaler common to all PLL inputs; will be 1 */
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#define STM32L4_PLLCFG_PLLM RCC_PLLCFG_PLLM(1)
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/* 'main' PLL config; we use this to generate our system clock via the R
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* output. We set it up as 4 MHz / 1 * 40 / 2 = 80 MHz
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*
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* XXX NOTE: currently the main PLL is implicitly turned on and is implicitly
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* the system clock; this should be configurable since not all applications may
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* want things done this way.
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*/
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#define STM32L4_PLLCFG_PLLN RCC_PLLCFG_PLLN(40)
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#define STM32L4_PLLCFG_PLLP 0
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#undef STM32L4_PLLCFG_PLLP_ENABLED
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#define STM32L4_PLLCFG_PLLQ RCC_PLLCFG_PLLQ_2
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#define STM32L4_PLLCFG_PLLQ_ENABLED
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#define STM32L4_PLLCFG_PLLR RCC_PLLCFG_PLLR_2
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#define STM32L4_PLLCFG_PLLR_ENABLED
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/* 'SAIPLL1' is used to generate the 48 MHz clock, since we can't
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* do that with the main PLL's N value. We set N = 12, and enable
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* the Q output (ultimately for CLK48) with /4. So,
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* 4 MHz / 1 * 24 / 2 = 48 MHz
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*
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* XXX NOTE: currently the SAIPLL /must/ be explicitly selected in the
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* menuconfig, or else all this is a moot point, and the various 48 MHz
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* peripherals will not work (RNG at present). I would suggest removing
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* that option from Kconfig altogether, and simply making it an option
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* that is selected via a #define here, like all these other params.
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*/
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#define STM32L4_PLLSAI1CFG_PLLN RCC_PLLSAI1CFG_PLLN(24)
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#define STM32L4_PLLSAI1CFG_PLLP 0
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#undef STM32L4_PLLSAI1CFG_PLLP_ENABLED
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#define STM32L4_PLLSAI1CFG_PLLQ RCC_PLLSAI1CFG_PLLQ_2
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#define STM32L4_PLLSAI1CFG_PLLQ_ENABLED
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#define STM32L4_PLLSAI1CFG_PLLR 0
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#undef STM32L4_PLLSAI1CFG_PLLR_ENABLED
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/* 'SAIPLL2' is not used in this application */
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#define STM32L4_PLLSAI2CFG_PLLN RCC_PLLSAI2CFG_PLLN(8)
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#define STM32L4_PLLSAI2CFG_PLLP 0
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#undef STM32L4_PLLSAI2CFG_PLLP_ENABLED
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#define STM32L4_PLLSAI2CFG_PLLR 0
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#undef STM32L4_PLLSAI2CFG_PLLR_ENABLED
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#define STM32L4_SYSCLK_FREQUENCY 80000000ul
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/* CLK48 will come from PLLSAI1 (implicitly Q) */
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#define STM32L4_USE_CLK48 1
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#define STM32L4_CLK48_SEL RCC_CCIPR_CLK48SEL_PLLSAI1
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/* Enable the LSE oscillator, used automatically trim the MSI, and for RTC */
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#define STM32L4_USE_LSE 1
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/* AHB clock (HCLK) is SYSCLK (80MHz) */
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#define STM32L4_RCC_CFGR_HPRE RCC_CFGR_HPRE_SYSCLK /* HCLK = SYSCLK / 1 */
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#define STM32L4_HCLK_FREQUENCY STM32L4_SYSCLK_FREQUENCY
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#define STM32L4_BOARD_HCLK STM32L4_HCLK_FREQUENCY /* Same as above, to satisfy compiler */
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/* APB1 clock (PCLK1) is HCLK/1 (80MHz) */
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#define STM32L4_RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_HCLK /* PCLK1 = HCLK / 1 */
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#define STM32L4_PCLK1_FREQUENCY (STM32L4_HCLK_FREQUENCY/1)
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/* Timers driven from APB1 will be twice PCLK1 */
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/* REVISIT : this can be configured */
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#define STM32L4_APB1_TIM2_CLKIN (2*STM32L4_PCLK1_FREQUENCY)
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#define STM32L4_APB1_TIM3_CLKIN (2*STM32L4_PCLK1_FREQUENCY)
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#define STM32L4_APB1_TIM4_CLKIN (2*STM32L4_PCLK1_FREQUENCY)
|
||||
#define STM32L4_APB1_TIM5_CLKIN (2*STM32L4_PCLK1_FREQUENCY)
|
||||
#define STM32L4_APB1_TIM6_CLKIN (2*STM32L4_PCLK1_FREQUENCY)
|
||||
#define STM32L4_APB1_TIM7_CLKIN (2*STM32L4_PCLK1_FREQUENCY)
|
||||
|
||||
/* APB2 clock (PCLK2) is HCLK (80MHz) */
|
||||
|
||||
#define STM32L4_RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_HCLK /* PCLK2 = HCLK / 1 */
|
||||
#define STM32L4_PCLK2_FREQUENCY (STM32L4_HCLK_FREQUENCY/1)
|
||||
|
||||
/* Timers driven from APB2 will be twice PCLK2 */
|
||||
/* REVISIT : this can be configured */
|
||||
|
||||
#define STM32L4_APB2_TIM1_CLKIN (2*STM32L4_PCLK2_FREQUENCY)
|
||||
#define STM32L4_APB2_TIM8_CLKIN (2*STM32L4_PCLK2_FREQUENCY)
|
||||
#define STM32L4_APB2_TIM15_CLKIN (2*STM32L4_PCLK2_FREQUENCY)
|
||||
#define STM32L4_APB2_TIM16_CLKIN (2*STM32L4_PCLK2_FREQUENCY)
|
||||
#define STM32L4_APB2_TIM17_CLKIN (2*STM32L4_PCLK2_FREQUENCY)
|
||||
|
||||
/* Timer Frequencies, if APBx is set to 1, frequency is same to APBx
|
||||
* otherwise frequency is 2xAPBx.
|
||||
* Note: TIM1,8,15,16,17 are on APB2, others on APB1
|
||||
*/
|
||||
/* REVISIT : this can be configured */
|
||||
|
||||
#endif
|
||||
|
||||
|
||||
@ -322,7 +322,7 @@ int stm32_setup_overcurrent(xcpt_t handler, void *arg)
|
||||
************************************************************************************/
|
||||
|
||||
#ifdef CONFIG_USBDEV
|
||||
void stm32_usbsuspend(FAR struct usbdev_s *dev, bool resume)
|
||||
void stm32l4_usbsuspend(FAR struct usbdev_s *dev, bool resume)
|
||||
{
|
||||
uinfo("resume: %d\n", resume);
|
||||
}
|
||||
|
||||
Loading…
x
Reference in New Issue
Block a user