SAMD20: SPI driver is code-complete, but untested
This commit is contained in:
Gregory Nutt
parent
e013c96358
commit
8bbf4f3ec8
@ -6626,4 +6626,6 @@
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a lot of missing logic (2014-2-19).
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* arch/arm/src/lm/lm_lowputc.c and lm_serial.c: Several errors
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are unmasked with UARTs > UART2 are enabled. From gosha (2014-2-19).
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* arch/arm/src/samd/sam_spi.c: The SPI driver is code complete,
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but untested (2014-2-19).
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@ -145,15 +145,18 @@
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# define SPI_CTRLA_MODE_MASTER (3 << SPI_CTRLA_MODE_SHIFT) /* SPI master operation */
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#define SPI_CTRLA_RUNSTDBY (1 << 7) /* Bit 7: Run in standby */
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#define SPI_CTRLA_IBON (1 << 8) /* Bit 8: Immediate BUFOVF notification */
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#define SPI_CTRLA_DOPO (1 << 16) /* Bit 16: Data out pinout */
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# define SPI_CTRLA_DOPAD0 (0)
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# define SPI_CTRLA_DOPAD2 SPI_CTRLA_DOPO
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#define SPI_CTRLA_DOPO_SHIFT (16) /* Bit 16-17: Data out pinout */
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#define SPI_CTRLA_DOPO_MASK (3 << SPI_CTRLA_DOPO_SHIFT) /* Bit 16-17: Data out pinout */
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# define SPI_CTRLA_DOPO_DOPAD012 (0 << SPI_CTRLA_DOPO_SHIFT) /* D0=PAD0 SCK=PAD1 SS=PAD2 */
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# define SPI_CTRLA_DOPO_DOPAD231 (1 << SPI_CTRLA_DOPO_SHIFT) /* D0=PAD2 SCK=PAD3 SS=PAD1 */
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# define SPI_CTRLA_DOPO_DOPAD312 (2 << SPI_CTRLA_DOPO_SHIFT) /* D0=PAD3 SCK=PAD1 SS=PAD2 */
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# define SPI_CTRLA_DOPO_DOPAD031 (3 << SPI_CTRLA_DOPO_SHIFT) /* D0=PAD0 SCK=PAD3 SS=PAD1 */
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#define SPI_CTRLA_DIPO_SHIFT (20) /* Bits 20-21: Data in pinout */
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#define SPI_CTRLA_DIPO_MASK (3 << SPI_CTRLA_DIPO_SHIFT)
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# define SPI_CTRLA_DIPAD0 (0 << SPI_CTRLA_DIPO_SHIFT) /* SERCOM PAD[0] for DI */
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# define SPI_CTRLA_DIPAD1 (1 << SPI_CTRLA_DIPO_SHIFT) /* SERCOM PAD[1] for DI */
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# define SPI_CTRLA_DIPAD2 (2 << SPI_CTRLA_DIPO_SHIFT) /* SERCOM PAD[2] for DI */
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# define SPI_CTRLA_DIPAD3 (3 << SPI_CTRLA_DIPO_SHIFT) /* SERCOM PAD[3] for DI */
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# define SPI_CTRLA_DIPAD0 (0 << SPI_CTRLA_DIPO_SHIFT) /* SERCOM PAD0 for DI */
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# define SPI_CTRLA_DIPAD1 (1 << SPI_CTRLA_DIPO_SHIFT) /* SERCOM PAD1 for DI */
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# define SPI_CTRLA_DIPAD2 (2 << SPI_CTRLA_DIPO_SHIFT) /* SERCOM PAD2 for DI */
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# define SPI_CTRLA_DIPAD3 (3 << SPI_CTRLA_DIPO_SHIFT) /* SERCOM PAD3 for DI */
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#define SPI_CTRLA_FORM_SHIFT (24) /* Bits 24-27: Frame format */
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#define SPI_CTRLA_FORM_MASK (7 << SPI_CTRLA_FORM_SHIFT)
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# define SPI_CTRLA_FORM_SPI (0 << SPI_CTRLA_FORM_SHIFT) /* SPI frame (no address) */
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@ -56,6 +56,8 @@
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#include "sam_config.h"
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#include <arch/board/board.h>
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#include "chip/sam_pm.h"
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#include "chip/sam_gclk.h"
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#include "chip/sam_usart.h"
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@ -301,7 +303,7 @@ int sam_usart_internal(const struct sam_usart_config_s * const config)
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/* Configure the GCLKs for the SERCOM module */
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sercom_coreclk_configure(config->sercom, config->gclkgen, false);
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sercom_slowclk_configure(config->gclkgen);
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sercom_slowclk_configure(BOARD_SERCOM_SLOW_GCLKGEN);
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/* Set USART configuration according to the board configuration */
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@ -44,7 +44,9 @@
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#include <stdbool.h>
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#include "up_arch.h"
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#include "sam_config.h"
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#include "chip/sam_pm.h"
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/****************************************************************************
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* Pre-processor Definitions
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@ -85,7 +87,7 @@ extern "C"
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*
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****************************************************************************/
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static inline int sercom_enable(int sercom)
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static inline void sercom_enable(int sercom)
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{
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uint32_t regval;
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@ -561,7 +561,7 @@ static int sam_interrupt(struct uart_dev_s *dev)
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uint8_t intflag;
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uint8_t inten;
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/* Get the set of pending USART usarts (we are only interested in the
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/* Get the set of pending USART interrupts (we are only interested in the
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* unmasked interrupts).
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*/
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@ -114,7 +114,9 @@ struct sam_spidev_s
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/* Fixed configuration */
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uint8_t sercom; /* Identifies the SERCOM peripheral */
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#if 0 /* Not used */
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uint8_t irq; /* SERCOM IRQ number */
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#endif
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uint8_t gclkgen; /* Source GCLK generator */
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port_pinset_t pad0; /* Pin configuration for PAD0 */
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port_pinset_t pad1; /* Pin configuration for PAD1 */
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@ -123,6 +125,9 @@ struct sam_spidev_s
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uint32_t muxconfig; /* Pad multiplexing configuration */
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uint32_t srcfreq; /* Source clock frequency */
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uintptr_t base; /* SERCOM base address */
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#if 0 /* Not used */
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xcpt_t handler; /* SERCOM interrupt handler */
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#endif
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/* Dynamic configuration */
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@ -151,29 +156,54 @@ struct sam_spidev_s
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/* Helpers */
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#ifdef CONFIG_SAMD_SPI_REGDEBUG
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static bool spi_checkreg(struct sam_spidev_s *spi, bool wr,
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static bool spi_checkreg(struct sam_spidev_s *priv, bool wr,
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uint32_t regval, uint32_t regaddr);
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#else
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# define spi_checkreg(spi,wr,regval,regaddr) (false)
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# define spi_checkreg(priv,wr,regval,regaddr) (false)
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#endif
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static uint8_t spi_getreg8(struct sam_spidev_s *spi,
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static uint8_t spi_getreg8(struct sam_spidev_s *priv,
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unsigned int offset);
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static void spi_putreg8(struct sam_spidev_s *spi, uint8_t regval,
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static void spi_putreg8(struct sam_spidev_s *priv, uint8_t regval,
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unsigned int offset);
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static uint16_t spi_getreg16(struct sam_spidev_s *spi,
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static uint16_t spi_getreg16(struct sam_spidev_s *priv,
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unsigned int offset);
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static void spi_putreg16(struct sam_spidev_s *spi, uint16_t regval,
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static void spi_putreg16(struct sam_spidev_s *priv, uint16_t regval,
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unsigned int offset);
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static uint32_t spi_getreg32(struct sam_spidev_s *spi,
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static uint32_t spi_getreg32(struct sam_spidev_s *priv,
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unsigned int offset);
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static void spi_putreg32(struct sam_spidev_s *spi, uint32_t regval,
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static void spi_putreg32(struct sam_spidev_s *priv, uint32_t regval,
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unsigned int offset);
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#if defined(CONFIG_DEBUG_SPI) && defined(CONFIG_DEBUG_VERBOSE)
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static void spi_dumpregs(struct sam_spidev_s *spi, const char *msg);
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static void spi_dumpregs(struct sam_spidev_s *priv, const char *msg);
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#else
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# define spi_dumpregs(spi,msg)
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# define spi_dumpregs(priv,msg)
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#endif
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/* Interrupt handling */
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#if 0 /* Not used */
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static int spi_interrupt(struct sam_spidev_s *dev);
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#ifdef SAMD_HAVE_USART0
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static int spi0_interrupt(int irq, void *context);
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#endif
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#ifdef SAMD_HAVE_USART1
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static int spi1_interrupt(int irq, void *context);
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#endif
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#ifdef SAMD_HAVE_USART2
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static int spi2_interrupt(int irq, void *context);
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#endif
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#ifdef SAMD_HAVE_USART3
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static int spi3_interrupt(int irq, void *context);
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#endif
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#ifdef SAMD_HAVE_USART4
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static int spi4_interrupt(int irq, void *context);
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#endif
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#ifdef SAMD_HAVE_USART5
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static int spi5_interrupt(int irq, void *context);
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#endif
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#endif
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/* SPI methods */
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@ -234,7 +264,9 @@ static struct sam_spidev_s g_spi0dev =
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{
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.ops = &g_spi0ops,
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.sercom = 0,
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#if 0 /* Not used */
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.irq = SAM_IRQ_SERCOM0,
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#endif
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.gclkgen = (BOARD_SERCOM0_GCLKGEN >> GCLK_CLKCTRL_GEN_SHIFT),
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.pad0 = BOARD_SERCOM0_PINMAP_PAD0,
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.pad1 = BOARD_SERCOM0_PINMAP_PAD1,
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@ -243,6 +275,9 @@ static struct sam_spidev_s g_spi0dev =
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.muxconfig = BOARD_SERCOM0_MUXCONFIG,
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.srcfreq = BOARD_SERCOM0_FREQUENCY,
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.base = SAM_SERCOM0_BASE,
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#if 0 /* Not used */
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.handler = spi0_interrupt,
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#endif
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#ifndef CONFIG_SPI_OWNBUS
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.spilock = SEM_INITIALIZER(1),
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#endif
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@ -281,7 +316,9 @@ static struct sam_spidev_s g_spi1dev =
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{
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.ops = &g_spi1ops,
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.sercom = 1,
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#if 0 /* Not used */
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.irq = SAM_IRQ_SERCOM1,
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#endif
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.gclkgen = (BOARD_SERCOM1_GCLKGEN >> GCLK_CLKCTRL_GEN_SHIFT),
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.pad0 = BOARD_SERCOM1_PINMAP_PAD0,
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.pad1 = BOARD_SERCOM1_PINMAP_PAD1,
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@ -290,6 +327,9 @@ static struct sam_spidev_s g_spi1dev =
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.muxconfig = BOARD_SERCOM1_MUXCONFIG,
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.srcfreq = BOARD_SERCOM1_FREQUENCY,
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.base = SAM_SERCOM1_BASE,
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#if 0 /* Not used */
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.handler = spi1_interrupt,
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#endif
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#ifndef CONFIG_SPI_OWNBUS
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.spilock = SEM_INITIALIZER(1),
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#endif
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@ -328,7 +368,9 @@ static struct sam_spidev_s g_spi2dev =
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{
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.ops = &g_spi1ops,
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.sercom = 2,
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#if 0 /* Not used */
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.irq = SAM_IRQ_SERCOM2,
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#endif
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.gclkgen = (BOARD_SERCOM2_GCLKGEN >> GCLK_CLKCTRL_GEN_SHIFT),
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.pad0 = BOARD_SERCOM2_PINMAP_PAD0,
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.pad1 = BOARD_SERCOM2_PINMAP_PAD1,
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@ -337,6 +379,9 @@ static struct sam_spidev_s g_spi2dev =
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.muxconfig = BOARD_SERCOM2_MUXCONFIG,
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.srcfreq = BOARD_SERCOM2_FREQUENCY,
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.base = SAM_SERCOM2_BASE,
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#if 0 /* Not used */
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.handler = spi2_interrupt,
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#endif
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#ifndef CONFIG_SPI_OWNBUS
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.spilock = SEM_INITIALIZER(1),
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#endif
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@ -375,7 +420,9 @@ static struct sam_spidev_s g_spi3dev =
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{
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.ops = &g_spi3ops,
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.sercom = 3,
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#if 0 /* Not used */
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.irq = SAM_IRQ_SERCOM3,
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#endif
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.gclkgen = (BOARD_SERCOM3_GCLKGEN >> GCLK_CLKCTRL_GEN_SHIFT),
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.pad0 = BOARD_SERCOM3_PINMAP_PAD0,
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.pad1 = BOARD_SERCOM3_PINMAP_PAD1,
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@ -384,6 +431,9 @@ static struct sam_spidev_s g_spi3dev =
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.muxconfig = BOARD_SERCOM3_MUXCONFIG,
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.srcfreq = BOARD_SERCOM3_FREQUENCY,
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.base = SAM_SERCOM3_BASE,
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#if 0 /* Not used */
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.handler = spi3_interrupt,
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#endif
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#ifndef CONFIG_SPI_OWNBUS
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.spilock = SEM_INITIALIZER(1),
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#endif
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@ -422,7 +472,9 @@ static struct sam_spidev_s g_spi4dev =
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{
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.ops = &g_spi4ops,
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.sercom = 4,
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#if 0 /* Not used */
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.irq = SAM_IRQ_SERCOM4,
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#endif
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.gclkgen = (BOARD_SERCOM4_GCLKGEN >> GCLK_CLKCTRL_GEN_SHIFT),
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.pad0 = BOARD_SERCOM4_PINMAP_PAD0,
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.pad1 = BOARD_SERCOM4_PINMAP_PAD1,
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@ -431,6 +483,9 @@ static struct sam_spidev_s g_spi4dev =
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.muxconfig = BOARD_SERCOM4_MUXCONFIG,
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.srcfreq = BOARD_SERCOM4_FREQUENCY,
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.base = SAM_SERCOM4_BASE,
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#if 0 /* Not used */
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.handler = spi4_interrupt,
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#endif
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#ifndef CONFIG_SPI_OWNBUS
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.spilock = SEM_INITIALIZER(1),
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#endif
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@ -469,7 +524,9 @@ static struct sam_spidev_s g_spi5dev =
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{
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.ops = &g_spi5ops,
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.sercom = 5,
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#if 0 /* Not used */
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.irq = SAM_IRQ_SERCOM5,
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#endif
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.gclkgen = (BOARD_SERCOM5_GCLKGEN >> GCLK_CLKCTRL_GEN_SHIFT),
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.pad0 = BOARD_SERCOM5_PINMAP_PAD0,
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.pad1 = BOARD_SERCOM5_PINMAP_PAD1,
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@ -478,6 +535,9 @@ static struct sam_spidev_s g_spi5dev =
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.muxconfig = BOARD_SERCOM5_MUXCONFIG,
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.srcfreq = BOARD_SERCOM5_FREQUENCY,
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.base = SAM_SERCOM5_BASE,
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#if 0 /* Not used */
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.handler = spi5_interrupt,
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#endif
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#ifndef CONFIG_SPI_OWNBUS
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.spilock = SEM_INITIALIZER(1),
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#endif
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@ -717,6 +777,115 @@ static void spi_dumpregs(struct sam_spidev_s *priv, const char *msg)
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}
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#endif
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/****************************************************************************
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* Name: spi_interrupt
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*
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* Description:
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* This is the USART interrupt handler. It will be invoked when an
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* interrupt received on the 'irq' It should call uart_transmitchars or
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* uart_receivechar to perform the appropriate data transfers. The
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* interrupt handling logic must be able to map the 'irq' number into the
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* approprite sam_spidev_s structure in order to call these functions.
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*
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****************************************************************************/
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#if 0 /* Not used */
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static int spi_interrupt(struct sam_spidev_s *dev)
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{
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struct sam_dev_s *priv = (struct sam_dev_s*)dev->priv;;
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uint8_t pending;
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uint8_t intflag;
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uint8_t inten;
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/* Get the set of pending SPI interrupts (we are only interested in the
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* unmasked interrupts).
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*/
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intflag = sam_serialin8(priv, SAM_USART_INTFLAG_OFFSET);
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inten = sam_serialin8(priv, SAM_USART_INTENCLR_OFFSET);
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pending = intflag & inten;
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/* Handle an incoming, receive byte. The RXC flag is set when there is
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* unread data in DATA register. This flag is cleared by reading the DATA
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* register (or by disabling the receiver).
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*/
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if ((pending & USART_INT_RXC) != 0)
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{
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/* Received data ready... process incoming SPI ata */
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#warning Missing logic
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}
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/* Handle outgoing, transmit bytes. The DRE flag is set when the DATA
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* register is empty and ready to be written. This flag is cleared by
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* writing new data to the DATA register. If there is no further data to
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* be transmitted, the serial driver will disable TX interrupts, prohibit
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* further interrupts until TX interrupts are re-enabled.
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*/
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if ((pending & USART_INT_DRE) != 0)
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{
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/* Transmit data register empty ... process outgoing bytes */
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#warning Missing logic
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}
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return OK;
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}
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#endif
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/****************************************************************************
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* Name: spiN_interrupt
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*
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* Description:
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* Handle each SERCOM USART interrupt by calling the common interrupt
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* handling logic with the USART-specific state.
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*
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****************************************************************************/
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#if 0 /* Not used */
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#ifdef SAMD_HAVE_USART0
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static int spi0_interrupt(int irq, void *context)
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{
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return spi_interrupt(&g_spi0dev);
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}
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#endif
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#ifdef SAMD_HAVE_USART1
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static int spi1_interrupt(int irq, void *context)
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{
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return spi_interrupt(&g_spi1dev);
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}
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#endif
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#ifdef SAMD_HAVE_USART2
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static int spi2_interrupt(int irq, void *context)
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{
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return spi_interrupt(&g_spi2dev);
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}
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#endif
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#ifdef SAMD_HAVE_USART3
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static int spi3_interrupt(int irq, void *context)
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{
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return spi_interrupt(&g_spi3dev);
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}
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#endif
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#ifdef SAMD_HAVE_USART4
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static int spi4_interrupt(int irq, void *context)
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{
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return spi_interrupt(&g_spi4dev);
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}
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#endif
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#ifdef SAMD_HAVE_USART5
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static int spi5_interrupt(int irq, void *context)
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{
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return spi_interrupt(&g_spi5dev);
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}
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#endif
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#endif
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/****************************************************************************
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* Name: spi_lock
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*
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@ -784,10 +953,23 @@ static int spi_lock(struct spi_dev_s *dev, bool lock)
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static uint32_t spi_setfrequency(struct spi_dev_s *dev, uint32_t frequency)
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{
|
||||
struct sam_spidev_s *priv =(struct sam_spidev_s *)dev;
|
||||
uint32_t maxfreq;
|
||||
uint32_t actual;
|
||||
uint32_t baud;
|
||||
|
||||
spivdbg("sercom=%d frequency=%d\n", priv->sercom, frequency);
|
||||
|
||||
/* Check if the configured BAUD is within the valid range */
|
||||
|
||||
maxfreq = (priv->srcfreq >> 1);
|
||||
if (frequency > maxfreq)
|
||||
{
|
||||
/* Set the frequency to the maximum */
|
||||
|
||||
spidbg("ERROR: Cannot realize frequency: %ld\n", (long)frequency);
|
||||
frequency = maxfreq;
|
||||
}
|
||||
|
||||
/* Check if the requested frequency is the same as the frequency selection */
|
||||
|
||||
#ifndef CONFIG_SPI_OWNBUS
|
||||
@ -799,15 +981,33 @@ static uint32_t spi_setfrequency(struct spi_dev_s *dev, uint32_t frequency)
|
||||
}
|
||||
#endif
|
||||
|
||||
/* Configure SPI to a frequency as close as possible to the requested
|
||||
* frequency.
|
||||
/* For synchronous mode, the BAUAD rate (Fbaud) is generated from the
|
||||
* source clock frequency (Fref) as follows:
|
||||
*
|
||||
* Fbaud = Fref / (2 * (BAUD + 1))
|
||||
*
|
||||
* Or
|
||||
*
|
||||
* BAUD = (Fref / (2 * Fbaud)) - 1
|
||||
*
|
||||
* Where BAUD <= 255
|
||||
*/
|
||||
#warning Missing logic
|
||||
|
||||
baud = ((priv->srcfreq + frequency) / (frequency << 1)) - 1;
|
||||
|
||||
/* Verify that the resulting if BAUD divisor is within range */
|
||||
|
||||
if (baud > 255)
|
||||
{
|
||||
spidbg("ERROR: BAUD is out of range: %ld\n", (long)baud);
|
||||
baud = 255;
|
||||
}
|
||||
|
||||
spi_putreg8(priv, (uint8_t)baud, SAM_SPI_BAUD_OFFSET);
|
||||
|
||||
/* Calculate the new actual frequency */
|
||||
#warning Missing logic
|
||||
|
||||
spivdbg("actual=%d\n", offset, regval, actual);
|
||||
actual = priv->srcfreq / ((baud + 1) << 1);
|
||||
|
||||
/* Save the frequency setting */
|
||||
|
||||
@ -816,7 +1016,7 @@ static uint32_t spi_setfrequency(struct spi_dev_s *dev, uint32_t frequency)
|
||||
priv->actual = actual;
|
||||
#endif
|
||||
|
||||
spidbg("Frequency %d->%d\n", frequency, actual);
|
||||
spivdbg("Frequency %d->%d\n", frequency, actual);
|
||||
return actual;
|
||||
}
|
||||
|
||||
@ -909,13 +1109,6 @@ static void spi_setbits(struct spi_dev_s *dev, int nbits)
|
||||
spivdbg("sercom=%d nbits=%d\n", priv->sercom, nbits);
|
||||
DEBUGASSERT(priv && nbits > 7 && nbits < 10);
|
||||
|
||||
/* NOTE: The logic in spi_send and in spi_exchange only handles 8-bit
|
||||
* data at the present time. So the following extra assertion is a
|
||||
* reminder that we have to fix that someday.
|
||||
*/
|
||||
|
||||
DEBUGASSERT(nbits == 8); /* Temporary -- FIX ME */
|
||||
|
||||
/* Has the number of bits changed? */
|
||||
|
||||
#ifndef CONFIG_SPI_OWNBUS
|
||||
@ -1001,12 +1194,28 @@ static void spi_exchange(struct spi_dev_s *dev, const void *txbuffer,
|
||||
void *rxbuffer, size_t nwords)
|
||||
{
|
||||
struct sam_spidev_s *priv = (struct sam_spidev_s *)dev;
|
||||
cont uint8_t *txptr = (const uint8_t *)txbuffer;
|
||||
uint8_t *rxptr = (uint8_t *)rxbuffer;
|
||||
const uint16_t *ptx16 = NULL;
|
||||
const uint8_t *ptx8 = NULL;
|
||||
uint16_t *prx16 = NULL;
|
||||
uint8_t *prx8 = NULL;
|
||||
uint16_t data;
|
||||
|
||||
spivdbg("txbuffer=%p rxbuffer=%p nwords=%d\n", txbuffer, rxbuffer, nwords);
|
||||
|
||||
/* Set up data receive and transmit pointers */
|
||||
|
||||
wide = ;
|
||||
if (priv->nbits > 8)
|
||||
{
|
||||
ptx16 = (const uint16_t *)txbuffer;
|
||||
prx16 = (uint16_t *)rxbuffer;
|
||||
}
|
||||
else
|
||||
{
|
||||
ptx8 = (const uint8_t *)txbuffer;
|
||||
prx8 = (uint8_t *)rxbuffer;
|
||||
}
|
||||
|
||||
/* Loop, sending each word in the user-provided data buffer.
|
||||
*
|
||||
* Note 1: Right now, this only deals with 8-bit words. If the SPI
|
||||
@ -1040,13 +1249,17 @@ static void spi_exchange(struct spi_dev_s *dev, const void *txbuffer,
|
||||
{
|
||||
/* Get the data to send (0xff if there is no data source) */
|
||||
|
||||
if (txptr)
|
||||
if (ptx8)
|
||||
{
|
||||
data = (uint32_t)*txptr++;
|
||||
data = (uint16_t)*ptx8++;
|
||||
}
|
||||
else if (ptx16)
|
||||
{
|
||||
data = *ptx16++;
|
||||
}
|
||||
else
|
||||
{
|
||||
data = 0xffff;
|
||||
data = 0x01ff;
|
||||
}
|
||||
|
||||
/* Wait for any previous data written to the DATA register to be
|
||||
@ -1063,14 +1276,33 @@ static void spi_exchange(struct spi_dev_s *dev, const void *txbuffer,
|
||||
|
||||
while ((spi_getreg32(priv, SAM_SPI_INTFLAG_OFFSET) & SPI_INT_RXC) == 0);
|
||||
|
||||
/* Check for data overflow. The BUFOVF bit provides the status of the
|
||||
* next DATA to be read. On buffer overflow, the corresponding DATA
|
||||
* will be 0.
|
||||
*/
|
||||
|
||||
data = spi_getreg16(priv, SAM_SPI_STATUS_OFFSET);
|
||||
if (data & SPI_STATUS_BUFOVF) != 0)
|
||||
{
|
||||
spidbg("ERROR: Buffer overflow!\n");
|
||||
|
||||
/* Clear the buffer overflow flag */
|
||||
|
||||
spi_putreg(priv, data, SAM_SPI_STATUS_OFFSET);
|
||||
}
|
||||
|
||||
/* Read the received data from the SPI DATA Register..
|
||||
* TODO: The following only works if nbits <= 8.
|
||||
*/
|
||||
|
||||
data = spi_getreg16(priv, SAM_SPI_DATA_OFFSET);
|
||||
if (rxptr)
|
||||
if (prx8)
|
||||
{
|
||||
*rxptr++ = (uint8_t)data;
|
||||
*prx8++ = (uint8_t)data;
|
||||
}
|
||||
else if (prx16)
|
||||
{
|
||||
*prx16++ = (uint16_t)data;
|
||||
}
|
||||
}
|
||||
}
|
||||
@ -1131,6 +1363,19 @@ static void spi_recvblock(struct spi_dev_s *dev, void *buffer, size_t nwords)
|
||||
}
|
||||
#endif
|
||||
|
||||
/****************************************************************************
|
||||
* Name: spi_wait_synchronization
|
||||
*
|
||||
* Description:
|
||||
* Wait until the SERCOM SPI reports that it is synchronized.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
static void spi_wait_synchronization(struct sam_spidev_s *priv)
|
||||
{
|
||||
while ((getreg16(priv->base + SAM_USART_STATUS_OFFSET) & USART_STATUS_SYNCBUSY) != 0);
|
||||
}
|
||||
|
||||
/****************************************************************************
|
||||
* Name: spi_pad_configure
|
||||
*
|
||||
@ -1186,10 +1431,9 @@ struct spi_dev_s *up_spiinitialize(int port)
|
||||
{
|
||||
struct sam_spidev_s *priv;
|
||||
irqstate_t flags;
|
||||
#ifndef CONFIG_SPI_OWNBUS
|
||||
uint32_t regval;
|
||||
unsigned int offset;
|
||||
#endif
|
||||
uint32_t baud;
|
||||
int ret;
|
||||
|
||||
/* Get the port state structure */
|
||||
|
||||
@ -1247,36 +1491,84 @@ struct spi_dev_s *up_spiinitialize(int port)
|
||||
return NULL;
|
||||
}
|
||||
|
||||
/* Enable clocking to the SPI SERCOM */
|
||||
/* Enable clocking to the SERCOM module in PM */
|
||||
|
||||
flags = irqsave();
|
||||
#warning Missing logic
|
||||
flags = irqsave();
|
||||
sercom_enable(priv->sercom);
|
||||
|
||||
/* Configure multiplexed pins as connected on the board. */
|
||||
#warning Missing logic
|
||||
/* Configure the GCLKs for the SERCOM module */
|
||||
|
||||
/* Execute a software reset of the SPI SERCOM */
|
||||
#warning Missing logic
|
||||
sercom_coreclk_configure(priv->sercom, priv->gclkgen, false);
|
||||
sercom_slowclk_configure(BOARD_SERCOM_SLOW_GCLKGEN);
|
||||
|
||||
/* Configure the SPI SERCOM */
|
||||
#warning Missing logic
|
||||
/* Set the SERCOM in SPI master mode */
|
||||
|
||||
/* And enable the SPI */
|
||||
#warning Missing logic
|
||||
regval = spi_getreg32(priv, SAM_SPI_CTRLA_OFFSET);
|
||||
regval &= ~SPI_CTRLA_MODE_MASK;
|
||||
regval |= SPI_CTRLA_MODE_MASTER;
|
||||
spi_putreg32(priv, regval, SAM_SPI_CTRLA_OFFSET);
|
||||
|
||||
spi_dumpregs(priv, "After initialization");
|
||||
/* Configure pads */
|
||||
|
||||
#ifndef CONFIG_SPI_OWNBUS
|
||||
/* Set to mode=0 and nbits=8 and some initial frequency. It is only
|
||||
* critical to do this if CONFIG_SPI_OWNBUS is not defined because in
|
||||
* that case, the SPI will only be reconfigured if there is a change.
|
||||
spi_pad_configure(priv);
|
||||
|
||||
/* Set an initial baud value. This will be changed by the upper-half
|
||||
* driver as soon as it starts.
|
||||
*/
|
||||
|
||||
spi_setmode((struct spi_dev_s *)priv, SPIDEV_MODE0);
|
||||
spi_setfrequency((struct spi_dev_s *)priv, 400000);
|
||||
spi_setbits((struct spi_dev_s *)priv, 8);
|
||||
(void)spi_setfrequency((struct spi_dev_s *)priv, 400000);
|
||||
|
||||
/* Set MSB first data order and the configured pad mux setting,
|
||||
* Note that SPI mode 0 are assumed initially.
|
||||
*/
|
||||
|
||||
regval = (SPI_DATA_ORDER_MSB | priv->muxconfig);
|
||||
spi_putreg8(priv, regval, SAM_SPI_CTRLA_OFFSET);
|
||||
|
||||
/* Enable the receiver. Note that 8-bit data width is assumed initially */
|
||||
|
||||
regval = SPI_CTRLB_RXEN;
|
||||
spi_putreg8(priv, regval, SAM_SPI_CTRLB_OFFSET);
|
||||
|
||||
#ifndef CONFIG_SPI_OWNBUS
|
||||
priv->nbits = nbits;
|
||||
#endif
|
||||
|
||||
/* Wait until the synchronization is complete */
|
||||
|
||||
spi_wait_synchronization(priv);
|
||||
|
||||
/* Enable SPI */
|
||||
|
||||
regval = spi_getreg32(priv, SAM_SPI_CTRLA_OFFSET);
|
||||
regval |= SPI_CTRLA_ENABLE;
|
||||
spi_putreg32(priv, regval, SAM_SPI_CTRLA_OFFSET);
|
||||
|
||||
/* Disable all interrupts at the SPI source and clear all pending
|
||||
* status that we can.
|
||||
*/
|
||||
|
||||
spi_putreg8(priv, SPI_INT_ALL, SAM_SPI_INTENCLR_OFFSET);
|
||||
spi_putreg8(priv, SPI_INT_ALL, SAM_SPI_INTFLAG_OFFSET);
|
||||
spi_putreg16(priv, SPI_STATUS_CLRALL, SAM_SPI_STATUS_OFFSET);
|
||||
|
||||
#if 0 /* Not used */
|
||||
/* Attach and enable the SERCOM interrupt handler */
|
||||
|
||||
ret = irq_attach(priv->irq, priv->handler);
|
||||
if (ret < 0)
|
||||
{
|
||||
spidbg("ERROR: Failed to attach interrupt: %d\n", irq);
|
||||
return NULL;
|
||||
}
|
||||
|
||||
/* Enable SERCOM interrupts at the NVIC */
|
||||
|
||||
up_enable_irq(priv->irq);
|
||||
#endif
|
||||
|
||||
spi_dumpregs(priv, "After initialization");
|
||||
irqrestore(flags);
|
||||
return (struct spi_dev_s *)priv;
|
||||
}
|
||||
|
||||
|
||||
@ -355,7 +355,65 @@
|
||||
#endif
|
||||
|
||||
/* SERCOM definitions ***************************************************************/
|
||||
/* SERCOM4 is available on connectors EXT1, EXT2, and EXT3
|
||||
/* This is the source clock generator for the GCLK_SERCOM_SLOW clock that is common
|
||||
* to all SERCOM modules.
|
||||
*/
|
||||
|
||||
#define BOARD_SERCOM_SLOW_GCLKGEN (GCLK_CLKCTRL_GEN0 >> GCLK_CLKCTRL_GEN_SHIFT)
|
||||
|
||||
/* SERCOM0 SPI is available on EXT1
|
||||
*
|
||||
* PIN PORT SERCOM FUNCTION
|
||||
* --- ------------------ -----------
|
||||
* 15 PA5 SERCOM0 PAD1 SPI SS
|
||||
* 16 PA6 SERCOM0 PAD2 SPI MOSI
|
||||
* 17 PA4 SERCOM0 PAD0 SPI MISO
|
||||
* 18 PA7 SERCOM0 PAD3 SPI SCK
|
||||
*/
|
||||
|
||||
#define BOARD_SERCOM0_CLKGEN GCLK_CLKCTRL_GEN0
|
||||
#define BOARD_SERCOM0_MUX_SETTING (SPI_CTRLA_DOPO_DOPAD231 | SPI_CTRLA_DIPAD0)
|
||||
#define BOARD_SERCOM0_PINMUX_PAD0 PINMUX_PA04D_SERCOM0_PAD0 /* SPI_MISO */
|
||||
#define BOARD_SERCOM0_PINMUX_PAD1 0 /* microSD_SS */
|
||||
#define BOARD_SERCOM0_PINMUX_PAD2 PINMUX_PA06D_SERCOM0_PAD2 /* SPI_MOSI */
|
||||
#define BOARD_SERCOM0_PINMUX_PAD3 PINMUX_PA07D_SERCOM0_PAD3 /* SPI_SCK */
|
||||
|
||||
/* SERCOM1 SPI is available on EXT2
|
||||
*
|
||||
* PIN PORT SERCOM FUNCTION
|
||||
* --- ------------------ -----------
|
||||
* 15 PA17 SERCOM1 PAD1 SPI SS
|
||||
* 16 PA18 SERCOM1 PAD2 SPI MOSI
|
||||
* 17 PA16 SERCOM1 PAD0 SPI MISO
|
||||
* 18 PA19 SERCOM1 PAD3 SPI SCK
|
||||
*/
|
||||
|
||||
#define BOARD_SERCOM1_CLKGEN GCLK_CLKCTRL_GEN0
|
||||
#define BOARD_SERCOM1_MUX_SETTING (SPI_CTRLA_DOPO_DOPAD231 | SPI_CTRLA_DIPAD0)
|
||||
#define BOARD_SERCOM1_PINMUX_PAD0 PINMUX_PA16C_SERCOM1_PAD0 /* SPI_MISO */
|
||||
#define BOARD_SERCOM1_PINMUX_PAD1 0 /* microSD_SS */
|
||||
#define BOARD_SERCOM1_PINMUX_PAD2 PINMUX_PA18C_SERCOM1_PAD2 /* SPI_MOSI */
|
||||
#define BOARD_SERCOM1_PINMUX_PAD3 PINMUX_PA19C_SERCOM1_PAD3 /* SPI_SCK */
|
||||
|
||||
/* The SAMD20 Xplained Pro contains an Embedded Debugger (EDBG) that can be
|
||||
* used to program and debug the ATSAMD20J18A using Serial Wire Debug (SWD).
|
||||
* The Embedded debugger also include a Virtual COM port interface over
|
||||
* SERCOM3. Virtual COM port connections:
|
||||
*
|
||||
* PA24 SERCOM3 / USART TXD
|
||||
* PA25 SERCOM3 / USART RXD
|
||||
*/
|
||||
|
||||
#define BOARD_SERCOM3_GCLKGEN GCLK_CLKCTRL_GEN0
|
||||
#define BOARD_SERCOM3_MUXCONFIG (USART_CTRLA_RXPAD3 | USART_CTRLA_TXPAD2)
|
||||
#define BOARD_SERCOM3_PINMAP_PAD0 0
|
||||
#define BOARD_SERCOM3_PINMAP_PAD1 0
|
||||
#define BOARD_SERCOM3_PINMAP_PAD2 PORT_SERCOM3_PAD2_1 /* USART TX */
|
||||
#define BOARD_SERCOM3_PINMAP_PAD3 PORT_SERCOM3_PAD3_1 /* USART RX */
|
||||
|
||||
#define BOARD_SERCOM3_FREQUENCY BOARD_GCLK0_FREQUENCY
|
||||
|
||||
/* The SERCOM4 USART is available on connectors EXT1, EXT2, and EXT3
|
||||
*
|
||||
* PIN EXT1 EXT2 EXT3 GPIO Function
|
||||
* ---- ---- ---- ---- ------------------
|
||||
@ -374,43 +432,42 @@
|
||||
|
||||
#if defined(CONFIG_SAMD20_XPLAINED_USART4_EXT1)
|
||||
# define BOARD_SERCOM4_MUXCONFIG (USART_CTRLA_RXPAD1 | USART_CTRLA_TXPAD0)
|
||||
# define BOARD_SERCOM4_PINMAP_PAD0 PORT_SERCOM4_PAD0_3
|
||||
# define BOARD_SERCOM4_PINMAP_PAD1 PORT_SERCOM4_PAD1_3
|
||||
# define BOARD_SERCOM4_PINMAP_PAD0 PORT_SERCOM4_PAD0_3 /* USART TX */
|
||||
# define BOARD_SERCOM4_PINMAP_PAD1 PORT_SERCOM4_PAD1_3 /* USART RX */
|
||||
# define BOARD_SERCOM4_PINMAP_PAD2 0
|
||||
# define BOARD_SERCOM4_PINMAP_PAD3 0
|
||||
#elif defined(CONFIG_SAMD20_XPLAINED_USART4_EXT2)
|
||||
# define BOARD_SERCOM4_MUXCONFIG (USART_CTRLA_RXPAD1 | USART_CTRLA_TXPAD0)
|
||||
# define BOARD_SERCOM4_PINMAP_PAD0 PORT_SERCOM4_PAD0_1
|
||||
# define BOARD_SERCOM4_PINMAP_PAD1 PORT_SERCOM4_PAD1_1
|
||||
# define BOARD_SERCOM4_PINMAP_PAD0 PORT_SERCOM4_PAD0_1 /* USART TX */
|
||||
# define BOARD_SERCOM4_PINMAP_PAD1 PORT_SERCOM4_PAD1_1 /* USART RX */
|
||||
# define BOARD_SERCOM4_PINMAP_PAD2 0
|
||||
# define BOARD_SERCOM4_PINMAP_PAD3 0
|
||||
#else /* if defined(CONFIG_SAMD20_XPLAINED_USART4_EXT3) */
|
||||
# define BOARD_SERCOM4_MUXCONFIG (USART_CTRLA_RXPAD3 | USART_CTRLA_TXPAD2)
|
||||
# define BOARD_SERCOM4_PINMAP_PAD0 0
|
||||
# define BOARD_SERCOM4_PINMAP_PAD1 0
|
||||
# define BOARD_SERCOM4_PINMAP_PAD2 PORT_SERCOM4_PAD2_3
|
||||
# define BOARD_SERCOM4_PINMAP_PAD3 PORT_SERCOM4_PAD3_3
|
||||
# define BOARD_SERCOM4_PINMAP_PAD2 PORT_SERCOM4_PAD2_3 /* USART TX */
|
||||
# define BOARD_SERCOM4_PINMAP_PAD3 PORT_SERCOM4_PAD3_3 /* USART RX */
|
||||
#endif
|
||||
|
||||
#define BOARD_SERCOM4_FREQUENCY BOARD_GCLK0_FREQUENCY
|
||||
|
||||
/* The SAMD20 Xplained Pro contains an Embedded Debugger (EDBG) that can be
|
||||
* used to program and debug the ATSAMD20J18A using Serial Wire Debug (SWD).
|
||||
* The Embedded debugger also include a Virtual COM port interface over
|
||||
* SERCOM3. Virtual COM port connections:
|
||||
/* SERCOM5 SPI is available on EXT3
|
||||
*
|
||||
* PA24 SERCOM3 / USART TXD
|
||||
* PA25 SERCOM3 / USART RXD
|
||||
* PIN PORT SERCOM FUNCTION
|
||||
* --- ------------------ -----------
|
||||
* 15 PB17 SERCOM5 PAD1 SPI SS
|
||||
* 16 PB22 SERCOM5 PAD2 SPI MOSI
|
||||
* 17 PB16 SERCOM5 PAD0 SPI MISO
|
||||
* 18 PB23 SERCOM5 PAD3 SPI SCK
|
||||
*/
|
||||
|
||||
#define BOARD_SERCOM3_GCLKGEN GCLK_CLKCTRL_GEN0
|
||||
#define BOARD_SERCOM3_MUXCONFIG (USART_CTRLA_RXPAD3 | USART_CTRLA_TXPAD2)
|
||||
#define BOARD_SERCOM3_PINMAP_PAD0 0
|
||||
#define BOARD_SERCOM3_PINMAP_PAD1 0
|
||||
#define BOARD_SERCOM3_PINMAP_PAD2 PORT_SERCOM3_PAD2_1
|
||||
#define BOARD_SERCOM3_PINMAP_PAD3 PORT_SERCOM3_PAD3_1
|
||||
|
||||
#define BOARD_SERCOM3_FREQUENCY BOARD_GCLK0_FREQUENCY
|
||||
#define BOARD_SERCOM5_CLKGEN GCLK_CLKCTRL_GEN0
|
||||
#define BOARD_SERCOM5_MUX_SETTING (SPI_CTRLA_DOPO_DOPAD231 | SPI_CTRLA_DIPAD0)
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#define BOARD_SERCOM5_PINMUX_PAD0 PINMUX_PB16C_SERCOM5_PAD0 /* SPI_MISO */
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#define BOARD_SERCOM5_PINMUX_PAD1 0 /* microSD_SS */
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#define BOARD_SERCOM5_PINMUX_PAD2 PINMUX_PB22D_SERCOM5_PAD2 /* SPI_MOSI */
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#define BOARD_SERCOM5_PINMUX_PAD3 PINMUX_PB23D_SERCOM5_PAD3 /* SPI_SCK */
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|
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/* LED definitions ******************************************************************/
|
||||
/* There are three LEDs on board the SAMD20 Xplained Pro board: The EDBG
|
||||
|
||||
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Reference in New Issue
Block a user