Cosmetic changes from review of last PR
This commit is contained in:
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22faa90d73
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8bcb5f0251
@ -167,21 +167,21 @@
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struct stm32l4_qspidev_s
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struct stm32l4_qspidev_s
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{
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{
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struct qspi_dev_s qspi; /* Externally visible part of the QSPI interface */
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struct qspi_dev_s qspi; /* Externally visible part of the QSPI interface */
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uint32_t base; /* QSPI controller register base address */
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uint32_t base; /* QSPI controller register base address */
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uint32_t frequency; /* Requested clock frequency */
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uint32_t frequency; /* Requested clock frequency */
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uint32_t actual; /* Actual clock frequency */
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uint32_t actual; /* Actual clock frequency */
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uint8_t mode; /* Mode 0,3 */
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uint8_t mode; /* Mode 0,3 */
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uint8_t nbits; /* Width of word in bits (8 to 32) */
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uint8_t nbits; /* Width of word in bits (8 to 32) */
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uint8_t intf; /* QSPI controller number (0) */
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uint8_t intf; /* QSPI controller number (0) */
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bool initialized; /* TRUE: Controller has been initialized */
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bool initialized; /* TRUE: Controller has been initialized */
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sem_t exclsem; /* Assures mutually exclusive access to QSPI */
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sem_t exclsem; /* Assures mutually exclusive access to QSPI */
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#ifdef QSPI_USE_INTERRUPTS
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#ifdef QSPI_USE_INTERRUPTS
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xcpt_t handler; /* Interrupt handler */
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xcpt_t handler; /* Interrupt handler */
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uint8_t irq; /* Interrupt number */
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uint8_t irq; /* Interrupt number */
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sem_t op_sem; /* Block until complete */
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sem_t op_sem; /* Block until complete */
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struct qspi_xctnspec_s* xctn; /* context of transaction in progress*/
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struct qspi_xctnspec_s *xctn; /* context of transaction in progress*/
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#endif
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#endif
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#ifdef CONFIG_STM32L4_QSPI_DMA
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#ifdef CONFIG_STM32L4_QSPI_DMA
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@ -786,7 +786,9 @@ static int qspi_setupxctnfrommem(struct qspi_xctnspec_s *xctn,
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xctn->buffer = meminfo->buffer;
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xctn->buffer = meminfo->buffer;
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/* XXX III there should be a separate flags for single/dual/quad for each of i,a,d */
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/* XXX III there should be a separate flags for single/dual/quad for each
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* of i,a,d
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*/
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if (QSPIMEM_ISDUALIO(meminfo->flags))
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if (QSPIMEM_ISDUALIO(meminfo->flags))
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{
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{
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@ -864,6 +866,7 @@ static void qspi_waitstatusflags(struct stm32l4_qspidev_s *priv,
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static void qspi_abort(struct stm32l4_qspidev_s *priv)
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static void qspi_abort(struct stm32l4_qspidev_s *priv)
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{
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{
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uint32_t regval;
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uint32_t regval;
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regval = qspi_getreg(priv, STM32L4_QUADSPI_CR_OFFSET);
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regval = qspi_getreg(priv, STM32L4_QUADSPI_CR_OFFSET);
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regval |= QSPI_CR_ABORT;
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regval |= QSPI_CR_ABORT;
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qspi_putreg(priv, regval, STM32L4_QUADSPI_CR_OFFSET);
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qspi_putreg(priv, regval, STM32L4_QUADSPI_CR_OFFSET);
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@ -951,17 +954,17 @@ static int qspi0_interrupt(int irq, void *context)
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uint32_t cr;
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uint32_t cr;
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uint32_t regval;
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uint32_t regval;
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/* let's find out what is going on */
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/* Let's find out what is going on */
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status = qspi_getreg(&g_qspi0dev, STM32L4_QUADSPI_SR_OFFSET);
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status = qspi_getreg(&g_qspi0dev, STM32L4_QUADSPI_SR_OFFSET);
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cr = qspi_getreg(&g_qspi0dev, STM32L4_QUADSPI_CR_OFFSET);
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cr = qspi_getreg(&g_qspi0dev, STM32L4_QUADSPI_CR_OFFSET);
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/* is it 'FIFO Threshold'? */
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/* Is it 'FIFO Threshold'? */
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if((status & QSPI_SR_FTF) && (cr & QSPI_CR_FTIE))
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if ((status & QSPI_SR_FTF) && (cr & QSPI_CR_FTIE))
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{
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{
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volatile uint32_t *datareg = (volatile uint32_t*)(g_qspi0dev.base + STM32L4_QUADSPI_DR_OFFSET);
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volatile uint32_t *datareg = (volatile uint32_t*)(g_qspi0dev.base + STM32L4_QUADSPI_DR_OFFSET);
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if(g_qspi0dev.xctn->function == CCR_FMODE_INDWR)
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if (g_qspi0dev.xctn->function == CCR_FMODE_INDWR)
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{
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{
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/* Write data until we have no more or have no place to put it */
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/* Write data until we have no more or have no place to put it */
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@ -974,13 +977,13 @@ static int qspi0_interrupt(int irq, void *context)
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}
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}
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else
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else
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{
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{
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/* fresh out of data to write */
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/* Fresh out of data to write */
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break;
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break;
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}
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}
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}
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}
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}
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}
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else if(g_qspi0dev.xctn->function == CCR_FMODE_INDRD)
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else if (g_qspi0dev.xctn->function == CCR_FMODE_INDRD)
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{
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{
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/* Read data until we have no more or have no place to put it */
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/* Read data until we have no more or have no place to put it */
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@ -1001,11 +1004,11 @@ static int qspi0_interrupt(int irq, void *context)
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}
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}
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}
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}
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/* is it 'Transfer Complete'? */
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/* Is it 'Transfer Complete'? */
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if((status & QSPI_SR_TCF) && (cr & QSPI_CR_TCIE))
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if ((status & QSPI_SR_TCF) && (cr & QSPI_CR_TCIE))
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{
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{
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/* acknowledge interrupt */
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/* Acknowledge interrupt */
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qspi_putreg(&g_qspi0dev, QSPI_FCR_CTCF, STM32L4_QUADSPI_FCR);
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qspi_putreg(&g_qspi0dev, QSPI_FCR_CTCF, STM32L4_QUADSPI_FCR);
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@ -1015,9 +1018,9 @@ static int qspi0_interrupt(int irq, void *context)
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regval &= ~(QSPI_CR_TEIE | QSPI_CR_TCIE | QSPI_CR_FTIE);
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regval &= ~(QSPI_CR_TEIE | QSPI_CR_TCIE | QSPI_CR_FTIE);
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qspi_putreg(&g_qspi0dev, regval, STM32L4_QUADSPI_CR_OFFSET);
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qspi_putreg(&g_qspi0dev, regval, STM32L4_QUADSPI_CR_OFFSET);
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/* do the last bit of read if needed */
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/* Do the last bit of read if needed */
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if(g_qspi0dev.xctn->function == CCR_FMODE_INDRD)
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if (g_qspi0dev.xctn->function == CCR_FMODE_INDRD)
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{
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{
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volatile uint32_t *datareg = (volatile uint32_t*)(g_qspi0dev.base + STM32L4_QUADSPI_DR_OFFSET);
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volatile uint32_t *datareg = (volatile uint32_t*)(g_qspi0dev.base + STM32L4_QUADSPI_DR_OFFSET);
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@ -1032,36 +1035,37 @@ static int qspi0_interrupt(int irq, void *context)
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}
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}
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else
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else
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{
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{
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/* no room at the inn */
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/* No room at the inn */
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break;
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break;
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}
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}
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}
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}
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}
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}
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/* use 'abort' to ditch any stray fifo contents and clear BUSY flag */
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/* Use 'abort' to ditch any stray fifo contents and clear BUSY flag */
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qspi_abort(&g_qspi0dev);
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qspi_abort(&g_qspi0dev);
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/* set success status */
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/* Set success status */
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g_qspi0dev.xctn->disposition = OK;
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g_qspi0dev.xctn->disposition = OK;
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/* signal complete */
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/* Signal complete */
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sem_post(&g_qspi0dev.op_sem);
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sem_post(&g_qspi0dev.op_sem);
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}
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}
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/* is it 'Status Match'? */
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/* Is it 'Status Match'? */
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if((status & QSPI_SR_SMF) && (cr & QSPI_CR_SMIE))
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if ((status & QSPI_SR_SMF) && (cr & QSPI_CR_SMIE))
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{
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{
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/* acknowledge interrupt */
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/* Acknowledge interrupt */
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qspi_putreg(&g_qspi0dev, QSPI_FCR_CSMF, STM32L4_QUADSPI_FCR);
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qspi_putreg(&g_qspi0dev, QSPI_FCR_CSMF, STM32L4_QUADSPI_FCR);
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/* If 'automatic poll mode stop' is activated, we're done */
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/* If 'automatic poll mode stop' is activated, we're done */
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if(cr & QSPI_CR_APMS)
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if (cr & QSPI_CR_APMS)
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{
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{
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/* Disable the QSPI Transfer Error and Status Match Interrupts */
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/* Disable the QSPI Transfer Error and Status Match Interrupts */
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@ -1069,25 +1073,25 @@ static int qspi0_interrupt(int irq, void *context)
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regval &= ~(QSPI_CR_TEIE | QSPI_CR_SMIE);
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regval &= ~(QSPI_CR_TEIE | QSPI_CR_SMIE);
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qspi_putreg(&g_qspi0dev, regval, STM32L4_QUADSPI_CR_OFFSET);
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qspi_putreg(&g_qspi0dev, regval, STM32L4_QUADSPI_CR_OFFSET);
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/* set success status */
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/* Set success status */
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g_qspi0dev.xctn->disposition = OK;
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g_qspi0dev.xctn->disposition = OK;
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/* signal complete */
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/* Signal complete */
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sem_post(&g_qspi0dev.op_sem);
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sem_post(&g_qspi0dev.op_sem);
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}
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}
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else
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else
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{
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{
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/* XXX if it's NOT auto stop; something needs to happen here; a callback?*/
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/* XXX if it's NOT auto stop; something needs to happen here; a callback? */
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}
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}
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}
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}
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/* is it' Transfer Error'? :( */
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/* Is it' Transfer Error'? :( */
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if((status & QSPI_SR_TEF) && (cr & QSPI_CR_TEIE))
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if ((status & QSPI_SR_TEF) && (cr & QSPI_CR_TEIE))
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{
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{
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/* acknowledge interrupt */
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/* Acknowledge interrupt */
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qspi_putreg(&g_qspi0dev, QSPI_FCR_CTEF, STM32L4_QUADSPI_FCR);
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qspi_putreg(&g_qspi0dev, QSPI_FCR_CTEF, STM32L4_QUADSPI_FCR);
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@ -1097,28 +1101,28 @@ static int qspi0_interrupt(int irq, void *context)
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regval &= ~(QSPI_CR_TEIE | QSPI_CR_TCIE | QSPI_CR_FTIE | QSPI_CR_SMIE | QSPI_CR_TOIE);
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regval &= ~(QSPI_CR_TEIE | QSPI_CR_TCIE | QSPI_CR_FTIE | QSPI_CR_SMIE | QSPI_CR_TOIE);
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qspi_putreg(&g_qspi0dev, regval, STM32L4_QUADSPI_CR_OFFSET);
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qspi_putreg(&g_qspi0dev, regval, STM32L4_QUADSPI_CR_OFFSET);
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/* set error status */
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/* Set error status */
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g_qspi0dev.xctn->disposition = - EIO;
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g_qspi0dev.xctn->disposition = - EIO;
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/* signal complete */
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/* Signal complete */
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sem_post(&g_qspi0dev.op_sem);
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sem_post(&g_qspi0dev.op_sem);
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}
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}
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/* is it 'Timeout'? (: */
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/* Is it 'Timeout'? (: */
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if((status & QSPI_SR_TOF) && (cr & QSPI_CR_TOIE))
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if ((status & QSPI_SR_TOF) && (cr & QSPI_CR_TOIE))
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{
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{
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/* acknowledge interrupt */
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/* Acknowledge interrupt */
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qspi_putreg(&g_qspi0dev, QSPI_FCR_CTOF, STM32L4_QUADSPI_FCR);
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qspi_putreg(&g_qspi0dev, QSPI_FCR_CTOF, STM32L4_QUADSPI_FCR);
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/* set error status */
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/* Set error status */
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g_qspi0dev.xctn->disposition = - ETIMEDOUT;
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g_qspi0dev.xctn->disposition = - ETIMEDOUT;
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/* signal complete */
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/* Signal complete */
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sem_post(&g_qspi0dev.op_sem);
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sem_post(&g_qspi0dev.op_sem);
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}
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}
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@ -1531,7 +1535,8 @@ static int qspi_command(struct qspi_dev_s *dev,
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/* Clear flags */
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/* Clear flags */
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qspi_putreg(priv, QSPI_FCR_CTEF | QSPI_FCR_CTCF | QSPI_FCR_CSMF | QSPI_FCR_CTOF,
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qspi_putreg(priv,
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QSPI_FCR_CTEF | QSPI_FCR_CTCF | QSPI_FCR_CSMF | QSPI_FCR_CTOF,
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STM32L4_QUADSPI_FCR);
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STM32L4_QUADSPI_FCR);
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#ifdef QSPI_USE_INTERRUPTS
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#ifdef QSPI_USE_INTERRUPTS
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@ -1548,11 +1553,15 @@ static int qspi_command(struct qspi_dev_s *dev,
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{
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{
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uint32_t regval;
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uint32_t regval;
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/* Set up the Communications Configuration Register as per command info */
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/* Set up the Communications Configuration Register as per command
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* info
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*/
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qspi_ccrconfig(priv, &xctn, CCR_FMODE_INDWR);
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qspi_ccrconfig(priv, &xctn, CCR_FMODE_INDWR);
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/* Enable 'Transfer Error' 'FIFO Threshhold' and 'Transfer Complete' interrupts */
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/* Enable 'Transfer Error' 'FIFO Threshhold' and 'Transfer Complete'
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* interrupts.
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*/
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regval = qspi_getreg(priv, STM32L4_QUADSPI_CR_OFFSET);
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regval = qspi_getreg(priv, STM32L4_QUADSPI_CR_OFFSET);
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regval |= (QSPI_CR_TEIE | QSPI_CR_FTIE | QSPI_CR_TCIE);
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regval |= (QSPI_CR_TEIE | QSPI_CR_FTIE | QSPI_CR_TCIE);
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@ -1565,7 +1574,9 @@ static int qspi_command(struct qspi_dev_s *dev,
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addrval = qspi_getreg(priv, STM32L4_QUADSPI_AR_OFFSET);
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addrval = qspi_getreg(priv, STM32L4_QUADSPI_AR_OFFSET);
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/* Set up the Communications Configuration Register as per command info */
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/* Set up the Communications Configuration Register as per command
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* info
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*/
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qspi_ccrconfig(priv, &xctn, CCR_FMODE_INDRD);
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qspi_ccrconfig(priv, &xctn, CCR_FMODE_INDRD);
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@ -1573,7 +1584,9 @@ static int qspi_command(struct qspi_dev_s *dev,
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qspi_putreg(priv, addrval, STM32L4_QUADSPI_AR_OFFSET);
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qspi_putreg(priv, addrval, STM32L4_QUADSPI_AR_OFFSET);
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/* Enable 'Transfer Error' 'FIFO Threshhold' and 'Transfer Complete' interrupts */
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/* Enable 'Transfer Error' 'FIFO Threshhold' and 'Transfer Complete'
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* interrupts
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*/
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regval = qspi_getreg(priv, STM32L4_QUADSPI_CR_OFFSET);
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regval = qspi_getreg(priv, STM32L4_QUADSPI_CR_OFFSET);
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regval |= (QSPI_CR_TEIE | QSPI_CR_FTIE | QSPI_CR_TCIE);
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regval |= (QSPI_CR_TEIE | QSPI_CR_FTIE | QSPI_CR_TCIE);
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@ -1584,7 +1597,9 @@ static int qspi_command(struct qspi_dev_s *dev,
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{
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{
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uint32_t regval;
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uint32_t regval;
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/* We have no data phase, the command will execute as soon as we emit the CCR */
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/* We have no data phase, the command will execute as soon as we emit
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* the CCR
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*/
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/* Enable 'Transfer Error' and 'Transfer Complete' interrupts */
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/* Enable 'Transfer Error' and 'Transfer Complete' interrupts */
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@ -1592,7 +1607,9 @@ static int qspi_command(struct qspi_dev_s *dev,
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regval |= (QSPI_CR_TEIE | QSPI_CR_TCIE);
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regval |= (QSPI_CR_TEIE | QSPI_CR_TCIE);
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qspi_putreg(priv, regval, STM32L4_QUADSPI_CR_OFFSET);
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qspi_putreg(priv, regval, STM32L4_QUADSPI_CR_OFFSET);
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/* Set up the Communications Configuration Register as per command info */
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/* Set up the Communications Configuration Register as per command
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* info
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*/
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qspi_ccrconfig(priv, &xctn, CCR_FMODE_INDRD);
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qspi_ccrconfig(priv, &xctn, CCR_FMODE_INDRD);
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}
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}
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@ -1602,7 +1619,7 @@ static int qspi_command(struct qspi_dev_s *dev,
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sem_wait(&priv->op_sem);
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sem_wait(&priv->op_sem);
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MEMORY_SYNC();
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MEMORY_SYNC();
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/* convey the result */
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/* Convey the result */
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ret = xctn.disposition;
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ret = xctn.disposition;
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@ -1610,7 +1627,7 @@ static int qspi_command(struct qspi_dev_s *dev,
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/* XXX III dma mode (and 'autopolling'?) */
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/* XXX III dma mode (and 'autopolling'?) */
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#else
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#else
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/* polling mode */
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/* Polling mode */
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/* Set up the Communications Configuration Register as per command info */
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/* Set up the Communications Configuration Register as per command info */
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@ -1689,7 +1706,8 @@ static int qspi_memory(struct qspi_dev_s *dev,
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/* Clear flags */
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/* Clear flags */
|
||||||
|
|
||||||
qspi_putreg(priv, QSPI_FCR_CTEF | QSPI_FCR_CTCF | QSPI_FCR_CSMF | QSPI_FCR_CTOF,
|
qspi_putreg(priv,
|
||||||
|
QSPI_FCR_CTEF | QSPI_FCR_CTCF | QSPI_FCR_CSMF | QSPI_FCR_CTOF,
|
||||||
STM32L4_QUADSPI_FCR);
|
STM32L4_QUADSPI_FCR);
|
||||||
|
|
||||||
#ifdef QSPI_USE_INTERRUPTS
|
#ifdef QSPI_USE_INTERRUPTS
|
||||||
@ -1704,11 +1722,15 @@ static int qspi_memory(struct qspi_dev_s *dev,
|
|||||||
{
|
{
|
||||||
uint32_t regval;
|
uint32_t regval;
|
||||||
|
|
||||||
/* Set up the Communications Configuration Register as per command info */
|
/* Set up the Communications Configuration Register as per command
|
||||||
|
* info
|
||||||
|
*/
|
||||||
|
|
||||||
qspi_ccrconfig(priv, &xctn, CCR_FMODE_INDWR);
|
qspi_ccrconfig(priv, &xctn, CCR_FMODE_INDWR);
|
||||||
|
|
||||||
/* Enable 'Transfer Error' 'FIFO Threshhold' and 'Transfer Complete' interrupts */
|
/* Enable 'Transfer Error' 'FIFO Threshhold' and 'Transfer Complete'
|
||||||
|
* interrupts
|
||||||
|
*/
|
||||||
|
|
||||||
regval = qspi_getreg(priv, STM32L4_QUADSPI_CR_OFFSET);
|
regval = qspi_getreg(priv, STM32L4_QUADSPI_CR_OFFSET);
|
||||||
regval |= (QSPI_CR_TEIE | QSPI_CR_FTIE | QSPI_CR_TCIE);
|
regval |= (QSPI_CR_TEIE | QSPI_CR_FTIE | QSPI_CR_TCIE);
|
||||||
@ -1721,7 +1743,9 @@ static int qspi_memory(struct qspi_dev_s *dev,
|
|||||||
|
|
||||||
addrval = qspi_getreg(priv, STM32L4_QUADSPI_AR_OFFSET);
|
addrval = qspi_getreg(priv, STM32L4_QUADSPI_AR_OFFSET);
|
||||||
|
|
||||||
/* Set up the Communications Configuration Register as per command info */
|
/* Set up the Communications Configuration Register as per command
|
||||||
|
* info
|
||||||
|
*/
|
||||||
|
|
||||||
qspi_ccrconfig(priv, &xctn, CCR_FMODE_INDRD);
|
qspi_ccrconfig(priv, &xctn, CCR_FMODE_INDRD);
|
||||||
|
|
||||||
@ -1729,7 +1753,9 @@ static int qspi_memory(struct qspi_dev_s *dev,
|
|||||||
|
|
||||||
qspi_putreg(priv, addrval, STM32L4_QUADSPI_AR_OFFSET);
|
qspi_putreg(priv, addrval, STM32L4_QUADSPI_AR_OFFSET);
|
||||||
|
|
||||||
/* Enable 'Transfer Error' 'FIFO Threshhold' and 'Transfer Complete' interrupts */
|
/* Enable 'Transfer Error' 'FIFO Threshhold' and 'Transfer Complete'
|
||||||
|
* interrupts
|
||||||
|
*/
|
||||||
|
|
||||||
regval = qspi_getreg(priv, STM32L4_QUADSPI_CR_OFFSET);
|
regval = qspi_getreg(priv, STM32L4_QUADSPI_CR_OFFSET);
|
||||||
regval |= (QSPI_CR_TEIE | QSPI_CR_FTIE | QSPI_CR_TCIE);
|
regval |= (QSPI_CR_TEIE | QSPI_CR_FTIE | QSPI_CR_TCIE);
|
||||||
@ -1769,6 +1795,7 @@ static int qspi_memory(struct qspi_dev_s *dev,
|
|||||||
{
|
{
|
||||||
ret = qspi_receive_blocking(priv, &xctn);
|
ret = qspi_receive_blocking(priv, &xctn);
|
||||||
}
|
}
|
||||||
|
|
||||||
MEMORY_SYNC();
|
MEMORY_SYNC();
|
||||||
|
|
||||||
#if 0
|
#if 0
|
||||||
@ -2035,7 +2062,7 @@ struct qspi_dev_s *stm32l4_qspi_initialize(int intf)
|
|||||||
|
|
||||||
/* Initialize the semaphore that blocks until the operation completes */
|
/* Initialize the semaphore that blocks until the operation completes */
|
||||||
|
|
||||||
sem_init(&priv->op_sem, 0, 0);
|
sem_init(&priv->op_sem, 0, 0);
|
||||||
|
|
||||||
#endif
|
#endif
|
||||||
|
|
||||||
|
Loading…
Reference in New Issue
Block a user